1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_FLASHCTRL_A_REGISTERS_H__ 27 #define __SI32_FLASHCTRL_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_FLASHCTRL_A_CONFIG_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Flash Speed Mode 42 volatile uint32_t SPMD: 2; 43 uint32_t reserved0: 2; 44 // Read Store Mode Enable 45 volatile uint32_t RDSEN: 1; 46 uint32_t reserved1: 1; 47 // Data Prefetch Enable 48 volatile uint32_t DPFEN: 1; 49 // Prefetch Inhibit 50 volatile uint32_t PFINH: 1; 51 uint32_t reserved2: 8; 52 // Flash Write Sequence Enable 53 volatile uint32_t SQWEN: 1; 54 uint32_t reserved3: 1; 55 // Flash Page Erase Enable 56 volatile uint32_t ERASEEN: 1; 57 // Flash Buffer Status 58 volatile uint32_t BUFSTS: 1; 59 // Flash Operation Busy Flag 60 volatile uint32_t BUSYF: 1; 61 uint32_t reserved4: 11; 62 }; 63 volatile uint32_t U32; 64 }; 65 }; 66 67 #define SI32_FLASHCTRL_A_CONFIG_SPMD_MASK 0x00000003 68 #define SI32_FLASHCTRL_A_CONFIG_SPMD_SHIFT 0 69 // Read and write the flash at speed mode 0. 70 #define SI32_FLASHCTRL_A_CONFIG_SPMD_MODE0_VALUE 0 71 #define SI32_FLASHCTRL_A_CONFIG_SPMD_MODE0_U32 \ 72 (SI32_FLASHCTRL_A_CONFIG_SPMD_MODE0_VALUE << SI32_FLASHCTRL_A_CONFIG_SPMD_SHIFT) 73 // Read and write the flash at speed mode 1. 74 #define SI32_FLASHCTRL_A_CONFIG_SPMD_MODE1_VALUE 1 75 #define SI32_FLASHCTRL_A_CONFIG_SPMD_MODE1_U32 \ 76 (SI32_FLASHCTRL_A_CONFIG_SPMD_MODE1_VALUE << SI32_FLASHCTRL_A_CONFIG_SPMD_SHIFT) 77 // Read and write the flash at speed mode 2. 78 #define SI32_FLASHCTRL_A_CONFIG_SPMD_MODE2_VALUE 2 79 #define SI32_FLASHCTRL_A_CONFIG_SPMD_MODE2_U32 \ 80 (SI32_FLASHCTRL_A_CONFIG_SPMD_MODE2_VALUE << SI32_FLASHCTRL_A_CONFIG_SPMD_SHIFT) 81 // Read and write the flash at speed mode 3. 82 #define SI32_FLASHCTRL_A_CONFIG_SPMD_MODE3_VALUE 3 83 #define SI32_FLASHCTRL_A_CONFIG_SPMD_MODE3_U32 \ 84 (SI32_FLASHCTRL_A_CONFIG_SPMD_MODE3_VALUE << SI32_FLASHCTRL_A_CONFIG_SPMD_SHIFT) 85 86 #define SI32_FLASHCTRL_A_CONFIG_RDSEN_MASK 0x00000010 87 #define SI32_FLASHCTRL_A_CONFIG_RDSEN_SHIFT 4 88 // Disable read store mode. 89 #define SI32_FLASHCTRL_A_CONFIG_RDSEN_DISABLED_VALUE 0 90 #define SI32_FLASHCTRL_A_CONFIG_RDSEN_DISABLED_U32 \ 91 (SI32_FLASHCTRL_A_CONFIG_RDSEN_DISABLED_VALUE << SI32_FLASHCTRL_A_CONFIG_RDSEN_SHIFT) 92 // Enable read store mode. 93 #define SI32_FLASHCTRL_A_CONFIG_RDSEN_ENABLED_VALUE 1 94 #define SI32_FLASHCTRL_A_CONFIG_RDSEN_ENABLED_U32 \ 95 (SI32_FLASHCTRL_A_CONFIG_RDSEN_ENABLED_VALUE << SI32_FLASHCTRL_A_CONFIG_RDSEN_SHIFT) 96 97 #define SI32_FLASHCTRL_A_CONFIG_DPFEN_MASK 0x00000040 98 #define SI32_FLASHCTRL_A_CONFIG_DPFEN_SHIFT 6 99 // Data accesses are excluded from the prefetch buffer. 100 #define SI32_FLASHCTRL_A_CONFIG_DPFEN_DISABLED_VALUE 0 101 #define SI32_FLASHCTRL_A_CONFIG_DPFEN_DISABLED_U32 \ 102 (SI32_FLASHCTRL_A_CONFIG_DPFEN_DISABLED_VALUE << SI32_FLASHCTRL_A_CONFIG_DPFEN_SHIFT) 103 // Data accesses are included in the prefetch buffer. 104 #define SI32_FLASHCTRL_A_CONFIG_DPFEN_ENABLED_VALUE 1 105 #define SI32_FLASHCTRL_A_CONFIG_DPFEN_ENABLED_U32 \ 106 (SI32_FLASHCTRL_A_CONFIG_DPFEN_ENABLED_VALUE << SI32_FLASHCTRL_A_CONFIG_DPFEN_SHIFT) 107 108 #define SI32_FLASHCTRL_A_CONFIG_PFINH_MASK 0x00000080 109 #define SI32_FLASHCTRL_A_CONFIG_PFINH_SHIFT 7 110 // Any reads from flash are prefetched until the prefetch buffer is full. 111 #define SI32_FLASHCTRL_A_CONFIG_PFINH_INACTIVE_VALUE 0 112 #define SI32_FLASHCTRL_A_CONFIG_PFINH_INACTIVE_U32 \ 113 (SI32_FLASHCTRL_A_CONFIG_PFINH_INACTIVE_VALUE << SI32_FLASHCTRL_A_CONFIG_PFINH_SHIFT) 114 // Inhibit the prefetch engine. 115 #define SI32_FLASHCTRL_A_CONFIG_PFINH_ACTIVE_VALUE 1 116 #define SI32_FLASHCTRL_A_CONFIG_PFINH_ACTIVE_U32 \ 117 (SI32_FLASHCTRL_A_CONFIG_PFINH_ACTIVE_VALUE << SI32_FLASHCTRL_A_CONFIG_PFINH_SHIFT) 118 119 #define SI32_FLASHCTRL_A_CONFIG_SQWEN_MASK 0x00010000 120 #define SI32_FLASHCTRL_A_CONFIG_SQWEN_SHIFT 16 121 // Disable sequential write mode. 122 #define SI32_FLASHCTRL_A_CONFIG_SQWEN_DISABLED_VALUE 0 123 #define SI32_FLASHCTRL_A_CONFIG_SQWEN_DISABLED_U32 \ 124 (SI32_FLASHCTRL_A_CONFIG_SQWEN_DISABLED_VALUE << SI32_FLASHCTRL_A_CONFIG_SQWEN_SHIFT) 125 // Enable sequential write mode. 126 #define SI32_FLASHCTRL_A_CONFIG_SQWEN_ENABLED_VALUE 1 127 #define SI32_FLASHCTRL_A_CONFIG_SQWEN_ENABLED_U32 \ 128 (SI32_FLASHCTRL_A_CONFIG_SQWEN_ENABLED_VALUE << SI32_FLASHCTRL_A_CONFIG_SQWEN_SHIFT) 129 130 #define SI32_FLASHCTRL_A_CONFIG_ERASEEN_MASK 0x00040000 131 #define SI32_FLASHCTRL_A_CONFIG_ERASEEN_SHIFT 18 132 // Writes to the WRDATA field will initiate a write to flash at the address in the 133 // WRADDR field. 134 #define SI32_FLASHCTRL_A_CONFIG_ERASEEN_DISABLED_VALUE 0 135 #define SI32_FLASHCTRL_A_CONFIG_ERASEEN_DISABLED_U32 \ 136 (SI32_FLASHCTRL_A_CONFIG_ERASEEN_DISABLED_VALUE << SI32_FLASHCTRL_A_CONFIG_ERASEEN_SHIFT) 137 // Writes to the WRDATA field will initiate an erase of the flash page containing 138 // the address in the WRADDR field. 139 #define SI32_FLASHCTRL_A_CONFIG_ERASEEN_ENABLED_VALUE 1 140 #define SI32_FLASHCTRL_A_CONFIG_ERASEEN_ENABLED_U32 \ 141 (SI32_FLASHCTRL_A_CONFIG_ERASEEN_ENABLED_VALUE << SI32_FLASHCTRL_A_CONFIG_ERASEEN_SHIFT) 142 143 #define SI32_FLASHCTRL_A_CONFIG_BUFSTS_MASK 0x00080000 144 #define SI32_FLASHCTRL_A_CONFIG_BUFSTS_SHIFT 19 145 // The flash controller write data buffer is empty. 146 #define SI32_FLASHCTRL_A_CONFIG_BUFSTS_EMPTY_VALUE 0 147 #define SI32_FLASHCTRL_A_CONFIG_BUFSTS_EMPTY_U32 \ 148 (SI32_FLASHCTRL_A_CONFIG_BUFSTS_EMPTY_VALUE << SI32_FLASHCTRL_A_CONFIG_BUFSTS_SHIFT) 149 // The flash controller write data buffer is full. 150 #define SI32_FLASHCTRL_A_CONFIG_BUFSTS_FULL_VALUE 1 151 #define SI32_FLASHCTRL_A_CONFIG_BUFSTS_FULL_U32 \ 152 (SI32_FLASHCTRL_A_CONFIG_BUFSTS_FULL_VALUE << SI32_FLASHCTRL_A_CONFIG_BUFSTS_SHIFT) 153 154 #define SI32_FLASHCTRL_A_CONFIG_BUSYF_MASK 0x00100000 155 #define SI32_FLASHCTRL_A_CONFIG_BUSYF_SHIFT 20 156 // The flash interface is not busy. 157 #define SI32_FLASHCTRL_A_CONFIG_BUSYF_NOT_SET_VALUE 0 158 #define SI32_FLASHCTRL_A_CONFIG_BUSYF_NOT_SET_U32 \ 159 (SI32_FLASHCTRL_A_CONFIG_BUSYF_NOT_SET_VALUE << SI32_FLASHCTRL_A_CONFIG_BUSYF_SHIFT) 160 // The flash interface is busy with an operation. 161 #define SI32_FLASHCTRL_A_CONFIG_BUSYF_SET_VALUE 1 162 #define SI32_FLASHCTRL_A_CONFIG_BUSYF_SET_U32 \ 163 (SI32_FLASHCTRL_A_CONFIG_BUSYF_SET_VALUE << SI32_FLASHCTRL_A_CONFIG_BUSYF_SHIFT) 164 165 166 167 struct SI32_FLASHCTRL_A_WRADDR_Struct 168 { 169 union 170 { 171 struct 172 { 173 // Flash Write Address 174 volatile uint32_t WRADDR_BITS; 175 }; 176 volatile uint32_t U32; 177 }; 178 }; 179 180 #define SI32_FLASHCTRL_A_WRADDR_WRADDR_MASK 0xFFFFFFFF 181 #define SI32_FLASHCTRL_A_WRADDR_WRADDR_SHIFT 0 182 183 184 185 struct SI32_FLASHCTRL_A_WRDATA_Struct 186 { 187 union 188 { 189 struct 190 { 191 // Flash Write Data 192 volatile uint32_t WRDATA_BITS; 193 }; 194 volatile uint32_t U32; 195 }; 196 }; 197 198 #define SI32_FLASHCTRL_A_WRDATA_WRDATA_MASK 0xFFFFFFFF 199 #define SI32_FLASHCTRL_A_WRDATA_WRDATA_SHIFT 0 200 201 202 203 struct SI32_FLASHCTRL_A_KEY_Struct 204 { 205 union 206 { 207 struct 208 { 209 // Flash Key 210 volatile uint8_t KEY_BITS; 211 uint32_t reserved0: 24; 212 }; 213 volatile uint32_t U32; 214 }; 215 }; 216 217 #define SI32_FLASHCTRL_A_KEY_KEY_MASK 0x000000FF 218 #define SI32_FLASHCTRL_A_KEY_KEY_SHIFT 0 219 #define SI32_FLASHCTRL_A_KEY_KEY_MULTI_LOCK_VALUE 90 220 #define SI32_FLASHCTRL_A_KEY_KEY_MULTI_LOCK_U32 \ 221 (SI32_FLASHCTRL_A_KEY_KEY_MULTI_LOCK_VALUE << SI32_FLASHCTRL_A_KEY_KEY_SHIFT) 222 #define SI32_FLASHCTRL_A_KEY_KEY_INITIAL_UNLOCK_VALUE 165 223 #define SI32_FLASHCTRL_A_KEY_KEY_INITIAL_UNLOCK_U32 \ 224 (SI32_FLASHCTRL_A_KEY_KEY_INITIAL_UNLOCK_VALUE << SI32_FLASHCTRL_A_KEY_KEY_SHIFT) 225 #define SI32_FLASHCTRL_A_KEY_KEY_SINGLE_UNLOCK_VALUE 241 226 #define SI32_FLASHCTRL_A_KEY_KEY_SINGLE_UNLOCK_U32 \ 227 (SI32_FLASHCTRL_A_KEY_KEY_SINGLE_UNLOCK_VALUE << SI32_FLASHCTRL_A_KEY_KEY_SHIFT) 228 #define SI32_FLASHCTRL_A_KEY_KEY_MULTI_UNLOCK_VALUE 242 229 #define SI32_FLASHCTRL_A_KEY_KEY_MULTI_UNLOCK_U32 \ 230 (SI32_FLASHCTRL_A_KEY_KEY_MULTI_UNLOCK_VALUE << SI32_FLASHCTRL_A_KEY_KEY_SHIFT) 231 232 233 234 struct SI32_FLASHCTRL_A_TCONTROL_Struct 235 { 236 union 237 { 238 struct 239 { 240 uint32_t reserved0: 6; 241 // Flash Read Timing Mode 242 volatile uint32_t FLRTMD: 1; 243 uint32_t reserved1: 25; 244 }; 245 volatile uint32_t U32; 246 }; 247 }; 248 249 #define SI32_FLASHCTRL_A_TCONTROL_FLRTMD_MASK 0x00000040 250 #define SI32_FLASHCTRL_A_TCONTROL_FLRTMD_SHIFT 6 251 // Configure the flash read controller for AHB clocks below 12 MHz. 252 #define SI32_FLASHCTRL_A_TCONTROL_FLRTMD_SLOW_VALUE 0 253 #define SI32_FLASHCTRL_A_TCONTROL_FLRTMD_SLOW_U32 \ 254 (SI32_FLASHCTRL_A_TCONTROL_FLRTMD_SLOW_VALUE << SI32_FLASHCTRL_A_TCONTROL_FLRTMD_SHIFT) 255 // Configure the flash read controller for AHB clocks above 12 MHz. 256 #define SI32_FLASHCTRL_A_TCONTROL_FLRTMD_FAST_VALUE 1 257 #define SI32_FLASHCTRL_A_TCONTROL_FLRTMD_FAST_U32 \ 258 (SI32_FLASHCTRL_A_TCONTROL_FLRTMD_FAST_VALUE << SI32_FLASHCTRL_A_TCONTROL_FLRTMD_SHIFT) 259 260 261 262 typedef struct SI32_FLASHCTRL_A_Struct 263 { 264 struct SI32_FLASHCTRL_A_CONFIG_Struct CONFIG ; // Base Address + 0x0 265 volatile uint32_t CONFIG_SET; 266 volatile uint32_t CONFIG_CLR; 267 uint32_t reserved0; 268 uint32_t reserved1[4]; 269 uint32_t reserved2[4]; 270 uint32_t reserved3[4]; 271 uint32_t reserved4[4]; 272 uint32_t reserved5[4]; 273 uint32_t reserved6[4]; 274 uint32_t reserved7[4]; 275 uint32_t reserved8[4]; 276 uint32_t reserved9[4]; 277 struct SI32_FLASHCTRL_A_WRADDR_Struct WRADDR ; // Base Address + 0xa0 278 uint32_t reserved10; 279 uint32_t reserved11; 280 uint32_t reserved12; 281 struct SI32_FLASHCTRL_A_WRDATA_Struct WRDATA ; // Base Address + 0xb0 282 uint32_t reserved13; 283 uint32_t reserved14; 284 uint32_t reserved15; 285 struct SI32_FLASHCTRL_A_KEY_Struct KEY ; // Base Address + 0xc0 286 uint32_t reserved16; 287 uint32_t reserved17; 288 uint32_t reserved18; 289 struct SI32_FLASHCTRL_A_TCONTROL_Struct TCONTROL ; // Base Address + 0xd0 290 uint32_t reserved19; 291 uint32_t reserved20; 292 uint32_t reserved21; 293 uint32_t reserved22[4]; 294 uint32_t reserved23[4]; 295 uint32_t reserved24[4]; 296 uint32_t reserved25[4]; 297 uint32_t reserved26[4]; 298 uint32_t reserved27[4]; 299 uint32_t reserved28[4]; 300 uint32_t reserved29[4]; 301 } SI32_FLASHCTRL_A_Type; 302 303 #ifdef __cplusplus 304 } 305 #endif 306 307 #endif // __SI32_FLASHCTRL_A_REGISTERS_H__ 308 309 //-eof-------------------------------------------------------------------------- 310 311
