1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_ENCDEC_A_REGISTERS_H__ 27 #define __SI32_ENCDEC_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_ENCDEC_A_CONTROL_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Input Ready Interrupt Enable 42 volatile uint32_t INRDYIEN: 1; 43 // Output Ready Interrupt Enable 44 volatile uint32_t ORDYIEN: 1; 45 // Error Interrupt Enable 46 volatile uint32_t ERRIEN: 1; 47 // Module Reset 48 volatile uint32_t RESET: 1; 49 // Manchester Output Size 50 volatile uint32_t MOSIZE: 1; 51 // Encode Decode Mode 52 volatile uint32_t EDMD: 1; 53 // Operation Mode 54 volatile uint32_t OPMD: 1; 55 uint32_t reserved0: 1; 56 // Bypass Encoder/Decoder Operation Enable 57 volatile uint32_t BEN: 1; 58 // DMA Mode Enable 59 volatile uint32_t DMAEN: 1; 60 // Debug Mode 61 volatile uint32_t DBGMD: 1; 62 uint32_t reserved1: 1; 63 // Output Order Mode 64 volatile uint32_t OORDER: 2; 65 // Input Order Mode 66 volatile uint32_t IORDER: 2; 67 uint32_t reserved2: 16; 68 }; 69 volatile uint32_t U32; 70 }; 71 }; 72 73 #define SI32_ENCDEC_A_CONTROL_INRDYIEN_MASK 0x00000001 74 #define SI32_ENCDEC_A_CONTROL_INRDYIEN_SHIFT 0 75 // Disable the input ready interrupt. 76 #define SI32_ENCDEC_A_CONTROL_INRDYIEN_DISABLED_VALUE 0 77 #define SI32_ENCDEC_A_CONTROL_INRDYIEN_DISABLED_U32 \ 78 (SI32_ENCDEC_A_CONTROL_INRDYIEN_DISABLED_VALUE << SI32_ENCDEC_A_CONTROL_INRDYIEN_SHIFT) 79 // Enable the input ready interrupt. 80 #define SI32_ENCDEC_A_CONTROL_INRDYIEN_ENABLED_VALUE 1 81 #define SI32_ENCDEC_A_CONTROL_INRDYIEN_ENABLED_U32 \ 82 (SI32_ENCDEC_A_CONTROL_INRDYIEN_ENABLED_VALUE << SI32_ENCDEC_A_CONTROL_INRDYIEN_SHIFT) 83 84 #define SI32_ENCDEC_A_CONTROL_ORDYIEN_MASK 0x00000002 85 #define SI32_ENCDEC_A_CONTROL_ORDYIEN_SHIFT 1 86 // Disable the output ready interrupt. 87 #define SI32_ENCDEC_A_CONTROL_ORDYIEN_DISABLED_VALUE 0 88 #define SI32_ENCDEC_A_CONTROL_ORDYIEN_DISABLED_U32 \ 89 (SI32_ENCDEC_A_CONTROL_ORDYIEN_DISABLED_VALUE << SI32_ENCDEC_A_CONTROL_ORDYIEN_SHIFT) 90 // Enable the output ready interrupt. 91 #define SI32_ENCDEC_A_CONTROL_ORDYIEN_ENABLED_VALUE 1 92 #define SI32_ENCDEC_A_CONTROL_ORDYIEN_ENABLED_U32 \ 93 (SI32_ENCDEC_A_CONTROL_ORDYIEN_ENABLED_VALUE << SI32_ENCDEC_A_CONTROL_ORDYIEN_SHIFT) 94 95 #define SI32_ENCDEC_A_CONTROL_ERRIEN_MASK 0x00000004 96 #define SI32_ENCDEC_A_CONTROL_ERRIEN_SHIFT 2 97 // Disable the error interrupt. 98 #define SI32_ENCDEC_A_CONTROL_ERRIEN_DISABLED_VALUE 0 99 #define SI32_ENCDEC_A_CONTROL_ERRIEN_DISABLED_U32 \ 100 (SI32_ENCDEC_A_CONTROL_ERRIEN_DISABLED_VALUE << SI32_ENCDEC_A_CONTROL_ERRIEN_SHIFT) 101 // Enable the error interrupt. 102 #define SI32_ENCDEC_A_CONTROL_ERRIEN_ENABLED_VALUE 1 103 #define SI32_ENCDEC_A_CONTROL_ERRIEN_ENABLED_U32 \ 104 (SI32_ENCDEC_A_CONTROL_ERRIEN_ENABLED_VALUE << SI32_ENCDEC_A_CONTROL_ERRIEN_SHIFT) 105 106 #define SI32_ENCDEC_A_CONTROL_RESET_MASK 0x00000008 107 #define SI32_ENCDEC_A_CONTROL_RESET_SHIFT 3 108 // Reset the module. 109 #define SI32_ENCDEC_A_CONTROL_RESET_ACTIVE_VALUE 1 110 #define SI32_ENCDEC_A_CONTROL_RESET_ACTIVE_U32 \ 111 (SI32_ENCDEC_A_CONTROL_RESET_ACTIVE_VALUE << SI32_ENCDEC_A_CONTROL_RESET_SHIFT) 112 113 #define SI32_ENCDEC_A_CONTROL_MOSIZE_MASK 0x00000010 114 #define SI32_ENCDEC_A_CONTROL_MOSIZE_SHIFT 4 115 // Manchester encode operations generate a half-word output, and decode operations 116 // generate a byte output. 117 #define SI32_ENCDEC_A_CONTROL_MOSIZE_SMALL_VALUE 0 118 #define SI32_ENCDEC_A_CONTROL_MOSIZE_SMALL_U32 \ 119 (SI32_ENCDEC_A_CONTROL_MOSIZE_SMALL_VALUE << SI32_ENCDEC_A_CONTROL_MOSIZE_SHIFT) 120 // Manchester encode operations generate a word output, and decode operations 121 // generate a half-word output. 122 #define SI32_ENCDEC_A_CONTROL_MOSIZE_LARGE_VALUE 1 123 #define SI32_ENCDEC_A_CONTROL_MOSIZE_LARGE_U32 \ 124 (SI32_ENCDEC_A_CONTROL_MOSIZE_LARGE_VALUE << SI32_ENCDEC_A_CONTROL_MOSIZE_SHIFT) 125 126 #define SI32_ENCDEC_A_CONTROL_EDMD_MASK 0x00000020 127 #define SI32_ENCDEC_A_CONTROL_EDMD_SHIFT 5 128 // Decode data written to DATAIN. 129 #define SI32_ENCDEC_A_CONTROL_EDMD_DECODE_VALUE 0 130 #define SI32_ENCDEC_A_CONTROL_EDMD_DECODE_U32 \ 131 (SI32_ENCDEC_A_CONTROL_EDMD_DECODE_VALUE << SI32_ENCDEC_A_CONTROL_EDMD_SHIFT) 132 // Encode data written to DATAIN. 133 #define SI32_ENCDEC_A_CONTROL_EDMD_ENCODE_VALUE 1 134 #define SI32_ENCDEC_A_CONTROL_EDMD_ENCODE_U32 \ 135 (SI32_ENCDEC_A_CONTROL_EDMD_ENCODE_VALUE << SI32_ENCDEC_A_CONTROL_EDMD_SHIFT) 136 137 #define SI32_ENCDEC_A_CONTROL_OPMD_MASK 0x00000040 138 #define SI32_ENCDEC_A_CONTROL_OPMD_SHIFT 6 139 // The operation selected by EDMD uses Manchester mode. 140 #define SI32_ENCDEC_A_CONTROL_OPMD_MANCHESTER_VALUE 0 141 #define SI32_ENCDEC_A_CONTROL_OPMD_MANCHESTER_U32 \ 142 (SI32_ENCDEC_A_CONTROL_OPMD_MANCHESTER_VALUE << SI32_ENCDEC_A_CONTROL_OPMD_SHIFT) 143 // The operation selected by EDMD uses Three-out-of-Six mode. 144 #define SI32_ENCDEC_A_CONTROL_OPMD_3OUTOF6_VALUE 1 145 #define SI32_ENCDEC_A_CONTROL_OPMD_3OUTOF6_U32 \ 146 (SI32_ENCDEC_A_CONTROL_OPMD_3OUTOF6_VALUE << SI32_ENCDEC_A_CONTROL_OPMD_SHIFT) 147 148 #define SI32_ENCDEC_A_CONTROL_BEN_MASK 0x00000100 149 #define SI32_ENCDEC_A_CONTROL_BEN_SHIFT 8 150 // Do not bypass ENCDEC operations. 151 #define SI32_ENCDEC_A_CONTROL_BEN_DISABLED_VALUE 0 152 #define SI32_ENCDEC_A_CONTROL_BEN_DISABLED_U32 \ 153 (SI32_ENCDEC_A_CONTROL_BEN_DISABLED_VALUE << SI32_ENCDEC_A_CONTROL_BEN_SHIFT) 154 // Bypass ENCDEC operations. 155 #define SI32_ENCDEC_A_CONTROL_BEN_ENABLED_VALUE 1 156 #define SI32_ENCDEC_A_CONTROL_BEN_ENABLED_U32 \ 157 (SI32_ENCDEC_A_CONTROL_BEN_ENABLED_VALUE << SI32_ENCDEC_A_CONTROL_BEN_SHIFT) 158 159 #define SI32_ENCDEC_A_CONTROL_DMAEN_MASK 0x00000200 160 #define SI32_ENCDEC_A_CONTROL_DMAEN_SHIFT 9 161 // Disable DMA mode. 162 #define SI32_ENCDEC_A_CONTROL_DMAEN_DISABLED_VALUE 0 163 #define SI32_ENCDEC_A_CONTROL_DMAEN_DISABLED_U32 \ 164 (SI32_ENCDEC_A_CONTROL_DMAEN_DISABLED_VALUE << SI32_ENCDEC_A_CONTROL_DMAEN_SHIFT) 165 // Enable DMA mode. 166 #define SI32_ENCDEC_A_CONTROL_DMAEN_ENABLED_VALUE 1 167 #define SI32_ENCDEC_A_CONTROL_DMAEN_ENABLED_U32 \ 168 (SI32_ENCDEC_A_CONTROL_DMAEN_ENABLED_VALUE << SI32_ENCDEC_A_CONTROL_DMAEN_SHIFT) 169 170 #define SI32_ENCDEC_A_CONTROL_DBGMD_MASK 0x00000400 171 #define SI32_ENCDEC_A_CONTROL_DBGMD_SHIFT 10 172 // The ENCDEC module will continue to operate while the core is halted in debug 173 // mode. 174 #define SI32_ENCDEC_A_CONTROL_DBGMD_RUN_VALUE 0 175 #define SI32_ENCDEC_A_CONTROL_DBGMD_RUN_U32 \ 176 (SI32_ENCDEC_A_CONTROL_DBGMD_RUN_VALUE << SI32_ENCDEC_A_CONTROL_DBGMD_SHIFT) 177 // A debug breakpoint will cause the ENCDEC module to halt. 178 #define SI32_ENCDEC_A_CONTROL_DBGMD_HALT_VALUE 1 179 #define SI32_ENCDEC_A_CONTROL_DBGMD_HALT_U32 \ 180 (SI32_ENCDEC_A_CONTROL_DBGMD_HALT_VALUE << SI32_ENCDEC_A_CONTROL_DBGMD_SHIFT) 181 182 #define SI32_ENCDEC_A_CONTROL_OORDER_MASK 0x00003000 183 #define SI32_ENCDEC_A_CONTROL_OORDER_SHIFT 12 184 // The module outputs data to DATAOUT in the same order as it was processed (input: 185 // B3 B2 B1 B0, output: B3 B2 B1 B0). 186 #define SI32_ENCDEC_A_CONTROL_OORDER_NO_CHANGE_VALUE 0 187 #define SI32_ENCDEC_A_CONTROL_OORDER_NO_CHANGE_U32 \ 188 (SI32_ENCDEC_A_CONTROL_OORDER_NO_CHANGE_VALUE << SI32_ENCDEC_A_CONTROL_OORDER_SHIFT) 189 // The module flips the data in half-words before outputting to DATAOUT (input: B3 190 // B2 B1 B0, output: B2 B3 B0 B1). 191 #define SI32_ENCDEC_A_CONTROL_OORDER_HALF_WORD_VALUE 1 192 #define SI32_ENCDEC_A_CONTROL_OORDER_HALF_WORD_U32 \ 193 (SI32_ENCDEC_A_CONTROL_OORDER_HALF_WORD_VALUE << SI32_ENCDEC_A_CONTROL_OORDER_SHIFT) 194 // The module flips the data in words before outputting to DATAOUT (input: B3 B2 B1 195 // B0, output: B0 B1 B2 B3). 196 #define SI32_ENCDEC_A_CONTROL_OORDER_WORD_VALUE 2 197 #define SI32_ENCDEC_A_CONTROL_OORDER_WORD_U32 \ 198 (SI32_ENCDEC_A_CONTROL_OORDER_WORD_VALUE << SI32_ENCDEC_A_CONTROL_OORDER_SHIFT) 199 // The module flips the lower three bytes before outputting to DATAOUT (input: B3 200 // B2 B1 B0, output: B3 B0 B1 B2). 201 #define SI32_ENCDEC_A_CONTROL_OORDER_LOWER_THREE_BYTES_VALUE 3 202 #define SI32_ENCDEC_A_CONTROL_OORDER_LOWER_THREE_BYTES_U32 \ 203 (SI32_ENCDEC_A_CONTROL_OORDER_LOWER_THREE_BYTES_VALUE << SI32_ENCDEC_A_CONTROL_OORDER_SHIFT) 204 205 #define SI32_ENCDEC_A_CONTROL_IORDER_MASK 0x0000C000 206 #define SI32_ENCDEC_A_CONTROL_IORDER_SHIFT 14 207 // Data written to DATAIN is processed in the order written (input: B3 B2 B1 B0, 208 // output: B3 B2 B1 B0). 209 #define SI32_ENCDEC_A_CONTROL_IORDER_NO_CHANGE_VALUE 0 210 #define SI32_ENCDEC_A_CONTROL_IORDER_NO_CHANGE_U32 \ 211 (SI32_ENCDEC_A_CONTROL_IORDER_NO_CHANGE_VALUE << SI32_ENCDEC_A_CONTROL_IORDER_SHIFT) 212 // The module flips the DATAIN input data in half-words (input: B2 B3 B0 B1, 213 // output: B3 B2 B1 B0). 214 #define SI32_ENCDEC_A_CONTROL_IORDER_HALF_WORD_VALUE 1 215 #define SI32_ENCDEC_A_CONTROL_IORDER_HALF_WORD_U32 \ 216 (SI32_ENCDEC_A_CONTROL_IORDER_HALF_WORD_VALUE << SI32_ENCDEC_A_CONTROL_IORDER_SHIFT) 217 // The module flips the DATAIN input data in words (input: B0 B1 B2 B3, output: B3 218 // B2 B1 B0). 219 #define SI32_ENCDEC_A_CONTROL_IORDER_WORD_VALUE 2 220 #define SI32_ENCDEC_A_CONTROL_IORDER_WORD_U32 \ 221 (SI32_ENCDEC_A_CONTROL_IORDER_WORD_VALUE << SI32_ENCDEC_A_CONTROL_IORDER_SHIFT) 222 // The module flips the lower three bytes of the DATAIN input data (input: B3 B0 B1 223 // B2, output: B3 B2 B1 B0). 224 #define SI32_ENCDEC_A_CONTROL_IORDER_LOWER_THREE_BYTES_VALUE 3 225 #define SI32_ENCDEC_A_CONTROL_IORDER_LOWER_THREE_BYTES_U32 \ 226 (SI32_ENCDEC_A_CONTROL_IORDER_LOWER_THREE_BYTES_VALUE << SI32_ENCDEC_A_CONTROL_IORDER_SHIFT) 227 228 229 230 struct SI32_ENCDEC_A_STATUS_Struct 231 { 232 union 233 { 234 struct 235 { 236 // Input Ready Interrupt Flag 237 volatile uint32_t INRDYI: 1; 238 // Output Ready Interrupt Flag 239 volatile uint32_t ORDYI: 1; 240 // Data Error Interrupt Flag 241 volatile uint32_t DERRI: 1; 242 // Data Underrun Interrupt Flag 243 volatile uint32_t DURI: 1; 244 // Data Overrun Interrupt Flag 245 volatile uint32_t DORI: 1; 246 uint32_t reserved0: 27; 247 }; 248 volatile uint32_t U32; 249 }; 250 }; 251 252 #define SI32_ENCDEC_A_STATUS_INRDYI_MASK 0x00000001 253 #define SI32_ENCDEC_A_STATUS_INRDYI_SHIFT 0 254 // The input FIFO is not ready for new data. 255 #define SI32_ENCDEC_A_STATUS_INRDYI_NOT_SET_VALUE 0 256 #define SI32_ENCDEC_A_STATUS_INRDYI_NOT_SET_U32 \ 257 (SI32_ENCDEC_A_STATUS_INRDYI_NOT_SET_VALUE << SI32_ENCDEC_A_STATUS_INRDYI_SHIFT) 258 // Firmware can write new input data to DATAIN. 259 #define SI32_ENCDEC_A_STATUS_INRDYI_SET_VALUE 1 260 #define SI32_ENCDEC_A_STATUS_INRDYI_SET_U32 \ 261 (SI32_ENCDEC_A_STATUS_INRDYI_SET_VALUE << SI32_ENCDEC_A_STATUS_INRDYI_SHIFT) 262 263 #define SI32_ENCDEC_A_STATUS_ORDYI_MASK 0x00000002 264 #define SI32_ENCDEC_A_STATUS_ORDYI_SHIFT 1 265 // The output data is not ready. 266 #define SI32_ENCDEC_A_STATUS_ORDYI_NOT_SET_VALUE 0 267 #define SI32_ENCDEC_A_STATUS_ORDYI_NOT_SET_U32 \ 268 (SI32_ENCDEC_A_STATUS_ORDYI_NOT_SET_VALUE << SI32_ENCDEC_A_STATUS_ORDYI_SHIFT) 269 // The output data is ready to be read by firmware. 270 #define SI32_ENCDEC_A_STATUS_ORDYI_SET_VALUE 1 271 #define SI32_ENCDEC_A_STATUS_ORDYI_SET_U32 \ 272 (SI32_ENCDEC_A_STATUS_ORDYI_SET_VALUE << SI32_ENCDEC_A_STATUS_ORDYI_SHIFT) 273 274 #define SI32_ENCDEC_A_STATUS_DERRI_MASK 0x00000004 275 #define SI32_ENCDEC_A_STATUS_DERRI_SHIFT 2 276 #define SI32_ENCDEC_A_STATUS_DERRI_NOT_SET_VALUE 0 277 #define SI32_ENCDEC_A_STATUS_DERRI_NOT_SET_U32 \ 278 (SI32_ENCDEC_A_STATUS_DERRI_NOT_SET_VALUE << SI32_ENCDEC_A_STATUS_DERRI_SHIFT) 279 #define SI32_ENCDEC_A_STATUS_DERRI_SET_VALUE 1 280 #define SI32_ENCDEC_A_STATUS_DERRI_SET_U32 \ 281 (SI32_ENCDEC_A_STATUS_DERRI_SET_VALUE << SI32_ENCDEC_A_STATUS_DERRI_SHIFT) 282 283 #define SI32_ENCDEC_A_STATUS_DURI_MASK 0x00000008 284 #define SI32_ENCDEC_A_STATUS_DURI_SHIFT 3 285 // No output data FIFO underrun. 286 #define SI32_ENCDEC_A_STATUS_DURI_NOT_SET_VALUE 0 287 #define SI32_ENCDEC_A_STATUS_DURI_NOT_SET_U32 \ 288 (SI32_ENCDEC_A_STATUS_DURI_NOT_SET_VALUE << SI32_ENCDEC_A_STATUS_DURI_SHIFT) 289 // An output data FIFO underrun has occurred. 290 #define SI32_ENCDEC_A_STATUS_DURI_SET_VALUE 1 291 #define SI32_ENCDEC_A_STATUS_DURI_SET_U32 \ 292 (SI32_ENCDEC_A_STATUS_DURI_SET_VALUE << SI32_ENCDEC_A_STATUS_DURI_SHIFT) 293 294 #define SI32_ENCDEC_A_STATUS_DORI_MASK 0x00000010 295 #define SI32_ENCDEC_A_STATUS_DORI_SHIFT 4 296 // No input data FIFO overrun. 297 #define SI32_ENCDEC_A_STATUS_DORI_NOT_SET_VALUE 0 298 #define SI32_ENCDEC_A_STATUS_DORI_NOT_SET_U32 \ 299 (SI32_ENCDEC_A_STATUS_DORI_NOT_SET_VALUE << SI32_ENCDEC_A_STATUS_DORI_SHIFT) 300 // An input data FIFO overrun has occurred. 301 #define SI32_ENCDEC_A_STATUS_DORI_SET_VALUE 1 302 #define SI32_ENCDEC_A_STATUS_DORI_SET_U32 \ 303 (SI32_ENCDEC_A_STATUS_DORI_SET_VALUE << SI32_ENCDEC_A_STATUS_DORI_SHIFT) 304 305 306 307 struct SI32_ENCDEC_A_DATAIN_Struct 308 { 309 union 310 { 311 // This is a FIFO register 312 volatile uint8_t U8; 313 volatile uint16_t U16; 314 volatile uint32_t U32; 315 }; 316 }; 317 318 #define SI32_ENCDEC_A_DATAIN_DATAIN_MASK 0xFFFFFFFF 319 #define SI32_ENCDEC_A_DATAIN_DATAIN_SHIFT 0 320 321 322 323 struct SI32_ENCDEC_A_DATAOUT_Struct 324 { 325 union 326 { 327 // This is a FIFO register 328 volatile uint8_t U8; 329 volatile uint16_t U16; 330 volatile uint32_t U32; 331 }; 332 }; 333 334 #define SI32_ENCDEC_A_DATAOUT_DATAOUT_MASK 0xFFFFFFFF 335 #define SI32_ENCDEC_A_DATAOUT_DATAOUT_SHIFT 0 336 337 338 339 struct SI32_ENCDEC_A_DATAOUTC_Struct 340 { 341 union 342 { 343 // This is a FIFO register 344 volatile uint8_t U8; 345 volatile uint16_t U16; 346 volatile uint32_t U32; 347 }; 348 }; 349 350 #define SI32_ENCDEC_A_DATAOUTC_DATAOUTC_MASK 0xFFFFFFFF 351 #define SI32_ENCDEC_A_DATAOUTC_DATAOUTC_SHIFT 0 352 353 354 355 typedef struct SI32_ENCDEC_A_Struct 356 { 357 struct SI32_ENCDEC_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 358 volatile uint32_t CONTROL_SET; 359 volatile uint32_t CONTROL_CLR; 360 uint32_t reserved0; 361 struct SI32_ENCDEC_A_STATUS_Struct STATUS ; // Base Address + 0x10 362 uint32_t reserved1; 363 uint32_t reserved2; 364 uint32_t reserved3; 365 struct SI32_ENCDEC_A_DATAIN_Struct DATAIN ; // Base Address + 0x20 366 uint32_t reserved4; 367 uint32_t reserved5; 368 uint32_t reserved6; 369 struct SI32_ENCDEC_A_DATAOUT_Struct DATAOUT ; // Base Address + 0x30 370 uint32_t reserved7; 371 uint32_t reserved8; 372 uint32_t reserved9; 373 struct SI32_ENCDEC_A_DATAOUTC_Struct DATAOUTC ; // Base Address + 0x40 374 uint32_t reserved10; 375 uint32_t reserved11; 376 uint32_t reserved12; 377 } SI32_ENCDEC_A_Type; 378 379 #ifdef __cplusplus 380 } 381 #endif 382 383 #endif // __SI32_ENCDEC_A_REGISTERS_H__ 384 385 //-eof-------------------------------------------------------------------------- 386 387
