1 //----------------------------------------------------------------------------- 2 // Copyright 2013 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.62 24 // Version: 1 25 26 #ifndef __SI32_EMIF_A_REGISTERS_H__ 27 #define __SI32_EMIF_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_EMIF_A_CONTROL_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Interface 0 Enable 42 volatile uint32_t IF0EN: 1; 43 // Interface 1 Enable 44 volatile uint32_t IF1EN: 1; 45 uint32_t reserved0: 2; 46 // OFF Output State Enable 47 volatile uint32_t OFFSTEN: 1; 48 uint32_t reserved1: 27; 49 }; 50 volatile uint32_t U32; 51 }; 52 }; 53 54 #define SI32_EMIF_A_CONTROL_IF0EN_MASK 0x00000001 55 #define SI32_EMIF_A_CONTROL_IF0EN_SHIFT 0 56 // Disable interface 0. 57 #define SI32_EMIF_A_CONTROL_IF0EN_DISABLED_VALUE 0 58 #define SI32_EMIF_A_CONTROL_IF0EN_DISABLED_U32 \ 59 (SI32_EMIF_A_CONTROL_IF0EN_DISABLED_VALUE << SI32_EMIF_A_CONTROL_IF0EN_SHIFT) 60 // Enable interface 0. 61 #define SI32_EMIF_A_CONTROL_IF0EN_ENABLED_VALUE 1 62 #define SI32_EMIF_A_CONTROL_IF0EN_ENABLED_U32 \ 63 (SI32_EMIF_A_CONTROL_IF0EN_ENABLED_VALUE << SI32_EMIF_A_CONTROL_IF0EN_SHIFT) 64 65 #define SI32_EMIF_A_CONTROL_IF1EN_MASK 0x00000002 66 #define SI32_EMIF_A_CONTROL_IF1EN_SHIFT 1 67 // Disable interface 1. 68 #define SI32_EMIF_A_CONTROL_IF1EN_DISABLED_VALUE 0 69 #define SI32_EMIF_A_CONTROL_IF1EN_DISABLED_U32 \ 70 (SI32_EMIF_A_CONTROL_IF1EN_DISABLED_VALUE << SI32_EMIF_A_CONTROL_IF1EN_SHIFT) 71 // Enable interface 1. 72 #define SI32_EMIF_A_CONTROL_IF1EN_ENABLED_VALUE 1 73 #define SI32_EMIF_A_CONTROL_IF1EN_ENABLED_U32 \ 74 (SI32_EMIF_A_CONTROL_IF1EN_ENABLED_VALUE << SI32_EMIF_A_CONTROL_IF1EN_SHIFT) 75 76 #define SI32_EMIF_A_CONTROL_OFFSTEN_MASK 0x00000010 77 #define SI32_EMIF_A_CONTROL_OFFSTEN_SHIFT 4 78 // EMIF will not enter the off state after 4 idle cycles. 79 #define SI32_EMIF_A_CONTROL_OFFSTEN_DISABLED_VALUE 0 80 #define SI32_EMIF_A_CONTROL_OFFSTEN_DISABLED_U32 \ 81 (SI32_EMIF_A_CONTROL_OFFSTEN_DISABLED_VALUE << SI32_EMIF_A_CONTROL_OFFSTEN_SHIFT) 82 // EMIF will enter the off state after 4 idle cycles. 83 #define SI32_EMIF_A_CONTROL_OFFSTEN_ENABLED_VALUE 1 84 #define SI32_EMIF_A_CONTROL_OFFSTEN_ENABLED_U32 \ 85 (SI32_EMIF_A_CONTROL_OFFSTEN_ENABLED_VALUE << SI32_EMIF_A_CONTROL_OFFSTEN_SHIFT) 86 87 88 89 struct SI32_EMIF_A_STATUS_Struct 90 { 91 union 92 { 93 struct 94 { 95 // EMIF OFF Status 96 volatile uint32_t OFFSTS: 1; 97 // EMIF IDLE Status 98 volatile uint32_t IDLESTS: 1; 99 uint32_t reserved0: 30; 100 }; 101 volatile uint32_t U32; 102 }; 103 }; 104 105 #define SI32_EMIF_A_STATUS_OFFSTS_MASK 0x00000001 106 #define SI32_EMIF_A_STATUS_OFFSTS_SHIFT 0 107 // The EMIF bus is active. 108 #define SI32_EMIF_A_STATUS_OFFSTS_ON_VALUE 0 109 #define SI32_EMIF_A_STATUS_OFFSTS_ON_U32 \ 110 (SI32_EMIF_A_STATUS_OFFSTS_ON_VALUE << SI32_EMIF_A_STATUS_OFFSTS_SHIFT) 111 // The EMIF is in the off bus state. 112 #define SI32_EMIF_A_STATUS_OFFSTS_OFF_VALUE 1 113 #define SI32_EMIF_A_STATUS_OFFSTS_OFF_U32 \ 114 (SI32_EMIF_A_STATUS_OFFSTS_OFF_VALUE << SI32_EMIF_A_STATUS_OFFSTS_SHIFT) 115 116 #define SI32_EMIF_A_STATUS_IDLESTS_MASK 0x00000002 117 #define SI32_EMIF_A_STATUS_IDLESTS_SHIFT 1 118 // The EMIF has not been idle for four cycles. 119 #define SI32_EMIF_A_STATUS_IDLESTS_NOT_IDLE_VALUE 0 120 #define SI32_EMIF_A_STATUS_IDLESTS_NOT_IDLE_U32 \ 121 (SI32_EMIF_A_STATUS_IDLESTS_NOT_IDLE_VALUE << SI32_EMIF_A_STATUS_IDLESTS_SHIFT) 122 // The EMIF has been idle for four four cycles. 123 #define SI32_EMIF_A_STATUS_IDLESTS_IDLE_VALUE 1 124 #define SI32_EMIF_A_STATUS_IDLESTS_IDLE_U32 \ 125 (SI32_EMIF_A_STATUS_IDLESTS_IDLE_VALUE << SI32_EMIF_A_STATUS_IDLESTS_SHIFT) 126 127 128 129 typedef struct SI32_EMIF_A_Struct 130 { 131 struct SI32_EMIF_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 132 volatile uint32_t CONTROL_SET; 133 volatile uint32_t CONTROL_CLR; 134 uint32_t reserved0; 135 uint32_t reserved1[4]; 136 struct SI32_EMIF_A_STATUS_Struct STATUS ; // Base Address + 0x20 137 uint32_t reserved2; 138 uint32_t reserved3; 139 uint32_t reserved4; 140 } SI32_EMIF_A_Type; 141 142 #ifdef __cplusplus 143 } 144 #endif 145 146 #endif // __SI32_EMIF_A_REGISTERS_H__ 147 148 //-eof-------------------------------------------------------------------------- 149 150
