1 //----------------------------------------------------------------------------- 2 // Copyright 2013 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.62 24 // Version: 1 25 26 #ifndef __SI32_EMIFIF_A_REGISTERS_H__ 27 #define __SI32_EMIFIF_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_EMIFIF_A_CONFIG_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Interface Bus Data Width 42 volatile uint32_t BUSWIDTH: 1; 43 uint32_t reserved0: 1; 44 // Interface Mux Mode 45 volatile uint32_t MUXMD: 1; 46 // Interface Automatic Address Shift Enable 47 volatile uint32_t ASEN: 1; 48 // Interface Read Only Enable 49 volatile uint32_t ROEN: 1; 50 uint32_t reserved1: 3; 51 // Write Data Hold State Inhibit 52 volatile uint32_t WDHINH: 1; 53 uint32_t reserved2: 3; 54 // Output Enable Delay 55 volatile uint32_t DELAYOE: 1; 56 uint32_t reserved3: 3; 57 // Keep Last Read Enable 58 volatile uint32_t KLREN: 1; 59 uint32_t reserved4: 15; 60 }; 61 volatile uint32_t U32; 62 }; 63 }; 64 65 #define SI32_EMIFIF_A_CONFIG_BUSWIDTH_MASK 0x00000001 66 #define SI32_EMIFIF_A_CONFIG_BUSWIDTH_SHIFT 0 67 // The data bus is 8-bits wide. 68 #define SI32_EMIFIF_A_CONFIG_BUSWIDTH_8BIT_VALUE 0 69 #define SI32_EMIFIF_A_CONFIG_BUSWIDTH_8BIT_U32 \ 70 (SI32_EMIFIF_A_CONFIG_BUSWIDTH_8BIT_VALUE << SI32_EMIFIF_A_CONFIG_BUSWIDTH_SHIFT) 71 // The data bus is 16-bits wide. This option should only be used in multiplexed 72 // mode (MUXMD = 1). 73 #define SI32_EMIFIF_A_CONFIG_BUSWIDTH_16BIT_VALUE 1 74 #define SI32_EMIFIF_A_CONFIG_BUSWIDTH_16BIT_U32 \ 75 (SI32_EMIFIF_A_CONFIG_BUSWIDTH_16BIT_VALUE << SI32_EMIFIF_A_CONFIG_BUSWIDTH_SHIFT) 76 77 #define SI32_EMIFIF_A_CONFIG_MUXMD_MASK 0x00000004 78 #define SI32_EMIFIF_A_CONFIG_MUXMD_SHIFT 2 79 // The interface operates in non-multiplexed mode. 80 #define SI32_EMIFIF_A_CONFIG_MUXMD_NONMUXED_VALUE 0 81 #define SI32_EMIFIF_A_CONFIG_MUXMD_NONMUXED_U32 \ 82 (SI32_EMIFIF_A_CONFIG_MUXMD_NONMUXED_VALUE << SI32_EMIFIF_A_CONFIG_MUXMD_SHIFT) 83 // The interface operates in multiplexed mode. 84 #define SI32_EMIFIF_A_CONFIG_MUXMD_MUXED_VALUE 1 85 #define SI32_EMIFIF_A_CONFIG_MUXMD_MUXED_U32 \ 86 (SI32_EMIFIF_A_CONFIG_MUXMD_MUXED_VALUE << SI32_EMIFIF_A_CONFIG_MUXMD_SHIFT) 87 88 #define SI32_EMIFIF_A_CONFIG_ASEN_MASK 0x00000008 89 #define SI32_EMIFIF_A_CONFIG_ASEN_SHIFT 3 90 // The address is not automatically shifted. 91 #define SI32_EMIFIF_A_CONFIG_ASEN_DISABLED_VALUE 0 92 #define SI32_EMIFIF_A_CONFIG_ASEN_DISABLED_U32 \ 93 (SI32_EMIFIF_A_CONFIG_ASEN_DISABLED_VALUE << SI32_EMIFIF_A_CONFIG_ASEN_SHIFT) 94 // The address is automatically shifted. 95 #define SI32_EMIFIF_A_CONFIG_ASEN_ENABLED_VALUE 1 96 #define SI32_EMIFIF_A_CONFIG_ASEN_ENABLED_U32 \ 97 (SI32_EMIFIF_A_CONFIG_ASEN_ENABLED_VALUE << SI32_EMIFIF_A_CONFIG_ASEN_SHIFT) 98 99 #define SI32_EMIFIF_A_CONFIG_ROEN_MASK 0x00000010 100 #define SI32_EMIFIF_A_CONFIG_ROEN_SHIFT 4 101 // The interface supports reads and writes. 102 #define SI32_EMIFIF_A_CONFIG_ROEN_DISABLED_VALUE 0 103 #define SI32_EMIFIF_A_CONFIG_ROEN_DISABLED_U32 \ 104 (SI32_EMIFIF_A_CONFIG_ROEN_DISABLED_VALUE << SI32_EMIFIF_A_CONFIG_ROEN_SHIFT) 105 // The interface supports only reads. 106 #define SI32_EMIFIF_A_CONFIG_ROEN_ENABLED_VALUE 1 107 #define SI32_EMIFIF_A_CONFIG_ROEN_ENABLED_U32 \ 108 (SI32_EMIFIF_A_CONFIG_ROEN_ENABLED_VALUE << SI32_EMIFIF_A_CONFIG_ROEN_SHIFT) 109 110 #define SI32_EMIFIF_A_CONFIG_WDHINH_MASK 0x00000100 111 #define SI32_EMIFIF_A_CONFIG_WDHINH_SHIFT 8 112 // Enable the write data hold state. 113 #define SI32_EMIFIF_A_CONFIG_WDHINH_INACTIVE_VALUE 0 114 #define SI32_EMIFIF_A_CONFIG_WDHINH_INACTIVE_U32 \ 115 (SI32_EMIFIF_A_CONFIG_WDHINH_INACTIVE_VALUE << SI32_EMIFIF_A_CONFIG_WDHINH_SHIFT) 116 // Inhibit the write data hold state. 117 #define SI32_EMIFIF_A_CONFIG_WDHINH_ACTIVE_VALUE 1 118 #define SI32_EMIFIF_A_CONFIG_WDHINH_ACTIVE_U32 \ 119 (SI32_EMIFIF_A_CONFIG_WDHINH_ACTIVE_VALUE << SI32_EMIFIF_A_CONFIG_WDHINH_SHIFT) 120 121 #define SI32_EMIFIF_A_CONFIG_DELAYOE_MASK 0x00001000 122 #define SI32_EMIFIF_A_CONFIG_DELAYOE_SHIFT 12 123 // The output enable signal (/OE) is not delayed. 124 #define SI32_EMIFIF_A_CONFIG_DELAYOE_DISABLED_VALUE 0 125 #define SI32_EMIFIF_A_CONFIG_DELAYOE_DISABLED_U32 \ 126 (SI32_EMIFIF_A_CONFIG_DELAYOE_DISABLED_VALUE << SI32_EMIFIF_A_CONFIG_DELAYOE_SHIFT) 127 // The output enable signal (/OE) is delayed. 128 #define SI32_EMIFIF_A_CONFIG_DELAYOE_ENABLED_VALUE 1 129 #define SI32_EMIFIF_A_CONFIG_DELAYOE_ENABLED_U32 \ 130 (SI32_EMIFIF_A_CONFIG_DELAYOE_ENABLED_VALUE << SI32_EMIFIF_A_CONFIG_DELAYOE_SHIFT) 131 132 #define SI32_EMIFIF_A_CONFIG_KLREN_MASK 0x00010000 133 #define SI32_EMIFIF_A_CONFIG_KLREN_SHIFT 16 134 // The bus is driven to the idle state between active requests. 135 #define SI32_EMIFIF_A_CONFIG_KLREN_DISABLED_VALUE 0 136 #define SI32_EMIFIF_A_CONFIG_KLREN_DISABLED_U32 \ 137 (SI32_EMIFIF_A_CONFIG_KLREN_DISABLED_VALUE << SI32_EMIFIF_A_CONFIG_KLREN_SHIFT) 138 // The bus drives the last value read on the interface between active requests. 139 #define SI32_EMIFIF_A_CONFIG_KLREN_ENABLED_VALUE 1 140 #define SI32_EMIFIF_A_CONFIG_KLREN_ENABLED_U32 \ 141 (SI32_EMIFIF_A_CONFIG_KLREN_ENABLED_VALUE << SI32_EMIFIF_A_CONFIG_KLREN_SHIFT) 142 143 144 145 struct SI32_EMIFIF_A_IFRT_Struct 146 { 147 union 148 { 149 struct 150 { 151 // Interface Read Address Setup Delay 152 volatile uint32_t RASET: 4; 153 // Interface Read Address Hold Delay 154 volatile uint32_t RAHOLD: 4; 155 // Interface Read Data Hold Delay 156 volatile uint32_t RDHOLD: 4; 157 uint32_t reserved0: 4; 158 // Interface Read Data Wait Delay 159 volatile uint32_t RDWAIT: 6; 160 uint32_t reserved1: 10; 161 }; 162 volatile uint32_t U32; 163 }; 164 }; 165 166 #define SI32_EMIFIF_A_IFRT_RASET_MASK 0x0000000F 167 #define SI32_EMIFIF_A_IFRT_RASET_SHIFT 0 168 169 #define SI32_EMIFIF_A_IFRT_RAHOLD_MASK 0x000000F0 170 #define SI32_EMIFIF_A_IFRT_RAHOLD_SHIFT 4 171 172 #define SI32_EMIFIF_A_IFRT_RDHOLD_MASK 0x00000F00 173 #define SI32_EMIFIF_A_IFRT_RDHOLD_SHIFT 8 174 175 #define SI32_EMIFIF_A_IFRT_RDWAIT_MASK 0x003F0000 176 #define SI32_EMIFIF_A_IFRT_RDWAIT_SHIFT 16 177 178 179 180 struct SI32_EMIFIF_A_IFWT_Struct 181 { 182 union 183 { 184 struct 185 { 186 // Interface Write Address Setup Delay 187 volatile uint32_t WASET: 4; 188 // Interface Write Address Hold Delay 189 volatile uint32_t WAHOLD: 4; 190 // Interface Write Data Hold Delay 191 volatile uint32_t WDHOLD: 4; 192 uint32_t reserved0: 4; 193 // Interface Write Data Wait Delay 194 volatile uint32_t WDWAIT: 6; 195 uint32_t reserved1: 10; 196 }; 197 volatile uint32_t U32; 198 }; 199 }; 200 201 #define SI32_EMIFIF_A_IFWT_WASET_MASK 0x0000000F 202 #define SI32_EMIFIF_A_IFWT_WASET_SHIFT 0 203 204 #define SI32_EMIFIF_A_IFWT_WAHOLD_MASK 0x000000F0 205 #define SI32_EMIFIF_A_IFWT_WAHOLD_SHIFT 4 206 207 #define SI32_EMIFIF_A_IFWT_WDHOLD_MASK 0x00000F00 208 #define SI32_EMIFIF_A_IFWT_WDHOLD_SHIFT 8 209 210 #define SI32_EMIFIF_A_IFWT_WDWAIT_MASK 0x003F0000 211 #define SI32_EMIFIF_A_IFWT_WDWAIT_SHIFT 16 212 213 214 215 struct SI32_EMIFIF_A_IFRCST_Struct 216 { 217 union 218 { 219 struct 220 { 221 // Chip Select Read Address Setup State 222 volatile uint32_t CSRAS: 1; 223 // Chip Select Read Address Hold State 224 volatile uint32_t CSRAH: 1; 225 // Chip Select Read Data Wait State 226 volatile uint32_t CSRDW: 1; 227 // Chip Select Read Data Hold State 228 volatile uint32_t CSRDH: 1; 229 // Output Enable Read Address Setup State 230 volatile uint32_t OERAS: 1; 231 // Output Enable Read Address Hold State 232 volatile uint32_t OERAH: 1; 233 // Output Enable Read Data Wait State 234 volatile uint32_t OERDW: 1; 235 // Output Enable Read Data Hold State 236 volatile uint32_t OERDH: 1; 237 // Write Signal Read Address Setup State 238 volatile uint32_t WRRAS: 1; 239 // Write Signal Read Address Hold State 240 volatile uint32_t WRRAH: 1; 241 // Write Signal Read Data Wait State 242 volatile uint32_t WRRDW: 1; 243 // Write Signal Read Data Hold State 244 volatile uint32_t WRRDH: 1; 245 // Address Latch Enable Read Address Setup State 246 volatile uint32_t ALERAS: 1; 247 // Address Latch Enable Read Address Hold State 248 volatile uint32_t ALERAH: 1; 249 // Address Latch Enable Read Data Wait State 250 volatile uint32_t ALERDW: 1; 251 // Address Latch Enable Read Data Hold State 252 volatile uint32_t ALERDH: 1; 253 uint32_t reserved0: 16; 254 }; 255 volatile uint32_t U32; 256 }; 257 }; 258 259 #define SI32_EMIFIF_A_IFRCST_CSRAS_MASK 0x00000001 260 #define SI32_EMIFIF_A_IFRCST_CSRAS_SHIFT 0 261 // Set chip select (CSx) to low during the read address setup state. 262 #define SI32_EMIFIF_A_IFRCST_CSRAS_LOW_VALUE 0 263 #define SI32_EMIFIF_A_IFRCST_CSRAS_LOW_U32 \ 264 (SI32_EMIFIF_A_IFRCST_CSRAS_LOW_VALUE << SI32_EMIFIF_A_IFRCST_CSRAS_SHIFT) 265 // Set chip select (CSx) to high during the read address setup state. 266 #define SI32_EMIFIF_A_IFRCST_CSRAS_HIGH_VALUE 1 267 #define SI32_EMIFIF_A_IFRCST_CSRAS_HIGH_U32 \ 268 (SI32_EMIFIF_A_IFRCST_CSRAS_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_CSRAS_SHIFT) 269 270 #define SI32_EMIFIF_A_IFRCST_CSRAH_MASK 0x00000002 271 #define SI32_EMIFIF_A_IFRCST_CSRAH_SHIFT 1 272 // Set chip select (CSx) to low during the read address hold state. 273 #define SI32_EMIFIF_A_IFRCST_CSRAH_LOW_VALUE 0 274 #define SI32_EMIFIF_A_IFRCST_CSRAH_LOW_U32 \ 275 (SI32_EMIFIF_A_IFRCST_CSRAH_LOW_VALUE << SI32_EMIFIF_A_IFRCST_CSRAH_SHIFT) 276 // Set chip select (CSx) to high during the read address hold state. 277 #define SI32_EMIFIF_A_IFRCST_CSRAH_HIGH_VALUE 1 278 #define SI32_EMIFIF_A_IFRCST_CSRAH_HIGH_U32 \ 279 (SI32_EMIFIF_A_IFRCST_CSRAH_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_CSRAH_SHIFT) 280 281 #define SI32_EMIFIF_A_IFRCST_CSRDW_MASK 0x00000004 282 #define SI32_EMIFIF_A_IFRCST_CSRDW_SHIFT 2 283 // Set chip select (CSx) to low during the read data wait state. 284 #define SI32_EMIFIF_A_IFRCST_CSRDW_LOW_VALUE 0 285 #define SI32_EMIFIF_A_IFRCST_CSRDW_LOW_U32 \ 286 (SI32_EMIFIF_A_IFRCST_CSRDW_LOW_VALUE << SI32_EMIFIF_A_IFRCST_CSRDW_SHIFT) 287 // Set chip select (CSx) to high during the read data wait state. 288 #define SI32_EMIFIF_A_IFRCST_CSRDW_HIGH_VALUE 1 289 #define SI32_EMIFIF_A_IFRCST_CSRDW_HIGH_U32 \ 290 (SI32_EMIFIF_A_IFRCST_CSRDW_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_CSRDW_SHIFT) 291 292 #define SI32_EMIFIF_A_IFRCST_CSRDH_MASK 0x00000008 293 #define SI32_EMIFIF_A_IFRCST_CSRDH_SHIFT 3 294 // Set chip select (CSx) to low during the read data hold state. 295 #define SI32_EMIFIF_A_IFRCST_CSRDH_LOW_VALUE 0 296 #define SI32_EMIFIF_A_IFRCST_CSRDH_LOW_U32 \ 297 (SI32_EMIFIF_A_IFRCST_CSRDH_LOW_VALUE << SI32_EMIFIF_A_IFRCST_CSRDH_SHIFT) 298 // Set chip select (CSx) to high during the read data hold state. 299 #define SI32_EMIFIF_A_IFRCST_CSRDH_HIGH_VALUE 1 300 #define SI32_EMIFIF_A_IFRCST_CSRDH_HIGH_U32 \ 301 (SI32_EMIFIF_A_IFRCST_CSRDH_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_CSRDH_SHIFT) 302 303 #define SI32_EMIFIF_A_IFRCST_OERAS_MASK 0x00000010 304 #define SI32_EMIFIF_A_IFRCST_OERAS_SHIFT 4 305 // Set output enable (/OE) to low during the read address setup state. 306 #define SI32_EMIFIF_A_IFRCST_OERAS_LOW_VALUE 0 307 #define SI32_EMIFIF_A_IFRCST_OERAS_LOW_U32 \ 308 (SI32_EMIFIF_A_IFRCST_OERAS_LOW_VALUE << SI32_EMIFIF_A_IFRCST_OERAS_SHIFT) 309 // Set output enable (/OE) to high during the read address setup state. 310 #define SI32_EMIFIF_A_IFRCST_OERAS_HIGH_VALUE 1 311 #define SI32_EMIFIF_A_IFRCST_OERAS_HIGH_U32 \ 312 (SI32_EMIFIF_A_IFRCST_OERAS_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_OERAS_SHIFT) 313 314 #define SI32_EMIFIF_A_IFRCST_OERAH_MASK 0x00000020 315 #define SI32_EMIFIF_A_IFRCST_OERAH_SHIFT 5 316 // Set output enable (/OE) to low during the read address hold state. 317 #define SI32_EMIFIF_A_IFRCST_OERAH_LOW_VALUE 0 318 #define SI32_EMIFIF_A_IFRCST_OERAH_LOW_U32 \ 319 (SI32_EMIFIF_A_IFRCST_OERAH_LOW_VALUE << SI32_EMIFIF_A_IFRCST_OERAH_SHIFT) 320 // Set output enable (/OE) to high during the read address hold state. 321 #define SI32_EMIFIF_A_IFRCST_OERAH_HIGH_VALUE 1 322 #define SI32_EMIFIF_A_IFRCST_OERAH_HIGH_U32 \ 323 (SI32_EMIFIF_A_IFRCST_OERAH_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_OERAH_SHIFT) 324 325 #define SI32_EMIFIF_A_IFRCST_OERDW_MASK 0x00000040 326 #define SI32_EMIFIF_A_IFRCST_OERDW_SHIFT 6 327 // Set output enable (/OE) to low during the read data wait state. 328 #define SI32_EMIFIF_A_IFRCST_OERDW_LOW_VALUE 0 329 #define SI32_EMIFIF_A_IFRCST_OERDW_LOW_U32 \ 330 (SI32_EMIFIF_A_IFRCST_OERDW_LOW_VALUE << SI32_EMIFIF_A_IFRCST_OERDW_SHIFT) 331 // Set output enable (/OE) to high during the read data wait state. 332 #define SI32_EMIFIF_A_IFRCST_OERDW_HIGH_VALUE 1 333 #define SI32_EMIFIF_A_IFRCST_OERDW_HIGH_U32 \ 334 (SI32_EMIFIF_A_IFRCST_OERDW_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_OERDW_SHIFT) 335 336 #define SI32_EMIFIF_A_IFRCST_OERDH_MASK 0x00000080 337 #define SI32_EMIFIF_A_IFRCST_OERDH_SHIFT 7 338 // Set output enable (/OE) to low during the read data hold state. 339 #define SI32_EMIFIF_A_IFRCST_OERDH_LOW_VALUE 0 340 #define SI32_EMIFIF_A_IFRCST_OERDH_LOW_U32 \ 341 (SI32_EMIFIF_A_IFRCST_OERDH_LOW_VALUE << SI32_EMIFIF_A_IFRCST_OERDH_SHIFT) 342 // Set output enable (/OE) to high during the read data hold state. 343 #define SI32_EMIFIF_A_IFRCST_OERDH_HIGH_VALUE 1 344 #define SI32_EMIFIF_A_IFRCST_OERDH_HIGH_U32 \ 345 (SI32_EMIFIF_A_IFRCST_OERDH_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_OERDH_SHIFT) 346 347 #define SI32_EMIFIF_A_IFRCST_WRRAS_MASK 0x00000100 348 #define SI32_EMIFIF_A_IFRCST_WRRAS_SHIFT 8 349 // Set write signal (/WR) to low during the read address setup state. 350 #define SI32_EMIFIF_A_IFRCST_WRRAS_LOW_VALUE 0 351 #define SI32_EMIFIF_A_IFRCST_WRRAS_LOW_U32 \ 352 (SI32_EMIFIF_A_IFRCST_WRRAS_LOW_VALUE << SI32_EMIFIF_A_IFRCST_WRRAS_SHIFT) 353 // Set write signal (/WR) to high during the read address setup state. 354 #define SI32_EMIFIF_A_IFRCST_WRRAS_HIGH_VALUE 1 355 #define SI32_EMIFIF_A_IFRCST_WRRAS_HIGH_U32 \ 356 (SI32_EMIFIF_A_IFRCST_WRRAS_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_WRRAS_SHIFT) 357 358 #define SI32_EMIFIF_A_IFRCST_WRRAH_MASK 0x00000200 359 #define SI32_EMIFIF_A_IFRCST_WRRAH_SHIFT 9 360 // Set write signal (/WR) to low during the read address hold state. 361 #define SI32_EMIFIF_A_IFRCST_WRRAH_LOW_VALUE 0 362 #define SI32_EMIFIF_A_IFRCST_WRRAH_LOW_U32 \ 363 (SI32_EMIFIF_A_IFRCST_WRRAH_LOW_VALUE << SI32_EMIFIF_A_IFRCST_WRRAH_SHIFT) 364 // Set write signal (/WR) to high during the read address hold state. 365 #define SI32_EMIFIF_A_IFRCST_WRRAH_HIGH_VALUE 1 366 #define SI32_EMIFIF_A_IFRCST_WRRAH_HIGH_U32 \ 367 (SI32_EMIFIF_A_IFRCST_WRRAH_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_WRRAH_SHIFT) 368 369 #define SI32_EMIFIF_A_IFRCST_WRRDW_MASK 0x00000400 370 #define SI32_EMIFIF_A_IFRCST_WRRDW_SHIFT 10 371 // Set write signal (/WR) to low during the read data wait state. 372 #define SI32_EMIFIF_A_IFRCST_WRRDW_LOW_VALUE 0 373 #define SI32_EMIFIF_A_IFRCST_WRRDW_LOW_U32 \ 374 (SI32_EMIFIF_A_IFRCST_WRRDW_LOW_VALUE << SI32_EMIFIF_A_IFRCST_WRRDW_SHIFT) 375 // Set write signal (/WR) to high during the read data wait state. 376 #define SI32_EMIFIF_A_IFRCST_WRRDW_HIGH_VALUE 1 377 #define SI32_EMIFIF_A_IFRCST_WRRDW_HIGH_U32 \ 378 (SI32_EMIFIF_A_IFRCST_WRRDW_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_WRRDW_SHIFT) 379 380 #define SI32_EMIFIF_A_IFRCST_WRRDH_MASK 0x00000800 381 #define SI32_EMIFIF_A_IFRCST_WRRDH_SHIFT 11 382 // Set write signal (/WR) to low during the read data hold state. 383 #define SI32_EMIFIF_A_IFRCST_WRRDH_LOW_VALUE 0 384 #define SI32_EMIFIF_A_IFRCST_WRRDH_LOW_U32 \ 385 (SI32_EMIFIF_A_IFRCST_WRRDH_LOW_VALUE << SI32_EMIFIF_A_IFRCST_WRRDH_SHIFT) 386 // Set write signal (/WR) to high during the read data hold state. 387 #define SI32_EMIFIF_A_IFRCST_WRRDH_HIGH_VALUE 1 388 #define SI32_EMIFIF_A_IFRCST_WRRDH_HIGH_U32 \ 389 (SI32_EMIFIF_A_IFRCST_WRRDH_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_WRRDH_SHIFT) 390 391 #define SI32_EMIFIF_A_IFRCST_ALERAS_MASK 0x00001000 392 #define SI32_EMIFIF_A_IFRCST_ALERAS_SHIFT 12 393 // Set address latch enable (ALEm) to low during the read address setup state. 394 #define SI32_EMIFIF_A_IFRCST_ALERAS_LOW_VALUE 0 395 #define SI32_EMIFIF_A_IFRCST_ALERAS_LOW_U32 \ 396 (SI32_EMIFIF_A_IFRCST_ALERAS_LOW_VALUE << SI32_EMIFIF_A_IFRCST_ALERAS_SHIFT) 397 // Set address latch enable (ALEm) to high during the read address setup state. 398 #define SI32_EMIFIF_A_IFRCST_ALERAS_HIGH_VALUE 1 399 #define SI32_EMIFIF_A_IFRCST_ALERAS_HIGH_U32 \ 400 (SI32_EMIFIF_A_IFRCST_ALERAS_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_ALERAS_SHIFT) 401 402 #define SI32_EMIFIF_A_IFRCST_ALERAH_MASK 0x00002000 403 #define SI32_EMIFIF_A_IFRCST_ALERAH_SHIFT 13 404 // Set address latch enable (ALEm) to low during the read address hold state. 405 #define SI32_EMIFIF_A_IFRCST_ALERAH_LOW_VALUE 0 406 #define SI32_EMIFIF_A_IFRCST_ALERAH_LOW_U32 \ 407 (SI32_EMIFIF_A_IFRCST_ALERAH_LOW_VALUE << SI32_EMIFIF_A_IFRCST_ALERAH_SHIFT) 408 // Set address latch enable (ALEm) to high during the read address hold state. 409 #define SI32_EMIFIF_A_IFRCST_ALERAH_HIGH_VALUE 1 410 #define SI32_EMIFIF_A_IFRCST_ALERAH_HIGH_U32 \ 411 (SI32_EMIFIF_A_IFRCST_ALERAH_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_ALERAH_SHIFT) 412 413 #define SI32_EMIFIF_A_IFRCST_ALERDW_MASK 0x00004000 414 #define SI32_EMIFIF_A_IFRCST_ALERDW_SHIFT 14 415 // Set address latch enable (ALEm) to low during the read data wait state. 416 #define SI32_EMIFIF_A_IFRCST_ALERDW_LOW_VALUE 0 417 #define SI32_EMIFIF_A_IFRCST_ALERDW_LOW_U32 \ 418 (SI32_EMIFIF_A_IFRCST_ALERDW_LOW_VALUE << SI32_EMIFIF_A_IFRCST_ALERDW_SHIFT) 419 // Set address latch enable (ALEm) to high during the read data wait state. 420 #define SI32_EMIFIF_A_IFRCST_ALERDW_HIGH_VALUE 1 421 #define SI32_EMIFIF_A_IFRCST_ALERDW_HIGH_U32 \ 422 (SI32_EMIFIF_A_IFRCST_ALERDW_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_ALERDW_SHIFT) 423 424 #define SI32_EMIFIF_A_IFRCST_ALERDH_MASK 0x00008000 425 #define SI32_EMIFIF_A_IFRCST_ALERDH_SHIFT 15 426 // Set address latch enable (ALEm) to low during the read data hold state. 427 #define SI32_EMIFIF_A_IFRCST_ALERDH_LOW_VALUE 0 428 #define SI32_EMIFIF_A_IFRCST_ALERDH_LOW_U32 \ 429 (SI32_EMIFIF_A_IFRCST_ALERDH_LOW_VALUE << SI32_EMIFIF_A_IFRCST_ALERDH_SHIFT) 430 // Set address latch enable (ALEm) to high during the read data hold state. 431 #define SI32_EMIFIF_A_IFRCST_ALERDH_HIGH_VALUE 1 432 #define SI32_EMIFIF_A_IFRCST_ALERDH_HIGH_U32 \ 433 (SI32_EMIFIF_A_IFRCST_ALERDH_HIGH_VALUE << SI32_EMIFIF_A_IFRCST_ALERDH_SHIFT) 434 435 436 437 struct SI32_EMIFIF_A_IFWCST_Struct 438 { 439 union 440 { 441 struct 442 { 443 // Chip Select Write Address Setup State 444 volatile uint32_t CSWAS: 1; 445 // Chip Select Write Address Hold State 446 volatile uint32_t CSWAH: 1; 447 // Chip Select Write Data Wait State 448 volatile uint32_t CSWDW: 1; 449 // Chip Select Write Data Hold State 450 volatile uint32_t CSWDH: 1; 451 // Output Enable Write Address Setup State 452 volatile uint32_t OEWAS: 1; 453 // Output Enable Write Address Hold State 454 volatile uint32_t OEWAH: 1; 455 // Output Enable Write Data Wait State 456 volatile uint32_t OEWDW: 1; 457 // Output Enable Write Data Hold State 458 volatile uint32_t OEWDH: 1; 459 // Write Signal Write Address Setup State 460 volatile uint32_t WRWAS: 1; 461 // Write Signal Write Address Hold State 462 volatile uint32_t WRWAH: 1; 463 // Write Signal Write Data Wait State 464 volatile uint32_t WRWDW: 1; 465 // Write Signal Write Data Hold State 466 volatile uint32_t WRWDH: 1; 467 // Address Latch Enable Write Address Setup State 468 volatile uint32_t ALEWAS: 1; 469 // Address Latch Enable Write Address Hold State 470 volatile uint32_t ALEWAH: 1; 471 // Address Latch Enable Write Data Wait State 472 volatile uint32_t ALEWDW: 1; 473 // Address Latch Enable Write Data Hold State 474 volatile uint32_t ALEWDH: 1; 475 uint32_t reserved0: 16; 476 }; 477 volatile uint32_t U32; 478 }; 479 }; 480 481 #define SI32_EMIFIF_A_IFWCST_CSWAS_MASK 0x00000001 482 #define SI32_EMIFIF_A_IFWCST_CSWAS_SHIFT 0 483 // Set chip select (CSx) to low during the write address setup state. 484 #define SI32_EMIFIF_A_IFWCST_CSWAS_LOW_VALUE 0 485 #define SI32_EMIFIF_A_IFWCST_CSWAS_LOW_U32 \ 486 (SI32_EMIFIF_A_IFWCST_CSWAS_LOW_VALUE << SI32_EMIFIF_A_IFWCST_CSWAS_SHIFT) 487 // Set chip select (CSx) to high during the write address setup state. 488 #define SI32_EMIFIF_A_IFWCST_CSWAS_HIGH_VALUE 1 489 #define SI32_EMIFIF_A_IFWCST_CSWAS_HIGH_U32 \ 490 (SI32_EMIFIF_A_IFWCST_CSWAS_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_CSWAS_SHIFT) 491 492 #define SI32_EMIFIF_A_IFWCST_CSWAH_MASK 0x00000002 493 #define SI32_EMIFIF_A_IFWCST_CSWAH_SHIFT 1 494 // Set chip select (CSx) to low during the write address hold state. 495 #define SI32_EMIFIF_A_IFWCST_CSWAH_LOW_VALUE 0 496 #define SI32_EMIFIF_A_IFWCST_CSWAH_LOW_U32 \ 497 (SI32_EMIFIF_A_IFWCST_CSWAH_LOW_VALUE << SI32_EMIFIF_A_IFWCST_CSWAH_SHIFT) 498 // Set chip select (CSx) to high during the write address hold state. 499 #define SI32_EMIFIF_A_IFWCST_CSWAH_HIGH_VALUE 1 500 #define SI32_EMIFIF_A_IFWCST_CSWAH_HIGH_U32 \ 501 (SI32_EMIFIF_A_IFWCST_CSWAH_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_CSWAH_SHIFT) 502 503 #define SI32_EMIFIF_A_IFWCST_CSWDW_MASK 0x00000004 504 #define SI32_EMIFIF_A_IFWCST_CSWDW_SHIFT 2 505 // Set chip select (CSx) to low during the write data wait state. 506 #define SI32_EMIFIF_A_IFWCST_CSWDW_LOW_VALUE 0 507 #define SI32_EMIFIF_A_IFWCST_CSWDW_LOW_U32 \ 508 (SI32_EMIFIF_A_IFWCST_CSWDW_LOW_VALUE << SI32_EMIFIF_A_IFWCST_CSWDW_SHIFT) 509 // Set chip select (CSx) to high during the write data wait state. 510 #define SI32_EMIFIF_A_IFWCST_CSWDW_HIGH_VALUE 1 511 #define SI32_EMIFIF_A_IFWCST_CSWDW_HIGH_U32 \ 512 (SI32_EMIFIF_A_IFWCST_CSWDW_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_CSWDW_SHIFT) 513 514 #define SI32_EMIFIF_A_IFWCST_CSWDH_MASK 0x00000008 515 #define SI32_EMIFIF_A_IFWCST_CSWDH_SHIFT 3 516 // Set chip select (CSx) to low during the write data hold state. 517 #define SI32_EMIFIF_A_IFWCST_CSWDH_LOW_VALUE 0 518 #define SI32_EMIFIF_A_IFWCST_CSWDH_LOW_U32 \ 519 (SI32_EMIFIF_A_IFWCST_CSWDH_LOW_VALUE << SI32_EMIFIF_A_IFWCST_CSWDH_SHIFT) 520 // Set chip select (CSx) to high during the write data hold state. 521 #define SI32_EMIFIF_A_IFWCST_CSWDH_HIGH_VALUE 1 522 #define SI32_EMIFIF_A_IFWCST_CSWDH_HIGH_U32 \ 523 (SI32_EMIFIF_A_IFWCST_CSWDH_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_CSWDH_SHIFT) 524 525 #define SI32_EMIFIF_A_IFWCST_OEWAS_MASK 0x00000010 526 #define SI32_EMIFIF_A_IFWCST_OEWAS_SHIFT 4 527 // Set output enable (/OE) to low during the write address setup state. 528 #define SI32_EMIFIF_A_IFWCST_OEWAS_LOW_VALUE 0 529 #define SI32_EMIFIF_A_IFWCST_OEWAS_LOW_U32 \ 530 (SI32_EMIFIF_A_IFWCST_OEWAS_LOW_VALUE << SI32_EMIFIF_A_IFWCST_OEWAS_SHIFT) 531 // Set output enable (/OE) to high during the write address setup state. 532 #define SI32_EMIFIF_A_IFWCST_OEWAS_HIGH_VALUE 1 533 #define SI32_EMIFIF_A_IFWCST_OEWAS_HIGH_U32 \ 534 (SI32_EMIFIF_A_IFWCST_OEWAS_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_OEWAS_SHIFT) 535 536 #define SI32_EMIFIF_A_IFWCST_OEWAH_MASK 0x00000020 537 #define SI32_EMIFIF_A_IFWCST_OEWAH_SHIFT 5 538 // Set output enable (/OE) to low during the write address hold state. 539 #define SI32_EMIFIF_A_IFWCST_OEWAH_LOW_VALUE 0 540 #define SI32_EMIFIF_A_IFWCST_OEWAH_LOW_U32 \ 541 (SI32_EMIFIF_A_IFWCST_OEWAH_LOW_VALUE << SI32_EMIFIF_A_IFWCST_OEWAH_SHIFT) 542 // Set output enable (/OE) to high during the write address hold state. 543 #define SI32_EMIFIF_A_IFWCST_OEWAH_HIGH_VALUE 1 544 #define SI32_EMIFIF_A_IFWCST_OEWAH_HIGH_U32 \ 545 (SI32_EMIFIF_A_IFWCST_OEWAH_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_OEWAH_SHIFT) 546 547 #define SI32_EMIFIF_A_IFWCST_OEWDW_MASK 0x00000040 548 #define SI32_EMIFIF_A_IFWCST_OEWDW_SHIFT 6 549 // Set output enable (/OE) to low during the write data wait state. 550 #define SI32_EMIFIF_A_IFWCST_OEWDW_LOW_VALUE 0 551 #define SI32_EMIFIF_A_IFWCST_OEWDW_LOW_U32 \ 552 (SI32_EMIFIF_A_IFWCST_OEWDW_LOW_VALUE << SI32_EMIFIF_A_IFWCST_OEWDW_SHIFT) 553 // Set output enable (/OE) to high during the write data wait state. 554 #define SI32_EMIFIF_A_IFWCST_OEWDW_HIGH_VALUE 1 555 #define SI32_EMIFIF_A_IFWCST_OEWDW_HIGH_U32 \ 556 (SI32_EMIFIF_A_IFWCST_OEWDW_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_OEWDW_SHIFT) 557 558 #define SI32_EMIFIF_A_IFWCST_OEWDH_MASK 0x00000080 559 #define SI32_EMIFIF_A_IFWCST_OEWDH_SHIFT 7 560 // Set output enable (/OE) to low during the write data hold state. 561 #define SI32_EMIFIF_A_IFWCST_OEWDH_LOW_VALUE 0 562 #define SI32_EMIFIF_A_IFWCST_OEWDH_LOW_U32 \ 563 (SI32_EMIFIF_A_IFWCST_OEWDH_LOW_VALUE << SI32_EMIFIF_A_IFWCST_OEWDH_SHIFT) 564 // Set output enable (/OE) to high during the write data hold state. 565 #define SI32_EMIFIF_A_IFWCST_OEWDH_HIGH_VALUE 1 566 #define SI32_EMIFIF_A_IFWCST_OEWDH_HIGH_U32 \ 567 (SI32_EMIFIF_A_IFWCST_OEWDH_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_OEWDH_SHIFT) 568 569 #define SI32_EMIFIF_A_IFWCST_WRWAS_MASK 0x00000100 570 #define SI32_EMIFIF_A_IFWCST_WRWAS_SHIFT 8 571 // Set write signal (/WR) to low during the write address setup state. 572 #define SI32_EMIFIF_A_IFWCST_WRWAS_LOW_VALUE 0 573 #define SI32_EMIFIF_A_IFWCST_WRWAS_LOW_U32 \ 574 (SI32_EMIFIF_A_IFWCST_WRWAS_LOW_VALUE << SI32_EMIFIF_A_IFWCST_WRWAS_SHIFT) 575 // Set write signal (/WR) to high during the write address setup state. 576 #define SI32_EMIFIF_A_IFWCST_WRWAS_HIGH_VALUE 1 577 #define SI32_EMIFIF_A_IFWCST_WRWAS_HIGH_U32 \ 578 (SI32_EMIFIF_A_IFWCST_WRWAS_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_WRWAS_SHIFT) 579 580 #define SI32_EMIFIF_A_IFWCST_WRWAH_MASK 0x00000200 581 #define SI32_EMIFIF_A_IFWCST_WRWAH_SHIFT 9 582 // Set write signal (/WR) to low during the write address hold state. 583 #define SI32_EMIFIF_A_IFWCST_WRWAH_LOW_VALUE 0 584 #define SI32_EMIFIF_A_IFWCST_WRWAH_LOW_U32 \ 585 (SI32_EMIFIF_A_IFWCST_WRWAH_LOW_VALUE << SI32_EMIFIF_A_IFWCST_WRWAH_SHIFT) 586 // Set write signal (/WR) to high during the write address hold state. 587 #define SI32_EMIFIF_A_IFWCST_WRWAH_HIGH_VALUE 1 588 #define SI32_EMIFIF_A_IFWCST_WRWAH_HIGH_U32 \ 589 (SI32_EMIFIF_A_IFWCST_WRWAH_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_WRWAH_SHIFT) 590 591 #define SI32_EMIFIF_A_IFWCST_WRWDW_MASK 0x00000400 592 #define SI32_EMIFIF_A_IFWCST_WRWDW_SHIFT 10 593 // Set write signal (/WR) to low during the write data wait state. 594 #define SI32_EMIFIF_A_IFWCST_WRWDW_LOW_VALUE 0 595 #define SI32_EMIFIF_A_IFWCST_WRWDW_LOW_U32 \ 596 (SI32_EMIFIF_A_IFWCST_WRWDW_LOW_VALUE << SI32_EMIFIF_A_IFWCST_WRWDW_SHIFT) 597 // Set write signal (/WR) to high during the write data wait state. 598 #define SI32_EMIFIF_A_IFWCST_WRWDW_HIGH_VALUE 1 599 #define SI32_EMIFIF_A_IFWCST_WRWDW_HIGH_U32 \ 600 (SI32_EMIFIF_A_IFWCST_WRWDW_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_WRWDW_SHIFT) 601 602 #define SI32_EMIFIF_A_IFWCST_WRWDH_MASK 0x00000800 603 #define SI32_EMIFIF_A_IFWCST_WRWDH_SHIFT 11 604 // Set write signal (/WR) to low during the write data hold state. 605 #define SI32_EMIFIF_A_IFWCST_WRWDH_LOW_VALUE 0 606 #define SI32_EMIFIF_A_IFWCST_WRWDH_LOW_U32 \ 607 (SI32_EMIFIF_A_IFWCST_WRWDH_LOW_VALUE << SI32_EMIFIF_A_IFWCST_WRWDH_SHIFT) 608 // Set write signal (/WR) to high during the write data hold state. 609 #define SI32_EMIFIF_A_IFWCST_WRWDH_HIGH_VALUE 1 610 #define SI32_EMIFIF_A_IFWCST_WRWDH_HIGH_U32 \ 611 (SI32_EMIFIF_A_IFWCST_WRWDH_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_WRWDH_SHIFT) 612 613 #define SI32_EMIFIF_A_IFWCST_ALEWAS_MASK 0x00001000 614 #define SI32_EMIFIF_A_IFWCST_ALEWAS_SHIFT 12 615 // Set address latch enable (ALEm) to low during the write address setup state. 616 #define SI32_EMIFIF_A_IFWCST_ALEWAS_LOW_VALUE 0 617 #define SI32_EMIFIF_A_IFWCST_ALEWAS_LOW_U32 \ 618 (SI32_EMIFIF_A_IFWCST_ALEWAS_LOW_VALUE << SI32_EMIFIF_A_IFWCST_ALEWAS_SHIFT) 619 // Set address latch enable (ALEm) to high during the write address setup state. 620 #define SI32_EMIFIF_A_IFWCST_ALEWAS_HIGH_VALUE 1 621 #define SI32_EMIFIF_A_IFWCST_ALEWAS_HIGH_U32 \ 622 (SI32_EMIFIF_A_IFWCST_ALEWAS_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_ALEWAS_SHIFT) 623 624 #define SI32_EMIFIF_A_IFWCST_ALEWAH_MASK 0x00002000 625 #define SI32_EMIFIF_A_IFWCST_ALEWAH_SHIFT 13 626 // Set address latch enable (ALEm) to low during the write address hold state. 627 #define SI32_EMIFIF_A_IFWCST_ALEWAH_LOW_VALUE 0 628 #define SI32_EMIFIF_A_IFWCST_ALEWAH_LOW_U32 \ 629 (SI32_EMIFIF_A_IFWCST_ALEWAH_LOW_VALUE << SI32_EMIFIF_A_IFWCST_ALEWAH_SHIFT) 630 // Set address latch enable (ALEm) to high during the write address hold state. 631 #define SI32_EMIFIF_A_IFWCST_ALEWAH_HIGH_VALUE 1 632 #define SI32_EMIFIF_A_IFWCST_ALEWAH_HIGH_U32 \ 633 (SI32_EMIFIF_A_IFWCST_ALEWAH_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_ALEWAH_SHIFT) 634 635 #define SI32_EMIFIF_A_IFWCST_ALEWDW_MASK 0x00004000 636 #define SI32_EMIFIF_A_IFWCST_ALEWDW_SHIFT 14 637 // Set address latch enable (ALEm) to low during the write data wait state. 638 #define SI32_EMIFIF_A_IFWCST_ALEWDW_LOW_VALUE 0 639 #define SI32_EMIFIF_A_IFWCST_ALEWDW_LOW_U32 \ 640 (SI32_EMIFIF_A_IFWCST_ALEWDW_LOW_VALUE << SI32_EMIFIF_A_IFWCST_ALEWDW_SHIFT) 641 // Set address latch enable (ALEm) to high during the write data wait state. 642 #define SI32_EMIFIF_A_IFWCST_ALEWDW_HIGH_VALUE 1 643 #define SI32_EMIFIF_A_IFWCST_ALEWDW_HIGH_U32 \ 644 (SI32_EMIFIF_A_IFWCST_ALEWDW_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_ALEWDW_SHIFT) 645 646 #define SI32_EMIFIF_A_IFWCST_ALEWDH_MASK 0x00008000 647 #define SI32_EMIFIF_A_IFWCST_ALEWDH_SHIFT 15 648 // Set address latch enable (ALEm) to low during the write data hold state. 649 #define SI32_EMIFIF_A_IFWCST_ALEWDH_LOW_VALUE 0 650 #define SI32_EMIFIF_A_IFWCST_ALEWDH_LOW_U32 \ 651 (SI32_EMIFIF_A_IFWCST_ALEWDH_LOW_VALUE << SI32_EMIFIF_A_IFWCST_ALEWDH_SHIFT) 652 // Set address latch enable (ALEm) to high during the write data hold state. 653 #define SI32_EMIFIF_A_IFWCST_ALEWDH_HIGH_VALUE 1 654 #define SI32_EMIFIF_A_IFWCST_ALEWDH_HIGH_U32 \ 655 (SI32_EMIFIF_A_IFWCST_ALEWDH_HIGH_VALUE << SI32_EMIFIF_A_IFWCST_ALEWDH_SHIFT) 656 657 658 659 typedef struct SI32_EMIFIF_A_Struct 660 { 661 struct SI32_EMIFIF_A_CONFIG_Struct CONFIG ; // Base Address + 0x0 662 volatile uint32_t CONFIG_SET; 663 volatile uint32_t CONFIG_CLR; 664 uint32_t reserved0; 665 struct SI32_EMIFIF_A_IFRT_Struct IFRT ; // Base Address + 0x10 666 uint32_t reserved1; 667 uint32_t reserved2; 668 uint32_t reserved3; 669 struct SI32_EMIFIF_A_IFWT_Struct IFWT ; // Base Address + 0x20 670 uint32_t reserved4; 671 uint32_t reserved5; 672 uint32_t reserved6; 673 struct SI32_EMIFIF_A_IFRCST_Struct IFRCST ; // Base Address + 0x30 674 uint32_t reserved7; 675 uint32_t reserved8; 676 uint32_t reserved9; 677 struct SI32_EMIFIF_A_IFWCST_Struct IFWCST ; // Base Address + 0x40 678 uint32_t reserved10; 679 uint32_t reserved11; 680 uint32_t reserved12; 681 } SI32_EMIFIF_A_Type; 682 683 #ifdef __cplusplus 684 } 685 #endif 686 687 #endif // __SI32_EMIFIF_A_REGISTERS_H__ 688 689 //-eof-------------------------------------------------------------------------- 690 691
