1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_CAPSENSE_A_REGISTERS_H__ 27 #define __SI32_CAPSENSE_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_CAPSENSE_A_CONTROL_Struct 36 { 37 union 38 { 39 struct 40 { 41 // Start and Busy Flag 42 volatile uint32_t BUSYF: 1; 43 // Module Enable 44 volatile uint32_t CSEN: 1; 45 // Bias Enable 46 volatile uint32_t BIASEN: 1; 47 // Digital Comparator Polarity Select 48 volatile uint32_t CMPPOL: 1; 49 // Conversion Mode Select 50 volatile uint32_t CMD: 2; 51 // Conversion Rate 52 volatile uint32_t CNVR: 2; 53 // Accumulator Mode Select 54 volatile uint32_t ACCMD: 3; 55 // Multiple Channel Enable 56 volatile uint32_t MCEN: 1; 57 // Start of Conversion Mode Select 58 volatile uint32_t CSCM: 4; 59 // Pin Monitor Mode 60 volatile uint32_t PMMD: 2; 61 // Pin Monitor Event Flag 62 volatile uint32_t PMEF: 1; 63 uint32_t reserved0: 1; 64 // Threshold Comparator Enable 65 volatile uint32_t CMPEN: 1; 66 // Conversion Done Interrupt Enable 67 volatile uint32_t CDIEN: 1; 68 // End-of-Scan Interrupt Enable 69 volatile uint32_t EOSIEN: 1; 70 uint32_t reserved1: 1; 71 // Threshold Comparator Interrupt Flag 72 volatile uint32_t CMPI: 1; 73 // Conversion Done Interrupt Flag 74 volatile uint32_t CDI: 1; 75 // End-of-Scan Interrupt Flag 76 volatile uint32_t EOSI: 1; 77 uint32_t reserved2: 5; 78 }; 79 volatile uint32_t U32; 80 }; 81 }; 82 83 #define SI32_CAPSENSE_A_CONTROL_BUSYF_MASK 0x00000001 84 #define SI32_CAPSENSE_A_CONTROL_BUSYF_SHIFT 0 85 // Read: A capacitive sensing conversion is complete or a conversion is not 86 // currently in progress. Write: No effect. 87 #define SI32_CAPSENSE_A_CONTROL_BUSYF_IDLE_VALUE 0 88 #define SI32_CAPSENSE_A_CONTROL_BUSYF_IDLE_U32 \ 89 (SI32_CAPSENSE_A_CONTROL_BUSYF_IDLE_VALUE << SI32_CAPSENSE_A_CONTROL_BUSYF_SHIFT) 90 // Read: A capacitive sensing conversion is in progress. Write: Initiate a 91 // capacitive sensing conversion if BUSYF is selected as the start of conversion 92 // source. 93 #define SI32_CAPSENSE_A_CONTROL_BUSYF_BUSY_VALUE 1 94 #define SI32_CAPSENSE_A_CONTROL_BUSYF_BUSY_U32 \ 95 (SI32_CAPSENSE_A_CONTROL_BUSYF_BUSY_VALUE << SI32_CAPSENSE_A_CONTROL_BUSYF_SHIFT) 96 97 #define SI32_CAPSENSE_A_CONTROL_CSEN_MASK 0x00000002 98 #define SI32_CAPSENSE_A_CONTROL_CSEN_SHIFT 1 99 // Disable the capacitive sensing module. 100 #define SI32_CAPSENSE_A_CONTROL_CSEN_DISABLED_VALUE 0 101 #define SI32_CAPSENSE_A_CONTROL_CSEN_DISABLED_U32 \ 102 (SI32_CAPSENSE_A_CONTROL_CSEN_DISABLED_VALUE << SI32_CAPSENSE_A_CONTROL_CSEN_SHIFT) 103 // Enable the capacitive sensing module. 104 #define SI32_CAPSENSE_A_CONTROL_CSEN_ENABLED_VALUE 1 105 #define SI32_CAPSENSE_A_CONTROL_CSEN_ENABLED_U32 \ 106 (SI32_CAPSENSE_A_CONTROL_CSEN_ENABLED_VALUE << SI32_CAPSENSE_A_CONTROL_CSEN_SHIFT) 107 108 #define SI32_CAPSENSE_A_CONTROL_BIASEN_MASK 0x00000004 109 #define SI32_CAPSENSE_A_CONTROL_BIASEN_SHIFT 2 110 // Disable the bias. 111 #define SI32_CAPSENSE_A_CONTROL_BIASEN_DISABLED_VALUE 0 112 #define SI32_CAPSENSE_A_CONTROL_BIASEN_DISABLED_U32 \ 113 (SI32_CAPSENSE_A_CONTROL_BIASEN_DISABLED_VALUE << SI32_CAPSENSE_A_CONTROL_BIASEN_SHIFT) 114 // Enable the bias. 115 #define SI32_CAPSENSE_A_CONTROL_BIASEN_ENABLED_VALUE 1 116 #define SI32_CAPSENSE_A_CONTROL_BIASEN_ENABLED_U32 \ 117 (SI32_CAPSENSE_A_CONTROL_BIASEN_ENABLED_VALUE << SI32_CAPSENSE_A_CONTROL_BIASEN_SHIFT) 118 119 #define SI32_CAPSENSE_A_CONTROL_CMPPOL_MASK 0x00000008 120 #define SI32_CAPSENSE_A_CONTROL_CMPPOL_SHIFT 3 121 // The digital comparator generates an interrupt if the conversion is greater than 122 // the CSTH threshold. 123 #define SI32_CAPSENSE_A_CONTROL_CMPPOL_GT_VALUE 0 124 #define SI32_CAPSENSE_A_CONTROL_CMPPOL_GT_U32 \ 125 (SI32_CAPSENSE_A_CONTROL_CMPPOL_GT_VALUE << SI32_CAPSENSE_A_CONTROL_CMPPOL_SHIFT) 126 // The digital comparator generates an interrupt if the conversion is less than or 127 // equal to the CSTH threshold. 128 #define SI32_CAPSENSE_A_CONTROL_CMPPOL_LTE_VALUE 1 129 #define SI32_CAPSENSE_A_CONTROL_CMPPOL_LTE_U32 \ 130 (SI32_CAPSENSE_A_CONTROL_CMPPOL_LTE_VALUE << SI32_CAPSENSE_A_CONTROL_CMPPOL_SHIFT) 131 132 #define SI32_CAPSENSE_A_CONTROL_CMD_MASK 0x00000030 133 #define SI32_CAPSENSE_A_CONTROL_CMD_SHIFT 4 134 // Single Conversion Mode: One conversion occurs on a single channel. 135 #define SI32_CAPSENSE_A_CONTROL_CMD_SINGLE_VALUE 0 136 #define SI32_CAPSENSE_A_CONTROL_CMD_SINGLE_U32 \ 137 (SI32_CAPSENSE_A_CONTROL_CMD_SINGLE_VALUE << SI32_CAPSENSE_A_CONTROL_CMD_SHIFT) 138 // Single Scan Mode: One conversion on each channel selected by SCANEN occurs. An 139 // end-of-scan interrupt indicates all channels have been measured. 140 #define SI32_CAPSENSE_A_CONTROL_CMD_SCAN_VALUE 1 141 #define SI32_CAPSENSE_A_CONTROL_CMD_SCAN_U32 \ 142 (SI32_CAPSENSE_A_CONTROL_CMD_SCAN_VALUE << SI32_CAPSENSE_A_CONTROL_CMD_SHIFT) 143 // Continuous Single Conversion Mode: Continuously converts on a single channel. 144 // This operation ends only if the module is disabled (CSEN = 0) or if a compare 145 // threshold event occurs (CMPI = 1). 146 #define SI32_CAPSENSE_A_CONTROL_CMD_CONT_SINGLE_VALUE 2 147 #define SI32_CAPSENSE_A_CONTROL_CMD_CONT_SINGLE_U32 \ 148 (SI32_CAPSENSE_A_CONTROL_CMD_CONT_SINGLE_VALUE << SI32_CAPSENSE_A_CONTROL_CMD_SHIFT) 149 // Continuous Scan Mode: Continuously loops through and converts on all the 150 // channels selected by SCANEN. This operation ends only if the module is disabled 151 // (CSEN = 0) or if a compare threshold event occurs (CMPI = 1). 152 #define SI32_CAPSENSE_A_CONTROL_CMD_CONT_SCAN_VALUE 3 153 #define SI32_CAPSENSE_A_CONTROL_CMD_CONT_SCAN_U32 \ 154 (SI32_CAPSENSE_A_CONTROL_CMD_CONT_SCAN_VALUE << SI32_CAPSENSE_A_CONTROL_CMD_SHIFT) 155 156 #define SI32_CAPSENSE_A_CONTROL_CNVR_MASK 0x000000C0 157 #define SI32_CAPSENSE_A_CONTROL_CNVR_SHIFT 6 158 // Conversions last 12 internal CAPSENSE clocks and results are 12 bits in length. 159 #define SI32_CAPSENSE_A_CONTROL_CNVR_12BIT_VALUE 0 160 #define SI32_CAPSENSE_A_CONTROL_CNVR_12BIT_U32 \ 161 (SI32_CAPSENSE_A_CONTROL_CNVR_12BIT_VALUE << SI32_CAPSENSE_A_CONTROL_CNVR_SHIFT) 162 // Conversions last 13 internal CAPSENSE clocks and results are 13 bits in length. 163 #define SI32_CAPSENSE_A_CONTROL_CNVR_13BIT_VALUE 1 164 #define SI32_CAPSENSE_A_CONTROL_CNVR_13BIT_U32 \ 165 (SI32_CAPSENSE_A_CONTROL_CNVR_13BIT_VALUE << SI32_CAPSENSE_A_CONTROL_CNVR_SHIFT) 166 // Conversions last 14 internal CAPSENSE clocks and results are 14 bits in length. 167 #define SI32_CAPSENSE_A_CONTROL_CNVR_14BIT_VALUE 2 168 #define SI32_CAPSENSE_A_CONTROL_CNVR_14BIT_U32 \ 169 (SI32_CAPSENSE_A_CONTROL_CNVR_14BIT_VALUE << SI32_CAPSENSE_A_CONTROL_CNVR_SHIFT) 170 // Conversions last 16 internal CAPSENSE clocks and results are 16 bits in length. 171 #define SI32_CAPSENSE_A_CONTROL_CNVR_16BIT_VALUE 3 172 #define SI32_CAPSENSE_A_CONTROL_CNVR_16BIT_U32 \ 173 (SI32_CAPSENSE_A_CONTROL_CNVR_16BIT_VALUE << SI32_CAPSENSE_A_CONTROL_CNVR_SHIFT) 174 175 #define SI32_CAPSENSE_A_CONTROL_ACCMD_MASK 0x00000700 176 #define SI32_CAPSENSE_A_CONTROL_ACCMD_SHIFT 8 177 // Accumulate 1 sample. 178 #define SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_1_VALUE 0 179 #define SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_1_U32 \ 180 (SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_1_VALUE << SI32_CAPSENSE_A_CONTROL_ACCMD_SHIFT) 181 // Accumulate 4 samples. 182 #define SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_4_VALUE 1 183 #define SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_4_U32 \ 184 (SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_4_VALUE << SI32_CAPSENSE_A_CONTROL_ACCMD_SHIFT) 185 // Accumulate 8 samples. 186 #define SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_8_VALUE 2 187 #define SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_8_U32 \ 188 (SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_8_VALUE << SI32_CAPSENSE_A_CONTROL_ACCMD_SHIFT) 189 // Accumulate 16 samples. 190 #define SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_16_VALUE 3 191 #define SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_16_U32 \ 192 (SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_16_VALUE << SI32_CAPSENSE_A_CONTROL_ACCMD_SHIFT) 193 // Accumulate 32 samples. 194 #define SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_32_VALUE 4 195 #define SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_32_U32 \ 196 (SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_32_VALUE << SI32_CAPSENSE_A_CONTROL_ACCMD_SHIFT) 197 // Accumulate 64 samples. 198 #define SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_64_VALUE 5 199 #define SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_64_U32 \ 200 (SI32_CAPSENSE_A_CONTROL_ACCMD_ACC_64_VALUE << SI32_CAPSENSE_A_CONTROL_ACCMD_SHIFT) 201 202 #define SI32_CAPSENSE_A_CONTROL_MCEN_MASK 0x00000800 203 #define SI32_CAPSENSE_A_CONTROL_MCEN_SHIFT 11 204 // Disable the multiple channel measurement feature. 205 #define SI32_CAPSENSE_A_CONTROL_MCEN_DISABLED_VALUE 0 206 #define SI32_CAPSENSE_A_CONTROL_MCEN_DISABLED_U32 \ 207 (SI32_CAPSENSE_A_CONTROL_MCEN_DISABLED_VALUE << SI32_CAPSENSE_A_CONTROL_MCEN_SHIFT) 208 // Enable the multiple channel measurement feature. 209 #define SI32_CAPSENSE_A_CONTROL_MCEN_ENABLED_VALUE 1 210 #define SI32_CAPSENSE_A_CONTROL_MCEN_ENABLED_U32 \ 211 (SI32_CAPSENSE_A_CONTROL_MCEN_ENABLED_VALUE << SI32_CAPSENSE_A_CONTROL_MCEN_SHIFT) 212 213 #define SI32_CAPSENSE_A_CONTROL_CSCM_MASK 0x0000F000 214 #define SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT 12 215 // The CSnT0 trigger source starts conversions. 216 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT0_VALUE 0 217 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT0_U32 \ 218 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT0_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 219 // The CSnT1 trigger source starts conversions. 220 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT1_VALUE 1 221 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT1_U32 \ 222 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT1_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 223 // The CSnT2 trigger source starts conversions. 224 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT2_VALUE 2 225 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT2_U32 \ 226 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT2_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 227 // The CSnT3 trigger source starts conversions. 228 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT3_VALUE 3 229 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT3_U32 \ 230 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT3_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 231 // The CSnT4 trigger source starts conversions. 232 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT4_VALUE 4 233 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT4_U32 \ 234 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT4_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 235 // The CSnT5 trigger source starts conversions. 236 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT5_VALUE 5 237 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT5_U32 \ 238 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT5_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 239 // The CSnT6 trigger source starts conversions. 240 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT6_VALUE 6 241 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT6_U32 \ 242 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT6_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 243 // The CSnT7 trigger source starts conversions. 244 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT7_VALUE 7 245 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT7_U32 \ 246 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT7_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 247 // The CSnT8 trigger source starts conversions. 248 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT8_VALUE 8 249 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT8_U32 \ 250 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT8_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 251 // The CSnT9 trigger source starts conversions. 252 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT9_VALUE 9 253 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT9_U32 \ 254 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT9_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 255 // The CSnT10 trigger source starts conversions. 256 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT10_VALUE 10 257 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT10_U32 \ 258 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT10_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 259 // The CSnT11 trigger source starts conversions. 260 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT11_VALUE 11 261 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT11_U32 \ 262 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT11_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 263 // The CSnT12 trigger source starts conversions. 264 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT12_VALUE 12 265 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT12_U32 \ 266 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT12_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 267 // The CSnT13 trigger source starts conversions. 268 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT13_VALUE 13 269 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT13_U32 \ 270 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT13_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 271 // The CSnT14 trigger source starts conversions. 272 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT14_VALUE 14 273 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT14_U32 \ 274 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT14_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 275 // The CSnT15 trigger source starts conversions. 276 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT15_VALUE 15 277 #define SI32_CAPSENSE_A_CONTROL_CSCM_CSNT15_U32 \ 278 (SI32_CAPSENSE_A_CONTROL_CSCM_CSNT15_VALUE << SI32_CAPSENSE_A_CONTROL_CSCM_SHIFT) 279 280 #define SI32_CAPSENSE_A_CONTROL_PMMD_MASK 0x00030000 281 #define SI32_CAPSENSE_A_CONTROL_PMMD_SHIFT 16 282 // Always retry on a pin state change. 283 #define SI32_CAPSENSE_A_CONTROL_PMMD_ALWAYS_RETRY_VALUE 0 284 #define SI32_CAPSENSE_A_CONTROL_PMMD_ALWAYS_RETRY_U32 \ 285 (SI32_CAPSENSE_A_CONTROL_PMMD_ALWAYS_RETRY_VALUE << SI32_CAPSENSE_A_CONTROL_PMMD_SHIFT) 286 // Retry up to twice on consecutive bit cycles. 287 #define SI32_CAPSENSE_A_CONTROL_PMMD_RETRY_TWICE_VALUE 1 288 #define SI32_CAPSENSE_A_CONTROL_PMMD_RETRY_TWICE_U32 \ 289 (SI32_CAPSENSE_A_CONTROL_PMMD_RETRY_TWICE_VALUE << SI32_CAPSENSE_A_CONTROL_PMMD_SHIFT) 290 // Retry up to four times on consecutive bit cycles. 291 #define SI32_CAPSENSE_A_CONTROL_PMMD_RETRY_FOUR_TIMES_VALUE 2 292 #define SI32_CAPSENSE_A_CONTROL_PMMD_RETRY_FOUR_TIMES_U32 \ 293 (SI32_CAPSENSE_A_CONTROL_PMMD_RETRY_FOUR_TIMES_VALUE << SI32_CAPSENSE_A_CONTROL_PMMD_SHIFT) 294 // Ignore monitored signal state change. 295 #define SI32_CAPSENSE_A_CONTROL_PMMD_DO_NOT_RETRY_VALUE 3 296 #define SI32_CAPSENSE_A_CONTROL_PMMD_DO_NOT_RETRY_U32 \ 297 (SI32_CAPSENSE_A_CONTROL_PMMD_DO_NOT_RETRY_VALUE << SI32_CAPSENSE_A_CONTROL_PMMD_SHIFT) 298 299 #define SI32_CAPSENSE_A_CONTROL_PMEF_MASK 0x00040000 300 #define SI32_CAPSENSE_A_CONTROL_PMEF_SHIFT 18 301 // A retry did not occur due to a pin monitor event during the last conversion. 302 #define SI32_CAPSENSE_A_CONTROL_PMEF_NOT_SET_VALUE 0 303 #define SI32_CAPSENSE_A_CONTROL_PMEF_NOT_SET_U32 \ 304 (SI32_CAPSENSE_A_CONTROL_PMEF_NOT_SET_VALUE << SI32_CAPSENSE_A_CONTROL_PMEF_SHIFT) 305 // A retry occurred due to a pin monitor event during the last conversion. 306 #define SI32_CAPSENSE_A_CONTROL_PMEF_SET_VALUE 1 307 #define SI32_CAPSENSE_A_CONTROL_PMEF_SET_U32 \ 308 (SI32_CAPSENSE_A_CONTROL_PMEF_SET_VALUE << SI32_CAPSENSE_A_CONTROL_PMEF_SHIFT) 309 310 #define SI32_CAPSENSE_A_CONTROL_CMPEN_MASK 0x00100000 311 #define SI32_CAPSENSE_A_CONTROL_CMPEN_SHIFT 20 312 // Disable the threshold comparator. 313 #define SI32_CAPSENSE_A_CONTROL_CMPEN_DISABLED_VALUE 0 314 #define SI32_CAPSENSE_A_CONTROL_CMPEN_DISABLED_U32 \ 315 (SI32_CAPSENSE_A_CONTROL_CMPEN_DISABLED_VALUE << SI32_CAPSENSE_A_CONTROL_CMPEN_SHIFT) 316 // Enable the threshold comparator. 317 #define SI32_CAPSENSE_A_CONTROL_CMPEN_ENABLED_VALUE 1 318 #define SI32_CAPSENSE_A_CONTROL_CMPEN_ENABLED_U32 \ 319 (SI32_CAPSENSE_A_CONTROL_CMPEN_ENABLED_VALUE << SI32_CAPSENSE_A_CONTROL_CMPEN_SHIFT) 320 321 #define SI32_CAPSENSE_A_CONTROL_CDIEN_MASK 0x00200000 322 #define SI32_CAPSENSE_A_CONTROL_CDIEN_SHIFT 21 323 // Disable the single conversion done interrupt. 324 #define SI32_CAPSENSE_A_CONTROL_CDIEN_DISABLED_VALUE 0 325 #define SI32_CAPSENSE_A_CONTROL_CDIEN_DISABLED_U32 \ 326 (SI32_CAPSENSE_A_CONTROL_CDIEN_DISABLED_VALUE << SI32_CAPSENSE_A_CONTROL_CDIEN_SHIFT) 327 // Enable the single conversion done interrupt. 328 #define SI32_CAPSENSE_A_CONTROL_CDIEN_ENABLED_VALUE 1 329 #define SI32_CAPSENSE_A_CONTROL_CDIEN_ENABLED_U32 \ 330 (SI32_CAPSENSE_A_CONTROL_CDIEN_ENABLED_VALUE << SI32_CAPSENSE_A_CONTROL_CDIEN_SHIFT) 331 332 #define SI32_CAPSENSE_A_CONTROL_EOSIEN_MASK 0x00400000 333 #define SI32_CAPSENSE_A_CONTROL_EOSIEN_SHIFT 22 334 // Disable the single scan end-of-scan interrupt. 335 #define SI32_CAPSENSE_A_CONTROL_EOSIEN_DISABLED_VALUE 0 336 #define SI32_CAPSENSE_A_CONTROL_EOSIEN_DISABLED_U32 \ 337 (SI32_CAPSENSE_A_CONTROL_EOSIEN_DISABLED_VALUE << SI32_CAPSENSE_A_CONTROL_EOSIEN_SHIFT) 338 // Enable the single scan end-of-scan interrupt. 339 #define SI32_CAPSENSE_A_CONTROL_EOSIEN_ENABLED_VALUE 1 340 #define SI32_CAPSENSE_A_CONTROL_EOSIEN_ENABLED_U32 \ 341 (SI32_CAPSENSE_A_CONTROL_EOSIEN_ENABLED_VALUE << SI32_CAPSENSE_A_CONTROL_EOSIEN_SHIFT) 342 343 #define SI32_CAPSENSE_A_CONTROL_CMPI_MASK 0x01000000 344 #define SI32_CAPSENSE_A_CONTROL_CMPI_SHIFT 24 345 // The capacitive sensing result did not cause a compare threshold interrupt. 346 #define SI32_CAPSENSE_A_CONTROL_CMPI_NOT_SET_VALUE 0 347 #define SI32_CAPSENSE_A_CONTROL_CMPI_NOT_SET_U32 \ 348 (SI32_CAPSENSE_A_CONTROL_CMPI_NOT_SET_VALUE << SI32_CAPSENSE_A_CONTROL_CMPI_SHIFT) 349 // The capacitive sensing result caused a compare threshold interrupt. 350 #define SI32_CAPSENSE_A_CONTROL_CMPI_SET_VALUE 1 351 #define SI32_CAPSENSE_A_CONTROL_CMPI_SET_U32 \ 352 (SI32_CAPSENSE_A_CONTROL_CMPI_SET_VALUE << SI32_CAPSENSE_A_CONTROL_CMPI_SHIFT) 353 354 #define SI32_CAPSENSE_A_CONTROL_CDI_MASK 0x02000000 355 #define SI32_CAPSENSE_A_CONTROL_CDI_SHIFT 25 356 // Read: The CAPSENSEn module has not completed a data conversion since the last 357 // time CDI was cleared. Write: Clear the interrupt. 358 #define SI32_CAPSENSE_A_CONTROL_CDI_NOT_SET_VALUE 0 359 #define SI32_CAPSENSE_A_CONTROL_CDI_NOT_SET_U32 \ 360 (SI32_CAPSENSE_A_CONTROL_CDI_NOT_SET_VALUE << SI32_CAPSENSE_A_CONTROL_CDI_SHIFT) 361 // Read: The CAPSENSEn module completed a data conversion. Write: Force a 362 // conversion complete interrupt. 363 #define SI32_CAPSENSE_A_CONTROL_CDI_SET_VALUE 1 364 #define SI32_CAPSENSE_A_CONTROL_CDI_SET_U32 \ 365 (SI32_CAPSENSE_A_CONTROL_CDI_SET_VALUE << SI32_CAPSENSE_A_CONTROL_CDI_SHIFT) 366 367 #define SI32_CAPSENSE_A_CONTROL_EOSI_MASK 0x04000000 368 #define SI32_CAPSENSE_A_CONTROL_EOSI_SHIFT 26 369 // The CAPSENSEn module has not completed a scan since the last time EOSI was 370 // cleared. 371 #define SI32_CAPSENSE_A_CONTROL_EOSI_NOT_SET_VALUE 0 372 #define SI32_CAPSENSE_A_CONTROL_EOSI_NOT_SET_U32 \ 373 (SI32_CAPSENSE_A_CONTROL_EOSI_NOT_SET_VALUE << SI32_CAPSENSE_A_CONTROL_EOSI_SHIFT) 374 // The CAPSENSEn module completed a scan. 375 #define SI32_CAPSENSE_A_CONTROL_EOSI_SET_VALUE 1 376 #define SI32_CAPSENSE_A_CONTROL_EOSI_SET_U32 \ 377 (SI32_CAPSENSE_A_CONTROL_EOSI_SET_VALUE << SI32_CAPSENSE_A_CONTROL_EOSI_SHIFT) 378 379 380 381 struct SI32_CAPSENSE_A_MODE_Struct 382 { 383 union 384 { 385 struct 386 { 387 // Capacitance Gain Select 388 volatile uint32_t CGSEL: 3; 389 uint32_t reserved0: 3; 390 // Ramp Selection 391 volatile uint32_t RAMPSEL: 2; 392 // Output Current Select 393 volatile uint32_t IASEL: 3; 394 uint32_t reserved1: 1; 395 // Discharge Time Select 396 volatile uint32_t DTSEL: 3; 397 uint32_t reserved2: 17; 398 }; 399 volatile uint32_t U32; 400 }; 401 }; 402 403 #define SI32_CAPSENSE_A_MODE_CGSEL_MASK 0x00000007 404 #define SI32_CAPSENSE_A_MODE_CGSEL_SHIFT 0 405 406 #define SI32_CAPSENSE_A_MODE_RAMPSEL_MASK 0x000000C0 407 #define SI32_CAPSENSE_A_MODE_RAMPSEL_SHIFT 6 408 409 #define SI32_CAPSENSE_A_MODE_IASEL_MASK 0x00000700 410 #define SI32_CAPSENSE_A_MODE_IASEL_SHIFT 8 411 412 #define SI32_CAPSENSE_A_MODE_DTSEL_MASK 0x00007000 413 #define SI32_CAPSENSE_A_MODE_DTSEL_SHIFT 12 414 415 416 417 struct SI32_CAPSENSE_A_DATA_Struct 418 { 419 union 420 { 421 struct 422 { 423 // Capacitive Sensing Data 424 volatile uint16_t DATA_BITS; 425 uint32_t reserved0: 16; 426 }; 427 volatile uint32_t U32; 428 }; 429 }; 430 431 #define SI32_CAPSENSE_A_DATA_DATA_MASK 0x0000FFFF 432 #define SI32_CAPSENSE_A_DATA_DATA_SHIFT 0 433 434 435 436 struct SI32_CAPSENSE_A_SCAN_Struct 437 { 438 union 439 { 440 struct 441 { 442 // Channel Scan Enable 443 volatile uint16_t SCANEN; 444 uint32_t reserved0: 16; 445 }; 446 volatile uint32_t U32; 447 }; 448 }; 449 450 #define SI32_CAPSENSE_A_SCAN_SCANEN_MASK 0x0000FFFF 451 #define SI32_CAPSENSE_A_SCAN_SCANEN_SHIFT 0 452 453 454 455 struct SI32_CAPSENSE_A_CSTH_Struct 456 { 457 union 458 { 459 struct 460 { 461 // Compare Threshold 462 volatile uint16_t CSTH_BITS; 463 uint32_t reserved0: 16; 464 }; 465 volatile uint32_t U32; 466 }; 467 }; 468 469 #define SI32_CAPSENSE_A_CSTH_CSTH_MASK 0x0000FFFF 470 #define SI32_CAPSENSE_A_CSTH_CSTH_SHIFT 0 471 472 473 474 struct SI32_CAPSENSE_A_MUX_Struct 475 { 476 union 477 { 478 struct 479 { 480 // Mux Channel Select 481 volatile uint32_t CSMX: 4; 482 uint32_t reserved0: 3; 483 // Channel Disconnect 484 volatile uint32_t CSDISC: 1; 485 uint32_t reserved1: 24; 486 }; 487 volatile uint32_t U32; 488 }; 489 }; 490 491 #define SI32_CAPSENSE_A_MUX_CSMX_MASK 0x0000000F 492 #define SI32_CAPSENSE_A_MUX_CSMX_SHIFT 0 493 // Select CSn.0. 494 #define SI32_CAPSENSE_A_MUX_CSMX_CSN0_VALUE 0 495 #define SI32_CAPSENSE_A_MUX_CSMX_CSN0_U32 \ 496 (SI32_CAPSENSE_A_MUX_CSMX_CSN0_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 497 // Select CSn.1. 498 #define SI32_CAPSENSE_A_MUX_CSMX_CSN1_VALUE 1 499 #define SI32_CAPSENSE_A_MUX_CSMX_CSN1_U32 \ 500 (SI32_CAPSENSE_A_MUX_CSMX_CSN1_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 501 // Select CSn.2. 502 #define SI32_CAPSENSE_A_MUX_CSMX_CSN2_VALUE 2 503 #define SI32_CAPSENSE_A_MUX_CSMX_CSN2_U32 \ 504 (SI32_CAPSENSE_A_MUX_CSMX_CSN2_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 505 // Select CSn.3. 506 #define SI32_CAPSENSE_A_MUX_CSMX_CSN3_VALUE 3 507 #define SI32_CAPSENSE_A_MUX_CSMX_CSN3_U32 \ 508 (SI32_CAPSENSE_A_MUX_CSMX_CSN3_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 509 // Select CSn.4. 510 #define SI32_CAPSENSE_A_MUX_CSMX_CSN4_VALUE 4 511 #define SI32_CAPSENSE_A_MUX_CSMX_CSN4_U32 \ 512 (SI32_CAPSENSE_A_MUX_CSMX_CSN4_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 513 // Select CSn.5. 514 #define SI32_CAPSENSE_A_MUX_CSMX_CSN5_VALUE 5 515 #define SI32_CAPSENSE_A_MUX_CSMX_CSN5_U32 \ 516 (SI32_CAPSENSE_A_MUX_CSMX_CSN5_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 517 // Select CSn.6. 518 #define SI32_CAPSENSE_A_MUX_CSMX_CSN6_VALUE 6 519 #define SI32_CAPSENSE_A_MUX_CSMX_CSN6_U32 \ 520 (SI32_CAPSENSE_A_MUX_CSMX_CSN6_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 521 // Select CSn.7. 522 #define SI32_CAPSENSE_A_MUX_CSMX_CSN7_VALUE 7 523 #define SI32_CAPSENSE_A_MUX_CSMX_CSN7_U32 \ 524 (SI32_CAPSENSE_A_MUX_CSMX_CSN7_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 525 // Select CSn.8. 526 #define SI32_CAPSENSE_A_MUX_CSMX_CSN8_VALUE 8 527 #define SI32_CAPSENSE_A_MUX_CSMX_CSN8_U32 \ 528 (SI32_CAPSENSE_A_MUX_CSMX_CSN8_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 529 // Select CSn.9. 530 #define SI32_CAPSENSE_A_MUX_CSMX_CSN9_VALUE 9 531 #define SI32_CAPSENSE_A_MUX_CSMX_CSN9_U32 \ 532 (SI32_CAPSENSE_A_MUX_CSMX_CSN9_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 533 // Select CSn.10. 534 #define SI32_CAPSENSE_A_MUX_CSMX_CSN10_VALUE 10 535 #define SI32_CAPSENSE_A_MUX_CSMX_CSN10_U32 \ 536 (SI32_CAPSENSE_A_MUX_CSMX_CSN10_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 537 // Select CSn.11. 538 #define SI32_CAPSENSE_A_MUX_CSMX_CSN11_VALUE 11 539 #define SI32_CAPSENSE_A_MUX_CSMX_CSN11_U32 \ 540 (SI32_CAPSENSE_A_MUX_CSMX_CSN11_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 541 // Select CSn.12. 542 #define SI32_CAPSENSE_A_MUX_CSMX_CSN12_VALUE 12 543 #define SI32_CAPSENSE_A_MUX_CSMX_CSN12_U32 \ 544 (SI32_CAPSENSE_A_MUX_CSMX_CSN12_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 545 // Select CSn.13. 546 #define SI32_CAPSENSE_A_MUX_CSMX_CSN13_VALUE 13 547 #define SI32_CAPSENSE_A_MUX_CSMX_CSN13_U32 \ 548 (SI32_CAPSENSE_A_MUX_CSMX_CSN13_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 549 // Select CSn.14. 550 #define SI32_CAPSENSE_A_MUX_CSMX_CSN14_VALUE 14 551 #define SI32_CAPSENSE_A_MUX_CSMX_CSN14_U32 \ 552 (SI32_CAPSENSE_A_MUX_CSMX_CSN14_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 553 // Select CSn.15. 554 #define SI32_CAPSENSE_A_MUX_CSMX_CSN15_VALUE 15 555 #define SI32_CAPSENSE_A_MUX_CSMX_CSN15_U32 \ 556 (SI32_CAPSENSE_A_MUX_CSMX_CSN15_VALUE << SI32_CAPSENSE_A_MUX_CSMX_SHIFT) 557 558 #define SI32_CAPSENSE_A_MUX_CSDISC_MASK 0x00000080 559 #define SI32_CAPSENSE_A_MUX_CSDISC_SHIFT 7 560 // Connect the capacitive sensing circuit to the selected channel. 561 #define SI32_CAPSENSE_A_MUX_CSDISC_CONNECT_VALUE 0 562 #define SI32_CAPSENSE_A_MUX_CSDISC_CONNECT_U32 \ 563 (SI32_CAPSENSE_A_MUX_CSDISC_CONNECT_VALUE << SI32_CAPSENSE_A_MUX_CSDISC_SHIFT) 564 // Disconnect the capacitive sensing input channel. 565 #define SI32_CAPSENSE_A_MUX_CSDISC_DISCONNECT_VALUE 1 566 #define SI32_CAPSENSE_A_MUX_CSDISC_DISCONNECT_U32 \ 567 (SI32_CAPSENSE_A_MUX_CSDISC_DISCONNECT_VALUE << SI32_CAPSENSE_A_MUX_CSDISC_SHIFT) 568 569 570 571 typedef struct SI32_CAPSENSE_A_Struct 572 { 573 struct SI32_CAPSENSE_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 574 volatile uint32_t CONTROL_SET; 575 volatile uint32_t CONTROL_CLR; 576 uint32_t reserved0; 577 struct SI32_CAPSENSE_A_MODE_Struct MODE ; // Base Address + 0x10 578 volatile uint32_t MODE_SET; 579 volatile uint32_t MODE_CLR; 580 uint32_t reserved1; 581 struct SI32_CAPSENSE_A_DATA_Struct DATA ; // Base Address + 0x20 582 uint32_t reserved2; 583 uint32_t reserved3; 584 uint32_t reserved4; 585 struct SI32_CAPSENSE_A_SCAN_Struct SCAN ; // Base Address + 0x30 586 uint32_t reserved5; 587 uint32_t reserved6; 588 uint32_t reserved7; 589 struct SI32_CAPSENSE_A_CSTH_Struct CSTH ; // Base Address + 0x40 590 uint32_t reserved8; 591 uint32_t reserved9; 592 uint32_t reserved10; 593 struct SI32_CAPSENSE_A_MUX_Struct MUX ; // Base Address + 0x50 594 uint32_t reserved11; 595 uint32_t reserved12; 596 uint32_t reserved13; 597 uint32_t reserved14[4]; 598 uint32_t reserved15[4]; 599 } SI32_CAPSENSE_A_Type; 600 601 #ifdef __cplusplus 602 } 603 #endif 604 605 #endif // __SI32_CAPSENSE_A_REGISTERS_H__ 606 607 //-eof-------------------------------------------------------------------------- 608 609
