1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // Script: 0.61 24 // Version: 1 25 26 #ifndef __SI32_AES_B_REGISTERS_H__ 27 #define __SI32_AES_B_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_AES_B_CONTROL_Struct 36 { 37 union 38 { 39 struct 40 { 41 // AES Transfer Start 42 volatile uint32_t XFRSTA: 1; 43 // Key Capture Enable 44 volatile uint32_t KEYCPEN: 1; 45 // Encryption/Decryption Mode 46 volatile uint32_t EDMD: 1; 47 uint32_t reserved0: 5; 48 // Software Mode Enable 49 volatile uint32_t SWMDEN: 1; 50 // Bypass AES Operation Enable 51 volatile uint32_t BEN: 1; 52 // XOR Enable 53 volatile uint32_t XOREN: 2; 54 // Hardware Counter Mode Enable 55 volatile uint32_t HCTREN: 1; 56 // Hardware Cipher-Block Chaining Mode Enable 57 volatile uint32_t HCBCEN: 1; 58 uint32_t reserved1: 2; 59 // Keystore Size Select 60 volatile uint32_t KEYSIZE: 2; 61 uint32_t reserved2: 6; 62 // Error Interrupt Enable 63 volatile uint32_t ERRIEN: 1; 64 // Operation Complete Interrupt Enable 65 volatile uint32_t OCIEN: 1; 66 uint32_t reserved3: 4; 67 // AES Debug Mode 68 volatile uint32_t DBGMD: 1; 69 // Module Soft Reset 70 volatile uint32_t RESET: 1; 71 }; 72 volatile uint32_t U32; 73 }; 74 }; 75 76 #define SI32_AES_B_CONTROL_XFRSTA_MASK 0x00000001 77 #define SI32_AES_B_CONTROL_XFRSTA_SHIFT 0 78 // Start the AES operation. 79 #define SI32_AES_B_CONTROL_XFRSTA_START_VALUE 1 80 #define SI32_AES_B_CONTROL_XFRSTA_START_U32 \ 81 (SI32_AES_B_CONTROL_XFRSTA_START_VALUE << SI32_AES_B_CONTROL_XFRSTA_SHIFT) 82 83 #define SI32_AES_B_CONTROL_KEYCPEN_MASK 0x00000002 84 #define SI32_AES_B_CONTROL_KEYCPEN_SHIFT 1 85 // Disable key capture. 86 #define SI32_AES_B_CONTROL_KEYCPEN_DISABLED_VALUE 0 87 #define SI32_AES_B_CONTROL_KEYCPEN_DISABLED_U32 \ 88 (SI32_AES_B_CONTROL_KEYCPEN_DISABLED_VALUE << SI32_AES_B_CONTROL_KEYCPEN_SHIFT) 89 // Enable key capture. 90 #define SI32_AES_B_CONTROL_KEYCPEN_ENABLED_VALUE 1 91 #define SI32_AES_B_CONTROL_KEYCPEN_ENABLED_U32 \ 92 (SI32_AES_B_CONTROL_KEYCPEN_ENABLED_VALUE << SI32_AES_B_CONTROL_KEYCPEN_SHIFT) 93 94 #define SI32_AES_B_CONTROL_EDMD_MASK 0x00000004 95 #define SI32_AES_B_CONTROL_EDMD_SHIFT 2 96 // AES module performs a decryption operation 97 #define SI32_AES_B_CONTROL_EDMD_DECRYPT_VALUE 0 98 #define SI32_AES_B_CONTROL_EDMD_DECRYPT_U32 \ 99 (SI32_AES_B_CONTROL_EDMD_DECRYPT_VALUE << SI32_AES_B_CONTROL_EDMD_SHIFT) 100 // AES module performs an encryption operation. 101 #define SI32_AES_B_CONTROL_EDMD_ENCRYPT_VALUE 1 102 #define SI32_AES_B_CONTROL_EDMD_ENCRYPT_U32 \ 103 (SI32_AES_B_CONTROL_EDMD_ENCRYPT_VALUE << SI32_AES_B_CONTROL_EDMD_SHIFT) 104 105 #define SI32_AES_B_CONTROL_SWMDEN_MASK 0x00000100 106 #define SI32_AES_B_CONTROL_SWMDEN_SHIFT 8 107 // Disable software mode. 108 #define SI32_AES_B_CONTROL_SWMDEN_DISABLED_VALUE 0 109 #define SI32_AES_B_CONTROL_SWMDEN_DISABLED_U32 \ 110 (SI32_AES_B_CONTROL_SWMDEN_DISABLED_VALUE << SI32_AES_B_CONTROL_SWMDEN_SHIFT) 111 // Enable software mode. 112 #define SI32_AES_B_CONTROL_SWMDEN_ENABLED_VALUE 1 113 #define SI32_AES_B_CONTROL_SWMDEN_ENABLED_U32 \ 114 (SI32_AES_B_CONTROL_SWMDEN_ENABLED_VALUE << SI32_AES_B_CONTROL_SWMDEN_SHIFT) 115 116 #define SI32_AES_B_CONTROL_BEN_MASK 0x00000200 117 #define SI32_AES_B_CONTROL_BEN_SHIFT 9 118 // Do not bypass AES operations. 119 #define SI32_AES_B_CONTROL_BEN_DISABLED_VALUE 0 120 #define SI32_AES_B_CONTROL_BEN_DISABLED_U32 \ 121 (SI32_AES_B_CONTROL_BEN_DISABLED_VALUE << SI32_AES_B_CONTROL_BEN_SHIFT) 122 // Bypass AES operations. 123 #define SI32_AES_B_CONTROL_BEN_ENABLED_VALUE 1 124 #define SI32_AES_B_CONTROL_BEN_ENABLED_U32 \ 125 (SI32_AES_B_CONTROL_BEN_ENABLED_VALUE << SI32_AES_B_CONTROL_BEN_SHIFT) 126 127 #define SI32_AES_B_CONTROL_XOREN_MASK 0x00000C00 128 #define SI32_AES_B_CONTROL_XOREN_SHIFT 10 129 // Disable the XOR paths. 130 #define SI32_AES_B_CONTROL_XOREN_XOR_DISABLED_VALUE 0 131 #define SI32_AES_B_CONTROL_XOREN_XOR_DISABLED_U32 \ 132 (SI32_AES_B_CONTROL_XOREN_XOR_DISABLED_VALUE << SI32_AES_B_CONTROL_XOREN_SHIFT) 133 // Enable the XOR input path, disable the XOR output path. 134 #define SI32_AES_B_CONTROL_XOREN_XOR_INPUT_VALUE 1 135 #define SI32_AES_B_CONTROL_XOREN_XOR_INPUT_U32 \ 136 (SI32_AES_B_CONTROL_XOREN_XOR_INPUT_VALUE << SI32_AES_B_CONTROL_XOREN_SHIFT) 137 // Disable the XOR input path, enable the XOR output path. 138 #define SI32_AES_B_CONTROL_XOREN_XOR_OUTPUT_VALUE 2 139 #define SI32_AES_B_CONTROL_XOREN_XOR_OUTPUT_U32 \ 140 (SI32_AES_B_CONTROL_XOREN_XOR_OUTPUT_VALUE << SI32_AES_B_CONTROL_XOREN_SHIFT) 141 142 #define SI32_AES_B_CONTROL_HCTREN_MASK 0x00001000 143 #define SI32_AES_B_CONTROL_HCTREN_SHIFT 12 144 // Disable hardware counter mode. 145 #define SI32_AES_B_CONTROL_HCTREN_DISABLED_VALUE 0 146 #define SI32_AES_B_CONTROL_HCTREN_DISABLED_U32 \ 147 (SI32_AES_B_CONTROL_HCTREN_DISABLED_VALUE << SI32_AES_B_CONTROL_HCTREN_SHIFT) 148 // Enable hardware counter mode. 149 #define SI32_AES_B_CONTROL_HCTREN_ENABLED_VALUE 1 150 #define SI32_AES_B_CONTROL_HCTREN_ENABLED_U32 \ 151 (SI32_AES_B_CONTROL_HCTREN_ENABLED_VALUE << SI32_AES_B_CONTROL_HCTREN_SHIFT) 152 153 #define SI32_AES_B_CONTROL_HCBCEN_MASK 0x00002000 154 #define SI32_AES_B_CONTROL_HCBCEN_SHIFT 13 155 // Disable hardware cipher-block chaining (CBC) mode. 156 #define SI32_AES_B_CONTROL_HCBCEN_DISABLED_VALUE 0 157 #define SI32_AES_B_CONTROL_HCBCEN_DISABLED_U32 \ 158 (SI32_AES_B_CONTROL_HCBCEN_DISABLED_VALUE << SI32_AES_B_CONTROL_HCBCEN_SHIFT) 159 // Enable hardware cipher-block chaining (CBC) mode. 160 #define SI32_AES_B_CONTROL_HCBCEN_ENABLED_VALUE 1 161 #define SI32_AES_B_CONTROL_HCBCEN_ENABLED_U32 \ 162 (SI32_AES_B_CONTROL_HCBCEN_ENABLED_VALUE << SI32_AES_B_CONTROL_HCBCEN_SHIFT) 163 164 #define SI32_AES_B_CONTROL_KEYSIZE_MASK 0x00030000 165 #define SI32_AES_B_CONTROL_KEYSIZE_SHIFT 16 166 // Key is composed of 128 bits. 167 #define SI32_AES_B_CONTROL_KEYSIZE_KEY128_VALUE 0 168 #define SI32_AES_B_CONTROL_KEYSIZE_KEY128_U32 \ 169 (SI32_AES_B_CONTROL_KEYSIZE_KEY128_VALUE << SI32_AES_B_CONTROL_KEYSIZE_SHIFT) 170 // Key is composed of 192 bits. 171 #define SI32_AES_B_CONTROL_KEYSIZE_KEY192_VALUE 1 172 #define SI32_AES_B_CONTROL_KEYSIZE_KEY192_U32 \ 173 (SI32_AES_B_CONTROL_KEYSIZE_KEY192_VALUE << SI32_AES_B_CONTROL_KEYSIZE_SHIFT) 174 // Key is composed of 256 bits. 175 #define SI32_AES_B_CONTROL_KEYSIZE_KEY256_VALUE 2 176 #define SI32_AES_B_CONTROL_KEYSIZE_KEY256_U32 \ 177 (SI32_AES_B_CONTROL_KEYSIZE_KEY256_VALUE << SI32_AES_B_CONTROL_KEYSIZE_SHIFT) 178 179 #define SI32_AES_B_CONTROL_ERRIEN_MASK 0x01000000 180 #define SI32_AES_B_CONTROL_ERRIEN_SHIFT 24 181 // Disable the error interrupt. 182 #define SI32_AES_B_CONTROL_ERRIEN_DISABLED_VALUE 0 183 #define SI32_AES_B_CONTROL_ERRIEN_DISABLED_U32 \ 184 (SI32_AES_B_CONTROL_ERRIEN_DISABLED_VALUE << SI32_AES_B_CONTROL_ERRIEN_SHIFT) 185 // Enable the error interrupt. An interrupt is generated when the Input/Output Data 186 // FIFO Overun (DORI), Input/Output Data FIFO Underun (DURI), or XOR Data FIFO 187 // Overrun (XORI) flags are set. 188 #define SI32_AES_B_CONTROL_ERRIEN_ENABLED_VALUE 1 189 #define SI32_AES_B_CONTROL_ERRIEN_ENABLED_U32 \ 190 (SI32_AES_B_CONTROL_ERRIEN_ENABLED_VALUE << SI32_AES_B_CONTROL_ERRIEN_SHIFT) 191 192 #define SI32_AES_B_CONTROL_OCIEN_MASK 0x02000000 193 #define SI32_AES_B_CONTROL_OCIEN_SHIFT 25 194 // Disable the operation complete interrupt. 195 #define SI32_AES_B_CONTROL_OCIEN_DISABLED_VALUE 0 196 #define SI32_AES_B_CONTROL_OCIEN_DISABLED_U32 \ 197 (SI32_AES_B_CONTROL_OCIEN_DISABLED_VALUE << SI32_AES_B_CONTROL_OCIEN_SHIFT) 198 // Enable the operation complete interrupt. An interrupt is generated when the 199 // Operation Complete Interrupt (OCI) flag is set. 200 #define SI32_AES_B_CONTROL_OCIEN_ENABLED_VALUE 1 201 #define SI32_AES_B_CONTROL_OCIEN_ENABLED_U32 \ 202 (SI32_AES_B_CONTROL_OCIEN_ENABLED_VALUE << SI32_AES_B_CONTROL_OCIEN_SHIFT) 203 204 #define SI32_AES_B_CONTROL_DBGMD_MASK 0x40000000 205 #define SI32_AES_B_CONTROL_DBGMD_SHIFT 30 206 // A debug breakpoint will cause the AES module to halt. 207 #define SI32_AES_B_CONTROL_DBGMD_HALT_VALUE 0 208 #define SI32_AES_B_CONTROL_DBGMD_HALT_U32 \ 209 (SI32_AES_B_CONTROL_DBGMD_HALT_VALUE << SI32_AES_B_CONTROL_DBGMD_SHIFT) 210 // The AES module will continue to operate while the core is halted in debug mode. 211 #define SI32_AES_B_CONTROL_DBGMD_RUN_VALUE 1 212 #define SI32_AES_B_CONTROL_DBGMD_RUN_U32 \ 213 (SI32_AES_B_CONTROL_DBGMD_RUN_VALUE << SI32_AES_B_CONTROL_DBGMD_SHIFT) 214 215 #define SI32_AES_B_CONTROL_RESET_MASK 0x80000000 216 #define SI32_AES_B_CONTROL_RESET_SHIFT 31 217 // AES module is not in soft reset. 218 #define SI32_AES_B_CONTROL_RESET_INACTIVE_VALUE 0U 219 #define SI32_AES_B_CONTROL_RESET_INACTIVE_U32 \ 220 (SI32_AES_B_CONTROL_RESET_INACTIVE_VALUE << SI32_AES_B_CONTROL_RESET_SHIFT) 221 // AES module is in soft reset and none of the module bits can be accessed. 222 #define SI32_AES_B_CONTROL_RESET_ACTIVE_VALUE 1U 223 #define SI32_AES_B_CONTROL_RESET_ACTIVE_U32 \ 224 (SI32_AES_B_CONTROL_RESET_ACTIVE_VALUE << SI32_AES_B_CONTROL_RESET_SHIFT) 225 226 227 228 struct SI32_AES_B_XFRSIZE_Struct 229 { 230 union 231 { 232 struct 233 { 234 // Transfer Size 235 volatile uint32_t XFRSIZE_BITS: 11; 236 uint32_t reserved0: 21; 237 }; 238 volatile uint32_t U32; 239 }; 240 }; 241 242 #define SI32_AES_B_XFRSIZE_XFRSIZE_MASK 0x000007FF 243 #define SI32_AES_B_XFRSIZE_XFRSIZE_SHIFT 0 244 245 246 247 struct SI32_AES_B_DATAFIFO_Struct 248 { 249 union 250 { 251 // This is a FIFO register 252 volatile uint8_t U8; 253 volatile uint16_t U16; 254 volatile uint32_t U32; 255 }; 256 }; 257 258 #define SI32_AES_B_DATAFIFO_DATAFIFO_MASK 0xFFFFFFFF 259 #define SI32_AES_B_DATAFIFO_DATAFIFO_SHIFT 0 260 261 262 263 struct SI32_AES_B_XORFIFO_Struct 264 { 265 union 266 { 267 // This is a FIFO register 268 volatile uint8_t U8; 269 volatile uint16_t U16; 270 volatile uint32_t U32; 271 }; 272 }; 273 274 #define SI32_AES_B_XORFIFO_XORFIFO_MASK 0xFFFFFFFF 275 #define SI32_AES_B_XORFIFO_XORFIFO_SHIFT 0 276 277 278 279 struct SI32_AES_B_HWKEY0_Struct 280 { 281 union 282 { 283 struct 284 { 285 // Hardware Key Word 0 286 volatile uint32_t HWKEY0_BITS; 287 }; 288 volatile uint32_t U32; 289 }; 290 }; 291 292 #define SI32_AES_B_HWKEY0_HWKEY0_MASK 0xFFFFFFFF 293 #define SI32_AES_B_HWKEY0_HWKEY0_SHIFT 0 294 295 296 297 struct SI32_AES_B_HWKEY1_Struct 298 { 299 union 300 { 301 struct 302 { 303 // Hardware Key Word 1 304 volatile uint32_t HWKEY1_BITS; 305 }; 306 volatile uint32_t U32; 307 }; 308 }; 309 310 #define SI32_AES_B_HWKEY1_HWKEY1_MASK 0xFFFFFFFF 311 #define SI32_AES_B_HWKEY1_HWKEY1_SHIFT 0 312 313 314 315 struct SI32_AES_B_HWKEY2_Struct 316 { 317 union 318 { 319 struct 320 { 321 // Hardware Key Word 2 322 volatile uint32_t HWKEY2_BITS; 323 }; 324 volatile uint32_t U32; 325 }; 326 }; 327 328 #define SI32_AES_B_HWKEY2_HWKEY2_MASK 0xFFFFFFFF 329 #define SI32_AES_B_HWKEY2_HWKEY2_SHIFT 0 330 331 332 333 struct SI32_AES_B_HWKEY3_Struct 334 { 335 union 336 { 337 struct 338 { 339 // Hardware Key Word 3 340 volatile uint32_t HWKEY3_BITS; 341 }; 342 volatile uint32_t U32; 343 }; 344 }; 345 346 #define SI32_AES_B_HWKEY3_HWKEY3_MASK 0xFFFFFFFF 347 #define SI32_AES_B_HWKEY3_HWKEY3_SHIFT 0 348 349 350 351 struct SI32_AES_B_HWKEY4_Struct 352 { 353 union 354 { 355 struct 356 { 357 // Hardware Key Word 4 358 volatile uint32_t HWKEY4_BITS; 359 }; 360 volatile uint32_t U32; 361 }; 362 }; 363 364 #define SI32_AES_B_HWKEY4_HWKEY4_MASK 0xFFFFFFFF 365 #define SI32_AES_B_HWKEY4_HWKEY4_SHIFT 0 366 367 368 369 struct SI32_AES_B_HWKEY5_Struct 370 { 371 union 372 { 373 struct 374 { 375 // Hardware Key Word 5 376 volatile uint32_t HWKEY5_BITS; 377 }; 378 volatile uint32_t U32; 379 }; 380 }; 381 382 #define SI32_AES_B_HWKEY5_HWKEY5_MASK 0xFFFFFFFF 383 #define SI32_AES_B_HWKEY5_HWKEY5_SHIFT 0 384 385 386 387 struct SI32_AES_B_HWKEY6_Struct 388 { 389 union 390 { 391 struct 392 { 393 // Hardware Key Word 6 394 volatile uint32_t HWKEY6_BITS; 395 }; 396 volatile uint32_t U32; 397 }; 398 }; 399 400 #define SI32_AES_B_HWKEY6_HWKEY6_MASK 0xFFFFFFFF 401 #define SI32_AES_B_HWKEY6_HWKEY6_SHIFT 0 402 403 404 405 struct SI32_AES_B_HWKEY7_Struct 406 { 407 union 408 { 409 struct 410 { 411 // Hardware Key Word 7 412 volatile uint32_t HWKEY7_BITS; 413 }; 414 volatile uint32_t U32; 415 }; 416 }; 417 418 #define SI32_AES_B_HWKEY7_HWKEY7_MASK 0xFFFFFFFF 419 #define SI32_AES_B_HWKEY7_HWKEY7_SHIFT 0 420 421 422 423 struct SI32_AES_B_HWCTR0_Struct 424 { 425 union 426 { 427 struct 428 { 429 // Hardware Counter Word 0 430 volatile uint32_t HWCTR0_BITS; 431 }; 432 volatile uint32_t U32; 433 }; 434 }; 435 436 #define SI32_AES_B_HWCTR0_HWCTR0_MASK 0xFFFFFFFF 437 #define SI32_AES_B_HWCTR0_HWCTR0_SHIFT 0 438 439 440 441 struct SI32_AES_B_HWCTR1_Struct 442 { 443 union 444 { 445 struct 446 { 447 // Hardware Counter Word 1 448 volatile uint32_t HWCTR1_BITS; 449 }; 450 volatile uint32_t U32; 451 }; 452 }; 453 454 #define SI32_AES_B_HWCTR1_HWCTR1_MASK 0xFFFFFFFF 455 #define SI32_AES_B_HWCTR1_HWCTR1_SHIFT 0 456 457 458 459 struct SI32_AES_B_HWCTR2_Struct 460 { 461 union 462 { 463 struct 464 { 465 // Hardware Counter Word 2 466 volatile uint32_t HWCTR2_BITS; 467 }; 468 volatile uint32_t U32; 469 }; 470 }; 471 472 #define SI32_AES_B_HWCTR2_HWCTR2_MASK 0xFFFFFFFF 473 #define SI32_AES_B_HWCTR2_HWCTR2_SHIFT 0 474 475 476 477 struct SI32_AES_B_HWCTR3_Struct 478 { 479 union 480 { 481 struct 482 { 483 // Hardware Counter Word 3 484 volatile uint32_t HWCTR3_BITS; 485 }; 486 volatile uint32_t U32; 487 }; 488 }; 489 490 #define SI32_AES_B_HWCTR3_HWCTR3_MASK 0xFFFFFFFF 491 #define SI32_AES_B_HWCTR3_HWCTR3_SHIFT 0 492 493 494 495 struct SI32_AES_B_STATUS_Struct 496 { 497 union 498 { 499 struct 500 { 501 // Input/Output Data FIFO Level 502 volatile uint32_t DFIFOLVL: 5; 503 uint32_t reserved0: 3; 504 // XOR Data FIFO Level 505 volatile uint32_t XFIFOLVL: 5; 506 uint32_t reserved1: 11; 507 // Module Busy Flag 508 volatile uint32_t BUSYF: 1; 509 uint32_t reserved2: 3; 510 // Input/Output Data FIFO Underrun Interrupt Flag 511 volatile uint32_t DURI: 1; 512 // Input/Output Data FIFO Overrun Interrupt Flag 513 volatile uint32_t DORI: 1; 514 // XOR Data FIFO Overrun Interrupt Flag 515 volatile uint32_t XORI: 1; 516 // Operation Complete Interrupt Flag 517 volatile uint32_t OCI: 1; 518 }; 519 volatile uint32_t U32; 520 }; 521 }; 522 523 #define SI32_AES_B_STATUS_DFIFOLVL_MASK 0x0000001F 524 #define SI32_AES_B_STATUS_DFIFOLVL_SHIFT 0 525 // Input/Output data FIFO is empty. 526 #define SI32_AES_B_STATUS_DFIFOLVL_EMPTY_VALUE 0 527 #define SI32_AES_B_STATUS_DFIFOLVL_EMPTY_U32 \ 528 (SI32_AES_B_STATUS_DFIFOLVL_EMPTY_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 529 // Input/Output data FIFO contains 1 byte. 530 #define SI32_AES_B_STATUS_DFIFOLVL_1_BYTE_VALUE 1 531 #define SI32_AES_B_STATUS_DFIFOLVL_1_BYTE_U32 \ 532 (SI32_AES_B_STATUS_DFIFOLVL_1_BYTE_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 533 // Input/Output data FIFO contains 2 bytes. 534 #define SI32_AES_B_STATUS_DFIFOLVL_2_BYTES_VALUE 2 535 #define SI32_AES_B_STATUS_DFIFOLVL_2_BYTES_U32 \ 536 (SI32_AES_B_STATUS_DFIFOLVL_2_BYTES_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 537 // Input/Output data FIFO contains 3 bytes. 538 #define SI32_AES_B_STATUS_DFIFOLVL_3_BYTES_VALUE 3 539 #define SI32_AES_B_STATUS_DFIFOLVL_3_BYTES_U32 \ 540 (SI32_AES_B_STATUS_DFIFOLVL_3_BYTES_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 541 // Input/Output data FIFO contains 4 bytes. 542 #define SI32_AES_B_STATUS_DFIFOLVL_4_BYTES_VALUE 4 543 #define SI32_AES_B_STATUS_DFIFOLVL_4_BYTES_U32 \ 544 (SI32_AES_B_STATUS_DFIFOLVL_4_BYTES_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 545 // Input/Output data FIFO contains 5 bytes. 546 #define SI32_AES_B_STATUS_DFIFOLVL_5_BYTES_VALUE 5 547 #define SI32_AES_B_STATUS_DFIFOLVL_5_BYTES_U32 \ 548 (SI32_AES_B_STATUS_DFIFOLVL_5_BYTES_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 549 // Input/Output data FIFO contains 6 bytes. 550 #define SI32_AES_B_STATUS_DFIFOLVL_6_BYTES_VALUE 6 551 #define SI32_AES_B_STATUS_DFIFOLVL_6_BYTES_U32 \ 552 (SI32_AES_B_STATUS_DFIFOLVL_6_BYTES_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 553 // Input/Output data FIFO contains 7 bytes. 554 #define SI32_AES_B_STATUS_DFIFOLVL_7_BYTES_VALUE 7 555 #define SI32_AES_B_STATUS_DFIFOLVL_7_BYTES_U32 \ 556 (SI32_AES_B_STATUS_DFIFOLVL_7_BYTES_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 557 // Input/Output data FIFO contains 8 bytes. 558 #define SI32_AES_B_STATUS_DFIFOLVL_8_BYTES_VALUE 8 559 #define SI32_AES_B_STATUS_DFIFOLVL_8_BYTES_U32 \ 560 (SI32_AES_B_STATUS_DFIFOLVL_8_BYTES_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 561 // Input/Output data FIFO contains 9 bytes. 562 #define SI32_AES_B_STATUS_DFIFOLVL_9_BYTES_VALUE 9 563 #define SI32_AES_B_STATUS_DFIFOLVL_9_BYTES_U32 \ 564 (SI32_AES_B_STATUS_DFIFOLVL_9_BYTES_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 565 // Input/Output data FIFO contains 10 bytes. 566 #define SI32_AES_B_STATUS_DFIFOLVL_10_BYTES_VALUE 10 567 #define SI32_AES_B_STATUS_DFIFOLVL_10_BYTES_U32 \ 568 (SI32_AES_B_STATUS_DFIFOLVL_10_BYTES_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 569 // Input/Output data FIFO contains 11 bytes. 570 #define SI32_AES_B_STATUS_DFIFOLVL_11_BYTES_VALUE 11 571 #define SI32_AES_B_STATUS_DFIFOLVL_11_BYTES_U32 \ 572 (SI32_AES_B_STATUS_DFIFOLVL_11_BYTES_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 573 // Input/Output data FIFO contains 12 bytes. 574 #define SI32_AES_B_STATUS_DFIFOLVL_12_BYTES_VALUE 12 575 #define SI32_AES_B_STATUS_DFIFOLVL_12_BYTES_U32 \ 576 (SI32_AES_B_STATUS_DFIFOLVL_12_BYTES_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 577 // Input/Output data FIFO contains 13 bytes. 578 #define SI32_AES_B_STATUS_DFIFOLVL_13_BYTES_VALUE 13 579 #define SI32_AES_B_STATUS_DFIFOLVL_13_BYTES_U32 \ 580 (SI32_AES_B_STATUS_DFIFOLVL_13_BYTES_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 581 // Input/Output data FIFO contains 14 bytes. 582 #define SI32_AES_B_STATUS_DFIFOLVL_14_BYTES_VALUE 14 583 #define SI32_AES_B_STATUS_DFIFOLVL_14_BYTES_U32 \ 584 (SI32_AES_B_STATUS_DFIFOLVL_14_BYTES_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 585 // Input/Output data FIFO contains 15 bytes. 586 #define SI32_AES_B_STATUS_DFIFOLVL_15_BYTES_VALUE 15 587 #define SI32_AES_B_STATUS_DFIFOLVL_15_BYTES_U32 \ 588 (SI32_AES_B_STATUS_DFIFOLVL_15_BYTES_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 589 // Input/Output data FIFO contains 16 bytes (full). 590 #define SI32_AES_B_STATUS_DFIFOLVL_FULL_VALUE 16 591 #define SI32_AES_B_STATUS_DFIFOLVL_FULL_U32 \ 592 (SI32_AES_B_STATUS_DFIFOLVL_FULL_VALUE << SI32_AES_B_STATUS_DFIFOLVL_SHIFT) 593 594 #define SI32_AES_B_STATUS_XFIFOLVL_MASK 0x00001F00 595 #define SI32_AES_B_STATUS_XFIFOLVL_SHIFT 8 596 // XOR data FIFO is empty. 597 #define SI32_AES_B_STATUS_XFIFOLVL_EMPTY_VALUE 0 598 #define SI32_AES_B_STATUS_XFIFOLVL_EMPTY_U32 \ 599 (SI32_AES_B_STATUS_XFIFOLVL_EMPTY_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 600 // XOR data FIFO contains 1 byte. 601 #define SI32_AES_B_STATUS_XFIFOLVL_1_BYTE_VALUE 1 602 #define SI32_AES_B_STATUS_XFIFOLVL_1_BYTE_U32 \ 603 (SI32_AES_B_STATUS_XFIFOLVL_1_BYTE_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 604 // XOR data FIFO contains 2 bytes. 605 #define SI32_AES_B_STATUS_XFIFOLVL_2_BYTES_VALUE 2 606 #define SI32_AES_B_STATUS_XFIFOLVL_2_BYTES_U32 \ 607 (SI32_AES_B_STATUS_XFIFOLVL_2_BYTES_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 608 // XOR data FIFO contains 3 bytes. 609 #define SI32_AES_B_STATUS_XFIFOLVL_3_BYTES_VALUE 3 610 #define SI32_AES_B_STATUS_XFIFOLVL_3_BYTES_U32 \ 611 (SI32_AES_B_STATUS_XFIFOLVL_3_BYTES_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 612 // XOR data FIFO contains 4 bytes. 613 #define SI32_AES_B_STATUS_XFIFOLVL_4_BYTES_VALUE 4 614 #define SI32_AES_B_STATUS_XFIFOLVL_4_BYTES_U32 \ 615 (SI32_AES_B_STATUS_XFIFOLVL_4_BYTES_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 616 // XOR data FIFO contains 5 bytes. 617 #define SI32_AES_B_STATUS_XFIFOLVL_5_BYTES_VALUE 5 618 #define SI32_AES_B_STATUS_XFIFOLVL_5_BYTES_U32 \ 619 (SI32_AES_B_STATUS_XFIFOLVL_5_BYTES_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 620 // XOR data FIFO contains 6 bytes. 621 #define SI32_AES_B_STATUS_XFIFOLVL_6_BYTES_VALUE 6 622 #define SI32_AES_B_STATUS_XFIFOLVL_6_BYTES_U32 \ 623 (SI32_AES_B_STATUS_XFIFOLVL_6_BYTES_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 624 // XOR data FIFO contains 7 bytes. 625 #define SI32_AES_B_STATUS_XFIFOLVL_7_BYTES_VALUE 7 626 #define SI32_AES_B_STATUS_XFIFOLVL_7_BYTES_U32 \ 627 (SI32_AES_B_STATUS_XFIFOLVL_7_BYTES_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 628 // XOR data FIFO contains 8 bytes. 629 #define SI32_AES_B_STATUS_XFIFOLVL_8_BYTES_VALUE 8 630 #define SI32_AES_B_STATUS_XFIFOLVL_8_BYTES_U32 \ 631 (SI32_AES_B_STATUS_XFIFOLVL_8_BYTES_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 632 // XOR data FIFO contains 9 bytes. 633 #define SI32_AES_B_STATUS_XFIFOLVL_9_BYTES_VALUE 9 634 #define SI32_AES_B_STATUS_XFIFOLVL_9_BYTES_U32 \ 635 (SI32_AES_B_STATUS_XFIFOLVL_9_BYTES_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 636 // XOR data FIFO contains 10 bytes. 637 #define SI32_AES_B_STATUS_XFIFOLVL_10_BYTES_VALUE 10 638 #define SI32_AES_B_STATUS_XFIFOLVL_10_BYTES_U32 \ 639 (SI32_AES_B_STATUS_XFIFOLVL_10_BYTES_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 640 // XOR data FIFO contains 11 bytes. 641 #define SI32_AES_B_STATUS_XFIFOLVL_11_BYTES_VALUE 11 642 #define SI32_AES_B_STATUS_XFIFOLVL_11_BYTES_U32 \ 643 (SI32_AES_B_STATUS_XFIFOLVL_11_BYTES_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 644 // XOR data FIFO contains 12 bytes. 645 #define SI32_AES_B_STATUS_XFIFOLVL_12_BYTES_VALUE 12 646 #define SI32_AES_B_STATUS_XFIFOLVL_12_BYTES_U32 \ 647 (SI32_AES_B_STATUS_XFIFOLVL_12_BYTES_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 648 // XOR data FIFO contains 13 bytes. 649 #define SI32_AES_B_STATUS_XFIFOLVL_13_BYTES_VALUE 13 650 #define SI32_AES_B_STATUS_XFIFOLVL_13_BYTES_U32 \ 651 (SI32_AES_B_STATUS_XFIFOLVL_13_BYTES_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 652 // XOR data FIFO contains 14 bytes. 653 #define SI32_AES_B_STATUS_XFIFOLVL_14_BYTES_VALUE 14 654 #define SI32_AES_B_STATUS_XFIFOLVL_14_BYTES_U32 \ 655 (SI32_AES_B_STATUS_XFIFOLVL_14_BYTES_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 656 // XOR data FIFO contains 15 bytes. 657 #define SI32_AES_B_STATUS_XFIFOLVL_15_BYTES_VALUE 15 658 #define SI32_AES_B_STATUS_XFIFOLVL_15_BYTES_U32 \ 659 (SI32_AES_B_STATUS_XFIFOLVL_15_BYTES_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 660 // XOR data FIFO contains 16 bytes (full). 661 #define SI32_AES_B_STATUS_XFIFOLVL_FULL_VALUE 16 662 #define SI32_AES_B_STATUS_XFIFOLVL_FULL_U32 \ 663 (SI32_AES_B_STATUS_XFIFOLVL_FULL_VALUE << SI32_AES_B_STATUS_XFIFOLVL_SHIFT) 664 665 #define SI32_AES_B_STATUS_BUSYF_MASK 0x01000000 666 #define SI32_AES_B_STATUS_BUSYF_SHIFT 24 667 // AES module is not busy. 668 #define SI32_AES_B_STATUS_BUSYF_NOT_SET_VALUE 0 669 #define SI32_AES_B_STATUS_BUSYF_NOT_SET_U32 \ 670 (SI32_AES_B_STATUS_BUSYF_NOT_SET_VALUE << SI32_AES_B_STATUS_BUSYF_SHIFT) 671 // AES module is completing an operation. 672 #define SI32_AES_B_STATUS_BUSYF_SET_VALUE 1 673 #define SI32_AES_B_STATUS_BUSYF_SET_U32 \ 674 (SI32_AES_B_STATUS_BUSYF_SET_VALUE << SI32_AES_B_STATUS_BUSYF_SHIFT) 675 676 #define SI32_AES_B_STATUS_DURI_MASK 0x10000000 677 #define SI32_AES_B_STATUS_DURI_SHIFT 28 678 // No input/output data FIFO underrun. 679 #define SI32_AES_B_STATUS_DURI_NOT_SET_VALUE 0 680 #define SI32_AES_B_STATUS_DURI_NOT_SET_U32 \ 681 (SI32_AES_B_STATUS_DURI_NOT_SET_VALUE << SI32_AES_B_STATUS_DURI_SHIFT) 682 // An input/output data FIFO underrun has occurred. 683 #define SI32_AES_B_STATUS_DURI_SET_VALUE 1 684 #define SI32_AES_B_STATUS_DURI_SET_U32 \ 685 (SI32_AES_B_STATUS_DURI_SET_VALUE << SI32_AES_B_STATUS_DURI_SHIFT) 686 687 #define SI32_AES_B_STATUS_DORI_MASK 0x20000000 688 #define SI32_AES_B_STATUS_DORI_SHIFT 29 689 // No input/output data FIFO overrun. 690 #define SI32_AES_B_STATUS_DORI_NOT_SET_VALUE 0 691 #define SI32_AES_B_STATUS_DORI_NOT_SET_U32 \ 692 (SI32_AES_B_STATUS_DORI_NOT_SET_VALUE << SI32_AES_B_STATUS_DORI_SHIFT) 693 // An input/output data FIFO overrun has occurred. 694 #define SI32_AES_B_STATUS_DORI_SET_VALUE 1 695 #define SI32_AES_B_STATUS_DORI_SET_U32 \ 696 (SI32_AES_B_STATUS_DORI_SET_VALUE << SI32_AES_B_STATUS_DORI_SHIFT) 697 698 #define SI32_AES_B_STATUS_XORI_MASK 0x40000000 699 #define SI32_AES_B_STATUS_XORI_SHIFT 30 700 // No XOR data FIFO overrun. 701 #define SI32_AES_B_STATUS_XORI_NOT_SET_VALUE 0 702 #define SI32_AES_B_STATUS_XORI_NOT_SET_U32 \ 703 (SI32_AES_B_STATUS_XORI_NOT_SET_VALUE << SI32_AES_B_STATUS_XORI_SHIFT) 704 // An XOR data FIFO overrun has occurred. 705 #define SI32_AES_B_STATUS_XORI_SET_VALUE 1 706 #define SI32_AES_B_STATUS_XORI_SET_U32 \ 707 (SI32_AES_B_STATUS_XORI_SET_VALUE << SI32_AES_B_STATUS_XORI_SHIFT) 708 709 #define SI32_AES_B_STATUS_OCI_MASK 0x80000000 710 #define SI32_AES_B_STATUS_OCI_SHIFT 31 711 // AES operation complete interrupt has not occurred. 712 #define SI32_AES_B_STATUS_OCI_NOT_SET_VALUE 0U 713 #define SI32_AES_B_STATUS_OCI_NOT_SET_U32 \ 714 (SI32_AES_B_STATUS_OCI_NOT_SET_VALUE << SI32_AES_B_STATUS_OCI_SHIFT) 715 // AES operation complete interrupt occurred. 716 #define SI32_AES_B_STATUS_OCI_SET_VALUE 1U 717 #define SI32_AES_B_STATUS_OCI_SET_U32 \ 718 (SI32_AES_B_STATUS_OCI_SET_VALUE << SI32_AES_B_STATUS_OCI_SHIFT) 719 720 721 722 typedef struct SI32_AES_B_Struct 723 { 724 struct SI32_AES_B_CONTROL_Struct CONTROL ; // Base Address + 0x0 725 volatile uint32_t CONTROL_SET; 726 volatile uint32_t CONTROL_CLR; 727 uint32_t reserved0; 728 struct SI32_AES_B_XFRSIZE_Struct XFRSIZE ; // Base Address + 0x10 729 uint32_t reserved1; 730 uint32_t reserved2; 731 uint32_t reserved3; 732 struct SI32_AES_B_DATAFIFO_Struct DATAFIFO ; // Base Address + 0x20 733 uint32_t reserved4; 734 uint32_t reserved5; 735 uint32_t reserved6; 736 struct SI32_AES_B_XORFIFO_Struct XORFIFO ; // Base Address + 0x30 737 uint32_t reserved7; 738 uint32_t reserved8; 739 uint32_t reserved9; 740 struct SI32_AES_B_HWKEY0_Struct HWKEY0 ; // Base Address + 0x40 741 uint32_t reserved10; 742 uint32_t reserved11; 743 uint32_t reserved12; 744 struct SI32_AES_B_HWKEY1_Struct HWKEY1 ; // Base Address + 0x50 745 uint32_t reserved13; 746 uint32_t reserved14; 747 uint32_t reserved15; 748 struct SI32_AES_B_HWKEY2_Struct HWKEY2 ; // Base Address + 0x60 749 uint32_t reserved16; 750 uint32_t reserved17; 751 uint32_t reserved18; 752 struct SI32_AES_B_HWKEY3_Struct HWKEY3 ; // Base Address + 0x70 753 uint32_t reserved19; 754 uint32_t reserved20; 755 uint32_t reserved21; 756 struct SI32_AES_B_HWKEY4_Struct HWKEY4 ; // Base Address + 0x80 757 uint32_t reserved22; 758 uint32_t reserved23; 759 uint32_t reserved24; 760 struct SI32_AES_B_HWKEY5_Struct HWKEY5 ; // Base Address + 0x90 761 uint32_t reserved25; 762 uint32_t reserved26; 763 uint32_t reserved27; 764 struct SI32_AES_B_HWKEY6_Struct HWKEY6 ; // Base Address + 0xa0 765 uint32_t reserved28; 766 uint32_t reserved29; 767 uint32_t reserved30; 768 struct SI32_AES_B_HWKEY7_Struct HWKEY7 ; // Base Address + 0xb0 769 uint32_t reserved31; 770 uint32_t reserved32; 771 uint32_t reserved33; 772 struct SI32_AES_B_HWCTR0_Struct HWCTR0 ; // Base Address + 0xc0 773 uint32_t reserved34; 774 uint32_t reserved35; 775 uint32_t reserved36; 776 struct SI32_AES_B_HWCTR1_Struct HWCTR1 ; // Base Address + 0xd0 777 uint32_t reserved37; 778 uint32_t reserved38; 779 uint32_t reserved39; 780 struct SI32_AES_B_HWCTR2_Struct HWCTR2 ; // Base Address + 0xe0 781 uint32_t reserved40; 782 uint32_t reserved41; 783 uint32_t reserved42; 784 struct SI32_AES_B_HWCTR3_Struct HWCTR3 ; // Base Address + 0xf0 785 uint32_t reserved43; 786 uint32_t reserved44; 787 uint32_t reserved45; 788 struct SI32_AES_B_STATUS_Struct STATUS ; // Base Address + 0x100 789 volatile uint32_t STATUS_SET; 790 volatile uint32_t STATUS_CLR; 791 uint32_t reserved46; 792 } SI32_AES_B_Type; 793 794 #ifdef __cplusplus 795 } 796 #endif 797 798 #endif // __SI32_AES_B_REGISTERS_H__ 799 800 //-eof-------------------------------------------------------------------------- 801 802
