1 //------------------------------------------------------------------------------ 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //------------------------------------------------------------------------------ 22 // 23 // Script: 0.57 24 // Version: 1 25 26 #ifndef __SI32_AES_A_REGISTERS_H__ 27 #define __SI32_AES_A_REGISTERS_H__ 28 29 #include <stdint.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 struct SI32_AES_A_CONTROL_Struct 36 { 37 union 38 { 39 struct 40 { 41 // AES Transfer Start 42 volatile uint32_t XFRSTA: 1; 43 // Key Capture Enable 44 volatile uint32_t KEYCPEN: 1; 45 // Encryption/Decryption Mode 46 volatile uint32_t EDMD: 1; 47 uint32_t reserved0: 5; 48 // Software Mode Enable 49 volatile uint32_t SWMDEN: 1; 50 // Bypass AES Operation Enable 51 volatile uint32_t BEN: 1; 52 // XOR Enable 53 volatile uint32_t XOREN: 2; 54 // Hardware Counter Mode Enable 55 volatile uint32_t HCTREN: 1; 56 // Hardware Cipher-Block Chaining Mode Enable 57 volatile uint32_t HCBCEN: 1; 58 uint32_t reserved1: 2; 59 // Keystore Size Select 60 volatile uint32_t KEYSIZE: 2; 61 uint32_t reserved2: 6; 62 // Error Interrupt Enable 63 volatile uint32_t ERRIEN: 1; 64 // Operation Complete Interrupt Enable 65 volatile uint32_t OCIEN: 1; 66 uint32_t reserved3: 4; 67 // AES Debug Mode 68 volatile uint32_t DBGMD: 1; 69 // Module Soft Reset 70 volatile uint32_t RESET: 1; 71 }; 72 volatile uint32_t U32; 73 }; 74 }; 75 76 #define SI32_AES_A_CONTROL_XFRSTA_MASK 0x00000001 77 #define SI32_AES_A_CONTROL_XFRSTA_SHIFT 0 78 // Start the AES operation. 79 #define SI32_AES_A_CONTROL_XFRSTA_START_VALUE 1 80 #define SI32_AES_A_CONTROL_XFRSTA_START_U32 \ 81 (SI32_AES_A_CONTROL_XFRSTA_START_VALUE << SI32_AES_A_CONTROL_XFRSTA_SHIFT) 82 83 #define SI32_AES_A_CONTROL_KEYCPEN_MASK 0x00000002 84 #define SI32_AES_A_CONTROL_KEYCPEN_SHIFT 1 85 // Disable key capture. 86 #define SI32_AES_A_CONTROL_KEYCPEN_DISABLED_VALUE 0 87 #define SI32_AES_A_CONTROL_KEYCPEN_DISABLED_U32 \ 88 (SI32_AES_A_CONTROL_KEYCPEN_DISABLED_VALUE << SI32_AES_A_CONTROL_KEYCPEN_SHIFT) 89 // Enable key capture. 90 #define SI32_AES_A_CONTROL_KEYCPEN_ENABLED_VALUE 1 91 #define SI32_AES_A_CONTROL_KEYCPEN_ENABLED_U32 \ 92 (SI32_AES_A_CONTROL_KEYCPEN_ENABLED_VALUE << SI32_AES_A_CONTROL_KEYCPEN_SHIFT) 93 94 #define SI32_AES_A_CONTROL_EDMD_MASK 0x00000004 95 #define SI32_AES_A_CONTROL_EDMD_SHIFT 2 96 // AES module performs a decryption operation 97 #define SI32_AES_A_CONTROL_EDMD_DECRYPT_VALUE 0 98 #define SI32_AES_A_CONTROL_EDMD_DECRYPT_U32 \ 99 (SI32_AES_A_CONTROL_EDMD_DECRYPT_VALUE << SI32_AES_A_CONTROL_EDMD_SHIFT) 100 // AES module performs an encryption operation. 101 #define SI32_AES_A_CONTROL_EDMD_ENCRYPT_VALUE 1 102 #define SI32_AES_A_CONTROL_EDMD_ENCRYPT_U32 \ 103 (SI32_AES_A_CONTROL_EDMD_ENCRYPT_VALUE << SI32_AES_A_CONTROL_EDMD_SHIFT) 104 105 #define SI32_AES_A_CONTROL_SWMDEN_MASK 0x00000100 106 #define SI32_AES_A_CONTROL_SWMDEN_SHIFT 8 107 // Disable software mode. 108 #define SI32_AES_A_CONTROL_SWMDEN_DISABLED_VALUE 0 109 #define SI32_AES_A_CONTROL_SWMDEN_DISABLED_U32 \ 110 (SI32_AES_A_CONTROL_SWMDEN_DISABLED_VALUE << SI32_AES_A_CONTROL_SWMDEN_SHIFT) 111 // Enable software mode. 112 #define SI32_AES_A_CONTROL_SWMDEN_ENABLED_VALUE 1 113 #define SI32_AES_A_CONTROL_SWMDEN_ENABLED_U32 \ 114 (SI32_AES_A_CONTROL_SWMDEN_ENABLED_VALUE << SI32_AES_A_CONTROL_SWMDEN_SHIFT) 115 116 #define SI32_AES_A_CONTROL_BEN_MASK 0x00000200 117 #define SI32_AES_A_CONTROL_BEN_SHIFT 9 118 // Do not bypass AES operations. 119 #define SI32_AES_A_CONTROL_BEN_DISABLED_VALUE 0 120 #define SI32_AES_A_CONTROL_BEN_DISABLED_U32 \ 121 (SI32_AES_A_CONTROL_BEN_DISABLED_VALUE << SI32_AES_A_CONTROL_BEN_SHIFT) 122 // Bypass AES operations. 123 #define SI32_AES_A_CONTROL_BEN_ENABLED_VALUE 1 124 #define SI32_AES_A_CONTROL_BEN_ENABLED_U32 \ 125 (SI32_AES_A_CONTROL_BEN_ENABLED_VALUE << SI32_AES_A_CONTROL_BEN_SHIFT) 126 127 #define SI32_AES_A_CONTROL_XOREN_MASK 0x00000C00 128 #define SI32_AES_A_CONTROL_XOREN_SHIFT 10 129 // Disable the XOR paths. 130 #define SI32_AES_A_CONTROL_XOREN_XOR_DISABLED_VALUE 0 131 #define SI32_AES_A_CONTROL_XOREN_XOR_DISABLED_U32 \ 132 (SI32_AES_A_CONTROL_XOREN_XOR_DISABLED_VALUE << SI32_AES_A_CONTROL_XOREN_SHIFT) 133 // Enable the XOR input path, disable the XOR output path. 134 #define SI32_AES_A_CONTROL_XOREN_XOR_INPUT_VALUE 1 135 #define SI32_AES_A_CONTROL_XOREN_XOR_INPUT_U32 \ 136 (SI32_AES_A_CONTROL_XOREN_XOR_INPUT_VALUE << SI32_AES_A_CONTROL_XOREN_SHIFT) 137 // Disable the XOR input path, enable the XOR output path. 138 #define SI32_AES_A_CONTROL_XOREN_XOR_OUTPUT_VALUE 2 139 #define SI32_AES_A_CONTROL_XOREN_XOR_OUTPUT_U32 \ 140 (SI32_AES_A_CONTROL_XOREN_XOR_OUTPUT_VALUE << SI32_AES_A_CONTROL_XOREN_SHIFT) 141 142 #define SI32_AES_A_CONTROL_HCTREN_MASK 0x00001000 143 #define SI32_AES_A_CONTROL_HCTREN_SHIFT 12 144 // Disable hardware counter mode. 145 #define SI32_AES_A_CONTROL_HCTREN_DISABLED_VALUE 0 146 #define SI32_AES_A_CONTROL_HCTREN_DISABLED_U32 \ 147 (SI32_AES_A_CONTROL_HCTREN_DISABLED_VALUE << SI32_AES_A_CONTROL_HCTREN_SHIFT) 148 // Enable hardware counter mode. 149 #define SI32_AES_A_CONTROL_HCTREN_ENABLED_VALUE 1 150 #define SI32_AES_A_CONTROL_HCTREN_ENABLED_U32 \ 151 (SI32_AES_A_CONTROL_HCTREN_ENABLED_VALUE << SI32_AES_A_CONTROL_HCTREN_SHIFT) 152 153 #define SI32_AES_A_CONTROL_HCBCEN_MASK 0x00002000 154 #define SI32_AES_A_CONTROL_HCBCEN_SHIFT 13 155 // Disable hardware cipher-block chaining (CBC) mode. 156 #define SI32_AES_A_CONTROL_HCBCEN_DISABLED_VALUE 0 157 #define SI32_AES_A_CONTROL_HCBCEN_DISABLED_U32 \ 158 (SI32_AES_A_CONTROL_HCBCEN_DISABLED_VALUE << SI32_AES_A_CONTROL_HCBCEN_SHIFT) 159 // Enable hardware cipher-block chaining (CBC) mode. 160 #define SI32_AES_A_CONTROL_HCBCEN_ENABLED_VALUE 1 161 #define SI32_AES_A_CONTROL_HCBCEN_ENABLED_U32 \ 162 (SI32_AES_A_CONTROL_HCBCEN_ENABLED_VALUE << SI32_AES_A_CONTROL_HCBCEN_SHIFT) 163 164 #define SI32_AES_A_CONTROL_KEYSIZE_MASK 0x00030000 165 #define SI32_AES_A_CONTROL_KEYSIZE_SHIFT 16 166 // Key is composed of 128 bits. 167 #define SI32_AES_A_CONTROL_KEYSIZE_KEY128_VALUE 0 168 #define SI32_AES_A_CONTROL_KEYSIZE_KEY128_U32 \ 169 (SI32_AES_A_CONTROL_KEYSIZE_KEY128_VALUE << SI32_AES_A_CONTROL_KEYSIZE_SHIFT) 170 // Key is composed of 192 bits. 171 #define SI32_AES_A_CONTROL_KEYSIZE_KEY192_VALUE 1 172 #define SI32_AES_A_CONTROL_KEYSIZE_KEY192_U32 \ 173 (SI32_AES_A_CONTROL_KEYSIZE_KEY192_VALUE << SI32_AES_A_CONTROL_KEYSIZE_SHIFT) 174 // Key is composed of 256 bits. 175 #define SI32_AES_A_CONTROL_KEYSIZE_KEY256_VALUE 2 176 #define SI32_AES_A_CONTROL_KEYSIZE_KEY256_U32 \ 177 (SI32_AES_A_CONTROL_KEYSIZE_KEY256_VALUE << SI32_AES_A_CONTROL_KEYSIZE_SHIFT) 178 179 #define SI32_AES_A_CONTROL_ERRIEN_MASK 0x01000000 180 #define SI32_AES_A_CONTROL_ERRIEN_SHIFT 24 181 // Disable the error interrupt. 182 #define SI32_AES_A_CONTROL_ERRIEN_DISABLED_VALUE 0 183 #define SI32_AES_A_CONTROL_ERRIEN_DISABLED_U32 \ 184 (SI32_AES_A_CONTROL_ERRIEN_DISABLED_VALUE << SI32_AES_A_CONTROL_ERRIEN_SHIFT) 185 // Enable the error interrupt. 186 #define SI32_AES_A_CONTROL_ERRIEN_ENABLED_VALUE 1 187 #define SI32_AES_A_CONTROL_ERRIEN_ENABLED_U32 \ 188 (SI32_AES_A_CONTROL_ERRIEN_ENABLED_VALUE << SI32_AES_A_CONTROL_ERRIEN_SHIFT) 189 190 #define SI32_AES_A_CONTROL_OCIEN_MASK 0x02000000 191 #define SI32_AES_A_CONTROL_OCIEN_SHIFT 25 192 // Disable the operation complete interrupt. 193 #define SI32_AES_A_CONTROL_OCIEN_DISABLED_VALUE 0 194 #define SI32_AES_A_CONTROL_OCIEN_DISABLED_U32 \ 195 (SI32_AES_A_CONTROL_OCIEN_DISABLED_VALUE << SI32_AES_A_CONTROL_OCIEN_SHIFT) 196 // Enable the operation complete interrupt. 197 #define SI32_AES_A_CONTROL_OCIEN_ENABLED_VALUE 1 198 #define SI32_AES_A_CONTROL_OCIEN_ENABLED_U32 \ 199 (SI32_AES_A_CONTROL_OCIEN_ENABLED_VALUE << SI32_AES_A_CONTROL_OCIEN_SHIFT) 200 201 #define SI32_AES_A_CONTROL_DBGMD_MASK 0x40000000 202 #define SI32_AES_A_CONTROL_DBGMD_SHIFT 30 203 // A debug breakpoint will cause the AES module to halt. 204 #define SI32_AES_A_CONTROL_DBGMD_HALT_VALUE 0 205 #define SI32_AES_A_CONTROL_DBGMD_HALT_U32 \ 206 (SI32_AES_A_CONTROL_DBGMD_HALT_VALUE << SI32_AES_A_CONTROL_DBGMD_SHIFT) 207 // The AES module will continue to operate while the core is halted in debug mode. 208 #define SI32_AES_A_CONTROL_DBGMD_RUN_VALUE 1 209 #define SI32_AES_A_CONTROL_DBGMD_RUN_U32 \ 210 (SI32_AES_A_CONTROL_DBGMD_RUN_VALUE << SI32_AES_A_CONTROL_DBGMD_SHIFT) 211 212 #define SI32_AES_A_CONTROL_RESET_MASK 0x80000000 213 #define SI32_AES_A_CONTROL_RESET_SHIFT 31 214 // AES module is not in soft reset. 215 #define SI32_AES_A_CONTROL_RESET_INACTIVE_VALUE 0U 216 #define SI32_AES_A_CONTROL_RESET_INACTIVE_U32 \ 217 (SI32_AES_A_CONTROL_RESET_INACTIVE_VALUE << SI32_AES_A_CONTROL_RESET_SHIFT) 218 // AES module is in soft reset and none of the module bits can be accessed. 219 #define SI32_AES_A_CONTROL_RESET_ACTIVE_VALUE 1U 220 #define SI32_AES_A_CONTROL_RESET_ACTIVE_U32 \ 221 (SI32_AES_A_CONTROL_RESET_ACTIVE_VALUE << SI32_AES_A_CONTROL_RESET_SHIFT) 222 223 224 225 struct SI32_AES_A_XFRSIZE_Struct 226 { 227 union 228 { 229 struct 230 { 231 // Transfer Size 232 volatile uint32_t XFRSIZE_BITS: 11; 233 uint32_t reserved0: 21; 234 }; 235 volatile uint32_t U32; 236 }; 237 }; 238 239 #define SI32_AES_A_XFRSIZE_XFRSIZE_MASK 0x000007FF 240 #define SI32_AES_A_XFRSIZE_XFRSIZE_SHIFT 0 241 242 243 244 struct SI32_AES_A_DATAFIFO_Struct 245 { 246 union 247 { 248 struct 249 { 250 // Input/Output Data FIFO Access 251 volatile uint32_t DATAFIFO_BITS; 252 }; 253 volatile uint32_t U32; 254 }; 255 }; 256 257 #define SI32_AES_A_DATAFIFO_DATAFIFO_MASK 0xFFFFFFFF 258 #define SI32_AES_A_DATAFIFO_DATAFIFO_SHIFT 0 259 260 261 262 struct SI32_AES_A_XORFIFO_Struct 263 { 264 union 265 { 266 struct 267 { 268 // XOR Data FIFO Access 269 volatile uint32_t XORFIFO_BITS; 270 }; 271 volatile uint32_t U32; 272 }; 273 }; 274 275 #define SI32_AES_A_XORFIFO_XORFIFO_MASK 0xFFFFFFFF 276 #define SI32_AES_A_XORFIFO_XORFIFO_SHIFT 0 277 278 279 280 struct SI32_AES_A_HWKEY0_Struct 281 { 282 union 283 { 284 struct 285 { 286 // Hardware Key Word 0 287 volatile uint32_t HWKEY0_BITS; 288 }; 289 volatile uint32_t U32; 290 }; 291 }; 292 293 #define SI32_AES_A_HWKEY0_HWKEY0_MASK 0xFFFFFFFF 294 #define SI32_AES_A_HWKEY0_HWKEY0_SHIFT 0 295 296 297 298 struct SI32_AES_A_HWKEY1_Struct 299 { 300 union 301 { 302 struct 303 { 304 // Hardware Key Word 1 305 volatile uint32_t HWKEY1_BITS; 306 }; 307 volatile uint32_t U32; 308 }; 309 }; 310 311 #define SI32_AES_A_HWKEY1_HWKEY1_MASK 0xFFFFFFFF 312 #define SI32_AES_A_HWKEY1_HWKEY1_SHIFT 0 313 314 315 316 struct SI32_AES_A_HWKEY2_Struct 317 { 318 union 319 { 320 struct 321 { 322 // Hardware Key Word 2 323 volatile uint32_t HWKEY2_BITS; 324 }; 325 volatile uint32_t U32; 326 }; 327 }; 328 329 #define SI32_AES_A_HWKEY2_HWKEY2_MASK 0xFFFFFFFF 330 #define SI32_AES_A_HWKEY2_HWKEY2_SHIFT 0 331 332 333 334 struct SI32_AES_A_HWKEY3_Struct 335 { 336 union 337 { 338 struct 339 { 340 // Hardware Key Word 3 341 volatile uint32_t HWKEY3_BITS; 342 }; 343 volatile uint32_t U32; 344 }; 345 }; 346 347 #define SI32_AES_A_HWKEY3_HWKEY3_MASK 0xFFFFFFFF 348 #define SI32_AES_A_HWKEY3_HWKEY3_SHIFT 0 349 350 351 352 struct SI32_AES_A_HWKEY4_Struct 353 { 354 union 355 { 356 struct 357 { 358 // Hardware Key Word 4 359 volatile uint32_t HWKEY4_BITS; 360 }; 361 volatile uint32_t U32; 362 }; 363 }; 364 365 #define SI32_AES_A_HWKEY4_HWKEY4_MASK 0xFFFFFFFF 366 #define SI32_AES_A_HWKEY4_HWKEY4_SHIFT 0 367 368 369 370 struct SI32_AES_A_HWKEY5_Struct 371 { 372 union 373 { 374 struct 375 { 376 // Hardware Key Word 5 377 volatile uint32_t HWKEY5_BITS; 378 }; 379 volatile uint32_t U32; 380 }; 381 }; 382 383 #define SI32_AES_A_HWKEY5_HWKEY5_MASK 0xFFFFFFFF 384 #define SI32_AES_A_HWKEY5_HWKEY5_SHIFT 0 385 386 387 388 struct SI32_AES_A_HWKEY6_Struct 389 { 390 union 391 { 392 struct 393 { 394 // Hardware Key Word 6 395 volatile uint32_t HWKEY6_BITS; 396 }; 397 volatile uint32_t U32; 398 }; 399 }; 400 401 #define SI32_AES_A_HWKEY6_HWKEY6_MASK 0xFFFFFFFF 402 #define SI32_AES_A_HWKEY6_HWKEY6_SHIFT 0 403 404 405 406 struct SI32_AES_A_HWKEY7_Struct 407 { 408 union 409 { 410 struct 411 { 412 // Hardware Key Word 7 413 volatile uint32_t HWKEY7_BITS; 414 }; 415 volatile uint32_t U32; 416 }; 417 }; 418 419 #define SI32_AES_A_HWKEY7_HWKEY7_MASK 0xFFFFFFFF 420 #define SI32_AES_A_HWKEY7_HWKEY7_SHIFT 0 421 422 423 424 struct SI32_AES_A_HWCTR0_Struct 425 { 426 union 427 { 428 struct 429 { 430 // Hardware Counter Word 0 431 volatile uint32_t HWCTR0_BITS; 432 }; 433 volatile uint32_t U32; 434 }; 435 }; 436 437 #define SI32_AES_A_HWCTR0_HWCTR0_MASK 0xFFFFFFFF 438 #define SI32_AES_A_HWCTR0_HWCTR0_SHIFT 0 439 440 441 442 struct SI32_AES_A_HWCTR1_Struct 443 { 444 union 445 { 446 struct 447 { 448 // Hardware Counter Word 1 449 volatile uint32_t HWCTR1_BITS; 450 }; 451 volatile uint32_t U32; 452 }; 453 }; 454 455 #define SI32_AES_A_HWCTR1_HWCTR1_MASK 0xFFFFFFFF 456 #define SI32_AES_A_HWCTR1_HWCTR1_SHIFT 0 457 458 459 460 struct SI32_AES_A_HWCTR2_Struct 461 { 462 union 463 { 464 struct 465 { 466 // Hardware Counter Word 2 467 volatile uint32_t HWCTR2_BITS; 468 }; 469 volatile uint32_t U32; 470 }; 471 }; 472 473 #define SI32_AES_A_HWCTR2_HWCTR2_MASK 0xFFFFFFFF 474 #define SI32_AES_A_HWCTR2_HWCTR2_SHIFT 0 475 476 477 478 struct SI32_AES_A_HWCTR3_Struct 479 { 480 union 481 { 482 struct 483 { 484 // Hardware Counter Word 3 485 volatile uint32_t HWCTR3_BITS; 486 }; 487 volatile uint32_t U32; 488 }; 489 }; 490 491 #define SI32_AES_A_HWCTR3_HWCTR3_MASK 0xFFFFFFFF 492 #define SI32_AES_A_HWCTR3_HWCTR3_SHIFT 0 493 494 495 496 struct SI32_AES_A_STATUS_Struct 497 { 498 union 499 { 500 struct 501 { 502 // Input/Output Data FIFO Underrun Flag 503 volatile uint32_t DURF: 1; 504 // Input/Output Data FIFO Overrun Flag 505 volatile uint32_t DORF: 1; 506 // XOR Data FIFO Overrun Flag 507 volatile uint32_t XORF: 1; 508 uint32_t reserved0: 1; 509 // Input/Output Data FIFO Level 510 volatile uint32_t DFIFOLVL: 3; 511 uint32_t reserved1: 1; 512 // XOR Data FIFO Level 513 volatile uint32_t XFIFOLVL: 3; 514 uint32_t reserved2: 5; 515 // Module Busy Flag 516 volatile uint32_t BUSYF: 1; 517 uint32_t reserved3: 13; 518 // Error Interrupt Flag 519 volatile uint32_t ERRI: 1; 520 // Operation Complete Interrupt Flag 521 volatile uint32_t OCI: 1; 522 }; 523 volatile uint32_t U32; 524 }; 525 }; 526 527 #define SI32_AES_A_STATUS_DURF_MASK 0x00000001 528 #define SI32_AES_A_STATUS_DURF_SHIFT 0 529 // No input/output data FIFO underrun. 530 #define SI32_AES_A_STATUS_DURF_NOT_SET_VALUE 0 531 #define SI32_AES_A_STATUS_DURF_NOT_SET_U32 \ 532 (SI32_AES_A_STATUS_DURF_NOT_SET_VALUE << SI32_AES_A_STATUS_DURF_SHIFT) 533 // An input/output data FIFO underrun has occurred. 534 #define SI32_AES_A_STATUS_DURF_SET_VALUE 1 535 #define SI32_AES_A_STATUS_DURF_SET_U32 \ 536 (SI32_AES_A_STATUS_DURF_SET_VALUE << SI32_AES_A_STATUS_DURF_SHIFT) 537 538 #define SI32_AES_A_STATUS_DORF_MASK 0x00000002 539 #define SI32_AES_A_STATUS_DORF_SHIFT 1 540 // No input/output data FIFO overrun. 541 #define SI32_AES_A_STATUS_DORF_NOT_SET_VALUE 0 542 #define SI32_AES_A_STATUS_DORF_NOT_SET_U32 \ 543 (SI32_AES_A_STATUS_DORF_NOT_SET_VALUE << SI32_AES_A_STATUS_DORF_SHIFT) 544 // An input/output data FIFO overrun has occurred. 545 #define SI32_AES_A_STATUS_DORF_SET_VALUE 1 546 #define SI32_AES_A_STATUS_DORF_SET_U32 \ 547 (SI32_AES_A_STATUS_DORF_SET_VALUE << SI32_AES_A_STATUS_DORF_SHIFT) 548 549 #define SI32_AES_A_STATUS_XORF_MASK 0x00000004 550 #define SI32_AES_A_STATUS_XORF_SHIFT 2 551 // No XOR data FIFO overrun. 552 #define SI32_AES_A_STATUS_XORF_NOT_SET_VALUE 0 553 #define SI32_AES_A_STATUS_XORF_NOT_SET_U32 \ 554 (SI32_AES_A_STATUS_XORF_NOT_SET_VALUE << SI32_AES_A_STATUS_XORF_SHIFT) 555 // An XOR data FIFO overrun has occurred. 556 #define SI32_AES_A_STATUS_XORF_SET_VALUE 1 557 #define SI32_AES_A_STATUS_XORF_SET_U32 \ 558 (SI32_AES_A_STATUS_XORF_SET_VALUE << SI32_AES_A_STATUS_XORF_SHIFT) 559 560 #define SI32_AES_A_STATUS_DFIFOLVL_MASK 0x00000070 561 #define SI32_AES_A_STATUS_DFIFOLVL_SHIFT 4 562 // Input/Output data FIFO is empty. 563 #define SI32_AES_A_STATUS_DFIFOLVL_EMPTY_VALUE 0 564 #define SI32_AES_A_STATUS_DFIFOLVL_EMPTY_U32 \ 565 (SI32_AES_A_STATUS_DFIFOLVL_EMPTY_VALUE << SI32_AES_A_STATUS_DFIFOLVL_SHIFT) 566 // Input/Output data FIFO contains 1 word. 567 #define SI32_AES_A_STATUS_DFIFOLVL_1WORD_VALUE 1 568 #define SI32_AES_A_STATUS_DFIFOLVL_1WORD_U32 \ 569 (SI32_AES_A_STATUS_DFIFOLVL_1WORD_VALUE << SI32_AES_A_STATUS_DFIFOLVL_SHIFT) 570 // Input/Output data FIFO contains 2 words. 571 #define SI32_AES_A_STATUS_DFIFOLVL_2WORDS_VALUE 2 572 #define SI32_AES_A_STATUS_DFIFOLVL_2WORDS_U32 \ 573 (SI32_AES_A_STATUS_DFIFOLVL_2WORDS_VALUE << SI32_AES_A_STATUS_DFIFOLVL_SHIFT) 574 // Input/Output data FIFO contains 3 words. 575 #define SI32_AES_A_STATUS_DFIFOLVL_3WORDS_VALUE 3 576 #define SI32_AES_A_STATUS_DFIFOLVL_3WORDS_U32 \ 577 (SI32_AES_A_STATUS_DFIFOLVL_3WORDS_VALUE << SI32_AES_A_STATUS_DFIFOLVL_SHIFT) 578 // Input/Output data FIFO contains 4 words (full). 579 #define SI32_AES_A_STATUS_DFIFOLVL_FULL_VALUE 4 580 #define SI32_AES_A_STATUS_DFIFOLVL_FULL_U32 \ 581 (SI32_AES_A_STATUS_DFIFOLVL_FULL_VALUE << SI32_AES_A_STATUS_DFIFOLVL_SHIFT) 582 583 #define SI32_AES_A_STATUS_XFIFOLVL_MASK 0x00000700 584 #define SI32_AES_A_STATUS_XFIFOLVL_SHIFT 8 585 // XOR data FIFO is empty. 586 #define SI32_AES_A_STATUS_XFIFOLVL_EMPTY_VALUE 0 587 #define SI32_AES_A_STATUS_XFIFOLVL_EMPTY_U32 \ 588 (SI32_AES_A_STATUS_XFIFOLVL_EMPTY_VALUE << SI32_AES_A_STATUS_XFIFOLVL_SHIFT) 589 // XOR data FIFO contains 1 word. 590 #define SI32_AES_A_STATUS_XFIFOLVL_1WORD_VALUE 1 591 #define SI32_AES_A_STATUS_XFIFOLVL_1WORD_U32 \ 592 (SI32_AES_A_STATUS_XFIFOLVL_1WORD_VALUE << SI32_AES_A_STATUS_XFIFOLVL_SHIFT) 593 // XOR data FIFO contains 2 words. 594 #define SI32_AES_A_STATUS_XFIFOLVL_2WORDS_VALUE 2 595 #define SI32_AES_A_STATUS_XFIFOLVL_2WORDS_U32 \ 596 (SI32_AES_A_STATUS_XFIFOLVL_2WORDS_VALUE << SI32_AES_A_STATUS_XFIFOLVL_SHIFT) 597 // XOR data FIFO contains 3 words. 598 #define SI32_AES_A_STATUS_XFIFOLVL_3WORDS_VALUE 3 599 #define SI32_AES_A_STATUS_XFIFOLVL_3WORDS_U32 \ 600 (SI32_AES_A_STATUS_XFIFOLVL_3WORDS_VALUE << SI32_AES_A_STATUS_XFIFOLVL_SHIFT) 601 // XOR data FIFO contains 4 words (full). 602 #define SI32_AES_A_STATUS_XFIFOLVL_FULL_VALUE 4 603 #define SI32_AES_A_STATUS_XFIFOLVL_FULL_U32 \ 604 (SI32_AES_A_STATUS_XFIFOLVL_FULL_VALUE << SI32_AES_A_STATUS_XFIFOLVL_SHIFT) 605 606 #define SI32_AES_A_STATUS_BUSYF_MASK 0x00010000 607 #define SI32_AES_A_STATUS_BUSYF_SHIFT 16 608 // AES module is not busy. 609 #define SI32_AES_A_STATUS_BUSYF_NOT_SET_VALUE 0 610 #define SI32_AES_A_STATUS_BUSYF_NOT_SET_U32 \ 611 (SI32_AES_A_STATUS_BUSYF_NOT_SET_VALUE << SI32_AES_A_STATUS_BUSYF_SHIFT) 612 // AES module is completing an operation. 613 #define SI32_AES_A_STATUS_BUSYF_SET_VALUE 1 614 #define SI32_AES_A_STATUS_BUSYF_SET_U32 \ 615 (SI32_AES_A_STATUS_BUSYF_SET_VALUE << SI32_AES_A_STATUS_BUSYF_SHIFT) 616 617 #define SI32_AES_A_STATUS_ERRI_MASK 0x40000000 618 #define SI32_AES_A_STATUS_ERRI_SHIFT 30 619 // AES error interrupt has not occurred. 620 #define SI32_AES_A_STATUS_ERRI_NOT_SET_VALUE 0 621 #define SI32_AES_A_STATUS_ERRI_NOT_SET_U32 \ 622 (SI32_AES_A_STATUS_ERRI_NOT_SET_VALUE << SI32_AES_A_STATUS_ERRI_SHIFT) 623 // AES error interrupt has occurred. 624 #define SI32_AES_A_STATUS_ERRI_SET_VALUE 1 625 #define SI32_AES_A_STATUS_ERRI_SET_U32 \ 626 (SI32_AES_A_STATUS_ERRI_SET_VALUE << SI32_AES_A_STATUS_ERRI_SHIFT) 627 628 #define SI32_AES_A_STATUS_OCI_MASK 0x80000000 629 #define SI32_AES_A_STATUS_OCI_SHIFT 31 630 // AES operation complete interrupt has not occurred. 631 #define SI32_AES_A_STATUS_OCI_NOT_SET_VALUE 0U 632 #define SI32_AES_A_STATUS_OCI_NOT_SET_U32 \ 633 (SI32_AES_A_STATUS_OCI_NOT_SET_VALUE << SI32_AES_A_STATUS_OCI_SHIFT) 634 // AES operation complete interrupt occurred. 635 #define SI32_AES_A_STATUS_OCI_SET_VALUE 1U 636 #define SI32_AES_A_STATUS_OCI_SET_U32 \ 637 (SI32_AES_A_STATUS_OCI_SET_VALUE << SI32_AES_A_STATUS_OCI_SHIFT) 638 639 640 641 typedef struct SI32_AES_A_Struct 642 { 643 struct SI32_AES_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 644 volatile uint32_t CONTROL_SET; 645 volatile uint32_t CONTROL_CLR; 646 uint32_t reserved0; 647 struct SI32_AES_A_XFRSIZE_Struct XFRSIZE ; // Base Address + 0x10 648 uint32_t reserved1; 649 uint32_t reserved2; 650 uint32_t reserved3; 651 struct SI32_AES_A_DATAFIFO_Struct DATAFIFO ; // Base Address + 0x20 652 uint32_t reserved4; 653 uint32_t reserved5; 654 uint32_t reserved6; 655 struct SI32_AES_A_XORFIFO_Struct XORFIFO ; // Base Address + 0x30 656 uint32_t reserved7; 657 uint32_t reserved8; 658 uint32_t reserved9; 659 struct SI32_AES_A_HWKEY0_Struct HWKEY0 ; // Base Address + 0x40 660 uint32_t reserved10; 661 uint32_t reserved11; 662 uint32_t reserved12; 663 struct SI32_AES_A_HWKEY1_Struct HWKEY1 ; // Base Address + 0x50 664 uint32_t reserved13; 665 uint32_t reserved14; 666 uint32_t reserved15; 667 struct SI32_AES_A_HWKEY2_Struct HWKEY2 ; // Base Address + 0x60 668 uint32_t reserved16; 669 uint32_t reserved17; 670 uint32_t reserved18; 671 struct SI32_AES_A_HWKEY3_Struct HWKEY3 ; // Base Address + 0x70 672 uint32_t reserved19; 673 uint32_t reserved20; 674 uint32_t reserved21; 675 struct SI32_AES_A_HWKEY4_Struct HWKEY4 ; // Base Address + 0x80 676 uint32_t reserved22; 677 uint32_t reserved23; 678 uint32_t reserved24; 679 struct SI32_AES_A_HWKEY5_Struct HWKEY5 ; // Base Address + 0x90 680 uint32_t reserved25; 681 uint32_t reserved26; 682 uint32_t reserved27; 683 struct SI32_AES_A_HWKEY6_Struct HWKEY6 ; // Base Address + 0xa0 684 uint32_t reserved28; 685 uint32_t reserved29; 686 uint32_t reserved30; 687 struct SI32_AES_A_HWKEY7_Struct HWKEY7 ; // Base Address + 0xb0 688 uint32_t reserved31; 689 uint32_t reserved32; 690 uint32_t reserved33; 691 struct SI32_AES_A_HWCTR0_Struct HWCTR0 ; // Base Address + 0xc0 692 uint32_t reserved34; 693 uint32_t reserved35; 694 uint32_t reserved36; 695 struct SI32_AES_A_HWCTR1_Struct HWCTR1 ; // Base Address + 0xd0 696 uint32_t reserved37; 697 uint32_t reserved38; 698 uint32_t reserved39; 699 struct SI32_AES_A_HWCTR2_Struct HWCTR2 ; // Base Address + 0xe0 700 uint32_t reserved40; 701 uint32_t reserved41; 702 uint32_t reserved42; 703 struct SI32_AES_A_HWCTR3_Struct HWCTR3 ; // Base Address + 0xf0 704 uint32_t reserved43; 705 uint32_t reserved44; 706 uint32_t reserved45; 707 struct SI32_AES_A_STATUS_Struct STATUS ; // Base Address + 0x100 708 volatile uint32_t STATUS_SET; 709 volatile uint32_t STATUS_CLR; 710 uint32_t reserved46; 711 } SI32_AES_A_Type; 712 713 #ifdef __cplusplus 714 } 715 #endif 716 717 #endif // __SI32_AES_A_REGISTERS_H__ 718 719 //-eof-------------------------------------------------------------------------- 720 721
