1 /***************************************************************************//**
2 * @file
3 * @brief Universal asynchronous receiver/transmitter (EUSART) peripheral API
4 *******************************************************************************
5 * # License
6 * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
7 *******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 ******************************************************************************/
30
31 #ifndef EM_EUSART_H
32 #define EM_EUSART_H
33 #include "em_device.h"
34 #if defined(EUART_PRESENT) || defined(EUSART_PRESENT)
35 #include "sl_enum.h"
36 #include "em_eusart_compat.h"
37 #include <stdbool.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* *INDENT-OFF* */
44 // *****************************************************************************
45 /// @addtogroup eusart EUSART - Extended USART
46 /// @brief Extended Universal Synchronous/Asynchronous Receiver/Transmitter
47 ///
48 /// @li @ref eusart_intro
49 /// @li @ref eusart_example
50 /// @li @ref eusart_em2
51 ///
52 ///@n @section eusart_intro Introduction
53 /// This module contains functions to control the Enhanced Universal Synchronous
54 /// / Asynchronous Receiver / Transmitter controller(s) (EUSART) peripheral of Silicon
55 /// Labs' 32-bit MCUs and SoCs. EUSART can be used as a UART and can,
56 /// therefore, be connected to an external transceiver to communicate with
57 /// another host using the serial link.
58 ///
59 /// It supports full duplex asynchronous UART communication as well as RS-485,
60 /// SPI, MicroWire, and 3-wire. It can also interface with ISO7816 Smart-Cards,
61 /// and IrDA devices.
62 ///
63 /// EUSART has a wide selection of operating modes, frame formats, and baud rates.
64 /// All features are supported through the API of this module.
65 ///
66 /// This module does not support DMA configuration. UARTDRV and SPIDRV drivers
67 /// provide full support for DMA and more.
68 ///
69 ///@n @section eusart_example Example
70 ///
71 /// EUSART Async TX example:
72 /// @code{.c}
73 /// {
74 /// EUSART_UartInit_TypeDef init = EUSART_UART_INIT_DEFAULT_HF;
75 ///
76 /// // Configure the clocks.
77 /// CMU_ClockSelectSet(cmuClock_EUSART0CLK, cmuSelect_EM01GRPCCLK);
78 /// CMU_ClockEnable(cmuClock_EUSART0CLK, true);
79 /// // Initialize the EUSART
80 /// EUSART_UartInitHf(EUSART0, &init);
81 /// EUSART_Tx(EUSART0, data);
82 /// }
83 ///
84 /// @endcode
85 ///
86 /// EUSART Sync SPI Transaction example:
87 /// @code{.c}
88 /// {
89 /// EUSART_SpiInit_TypeDef init_master = EUSART_SPI_MASTER_INIT_DEFAULT_HF;
90 ///
91 /// // Configure the clocks.
92 /// CMU_ClockSelectSet(cmuClock_EM01GRPCCLK, cmuSelect_HFRCODPLL);
93 /// CMU_ClockEnable(cmuClock_EUSART1, true);
94 /// CMU_ClockEnable(cmuClock_GPIO, true);
95 ///
96 /// //Configure the SPI ports
97 /// GPIO_PinModeSet(sclk_port, sclk_pin, gpioModePushPull, 0);
98 /// GPIO_PinModeSet(mosi_port, mosi_pin, gpioModePushPull, 0);
99 /// GPIO_PinModeSet(mosi_port, miso_pin, gpioModeInput, 0);
100 ///
101 /// // Connect EUSART to ports
102 /// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].TXROUTE = (mosi_port << _GPIO_EUSART_TXROUTE_PORT_SHIFT)
103 /// | (mosi_pin << _GPIO_EUSART_TXROUTE_PIN_SHIFT);
104 /// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].RXROUTE = (miso_port << _GPIO_EUSART_RXROUTE_PORT_SHIFT)
105 /// | (miso_pin << _GPIO_EUSART_RXROUTE_PIN_SHIFT);
106 /// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].SCLKROUTE = (sclk_port << _GPIO_EUSART_SCLKROUTE_PORT_SHIFT)
107 /// | (sclk_pin << _GPIO_EUSART_SCLKROUTE_PIN_SHIFT);
108 /// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN;
109 ///
110 /// // Initialize the EUSART
111 /// EUSART_SpiInit(EUSART1, &init_master);
112 /// EUSART_Spi_TxRx(EUSART1, data);
113 /// }
114 ///
115 /// @endcode
116 ///@n @section eusart_em2 EM2 guidelines for non EM2-Capable instances
117 ///
118 /// @note EUSART instances located in the PD1 power domain are non EM2-capable.
119 /// The <b>EUSART_EM2_CAPABLE()</b> and <b>EUSART_NOT_EM2_CAPABLE()</b> macros can be used
120 /// to determine whether or not a EUSART instance is EM2-Capable.
121 ///
122 /// Follow theses steps when entering in EM2:
123 /// -# Wait for the current transaction to complete with TXCIF interrupt
124 /// -# Disable TX and RX using TXDIS and RXDIS cmd
125 /// -# Poll for EUSARTn_SYNCBUSY.TXDIS and EUSARTn_SYNCBUSY.RXDIS to go low
126 /// -# Wait for EUSARTn_STATUS.TXENS and EUSARTn_STATUS.RXENS to go low
127 /// -# Disable SCLKPEN and CSPEN in GPIO if they were previously enabled
128 /// -# Enter EM2
129 ///
130 /// On wakeup from EM2, EUSART transmitter/receiver and relevant GPIO
131 /// (SCLKPEN and CSPEN) must be re-enabled. For example:
132 ///
133 /// @code{.c}
134 /// {
135 /// // Enable TX and RX
136 /// EUSART_Enable(EUSART0, eusartEnable);
137 /// BUS_RegMaskedWrite(&GPIO->EUSARTROUTE[EUSART_NUM(EUSART0)].ROUTEEN,
138 /// _GPIO_EUSART_ROUTEEN_TXPEN_MASK | _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK,
139 /// GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN);
140 /// }
141 /// @endcode
142 ///
143 /// @{
144 // *****************************************************************************
145 /* *INDENT-ON* */
146
147 /*******************************************************************************
148 ******************************* DEFINES ***********************************
149 ******************************************************************************/
150
151 /** Define EUSART FIFO Depth information */
152 #if !defined(EUSART_FIFO_DEPTH)
153 #if defined(EUART_PRESENT)
154 #define EUSART0_FIFO_DEPTH 4
155 #elif defined(EUSART_PRESENT)
156 #define EUSART0_FIFO_DEPTH 16
157 #endif /* EUART_PRESENT */
158 #define EUSART1_FIFO_DEPTH EUSART0_FIFO_DEPTH
159 #define EUSART2_FIFO_DEPTH EUSART0_FIFO_DEPTH
160 #define EUSART3_FIFO_DEPTH EUSART0_FIFO_DEPTH
161 #define EUSART4_FIFO_DEPTH EUSART0_FIFO_DEPTH
162
163 #define EUSART_FIFO_DEPTH(n) (((n) == 0) ? EUSART0_FIFO_DEPTH \
164 : ((n) == 1) ? EUSART1_FIFO_DEPTH \
165 : ((n) == 2) ? EUSART2_FIFO_DEPTH \
166 : ((n) == 3) ? EUSART3_FIFO_DEPTH \
167 : ((n) == 4) ? EUSART4_FIFO_DEPTH \
168 : 0x0UL)
169 #endif /* EUSART_FIFO_DEPTH */
170
171 /*******************************************************************************
172 ******************************** ENUMS ************************************
173 ******************************************************************************/
174
175 /// Enable selection.
176 typedef enum {
177 /// Disable the peripheral.
178 eusartDisable = 0x0,
179
180 /// Enable receiver only, transmitter disabled.
181 eusartEnableRx = (EUSART_CMD_RXEN | EUSART_CMD_TXDIS),
182
183 /// Enable transmitter only, receiver disabled.
184 eusartEnableTx = (EUSART_CMD_TXEN | EUSART_CMD_RXDIS),
185
186 /// Enable both receiver and transmitter.
187 eusartEnable = (EUSART_CMD_RXEN | EUSART_CMD_TXEN)
188 } EUSART_Enable_TypeDef;
189
190 /// Data bit selection.
191 typedef enum {
192 eusartDataBits7 = EUSART_FRAMECFG_DATABITS_SEVEN, ///< 7 data bits.
193 eusartDataBits8 = EUSART_FRAMECFG_DATABITS_EIGHT, ///< 8 data bits.
194 eusartDataBits9 = EUSART_FRAMECFG_DATABITS_NINE, ///< 9 data bits.
195 #if defined(EUSART_PRESENT)
196 eusartDataBits10 = EUSART_FRAMECFG_DATABITS_TEN, ///< 10 data bits, SPI mode only.
197 eusartDataBits11 = EUSART_FRAMECFG_DATABITS_ELEVEN, ///< 11 data bits, SPI mode only.
198 eusartDataBits12 = EUSART_FRAMECFG_DATABITS_TWELVE, ///< 12 data bits, SPI mode only.
199 eusartDataBits13 = EUSART_FRAMECFG_DATABITS_THIRTEEN, ///< 13 data bits, SPI mode only.
200 eusartDataBits14 = EUSART_FRAMECFG_DATABITS_FOURTEEN, ///< 14 data bits, SPI mode only.
201 eusartDataBits15 = EUSART_FRAMECFG_DATABITS_FIFTEEN, ///< 15 data bits, SPI mode only.
202 eusartDataBits16 = EUSART_FRAMECFG_DATABITS_SIXTEEN, ///< 16 data bits, SPI mode only.
203 #endif
204 } EUSART_Databits_TypeDef;
205
206 /// Parity selection.
207 typedef enum {
208 eusartNoParity = EUSART_FRAMECFG_PARITY_NONE, ///< No parity.
209 eusartEvenParity = EUSART_FRAMECFG_PARITY_EVEN, ///< Even parity.
210 eusartOddParity = EUSART_FRAMECFG_PARITY_ODD ///< Odd parity.
211 } EUSART_Parity_TypeDef;
212
213 /// Stop bits selection.
214 typedef enum {
215 eusartStopbits0p5 = EUSART_FRAMECFG_STOPBITS_HALF, ///< 0.5 stop bits.
216 eusartStopbits1p5 = EUSART_FRAMECFG_STOPBITS_ONEANDAHALF, ///< 1.5 stop bits.
217 eusartStopbits1 = EUSART_FRAMECFG_STOPBITS_ONE, ///< 1 stop bits.
218 eusartStopbits2 = EUSART_FRAMECFG_STOPBITS_TWO ///< 2 stop bits.
219 } EUSART_Stopbits_TypeDef;
220
221 /// Oversampling selection, used for asynchronous operation.
222 typedef enum {
223 eusartOVS16 = EUSART_CFG0_OVS_X16, ///< 16x oversampling (normal).
224 eusartOVS8 = EUSART_CFG0_OVS_X8, ///< 8x oversampling.
225 eusartOVS6 = EUSART_CFG0_OVS_X6, ///< 6x oversampling.
226 eusartOVS4 = EUSART_CFG0_OVS_X4, ///< 4x oversampling.
227 eusartOVS0 = EUSART_CFG0_OVS_DISABLE ///< Oversampling disabled.
228 } EUSART_OVS_TypeDef;
229
230 /// HW flow control config.
231 typedef enum {
232 eusartHwFlowControlNone = 0, ///< No HW Flow Control.
233 eusartHwFlowControlCts, ///< CTS HW Flow Control.
234 eusartHwFlowControlRts, ///< RTS HW Flow Control.
235 eusartHwFlowControlCtsAndRts ///< CTS and RTS HW Flow Control.
236 } EUSART_HwFlowControl_TypeDef;
237
238 /// Loopback enable.
239 typedef enum {
240 eusartLoopbackEnable = EUSART_CFG0_LOOPBK, ///< Enable loopback.
241 eusartLoopbackDisable = _EUSART_CFG0_RESETVALUE ///< Disable loopback.
242 } EUSART_LoopbackEnable_TypeDef;
243
244 /// Majority vote enable.
245 typedef enum {
246 eusartMajorityVoteEnable = EUSART_CFG0_MVDIS_DEFAULT, ///< Enable majority vote for 16x, 8x and 6x oversampling modes.
247 eusartMajorityVoteDisable = EUSART_CFG0_MVDIS ///< Disable majority vote for 16x, 8x and 6x oversampling modes.
248 } EUSART_MajorityVote_TypeDef;
249
250 /// Block reception enable.
251 typedef enum {
252 eusartBlockRxEnable = EUSART_CMD_RXBLOCKEN, ///< Block reception enable, resulting in all incoming frames being discarded.
253 eusartBlockRxDisable = EUSART_CMD_RXBLOCKDIS ///< Block reception disable, resulting in all incoming frames being loaded into the RX FIFO.
254 } EUSART_BlockRx_TypeDef;
255
256 /// TX output tristate enable.
257 typedef enum {
258 eusartTristateTxEnable = EUSART_CMD_TXTRIEN, ///< Tristates the transmitter output.
259 eusartTristateTxDisable = EUSART_CMD_TXTRIDIS ///< Disables tristating of the transmitter output.
260 } EUSART_TristateTx_TypeDef;
261
262 /// IrDA filter enable.
263 typedef enum {
264 eusartIrDARxFilterEnable = EUSART_IRHFCFG_IRHFFILT_ENABLE, ///< Enable filter on demodulator.
265 eusartIrDARxFilterDisable = EUSART_IRHFCFG_IRHFFILT_DISABLE ///< Disable filter on demodulator.
266 } EUSART_IrDARxFilterEnable_TypeDef;
267
268 /// Pulse width selection for IrDA mode.
269 typedef enum {
270 /// IrDA pulse width is 1/16 for OVS=X16 and 1/8 for OVS=X8
271 eusartIrDAPulseWidthOne = EUSART_IRHFCFG_IRHFPW_ONE,
272
273 /// IrDA pulse width is 2/16 for OVS=X16 and 2/8 for OVS=X8
274 eusartIrDAPulseWidthTwo = EUSART_IRHFCFG_IRHFPW_TWO,
275
276 /// IrDA pulse width is 3/16 for OVS=X16 and 3/8 for OVS=X8
277 eusartIrDAPulseWidthThree = EUSART_IRHFCFG_IRHFPW_THREE,
278
279 /// IrDA pulse width is 4/16 for OVS=X16 and 4/8 for OVS=X8
280 eusartIrDAPulseWidthFour = EUSART_IRHFCFG_IRHFPW_FOUR
281 } EUSART_IrDAPulseWidth_Typedef;
282
283 /// PRS trigger enable.
284 typedef enum {
285 /// Disable trigger on both receiver and transmitter.
286 eusartPrsTriggerDisable = 0x0,
287
288 /// Enable receive trigger only, transmit disabled.
289 eusartPrsTriggerEnableRx = EUSART_TRIGCTRL_RXTEN,
290
291 /// Enable transmit trigger only, receive disabled.
292 eusartPrsTriggerEnableTx = EUSART_TRIGCTRL_TXTEN,
293
294 /// Enable trigger on both receive and transmit.
295 eusartPrsTriggerEnableRxTx = (EUSART_TRIGCTRL_RXTEN | EUSART_TRIGCTRL_TXTEN)
296 } EUSART_PrsTriggerEnable_TypeDef;
297
298 /// PRS Channel type.
299 typedef uint8_t EUSART_PrsChannel_TypeDef;
300
301 /// IO polarity selection.
302 typedef enum {
303 /// Disable inversion on both RX and TX signals.
304 eusartInvertIODisable = (EUSART_CFG0_RXINV_DISABLE | EUSART_CFG0_TXINV_DISABLE),
305
306 /// Invert RX signal, before receiver.
307 eusartInvertRxEnable = EUSART_CFG0_RXINV_ENABLE,
308
309 /// Invert TX signal, after transmitter.
310 eusartInvertTxEnable = EUSART_CFG0_TXINV_ENABLE,
311
312 /// Enable trigger on both receive and transmit.
313 eusartInvertIOEnable = (EUSART_CFG0_RXINV_ENABLE | EUSART_CFG0_TXINV_ENABLE)
314 } EUSART_InvertIO_TypeDef;
315
316 /// Auto TX delay transmission.
SL_ENUM(EUSART_AutoTxDelay_TypeDef)317 SL_ENUM(EUSART_AutoTxDelay_TypeDef) {
318 /// Frames are transmitted immediately.
319 eusartAutoTxDelayNone = EUSART_TIMINGCFG_TXDELAY_NONE,
320
321 /// Transmission of new frames is delayed by a single bit period.
322 eusartAutoTxDelaySingle = EUSART_TIMINGCFG_TXDELAY_SINGLE,
323
324 /// Transmission of new frames is delayed by a two bit periods.
325 eusartAutoTxDelayDouble = EUSART_TIMINGCFG_TXDELAY_DOUBLE,
326
327 /// Transmission of new frames is delayed by a three bit periods.
328 eusartAutoTxDelayTripple = EUSART_TIMINGCFG_TXDELAY_TRIPPLE
329 };
330
331 /// RX FIFO Interrupt ans Status Watermark.
332 typedef enum {
333 eusartRxFiFoWatermark1Frame = EUSART_CFG1_RXFIW_ONEFRAME,
334 eusartRxFiFoWatermark2Frame = EUSART_CFG1_RXFIW_TWOFRAMES,
335 eusartRxFiFoWatermark3Frame = EUSART_CFG1_RXFIW_THREEFRAMES,
336 eusartRxFiFoWatermark4Frame = EUSART_CFG1_RXFIW_FOURFRAMES,
337 #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2)
338 eusartRxFiFoWatermark5Frame = EUSART_CFG1_RXFIW_FIVEFRAMES,
339 eusartRxFiFoWatermark6Frame = EUSART_CFG1_RXFIW_SIXFRAMES,
340 eusartRxFiFoWatermark7Frame = EUSART_CFG1_RXFIW_SEVENFRAMES,
341 eusartRxFiFoWatermark8Frame = EUSART_CFG1_RXFIW_EIGHTFRAMES,
342 eusartRxFiFoWatermark9Frame = EUSART_CFG1_RXFIW_NINEFRAMES,
343 eusartRxFiFoWatermark10Frame = EUSART_CFG1_RXFIW_TENFRAMES,
344 eusartRxFiFoWatermark11Frame = EUSART_CFG1_RXFIW_ELEVENFRAMES,
345 eusartRxFiFoWatermark12Frame = EUSART_CFG1_RXFIW_TWELVEFRAMES,
346 eusartRxFiFoWatermark13Frame = EUSART_CFG1_RXFIW_THIRTEENFRAMES,
347 eusartRxFiFoWatermark14Frame = EUSART_CFG1_RXFIW_FOURTEENFRAMES,
348 eusartRxFiFoWatermark15Frame = EUSART_CFG1_RXFIW_FIFTEENFRAMES,
349 eusartRxFiFoWatermark16Frame = EUSART_CFG1_RXFIW_SIXTEENFRAMES
350 #endif
351 } EUSART_RxFifoWatermark_TypeDef;
352
353 /// TX FIFO Interrupt and Status Watermark.
354 typedef enum {
355 eusartTxFiFoWatermark1Frame = EUSART_CFG1_TXFIW_ONEFRAME,
356 eusartTxFiFoWatermark2Frame = EUSART_CFG1_TXFIW_TWOFRAMES,
357 eusartTxFiFoWatermark3Frame = EUSART_CFG1_TXFIW_THREEFRAMES,
358 eusartTxFiFoWatermark4Frame = EUSART_CFG1_TXFIW_FOURFRAMES,
359 #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2)
360 eusartTxFiFoWatermark5Frame = EUSART_CFG1_TXFIW_FIVEFRAMES,
361 eusartTxFiFoWatermark6Frame = EUSART_CFG1_TXFIW_SIXFRAMES,
362 eusartTxFiFoWatermark7Frame = EUSART_CFG1_TXFIW_SEVENFRAMES,
363 eusartTxFiFoWatermark8Frame = EUSART_CFG1_TXFIW_EIGHTFRAMES,
364 eusartTxFiFoWatermark9Frame = EUSART_CFG1_TXFIW_NINEFRAMES,
365 eusartTxFiFoWatermark10Frame = EUSART_CFG1_TXFIW_TENFRAMES,
366 eusartTxFiFoWatermark11Frame = EUSART_CFG1_TXFIW_ELEVENFRAMES,
367 eusartTxFiFoWatermark12Frame = EUSART_CFG1_TXFIW_TWELVEFRAMES,
368 eusartTxFiFoWatermark13Frame = EUSART_CFG1_TXFIW_THIRTEENFRAMES,
369 eusartTxFiFoWatermark14Frame = EUSART_CFG1_TXFIW_FOURTEENFRAMES,
370 eusartTxFiFoWatermark15Frame = EUSART_CFG1_TXFIW_FIFTEENFRAMES,
371 eusartTxFiFoWatermark16Frame = EUSART_CFG1_TXFIW_SIXTEENFRAMES
372 #endif
373 } EUSART_TxFifoWatermark_TypeDef;
374
375 #if defined(EUSART_PRESENT)
376 /// Clock polarity/phase mode.
377 typedef enum {
378 /// Clock idle low, sample on rising edge.
379 eusartClockMode0 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLELEADING,
380
381 /// Clock idle low, sample on falling edge.
382 eusartClockMode1 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLETRAILING,
383
384 /// Clock idle high, sample on falling edge.
385 eusartClockMode2 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLELEADING,
386
387 /// Clock idle high, sample on rising edge.
388 eusartClockMode3 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLETRAILING
389 } EUSART_ClockMode_TypeDef;
390
391 /// Chip select polarity.
392 typedef enum {
393 /// Chip select active low.
394 eusartCsActiveLow = EUSART_CFG2_CSINV_AL,
395
396 /// Chip select active high.
397 eusartCsActiveHigh = EUSART_CFG2_CSINV_AH,
398 } EUSART_CsPolarity_TypeDef;
399
400 #if defined(EUSART_DALICFG_DALIEN)
401 /// DALI TX databits (8-32).
402 typedef enum {
403 eusartDaliTxDataBits8 = EUSART_DALICFG_DALITXDATABITS_EIGHT, ///< Each frame contains 8 data bits.
404 eusartDaliTxDataBits9 = EUSART_DALICFG_DALITXDATABITS_NINE, ///< Each frame contains 9 data bits.
405 eusartDaliTxDataBits10 = EUSART_DALICFG_DALITXDATABITS_TEN, ///< Each frame contains 10 data bits.
406 eusartDaliTxDataBits11 = EUSART_DALICFG_DALITXDATABITS_ELEVEN, ///< Each frame contains 11 data bits.
407 eusartDaliTxDataBits12 = EUSART_DALICFG_DALITXDATABITS_TWELVE, ///< Each frame contains 12 data bits.
408 eusartDaliTxDataBits13 = EUSART_DALICFG_DALITXDATABITS_THIRTEEN, ///< Each frame contains 13 data bits.
409 eusartDaliTxDataBits14 = EUSART_DALICFG_DALITXDATABITS_FOURTEEN, ///< Each frame contains 14 data bits.
410 eusartDaliTxDataBits15 = EUSART_DALICFG_DALITXDATABITS_FIFTEEN, ///< Each frame contains 15 data bits.
411 eusartDaliTxDataBits16 = EUSART_DALICFG_DALITXDATABITS_SIXTEEN, ///< Each frame contains 16 data bits.
412 eusartDaliTxDataBits17 = EUSART_DALICFG_DALITXDATABITS_SEVENTEEN, ///< Each frame contains 17 data bits.
413 eusartDaliTxDataBits18 = EUSART_DALICFG_DALITXDATABITS_EIGHTEEN, ///< Each frame contains 18 data bits.
414 eusartDaliTxDataBits19 = EUSART_DALICFG_DALITXDATABITS_NINETEEN, ///< Each frame contains 19 data bits.
415 eusartDaliTxDataBits20 = EUSART_DALICFG_DALITXDATABITS_TWENTY, ///< Each frame contains 20 data bits.
416 eusartDaliTxDataBits21 = EUSART_DALICFG_DALITXDATABITS_TWENTYONE, ///< Each frame contains 21 data bits.
417 eusartDaliTxDataBits22 = EUSART_DALICFG_DALITXDATABITS_TWENTYTWO, ///< Each frame contains 22 data bits.
418 eusartDaliTxDataBits23 = EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT, ///< Each frame contains 23 data bits.
419 eusartDaliTxDataBits24 = EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR, ///< Each frame contains 24 data bits.
420 eusartDaliTxDataBits25 = EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE, ///< Each frame contains 25 data bits.
421 eusartDaliTxDataBits26 = EUSART_DALICFG_DALITXDATABITS_TWENTYSIX, ///< Each frame contains 26 data bits.
422 eusartDaliTxDataBits27 = EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN, ///< Each frame contains 27 data bits.
423 eusartDaliTxDataBits28 = EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT, ///< Each frame contains 28 data bits.
424 eusartDaliTxDataBits29 = EUSART_DALICFG_DALITXDATABITS_TWENTYNINE, ///< Each frame contains 29 data bits.
425 eusartDaliTxDataBits30 = EUSART_DALICFG_DALITXDATABITS_THIRTY, ///< Each frame contains 30 data bits.
426 eusartDaliTxDataBits31 = EUSART_DALICFG_DALITXDATABITS_THIRTYONE, ///< Each frame contains 31 data bits.
427 eusartDaliTxDataBits32 = EUSART_DALICFG_DALITXDATABITS_THIRTYTWO, ///< Each frame contains 32 data bits.
428 } EUSART_DaliTxDatabits_TypeDef;
429
430 /// DALI RX databits (8-32).
431 typedef enum {
432 eusartDaliRxDataBits8 = EUSART_DALICFG_DALIRXDATABITS_EIGHT, ///< Each frame contains 8 data bits.
433 eusartDaliRxDataBits9 = EUSART_DALICFG_DALIRXDATABITS_NINE, ///< Each frame contains 9 data bits.
434 eusartDaliRxDataBits10 = EUSART_DALICFG_DALIRXDATABITS_TEN, ///< Each frame contains 10 data bits.
435 eusartDaliRxDataBits11 = EUSART_DALICFG_DALIRXDATABITS_ELEVEN, ///< Each frame contains 11 data bits.
436 eusartDaliRxDataBits12 = EUSART_DALICFG_DALIRXDATABITS_TWELVE, ///< Each frame contains 12 data bits.
437 eusartDaliRxDataBits13 = EUSART_DALICFG_DALIRXDATABITS_THIRTEEN, ///< Each frame contains 13 data bits.
438 eusartDaliRxDataBits14 = EUSART_DALICFG_DALIRXDATABITS_FOURTEEN, ///< Each frame contains 14 data bits.
439 eusartDaliRxDataBits15 = EUSART_DALICFG_DALIRXDATABITS_FIFTEEN, ///< Each frame contains 15 data bits.
440 eusartDaliRxDataBits16 = EUSART_DALICFG_DALIRXDATABITS_SIXTEEN, ///< Each frame contains 16 data bits.
441 eusartDaliRxDataBits17 = EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN, ///< Each frame contains 17 data bits.
442 eusartDaliRxDataBits18 = EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN, ///< Each frame contains 18 data bits.
443 eusartDaliRxDataBits19 = EUSART_DALICFG_DALIRXDATABITS_NINETEEN, ///< Each frame contains 19 data bits.
444 eusartDaliRxDataBits20 = EUSART_DALICFG_DALIRXDATABITS_TWENTY, ///< Each frame contains 20 data bits.
445 eusartDaliRxDataBits21 = EUSART_DALICFG_DALIRXDATABITS_TWENTYONE, ///< Each frame contains 21 data bits.
446 eusartDaliRxDataBits22 = EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO, ///< Each frame contains 22 data bits.
447 eusartDaliRxDataBits23 = EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT, ///< Each frame contains 23 data bits.
448 eusartDaliRxDataBits24 = EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR, ///< Each frame contains 24 data bits.
449 eusartDaliRxDataBits25 = EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE, ///< Each frame contains 25 data bits.
450 eusartDaliRxDataBits26 = EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX, ///< Each frame contains 26 data bits.
451 eusartDaliRxDataBits27 = EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN, ///< Each frame contains 27 data bits.
452 eusartDaliRxDataBits28 = EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT, ///< Each frame contains 28 data bits.
453 eusartDaliRxDataBits29 = EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE, ///< Each frame contains 29 data bits.
454 eusartDaliRxDataBits30 = EUSART_DALICFG_DALIRXDATABITS_THIRTY, ///< Each frame contains 30 data bits.
455 eusartDaliRxDataBits31 = EUSART_DALICFG_DALIRXDATABITS_THIRTYONE, ///< Each frame contains 31 data bits.
456 eusartDaliRxDataBits32 = EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO, ///< Each frame contains 32 data bits.
457 } EUSART_DaliRxDatabits_TypeDef;
458 #endif /* EUSART_DALICFG_DALIEN */
459 #endif /* EUSART_PRESENT */
460
461 /*******************************************************************************
462 ******************************* STRUCTS ***********************************
463 ******************************************************************************/
464 /// Advanced initialization structure.
465 typedef struct {
466 /// Hardware flow control mode.
467 EUSART_HwFlowControl_TypeDef hwFlowControl;
468
469 /// Enable the collision Detection feature.
470 /// Internal (setting loopbackEnable) or external loopback must be done to use this feature.
471 bool collisionDetectEnable;
472
473 /// If true, data will be send with most significant bit first.
474 bool msbFirst;
475
476 /// Enable inversion of RX and/or TX signals.
477 EUSART_InvertIO_TypeDef invertIO;
478
479 /// Enable the automatic wake up from EM2 to EM1 for DMA RX operation.
480 bool dmaWakeUpOnRx;
481
482 /// Enable the automatic wake up from EM2 to EM1 for DMA TX operation.
483 bool dmaWakeUpOnTx;
484
485 /// Enable DMA requests blocking while framing or parity errors.
486 bool dmaHaltOnError;
487
488 /// Start frame that will enable RX operation. 0x00 Disable this feature.
489 uint8_t startFrame;
490
491 /// Enable automatic tristating of transmistter output when there is nothing to transmit.
492 bool txAutoTristate;
493
494 /// Enable EUSART capability to use a PRS channel as an input data line for the receiver.
495 /// The configured RX GPIO signal won't be routed to the EUSART receiver.
496 bool prsRxEnable;
497
498 /// PRS Channel used to transmit data from PRS to the EUSART.
499 EUSART_PrsChannel_TypeDef prsRxChannel;
500
501 /// Enable Multiprocessor mode. Address and data filtering using the 9th bit.
502 bool multiProcessorEnable;
503
504 /// Multiprocessor address bit value. If true, 9th bit of address frame must bit 1, 0 otherwise.
505 bool multiProcessorAddressBitHigh;
506
507 /// Auto TX delay before new transfers. Frames sent back-to-back are not delayed.
508 EUSART_AutoTxDelay_TypeDef autoTxDelay;
509
510 /// Interrupt and status level of the Receive FIFO.
511 EUSART_RxFifoWatermark_TypeDef RxFifoWatermark;
512
513 /// Interrupt and status level of the Transmit FIFO.
514 EUSART_TxFifoWatermark_TypeDef TxFifoWatermark;
515 } EUSART_AdvancedInit_TypeDef;
516
517 /// Initialization structure.
518 typedef struct {
519 /// Specifies whether TX and/or RX will be enabled when initialization completes.
520 EUSART_Enable_TypeDef enable;
521
522 /// EUSART reference clock assumed when configuring baud rate setup. Set
523 /// to 0 if using currently configured reference clock.
524 uint32_t refFreq;
525
526 /// Desired baud rate. If set to 0, Auto Baud feature is enabled and
527 /// the EUSART will wait for (0x55) frame to detect the Baudrate.
528 uint32_t baudrate;
529
530 /// Oversampling used.
531 EUSART_OVS_TypeDef oversampling;
532
533 /// Number of data bits in frame.
534 EUSART_Databits_TypeDef databits;
535
536 /// Parity mode to use.
537 EUSART_Parity_TypeDef parity;
538
539 /// Number of stop bits to use.
540 EUSART_Stopbits_TypeDef stopbits;
541
542 /// Majority Vote can be disabled for 16x, 8x and 6x oversampling modes.
543 EUSART_MajorityVote_TypeDef majorityVote;
544
545 /// Enable Loop Back configuration.
546 EUSART_LoopbackEnable_TypeDef loopbackEnable;
547
548 /// Advanced initialization structure pointer. It can be NULL.
549 EUSART_AdvancedInit_TypeDef *advancedSettings;
550 } EUSART_UartInit_TypeDef;
551
552 /// IrDA Initialization structure.
553 typedef struct {
554 /// General EUSART initialization structure.
555 EUSART_UartInit_TypeDef init;
556
557 /// Enable the IrDA low frequency mode. Only RX operation are enabled.
558 bool irDALowFrequencyEnable;
559
560 /// Set to enable filter on IrDA demodulator.
561 EUSART_IrDARxFilterEnable_TypeDef irDARxFilterEnable;
562
563 /// Configure the pulse width generated by the IrDA modulator as a fraction
564 /// of the configured EUSART bit period.
565 EUSART_IrDAPulseWidth_Typedef irDAPulseWidth;
566 } EUSART_IrDAInit_TypeDef;
567
568 /// PRS Trigger initialization structure.
569 typedef struct {
570 /// PRS to EUSART trigger mode.
571 EUSART_PrsTriggerEnable_TypeDef prs_trigger_enable;
572
573 /// PRS channel to be used to trigger auto transmission.
574 EUSART_PrsChannel_TypeDef prs_trigger_channel;
575 } EUSART_PrsTriggerInit_TypeDef;
576
577 #if defined(EUSART_PRESENT)
578 /// SPI Advanced initialization structure.
579 typedef struct {
580 /// Chip select polarity
581 EUSART_CsPolarity_TypeDef csPolarity;
582
583 /// Enable inversion of RX and/or TX signals.
584 EUSART_InvertIO_TypeDef invertIO;
585
586 /// Enable automatic chip select. CS is managed by the peripheral.
587 bool autoCsEnable;
588
589 /// If true, data will be send with most significant bit first.
590 bool msbFirst;
591
592 /// Auto CS setup time (before transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle).
593 uint8_t autoCsSetupTime;
594
595 /// Auto CS hold time (after transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle).
596 uint8_t autoCsHoldTime;
597
598 /// Inter-frame time in baud cycles. Acceptable value ( 0 to 7 baud cycle).
599 uint8_t autoInterFrameTime;
600
601 /// Enable AUTOTX mode. Transmits as long as the RX FIFO is not full.
602 /// Generates underflow interrupt if the TX FIFO is empty.
603 bool autoTxEnable;
604
605 /// Default transmitted data when the TXFIFO is empty.
606 uint16_t defaultTxData;
607
608 /// Enable the automatic wake up from EM2 to EM1 for DMA RX operation.
609 /// Only applicable to EM2 (low frequency) capable EUSART instances.
610 bool dmaWakeUpOnRx;
611
612 /// Enable EUSART capability to use a PRS channel as an input data line for the receiver.
613 /// The configured RX GPIO signal won't be routed to the EUSART receiver.
614 bool prsRxEnable;
615
616 /// PRS Channel used to transmit data from PRS to the EUSART.
617 EUSART_PrsChannel_TypeDef prsRxChannel;
618
619 /// Enable EUSART capability to use a PRS channel as an input SPI Clock.
620 /// Slave mode only.
621 bool prsClockEnable;
622
623 /// PRS Channel used to transmit SCLK from PRS to the EUSART.
624 EUSART_PrsChannel_TypeDef prsClockChannel;
625
626 /// Interrupt and status level of the Receive FIFO.
627 EUSART_RxFifoWatermark_TypeDef RxFifoWatermark;
628
629 /// Interrupt and status level of the Receive FIFO.
630 EUSART_TxFifoWatermark_TypeDef TxFifoWatermark;
631
632 /// Force load the first FIFO value.
633 bool forceLoad;
634
635 /// Setup window in bus clock cycles before the sampling edge of SCLK at word-boundary to avoid force load error.
636 uint8_t setupWindow;
637 } EUSART_SpiAdvancedInit_TypeDef;
638
639 /// SPI Initialization structure.
640 typedef struct {
641 /// Specifies whether TX and/or RX will be enabled when initialization completes.
642 EUSART_Enable_TypeDef enable;
643
644 /// EUSART reference clock assumed when configuring baud rate setup. Set
645 /// to 0 if using currently configured reference clock.
646 uint32_t refFreq;
647
648 /// Desired bit rate in Hz.
649 /// Depending on EUSART instance clock, not all bitrates
650 /// are achievable as the divider is limited to 255.
651 uint32_t bitRate;
652
653 /// Number of data bits in frame.
654 EUSART_Databits_TypeDef databits;
655
656 /// Select to operate in master or slave mode.
657 bool master;
658
659 /// Clock polarity/phase mode.
660 EUSART_ClockMode_TypeDef clockMode;
661
662 /// Enable Loop Back configuration.
663 EUSART_LoopbackEnable_TypeDef loopbackEnable;
664
665 /// Advanced initialization structure pointer. It can be NULL.
666 EUSART_SpiAdvancedInit_TypeDef *advancedSettings;
667 } EUSART_SpiInit_TypeDef;
668 #endif /* EUSART_PRESENT */
669
670 /// DALI Initialization structure.
671 typedef struct {
672 /// General EUSART initialization structure.
673 EUSART_UartInit_TypeDef init;
674
675 /// Enable the DALI low frequency mode.
676 bool daliLowFrequencyEnable;
677
678 #if defined(EUSART_DALICFG_DALIEN)
679 /// Number of TX data bits in frame.
680 EUSART_DaliTxDatabits_TypeDef TXdatabits;
681 /// Number of RX data bits in frame.
682 EUSART_DaliRxDatabits_TypeDef RXdatabits;
683 #endif
684 } EUSART_DaliInit_TypeDef;
685
686 /// Default configuration for EUSART initialization structure in UART mode with high-frequency clock.
687 #define EUSART_UART_INIT_DEFAULT_HF \
688 { \
689 eusartEnable, /* Enable RX/TX when initialization completed. */ \
690 0, /* Use current configured reference clock for configuring baud rate.*/ \
691 115200, /* 115200 bits/s. */ \
692 eusartOVS16, /* Oversampling x16. */ \
693 eusartDataBits8, /* 8 data bits. */ \
694 eusartNoParity, /* No parity. */ \
695 eusartStopbits1, /* 1 stop bit. */ \
696 eusartMajorityVoteEnable, /* Majority vote enabled. */ \
697 eusartLoopbackDisable, /* Loop back disabled. */ \
698 NULL, /* Default advanced settings. */ \
699 }
700
701 /// Default start frame configuration, i.e. feature disabled.
702 #define EUSART_DEFAULT_START_FRAME 0x00u
703
704 /// Default configuration for EUSART advanced initialization structure.
705 #define EUSART_ADVANCED_INIT_DEFAULT \
706 { \
707 eusartHwFlowControlNone, /* Flow control disabled. */ \
708 false, /* Collision detection disabled. */ \
709 false, /* Data is sent with the least significant bit first. */ \
710 eusartInvertIODisable, /* RX and TX signal active high. */ \
711 false, /* No DMA wake up on reception. */ \
712 false, /* No DMA wake up on transmission. */ \
713 false, /* Halt DMA on error disabled. */ \
714 EUSART_DEFAULT_START_FRAME, /* No start frame. */ \
715 false, /* TX auto tristate disabled. */ \
716 false, /* Do not use PRS signal as RX signal.*/ \
717 (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \
718 false, /* Multiprocessor mode disabled. */ \
719 false, /* Multiprocessor address bit : 0.*/ \
720 eusartAutoTxDelayNone, /* Frames are transmitted immediately */ \
721 eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \
722 eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \
723 }
724
725 /// Default configuration for EUSART initialization structure in UART mode with low-frequency clock.
726 #define EUSART_UART_INIT_DEFAULT_LF \
727 { \
728 eusartEnable, /* Enable RX/TX when initialization completed. */ \
729 0, /* Use current configured reference clock for configuring baud rate.*/ \
730 9600, /* 9600 bits/s. */ \
731 eusartOVS0, /* Oversampling disabled. */ \
732 eusartDataBits8, /* 8 data bits. */ \
733 eusartNoParity, /* No parity. */ \
734 eusartStopbits1, /* 1 stop bit. */ \
735 eusartMajorityVoteDisable, /* Majority vote enabled. */ \
736 eusartLoopbackDisable, /* Loop back disabled. */ \
737 NULL, /* Default advanced settings. */ \
738 }
739
740 /// Default configuration for EUSART initialization structure in IrDA mode with high-frequency clock.
741 #define EUSART_IRDA_INIT_DEFAULT_HF \
742 { \
743 EUSART_UART_INIT_DEFAULT_HF, /* Default high frequency configuration. */ \
744 false, /* Disable IrDA low frequency mode. */ \
745 eusartIrDARxFilterDisable, /* RX Filter disabled. */ \
746 eusartIrDAPulseWidthOne, /* Pulse width is set to 1/16. */ \
747 }
748
749 /// Default configuration for EUSART initialization structure in IrDA mode with low-frequency clock.
750 #define EUSART_IRDA_INIT_DEFAULT_LF \
751 { \
752 { \
753 eusartEnableRx, /* Enable RX when initialization completed (TX not allowed). */ \
754 0, /* Use current configured reference clock for configuring baud rate.*/ \
755 9600, /* 9600 bits/s. */ \
756 eusartOVS0, /* Oversampling disabled. */ \
757 eusartDataBits8, /* 8 data bits. */ \
758 eusartNoParity, /* No parity. */ \
759 eusartStopbits1, /* 1 stop bit. */ \
760 eusartMajorityVoteDisable, /* Majority vote enabled. */ \
761 eusartLoopbackDisable, /* Loop back disabled. */ \
762 NULL, /* Default advanced settings. */ \
763 }, \
764 true, /* Enable IrDA low frequency mode. */ \
765 eusartIrDARxFilterDisable, /* RX Filter disabled. */ \
766 eusartIrDAPulseWidthOne, /* Pulse width is set to 1. */ \
767 }
768
769 #if defined(EUSART_PRESENT)
770 /// Default advanced configuration for EUSART initialization structure in SPI mode with high-frequency clock.
771 #define EUSART_SPI_ADVANCED_INIT_DEFAULT \
772 { \
773 eusartCsActiveLow, /* CS active low. */ \
774 eusartInvertIODisable, /* RX and TX signal active High. */ \
775 true, /* AutoCS enabled. */ \
776 false, /* Data is sent with the least significant bit first. */ \
777 0u, /* CS setup time is 0 baud cycles */ \
778 0u, /* CS hold time is 0 baud cycles */ \
779 0u, /* Inter-frame time is 0 baud cycles */ \
780 false, /* AutoTX disabled. */ \
781 0x0000, /* Default transmitted data is 0. */ \
782 false, /* No DMA wake up on reception. */ \
783 false, /* Do not use PRS signal as RX signal. */ \
784 (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX tied to prs channel 0. */ \
785 false, /* Do not use PRS signal as SCLK signal. */ \
786 (EUSART_PrsChannel_TypeDef) 1u, /* EUSART SCLCK tied to prs channel 1. */ \
787 eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \
788 eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \
789 true, /* The first byte sent by the slave won't be the default value if a byte is made available \
790 after chip select is asserted. */ \
791 0x04u, /* Setup window before the sampling edge of SCLK at word-boundary to avoid force load error. */ \
792 }
793
794 /// Default configuration for EUSART initialization structure in SPI master mode with high-frequency clock.
795 #define EUSART_SPI_MASTER_INIT_DEFAULT_HF \
796 { \
797 eusartEnable, /* Enable RX/TX when initialization completed. */ \
798 0, /* Use current configured reference clock for configuring baud rate.*/ \
799 10000000, /* 10 Mbits/s. */ \
800 eusartDataBits8, /* 8 data bits. */ \
801 true, /* Master mode enabled. */ \
802 eusartClockMode0, /* Clock idle low, sample on rising edge. */ \
803 eusartLoopbackDisable, /* Loop back disabled. */ \
804 NULL, /* Default advanced settings. */ \
805 }
806
807 /// Default configuration for EUSART initialization structure in SPI slave mode with high-frequency clock.
808 #define EUSART_SPI_SLAVE_INIT_DEFAULT_HF \
809 { \
810 eusartEnable, /* Enable RX/TX when initialization completed. */ \
811 0, /* Use current configured reference clock for configuring baud rate.*/ \
812 10000000, /* 10 Mbits/s. */ \
813 eusartDataBits8, /* 8 data bits. */ \
814 false, /* Master mode enabled. */ \
815 eusartClockMode0, /* Clock idle low, sample on rising edge. */ \
816 eusartLoopbackDisable, /* Loop back disabled. */ \
817 NULL, /* Default advanced settings. */ \
818 }
819
820 #if defined(EUSART_DALICFG_DALIEN)
821 /// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock.
822 /// Default configuration for EUSART advanced initialization structure.
823 #define EUSART_ADVANCED_DALI_INIT_DEFAULT \
824 { \
825 eusartHwFlowControlNone, /* Flow control disabled. */ \
826 false, /* Collision detection disabled. */ \
827 true, /* Data is sent with the most significant bit first. */ \
828 eusartInvertIODisable, /* RX and TX signal active high. */ \
829 false, /* No DMA wake up on reception. */ \
830 false, /* No DMA wake up on transmission. */ \
831 false, /* Halt DMA on error disabled. */ \
832 EUSART_DEFAULT_START_FRAME, /* No start frame. */ \
833 false, /* TX auto tristate disabled. */ \
834 false, /* Do not use PRS signal as RX signal.*/ \
835 (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \
836 false, /* Multiprocessor mode disabled. */ \
837 false, /* Multiprocessor address bit : 0.*/ \
838 eusartAutoTxDelayNone, /* Frames are transmitted immediately */ \
839 eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \
840 eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \
841 }
842
843 /// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock.
844 #define EUSART_UART_DALI_INIT_DEFAULT_HF \
845 { \
846 eusartEnable, /* Enable RX/TX when initialization completed. */ \
847 0, /* Use current configured reference clock for configuring baud rate.*/ \
848 1200, /* 1200 bits/s. */ \
849 eusartOVS16, /* Oversampling x16. */ \
850 eusartDataBits8, /* 8 data bits. */ \
851 eusartNoParity, /* No parity. */ \
852 eusartStopbits1, /* 1 stop bit. */ \
853 eusartMajorityVoteEnable, /* Majority vote enabled. */ \
854 eusartLoopbackDisable, /* Loop back disabled. */ \
855 NULL, /* Default advanced settings. */ \
856 }
857
858 /// Default configuration for EUSART initialization structure in DALI mode with low-frequency clock.
859 #define EUSART_UART_DALI_INIT_DEFAULT_LF \
860 { \
861 eusartEnable, /* Enable RX/TX when initialization completed. */ \
862 0, /* Use current configured reference clock for configuring baud rate.*/ \
863 1200, /* 1200 bits/s. */ \
864 eusartOVS0, /* Oversampling disabled. */ \
865 eusartDataBits8, /* 8 data bits. */ \
866 eusartNoParity, /* No parity. */ \
867 eusartStopbits1, /* 1 stop bit. */ \
868 eusartMajorityVoteDisable, /* Majority vote enabled. */ \
869 eusartLoopbackDisable, /* Loop back disabled. */ \
870 NULL, /* Default advanced settings. */ \
871 }
872
873 /// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock.
874 #define EUSART_DALI_INIT_DEFAULT_HF \
875 { \
876 EUSART_UART_DALI_INIT_DEFAULT_HF, \
877 false, /* Disable DALI low frequency mode. */ \
878 eusartDaliTxDataBits16, /* TX 16 data bits. */ \
879 eusartDaliRxDataBits8, /* RX 8 data bits. */ \
880 } \
881
882 /// Default configuration for EUSART initialization structure in DALI mode with low-frequency clock.
883 #define EUSART_DALI_INIT_DEFAULT_LF \
884 { \
885 EUSART_UART_DALI_INIT_DEFAULT_LF, \
886 true, /* Enable DALI low frequency mode. */ \
887 eusartDaliTxDataBits16, /* TX 16 data bits. */ \
888 eusartDaliRxDataBits8, /* RX 8 data bits. */ \
889 } \
890
891 #endif /* EUSART_DALICFG_DALIEN */
892 #endif /* EUSART_PRESENT */
893
894 /*******************************************************************************
895 ***************************** PROTOTYPES **********************************
896 ******************************************************************************/
897
898 /***************************************************************************//**
899 * Initialize EUSART when used in UART mode with the high frequency clock.
900 *
901 * @param eusart Pointer to the EUSART peripheral register block.
902 * @param init A pointer to the initialization structure.
903 ******************************************************************************/
904 void EUSART_UartInitHf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init);
905
906 /***************************************************************************//**
907 * Initialize EUSART when used in UART mode with the low frequency clock.
908 *
909 * @param eusart Pointer to the EUSART peripheral register block.
910 * @param init A pointer to the initialization structure.
911 ******************************************************************************/
912 void EUSART_UartInitLf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init);
913
914 /***************************************************************************//**
915 * Initialize EUSART when used in IrDA mode with the high or low
916 * frequency clock.
917 *
918 * @param eusart Pointer to the EUSART peripheral register block.
919 * @param irdaInit A pointer to the initialization structure.
920 ******************************************************************************/
921 void EUSART_IrDAInit(EUSART_TypeDef *eusart,
922 const EUSART_IrDAInit_TypeDef *irdaInit);
923
924 #if defined(EUSART_PRESENT)
925 /***************************************************************************//**
926 * Initialize EUSART when used in SPI mode.
927 *
928 * @param eusart Pointer to the EUSART peripheral register block.
929 * @param init A pointer to the initialization structure.
930 ******************************************************************************/
931 void EUSART_SpiInit(EUSART_TypeDef *eusart, const EUSART_SpiInit_TypeDef *init);
932
933 #if defined(EUSART_DALICFG_DALIEN)
934 /***************************************************************************//**
935 * Initialize EUSART when used in DALI mode with the high or low
936 * frequency clock.
937 *
938 * @param eusart Pointer to the EUSART peripheral register block.
939 * @param daliInit A pointer to the initialization structure.
940 ******************************************************************************/
941 void EUSART_DaliInit(EUSART_TypeDef *eusart,
942 const EUSART_DaliInit_TypeDef *daliInit);
943
944 #endif /* EUSART_DALICFG_DALIEN */
945 #endif /* EUSART_PRESENT */
946
947 /***************************************************************************//**
948 * Configure EUSART to its reset state.
949 *
950 * @param eusart Pointer to the EUSART peripheral register block.
951 ******************************************************************************/
952 void EUSART_Reset(EUSART_TypeDef *eusart);
953
954 /***************************************************************************//**
955 * Enable/disable EUSART receiver and/or transmitter.
956 *
957 * @param eusart Pointer to the EUSART peripheral register block.
958 * @param enable Select the status for the receiver and transmitter.
959 ******************************************************************************/
960 void EUSART_Enable(EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable);
961
962 /***************************************************************************//**
963 * Receive one 8 bit frame, (or part of 9 bit frame).
964 *
965 * @param eusart Pointer to the EUSART peripheral register block.
966 *
967 * @note This function is normally used to receive one frame when operating with
968 * frame length of 8 bits. See EUSART_RxExt() for reception of 9 bit frames.
969 * Notice that possible parity/stop bits are not considered a part of the
970 * specified frame bit length.
971 * @note This function will stall if buffer is empty until data is received.
972 *
973 * @return Data received.
974 ******************************************************************************/
975 uint8_t EUSART_Rx(EUSART_TypeDef *eusart);
976
977 /***************************************************************************//**
978 * Receive one 8-16 bit frame with extended information.
979 *
980 * @param eusart Pointer to the EUSART peripheral register block.
981 *
982 * @note This function is normally used to receive one frame and additional RX
983 * status information.
984 * @note This function will stall if buffer is empty until data is received.
985 *
986 * @return Data received and receive status.
987 ******************************************************************************/
988 uint16_t EUSART_RxExt(EUSART_TypeDef *eusart);
989
990 /***************************************************************************//**
991 * Transmit one frame.
992 *
993 * @param eusart Pointer to the EUSART peripheral register block.
994 * @param data Data to transmit.
995 *
996 * @note Depending on the frame length configuration, 8 (least significant) bits
997 * from @p data are transmitted. If the frame length is 9, 8 bits are
998 * transmitted from @p data. See EUSART_TxExt() for transmitting 9 bit frame
999 * with full control of all 9 bits.
1000 * @note This function will stall if the 4 frame FIFO is full, until the buffer
1001 * becomes available.
1002 ******************************************************************************/
1003 void EUSART_Tx(EUSART_TypeDef *eusart, uint8_t data);
1004
1005 /***************************************************************************//**
1006 * Transmit one 8-9 bit frame with extended control.
1007 *
1008 * @param eusart Pointer to the EUSART peripheral register block.
1009 * @param data Data to transmit.
1010 *
1011 * @note Possible parity/stop bits in asynchronous mode are not
1012 * considered part of a specified frame bit length.
1013 * @note This function will stall if buffer is full until the buffer becomes
1014 * available.
1015 ******************************************************************************/
1016 void EUSART_TxExt(EUSART_TypeDef *eusart, uint16_t data);
1017
1018 #if defined(EUSART_PRESENT)
1019 /***************************************************************************//**
1020 * Transmit one 8-16 bit frame and return received data.
1021 *
1022 * @param eusart Pointer to the EUSART peripheral register block.
1023 * @param data Data to transmit.
1024 *
1025 * @return Data received and receive status.
1026 *
1027 * @note SPI master mode only.
1028 * @note This function will stall if the TX buffer is full until the buffer becomes
1029 * available.
1030 ******************************************************************************/
1031 uint16_t EUSART_Spi_TxRx(EUSART_TypeDef *eusart, uint16_t data);
1032
1033 #if defined(EUSART_DALICFG_DALIEN)
1034 /***************************************************************************//**
1035 * Transmit one DALI frame.
1036 *
1037 * @param eusart Pointer to the EUSART peripheral register block.
1038 * @param data Data to transmit.
1039 *
1040 * @note Depending on the TXdatabits configuration, N (least significant) bits
1041 * from @p data are transmitted.
1042 * @note This function will stall if the 16 frame FIFO is full, until the buffer
1043 * becomes available.
1044 ******************************************************************************/
1045 void EUSART_Dali_Tx(EUSART_TypeDef *eusart, uint32_t data);
1046
1047 /***************************************************************************//**
1048 * Receive one 8-32 bit DALI frame.
1049 *
1050 * @param eusart Pointer to the EUSART peripheral register block.
1051 *
1052 * @note This function is normally used to receive one DALI frame (RXdatabits).
1053 * @note This function will stall if the 16 frame FIFO is empty until new
1054 * data is received.
1055 *
1056 * @return Data received. Depending on the RXdatabits configuration, N
1057 * (least significant) bits are returned.
1058 ******************************************************************************/
1059 uint32_t EUSART_Dali_Rx(EUSART_TypeDef *eusart);
1060 #endif /* EUSART_DALICFG_DALIEN */
1061 #endif /* EUSART_PRESENT */
1062
1063 /***************************************************************************//**
1064 * Configure the baudrate (or as close as possible to a specified baudrate).
1065 *
1066 * @param eusart Pointer to the EUSART peripheral register block.
1067 * @param refFreq The EUSART reference clock frequency in Hz that will be used.
1068 * If set to 0, the currently configured peripheral clock is
1069 * used.
1070 * @param baudrate A baudrate to try to achieve.
1071 ******************************************************************************/
1072 void EUSART_BaudrateSet(EUSART_TypeDef *eusart,
1073 uint32_t refFreq,
1074 uint32_t baudrate);
1075
1076 /***************************************************************************//**
1077 * Get the current baudrate.
1078 *
1079 * @param eusart Pointer to the EUSART peripheral register block.
1080 *
1081 * @return The current baudrate.
1082 ******************************************************************************/
1083 uint32_t EUSART_BaudrateGet(EUSART_TypeDef *eusart);
1084
1085 /***************************************************************************//**
1086 * Enable/Disable reception operation until the configured start frame is
1087 * received.
1088 *
1089 * @param eusart Pointer to the EUSART peripheral register block.
1090 * @param enable Select the receiver blocking status.
1091 ******************************************************************************/
1092 void EUSART_RxBlock(EUSART_TypeDef *eusart,
1093 EUSART_BlockRx_TypeDef enable);
1094
1095 /***************************************************************************//**
1096 * Enable/Disable the tristating of the transmitter output.
1097 *
1098 * @param eusart Pointer to the EUSART peripheral register block.
1099 * @param enable Select the transmitter tristate status.
1100 ******************************************************************************/
1101 void EUSART_TxTristateSet(EUSART_TypeDef *eusart,
1102 EUSART_TristateTx_TypeDef enable);
1103
1104 /***************************************************************************//**
1105 * Initialize the automatic enabling of transmissions and/or reception using
1106 * the PRS as a trigger.
1107 * @note
1108 * Initialize EUSART with EUSART_UartInitHf() or EUSART_UartInitLf() before
1109 * enabling the PRS trigger.
1110 *
1111 * @param eusart Pointer to the EUSART peripheral register block.
1112 * @param init Pointer to the initialization structure.
1113 ******************************************************************************/
1114 void EUSART_PrsTriggerEnable(EUSART_TypeDef *eusart,
1115 const EUSART_PrsTriggerInit_TypeDef *init);
1116
1117 /***************************************************************************//**
1118 * Get EUSART STATUS register.
1119 *
1120 * @param eusart Pointer to the EUSART peripheral register block.
1121 *
1122 * @return STATUS register value.
1123 ******************************************************************************/
EUSART_StatusGet(EUSART_TypeDef * eusart)1124 __STATIC_INLINE uint32_t EUSART_StatusGet(EUSART_TypeDef *eusart)
1125 {
1126 return eusart->STATUS;
1127 }
1128
1129 /***************************************************************************//**
1130 * Clear one or more pending EUSART interrupts.
1131 *
1132 * @param eusart Pointer to the EUSART peripheral register block.
1133 *
1134 * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR
1135 * combination of valid interrupt flags for EUSART module
1136 * (EUSART_IF_nnn).
1137 ******************************************************************************/
EUSART_IntClear(EUSART_TypeDef * eusart,uint32_t flags)1138 __STATIC_INLINE void EUSART_IntClear(EUSART_TypeDef *eusart, uint32_t flags)
1139 {
1140 eusart->IF_CLR = flags;
1141 }
1142
1143 /***************************************************************************//**
1144 * Disable one or more EUSART interrupts.
1145 *
1146 * @param eusart Pointer to the EUSART peripheral register block.
1147 *
1148 * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR
1149 * combination of valid interrupt flags for EUSART module
1150 * (EUSART_IF_nnn).
1151 ******************************************************************************/
EUSART_IntDisable(EUSART_TypeDef * eusart,uint32_t flags)1152 __STATIC_INLINE void EUSART_IntDisable(EUSART_TypeDef *eusart, uint32_t flags)
1153 {
1154 eusart->IEN_CLR = flags;
1155 }
1156
1157 /***************************************************************************//**
1158 * Enable one or more EUSART interrupts.
1159 *
1160 * @param eusart Pointer to the EUSART peripheral register block.
1161 *
1162 * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR
1163 * combination of valid interrupt flags for EUSART module
1164 * (EUSART_IF_nnn).
1165 ******************************************************************************/
EUSART_IntEnable(EUSART_TypeDef * eusart,uint32_t flags)1166 __STATIC_INLINE void EUSART_IntEnable(EUSART_TypeDef *eusart, uint32_t flags)
1167 {
1168 eusart->IEN_SET = flags;
1169 }
1170
1171 /***************************************************************************//**
1172 * Get pending EUSART interrupt flags.
1173 *
1174 * @param eusart Pointer to the EUSART peripheral register block.
1175 *
1176 * @return Pending EUSART interrupt sources.
1177 ******************************************************************************/
EUSART_IntGet(EUSART_TypeDef * eusart)1178 __STATIC_INLINE uint32_t EUSART_IntGet(EUSART_TypeDef *eusart)
1179 {
1180 return eusart->IF;
1181 }
1182
1183 /***************************************************************************//**
1184 * Get enabled and pending EUSART interrupt flags.
1185 * Useful for handling more interrupt sources in the same interrupt handler.
1186 *
1187 * @param eusart Pointer to the EUSART peripheral register block.
1188 *
1189 * @return Pending and enabled EUSART interrupt sources.
1190 ******************************************************************************/
EUSART_IntGetEnabled(EUSART_TypeDef * eusart)1191 __STATIC_INLINE uint32_t EUSART_IntGetEnabled(EUSART_TypeDef *eusart)
1192 {
1193 uint32_t tmp;
1194
1195 /* Store EUSARTx->IEN in temporary variable in order to define explicit order
1196 * of volatile accesses. */
1197 tmp = eusart->IEN;
1198
1199 /* Bitwise AND of pending and enabled interrupts */
1200 return eusart->IF & tmp;
1201 }
1202
1203 /***************************************************************************//**
1204 * Set one or more pending EUSART interrupts from SW.
1205 *
1206 * @param eusart Pointer to the EUSART peripheral register block.
1207 *
1208 * @param flags Interrupt source(s) to set to pending. Use a bitwise logic OR
1209 * combination of valid interrupt flags for EUSART module
1210 * (EUSART_IF_nnn).
1211 ******************************************************************************/
EUSART_IntSet(EUSART_TypeDef * eusart,uint32_t flags)1212 __STATIC_INLINE void EUSART_IntSet(EUSART_TypeDef *eusart, uint32_t flags)
1213 {
1214 eusart->IF_SET = flags;
1215 }
1216
1217 #ifdef __cplusplus
1218 }
1219 #endif
1220
1221 /** @} (end addtogroup eusart) */
1222 #endif /* defined(EUART_PRESENT) || defined(EUSART_PRESENT) */
1223 #endif /* EM_EUSART_H */
1224
