1 /***************************************************************************//**
2  * @file
3  * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices.
4  *******************************************************************************
5  * # License
6  * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
7  *******************************************************************************
8  *
9  * SPDX-License-Identifier: Zlib
10  *
11  * The licensor of this software is Silicon Laboratories Inc.
12  *
13  * This software is provided 'as-is', without any express or implied
14  * warranty. In no event will the authors be held liable for any damages
15  * arising from the use of this software.
16  *
17  * Permission is granted to anyone to use this software for any purpose,
18  * including commercial applications, and to alter it and redistribute it
19  * freely, subject to the following restrictions:
20  *
21  * 1. The origin of this software must not be misrepresented; you must not
22  *    claim that you wrote the original software. If you use this software
23  *    in a product, an acknowledgment in the product documentation would be
24  *    appreciated but is not required.
25  * 2. Altered source versions must be plainly marked as such, and must not be
26  *    misrepresented as being the original software.
27  * 3. This notice may not be removed or altered from any source distribution.
28  *
29  ******************************************************************************/
30 
31 #ifndef SYSTEM_EFR32_H
32 #define SYSTEM_EFR32_H
33 
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 
38 #include <stdint.h>
39 
40 /***************************************************************************//**
41  * @addtogroup Parts
42  * @{
43  ******************************************************************************/
44 /***************************************************************************//**
45  * @addtogroup EFR32 EFR32
46  * @{
47  ******************************************************************************/
48 
49 /*******************************************************************************
50  ******************************   TYPEDEFS   ***********************************
51  ******************************************************************************/
52 
53 /* Interrupt vectortable entry */
54 typedef union {
55   void (*pFunc)(void);
56   void *topOfStack;
57 } tVectorEntry;
58 
59 /*******************************************************************************
60  **************************   GLOBAL VARIABLES   *******************************
61  ******************************************************************************/
62 
63 extern uint32_t SystemCoreClock;    /**< System Clock Frequency (Core Clock) */
64 extern uint32_t SystemHfrcoFreq;    /**< System HFRCO frequency */
65 
66 #if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
67 #if defined(__ICCARM__)    /* IAR requires the __vector_table symbol */
68 #define __Vectors    __vector_table
69 #endif
70 extern const tVectorEntry __Vectors[];
71 #endif
72 
73 /*******************************************************************************
74  *****************************   PROTOTYPES   **********************************
75  ******************************************************************************/
76 
77 void Reset_Handler(void);           /**< Reset Handler */
78 void NMI_Handler(void);             /**< NMI Handler */
79 void HardFault_Handler(void);       /**< Hard Fault Handler */
80 void MemManage_Handler(void);       /**< MPU Fault Handler */
81 void BusFault_Handler(void);        /**< Bus Fault Handler */
82 void UsageFault_Handler(void);      /**< Usage Fault Handler */
83 void SVC_Handler(void);             /**< SVCall Handler */
84 void DebugMon_Handler(void);        /**< Debug Monitor Handler */
85 void PendSV_Handler(void);          /**< PendSV Handler */
86 void SysTick_Handler(void);         /**< SysTick Handler */
87 
88 void EMU_IRQHandler(void);          /**< EMU IRQ Handler */
89 void FRC_PRI_IRQHandler(void);      /**< FRC_PRI IRQ Handler */
90 void WDOG0_IRQHandler(void);        /**< WDOG0 IRQ Handler */
91 void FRC_IRQHandler(void);          /**< FRC IRQ Handler */
92 void MODEM_IRQHandler(void);        /**< MODEM IRQ Handler */
93 void RAC_SEQ_IRQHandler(void);      /**< RAC_SEQ IRQ Handler */
94 void RAC_RSM_IRQHandler(void);      /**< RAC_RSM IRQ Handler */
95 void BUFC_IRQHandler(void);         /**< BUFC IRQ Handler */
96 void LDMA_IRQHandler(void);         /**< LDMA IRQ Handler */
97 void GPIO_EVEN_IRQHandler(void);    /**< GPIO_EVEN IRQ Handler */
98 void TIMER0_IRQHandler(void);       /**< TIMER0 IRQ Handler */
99 void USART0_RX_IRQHandler(void);    /**< USART0_RX IRQ Handler */
100 void USART0_TX_IRQHandler(void);    /**< USART0_TX IRQ Handler */
101 void ACMP0_IRQHandler(void);        /**< ACMP0 IRQ Handler */
102 void ADC0_IRQHandler(void);         /**< ADC0 IRQ Handler */
103 void IDAC0_IRQHandler(void);        /**< IDAC0 IRQ Handler */
104 void I2C0_IRQHandler(void);         /**< I2C0 IRQ Handler */
105 void GPIO_ODD_IRQHandler(void);     /**< GPIO_ODD IRQ Handler */
106 void TIMER1_IRQHandler(void);       /**< TIMER1 IRQ Handler */
107 void USART1_RX_IRQHandler(void);    /**< USART1_RX IRQ Handler */
108 void USART1_TX_IRQHandler(void);    /**< USART1_TX IRQ Handler */
109 void LEUART0_IRQHandler(void);      /**< LEUART0 IRQ Handler */
110 void PCNT0_IRQHandler(void);        /**< PCNT0 IRQ Handler */
111 void CMU_IRQHandler(void);          /**< CMU IRQ Handler */
112 void MSC_IRQHandler(void);          /**< MSC IRQ Handler */
113 void CRYPTO_IRQHandler(void);       /**< CRYPTO IRQ Handler */
114 void LETIMER0_IRQHandler(void);     /**< LETIMER0 IRQ Handler */
115 void AGC_IRQHandler(void);          /**< AGC IRQ Handler */
116 void PROTIMER_IRQHandler(void);     /**< PROTIMER IRQ Handler */
117 void RTCC_IRQHandler(void);         /**< RTCC IRQ Handler */
118 void SYNTH_IRQHandler(void);        /**< SYNTH IRQ Handler */
119 void CRYOTIMER_IRQHandler(void);    /**< CRYOTIMER IRQ Handler */
120 void RFSENSE_IRQHandler(void);      /**< RFSENSE IRQ Handler */
121 
122 #if (__FPU_PRESENT == 1)
123 void FPUEH_IRQHandler(void);        /**< FPUEH IRQ Handler */
124 #endif
125 
126 uint32_t SystemCoreClockGet(void);
127 
128 /***************************************************************************//**
129  * @brief
130  *   Update CMSIS SystemCoreClock variable.
131  *
132  * @details
133  *   CMSIS defines a global variable SystemCoreClock that shall hold the
134  *   core frequency in Hz. If the core frequency is dynamically changed, the
135  *   variable must be kept updated in order to be CMSIS compliant.
136  *
137  *   Notice that only if changing the core clock frequency through the EFR CMU
138  *   API, this variable will be kept updated. This function is only provided
139  *   for CMSIS compliance and if a user modifies the the core clock outside
140  *   the CMU API.
141  ******************************************************************************/
SystemCoreClockUpdate(void)142 static __INLINE void SystemCoreClockUpdate(void)
143 {
144   (void)SystemCoreClockGet();
145 }
146 
147 uint32_t SystemMaxCoreClockGet(void);
148 
149 void SystemInit(void);
150 uint32_t SystemHFClockGet(void);
151 
152 uint32_t SystemHFXOClockGet(void);
153 void SystemHFXOClockSet(uint32_t freq);
154 
155 uint32_t SystemLFRCOClockGet(void);
156 uint32_t SystemULFRCOClockGet(void);
157 
158 uint32_t SystemLFXOClockGet(void);
159 void SystemLFXOClockSet(uint32_t freq);
160 
161 /** @} End of group */
162 /** @} End of group Parts */
163 
164 #ifdef __cplusplus
165 }
166 #endif
167 #endif /* SYSTEM_EFR32_H */
168