1 /***************************************************************************//** 2 * @file 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File 4 * for EFR32BG13P532F512GM32 5 ******************************************************************************* 6 * # License 7 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 8 ******************************************************************************* 9 * 10 * SPDX-License-Identifier: Zlib 11 * 12 * The licensor of this software is Silicon Laboratories Inc. 13 * 14 * This software is provided 'as-is', without any express or implied 15 * warranty. In no event will the authors be held liable for any damages 16 * arising from the use of this software. 17 * 18 * Permission is granted to anyone to use this software for any purpose, 19 * including commercial applications, and to alter it and redistribute it 20 * freely, subject to the following restrictions: 21 * 22 * 1. The origin of this software must not be misrepresented; you must not 23 * claim that you wrote the original software. If you use this software 24 * in a product, an acknowledgment in the product documentation would be 25 * appreciated but is not required. 26 * 2. Altered source versions must be plainly marked as such, and must not be 27 * misrepresented as being the original software. 28 * 3. This notice may not be removed or altered from any source distribution. 29 * 30 ******************************************************************************/ 31 32 #if defined(__ICCARM__) 33 #pragma system_include /* Treat file as system include file. */ 34 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 35 #pragma clang system_header /* Treat file as system include file. */ 36 #endif 37 38 #ifndef EFR32BG13P532F512GM32_H 39 #define EFR32BG13P532F512GM32_H 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /***************************************************************************//** 46 * @addtogroup Parts 47 * @{ 48 ******************************************************************************/ 49 50 /***************************************************************************//** 51 * @defgroup EFR32BG13P532F512GM32 EFR32BG13P532F512GM32 52 * @{ 53 ******************************************************************************/ 54 55 /** Interrupt Number Definition */ 56 typedef enum IRQn{ 57 /****** Cortex-M4 Processor Exceptions Numbers ********************************************/ 58 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ 59 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ 60 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ 61 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ 62 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ 63 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ 64 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ 65 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ 66 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ 67 68 /****** EFR32BG13P Peripheral Interrupt Numbers ********************************************/ 69 70 EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */ 71 FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */ 72 WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */ 73 WDOG1_IRQn = 3, /*!< 16+3 EFR32 WDOG1 Interrupt */ 74 FRC_IRQn = 4, /*!< 16+4 EFR32 FRC Interrupt */ 75 MODEM_IRQn = 5, /*!< 16+5 EFR32 MODEM Interrupt */ 76 RAC_SEQ_IRQn = 6, /*!< 16+6 EFR32 RAC_SEQ Interrupt */ 77 RAC_RSM_IRQn = 7, /*!< 16+7 EFR32 RAC_RSM Interrupt */ 78 BUFC_IRQn = 8, /*!< 16+8 EFR32 BUFC Interrupt */ 79 LDMA_IRQn = 9, /*!< 16+9 EFR32 LDMA Interrupt */ 80 GPIO_EVEN_IRQn = 10, /*!< 16+10 EFR32 GPIO_EVEN Interrupt */ 81 TIMER0_IRQn = 11, /*!< 16+11 EFR32 TIMER0 Interrupt */ 82 USART0_RX_IRQn = 12, /*!< 16+12 EFR32 USART0_RX Interrupt */ 83 USART0_TX_IRQn = 13, /*!< 16+13 EFR32 USART0_TX Interrupt */ 84 ACMP0_IRQn = 14, /*!< 16+14 EFR32 ACMP0 Interrupt */ 85 ADC0_IRQn = 15, /*!< 16+15 EFR32 ADC0 Interrupt */ 86 IDAC0_IRQn = 16, /*!< 16+16 EFR32 IDAC0 Interrupt */ 87 I2C0_IRQn = 17, /*!< 16+17 EFR32 I2C0 Interrupt */ 88 GPIO_ODD_IRQn = 18, /*!< 16+18 EFR32 GPIO_ODD Interrupt */ 89 TIMER1_IRQn = 19, /*!< 16+19 EFR32 TIMER1 Interrupt */ 90 USART1_RX_IRQn = 20, /*!< 16+20 EFR32 USART1_RX Interrupt */ 91 USART1_TX_IRQn = 21, /*!< 16+21 EFR32 USART1_TX Interrupt */ 92 LEUART0_IRQn = 22, /*!< 16+22 EFR32 LEUART0 Interrupt */ 93 PCNT0_IRQn = 23, /*!< 16+23 EFR32 PCNT0 Interrupt */ 94 CMU_IRQn = 24, /*!< 16+24 EFR32 CMU Interrupt */ 95 MSC_IRQn = 25, /*!< 16+25 EFR32 MSC Interrupt */ 96 CRYPTO0_IRQn = 26, /*!< 16+26 EFR32 CRYPTO0 Interrupt */ 97 LETIMER0_IRQn = 27, /*!< 16+27 EFR32 LETIMER0 Interrupt */ 98 AGC_IRQn = 28, /*!< 16+28 EFR32 AGC Interrupt */ 99 PROTIMER_IRQn = 29, /*!< 16+29 EFR32 PROTIMER Interrupt */ 100 PRORTC_IRQn = 30, /*!< 16+30 EFR32 PRORTC Interrupt */ 101 RTCC_IRQn = 31, /*!< 16+31 EFR32 RTCC Interrupt */ 102 SYNTH_IRQn = 32, /*!< 16+32 EFR32 SYNTH Interrupt */ 103 CRYOTIMER_IRQn = 33, /*!< 16+33 EFR32 CRYOTIMER Interrupt */ 104 RFSENSE_IRQn = 34, /*!< 16+34 EFR32 RFSENSE Interrupt */ 105 FPUEH_IRQn = 35, /*!< 16+35 EFR32 FPUEH Interrupt */ 106 SMU_IRQn = 36, /*!< 16+36 EFR32 SMU Interrupt */ 107 WTIMER0_IRQn = 37, /*!< 16+37 EFR32 WTIMER0 Interrupt */ 108 USART2_RX_IRQn = 38, /*!< 16+38 EFR32 USART2_RX Interrupt */ 109 USART2_TX_IRQn = 39, /*!< 16+39 EFR32 USART2_TX Interrupt */ 110 I2C1_IRQn = 40, /*!< 16+40 EFR32 I2C1 Interrupt */ 111 VDAC0_IRQn = 41, /*!< 16+41 EFR32 VDAC0 Interrupt */ 112 CSEN_IRQn = 42, /*!< 16+42 EFR32 CSEN Interrupt */ 113 LESENSE_IRQn = 43, /*!< 16+43 EFR32 LESENSE Interrupt */ 114 CRYPTO1_IRQn = 44, /*!< 16+44 EFR32 CRYPTO1 Interrupt */ 115 TRNG0_IRQn = 45, /*!< 16+45 EFR32 TRNG0 Interrupt */ 116 } IRQn_Type; 117 118 #define CRYPTO_IRQn CRYPTO0_IRQn /*!< Alias for CRYPTO0_IRQn */ 119 120 /***************************************************************************//** 121 * @defgroup EFR32BG13P532F512GM32_Core Core 122 * @{ 123 * @brief Processor and Core Peripheral Section 124 ******************************************************************************/ 125 #define __MPU_PRESENT 1U /**< Presence of MPU */ 126 #define __FPU_PRESENT 1U /**< Presence of FPU */ 127 #define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ 128 #define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ 129 #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ 130 131 /** @} End of group EFR32BG13P532F512GM32_Core */ 132 133 /***************************************************************************//** 134 * @defgroup EFR32BG13P532F512GM32_Part Part 135 * @{ 136 ******************************************************************************/ 137 138 /** Part family */ 139 #define _EFR32_BLUE_FAMILY 1 /**< BLUE Gecko RF SoC Family */ 140 #define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ 141 #define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ 142 #define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ 143 #define _SILICON_LABS_32B_SERIES_1_CONFIG_3 /**< Series 1, Configuration 3 */ 144 #define _SILICON_LABS_32B_SERIES_1_CONFIG 3 /**< Series 1, Configuration 3 */ 145 #define _SILICON_LABS_GECKO_INTERNAL_SDID 89 /**< Silicon Labs internal use only, may change any time */ 146 #define _SILICON_LABS_GECKO_INTERNAL_SDID_89 /**< Silicon Labs internal use only, may change any time */ 147 #define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */ 148 #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */ 149 #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */ 150 #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */ 151 #define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ 152 #define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ 153 #define _SILICON_LABS_32B_PLATFORM_2_GEN_3 /**< @deprecated Platform 2, generation 3 */ 154 #define _SILICON_LABS_32B_PLATFORM_2_GEN 3 /**< @deprecated Platform 2, generation 3 */ 155 156 /* If part number is not defined as compiler option, define it */ 157 #if !defined(EFR32BG13P532F512GM32) 158 #define EFR32BG13P532F512GM32 1 /**< BLUE Gecko Part */ 159 #endif 160 161 /** Configure part number */ 162 #define PART_NUMBER "EFR32BG13P532F512GM32" /**< Part Number */ 163 164 /** Memory Base addresses and limits */ 165 #define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */ 166 #define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */ 167 #define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ 168 #define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ 169 #define RAM1_MEM_BASE (0x20008000UL) /**< RAM1 base address */ 170 #define RAM1_MEM_SIZE (0x8000UL) /**< RAM1 available address space */ 171 #define RAM1_MEM_END (0x2000FFFFUL) /**< RAM1 end address */ 172 #define RAM1_MEM_BITS (0x0000000FUL) /**< RAM1 used bits */ 173 #define RAM2_MEM_BASE (0x20010000UL) /**< RAM2 base address */ 174 #define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */ 175 #define RAM2_MEM_END (0x200107FFUL) /**< RAM2 end address */ 176 #define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */ 177 #define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ 178 #define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ 179 #define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ 180 #define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ 181 #define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ 182 #define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ 183 #define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ 184 #define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ 185 #define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */ 186 #define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */ 187 #define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */ 188 #define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */ 189 #define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ 190 #define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ 191 #define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ 192 #define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ 193 #define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ 194 #define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ 195 #define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ 196 #define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ 197 #define RAM1_CODE_MEM_BASE (0x10008000UL) /**< RAM1_CODE base address */ 198 #define RAM1_CODE_MEM_SIZE (0x8000UL) /**< RAM1_CODE available address space */ 199 #define RAM1_CODE_MEM_END (0x1000FFFFUL) /**< RAM1_CODE end address */ 200 #define RAM1_CODE_MEM_BITS (0x0000000FUL) /**< RAM1_CODE used bits */ 201 #define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ 202 #define RAM0_CODE_MEM_SIZE (0x8000UL) /**< RAM0_CODE available address space */ 203 #define RAM0_CODE_MEM_END (0x10007FFFUL) /**< RAM0_CODE end address */ 204 #define RAM0_CODE_MEM_BITS (0x0000000FUL) /**< RAM0_CODE used bits */ 205 #define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ 206 #define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */ 207 #define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */ 208 #define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */ 209 #define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */ 210 #define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */ 211 #define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */ 212 #define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */ 213 #define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ 214 #define RAM_MEM_SIZE (0x8000UL) /**< RAM available address space */ 215 #define RAM_MEM_END (0x20007FFFUL) /**< RAM end address */ 216 #define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */ 217 #define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ 218 #define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ 219 #define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ 220 #define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ 221 #define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ 222 #define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ 223 #define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ 224 #define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ 225 #define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ 226 #define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */ 227 #define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */ 228 #define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */ 229 #define PER_MEM_BASE (0x40000000UL) /**< PER base address */ 230 #define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */ 231 #define PER_MEM_END (0x400EFFFFUL) /**< PER end address */ 232 #define PER_MEM_BITS (0x00000014UL) /**< PER used bits */ 233 #define RAM2_CODE_MEM_BASE (0x10010000UL) /**< RAM2_CODE base address */ 234 #define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */ 235 #define RAM2_CODE_MEM_END (0x100107FFUL) /**< RAM2_CODE end address */ 236 #define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */ 237 #define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ 238 #define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */ 239 #define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */ 240 #define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */ 241 242 /** Bit banding area */ 243 #define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ 244 #define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ 245 246 /** Flash and SRAM limits for EFR32BG13P532F512GM32 */ 247 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ 248 #define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ 249 #define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */ 250 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ 251 #define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */ 252 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ 253 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ 254 #define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ 255 #define EXT_IRQ_COUNT 47 /**< Number of External (NVIC) interrupts */ 256 257 /** AF channels connect the different on-chip peripherals with the af-mux */ 258 #define AFCHAN_MAX 118U 259 /** AF channel maximum location number */ 260 #define AFCHANLOC_MAX 32U 261 /** Analog AF channels */ 262 #define AFACHAN_MAX 118U 263 264 /* Part number capabilities */ 265 266 #define CRYPTO_PRESENT /**< CRYPTO is available in this part */ 267 #define CRYPTO_COUNT 2 /**< 2 CRYPTOs available */ 268 #define TIMER_PRESENT /**< TIMER is available in this part */ 269 #define TIMER_COUNT 2 /**< 2 TIMERs available */ 270 #define WTIMER_PRESENT /**< WTIMER is available in this part */ 271 #define WTIMER_COUNT 1 /**< 1 WTIMERs available */ 272 #define USART_PRESENT /**< USART is available in this part */ 273 #define USART_COUNT 3 /**< 3 USARTs available */ 274 #define LEUART_PRESENT /**< LEUART is available in this part */ 275 #define LEUART_COUNT 1 /**< 1 LEUARTs available */ 276 #define LETIMER_PRESENT /**< LETIMER is available in this part */ 277 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */ 278 #define PCNT_PRESENT /**< PCNT is available in this part */ 279 #define PCNT_COUNT 1 /**< 1 PCNTs available */ 280 #define I2C_PRESENT /**< I2C is available in this part */ 281 #define I2C_COUNT 2 /**< 2 I2Cs available */ 282 #define ADC_PRESENT /**< ADC is available in this part */ 283 #define ADC_COUNT 1 /**< 1 ADCs available */ 284 #define ACMP_PRESENT /**< ACMP is available in this part */ 285 #define ACMP_COUNT 2 /**< 2 ACMPs available */ 286 #define VDAC_PRESENT /**< VDAC is available in this part */ 287 #define VDAC_COUNT 1 /**< 1 VDACs available */ 288 #define WDOG_PRESENT /**< WDOG is available in this part */ 289 #define WDOG_COUNT 2 /**< 2 WDOGs available */ 290 #define IDAC_PRESENT /**< IDAC is available in this part */ 291 #define IDAC_COUNT 1 /**< 1 IDACs available */ 292 #define TRNG_PRESENT /**< TRNG is available in this part */ 293 #define TRNG_COUNT 1 /**< 1 TRNGs available */ 294 #define MSC_PRESENT /**< MSC is available in this part */ 295 #define MSC_COUNT 1 /**< 1 MSC available */ 296 #define EMU_PRESENT /**< EMU is available in this part */ 297 #define EMU_COUNT 1 /**< 1 EMU available */ 298 #define RMU_PRESENT /**< RMU is available in this part */ 299 #define RMU_COUNT 1 /**< 1 RMU available */ 300 #define CMU_PRESENT /**< CMU is available in this part */ 301 #define CMU_COUNT 1 /**< 1 CMU available */ 302 #define GPIO_PRESENT /**< GPIO is available in this part */ 303 #define GPIO_COUNT 1 /**< 1 GPIO available */ 304 #define PRS_PRESENT /**< PRS is available in this part */ 305 #define PRS_COUNT 1 /**< 1 PRS available */ 306 #define LDMA_PRESENT /**< LDMA is available in this part */ 307 #define LDMA_COUNT 1 /**< 1 LDMA available */ 308 #define FPUEH_PRESENT /**< FPUEH is available in this part */ 309 #define FPUEH_COUNT 1 /**< 1 FPUEH available */ 310 #define GPCRC_PRESENT /**< GPCRC is available in this part */ 311 #define GPCRC_COUNT 1 /**< 1 GPCRC available */ 312 #define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ 313 #define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ 314 #define CSEN_PRESENT /**< CSEN is available in this part */ 315 #define CSEN_COUNT 1 /**< 1 CSEN available */ 316 #define LESENSE_PRESENT /**< LESENSE is available in this part */ 317 #define LESENSE_COUNT 1 /**< 1 LESENSE available */ 318 #define RTCC_PRESENT /**< RTCC is available in this part */ 319 #define RTCC_COUNT 1 /**< 1 RTCC available */ 320 #define PRORTC_PRESENT /**< PRORTC is available in this part */ 321 #define PRORTC_COUNT 1 /**< 1 PRORTC available */ 322 #define ETM_PRESENT /**< ETM is available in this part */ 323 #define ETM_COUNT 1 /**< 1 ETM available */ 324 #define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ 325 #define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ 326 #define SMU_PRESENT /**< SMU is available in this part */ 327 #define SMU_COUNT 1 /**< 1 SMU available */ 328 #define DCDC_PRESENT /**< DCDC is available in this part */ 329 #define DCDC_COUNT 1 /**< 1 DCDC available */ 330 331 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 332 #include "system_efr32bg13p.h" /* System Header File */ 333 334 /** @} End of group EFR32BG13P532F512GM32_Part */ 335 336 /***************************************************************************//** 337 * @defgroup EFR32BG13P532F512GM32_Peripheral_TypeDefs Peripheral TypeDefs 338 * @{ 339 * @brief Device Specific Peripheral Register Structures 340 ******************************************************************************/ 341 342 #include "efr32bg13p_msc.h" 343 #include "efr32bg13p_emu.h" 344 #include "efr32bg13p_rmu.h" 345 346 /***************************************************************************//** 347 * @defgroup EFR32BG13P532F512GM32_CMU CMU 348 * @{ 349 * @brief EFR32BG13P532F512GM32_CMU Register Declaration 350 ******************************************************************************/ 351 /** CMU Register Declaration */ 352 typedef struct { 353 __IOM uint32_t CTRL; /**< CMU Control Register */ 354 355 uint32_t RESERVED0[3U]; /**< Reserved for future use **/ 356 __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ 357 358 uint32_t RESERVED1[1U]; /**< Reserved for future use **/ 359 __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ 360 361 uint32_t RESERVED2[1U]; /**< Reserved for future use **/ 362 __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ 363 __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ 364 365 uint32_t RESERVED3[1U]; /**< Reserved for future use **/ 366 __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ 367 __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ 368 __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ 369 __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ 370 371 uint32_t RESERVED4[1U]; /**< Reserved for future use **/ 372 __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ 373 __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ 374 uint32_t RESERVED5[2U]; /**< Reserved for future use **/ 375 __IOM uint32_t CALCTRL; /**< Calibration Control Register */ 376 __IOM uint32_t CALCNT; /**< Calibration Counter Register */ 377 uint32_t RESERVED6[2U]; /**< Reserved for future use **/ 378 __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ 379 __IOM uint32_t CMD; /**< Command Register */ 380 uint32_t RESERVED7[2U]; /**< Reserved for future use **/ 381 __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ 382 __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ 383 uint32_t RESERVED8[2U]; /**< Reserved for future use **/ 384 __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ 385 __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ 386 __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ 387 388 uint32_t RESERVED9[1U]; /**< Reserved for future use **/ 389 __IM uint32_t STATUS; /**< Status Register */ 390 __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ 391 uint32_t RESERVED10[1U]; /**< Reserved for future use **/ 392 __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ 393 __IM uint32_t IF; /**< Interrupt Flag Register */ 394 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 395 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 396 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 397 __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ 398 399 uint32_t RESERVED11[3U]; /**< Reserved for future use **/ 400 __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ 401 402 uint32_t RESERVED12[7U]; /**< Reserved for future use **/ 403 __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ 404 uint32_t RESERVED13[1U]; /**< Reserved for future use **/ 405 __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ 406 407 uint32_t RESERVED14[1U]; /**< Reserved for future use **/ 408 __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ 409 uint32_t RESERVED15[3U]; /**< Reserved for future use **/ 410 __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ 411 412 uint32_t RESERVED16[1U]; /**< Reserved for future use **/ 413 __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ 414 __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ 415 416 uint32_t RESERVED17[1U]; /**< Reserved for future use **/ 417 __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ 418 419 uint32_t RESERVED18[2U]; /**< Reserved for future use **/ 420 __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ 421 uint32_t RESERVED19[1U]; /**< Reserved for future use **/ 422 __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ 423 uint32_t RESERVED20[1U]; /**< Reserved for future use **/ 424 __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ 425 426 uint32_t RESERVED21[3U]; /**< Reserved for future use **/ 427 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 428 __IOM uint32_t FREEZE; /**< Freeze Register */ 429 uint32_t RESERVED22[2U]; /**< Reserved for future use **/ 430 __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ 431 432 uint32_t RESERVED23[2U]; /**< Reserved for future use **/ 433 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ 434 435 uint32_t RESERVED24[4U]; /**< Reserved for future use **/ 436 __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ 437 __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ 438 __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ 439 uint32_t RESERVED25[1U]; /**< Reserved for future use **/ 440 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 441 __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ 442 443 uint32_t RESERVED26[30U]; /**< Reserved for future use **/ 444 __IOM uint32_t LFRCLKSEL; /**< Low Frequency R Clock Select Register */ 445 uint32_t RESERVED27[3U]; /**< Reserved for future use **/ 446 __IOM uint32_t LFRCLKEN0; /**< Low Frequency R Clock Enable Register 0 (Async Reg) */ 447 uint32_t RESERVED28[1U]; /**< Reserved for future use **/ 448 __IOM uint32_t LFRPRESC0; /**< Low Frequency R Prescaler Register 0 (Async Reg) */ 449 } CMU_TypeDef; /** @} */ 450 451 #include "efr32bg13p_crypto.h" 452 #include "efr32bg13p_gpio_p.h" 453 #include "efr32bg13p_gpio.h" 454 #include "efr32bg13p_prs_ch.h" 455 #include "efr32bg13p_prs.h" 456 #include "efr32bg13p_ldma_ch.h" 457 #include "efr32bg13p_ldma.h" 458 #include "efr32bg13p_fpueh.h" 459 #include "efr32bg13p_gpcrc.h" 460 #include "efr32bg13p_timer_cc.h" 461 #include "efr32bg13p_timer.h" 462 #include "efr32bg13p_usart.h" 463 #include "efr32bg13p_leuart.h" 464 #include "efr32bg13p_letimer.h" 465 #include "efr32bg13p_cryotimer.h" 466 #include "efr32bg13p_pcnt.h" 467 #include "efr32bg13p_i2c.h" 468 #include "efr32bg13p_adc.h" 469 #include "efr32bg13p_acmp.h" 470 #include "efr32bg13p_vdac_opa.h" 471 #include "efr32bg13p_vdac.h" 472 #include "efr32bg13p_csen.h" 473 #include "efr32bg13p_lesense_st.h" 474 #include "efr32bg13p_lesense_buf.h" 475 #include "efr32bg13p_lesense_ch.h" 476 #include "efr32bg13p_lesense.h" 477 #include "efr32bg13p_rtcc_cc.h" 478 #include "efr32bg13p_rtcc_ret.h" 479 #include "efr32bg13p_rtcc.h" 480 #include "efr32bg13p_rtc_comp.h" 481 #include "efr32bg13p_rtc.h" 482 #include "efr32bg13p_wdog_pch.h" 483 #include "efr32bg13p_wdog.h" 484 #include "efr32bg13p_etm.h" 485 #include "efr32bg13p_idac.h" 486 #include "efr32bg13p_smu.h" 487 #include "efr32bg13p_trng.h" 488 #include "efr32bg13p_dma_descriptor.h" 489 #include "efr32bg13p_devinfo.h" 490 #include "efr32bg13p_romtable.h" 491 492 /** @} End of group EFR32BG13P532F512GM32_Peripheral_TypeDefs */ 493 494 /***************************************************************************//** 495 * @defgroup EFR32BG13P532F512GM32_Peripheral_Base Peripheral Memory Map 496 * @{ 497 ******************************************************************************/ 498 499 #define MSC_BASE (0x400E0000UL) /**< MSC base address */ 500 #define EMU_BASE (0x400E3000UL) /**< EMU base address */ 501 #define RMU_BASE (0x400E5000UL) /**< RMU base address */ 502 #define CMU_BASE (0x400E4000UL) /**< CMU base address */ 503 #define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ 504 #define CRYPTO_BASE CRYPTO0_BASE /**< Alias for CRYPTO0 base address */ 505 #define CRYPTO1_BASE (0x400F0400UL) /**< CRYPTO1 base address */ 506 #define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ 507 #define PRS_BASE (0x400E6000UL) /**< PRS base address */ 508 #define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ 509 #define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ 510 #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ 511 #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ 512 #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ 513 #define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ 514 #define USART0_BASE (0x40010000UL) /**< USART0 base address */ 515 #define USART1_BASE (0x40010400UL) /**< USART1 base address */ 516 #define USART2_BASE (0x40010800UL) /**< USART2 base address */ 517 #define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ 518 #define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ 519 #define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ 520 #define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ 521 #define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ 522 #define I2C1_BASE (0x4000C400UL) /**< I2C1 base address */ 523 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ 524 #define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ 525 #define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ 526 #define VDAC0_BASE (0x40008000UL) /**< VDAC0 base address */ 527 #define CSEN_BASE (0x4001F000UL) /**< CSEN base address */ 528 #define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ 529 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ 530 #define PRORTC_BASE (0x40044000UL) /**< PRORTC base address */ 531 #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ 532 #define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ 533 #define ETM_BASE (0xE0041000UL) /**< ETM base address */ 534 #define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ 535 #define SMU_BASE (0x40022000UL) /**< SMU base address */ 536 #define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ 537 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ 538 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ 539 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ 540 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ 541 542 /** @} End of group EFR32BG13P532F512GM32_Peripheral_Base */ 543 544 /***************************************************************************//** 545 * @defgroup EFR32BG13P532F512GM32_Peripheral_Declaration Peripheral Declarations 546 * @{ 547 ******************************************************************************/ 548 549 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ 550 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ 551 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ 552 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ 553 #define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ 554 #define CRYPTO CRYPTO0 /**< Alias for CRYPTO0 base pointer */ 555 #define CRYPTO1 ((CRYPTO_TypeDef *) CRYPTO1_BASE) /**< CRYPTO1 base pointer */ 556 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ 557 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ 558 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ 559 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ 560 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ 561 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ 562 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ 563 #define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ 564 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ 565 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ 566 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ 567 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ 568 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ 569 #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ 570 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ 571 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ 572 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ 573 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ 574 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ 575 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ 576 #define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ 577 #define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ 578 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ 579 #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ 580 #define PRORTC ((RTC_TypeDef *) PRORTC_BASE) /**< PRORTC base pointer */ 581 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ 582 #define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ 583 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ 584 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ 585 #define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ 586 #define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ 587 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ 588 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ 589 590 /** @} End of group EFR32BG13P532F512GM32_Peripheral_Declaration */ 591 592 /***************************************************************************//** 593 * @defgroup EFR32BG13P532F512GM32_Peripheral_Offsets Peripheral Offsets 594 * @{ 595 ******************************************************************************/ 596 597 #define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ 598 #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ 599 #define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ 600 #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ 601 #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ 602 #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ 603 #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ 604 #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ 605 #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ 606 #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ 607 #define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ 608 #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ 609 #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ 610 #define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ 611 612 /** @} End of group EFR32BG13P532F512GM32_Peripheral_Offsets */ 613 614 /***************************************************************************//** 615 * @defgroup EFR32BG13P532F512GM32_BitFields Bit Fields 616 * @{ 617 ******************************************************************************/ 618 619 #include "efr32bg13p_prs_signals.h" 620 #include "efr32bg13p_dmareq.h" 621 622 /***************************************************************************//** 623 * @addtogroup EFR32BG13P532F512GM32_WTIMER 624 * @{ 625 * @defgroup EFR32BG13P532F512GM32_WTIMER_BitFields WTIMER Bit Fields 626 * @{ 627 ******************************************************************************/ 628 629 /* Bit fields for WTIMER CTRL */ 630 #define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ 631 #define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ 632 #define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ 633 #define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ 634 #define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 635 #define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ 636 #define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ 637 #define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ 638 #define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ 639 #define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 640 #define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ 641 #define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ 642 #define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ 643 #define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ 644 #define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ 645 #define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ 646 #define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ 647 #define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 648 #define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 649 #define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ 650 #define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ 651 #define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ 652 #define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 653 #define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 654 #define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ 655 #define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ 656 #define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ 657 #define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 658 #define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ 659 #define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ 660 #define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 661 #define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ 662 #define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ 663 #define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ 664 #define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ 665 #define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ 666 #define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 667 #define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 668 #define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ 669 #define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ 670 #define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ 671 #define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 672 #define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 673 #define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ 674 #define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ 675 #define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 676 #define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ 677 #define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ 678 #define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ 679 #define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ 680 #define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 681 #define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ 682 #define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ 683 #define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ 684 #define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ 685 #define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ 686 #define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ 687 #define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 688 #define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ 689 #define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ 690 #define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ 691 #define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ 692 #define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 693 #define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ 694 #define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ 695 #define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ 696 #define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ 697 #define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ 698 #define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ 699 #define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ 700 #define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 701 #define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 702 #define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ 703 #define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ 704 #define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ 705 #define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 706 #define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 707 #define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ 708 #define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ 709 #define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 710 #define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ 711 #define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ 712 #define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ 713 #define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 714 #define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ 715 #define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ 716 #define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ 717 #define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ 718 #define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ 719 #define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 720 #define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ 721 #define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ 722 #define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ 723 #define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ 724 #define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ 725 #define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ 726 #define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ 727 #define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ 728 #define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ 729 #define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ 730 #define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ 731 #define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 732 #define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ 733 #define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ 734 #define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ 735 #define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ 736 #define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ 737 #define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ 738 #define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ 739 #define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ 740 #define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ 741 #define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ 742 #define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ 743 #define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ 744 #define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ 745 #define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ 746 #define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 747 #define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 748 #define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ 749 #define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ 750 #define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ 751 #define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 752 #define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 753 754 /* Bit fields for WTIMER CMD */ 755 #define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ 756 #define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ 757 #define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ 758 #define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ 759 #define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ 760 #define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ 761 #define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ 762 #define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ 763 #define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ 764 #define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ 765 #define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ 766 #define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ 767 768 /* Bit fields for WTIMER STATUS */ 769 #define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ 770 #define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ 771 #define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ 772 #define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ 773 #define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ 774 #define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 775 #define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 776 #define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ 777 #define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ 778 #define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ 779 #define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 780 #define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ 781 #define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ 782 #define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 783 #define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ 784 #define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ 785 #define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ 786 #define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ 787 #define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ 788 #define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 789 #define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 790 #define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ 791 #define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ 792 #define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ 793 #define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 794 #define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 795 #define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ 796 #define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ 797 #define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ 798 #define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 799 #define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 800 #define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ 801 #define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ 802 #define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ 803 #define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 804 #define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 805 #define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ 806 #define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ 807 #define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ 808 #define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 809 #define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 810 #define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ 811 #define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ 812 #define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ 813 #define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 814 #define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 815 #define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ 816 #define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ 817 #define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ 818 #define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 819 #define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 820 #define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ 821 #define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ 822 #define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ 823 #define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 824 #define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 825 #define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ 826 #define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ 827 #define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ 828 #define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 829 #define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 830 #define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ 831 #define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ 832 #define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ 833 #define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 834 #define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ 835 #define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ 836 #define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 837 #define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ 838 #define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ 839 #define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ 840 #define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ 841 #define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ 842 #define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 843 #define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ 844 #define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ 845 #define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 846 #define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ 847 #define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ 848 #define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ 849 #define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ 850 #define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ 851 #define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 852 #define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ 853 #define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ 854 #define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 855 #define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ 856 #define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ 857 #define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ 858 #define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ 859 #define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ 860 #define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 861 #define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ 862 #define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ 863 #define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 864 #define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ 865 #define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ 866 867 /* Bit fields for WTIMER IF */ 868 #define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ 869 #define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ 870 #define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ 871 #define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ 872 #define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ 873 #define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 874 #define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ 875 #define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ 876 #define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ 877 #define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ 878 #define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 879 #define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ 880 #define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ 881 #define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ 882 #define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ 883 #define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 884 #define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ 885 #define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ 886 #define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ 887 #define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ 888 #define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 889 #define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ 890 #define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ 891 #define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ 892 #define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ 893 #define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 894 #define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ 895 #define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ 896 #define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ 897 #define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ 898 #define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 899 #define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ 900 #define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ 901 #define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ 902 #define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ 903 #define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 904 #define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ 905 #define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ 906 #define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ 907 #define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ 908 #define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 909 #define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ 910 #define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ 911 #define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ 912 #define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ 913 #define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 914 #define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ 915 #define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ 916 #define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ 917 #define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ 918 #define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 919 #define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ 920 #define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ 921 #define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ 922 #define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ 923 #define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 924 #define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ 925 926 /* Bit fields for WTIMER IFS */ 927 #define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ 928 #define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ 929 #define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ 930 #define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ 931 #define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ 932 #define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 933 #define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ 934 #define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ 935 #define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ 936 #define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ 937 #define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 938 #define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ 939 #define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ 940 #define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ 941 #define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ 942 #define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 943 #define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ 944 #define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ 945 #define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ 946 #define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ 947 #define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 948 #define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ 949 #define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ 950 #define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ 951 #define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ 952 #define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 953 #define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ 954 #define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ 955 #define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ 956 #define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ 957 #define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 958 #define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ 959 #define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ 960 #define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ 961 #define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ 962 #define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 963 #define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ 964 #define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ 965 #define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ 966 #define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ 967 #define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 968 #define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ 969 #define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ 970 #define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ 971 #define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ 972 #define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 973 #define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ 974 #define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ 975 #define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ 976 #define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ 977 #define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 978 #define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ 979 #define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ 980 #define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ 981 #define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ 982 #define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 983 #define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ 984 985 /* Bit fields for WTIMER IFC */ 986 #define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ 987 #define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ 988 #define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ 989 #define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ 990 #define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ 991 #define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 992 #define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ 993 #define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ 994 #define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ 995 #define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ 996 #define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 997 #define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ 998 #define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ 999 #define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ 1000 #define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ 1001 #define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1002 #define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1003 #define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ 1004 #define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ 1005 #define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ 1006 #define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1007 #define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1008 #define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ 1009 #define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ 1010 #define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ 1011 #define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1012 #define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1013 #define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ 1014 #define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ 1015 #define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ 1016 #define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1017 #define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1018 #define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ 1019 #define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ 1020 #define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ 1021 #define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1022 #define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1023 #define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ 1024 #define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ 1025 #define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ 1026 #define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1027 #define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1028 #define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ 1029 #define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ 1030 #define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ 1031 #define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1032 #define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1033 #define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ 1034 #define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ 1035 #define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ 1036 #define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1037 #define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1038 #define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ 1039 #define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ 1040 #define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ 1041 #define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1042 #define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1043 1044 /* Bit fields for WTIMER IEN */ 1045 #define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ 1046 #define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ 1047 #define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ 1048 #define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ 1049 #define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ 1050 #define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1051 #define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1052 #define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ 1053 #define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ 1054 #define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ 1055 #define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1056 #define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1057 #define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ 1058 #define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ 1059 #define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ 1060 #define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1061 #define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1062 #define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ 1063 #define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ 1064 #define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ 1065 #define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1066 #define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1067 #define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ 1068 #define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ 1069 #define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ 1070 #define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1071 #define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1072 #define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ 1073 #define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ 1074 #define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ 1075 #define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1076 #define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1077 #define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ 1078 #define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ 1079 #define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ 1080 #define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1081 #define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1082 #define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ 1083 #define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ 1084 #define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ 1085 #define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1086 #define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1087 #define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ 1088 #define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ 1089 #define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ 1090 #define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1091 #define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1092 #define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ 1093 #define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ 1094 #define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ 1095 #define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1096 #define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1097 #define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ 1098 #define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ 1099 #define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ 1100 #define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1101 #define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1102 1103 /* Bit fields for WTIMER TOP */ 1104 #define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ 1105 #define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ 1106 #define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ 1107 #define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ 1108 #define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ 1109 #define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ 1110 1111 /* Bit fields for WTIMER TOPB */ 1112 #define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ 1113 #define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ 1114 #define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ 1115 #define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ 1116 #define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ 1117 #define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ 1118 1119 /* Bit fields for WTIMER CNT */ 1120 #define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ 1121 #define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ 1122 #define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ 1123 #define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ 1124 #define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ 1125 #define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ 1126 1127 /* Bit fields for WTIMER LOCK */ 1128 #define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ 1129 #define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ 1130 #define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ 1131 #define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ 1132 #define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ 1133 #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ 1134 #define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ 1135 #define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ 1136 #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ 1137 #define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ 1138 #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ 1139 #define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ 1140 #define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ 1141 #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ 1142 1143 /* Bit fields for WTIMER ROUTEPEN */ 1144 #define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ 1145 #define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ 1146 #define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ 1147 #define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ 1148 #define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ 1149 #define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1150 #define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1151 #define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ 1152 #define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ 1153 #define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ 1154 #define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1155 #define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1156 #define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ 1157 #define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ 1158 #define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ 1159 #define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1160 #define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1161 #define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ 1162 #define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ 1163 #define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ 1164 #define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1165 #define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1166 #define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ 1167 #define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ 1168 #define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ 1169 #define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1170 #define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1171 #define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ 1172 #define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ 1173 #define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ 1174 #define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1175 #define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1176 #define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ 1177 #define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ 1178 #define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ 1179 #define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1180 #define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1181 1182 /* Bit fields for WTIMER ROUTELOC0 */ 1183 #define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ 1184 #define _WTIMER_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for WTIMER_ROUTELOC0 */ 1185 #define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ 1186 #define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CC0LOC */ 1187 #define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ 1188 #define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ 1189 #define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ 1190 #define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ 1191 #define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ 1192 #define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ 1193 #define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ 1194 #define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ 1195 #define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ 1196 #define _WTIMER_ROUTELOC0_CC0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ 1197 #define _WTIMER_ROUTELOC0_CC0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ 1198 #define _WTIMER_ROUTELOC0_CC0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ 1199 #define _WTIMER_ROUTELOC0_CC0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ 1200 #define _WTIMER_ROUTELOC0_CC0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ 1201 #define _WTIMER_ROUTELOC0_CC0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ 1202 #define _WTIMER_ROUTELOC0_CC0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ 1203 #define _WTIMER_ROUTELOC0_CC0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ 1204 #define _WTIMER_ROUTELOC0_CC0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ 1205 #define _WTIMER_ROUTELOC0_CC0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ 1206 #define _WTIMER_ROUTELOC0_CC0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ 1207 #define _WTIMER_ROUTELOC0_CC0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ 1208 #define _WTIMER_ROUTELOC0_CC0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ 1209 #define _WTIMER_ROUTELOC0_CC0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ 1210 #define _WTIMER_ROUTELOC0_CC0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ 1211 #define _WTIMER_ROUTELOC0_CC0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ 1212 #define _WTIMER_ROUTELOC0_CC0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ 1213 #define _WTIMER_ROUTELOC0_CC0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ 1214 #define _WTIMER_ROUTELOC0_CC0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ 1215 #define _WTIMER_ROUTELOC0_CC0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ 1216 #define _WTIMER_ROUTELOC0_CC0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ 1217 #define _WTIMER_ROUTELOC0_CC0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ 1218 #define _WTIMER_ROUTELOC0_CC0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ 1219 #define _WTIMER_ROUTELOC0_CC0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ 1220 #define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ 1221 #define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ 1222 #define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ 1223 #define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ 1224 #define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ 1225 #define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ 1226 #define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ 1227 #define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ 1228 #define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ 1229 #define WTIMER_ROUTELOC0_CC0LOC_LOC8 (_WTIMER_ROUTELOC0_CC0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ 1230 #define WTIMER_ROUTELOC0_CC0LOC_LOC9 (_WTIMER_ROUTELOC0_CC0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ 1231 #define WTIMER_ROUTELOC0_CC0LOC_LOC10 (_WTIMER_ROUTELOC0_CC0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ 1232 #define WTIMER_ROUTELOC0_CC0LOC_LOC11 (_WTIMER_ROUTELOC0_CC0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ 1233 #define WTIMER_ROUTELOC0_CC0LOC_LOC12 (_WTIMER_ROUTELOC0_CC0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ 1234 #define WTIMER_ROUTELOC0_CC0LOC_LOC13 (_WTIMER_ROUTELOC0_CC0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ 1235 #define WTIMER_ROUTELOC0_CC0LOC_LOC14 (_WTIMER_ROUTELOC0_CC0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ 1236 #define WTIMER_ROUTELOC0_CC0LOC_LOC15 (_WTIMER_ROUTELOC0_CC0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ 1237 #define WTIMER_ROUTELOC0_CC0LOC_LOC16 (_WTIMER_ROUTELOC0_CC0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ 1238 #define WTIMER_ROUTELOC0_CC0LOC_LOC17 (_WTIMER_ROUTELOC0_CC0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ 1239 #define WTIMER_ROUTELOC0_CC0LOC_LOC18 (_WTIMER_ROUTELOC0_CC0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ 1240 #define WTIMER_ROUTELOC0_CC0LOC_LOC19 (_WTIMER_ROUTELOC0_CC0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ 1241 #define WTIMER_ROUTELOC0_CC0LOC_LOC20 (_WTIMER_ROUTELOC0_CC0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ 1242 #define WTIMER_ROUTELOC0_CC0LOC_LOC21 (_WTIMER_ROUTELOC0_CC0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ 1243 #define WTIMER_ROUTELOC0_CC0LOC_LOC22 (_WTIMER_ROUTELOC0_CC0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ 1244 #define WTIMER_ROUTELOC0_CC0LOC_LOC23 (_WTIMER_ROUTELOC0_CC0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ 1245 #define WTIMER_ROUTELOC0_CC0LOC_LOC24 (_WTIMER_ROUTELOC0_CC0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ 1246 #define WTIMER_ROUTELOC0_CC0LOC_LOC25 (_WTIMER_ROUTELOC0_CC0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ 1247 #define WTIMER_ROUTELOC0_CC0LOC_LOC26 (_WTIMER_ROUTELOC0_CC0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ 1248 #define WTIMER_ROUTELOC0_CC0LOC_LOC27 (_WTIMER_ROUTELOC0_CC0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ 1249 #define WTIMER_ROUTELOC0_CC0LOC_LOC28 (_WTIMER_ROUTELOC0_CC0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ 1250 #define WTIMER_ROUTELOC0_CC0LOC_LOC29 (_WTIMER_ROUTELOC0_CC0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ 1251 #define WTIMER_ROUTELOC0_CC0LOC_LOC30 (_WTIMER_ROUTELOC0_CC0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ 1252 #define WTIMER_ROUTELOC0_CC0LOC_LOC31 (_WTIMER_ROUTELOC0_CC0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ 1253 #define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ 1254 #define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CC1LOC */ 1255 #define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ 1256 #define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ 1257 #define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ 1258 #define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ 1259 #define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ 1260 #define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ 1261 #define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ 1262 #define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ 1263 #define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ 1264 #define _WTIMER_ROUTELOC0_CC1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ 1265 #define _WTIMER_ROUTELOC0_CC1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ 1266 #define _WTIMER_ROUTELOC0_CC1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ 1267 #define _WTIMER_ROUTELOC0_CC1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ 1268 #define _WTIMER_ROUTELOC0_CC1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ 1269 #define _WTIMER_ROUTELOC0_CC1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ 1270 #define _WTIMER_ROUTELOC0_CC1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ 1271 #define _WTIMER_ROUTELOC0_CC1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ 1272 #define _WTIMER_ROUTELOC0_CC1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ 1273 #define _WTIMER_ROUTELOC0_CC1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ 1274 #define _WTIMER_ROUTELOC0_CC1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ 1275 #define _WTIMER_ROUTELOC0_CC1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ 1276 #define _WTIMER_ROUTELOC0_CC1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ 1277 #define _WTIMER_ROUTELOC0_CC1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ 1278 #define _WTIMER_ROUTELOC0_CC1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ 1279 #define _WTIMER_ROUTELOC0_CC1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ 1280 #define _WTIMER_ROUTELOC0_CC1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ 1281 #define _WTIMER_ROUTELOC0_CC1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ 1282 #define _WTIMER_ROUTELOC0_CC1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ 1283 #define _WTIMER_ROUTELOC0_CC1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ 1284 #define _WTIMER_ROUTELOC0_CC1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ 1285 #define _WTIMER_ROUTELOC0_CC1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ 1286 #define _WTIMER_ROUTELOC0_CC1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ 1287 #define _WTIMER_ROUTELOC0_CC1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ 1288 #define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ 1289 #define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ 1290 #define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ 1291 #define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ 1292 #define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ 1293 #define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ 1294 #define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ 1295 #define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ 1296 #define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ 1297 #define WTIMER_ROUTELOC0_CC1LOC_LOC8 (_WTIMER_ROUTELOC0_CC1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ 1298 #define WTIMER_ROUTELOC0_CC1LOC_LOC9 (_WTIMER_ROUTELOC0_CC1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ 1299 #define WTIMER_ROUTELOC0_CC1LOC_LOC10 (_WTIMER_ROUTELOC0_CC1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ 1300 #define WTIMER_ROUTELOC0_CC1LOC_LOC11 (_WTIMER_ROUTELOC0_CC1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ 1301 #define WTIMER_ROUTELOC0_CC1LOC_LOC12 (_WTIMER_ROUTELOC0_CC1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ 1302 #define WTIMER_ROUTELOC0_CC1LOC_LOC13 (_WTIMER_ROUTELOC0_CC1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ 1303 #define WTIMER_ROUTELOC0_CC1LOC_LOC14 (_WTIMER_ROUTELOC0_CC1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ 1304 #define WTIMER_ROUTELOC0_CC1LOC_LOC15 (_WTIMER_ROUTELOC0_CC1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ 1305 #define WTIMER_ROUTELOC0_CC1LOC_LOC16 (_WTIMER_ROUTELOC0_CC1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ 1306 #define WTIMER_ROUTELOC0_CC1LOC_LOC17 (_WTIMER_ROUTELOC0_CC1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ 1307 #define WTIMER_ROUTELOC0_CC1LOC_LOC18 (_WTIMER_ROUTELOC0_CC1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ 1308 #define WTIMER_ROUTELOC0_CC1LOC_LOC19 (_WTIMER_ROUTELOC0_CC1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ 1309 #define WTIMER_ROUTELOC0_CC1LOC_LOC20 (_WTIMER_ROUTELOC0_CC1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ 1310 #define WTIMER_ROUTELOC0_CC1LOC_LOC21 (_WTIMER_ROUTELOC0_CC1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ 1311 #define WTIMER_ROUTELOC0_CC1LOC_LOC22 (_WTIMER_ROUTELOC0_CC1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ 1312 #define WTIMER_ROUTELOC0_CC1LOC_LOC23 (_WTIMER_ROUTELOC0_CC1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ 1313 #define WTIMER_ROUTELOC0_CC1LOC_LOC24 (_WTIMER_ROUTELOC0_CC1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ 1314 #define WTIMER_ROUTELOC0_CC1LOC_LOC25 (_WTIMER_ROUTELOC0_CC1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ 1315 #define WTIMER_ROUTELOC0_CC1LOC_LOC26 (_WTIMER_ROUTELOC0_CC1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ 1316 #define WTIMER_ROUTELOC0_CC1LOC_LOC27 (_WTIMER_ROUTELOC0_CC1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ 1317 #define WTIMER_ROUTELOC0_CC1LOC_LOC28 (_WTIMER_ROUTELOC0_CC1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ 1318 #define WTIMER_ROUTELOC0_CC1LOC_LOC29 (_WTIMER_ROUTELOC0_CC1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ 1319 #define WTIMER_ROUTELOC0_CC1LOC_LOC30 (_WTIMER_ROUTELOC0_CC1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ 1320 #define WTIMER_ROUTELOC0_CC1LOC_LOC31 (_WTIMER_ROUTELOC0_CC1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ 1321 #define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ 1322 #define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CC2LOC */ 1323 #define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ 1324 #define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ 1325 #define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ 1326 #define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ 1327 #define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ 1328 #define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ 1329 #define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ 1330 #define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ 1331 #define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ 1332 #define _WTIMER_ROUTELOC0_CC2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ 1333 #define _WTIMER_ROUTELOC0_CC2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ 1334 #define _WTIMER_ROUTELOC0_CC2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ 1335 #define _WTIMER_ROUTELOC0_CC2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ 1336 #define _WTIMER_ROUTELOC0_CC2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ 1337 #define _WTIMER_ROUTELOC0_CC2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ 1338 #define _WTIMER_ROUTELOC0_CC2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ 1339 #define _WTIMER_ROUTELOC0_CC2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ 1340 #define _WTIMER_ROUTELOC0_CC2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ 1341 #define _WTIMER_ROUTELOC0_CC2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ 1342 #define _WTIMER_ROUTELOC0_CC2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ 1343 #define _WTIMER_ROUTELOC0_CC2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ 1344 #define _WTIMER_ROUTELOC0_CC2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ 1345 #define _WTIMER_ROUTELOC0_CC2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ 1346 #define _WTIMER_ROUTELOC0_CC2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ 1347 #define _WTIMER_ROUTELOC0_CC2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ 1348 #define _WTIMER_ROUTELOC0_CC2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ 1349 #define _WTIMER_ROUTELOC0_CC2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ 1350 #define _WTIMER_ROUTELOC0_CC2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ 1351 #define _WTIMER_ROUTELOC0_CC2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ 1352 #define _WTIMER_ROUTELOC0_CC2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ 1353 #define _WTIMER_ROUTELOC0_CC2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ 1354 #define _WTIMER_ROUTELOC0_CC2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ 1355 #define _WTIMER_ROUTELOC0_CC2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ 1356 #define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ 1357 #define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ 1358 #define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ 1359 #define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ 1360 #define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ 1361 #define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ 1362 #define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ 1363 #define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ 1364 #define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ 1365 #define WTIMER_ROUTELOC0_CC2LOC_LOC8 (_WTIMER_ROUTELOC0_CC2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ 1366 #define WTIMER_ROUTELOC0_CC2LOC_LOC9 (_WTIMER_ROUTELOC0_CC2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ 1367 #define WTIMER_ROUTELOC0_CC2LOC_LOC10 (_WTIMER_ROUTELOC0_CC2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ 1368 #define WTIMER_ROUTELOC0_CC2LOC_LOC11 (_WTIMER_ROUTELOC0_CC2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ 1369 #define WTIMER_ROUTELOC0_CC2LOC_LOC12 (_WTIMER_ROUTELOC0_CC2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ 1370 #define WTIMER_ROUTELOC0_CC2LOC_LOC13 (_WTIMER_ROUTELOC0_CC2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ 1371 #define WTIMER_ROUTELOC0_CC2LOC_LOC14 (_WTIMER_ROUTELOC0_CC2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ 1372 #define WTIMER_ROUTELOC0_CC2LOC_LOC15 (_WTIMER_ROUTELOC0_CC2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ 1373 #define WTIMER_ROUTELOC0_CC2LOC_LOC16 (_WTIMER_ROUTELOC0_CC2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ 1374 #define WTIMER_ROUTELOC0_CC2LOC_LOC17 (_WTIMER_ROUTELOC0_CC2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ 1375 #define WTIMER_ROUTELOC0_CC2LOC_LOC18 (_WTIMER_ROUTELOC0_CC2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ 1376 #define WTIMER_ROUTELOC0_CC2LOC_LOC19 (_WTIMER_ROUTELOC0_CC2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ 1377 #define WTIMER_ROUTELOC0_CC2LOC_LOC20 (_WTIMER_ROUTELOC0_CC2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ 1378 #define WTIMER_ROUTELOC0_CC2LOC_LOC21 (_WTIMER_ROUTELOC0_CC2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ 1379 #define WTIMER_ROUTELOC0_CC2LOC_LOC22 (_WTIMER_ROUTELOC0_CC2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ 1380 #define WTIMER_ROUTELOC0_CC2LOC_LOC23 (_WTIMER_ROUTELOC0_CC2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ 1381 #define WTIMER_ROUTELOC0_CC2LOC_LOC24 (_WTIMER_ROUTELOC0_CC2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ 1382 #define WTIMER_ROUTELOC0_CC2LOC_LOC25 (_WTIMER_ROUTELOC0_CC2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ 1383 #define WTIMER_ROUTELOC0_CC2LOC_LOC26 (_WTIMER_ROUTELOC0_CC2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ 1384 #define WTIMER_ROUTELOC0_CC2LOC_LOC27 (_WTIMER_ROUTELOC0_CC2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ 1385 #define WTIMER_ROUTELOC0_CC2LOC_LOC28 (_WTIMER_ROUTELOC0_CC2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ 1386 #define WTIMER_ROUTELOC0_CC2LOC_LOC29 (_WTIMER_ROUTELOC0_CC2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ 1387 #define WTIMER_ROUTELOC0_CC2LOC_LOC30 (_WTIMER_ROUTELOC0_CC2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ 1388 #define WTIMER_ROUTELOC0_CC2LOC_LOC31 (_WTIMER_ROUTELOC0_CC2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ 1389 #define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ 1390 #define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x1F000000UL /**< Bit mask for TIMER_CC3LOC */ 1391 #define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ 1392 #define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ 1393 #define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ 1394 #define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ 1395 #define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ 1396 #define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ 1397 #define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ 1398 #define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ 1399 #define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ 1400 #define _WTIMER_ROUTELOC0_CC3LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC0 */ 1401 #define _WTIMER_ROUTELOC0_CC3LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC0 */ 1402 #define _WTIMER_ROUTELOC0_CC3LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC0 */ 1403 #define _WTIMER_ROUTELOC0_CC3LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC0 */ 1404 #define _WTIMER_ROUTELOC0_CC3LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC0 */ 1405 #define _WTIMER_ROUTELOC0_CC3LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC0 */ 1406 #define _WTIMER_ROUTELOC0_CC3LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC0 */ 1407 #define _WTIMER_ROUTELOC0_CC3LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC0 */ 1408 #define _WTIMER_ROUTELOC0_CC3LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC0 */ 1409 #define _WTIMER_ROUTELOC0_CC3LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC0 */ 1410 #define _WTIMER_ROUTELOC0_CC3LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC0 */ 1411 #define _WTIMER_ROUTELOC0_CC3LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC0 */ 1412 #define _WTIMER_ROUTELOC0_CC3LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC0 */ 1413 #define _WTIMER_ROUTELOC0_CC3LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC0 */ 1414 #define _WTIMER_ROUTELOC0_CC3LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC0 */ 1415 #define _WTIMER_ROUTELOC0_CC3LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC0 */ 1416 #define _WTIMER_ROUTELOC0_CC3LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC0 */ 1417 #define _WTIMER_ROUTELOC0_CC3LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC0 */ 1418 #define _WTIMER_ROUTELOC0_CC3LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC0 */ 1419 #define _WTIMER_ROUTELOC0_CC3LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC0 */ 1420 #define _WTIMER_ROUTELOC0_CC3LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC0 */ 1421 #define _WTIMER_ROUTELOC0_CC3LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC0 */ 1422 #define _WTIMER_ROUTELOC0_CC3LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC0 */ 1423 #define _WTIMER_ROUTELOC0_CC3LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC0 */ 1424 #define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ 1425 #define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ 1426 #define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ 1427 #define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ 1428 #define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ 1429 #define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ 1430 #define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ 1431 #define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ 1432 #define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ 1433 #define WTIMER_ROUTELOC0_CC3LOC_LOC8 (_WTIMER_ROUTELOC0_CC3LOC_LOC8 << 24) /**< Shifted mode LOC8 for WTIMER_ROUTELOC0 */ 1434 #define WTIMER_ROUTELOC0_CC3LOC_LOC9 (_WTIMER_ROUTELOC0_CC3LOC_LOC9 << 24) /**< Shifted mode LOC9 for WTIMER_ROUTELOC0 */ 1435 #define WTIMER_ROUTELOC0_CC3LOC_LOC10 (_WTIMER_ROUTELOC0_CC3LOC_LOC10 << 24) /**< Shifted mode LOC10 for WTIMER_ROUTELOC0 */ 1436 #define WTIMER_ROUTELOC0_CC3LOC_LOC11 (_WTIMER_ROUTELOC0_CC3LOC_LOC11 << 24) /**< Shifted mode LOC11 for WTIMER_ROUTELOC0 */ 1437 #define WTIMER_ROUTELOC0_CC3LOC_LOC12 (_WTIMER_ROUTELOC0_CC3LOC_LOC12 << 24) /**< Shifted mode LOC12 for WTIMER_ROUTELOC0 */ 1438 #define WTIMER_ROUTELOC0_CC3LOC_LOC13 (_WTIMER_ROUTELOC0_CC3LOC_LOC13 << 24) /**< Shifted mode LOC13 for WTIMER_ROUTELOC0 */ 1439 #define WTIMER_ROUTELOC0_CC3LOC_LOC14 (_WTIMER_ROUTELOC0_CC3LOC_LOC14 << 24) /**< Shifted mode LOC14 for WTIMER_ROUTELOC0 */ 1440 #define WTIMER_ROUTELOC0_CC3LOC_LOC15 (_WTIMER_ROUTELOC0_CC3LOC_LOC15 << 24) /**< Shifted mode LOC15 for WTIMER_ROUTELOC0 */ 1441 #define WTIMER_ROUTELOC0_CC3LOC_LOC16 (_WTIMER_ROUTELOC0_CC3LOC_LOC16 << 24) /**< Shifted mode LOC16 for WTIMER_ROUTELOC0 */ 1442 #define WTIMER_ROUTELOC0_CC3LOC_LOC17 (_WTIMER_ROUTELOC0_CC3LOC_LOC17 << 24) /**< Shifted mode LOC17 for WTIMER_ROUTELOC0 */ 1443 #define WTIMER_ROUTELOC0_CC3LOC_LOC18 (_WTIMER_ROUTELOC0_CC3LOC_LOC18 << 24) /**< Shifted mode LOC18 for WTIMER_ROUTELOC0 */ 1444 #define WTIMER_ROUTELOC0_CC3LOC_LOC19 (_WTIMER_ROUTELOC0_CC3LOC_LOC19 << 24) /**< Shifted mode LOC19 for WTIMER_ROUTELOC0 */ 1445 #define WTIMER_ROUTELOC0_CC3LOC_LOC20 (_WTIMER_ROUTELOC0_CC3LOC_LOC20 << 24) /**< Shifted mode LOC20 for WTIMER_ROUTELOC0 */ 1446 #define WTIMER_ROUTELOC0_CC3LOC_LOC21 (_WTIMER_ROUTELOC0_CC3LOC_LOC21 << 24) /**< Shifted mode LOC21 for WTIMER_ROUTELOC0 */ 1447 #define WTIMER_ROUTELOC0_CC3LOC_LOC22 (_WTIMER_ROUTELOC0_CC3LOC_LOC22 << 24) /**< Shifted mode LOC22 for WTIMER_ROUTELOC0 */ 1448 #define WTIMER_ROUTELOC0_CC3LOC_LOC23 (_WTIMER_ROUTELOC0_CC3LOC_LOC23 << 24) /**< Shifted mode LOC23 for WTIMER_ROUTELOC0 */ 1449 #define WTIMER_ROUTELOC0_CC3LOC_LOC24 (_WTIMER_ROUTELOC0_CC3LOC_LOC24 << 24) /**< Shifted mode LOC24 for WTIMER_ROUTELOC0 */ 1450 #define WTIMER_ROUTELOC0_CC3LOC_LOC25 (_WTIMER_ROUTELOC0_CC3LOC_LOC25 << 24) /**< Shifted mode LOC25 for WTIMER_ROUTELOC0 */ 1451 #define WTIMER_ROUTELOC0_CC3LOC_LOC26 (_WTIMER_ROUTELOC0_CC3LOC_LOC26 << 24) /**< Shifted mode LOC26 for WTIMER_ROUTELOC0 */ 1452 #define WTIMER_ROUTELOC0_CC3LOC_LOC27 (_WTIMER_ROUTELOC0_CC3LOC_LOC27 << 24) /**< Shifted mode LOC27 for WTIMER_ROUTELOC0 */ 1453 #define WTIMER_ROUTELOC0_CC3LOC_LOC28 (_WTIMER_ROUTELOC0_CC3LOC_LOC28 << 24) /**< Shifted mode LOC28 for WTIMER_ROUTELOC0 */ 1454 #define WTIMER_ROUTELOC0_CC3LOC_LOC29 (_WTIMER_ROUTELOC0_CC3LOC_LOC29 << 24) /**< Shifted mode LOC29 for WTIMER_ROUTELOC0 */ 1455 #define WTIMER_ROUTELOC0_CC3LOC_LOC30 (_WTIMER_ROUTELOC0_CC3LOC_LOC30 << 24) /**< Shifted mode LOC30 for WTIMER_ROUTELOC0 */ 1456 #define WTIMER_ROUTELOC0_CC3LOC_LOC31 (_WTIMER_ROUTELOC0_CC3LOC_LOC31 << 24) /**< Shifted mode LOC31 for WTIMER_ROUTELOC0 */ 1457 1458 /* Bit fields for WTIMER ROUTELOC2 */ 1459 #define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ 1460 #define _WTIMER_ROUTELOC2_MASK 0x001F1F1FUL /**< Mask for WTIMER_ROUTELOC2 */ 1461 #define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ 1462 #define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x1FUL /**< Bit mask for TIMER_CDTI0LOC */ 1463 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ 1464 #define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ 1465 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ 1466 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ 1467 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ 1468 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ 1469 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ 1470 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ 1471 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ 1472 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ 1473 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ 1474 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ 1475 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ 1476 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ 1477 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ 1478 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ 1479 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ 1480 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ 1481 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ 1482 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ 1483 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ 1484 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ 1485 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ 1486 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ 1487 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ 1488 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ 1489 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ 1490 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ 1491 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ 1492 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ 1493 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ 1494 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ 1495 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ 1496 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ 1497 #define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ 1498 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ 1499 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ 1500 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ 1501 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ 1502 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ 1503 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ 1504 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ 1505 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC8 << 0) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ 1506 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC9 << 0) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ 1507 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC10 << 0) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ 1508 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC11 << 0) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ 1509 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC12 << 0) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ 1510 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC13 << 0) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ 1511 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC14 << 0) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ 1512 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC15 << 0) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ 1513 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC16 << 0) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ 1514 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC17 << 0) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ 1515 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC18 << 0) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ 1516 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC19 << 0) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ 1517 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC20 << 0) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ 1518 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC21 << 0) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ 1519 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC22 << 0) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ 1520 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC23 << 0) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ 1521 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC24 << 0) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ 1522 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC25 << 0) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ 1523 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC26 << 0) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ 1524 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC27 << 0) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ 1525 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC28 << 0) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ 1526 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC29 << 0) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ 1527 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC30 << 0) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ 1528 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC31 << 0) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ 1529 #define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ 1530 #define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x1F00UL /**< Bit mask for TIMER_CDTI1LOC */ 1531 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ 1532 #define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ 1533 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ 1534 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ 1535 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ 1536 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ 1537 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ 1538 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ 1539 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ 1540 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ 1541 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ 1542 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ 1543 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ 1544 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ 1545 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ 1546 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ 1547 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ 1548 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ 1549 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ 1550 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ 1551 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ 1552 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ 1553 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ 1554 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ 1555 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ 1556 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ 1557 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ 1558 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ 1559 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ 1560 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ 1561 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ 1562 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ 1563 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ 1564 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ 1565 #define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ 1566 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ 1567 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ 1568 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ 1569 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ 1570 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ 1571 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ 1572 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ 1573 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC8 << 8) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ 1574 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC9 << 8) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ 1575 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC10 << 8) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ 1576 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC11 << 8) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ 1577 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC12 << 8) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ 1578 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC13 << 8) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ 1579 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC14 << 8) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ 1580 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC15 << 8) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ 1581 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC16 << 8) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ 1582 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC17 << 8) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ 1583 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC18 << 8) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ 1584 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC19 << 8) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ 1585 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC20 << 8) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ 1586 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC21 << 8) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ 1587 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC22 << 8) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ 1588 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC23 << 8) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ 1589 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC24 << 8) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ 1590 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC25 << 8) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ 1591 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC26 << 8) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ 1592 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC27 << 8) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ 1593 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC28 << 8) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ 1594 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC29 << 8) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ 1595 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC30 << 8) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ 1596 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC31 << 8) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ 1597 #define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ 1598 #define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x1F0000UL /**< Bit mask for TIMER_CDTI2LOC */ 1599 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ 1600 #define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ 1601 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ 1602 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ 1603 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ 1604 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ 1605 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC2 */ 1606 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC2 */ 1607 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC2 */ 1608 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC8 0x00000008UL /**< Mode LOC8 for WTIMER_ROUTELOC2 */ 1609 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC9 0x00000009UL /**< Mode LOC9 for WTIMER_ROUTELOC2 */ 1610 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC10 0x0000000AUL /**< Mode LOC10 for WTIMER_ROUTELOC2 */ 1611 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC11 0x0000000BUL /**< Mode LOC11 for WTIMER_ROUTELOC2 */ 1612 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC12 0x0000000CUL /**< Mode LOC12 for WTIMER_ROUTELOC2 */ 1613 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC13 0x0000000DUL /**< Mode LOC13 for WTIMER_ROUTELOC2 */ 1614 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC14 0x0000000EUL /**< Mode LOC14 for WTIMER_ROUTELOC2 */ 1615 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC15 0x0000000FUL /**< Mode LOC15 for WTIMER_ROUTELOC2 */ 1616 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC16 0x00000010UL /**< Mode LOC16 for WTIMER_ROUTELOC2 */ 1617 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC17 0x00000011UL /**< Mode LOC17 for WTIMER_ROUTELOC2 */ 1618 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC18 0x00000012UL /**< Mode LOC18 for WTIMER_ROUTELOC2 */ 1619 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC19 0x00000013UL /**< Mode LOC19 for WTIMER_ROUTELOC2 */ 1620 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC20 0x00000014UL /**< Mode LOC20 for WTIMER_ROUTELOC2 */ 1621 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC21 0x00000015UL /**< Mode LOC21 for WTIMER_ROUTELOC2 */ 1622 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC22 0x00000016UL /**< Mode LOC22 for WTIMER_ROUTELOC2 */ 1623 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC23 0x00000017UL /**< Mode LOC23 for WTIMER_ROUTELOC2 */ 1624 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC24 0x00000018UL /**< Mode LOC24 for WTIMER_ROUTELOC2 */ 1625 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC25 0x00000019UL /**< Mode LOC25 for WTIMER_ROUTELOC2 */ 1626 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC26 0x0000001AUL /**< Mode LOC26 for WTIMER_ROUTELOC2 */ 1627 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC27 0x0000001BUL /**< Mode LOC27 for WTIMER_ROUTELOC2 */ 1628 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC28 0x0000001CUL /**< Mode LOC28 for WTIMER_ROUTELOC2 */ 1629 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC29 0x0000001DUL /**< Mode LOC29 for WTIMER_ROUTELOC2 */ 1630 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC30 0x0000001EUL /**< Mode LOC30 for WTIMER_ROUTELOC2 */ 1631 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC31 0x0000001FUL /**< Mode LOC31 for WTIMER_ROUTELOC2 */ 1632 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ 1633 #define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ 1634 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ 1635 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ 1636 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ 1637 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ 1638 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC5 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC2 */ 1639 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC6 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC2 */ 1640 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC7 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC2 */ 1641 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC8 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC8 << 16) /**< Shifted mode LOC8 for WTIMER_ROUTELOC2 */ 1642 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC9 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC9 << 16) /**< Shifted mode LOC9 for WTIMER_ROUTELOC2 */ 1643 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC10 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC10 << 16) /**< Shifted mode LOC10 for WTIMER_ROUTELOC2 */ 1644 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC11 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC11 << 16) /**< Shifted mode LOC11 for WTIMER_ROUTELOC2 */ 1645 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC12 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC12 << 16) /**< Shifted mode LOC12 for WTIMER_ROUTELOC2 */ 1646 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC13 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC13 << 16) /**< Shifted mode LOC13 for WTIMER_ROUTELOC2 */ 1647 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC14 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC14 << 16) /**< Shifted mode LOC14 for WTIMER_ROUTELOC2 */ 1648 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC15 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC15 << 16) /**< Shifted mode LOC15 for WTIMER_ROUTELOC2 */ 1649 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC16 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC16 << 16) /**< Shifted mode LOC16 for WTIMER_ROUTELOC2 */ 1650 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC17 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC17 << 16) /**< Shifted mode LOC17 for WTIMER_ROUTELOC2 */ 1651 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC18 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC18 << 16) /**< Shifted mode LOC18 for WTIMER_ROUTELOC2 */ 1652 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC19 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC19 << 16) /**< Shifted mode LOC19 for WTIMER_ROUTELOC2 */ 1653 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC20 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC20 << 16) /**< Shifted mode LOC20 for WTIMER_ROUTELOC2 */ 1654 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC21 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC21 << 16) /**< Shifted mode LOC21 for WTIMER_ROUTELOC2 */ 1655 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC22 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC22 << 16) /**< Shifted mode LOC22 for WTIMER_ROUTELOC2 */ 1656 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC23 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC23 << 16) /**< Shifted mode LOC23 for WTIMER_ROUTELOC2 */ 1657 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC24 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC24 << 16) /**< Shifted mode LOC24 for WTIMER_ROUTELOC2 */ 1658 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC25 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC25 << 16) /**< Shifted mode LOC25 for WTIMER_ROUTELOC2 */ 1659 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC26 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC26 << 16) /**< Shifted mode LOC26 for WTIMER_ROUTELOC2 */ 1660 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC27 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC27 << 16) /**< Shifted mode LOC27 for WTIMER_ROUTELOC2 */ 1661 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC28 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC28 << 16) /**< Shifted mode LOC28 for WTIMER_ROUTELOC2 */ 1662 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC29 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC29 << 16) /**< Shifted mode LOC29 for WTIMER_ROUTELOC2 */ 1663 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC30 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC30 << 16) /**< Shifted mode LOC30 for WTIMER_ROUTELOC2 */ 1664 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC31 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC31 << 16) /**< Shifted mode LOC31 for WTIMER_ROUTELOC2 */ 1665 1666 /* Bit fields for WTIMER CC_CTRL */ 1667 #define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ 1668 #define _WTIMER_CC_CTRL_MASK 0x7F0F3F17UL /**< Mask for WTIMER_CC_CTRL */ 1669 #define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ 1670 #define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ 1671 #define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1672 #define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ 1673 #define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ 1674 #define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ 1675 #define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ 1676 #define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1677 #define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ 1678 #define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ 1679 #define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ 1680 #define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ 1681 #define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ 1682 #define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ 1683 #define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ 1684 #define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1685 #define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1686 #define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ 1687 #define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ 1688 #define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ 1689 #define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1690 #define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1691 #define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ 1692 #define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ 1693 #define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1694 #define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ 1695 #define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ 1696 #define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ 1697 #define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ 1698 #define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1699 #define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ 1700 #define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ 1701 #define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ 1702 #define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ 1703 #define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ 1704 #define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ 1705 #define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1706 #define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ 1707 #define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ 1708 #define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ 1709 #define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ 1710 #define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1711 #define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ 1712 #define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ 1713 #define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ 1714 #define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ 1715 #define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ 1716 #define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ 1717 #define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1718 #define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ 1719 #define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ 1720 #define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ 1721 #define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ 1722 #define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1723 #define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ 1724 #define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ 1725 #define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ 1726 #define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ 1727 #define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ 1728 #define _WTIMER_CC_CTRL_PRSSEL_MASK 0xF0000UL /**< Bit mask for TIMER_PRSSEL */ 1729 #define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1730 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ 1731 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ 1732 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ 1733 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ 1734 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ 1735 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ 1736 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ 1737 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ 1738 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ 1739 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ 1740 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ 1741 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ 1742 #define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1743 #define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ 1744 #define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ 1745 #define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ 1746 #define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ 1747 #define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ 1748 #define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ 1749 #define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ 1750 #define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ 1751 #define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ 1752 #define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ 1753 #define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ 1754 #define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ 1755 #define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ 1756 #define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ 1757 #define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1758 #define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ 1759 #define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ 1760 #define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ 1761 #define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ 1762 #define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1763 #define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ 1764 #define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ 1765 #define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ 1766 #define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ 1767 #define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ 1768 #define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ 1769 #define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1770 #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ 1771 #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ 1772 #define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ 1773 #define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ 1774 #define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1775 #define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ 1776 #define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ 1777 #define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ 1778 #define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ 1779 #define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ 1780 #define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ 1781 #define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ 1782 #define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1783 #define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ 1784 #define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ 1785 #define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1786 #define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ 1787 #define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ 1788 #define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ 1789 #define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ 1790 #define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ 1791 #define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1792 #define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ 1793 #define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ 1794 #define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1795 #define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ 1796 #define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ 1797 #define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ 1798 #define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ 1799 #define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ 1800 #define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1801 #define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ 1802 #define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ 1803 #define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1804 #define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ 1805 #define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ 1806 1807 /* Bit fields for WTIMER CC_CCV */ 1808 #define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ 1809 #define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ 1810 #define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ 1811 #define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ 1812 #define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ 1813 #define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ 1814 1815 /* Bit fields for WTIMER CC_CCVP */ 1816 #define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ 1817 #define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ 1818 #define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ 1819 #define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ 1820 #define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ 1821 #define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ 1822 1823 /* Bit fields for WTIMER CC_CCVB */ 1824 #define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ 1825 #define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ 1826 #define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ 1827 #define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ 1828 #define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ 1829 #define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ 1830 1831 /* Bit fields for WTIMER DTCTRL */ 1832 #define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ 1833 #define _WTIMER_DTCTRL_MASK 0x010006FFUL /**< Mask for WTIMER_DTCTRL */ 1834 #define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ 1835 #define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ 1836 #define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ 1837 #define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1838 #define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1839 #define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ 1840 #define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ 1841 #define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ 1842 #define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1843 #define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ 1844 #define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ 1845 #define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1846 #define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ 1847 #define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ 1848 #define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ 1849 #define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ 1850 #define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ 1851 #define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1852 #define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1853 #define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ 1854 #define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ 1855 #define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ 1856 #define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1857 #define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1858 #define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ 1859 #define _WTIMER_DTCTRL_DTPRSSEL_MASK 0xF0UL /**< Bit mask for TIMER_DTPRSSEL */ 1860 #define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1861 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ 1862 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ 1863 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ 1864 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ 1865 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ 1866 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ 1867 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ 1868 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ 1869 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ 1870 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ 1871 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ 1872 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ 1873 #define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1874 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ 1875 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ 1876 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ 1877 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ 1878 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ 1879 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ 1880 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ 1881 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ 1882 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ 1883 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ 1884 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ 1885 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ 1886 #define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ 1887 #define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ 1888 #define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ 1889 #define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1890 #define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1891 #define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ 1892 #define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ 1893 #define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ 1894 #define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1895 #define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1896 #define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ 1897 #define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ 1898 #define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ 1899 #define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1900 #define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1901 1902 /* Bit fields for WTIMER DTTIME */ 1903 #define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ 1904 #define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ 1905 #define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ 1906 #define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ 1907 #define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ 1908 #define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ 1909 #define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ 1910 #define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ 1911 #define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ 1912 #define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ 1913 #define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ 1914 #define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ 1915 #define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ 1916 #define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ 1917 #define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ 1918 #define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ 1919 #define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ 1920 #define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ 1921 #define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ 1922 #define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ 1923 #define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ 1924 #define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ 1925 #define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ 1926 #define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ 1927 #define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ 1928 #define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ 1929 #define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ 1930 #define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ 1931 #define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ 1932 #define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ 1933 #define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ 1934 #define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ 1935 #define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ 1936 #define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ 1937 #define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ 1938 #define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ 1939 1940 /* Bit fields for WTIMER DTFC */ 1941 #define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ 1942 #define _WTIMER_DTFC_MASK 0x0F030F0FUL /**< Mask for WTIMER_DTFC */ 1943 #define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ 1944 #define _WTIMER_DTFC_DTPRS0FSEL_MASK 0xFUL /**< Bit mask for TIMER_DTPRS0FSEL */ 1945 #define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 1946 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ 1947 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ 1948 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ 1949 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ 1950 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ 1951 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ 1952 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ 1953 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ 1954 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ 1955 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ 1956 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ 1957 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ 1958 #define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 1959 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ 1960 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ 1961 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ 1962 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ 1963 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ 1964 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ 1965 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ 1966 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ 1967 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ 1968 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ 1969 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ 1970 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ 1971 #define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ 1972 #define _WTIMER_DTFC_DTPRS1FSEL_MASK 0xF00UL /**< Bit mask for TIMER_DTPRS1FSEL */ 1973 #define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 1974 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ 1975 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ 1976 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ 1977 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ 1978 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ 1979 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ 1980 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ 1981 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ 1982 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ 1983 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ 1984 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ 1985 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ 1986 #define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 1987 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ 1988 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ 1989 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ 1990 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ 1991 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ 1992 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ 1993 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ 1994 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ 1995 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ 1996 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ 1997 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ 1998 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ 1999 #define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ 2000 #define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ 2001 #define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 2002 #define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ 2003 #define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ 2004 #define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ 2005 #define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ 2006 #define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 2007 #define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ 2008 #define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ 2009 #define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ 2010 #define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ 2011 #define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ 2012 #define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ 2013 #define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ 2014 #define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 2015 #define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 2016 #define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ 2017 #define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ 2018 #define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ 2019 #define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 2020 #define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 2021 #define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ 2022 #define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ 2023 #define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ 2024 #define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 2025 #define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 2026 #define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ 2027 #define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ 2028 #define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ 2029 #define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 2030 #define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 2031 2032 /* Bit fields for WTIMER DTOGEN */ 2033 #define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ 2034 #define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ 2035 #define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ 2036 #define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ 2037 #define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ 2038 #define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 2039 #define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 2040 #define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ 2041 #define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ 2042 #define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ 2043 #define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 2044 #define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 2045 #define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ 2046 #define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ 2047 #define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ 2048 #define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 2049 #define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 2050 #define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ 2051 #define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ 2052 #define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ 2053 #define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 2054 #define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 2055 #define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ 2056 #define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ 2057 #define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ 2058 #define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 2059 #define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 2060 #define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ 2061 #define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ 2062 #define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ 2063 #define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 2064 #define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 2065 2066 /* Bit fields for WTIMER DTFAULT */ 2067 #define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ 2068 #define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ 2069 #define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ 2070 #define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ 2071 #define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ 2072 #define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ 2073 #define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ 2074 #define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ 2075 #define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ 2076 #define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ 2077 #define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ 2078 #define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ 2079 #define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ 2080 #define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ 2081 #define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ 2082 #define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ 2083 #define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ 2084 #define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ 2085 #define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ 2086 #define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ 2087 #define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ 2088 #define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ 2089 2090 /* Bit fields for WTIMER DTFAULTC */ 2091 #define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ 2092 #define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ 2093 #define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ 2094 #define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ 2095 #define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ 2096 #define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ 2097 #define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ 2098 #define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ 2099 #define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ 2100 #define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ 2101 #define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ 2102 #define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ 2103 #define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ 2104 #define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ 2105 #define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ 2106 #define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ 2107 #define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ 2108 #define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ 2109 #define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ 2110 #define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ 2111 #define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ 2112 #define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ 2113 2114 /* Bit fields for WTIMER DTLOCK */ 2115 #define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ 2116 #define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ 2117 #define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ 2118 #define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ 2119 #define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ 2120 #define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ 2121 #define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ 2122 #define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ 2123 #define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ 2124 #define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ 2125 #define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ 2126 #define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ 2127 #define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ 2128 #define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ 2129 2130 /** @} */ 2131 /** @} End of group EFR32BG13P532F512GM32_WTIMER */ 2132 2133 /***************************************************************************//** 2134 * @addtogroup EFR32BG13P532F512GM32_CMU 2135 * @{ 2136 * @defgroup EFR32BG13P532F512GM32_CMU_BitFields CMU Bit Fields 2137 * @{ 2138 ******************************************************************************/ 2139 2140 /* Bit fields for CMU CTRL */ 2141 #define _CMU_CTRL_RESETVALUE 0x00300000UL /**< Default value for CMU_CTRL */ 2142 #define _CMU_CTRL_MASK 0x001103FFUL /**< Mask for CMU_CTRL */ 2143 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ 2144 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ 2145 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 2146 #define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ 2147 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ 2148 #define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ 2149 #define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ 2150 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ 2151 #define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ 2152 #define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ 2153 #define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ 2154 #define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ 2155 #define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ 2156 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ 2157 #define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ 2158 #define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ 2159 #define _CMU_CTRL_CLKOUTSEL0_PLFRCO 0x00000010UL /**< Mode PLFRCO for CMU_CTRL */ 2160 #define _CMU_CTRL_CLKOUTSEL0_PLFRCOQ 0x00000011UL /**< Mode PLFRCOQ for CMU_CTRL */ 2161 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ 2162 #define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ 2163 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ 2164 #define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ 2165 #define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ 2166 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ 2167 #define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ 2168 #define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ 2169 #define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ 2170 #define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ 2171 #define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ 2172 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ 2173 #define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ 2174 #define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ 2175 #define CMU_CTRL_CLKOUTSEL0_PLFRCO (_CMU_CTRL_CLKOUTSEL0_PLFRCO << 0) /**< Shifted mode PLFRCO for CMU_CTRL */ 2176 #define CMU_CTRL_CLKOUTSEL0_PLFRCOQ (_CMU_CTRL_CLKOUTSEL0_PLFRCOQ << 0) /**< Shifted mode PLFRCOQ for CMU_CTRL */ 2177 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ 2178 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ 2179 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 2180 #define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ 2181 #define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ 2182 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ 2183 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ 2184 #define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ 2185 #define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ 2186 #define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ 2187 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ 2188 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ 2189 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ 2190 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ 2191 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ 2192 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ 2193 #define _CMU_CTRL_CLKOUTSEL1_PLFRCO 0x00000010UL /**< Mode PLFRCO for CMU_CTRL */ 2194 #define _CMU_CTRL_CLKOUTSEL1_PLFRCOQ 0x00000011UL /**< Mode PLFRCOQ for CMU_CTRL */ 2195 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ 2196 #define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ 2197 #define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ 2198 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ 2199 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ 2200 #define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ 2201 #define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ 2202 #define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ 2203 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ 2204 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ 2205 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ 2206 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ 2207 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ 2208 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ 2209 #define CMU_CTRL_CLKOUTSEL1_PLFRCO (_CMU_CTRL_CLKOUTSEL1_PLFRCO << 5) /**< Shifted mode PLFRCO for CMU_CTRL */ 2210 #define CMU_CTRL_CLKOUTSEL1_PLFRCOQ (_CMU_CTRL_CLKOUTSEL1_PLFRCOQ << 5) /**< Shifted mode PLFRCOQ for CMU_CTRL */ 2211 #define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ 2212 #define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ 2213 #define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ 2214 #define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 2215 #define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ 2216 #define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ 2217 #define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ 2218 #define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ 2219 #define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ 2220 #define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ 2221 2222 /* Bit fields for CMU HFRCOCTRL */ 2223 #define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ 2224 #define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ 2225 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 2226 #define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 2227 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 2228 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 2229 #define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ 2230 #define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ 2231 #define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 2232 #define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 2233 #define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ 2234 #define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ 2235 #define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 2236 #define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 2237 #define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ 2238 #define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ 2239 #define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 2240 #define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 2241 #define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ 2242 #define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ 2243 #define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ 2244 #define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 2245 #define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 2246 #define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ 2247 #define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ 2248 #define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 2249 #define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ 2250 #define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ 2251 #define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ 2252 #define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 2253 #define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ 2254 #define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ 2255 #define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ 2256 #define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ 2257 #define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ 2258 #define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ 2259 #define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 2260 #define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 2261 #define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ 2262 #define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ 2263 #define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 2264 #define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 2265 2266 /* Bit fields for CMU AUXHFRCOCTRL */ 2267 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ 2268 #define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ 2269 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 2270 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 2271 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 2272 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 2273 #define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ 2274 #define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ 2275 #define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 2276 #define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 2277 #define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ 2278 #define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ 2279 #define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 2280 #define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 2281 #define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ 2282 #define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ 2283 #define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 2284 #define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 2285 #define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ 2286 #define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ 2287 #define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ 2288 #define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 2289 #define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 2290 #define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ 2291 #define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ 2292 #define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 2293 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ 2294 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ 2295 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ 2296 #define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 2297 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ 2298 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ 2299 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ 2300 #define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ 2301 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ 2302 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ 2303 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 2304 #define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 2305 #define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ 2306 #define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ 2307 #define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 2308 #define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 2309 2310 /* Bit fields for CMU LFRCOCTRL */ 2311 #define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ 2312 #define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ 2313 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 2314 #define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ 2315 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 2316 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 2317 #define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ 2318 #define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ 2319 #define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ 2320 #define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 2321 #define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 2322 #define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ 2323 #define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ 2324 #define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ 2325 #define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 2326 #define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 2327 #define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ 2328 #define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ 2329 #define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ 2330 #define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 2331 #define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 2332 #define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ 2333 #define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ 2334 #define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 2335 #define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ 2336 #define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ 2337 #define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ 2338 #define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ 2339 #define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 2340 #define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ 2341 #define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ 2342 #define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ 2343 #define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ 2344 #define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ 2345 #define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ 2346 #define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ 2347 #define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 2348 #define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ 2349 #define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ 2350 #define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ 2351 #define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 2352 #define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ 2353 #define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ 2354 #define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ 2355 #define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ 2356 #define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 2357 #define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 2358 2359 /* Bit fields for CMU HFXOCTRL */ 2360 #define _CMU_HFXOCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOCTRL */ 2361 #define _CMU_HFXOCTRL_MASK 0x37000731UL /**< Mask for CMU_HFXOCTRL */ 2362 #define CMU_HFXOCTRL_MODE (0x1UL << 0) /**< HFXO Mode */ 2363 #define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ 2364 #define _CMU_HFXOCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ 2365 #define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 2366 #define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ 2367 #define _CMU_HFXOCTRL_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for CMU_HFXOCTRL */ 2368 #define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 2369 #define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ 2370 #define CMU_HFXOCTRL_MODE_EXTCLK (_CMU_HFXOCTRL_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for CMU_HFXOCTRL */ 2371 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETSHUNTOPTMODE */ 2372 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETSHUNTOPTMODE */ 2373 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 2374 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD 0x00000000UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ 2375 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD 0x00000001UL /**< Mode CMD for CMU_HFXOCTRL */ 2376 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL 0x00000002UL /**< Mode MANUAL for CMU_HFXOCTRL */ 2377 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 2378 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ 2379 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ 2380 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ 2381 #define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8) /**< Low Power Mode Control */ 2382 #define _CMU_HFXOCTRL_LOWPOWER_SHIFT 8 /**< Shift value for CMU_LOWPOWER */ 2383 #define _CMU_HFXOCTRL_LOWPOWER_MASK 0x100UL /**< Bit mask for CMU_LOWPOWER */ 2384 #define _CMU_HFXOCTRL_LOWPOWER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 2385 #define CMU_HFXOCTRL_LOWPOWER_DEFAULT (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 2386 #define CMU_HFXOCTRL_XTI2GND (0x1UL << 9) /**< Clamp HFXTAL_N Pin to Ground When HFXO Oscillator is Off */ 2387 #define _CMU_HFXOCTRL_XTI2GND_SHIFT 9 /**< Shift value for CMU_XTI2GND */ 2388 #define _CMU_HFXOCTRL_XTI2GND_MASK 0x200UL /**< Bit mask for CMU_XTI2GND */ 2389 #define _CMU_HFXOCTRL_XTI2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 2390 #define CMU_HFXOCTRL_XTI2GND_DEFAULT (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 2391 #define CMU_HFXOCTRL_XTO2GND (0x1UL << 10) /**< Clamp HFXTAL_P Pin to Ground When HFXO Oscillator is Off */ 2392 #define _CMU_HFXOCTRL_XTO2GND_SHIFT 10 /**< Shift value for CMU_XTO2GND */ 2393 #define _CMU_HFXOCTRL_XTO2GND_MASK 0x400UL /**< Bit mask for CMU_XTO2GND */ 2394 #define _CMU_HFXOCTRL_XTO2GND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 2395 #define CMU_HFXOCTRL_XTO2GND_DEFAULT (_CMU_HFXOCTRL_XTO2GND_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 2396 #define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ 2397 #define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ 2398 #define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 2399 #define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ 2400 #define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ 2401 #define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ 2402 #define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ 2403 #define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ 2404 #define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ 2405 #define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ 2406 #define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ 2407 #define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 2408 #define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ 2409 #define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ 2410 #define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ 2411 #define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ 2412 #define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ 2413 #define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ 2414 #define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ 2415 #define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ 2416 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ 2417 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ 2418 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ 2419 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 2420 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 2421 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ 2422 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ 2423 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ 2424 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 2425 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 2426 2427 /* Bit fields for CMU HFXOSTARTUPCTRL */ 2428 #define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00050020UL /**< Default value for CMU_HFXOSTARTUPCTRL */ 2429 #define _CMU_HFXOSTARTUPCTRL_MASK 0x000FF87FUL /**< Mask for CMU_HFXOSTARTUPCTRL */ 2430 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ 2431 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ 2432 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 2433 #define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 2434 #define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ 2435 #define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ 2436 #define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x000000A0UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 2437 #define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 2438 2439 /* Bit fields for CMU HFXOSTEADYSTATECTRL */ 2440 #define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0xA30B4507UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ 2441 #define _CMU_HFXOSTEADYSTATECTRL_MASK 0xF70FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ 2442 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ 2443 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ 2444 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 2445 #define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 2446 #define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */ 2447 #define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */ 2448 #define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 2449 #define CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 2450 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ 2451 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ 2452 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000168UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 2453 #define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 2454 #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT 24 /**< Shift value for CMU_REGSELILOW */ 2455 #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK 0x3000000UL /**< Bit mask for CMU_REGSELILOW */ 2456 #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 2457 #define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 2458 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ 2459 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ 2460 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ 2461 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 2462 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 2463 #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT 28 /**< Shift value for CMU_REGISHUPPER */ 2464 #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK 0xF0000000UL /**< Bit mask for CMU_REGISHUPPER */ 2465 #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 2466 #define CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 2467 2468 /* Bit fields for CMU HFXOTIMEOUTCTRL */ 2469 #define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0002A067UL /**< Default value for CMU_HFXOTIMEOUTCTRL */ 2470 #define _CMU_HFXOTIMEOUTCTRL_MASK 0x000FF0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ 2471 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ 2472 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ 2473 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 2474 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 2475 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 2476 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 2477 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 2478 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2479 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2480 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 2481 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2482 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2483 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2484 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2485 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 2486 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 2487 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 2488 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 2489 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 2490 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2491 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2492 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 2493 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2494 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2495 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2496 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2497 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ 2498 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ 2499 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 2500 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 2501 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 2502 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 2503 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 2504 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2505 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000006UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 2506 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2507 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2508 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2509 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2510 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2511 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 2512 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 2513 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 2514 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 2515 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 2516 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2517 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 2518 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2519 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2520 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2521 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2522 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2523 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ 2524 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ 2525 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 2526 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 2527 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 2528 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 2529 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 2530 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2531 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2532 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2533 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2534 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2535 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 2536 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2537 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 2538 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 2539 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 2540 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 2541 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 2542 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2543 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2544 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2545 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2546 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2547 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 2548 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2549 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT 16 /**< Shift value for CMU_SHUNTOPTTIMEOUT */ 2550 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK 0xF0000UL /**< Bit mask for CMU_SHUNTOPTTIMEOUT */ 2551 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 2552 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 2553 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 2554 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 2555 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 2556 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES 0x00000004UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 2557 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES 0x00000005UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2558 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES 0x00000006UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2559 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2560 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES 0x00000008UL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2561 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES 0x00000009UL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2562 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES 0x0000000AUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2563 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES << 16) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 2564 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES << 16) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 2565 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 2566 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES << 16) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 2567 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES << 16) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 2568 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES << 16) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 2569 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES << 16) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2570 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES << 16) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2571 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES << 16) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2572 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES << 16) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2573 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES << 16) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2574 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES << 16) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 2575 2576 /* Bit fields for CMU LFXOCTRL */ 2577 #define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ 2578 #define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ 2579 #define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 2580 #define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 2581 #define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 2582 #define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 2583 #define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ 2584 #define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ 2585 #define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 2586 #define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ 2587 #define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ 2588 #define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ 2589 #define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 2590 #define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ 2591 #define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ 2592 #define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ 2593 #define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ 2594 #define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ 2595 #define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 2596 #define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 2597 #define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ 2598 #define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ 2599 #define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ 2600 #define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 2601 #define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 2602 #define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ 2603 #define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ 2604 #define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ 2605 #define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 2606 #define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 2607 #define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ 2608 #define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ 2609 #define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 2610 #define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 2611 #define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ 2612 #define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ 2613 #define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ 2614 #define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 2615 #define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 2616 #define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ 2617 #define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ 2618 #define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ 2619 #define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ 2620 #define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ 2621 #define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ 2622 #define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ 2623 #define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ 2624 #define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ 2625 #define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 2626 #define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ 2627 #define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ 2628 #define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ 2629 #define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ 2630 #define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ 2631 #define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ 2632 #define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ 2633 #define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ 2634 #define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 2635 #define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ 2636 2637 /* Bit fields for CMU DPLLCTRL */ 2638 #define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ 2639 #define _CMU_DPLLCTRL_MASK 0x0000001FUL /**< Mask for CMU_DPLLCTRL */ 2640 #define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ 2641 #define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ 2642 #define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ 2643 #define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 2644 #define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ 2645 #define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ 2646 #define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 2647 #define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ 2648 #define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ 2649 #define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ 2650 #define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ 2651 #define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ 2652 #define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 2653 #define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ 2654 #define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ 2655 #define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 2656 #define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ 2657 #define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ 2658 #define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ 2659 #define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ 2660 #define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ 2661 #define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 2662 #define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 2663 #define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ 2664 #define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ 2665 #define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 2666 #define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ 2667 #define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ 2668 #define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ 2669 #define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 2670 #define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ 2671 #define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ 2672 #define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ 2673 2674 /* Bit fields for CMU DPLLCTRL1 */ 2675 #define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ 2676 #define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ 2677 #define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ 2678 #define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ 2679 #define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ 2680 #define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ 2681 #define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ 2682 #define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ 2683 #define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ 2684 #define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ 2685 2686 /* Bit fields for CMU CALCTRL */ 2687 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ 2688 #define _CMU_CALCTRL_MASK 0x0F0F01FFUL /**< Mask for CMU_CALCTRL */ 2689 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ 2690 #define _CMU_CALCTRL_UPSEL_MASK 0xFUL /**< Bit mask for CMU_UPSEL */ 2691 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 2692 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ 2693 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ 2694 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ 2695 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ 2696 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ 2697 #define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ 2698 #define _CMU_CALCTRL_UPSEL_PLFRCO 0x00000008UL /**< Mode PLFRCO for CMU_CALCTRL */ 2699 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 2700 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ 2701 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ 2702 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ 2703 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ 2704 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ 2705 #define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ 2706 #define CMU_CALCTRL_UPSEL_PLFRCO (_CMU_CALCTRL_UPSEL_PLFRCO << 0) /**< Shifted mode PLFRCO for CMU_CALCTRL */ 2707 #define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ 2708 #define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ 2709 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 2710 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ 2711 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ 2712 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ 2713 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ 2714 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ 2715 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ 2716 #define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ 2717 #define _CMU_CALCTRL_DOWNSEL_PLFRCO 0x00000009UL /**< Mode PLFRCO for CMU_CALCTRL */ 2718 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 2719 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ 2720 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ 2721 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ 2722 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ 2723 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ 2724 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ 2725 #define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ 2726 #define CMU_CALCTRL_DOWNSEL_PLFRCO (_CMU_CALCTRL_DOWNSEL_PLFRCO << 4) /**< Shifted mode PLFRCO for CMU_CALCTRL */ 2727 #define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ 2728 #define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ 2729 #define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ 2730 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 2731 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 2732 #define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ 2733 #define _CMU_CALCTRL_PRSUPSEL_MASK 0xF0000UL /**< Bit mask for CMU_PRSUPSEL */ 2734 #define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 2735 #define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ 2736 #define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ 2737 #define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ 2738 #define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ 2739 #define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ 2740 #define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ 2741 #define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ 2742 #define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ 2743 #define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ 2744 #define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ 2745 #define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ 2746 #define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ 2747 #define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 2748 #define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ 2749 #define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ 2750 #define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ 2751 #define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ 2752 #define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ 2753 #define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ 2754 #define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ 2755 #define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ 2756 #define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ 2757 #define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ 2758 #define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ 2759 #define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ 2760 #define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ 2761 #define _CMU_CALCTRL_PRSDOWNSEL_MASK 0xF000000UL /**< Bit mask for CMU_PRSDOWNSEL */ 2762 #define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 2763 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ 2764 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ 2765 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ 2766 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ 2767 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ 2768 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ 2769 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ 2770 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ 2771 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ 2772 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ 2773 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ 2774 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ 2775 #define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 2776 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ 2777 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ 2778 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ 2779 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ 2780 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ 2781 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ 2782 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ 2783 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ 2784 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ 2785 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ 2786 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ 2787 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ 2788 2789 /* Bit fields for CMU CALCNT */ 2790 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ 2791 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ 2792 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ 2793 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ 2794 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ 2795 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ 2796 2797 /* Bit fields for CMU OSCENCMD */ 2798 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ 2799 #define _CMU_OSCENCMD_MASK 0x0000F3FFUL /**< Mask for CMU_OSCENCMD */ 2800 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ 2801 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ 2802 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ 2803 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 2804 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 2805 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ 2806 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ 2807 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ 2808 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 2809 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 2810 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ 2811 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ 2812 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ 2813 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 2814 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 2815 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ 2816 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ 2817 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ 2818 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 2819 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 2820 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ 2821 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ 2822 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ 2823 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 2824 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 2825 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ 2826 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ 2827 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ 2828 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 2829 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 2830 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ 2831 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ 2832 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ 2833 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 2834 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 2835 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ 2836 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ 2837 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ 2838 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 2839 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 2840 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ 2841 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ 2842 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ 2843 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 2844 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 2845 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ 2846 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ 2847 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ 2848 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 2849 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 2850 #define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ 2851 #define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ 2852 #define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ 2853 #define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 2854 #define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 2855 #define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ 2856 #define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ 2857 #define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ 2858 #define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 2859 #define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 2860 #define CMU_OSCENCMD_PLFRCOEN (0x1UL << 14) /**< PLFRCO Enable */ 2861 #define _CMU_OSCENCMD_PLFRCOEN_SHIFT 14 /**< Shift value for CMU_PLFRCOEN */ 2862 #define _CMU_OSCENCMD_PLFRCOEN_MASK 0x4000UL /**< Bit mask for CMU_PLFRCOEN */ 2863 #define _CMU_OSCENCMD_PLFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 2864 #define CMU_OSCENCMD_PLFRCOEN_DEFAULT (_CMU_OSCENCMD_PLFRCOEN_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 2865 #define CMU_OSCENCMD_PLFRCODIS (0x1UL << 15) /**< PLFRCO Disable */ 2866 #define _CMU_OSCENCMD_PLFRCODIS_SHIFT 15 /**< Shift value for CMU_PLFRCODIS */ 2867 #define _CMU_OSCENCMD_PLFRCODIS_MASK 0x8000UL /**< Bit mask for CMU_PLFRCODIS */ 2868 #define _CMU_OSCENCMD_PLFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 2869 #define CMU_OSCENCMD_PLFRCODIS_DEFAULT (_CMU_OSCENCMD_PLFRCODIS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 2870 2871 /* Bit fields for CMU CMD */ 2872 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ 2873 #define _CMU_CMD_MASK 0x00000033UL /**< Mask for CMU_CMD */ 2874 #define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ 2875 #define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ 2876 #define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ 2877 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 2878 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ 2879 #define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ 2880 #define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ 2881 #define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ 2882 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 2883 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ 2884 #define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ 2885 #define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ 2886 #define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ 2887 #define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 2888 #define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ 2889 #define CMU_CMD_HFXOSHUNTOPTSTART (0x1UL << 5) /**< HFXO Shunt Current Optimization Start */ 2890 #define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT 5 /**< Shift value for CMU_HFXOSHUNTOPTSTART */ 2891 #define _CMU_CMD_HFXOSHUNTOPTSTART_MASK 0x20UL /**< Bit mask for CMU_HFXOSHUNTOPTSTART */ 2892 #define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 2893 #define CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT (_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */ 2894 2895 /* Bit fields for CMU DBGCLKSEL */ 2896 #define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ 2897 #define _CMU_DBGCLKSEL_MASK 0x00000001UL /**< Mask for CMU_DBGCLKSEL */ 2898 #define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ 2899 #define _CMU_DBGCLKSEL_DBG_MASK 0x1UL /**< Bit mask for CMU_DBG */ 2900 #define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ 2901 #define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ 2902 #define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ 2903 #define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ 2904 #define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ 2905 #define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ 2906 2907 /* Bit fields for CMU HFCLKSEL */ 2908 #define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ 2909 #define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ 2910 #define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ 2911 #define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ 2912 #define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ 2913 #define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ 2914 #define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ 2915 #define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ 2916 #define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ 2917 #define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ 2918 #define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ 2919 #define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ 2920 #define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ 2921 #define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ 2922 #define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ 2923 #define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ 2924 #define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ 2925 #define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ 2926 2927 /* Bit fields for CMU LFACLKSEL */ 2928 #define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ 2929 #define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ 2930 #define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ 2931 #define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ 2932 #define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ 2933 #define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ 2934 #define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ 2935 #define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ 2936 #define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ 2937 #define _CMU_LFACLKSEL_LFA_PLFRCO 0x00000005UL /**< Mode PLFRCO for CMU_LFACLKSEL */ 2938 #define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ 2939 #define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ 2940 #define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ 2941 #define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ 2942 #define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ 2943 #define CMU_LFACLKSEL_LFA_PLFRCO (_CMU_LFACLKSEL_LFA_PLFRCO << 0) /**< Shifted mode PLFRCO for CMU_LFACLKSEL */ 2944 2945 /* Bit fields for CMU LFBCLKSEL */ 2946 #define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ 2947 #define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ 2948 #define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ 2949 #define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ 2950 #define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ 2951 #define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ 2952 #define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ 2953 #define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ 2954 #define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ 2955 #define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ 2956 #define _CMU_LFBCLKSEL_LFB_PLFRCO 0x00000005UL /**< Mode PLFRCO for CMU_LFBCLKSEL */ 2957 #define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ 2958 #define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ 2959 #define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ 2960 #define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ 2961 #define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ 2962 #define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ 2963 #define CMU_LFBCLKSEL_LFB_PLFRCO (_CMU_LFBCLKSEL_LFB_PLFRCO << 0) /**< Shifted mode PLFRCO for CMU_LFBCLKSEL */ 2964 2965 /* Bit fields for CMU LFECLKSEL */ 2966 #define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ 2967 #define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ 2968 #define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ 2969 #define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ 2970 #define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ 2971 #define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ 2972 #define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ 2973 #define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ 2974 #define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ 2975 #define _CMU_LFECLKSEL_LFE_PLFRCO 0x00000005UL /**< Mode PLFRCO for CMU_LFECLKSEL */ 2976 #define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ 2977 #define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ 2978 #define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ 2979 #define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ 2980 #define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ 2981 #define CMU_LFECLKSEL_LFE_PLFRCO (_CMU_LFECLKSEL_LFE_PLFRCO << 0) /**< Shifted mode PLFRCO for CMU_LFECLKSEL */ 2982 2983 /* Bit fields for CMU STATUS */ 2984 #define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ 2985 #define _CMU_STATUS_MASK 0x7FE1F3FFUL /**< Mask for CMU_STATUS */ 2986 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ 2987 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ 2988 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ 2989 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 2990 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ 2991 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ 2992 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ 2993 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ 2994 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 2995 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ 2996 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ 2997 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ 2998 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ 2999 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3000 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ 3001 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ 3002 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ 3003 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ 3004 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3005 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ 3006 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ 3007 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ 3008 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ 3009 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3010 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ 3011 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ 3012 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ 3013 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ 3014 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3015 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ 3016 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ 3017 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ 3018 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ 3019 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3020 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ 3021 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ 3022 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ 3023 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ 3024 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3025 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ 3026 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ 3027 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ 3028 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ 3029 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3030 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ 3031 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ 3032 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ 3033 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ 3034 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3035 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ 3036 #define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ 3037 #define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ 3038 #define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ 3039 #define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3040 #define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ 3041 #define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ 3042 #define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ 3043 #define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ 3044 #define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3045 #define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ 3046 #define CMU_STATUS_PLFRCOENS (0x1UL << 14) /**< PLFRCO Enable Status */ 3047 #define _CMU_STATUS_PLFRCOENS_SHIFT 14 /**< Shift value for CMU_PLFRCOENS */ 3048 #define _CMU_STATUS_PLFRCOENS_MASK 0x4000UL /**< Bit mask for CMU_PLFRCOENS */ 3049 #define _CMU_STATUS_PLFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3050 #define CMU_STATUS_PLFRCOENS_DEFAULT (_CMU_STATUS_PLFRCOENS_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */ 3051 #define CMU_STATUS_PLFRCORDY (0x1UL << 15) /**< PLFRCO Ready */ 3052 #define _CMU_STATUS_PLFRCORDY_SHIFT 15 /**< Shift value for CMU_PLFRCORDY */ 3053 #define _CMU_STATUS_PLFRCORDY_MASK 0x8000UL /**< Bit mask for CMU_PLFRCORDY */ 3054 #define _CMU_STATUS_PLFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3055 #define CMU_STATUS_PLFRCORDY_DEFAULT (_CMU_STATUS_PLFRCORDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */ 3056 #define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ 3057 #define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ 3058 #define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ 3059 #define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 3060 #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ 3061 #define CMU_STATUS_HFXOREQ (0x1UL << 21) /**< HFXO is Required By Hardware */ 3062 #define _CMU_STATUS_HFXOREQ_SHIFT 21 /**< Shift value for CMU_HFXOREQ */ 3063 #define _CMU_STATUS_HFXOREQ_MASK 0x200000UL /**< Bit mask for CMU_HFXOREQ */ 3064 #define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3065 #define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */ 3066 #define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ 3067 #define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ 3068 #define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 3069 #define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3070 #define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ 3071 #define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23) /**< HFXO Shunt Current Optimization Ready */ 3072 #define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT 23 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ 3073 #define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK 0x800000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ 3074 #define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3075 #define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */ 3076 #define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24) /**< HFXO Oscillation Amplitude is Too High */ 3077 #define _CMU_STATUS_HFXOAMPHIGH_SHIFT 24 /**< Shift value for CMU_HFXOAMPHIGH */ 3078 #define _CMU_STATUS_HFXOAMPHIGH_MASK 0x1000000UL /**< Bit mask for CMU_HFXOAMPHIGH */ 3079 #define _CMU_STATUS_HFXOAMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3080 #define CMU_STATUS_HFXOAMPHIGH_DEFAULT (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_STATUS */ 3081 #define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ 3082 #define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ 3083 #define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ 3084 #define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3085 #define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ 3086 #define CMU_STATUS_HFXOREGILOW (0x1UL << 26) /**< HFXO Regulator Shunt Current Too Low */ 3087 #define _CMU_STATUS_HFXOREGILOW_SHIFT 26 /**< Shift value for CMU_HFXOREGILOW */ 3088 #define _CMU_STATUS_HFXOREGILOW_MASK 0x4000000UL /**< Bit mask for CMU_HFXOREGILOW */ 3089 #define _CMU_STATUS_HFXOREGILOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3090 #define CMU_STATUS_HFXOREGILOW_DEFAULT (_CMU_STATUS_HFXOREGILOW_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_STATUS */ 3091 #define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ 3092 #define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ 3093 #define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ 3094 #define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3095 #define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ 3096 #define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ 3097 #define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ 3098 #define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ 3099 #define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3100 #define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ 3101 #define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ 3102 #define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ 3103 #define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ 3104 #define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3105 #define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ 3106 #define CMU_STATUS_PLFRCOPHASE (0x1UL << 30) /**< PLFRCO Clock Phase */ 3107 #define _CMU_STATUS_PLFRCOPHASE_SHIFT 30 /**< Shift value for CMU_PLFRCOPHASE */ 3108 #define _CMU_STATUS_PLFRCOPHASE_MASK 0x40000000UL /**< Bit mask for CMU_PLFRCOPHASE */ 3109 #define _CMU_STATUS_PLFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 3110 #define CMU_STATUS_PLFRCOPHASE_DEFAULT (_CMU_STATUS_PLFRCOPHASE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ 3111 3112 /* Bit fields for CMU HFCLKSTATUS */ 3113 #define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ 3114 #define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ 3115 #define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ 3116 #define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ 3117 #define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ 3118 #define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ 3119 #define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ 3120 #define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ 3121 #define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ 3122 #define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ 3123 #define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ 3124 #define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ 3125 #define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ 3126 #define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ 3127 #define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ 3128 #define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ 3129 #define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ 3130 #define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ 3131 3132 /* Bit fields for CMU HFXOTRIMSTATUS */ 3133 #define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000500UL /**< Default value for CMU_HFXOTRIMSTATUS */ 3134 #define _CMU_HFXOTRIMSTATUS_MASK 0x000007FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ 3135 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ 3136 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FUL /**< Bit mask for CMU_IBTRIMXOCORE */ 3137 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ 3138 #define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ 3139 #define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT 7 /**< Shift value for CMU_REGISH */ 3140 #define _CMU_HFXOTRIMSTATUS_REGISH_MASK 0x780UL /**< Bit mask for CMU_REGISH */ 3141 #define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT 0x0000000AUL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ 3142 #define CMU_HFXOTRIMSTATUS_REGISH_DEFAULT (_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ 3143 3144 /* Bit fields for CMU IF */ 3145 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ 3146 #define _CMU_IF_MASK 0xF87FFF7FUL /**< Mask for CMU_IF */ 3147 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ 3148 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 3149 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 3150 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ 3151 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ 3152 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ 3153 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 3154 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 3155 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3156 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ 3157 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ 3158 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 3159 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 3160 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3161 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ 3162 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ 3163 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 3164 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 3165 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3166 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ 3167 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ 3168 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 3169 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 3170 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3171 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ 3172 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ 3173 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 3174 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 3175 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3176 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ 3177 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ 3178 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 3179 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 3180 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3181 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ 3182 #define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ 3183 #define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 3184 #define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 3185 #define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3186 #define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ 3187 #define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ 3188 #define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 3189 #define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 3190 #define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3191 #define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ 3192 #define CMU_IF_HFXOPEAKDETERR (0x1UL << 10) /**< HFXO Automatic Peak Detection Error Interrupt Flag */ 3193 #define _CMU_IF_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ 3194 #define _CMU_IF_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ 3195 #define _CMU_IF_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3196 #define CMU_IF_HFXOPEAKDETERR_DEFAULT (_CMU_IF_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IF */ 3197 #define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ 3198 #define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 3199 #define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 3200 #define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3201 #define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ 3202 #define CMU_IF_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXO Automatic Shunt Current Optimization Ready Interrupt Flag */ 3203 #define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ 3204 #define _CMU_IF_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ 3205 #define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3206 #define CMU_IF_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IF */ 3207 #define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ 3208 #define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 3209 #define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 3210 #define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3211 #define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ 3212 #define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ 3213 #define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 3214 #define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 3215 #define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3216 #define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ 3217 #define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ 3218 #define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 3219 #define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 3220 #define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3221 #define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ 3222 #define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ 3223 #define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 3224 #define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 3225 #define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3226 #define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ 3227 #define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ 3228 #define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 3229 #define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 3230 #define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3231 #define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ 3232 #define CMU_IF_PLFRCOCALDONE (0x1UL << 18) /**< Calibration Interrupt Flag */ 3233 #define _CMU_IF_PLFRCOCALDONE_SHIFT 18 /**< Shift value for CMU_PLFRCOCALDONE */ 3234 #define _CMU_IF_PLFRCOCALDONE_MASK 0x40000UL /**< Bit mask for CMU_PLFRCOCALDONE */ 3235 #define _CMU_IF_PLFRCOCALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3236 #define CMU_IF_PLFRCOCALDONE_DEFAULT (_CMU_IF_PLFRCOCALDONE_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_IF */ 3237 #define CMU_IF_PLFRCORDY (0x1UL << 19) /**< PLFRCO Ready Interrupt Flag */ 3238 #define _CMU_IF_PLFRCORDY_SHIFT 19 /**< Shift value for CMU_PLFRCORDY */ 3239 #define _CMU_IF_PLFRCORDY_MASK 0x80000UL /**< Bit mask for CMU_PLFRCORDY */ 3240 #define _CMU_IF_PLFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3241 #define CMU_IF_PLFRCORDY_DEFAULT (_CMU_IF_PLFRCORDY_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_IF */ 3242 #define CMU_IF_PLFRCOHFXODNSERR (0x1UL << 20) /**< Error Due to HFXO Not Starting Interrupt Flag */ 3243 #define _CMU_IF_PLFRCOHFXODNSERR_SHIFT 20 /**< Shift value for CMU_PLFRCOHFXODNSERR */ 3244 #define _CMU_IF_PLFRCOHFXODNSERR_MASK 0x100000UL /**< Bit mask for CMU_PLFRCOHFXODNSERR */ 3245 #define _CMU_IF_PLFRCOHFXODNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3246 #define CMU_IF_PLFRCOHFXODNSERR_DEFAULT (_CMU_IF_PLFRCOHFXODNSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_IF */ 3247 #define CMU_IF_PLFRCOTEMPCHKDONE (0x1UL << 21) /**< Temperature Check Done Interrupt Flag */ 3248 #define _CMU_IF_PLFRCOTEMPCHKDONE_SHIFT 21 /**< Shift value for CMU_PLFRCOTEMPCHKDONE */ 3249 #define _CMU_IF_PLFRCOTEMPCHKDONE_MASK 0x200000UL /**< Bit mask for CMU_PLFRCOTEMPCHKDONE */ 3250 #define _CMU_IF_PLFRCOTEMPCHKDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3251 #define CMU_IF_PLFRCOTEMPCHKDONE_DEFAULT (_CMU_IF_PLFRCOTEMPCHKDONE_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_IF */ 3252 #define CMU_IF_PLFRCOTIMERDONE (0x1UL << 22) /**< Timer Done Interrupt Flag */ 3253 #define _CMU_IF_PLFRCOTIMERDONE_SHIFT 22 /**< Shift value for CMU_PLFRCOTIMERDONE */ 3254 #define _CMU_IF_PLFRCOTIMERDONE_MASK 0x400000UL /**< Bit mask for CMU_PLFRCOTIMERDONE */ 3255 #define _CMU_IF_PLFRCOTIMERDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3256 #define CMU_IF_PLFRCOTIMERDONE_DEFAULT (_CMU_IF_PLFRCOTIMERDONE_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_IF */ 3257 #define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ 3258 #define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 3259 #define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 3260 #define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3261 #define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ 3262 #define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ 3263 #define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 3264 #define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 3265 #define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3266 #define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ 3267 #define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ 3268 #define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 3269 #define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 3270 #define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3271 #define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ 3272 #define CMU_IF_PLFRCOEDGE (0x1UL << 30) /**< PLFRCO Clock Edge Detected Interrupt Flag */ 3273 #define _CMU_IF_PLFRCOEDGE_SHIFT 30 /**< Shift value for CMU_PLFRCOEDGE */ 3274 #define _CMU_IF_PLFRCOEDGE_MASK 0x40000000UL /**< Bit mask for CMU_PLFRCOEDGE */ 3275 #define _CMU_IF_PLFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3276 #define CMU_IF_PLFRCOEDGE_DEFAULT (_CMU_IF_PLFRCOEDGE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_IF */ 3277 #define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ 3278 #define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 3279 #define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 3280 #define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 3281 #define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ 3282 3283 /* Bit fields for CMU IFS */ 3284 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ 3285 #define _CMU_IFS_MASK 0xF87FFF7FUL /**< Mask for CMU_IFS */ 3286 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ 3287 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 3288 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 3289 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3290 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ 3291 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ 3292 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 3293 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 3294 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3295 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ 3296 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ 3297 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 3298 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 3299 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3300 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ 3301 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ 3302 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 3303 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 3304 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3305 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ 3306 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ 3307 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 3308 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 3309 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3310 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ 3311 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ 3312 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 3313 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 3314 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3315 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ 3316 #define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ 3317 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 3318 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 3319 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3320 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ 3321 #define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ 3322 #define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 3323 #define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 3324 #define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3325 #define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ 3326 #define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ 3327 #define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 3328 #define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 3329 #define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3330 #define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ 3331 #define CMU_IFS_HFXOPEAKDETERR (0x1UL << 10) /**< Set HFXOPEAKDETERR Interrupt Flag */ 3332 #define _CMU_IFS_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ 3333 #define _CMU_IFS_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ 3334 #define _CMU_IFS_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3335 #define CMU_IFS_HFXOPEAKDETERR_DEFAULT (_CMU_IFS_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFS */ 3336 #define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ 3337 #define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 3338 #define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 3339 #define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3340 #define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ 3341 #define CMU_IFS_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Set HFXOSHUNTOPTRDY Interrupt Flag */ 3342 #define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ 3343 #define _CMU_IFS_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ 3344 #define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3345 #define CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFS */ 3346 #define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ 3347 #define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 3348 #define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 3349 #define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3350 #define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ 3351 #define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ 3352 #define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 3353 #define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 3354 #define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3355 #define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ 3356 #define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ 3357 #define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 3358 #define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 3359 #define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3360 #define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ 3361 #define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ 3362 #define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 3363 #define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 3364 #define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3365 #define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ 3366 #define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ 3367 #define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 3368 #define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 3369 #define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3370 #define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ 3371 #define CMU_IFS_PLFRCOCALDONE (0x1UL << 18) /**< Set PLFRCOCALDONE Interrupt Flag */ 3372 #define _CMU_IFS_PLFRCOCALDONE_SHIFT 18 /**< Shift value for CMU_PLFRCOCALDONE */ 3373 #define _CMU_IFS_PLFRCOCALDONE_MASK 0x40000UL /**< Bit mask for CMU_PLFRCOCALDONE */ 3374 #define _CMU_IFS_PLFRCOCALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3375 #define CMU_IFS_PLFRCOCALDONE_DEFAULT (_CMU_IFS_PLFRCOCALDONE_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_IFS */ 3376 #define CMU_IFS_PLFRCORDY (0x1UL << 19) /**< Set PLFRCORDY Interrupt Flag */ 3377 #define _CMU_IFS_PLFRCORDY_SHIFT 19 /**< Shift value for CMU_PLFRCORDY */ 3378 #define _CMU_IFS_PLFRCORDY_MASK 0x80000UL /**< Bit mask for CMU_PLFRCORDY */ 3379 #define _CMU_IFS_PLFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3380 #define CMU_IFS_PLFRCORDY_DEFAULT (_CMU_IFS_PLFRCORDY_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_IFS */ 3381 #define CMU_IFS_PLFRCOHFXODNSERR (0x1UL << 20) /**< Set PLFRCOHFXODNSERR Interrupt Flag */ 3382 #define _CMU_IFS_PLFRCOHFXODNSERR_SHIFT 20 /**< Shift value for CMU_PLFRCOHFXODNSERR */ 3383 #define _CMU_IFS_PLFRCOHFXODNSERR_MASK 0x100000UL /**< Bit mask for CMU_PLFRCOHFXODNSERR */ 3384 #define _CMU_IFS_PLFRCOHFXODNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3385 #define CMU_IFS_PLFRCOHFXODNSERR_DEFAULT (_CMU_IFS_PLFRCOHFXODNSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_IFS */ 3386 #define CMU_IFS_PLFRCOTEMPCHKDONE (0x1UL << 21) /**< Set PLFRCOTEMPCHKDONE Interrupt Flag */ 3387 #define _CMU_IFS_PLFRCOTEMPCHKDONE_SHIFT 21 /**< Shift value for CMU_PLFRCOTEMPCHKDONE */ 3388 #define _CMU_IFS_PLFRCOTEMPCHKDONE_MASK 0x200000UL /**< Bit mask for CMU_PLFRCOTEMPCHKDONE */ 3389 #define _CMU_IFS_PLFRCOTEMPCHKDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3390 #define CMU_IFS_PLFRCOTEMPCHKDONE_DEFAULT (_CMU_IFS_PLFRCOTEMPCHKDONE_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_IFS */ 3391 #define CMU_IFS_PLFRCOTIMERDONE (0x1UL << 22) /**< Set PLFRCOTIMERDONE Interrupt Flag */ 3392 #define _CMU_IFS_PLFRCOTIMERDONE_SHIFT 22 /**< Shift value for CMU_PLFRCOTIMERDONE */ 3393 #define _CMU_IFS_PLFRCOTIMERDONE_MASK 0x400000UL /**< Bit mask for CMU_PLFRCOTIMERDONE */ 3394 #define _CMU_IFS_PLFRCOTIMERDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3395 #define CMU_IFS_PLFRCOTIMERDONE_DEFAULT (_CMU_IFS_PLFRCOTIMERDONE_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_IFS */ 3396 #define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ 3397 #define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 3398 #define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 3399 #define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3400 #define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ 3401 #define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ 3402 #define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 3403 #define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 3404 #define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3405 #define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ 3406 #define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ 3407 #define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 3408 #define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 3409 #define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3410 #define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ 3411 #define CMU_IFS_PLFRCOEDGE (0x1UL << 30) /**< Set PLFRCOEDGE Interrupt Flag */ 3412 #define _CMU_IFS_PLFRCOEDGE_SHIFT 30 /**< Shift value for CMU_PLFRCOEDGE */ 3413 #define _CMU_IFS_PLFRCOEDGE_MASK 0x40000000UL /**< Bit mask for CMU_PLFRCOEDGE */ 3414 #define _CMU_IFS_PLFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3415 #define CMU_IFS_PLFRCOEDGE_DEFAULT (_CMU_IFS_PLFRCOEDGE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_IFS */ 3416 #define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ 3417 #define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 3418 #define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 3419 #define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 3420 #define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ 3421 3422 /* Bit fields for CMU IFC */ 3423 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ 3424 #define _CMU_IFC_MASK 0xF87FFF7FUL /**< Mask for CMU_IFC */ 3425 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ 3426 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 3427 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 3428 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3429 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ 3430 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ 3431 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 3432 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 3433 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3434 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ 3435 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ 3436 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 3437 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 3438 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3439 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ 3440 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ 3441 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 3442 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 3443 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3444 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ 3445 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ 3446 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 3447 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 3448 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3449 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ 3450 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ 3451 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 3452 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 3453 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3454 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ 3455 #define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ 3456 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 3457 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 3458 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3459 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ 3460 #define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ 3461 #define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 3462 #define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 3463 #define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3464 #define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ 3465 #define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ 3466 #define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 3467 #define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 3468 #define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3469 #define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ 3470 #define CMU_IFC_HFXOPEAKDETERR (0x1UL << 10) /**< Clear HFXOPEAKDETERR Interrupt Flag */ 3471 #define _CMU_IFC_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ 3472 #define _CMU_IFC_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ 3473 #define _CMU_IFC_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3474 #define CMU_IFC_HFXOPEAKDETERR_DEFAULT (_CMU_IFC_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IFC */ 3475 #define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ 3476 #define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 3477 #define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 3478 #define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3479 #define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ 3480 #define CMU_IFC_HFXOSHUNTOPTRDY (0x1UL << 12) /**< Clear HFXOSHUNTOPTRDY Interrupt Flag */ 3481 #define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ 3482 #define _CMU_IFC_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ 3483 #define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3484 #define CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IFC */ 3485 #define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ 3486 #define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 3487 #define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 3488 #define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3489 #define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ 3490 #define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ 3491 #define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 3492 #define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 3493 #define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3494 #define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ 3495 #define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ 3496 #define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 3497 #define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 3498 #define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3499 #define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ 3500 #define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ 3501 #define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 3502 #define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 3503 #define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3504 #define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ 3505 #define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ 3506 #define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 3507 #define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 3508 #define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3509 #define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ 3510 #define CMU_IFC_PLFRCOCALDONE (0x1UL << 18) /**< Clear PLFRCOCALDONE Interrupt Flag */ 3511 #define _CMU_IFC_PLFRCOCALDONE_SHIFT 18 /**< Shift value for CMU_PLFRCOCALDONE */ 3512 #define _CMU_IFC_PLFRCOCALDONE_MASK 0x40000UL /**< Bit mask for CMU_PLFRCOCALDONE */ 3513 #define _CMU_IFC_PLFRCOCALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3514 #define CMU_IFC_PLFRCOCALDONE_DEFAULT (_CMU_IFC_PLFRCOCALDONE_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_IFC */ 3515 #define CMU_IFC_PLFRCORDY (0x1UL << 19) /**< Clear PLFRCORDY Interrupt Flag */ 3516 #define _CMU_IFC_PLFRCORDY_SHIFT 19 /**< Shift value for CMU_PLFRCORDY */ 3517 #define _CMU_IFC_PLFRCORDY_MASK 0x80000UL /**< Bit mask for CMU_PLFRCORDY */ 3518 #define _CMU_IFC_PLFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3519 #define CMU_IFC_PLFRCORDY_DEFAULT (_CMU_IFC_PLFRCORDY_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_IFC */ 3520 #define CMU_IFC_PLFRCOHFXODNSERR (0x1UL << 20) /**< Clear PLFRCOHFXODNSERR Interrupt Flag */ 3521 #define _CMU_IFC_PLFRCOHFXODNSERR_SHIFT 20 /**< Shift value for CMU_PLFRCOHFXODNSERR */ 3522 #define _CMU_IFC_PLFRCOHFXODNSERR_MASK 0x100000UL /**< Bit mask for CMU_PLFRCOHFXODNSERR */ 3523 #define _CMU_IFC_PLFRCOHFXODNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3524 #define CMU_IFC_PLFRCOHFXODNSERR_DEFAULT (_CMU_IFC_PLFRCOHFXODNSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_IFC */ 3525 #define CMU_IFC_PLFRCOTEMPCHKDONE (0x1UL << 21) /**< Clear PLFRCOTEMPCHKDONE Interrupt Flag */ 3526 #define _CMU_IFC_PLFRCOTEMPCHKDONE_SHIFT 21 /**< Shift value for CMU_PLFRCOTEMPCHKDONE */ 3527 #define _CMU_IFC_PLFRCOTEMPCHKDONE_MASK 0x200000UL /**< Bit mask for CMU_PLFRCOTEMPCHKDONE */ 3528 #define _CMU_IFC_PLFRCOTEMPCHKDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3529 #define CMU_IFC_PLFRCOTEMPCHKDONE_DEFAULT (_CMU_IFC_PLFRCOTEMPCHKDONE_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_IFC */ 3530 #define CMU_IFC_PLFRCOTIMERDONE (0x1UL << 22) /**< Clear PLFRCOTIMERDONE Interrupt Flag */ 3531 #define _CMU_IFC_PLFRCOTIMERDONE_SHIFT 22 /**< Shift value for CMU_PLFRCOTIMERDONE */ 3532 #define _CMU_IFC_PLFRCOTIMERDONE_MASK 0x400000UL /**< Bit mask for CMU_PLFRCOTIMERDONE */ 3533 #define _CMU_IFC_PLFRCOTIMERDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3534 #define CMU_IFC_PLFRCOTIMERDONE_DEFAULT (_CMU_IFC_PLFRCOTIMERDONE_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_IFC */ 3535 #define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ 3536 #define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 3537 #define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 3538 #define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3539 #define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ 3540 #define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ 3541 #define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 3542 #define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 3543 #define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3544 #define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ 3545 #define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ 3546 #define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 3547 #define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 3548 #define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3549 #define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ 3550 #define CMU_IFC_PLFRCOEDGE (0x1UL << 30) /**< Clear PLFRCOEDGE Interrupt Flag */ 3551 #define _CMU_IFC_PLFRCOEDGE_SHIFT 30 /**< Shift value for CMU_PLFRCOEDGE */ 3552 #define _CMU_IFC_PLFRCOEDGE_MASK 0x40000000UL /**< Bit mask for CMU_PLFRCOEDGE */ 3553 #define _CMU_IFC_PLFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3554 #define CMU_IFC_PLFRCOEDGE_DEFAULT (_CMU_IFC_PLFRCOEDGE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_IFC */ 3555 #define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ 3556 #define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 3557 #define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 3558 #define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 3559 #define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ 3560 3561 /* Bit fields for CMU IEN */ 3562 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ 3563 #define _CMU_IEN_MASK 0xF87FFF7FUL /**< Mask for CMU_IEN */ 3564 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ 3565 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 3566 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 3567 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3568 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ 3569 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ 3570 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 3571 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 3572 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3573 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ 3574 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ 3575 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 3576 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 3577 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3578 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ 3579 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ 3580 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 3581 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 3582 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3583 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ 3584 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ 3585 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 3586 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 3587 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3588 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ 3589 #define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ 3590 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 3591 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 3592 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3593 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ 3594 #define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ 3595 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 3596 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 3597 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3598 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ 3599 #define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ 3600 #define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 3601 #define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 3602 #define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3603 #define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ 3604 #define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ 3605 #define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 3606 #define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 3607 #define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3608 #define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ 3609 #define CMU_IEN_HFXOPEAKDETERR (0x1UL << 10) /**< HFXOPEAKDETERR Interrupt Enable */ 3610 #define _CMU_IEN_HFXOPEAKDETERR_SHIFT 10 /**< Shift value for CMU_HFXOPEAKDETERR */ 3611 #define _CMU_IEN_HFXOPEAKDETERR_MASK 0x400UL /**< Bit mask for CMU_HFXOPEAKDETERR */ 3612 #define _CMU_IEN_HFXOPEAKDETERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3613 #define CMU_IEN_HFXOPEAKDETERR_DEFAULT (_CMU_IEN_HFXOPEAKDETERR_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_IEN */ 3614 #define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ 3615 #define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 3616 #define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 3617 #define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3618 #define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ 3619 #define CMU_IEN_HFXOSHUNTOPTRDY (0x1UL << 12) /**< HFXOSHUNTOPTRDY Interrupt Enable */ 3620 #define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT 12 /**< Shift value for CMU_HFXOSHUNTOPTRDY */ 3621 #define _CMU_IEN_HFXOSHUNTOPTRDY_MASK 0x1000UL /**< Bit mask for CMU_HFXOSHUNTOPTRDY */ 3622 #define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3623 #define CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_IEN */ 3624 #define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ 3625 #define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 3626 #define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 3627 #define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3628 #define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ 3629 #define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ 3630 #define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 3631 #define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 3632 #define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3633 #define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ 3634 #define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ 3635 #define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 3636 #define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 3637 #define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3638 #define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ 3639 #define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ 3640 #define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 3641 #define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 3642 #define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3643 #define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ 3644 #define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ 3645 #define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 3646 #define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 3647 #define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3648 #define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ 3649 #define CMU_IEN_PLFRCOCALDONE (0x1UL << 18) /**< PLFRCOCALDONE Interrupt Enable */ 3650 #define _CMU_IEN_PLFRCOCALDONE_SHIFT 18 /**< Shift value for CMU_PLFRCOCALDONE */ 3651 #define _CMU_IEN_PLFRCOCALDONE_MASK 0x40000UL /**< Bit mask for CMU_PLFRCOCALDONE */ 3652 #define _CMU_IEN_PLFRCOCALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3653 #define CMU_IEN_PLFRCOCALDONE_DEFAULT (_CMU_IEN_PLFRCOCALDONE_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_IEN */ 3654 #define CMU_IEN_PLFRCORDY (0x1UL << 19) /**< PLFRCORDY Interrupt Enable */ 3655 #define _CMU_IEN_PLFRCORDY_SHIFT 19 /**< Shift value for CMU_PLFRCORDY */ 3656 #define _CMU_IEN_PLFRCORDY_MASK 0x80000UL /**< Bit mask for CMU_PLFRCORDY */ 3657 #define _CMU_IEN_PLFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3658 #define CMU_IEN_PLFRCORDY_DEFAULT (_CMU_IEN_PLFRCORDY_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_IEN */ 3659 #define CMU_IEN_PLFRCOHFXODNSERR (0x1UL << 20) /**< PLFRCOHFXODNSERR Interrupt Enable */ 3660 #define _CMU_IEN_PLFRCOHFXODNSERR_SHIFT 20 /**< Shift value for CMU_PLFRCOHFXODNSERR */ 3661 #define _CMU_IEN_PLFRCOHFXODNSERR_MASK 0x100000UL /**< Bit mask for CMU_PLFRCOHFXODNSERR */ 3662 #define _CMU_IEN_PLFRCOHFXODNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3663 #define CMU_IEN_PLFRCOHFXODNSERR_DEFAULT (_CMU_IEN_PLFRCOHFXODNSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_IEN */ 3664 #define CMU_IEN_PLFRCOTEMPCHKDONE (0x1UL << 21) /**< PLFRCOTEMPCHKDONE Interrupt Enable */ 3665 #define _CMU_IEN_PLFRCOTEMPCHKDONE_SHIFT 21 /**< Shift value for CMU_PLFRCOTEMPCHKDONE */ 3666 #define _CMU_IEN_PLFRCOTEMPCHKDONE_MASK 0x200000UL /**< Bit mask for CMU_PLFRCOTEMPCHKDONE */ 3667 #define _CMU_IEN_PLFRCOTEMPCHKDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3668 #define CMU_IEN_PLFRCOTEMPCHKDONE_DEFAULT (_CMU_IEN_PLFRCOTEMPCHKDONE_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_IEN */ 3669 #define CMU_IEN_PLFRCOTIMERDONE (0x1UL << 22) /**< PLFRCOTIMERDONE Interrupt Enable */ 3670 #define _CMU_IEN_PLFRCOTIMERDONE_SHIFT 22 /**< Shift value for CMU_PLFRCOTIMERDONE */ 3671 #define _CMU_IEN_PLFRCOTIMERDONE_MASK 0x400000UL /**< Bit mask for CMU_PLFRCOTIMERDONE */ 3672 #define _CMU_IEN_PLFRCOTIMERDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3673 #define CMU_IEN_PLFRCOTIMERDONE_DEFAULT (_CMU_IEN_PLFRCOTIMERDONE_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_IEN */ 3674 #define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ 3675 #define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 3676 #define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 3677 #define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3678 #define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ 3679 #define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ 3680 #define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 3681 #define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 3682 #define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3683 #define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ 3684 #define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ 3685 #define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 3686 #define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 3687 #define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3688 #define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ 3689 #define CMU_IEN_PLFRCOEDGE (0x1UL << 30) /**< PLFRCOEDGE Interrupt Enable */ 3690 #define _CMU_IEN_PLFRCOEDGE_SHIFT 30 /**< Shift value for CMU_PLFRCOEDGE */ 3691 #define _CMU_IEN_PLFRCOEDGE_MASK 0x40000000UL /**< Bit mask for CMU_PLFRCOEDGE */ 3692 #define _CMU_IEN_PLFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3693 #define CMU_IEN_PLFRCOEDGE_DEFAULT (_CMU_IEN_PLFRCOEDGE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_IEN */ 3694 #define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ 3695 #define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 3696 #define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 3697 #define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 3698 #define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ 3699 3700 /* Bit fields for CMU HFBUSCLKEN0 */ 3701 #define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ 3702 #define _CMU_HFBUSCLKEN0_MASK 0x0000007FUL /**< Mask for CMU_HFBUSCLKEN0 */ 3703 #define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 0) /**< Advanced Encryption Standard Accelerator 0 Clock Enable */ 3704 #define CMU_HFBUSCLKEN0_CRYPTO CMU_HFBUSCLKEN0_CRYPTO0 /**< Alias for CRYPTO0 */ 3705 #define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 0 /**< Shift value for CMU_CRYPTO0 */ 3706 #define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x1UL /**< Bit mask for CMU_CRYPTO0 */ 3707 #define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT /**< Alias for CMU_CRYPTO0 */ 3708 #define _CMU_HFBUSCLKEN0_CRYPTO_MASK _CMU_HFBUSCLKEN0_CRYPTO0_MASK /**< Alias for CMU_CRYPTO0 */ 3709 #define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 3710 #define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT */ 3711 #define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 3712 #define CMU_HFBUSCLKEN0_CRYPTO_DEFAULT CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT /**< Alias for CRYPTO0 mode DEFAULT*/ 3713 #define CMU_HFBUSCLKEN0_CRYPTO1 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator 1 Clock Enable */ 3714 #define _CMU_HFBUSCLKEN0_CRYPTO1_SHIFT 1 /**< Shift value for CMU_CRYPTO1 */ 3715 #define _CMU_HFBUSCLKEN0_CRYPTO1_MASK 0x2UL /**< Bit mask for CMU_CRYPTO1 */ 3716 #define _CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 3717 #define CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 3718 #define CMU_HFBUSCLKEN0_LE (0x1UL << 2) /**< Low Energy Peripheral Interface Clock Enable */ 3719 #define _CMU_HFBUSCLKEN0_LE_SHIFT 2 /**< Shift value for CMU_LE */ 3720 #define _CMU_HFBUSCLKEN0_LE_MASK 0x4UL /**< Bit mask for CMU_LE */ 3721 #define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 3722 #define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 3723 #define CMU_HFBUSCLKEN0_GPIO (0x1UL << 3) /**< General purpose Input/Output Clock Enable */ 3724 #define _CMU_HFBUSCLKEN0_GPIO_SHIFT 3 /**< Shift value for CMU_GPIO */ 3725 #define _CMU_HFBUSCLKEN0_GPIO_MASK 0x8UL /**< Bit mask for CMU_GPIO */ 3726 #define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 3727 #define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 3728 #define CMU_HFBUSCLKEN0_PRS (0x1UL << 4) /**< Peripheral Reflex System Clock Enable */ 3729 #define _CMU_HFBUSCLKEN0_PRS_SHIFT 4 /**< Shift value for CMU_PRS */ 3730 #define _CMU_HFBUSCLKEN0_PRS_MASK 0x10UL /**< Bit mask for CMU_PRS */ 3731 #define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 3732 #define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 3733 #define CMU_HFBUSCLKEN0_LDMA (0x1UL << 5) /**< Linked Direct Memory Access Controller Clock Enable */ 3734 #define _CMU_HFBUSCLKEN0_LDMA_SHIFT 5 /**< Shift value for CMU_LDMA */ 3735 #define _CMU_HFBUSCLKEN0_LDMA_MASK 0x20UL /**< Bit mask for CMU_LDMA */ 3736 #define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 3737 #define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 3738 #define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 6) /**< General Purpose CRC Clock Enable */ 3739 #define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 6 /**< Shift value for CMU_GPCRC */ 3740 #define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x40UL /**< Bit mask for CMU_GPCRC */ 3741 #define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 3742 #define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 3743 3744 /* Bit fields for CMU HFPERCLKEN0 */ 3745 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ 3746 #define _CMU_HFPERCLKEN0_MASK 0x0000FFFFUL /**< Mask for CMU_HFPERCLKEN0 */ 3747 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ 3748 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ 3749 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ 3750 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3751 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3752 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ 3753 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ 3754 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ 3755 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3756 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3757 #define CMU_HFPERCLKEN0_WTIMER0 (0x1UL << 2) /**< Wide Timer 0 Clock Enable */ 3758 #define _CMU_HFPERCLKEN0_WTIMER0_SHIFT 2 /**< Shift value for CMU_WTIMER0 */ 3759 #define _CMU_HFPERCLKEN0_WTIMER0_MASK 0x4UL /**< Bit mask for CMU_WTIMER0 */ 3760 #define _CMU_HFPERCLKEN0_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3761 #define CMU_HFPERCLKEN0_WTIMER0_DEFAULT (_CMU_HFPERCLKEN0_WTIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3762 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 3) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ 3763 #define _CMU_HFPERCLKEN0_USART0_SHIFT 3 /**< Shift value for CMU_USART0 */ 3764 #define _CMU_HFPERCLKEN0_USART0_MASK 0x8UL /**< Bit mask for CMU_USART0 */ 3765 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3766 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3767 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 4) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ 3768 #define _CMU_HFPERCLKEN0_USART1_SHIFT 4 /**< Shift value for CMU_USART1 */ 3769 #define _CMU_HFPERCLKEN0_USART1_MASK 0x10UL /**< Bit mask for CMU_USART1 */ 3770 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3771 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3772 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 5) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ 3773 #define _CMU_HFPERCLKEN0_USART2_SHIFT 5 /**< Shift value for CMU_USART2 */ 3774 #define _CMU_HFPERCLKEN0_USART2_MASK 0x20UL /**< Bit mask for CMU_USART2 */ 3775 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3776 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3777 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 6) /**< I2C 0 Clock Enable */ 3778 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 6 /**< Shift value for CMU_I2C0 */ 3779 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x40UL /**< Bit mask for CMU_I2C0 */ 3780 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3781 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3782 #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 7) /**< I2C 1 Clock Enable */ 3783 #define _CMU_HFPERCLKEN0_I2C1_SHIFT 7 /**< Shift value for CMU_I2C1 */ 3784 #define _CMU_HFPERCLKEN0_I2C1_MASK 0x80UL /**< Bit mask for CMU_I2C1 */ 3785 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3786 #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3787 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 8) /**< Analog Comparator 0 Clock Enable */ 3788 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 8 /**< Shift value for CMU_ACMP0 */ 3789 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x100UL /**< Bit mask for CMU_ACMP0 */ 3790 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3791 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3792 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 9) /**< Analog Comparator 1 Clock Enable */ 3793 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 9 /**< Shift value for CMU_ACMP1 */ 3794 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x200UL /**< Bit mask for CMU_ACMP1 */ 3795 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3796 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3797 #define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 10) /**< CRYOTIMER Clock Enable */ 3798 #define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 10 /**< Shift value for CMU_CRYOTIMER */ 3799 #define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400UL /**< Bit mask for CMU_CRYOTIMER */ 3800 #define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3801 #define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3802 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 11) /**< Analog to Digital Converter 0 Clock Enable */ 3803 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 11 /**< Shift value for CMU_ADC0 */ 3804 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x800UL /**< Bit mask for CMU_ADC0 */ 3805 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3806 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3807 #define CMU_HFPERCLKEN0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 Clock Enable */ 3808 #define _CMU_HFPERCLKEN0_VDAC0_SHIFT 12 /**< Shift value for CMU_VDAC0 */ 3809 #define _CMU_HFPERCLKEN0_VDAC0_MASK 0x1000UL /**< Bit mask for CMU_VDAC0 */ 3810 #define _CMU_HFPERCLKEN0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3811 #define CMU_HFPERCLKEN0_VDAC0_DEFAULT (_CMU_HFPERCLKEN0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3812 #define CMU_HFPERCLKEN0_CSEN (0x1UL << 13) /**< Capacitive touch sense module Clock Enable */ 3813 #define _CMU_HFPERCLKEN0_CSEN_SHIFT 13 /**< Shift value for CMU_CSEN */ 3814 #define _CMU_HFPERCLKEN0_CSEN_MASK 0x2000UL /**< Bit mask for CMU_CSEN */ 3815 #define _CMU_HFPERCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3816 #define CMU_HFPERCLKEN0_CSEN_DEFAULT (_CMU_HFPERCLKEN0_CSEN_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3817 #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 14) /**< Current Digital to Analog Converter 0 Clock Enable */ 3818 #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 14 /**< Shift value for CMU_IDAC0 */ 3819 #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x4000UL /**< Bit mask for CMU_IDAC0 */ 3820 #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3821 #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3822 #define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 15) /**< True Random Number Generator 0 Clock Enable */ 3823 #define _CMU_HFPERCLKEN0_TRNG0_SHIFT 15 /**< Shift value for CMU_TRNG0 */ 3824 #define _CMU_HFPERCLKEN0_TRNG0_MASK 0x8000UL /**< Bit mask for CMU_TRNG0 */ 3825 #define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 3826 #define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 3827 3828 /* Bit fields for CMU LFACLKEN0 */ 3829 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ 3830 #define _CMU_LFACLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFACLKEN0 */ 3831 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ 3832 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ 3833 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ 3834 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 3835 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 3836 #define CMU_LFACLKEN0_LESENSE (0x1UL << 1) /**< Low Energy Sensor Interface Clock Enable */ 3837 #define _CMU_LFACLKEN0_LESENSE_SHIFT 1 /**< Shift value for CMU_LESENSE */ 3838 #define _CMU_LFACLKEN0_LESENSE_MASK 0x2UL /**< Bit mask for CMU_LESENSE */ 3839 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 3840 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 3841 3842 /* Bit fields for CMU LFBCLKEN0 */ 3843 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ 3844 #define _CMU_LFBCLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFBCLKEN0 */ 3845 #define CMU_LFBCLKEN0_SYSTICK (0x1UL << 0) /**< Clock Enable */ 3846 #define _CMU_LFBCLKEN0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */ 3847 #define _CMU_LFBCLKEN0_SYSTICK_MASK 0x1UL /**< Bit mask for CMU_SYSTICK */ 3848 #define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 3849 #define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 3850 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 1) /**< Low Energy UART 0 Clock Enable */ 3851 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 1 /**< Shift value for CMU_LEUART0 */ 3852 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x2UL /**< Bit mask for CMU_LEUART0 */ 3853 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 3854 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 3855 #define CMU_LFBCLKEN0_CSEN (0x1UL << 2) /**< Capacitive touch sense module Clock Enable */ 3856 #define _CMU_LFBCLKEN0_CSEN_SHIFT 2 /**< Shift value for CMU_CSEN */ 3857 #define _CMU_LFBCLKEN0_CSEN_MASK 0x4UL /**< Bit mask for CMU_CSEN */ 3858 #define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 3859 #define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 3860 3861 /* Bit fields for CMU LFECLKEN0 */ 3862 #define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ 3863 #define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ 3864 #define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ 3865 #define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ 3866 #define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ 3867 #define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ 3868 #define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ 3869 3870 /* Bit fields for CMU HFPRESC */ 3871 #define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ 3872 #define _CMU_HFPRESC_MASK 0x01001F00UL /**< Mask for CMU_HFPRESC */ 3873 #define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 3874 #define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ 3875 #define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ 3876 #define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ 3877 #define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ 3878 #define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ 3879 #define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ 3880 #define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x1000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ 3881 #define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ 3882 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ 3883 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ 3884 #define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ 3885 #define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ 3886 #define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ 3887 3888 /* Bit fields for CMU HFCOREPRESC */ 3889 #define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ 3890 #define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ 3891 #define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 3892 #define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ 3893 #define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ 3894 #define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ 3895 #define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ 3896 #define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ 3897 3898 /* Bit fields for CMU HFPERPRESC */ 3899 #define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ 3900 #define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ 3901 #define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 3902 #define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ 3903 #define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ 3904 #define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ 3905 #define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ 3906 #define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ 3907 3908 /* Bit fields for CMU HFEXPPRESC */ 3909 #define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ 3910 #define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ 3911 #define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 3912 #define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ 3913 #define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ 3914 #define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ 3915 #define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ 3916 #define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ 3917 3918 /* Bit fields for CMU LFAPRESC0 */ 3919 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ 3920 #define _CMU_LFAPRESC0_MASK 0x0000003FUL /**< Mask for CMU_LFAPRESC0 */ 3921 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ 3922 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ 3923 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 3924 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 3925 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 3926 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 3927 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ 3928 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ 3929 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ 3930 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ 3931 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ 3932 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ 3933 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ 3934 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ 3935 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ 3936 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ 3937 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ 3938 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ 3939 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 3940 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 3941 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 3942 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 3943 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ 3944 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ 3945 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ 3946 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ 3947 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ 3948 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ 3949 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ 3950 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ 3951 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ 3952 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ 3953 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ 3954 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ 3955 #define _CMU_LFAPRESC0_LESENSE_SHIFT 4 /**< Shift value for CMU_LESENSE */ 3956 #define _CMU_LFAPRESC0_LESENSE_MASK 0x30UL /**< Bit mask for CMU_LESENSE */ 3957 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 3958 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 3959 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 3960 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 3961 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 3962 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 3963 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 3964 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 3965 3966 /* Bit fields for CMU LFBPRESC0 */ 3967 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ 3968 #define _CMU_LFBPRESC0_MASK 0x0000033FUL /**< Mask for CMU_LFBPRESC0 */ 3969 #define _CMU_LFBPRESC0_SYSTICK_SHIFT 0 /**< Shift value for CMU_SYSTICK */ 3970 #define _CMU_LFBPRESC0_SYSTICK_MASK 0xFUL /**< Bit mask for CMU_SYSTICK */ 3971 #define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ 3972 #define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ 3973 #define _CMU_LFBPRESC0_LEUART0_SHIFT 4 /**< Shift value for CMU_LEUART0 */ 3974 #define _CMU_LFBPRESC0_LEUART0_MASK 0x30UL /**< Bit mask for CMU_LEUART0 */ 3975 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ 3976 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ 3977 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ 3978 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ 3979 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ 3980 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ 3981 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ 3982 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ 3983 #define _CMU_LFBPRESC0_CSEN_SHIFT 8 /**< Shift value for CMU_CSEN */ 3984 #define _CMU_LFBPRESC0_CSEN_MASK 0x300UL /**< Bit mask for CMU_CSEN */ 3985 #define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ 3986 #define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ 3987 #define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ 3988 #define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ 3989 #define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ 3990 #define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ 3991 #define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ 3992 #define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ 3993 3994 /* Bit fields for CMU LFEPRESC0 */ 3995 #define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ 3996 #define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ 3997 #define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ 3998 #define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ 3999 #define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ 4000 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ 4001 #define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ 4002 #define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ 4003 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ 4004 #define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ 4005 4006 /* Bit fields for CMU SYNCBUSY */ 4007 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ 4008 #define _CMU_SYNCBUSY_MASK 0x3F055055UL /**< Mask for CMU_SYNCBUSY */ 4009 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ 4010 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ 4011 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ 4012 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 4013 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 4014 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ 4015 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ 4016 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ 4017 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 4018 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 4019 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ 4020 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ 4021 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ 4022 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 4023 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 4024 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ 4025 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ 4026 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ 4027 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 4028 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 4029 #define CMU_SYNCBUSY_LFRCLKEN0 (0x1UL << 12) /**< Low Frequency R Clock Enable 0 Busy */ 4030 #define _CMU_SYNCBUSY_LFRCLKEN0_SHIFT 12 /**< Shift value for CMU_LFRCLKEN0 */ 4031 #define _CMU_SYNCBUSY_LFRCLKEN0_MASK 0x1000UL /**< Bit mask for CMU_LFRCLKEN0 */ 4032 #define _CMU_SYNCBUSY_LFRCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 4033 #define CMU_SYNCBUSY_LFRCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFRCLKEN0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 4034 #define CMU_SYNCBUSY_LFRPRESC0 (0x1UL << 14) /**< Low Frequency R Prescaler 0 Busy */ 4035 #define _CMU_SYNCBUSY_LFRPRESC0_SHIFT 14 /**< Shift value for CMU_LFRPRESC0 */ 4036 #define _CMU_SYNCBUSY_LFRPRESC0_MASK 0x4000UL /**< Bit mask for CMU_LFRPRESC0 */ 4037 #define _CMU_SYNCBUSY_LFRPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 4038 #define CMU_SYNCBUSY_LFRPRESC0_DEFAULT (_CMU_SYNCBUSY_LFRPRESC0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 4039 #define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ 4040 #define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ 4041 #define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ 4042 #define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 4043 #define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 4044 #define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ 4045 #define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ 4046 #define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ 4047 #define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 4048 #define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 4049 #define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ 4050 #define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ 4051 #define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ 4052 #define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 4053 #define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 4054 #define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ 4055 #define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ 4056 #define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ 4057 #define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 4058 #define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 4059 #define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ 4060 #define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ 4061 #define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ 4062 #define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 4063 #define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 4064 #define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ 4065 #define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ 4066 #define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ 4067 #define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 4068 #define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 4069 #define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ 4070 #define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ 4071 #define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ 4072 #define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 4073 #define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 4074 #define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ 4075 #define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ 4076 #define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ 4077 #define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 4078 #define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 4079 4080 /* Bit fields for CMU FREEZE */ 4081 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ 4082 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ 4083 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ 4084 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ 4085 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ 4086 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ 4087 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ 4088 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ 4089 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ 4090 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ 4091 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ 4092 4093 /* Bit fields for CMU PCNTCTRL */ 4094 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ 4095 #define _CMU_PCNTCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNTCTRL */ 4096 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ 4097 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ 4098 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ 4099 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 4100 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 4101 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ 4102 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ 4103 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ 4104 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 4105 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ 4106 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ 4107 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 4108 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ 4109 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ 4110 4111 /* Bit fields for CMU ADCCTRL */ 4112 #define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ 4113 #define _CMU_ADCCTRL_MASK 0x00000130UL /**< Mask for CMU_ADCCTRL */ 4114 #define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ 4115 #define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ 4116 #define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 4117 #define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ 4118 #define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ 4119 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ 4120 #define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ 4121 #define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 4122 #define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ 4123 #define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ 4124 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ 4125 #define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ 4126 #define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ 4127 #define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ 4128 #define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ 4129 #define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 4130 #define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 4131 4132 /* Bit fields for CMU ROUTEPEN */ 4133 #define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ 4134 #define _CMU_ROUTEPEN_MASK 0x10000003UL /**< Mask for CMU_ROUTEPEN */ 4135 #define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ 4136 #define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ 4137 #define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ 4138 #define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ 4139 #define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ 4140 #define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ 4141 #define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ 4142 #define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ 4143 #define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ 4144 #define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ 4145 #define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ 4146 #define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ 4147 #define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ 4148 #define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ 4149 #define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ 4150 4151 /* Bit fields for CMU ROUTELOC0 */ 4152 #define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ 4153 #define _CMU_ROUTELOC0_MASK 0x00000707UL /**< Mask for CMU_ROUTELOC0 */ 4154 #define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ 4155 #define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ 4156 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ 4157 #define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ 4158 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ 4159 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ 4160 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ 4161 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ 4162 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ 4163 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */ 4164 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */ 4165 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ 4166 #define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ 4167 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ 4168 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ 4169 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ 4170 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ 4171 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ 4172 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */ 4173 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */ 4174 #define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ 4175 #define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ 4176 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ 4177 #define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ 4178 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ 4179 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ 4180 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ 4181 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ 4182 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ 4183 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC0 */ 4184 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC0 */ 4185 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ 4186 #define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ 4187 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ 4188 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ 4189 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ 4190 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ 4191 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ 4192 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for CMU_ROUTELOC0 */ 4193 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for CMU_ROUTELOC0 */ 4194 4195 /* Bit fields for CMU ROUTELOC1 */ 4196 #define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ 4197 #define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ 4198 #define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ 4199 #define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ 4200 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ 4201 #define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ 4202 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ 4203 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ 4204 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ 4205 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ 4206 #define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ 4207 #define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ 4208 #define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ 4209 #define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ 4210 #define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ 4211 #define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ 4212 4213 /* Bit fields for CMU LOCK */ 4214 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ 4215 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ 4216 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ 4217 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ 4218 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ 4219 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ 4220 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ 4221 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ 4222 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ 4223 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ 4224 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ 4225 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ 4226 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ 4227 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ 4228 4229 /* Bit fields for CMU HFRCOSS */ 4230 #define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ 4231 #define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ 4232 #define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ 4233 #define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ 4234 #define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ 4235 #define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ 4236 #define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ 4237 #define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ 4238 #define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ 4239 #define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ 4240 4241 /* Bit fields for CMU LFRCLKSEL */ 4242 #define _CMU_LFRCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFRCLKSEL */ 4243 #define _CMU_LFRCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFRCLKSEL */ 4244 #define _CMU_LFRCLKSEL_LFR_SHIFT 0 /**< Shift value for CMU_LFR */ 4245 #define _CMU_LFRCLKSEL_LFR_MASK 0x7UL /**< Bit mask for CMU_LFR */ 4246 #define _CMU_LFRCLKSEL_LFR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCLKSEL */ 4247 #define _CMU_LFRCLKSEL_LFR_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFRCLKSEL */ 4248 #define _CMU_LFRCLKSEL_LFR_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFRCLKSEL */ 4249 #define _CMU_LFRCLKSEL_LFR_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFRCLKSEL */ 4250 #define _CMU_LFRCLKSEL_LFR_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFRCLKSEL */ 4251 #define _CMU_LFRCLKSEL_LFR_PLFRCO 0x00000005UL /**< Mode PLFRCO for CMU_LFRCLKSEL */ 4252 #define CMU_LFRCLKSEL_LFR_DEFAULT (_CMU_LFRCLKSEL_LFR_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCLKSEL */ 4253 #define CMU_LFRCLKSEL_LFR_DISABLED (_CMU_LFRCLKSEL_LFR_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFRCLKSEL */ 4254 #define CMU_LFRCLKSEL_LFR_LFRCO (_CMU_LFRCLKSEL_LFR_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFRCLKSEL */ 4255 #define CMU_LFRCLKSEL_LFR_LFXO (_CMU_LFRCLKSEL_LFR_LFXO << 0) /**< Shifted mode LFXO for CMU_LFRCLKSEL */ 4256 #define CMU_LFRCLKSEL_LFR_ULFRCO (_CMU_LFRCLKSEL_LFR_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFRCLKSEL */ 4257 #define CMU_LFRCLKSEL_LFR_PLFRCO (_CMU_LFRCLKSEL_LFR_PLFRCO << 0) /**< Shifted mode PLFRCO for CMU_LFRCLKSEL */ 4258 4259 /* Bit fields for CMU LFRCLKEN0 */ 4260 #define _CMU_LFRCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFRCLKEN0 */ 4261 #define _CMU_LFRCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFRCLKEN0 */ 4262 #define CMU_LFRCLKEN0_PRORTC (0x1UL << 0) /**< Protocol Real-Time Counter Clock Enable */ 4263 #define _CMU_LFRCLKEN0_PRORTC_SHIFT 0 /**< Shift value for CMU_PRORTC */ 4264 #define _CMU_LFRCLKEN0_PRORTC_MASK 0x1UL /**< Bit mask for CMU_PRORTC */ 4265 #define _CMU_LFRCLKEN0_PRORTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCLKEN0 */ 4266 #define CMU_LFRCLKEN0_PRORTC_DEFAULT (_CMU_LFRCLKEN0_PRORTC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCLKEN0 */ 4267 4268 /* Bit fields for CMU LFRPRESC0 */ 4269 #define _CMU_LFRPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFRPRESC0 */ 4270 #define _CMU_LFRPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFRPRESC0 */ 4271 #define _CMU_LFRPRESC0_PRORTC_SHIFT 0 /**< Shift value for CMU_PRORTC */ 4272 #define _CMU_LFRPRESC0_PRORTC_MASK 0x3UL /**< Bit mask for CMU_PRORTC */ 4273 #define _CMU_LFRPRESC0_PRORTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFRPRESC0 */ 4274 #define _CMU_LFRPRESC0_PRORTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFRPRESC0 */ 4275 #define _CMU_LFRPRESC0_PRORTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFRPRESC0 */ 4276 #define CMU_LFRPRESC0_PRORTC_DIV1 (_CMU_LFRPRESC0_PRORTC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFRPRESC0 */ 4277 #define CMU_LFRPRESC0_PRORTC_DIV2 (_CMU_LFRPRESC0_PRORTC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFRPRESC0 */ 4278 #define CMU_LFRPRESC0_PRORTC_DIV4 (_CMU_LFRPRESC0_PRORTC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFRPRESC0 */ 4279 4280 /** @} */ 4281 /** @} End of group EFR32BG13P532F512GM32_CMU */ 4282 4283 /***************************************************************************//** 4284 * @addtogroup EFR32BG13P532F512GM32_PRORTC 4285 * @{ 4286 * @defgroup EFR32BG13P532F512GM32_PRORTC_BitFields PRORTC Bit Fields 4287 * @{ 4288 ******************************************************************************/ 4289 4290 /* Bit fields for PRORTC CTRL */ 4291 #define _PRORTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRORTC_CTRL */ 4292 #define _PRORTC_CTRL_MASK 0x00000007UL /**< Mask for PRORTC_CTRL */ 4293 #define PRORTC_CTRL_EN (0x1UL << 0) /**< RTC Enable */ 4294 #define _PRORTC_CTRL_EN_SHIFT 0 /**< Shift value for RTC_EN */ 4295 #define _PRORTC_CTRL_EN_MASK 0x1UL /**< Bit mask for RTC_EN */ 4296 #define _PRORTC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRORTC_CTRL */ 4297 #define PRORTC_CTRL_EN_DEFAULT (_PRORTC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRORTC_CTRL */ 4298 #define PRORTC_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ 4299 #define _PRORTC_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for RTC_DEBUGRUN */ 4300 #define _PRORTC_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for RTC_DEBUGRUN */ 4301 #define _PRORTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRORTC_CTRL */ 4302 #define PRORTC_CTRL_DEBUGRUN_DEFAULT (_PRORTC_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRORTC_CTRL */ 4303 #define PRORTC_CTRL_COMP0TOP (0x1UL << 2) /**< Compare Channel 0 is Top Value */ 4304 #define _PRORTC_CTRL_COMP0TOP_SHIFT 2 /**< Shift value for RTC_COMP0TOP */ 4305 #define _PRORTC_CTRL_COMP0TOP_MASK 0x4UL /**< Bit mask for RTC_COMP0TOP */ 4306 #define _PRORTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRORTC_CTRL */ 4307 #define _PRORTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /**< Mode DISABLE for PRORTC_CTRL */ 4308 #define _PRORTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /**< Mode ENABLE for PRORTC_CTRL */ 4309 #define PRORTC_CTRL_COMP0TOP_DEFAULT (_PRORTC_CTRL_COMP0TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for PRORTC_CTRL */ 4310 #define PRORTC_CTRL_COMP0TOP_DISABLE (_PRORTC_CTRL_COMP0TOP_DISABLE << 2) /**< Shifted mode DISABLE for PRORTC_CTRL */ 4311 #define PRORTC_CTRL_COMP0TOP_ENABLE (_PRORTC_CTRL_COMP0TOP_ENABLE << 2) /**< Shifted mode ENABLE for PRORTC_CTRL */ 4312 4313 /* Bit fields for PRORTC CNT */ 4314 #define _PRORTC_CNT_RESETVALUE 0x00000000UL /**< Default value for PRORTC_CNT */ 4315 #define _PRORTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for PRORTC_CNT */ 4316 #define _PRORTC_CNT_CNT_SHIFT 0 /**< Shift value for RTC_CNT */ 4317 #define _PRORTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTC_CNT */ 4318 #define _PRORTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRORTC_CNT */ 4319 #define PRORTC_CNT_CNT_DEFAULT (_PRORTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PRORTC_CNT */ 4320 4321 /* Bit fields for PRORTC IF */ 4322 #define _PRORTC_IF_RESETVALUE 0x00000000UL /**< Default value for PRORTC_IF */ 4323 #define _PRORTC_IF_MASK 0x00000007UL /**< Mask for PRORTC_IF */ 4324 #define PRORTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ 4325 #define _PRORTC_IF_OF_SHIFT 0 /**< Shift value for RTC_OF */ 4326 #define _PRORTC_IF_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 4327 #define _PRORTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRORTC_IF */ 4328 #define PRORTC_IF_OF_DEFAULT (_PRORTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for PRORTC_IF */ 4329 #define _PRORTC_IF_COMP_SHIFT 1 /**< Shift value for RTC_COMP */ 4330 #define _PRORTC_IF_COMP_MASK 0x6UL /**< Bit mask for RTC_COMP */ 4331 #define _PRORTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRORTC_IF */ 4332 #define PRORTC_IF_COMP_DEFAULT (_PRORTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for PRORTC_IF */ 4333 4334 /* Bit fields for PRORTC IFS */ 4335 #define _PRORTC_IFS_RESETVALUE 0x00000000UL /**< Default value for PRORTC_IFS */ 4336 #define _PRORTC_IFS_MASK 0x00000007UL /**< Mask for PRORTC_IFS */ 4337 #define PRORTC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ 4338 #define _PRORTC_IFS_OF_SHIFT 0 /**< Shift value for RTC_OF */ 4339 #define _PRORTC_IFS_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 4340 #define _PRORTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRORTC_IFS */ 4341 #define PRORTC_IFS_OF_DEFAULT (_PRORTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for PRORTC_IFS */ 4342 #define _PRORTC_IFS_COMP_SHIFT 1 /**< Shift value for RTC_COMP */ 4343 #define _PRORTC_IFS_COMP_MASK 0x6UL /**< Bit mask for RTC_COMP */ 4344 #define _PRORTC_IFS_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRORTC_IFS */ 4345 #define PRORTC_IFS_COMP_DEFAULT (_PRORTC_IFS_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for PRORTC_IFS */ 4346 4347 /* Bit fields for PRORTC IFC */ 4348 #define _PRORTC_IFC_RESETVALUE 0x00000000UL /**< Default value for PRORTC_IFC */ 4349 #define _PRORTC_IFC_MASK 0x00000007UL /**< Mask for PRORTC_IFC */ 4350 #define PRORTC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ 4351 #define _PRORTC_IFC_OF_SHIFT 0 /**< Shift value for RTC_OF */ 4352 #define _PRORTC_IFC_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 4353 #define _PRORTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRORTC_IFC */ 4354 #define PRORTC_IFC_OF_DEFAULT (_PRORTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for PRORTC_IFC */ 4355 #define _PRORTC_IFC_COMP_SHIFT 1 /**< Shift value for RTC_COMP */ 4356 #define _PRORTC_IFC_COMP_MASK 0x6UL /**< Bit mask for RTC_COMP */ 4357 #define _PRORTC_IFC_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRORTC_IFC */ 4358 #define PRORTC_IFC_COMP_DEFAULT (_PRORTC_IFC_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for PRORTC_IFC */ 4359 4360 /* Bit fields for PRORTC IEN */ 4361 #define _PRORTC_IEN_RESETVALUE 0x00000000UL /**< Default value for PRORTC_IEN */ 4362 #define _PRORTC_IEN_MASK 0x00000007UL /**< Mask for PRORTC_IEN */ 4363 #define PRORTC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ 4364 #define _PRORTC_IEN_OF_SHIFT 0 /**< Shift value for RTC_OF */ 4365 #define _PRORTC_IEN_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ 4366 #define _PRORTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRORTC_IEN */ 4367 #define PRORTC_IEN_OF_DEFAULT (_PRORTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for PRORTC_IEN */ 4368 #define _PRORTC_IEN_COMP_SHIFT 1 /**< Shift value for RTC_COMP */ 4369 #define _PRORTC_IEN_COMP_MASK 0x6UL /**< Bit mask for RTC_COMP */ 4370 #define _PRORTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRORTC_IEN */ 4371 #define PRORTC_IEN_COMP_DEFAULT (_PRORTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for PRORTC_IEN */ 4372 4373 /* Bit fields for PRORTC COMP_COMP */ 4374 #define _PRORTC_COMP_COMP_RESETVALUE 0x00000000UL /**< Default value for PRORTC_COMP_COMP */ 4375 #define _PRORTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Mask for PRORTC_COMP_COMP */ 4376 #define _PRORTC_COMP_COMP_COMP_SHIFT 0 /**< Shift value for RTC_COMP */ 4377 #define _PRORTC_COMP_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for RTC_COMP */ 4378 #define _PRORTC_COMP_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRORTC_COMP_COMP */ 4379 #define PRORTC_COMP_COMP_COMP_DEFAULT (_PRORTC_COMP_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for PRORTC_COMP_COMP */ 4380 4381 /** @} */ 4382 /** @} End of group EFR32BG13P532F512GM32_PRORTC */ 4383 4384 /***************************************************************************//** 4385 * @defgroup EFR32BG13P532F512GM32_UNLOCK Unlock Codes 4386 * @{ 4387 ******************************************************************************/ 4388 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ 4389 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ 4390 #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ 4391 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ 4392 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ 4393 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ 4394 #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ 4395 4396 /** @} End of group EFR32BG13P532F512GM32_UNLOCK */ 4397 4398 /** @} End of group EFR32BG13P532F512GM32_BitFields */ 4399 4400 #include "efr32bg13p_af_ports.h" 4401 #include "efr32bg13p_af_pins.h" 4402 4403 /** @} End of group EFR32BG13P532F512GM32 */ 4404 4405 /** @} End of group Parts */ 4406 4407 #ifdef __cplusplus 4408 } 4409 #endif 4410 #endif /* EFR32BG13P532F512GM32_H */ 4411
