1 /***************************************************************************//** 2 * @file 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File 4 * for EFM32WG995F128 5 ******************************************************************************* 6 * # License 7 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 8 ******************************************************************************* 9 * 10 * SPDX-License-Identifier: Zlib 11 * 12 * The licensor of this software is Silicon Laboratories Inc. 13 * 14 * This software is provided 'as-is', without any express or implied 15 * warranty. In no event will the authors be held liable for any damages 16 * arising from the use of this software. 17 * 18 * Permission is granted to anyone to use this software for any purpose, 19 * including commercial applications, and to alter it and redistribute it 20 * freely, subject to the following restrictions: 21 * 22 * 1. The origin of this software must not be misrepresented; you must not 23 * claim that you wrote the original software. If you use this software 24 * in a product, an acknowledgment in the product documentation would be 25 * appreciated but is not required. 26 * 2. Altered source versions must be plainly marked as such, and must not be 27 * misrepresented as being the original software. 28 * 3. This notice may not be removed or altered from any source distribution. 29 * 30 ******************************************************************************/ 31 32 #if defined(__ICCARM__) 33 #pragma system_include /* Treat file as system include file. */ 34 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 35 #pragma clang system_header /* Treat file as system include file. */ 36 #endif 37 38 #ifndef EFM32WG995F128_H 39 #define EFM32WG995F128_H 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /***************************************************************************//** 46 * @addtogroup Parts 47 * @{ 48 ******************************************************************************/ 49 50 /***************************************************************************//** 51 * @defgroup EFM32WG995F128 EFM32WG995F128 52 * @{ 53 ******************************************************************************/ 54 55 /** Interrupt Number Definition */ 56 typedef enum IRQn{ 57 /****** Cortex-M4 Processor Exceptions Numbers ********************************************/ 58 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ 59 HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ 60 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ 61 BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ 62 UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ 63 SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ 64 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ 65 PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ 66 SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ 67 68 /****** EFM32WG Peripheral Interrupt Numbers **********************************************/ 69 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */ 70 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */ 71 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */ 72 USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */ 73 USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */ 74 USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */ 75 ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */ 76 ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */ 77 DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */ 78 I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */ 79 I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */ 80 GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */ 81 TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */ 82 TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */ 83 TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */ 84 USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */ 85 USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */ 86 LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */ 87 USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */ 88 USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */ 89 UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */ 90 UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */ 91 UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */ 92 UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */ 93 LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */ 94 LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */ 95 LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */ 96 PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */ 97 PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */ 98 PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */ 99 RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */ 100 BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */ 101 CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */ 102 VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */ 103 LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */ 104 MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */ 105 AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */ 106 EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */ 107 EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */ 108 FPUEH_IRQn = 39, /*!< 39 EFM32 FPUEH Interrupt */ 109 } IRQn_Type; 110 111 /***************************************************************************//** 112 * @defgroup EFM32WG995F128_Core EFM32WG995F128 Core 113 * @{ 114 * @brief Processor and Core Peripheral Section 115 ******************************************************************************/ 116 #define __MPU_PRESENT 1U /**< Presence of MPU */ 117 #define __FPU_PRESENT 1U /**< Presence of FPU */ 118 #define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ 119 #define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ 120 #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ 121 122 /** @} End of group EFM32WG995F128_Core */ 123 124 /***************************************************************************//** 125 * @defgroup EFM32WG995F128_Part EFM32WG995F128 Part 126 * @{ 127 ******************************************************************************/ 128 129 /** Part family */ 130 #define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ 131 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ 132 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ 133 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ 134 #define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /**< Silicon Labs internal use only, may change any time */ 135 #define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /**< Silicon Labs internal use only, may change any time */ 136 #define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ 137 #define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ 138 139 /* If part number is not defined as compiler option, define it */ 140 #if !defined(EFM32WG995F128) 141 #define EFM32WG995F128 1 /**< Wonder Gecko Part */ 142 #endif 143 144 /** Configure part number */ 145 #define PART_NUMBER "EFM32WG995F128" /**< Part Number */ 146 147 /** Memory Base addresses and limits */ 148 #define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ 149 #define RAM_MEM_SIZE (0x40000UL) /**< RAM available address space */ 150 #define RAM_MEM_END (0x2003FFFFUL) /**< RAM end address */ 151 #define RAM_MEM_BITS (0x18UL) /**< RAM used bits */ 152 #define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ 153 #define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ 154 #define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ 155 #define EBI_CODE_MEM_BITS (0x28UL) /**< EBI_CODE used bits */ 156 #define USBC_MEM_BASE (0x40100000UL) /**< USBC base address */ 157 #define USBC_MEM_SIZE (0x40000UL) /**< USBC available address space */ 158 #define USBC_MEM_END (0x4013FFFFUL) /**< USBC end address */ 159 #define USBC_MEM_BITS (0x18UL) /**< USBC used bits */ 160 #define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */ 161 #define RAM_CODE_MEM_SIZE (0x20000UL) /**< RAM_CODE available address space */ 162 #define RAM_CODE_MEM_END (0x1001FFFFUL) /**< RAM_CODE end address */ 163 #define RAM_CODE_MEM_BITS (0x17UL) /**< RAM_CODE used bits */ 164 #define PER_MEM_BASE (0x40000000UL) /**< PER base address */ 165 #define PER_MEM_SIZE (0xE0000UL) /**< PER available address space */ 166 #define PER_MEM_END (0x400DFFFFUL) /**< PER end address */ 167 #define PER_MEM_BITS (0x20UL) /**< PER used bits */ 168 #define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ 169 #define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ 170 #define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ 171 #define EBI_MEM_BITS (0x30UL) /**< EBI used bits */ 172 #define FLASH_MEM_BASE (0x0UL) /**< FLASH base address */ 173 #define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */ 174 #define FLASH_MEM_END (0xFFFFFFFUL) /**< FLASH end address */ 175 #define FLASH_MEM_BITS (0x28UL) /**< FLASH used bits */ 176 #define AES_MEM_BASE (0x400E0000UL) /**< AES base address */ 177 #define AES_MEM_SIZE (0x400UL) /**< AES available address space */ 178 #define AES_MEM_END (0x400E03FFUL) /**< AES end address */ 179 #define AES_MEM_BITS (0x10UL) /**< AES used bits */ 180 181 /** Bit banding area */ 182 #define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ 183 #define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ 184 185 /** Flash and SRAM limits for EFM32WG995F128 */ 186 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ 187 #define FLASH_SIZE (0x00020000UL) /**< Available Flash Memory */ 188 #define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */ 189 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ 190 #define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */ 191 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ 192 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ 193 #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */ 194 #define EXT_IRQ_COUNT 40 /**< Number of External (NVIC) interrupts */ 195 196 /** AF channels connect the different on-chip peripherals with the af-mux */ 197 #define AFCHAN_MAX 163U 198 #define AFCHANLOC_MAX 7U 199 /** Analog AF channels */ 200 #define AFACHAN_MAX 53U 201 202 /* Part number capabilities */ 203 204 #define USART_PRESENT /**< USART is available in this part */ 205 #define USART_COUNT 3 /**< 3 USARTs available */ 206 #define UART_PRESENT /**< UART is available in this part */ 207 #define UART_COUNT 2 /**< 2 UARTs available */ 208 #define TIMER_PRESENT /**< TIMER is available in this part */ 209 #define TIMER_COUNT 4 /**< 4 TIMERs available */ 210 #define ACMP_PRESENT /**< ACMP is available in this part */ 211 #define ACMP_COUNT 2 /**< 2 ACMPs available */ 212 #define LEUART_PRESENT /**< LEUART is available in this part */ 213 #define LEUART_COUNT 2 /**< 2 LEUARTs available */ 214 #define LETIMER_PRESENT /**< LETIMER is available in this part */ 215 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */ 216 #define PCNT_PRESENT /**< PCNT is available in this part */ 217 #define PCNT_COUNT 3 /**< 3 PCNTs available */ 218 #define I2C_PRESENT /**< I2C is available in this part */ 219 #define I2C_COUNT 2 /**< 2 I2Cs available */ 220 #define ADC_PRESENT /**< ADC is available in this part */ 221 #define ADC_COUNT 1 /**< 1 ADCs available */ 222 #define DAC_PRESENT /**< DAC is available in this part */ 223 #define DAC_COUNT 1 /**< 1 DACs available */ 224 #define DMA_PRESENT /**< DMA is available in this part */ 225 #define DMA_COUNT 1 /**< 1 DMA available */ 226 #define AES_PRESENT /**< AES is available in this part */ 227 #define AES_COUNT 1 /**< 1 AES available */ 228 #define USBC_PRESENT /**< USBC is available in this part */ 229 #define USBC_COUNT 1 /**< 1 USBC available */ 230 #define USB_PRESENT /**< USB is available in this part */ 231 #define USB_COUNT 1 /**< 1 USB available */ 232 #define LE_PRESENT /**< LE is available in this part */ 233 #define LE_COUNT 1 /**< 1 LE available */ 234 #define MSC_PRESENT /**< MSC is available in this part */ 235 #define MSC_COUNT 1 /**< 1 MSC available */ 236 #define EMU_PRESENT /**< EMU is available in this part */ 237 #define EMU_COUNT 1 /**< 1 EMU available */ 238 #define RMU_PRESENT /**< RMU is available in this part */ 239 #define RMU_COUNT 1 /**< 1 RMU available */ 240 #define CMU_PRESENT /**< CMU is available in this part */ 241 #define CMU_COUNT 1 /**< 1 CMU available */ 242 #define LESENSE_PRESENT /**< LESENSE is available in this part */ 243 #define LESENSE_COUNT 1 /**< 1 LESENSE available */ 244 #define EBI_PRESENT /**< EBI is available in this part */ 245 #define EBI_COUNT 1 /**< 1 EBI available */ 246 #define FPUEH_PRESENT /**< FPUEH is available in this part */ 247 #define FPUEH_COUNT 1 /**< 1 FPUEH available */ 248 #define RTC_PRESENT /**< RTC is available in this part */ 249 #define RTC_COUNT 1 /**< 1 RTC available */ 250 #define GPIO_PRESENT /**< GPIO is available in this part */ 251 #define GPIO_COUNT 1 /**< 1 GPIO available */ 252 #define VCMP_PRESENT /**< VCMP is available in this part */ 253 #define VCMP_COUNT 1 /**< 1 VCMP available */ 254 #define PRS_PRESENT /**< PRS is available in this part */ 255 #define PRS_COUNT 1 /**< 1 PRS available */ 256 #define OPAMP_PRESENT /**< OPAMP is available in this part */ 257 #define OPAMP_COUNT 1 /**< 1 OPAMP available */ 258 #define BU_PRESENT /**< BU is available in this part */ 259 #define BU_COUNT 1 /**< 1 BU available */ 260 #define LCD_PRESENT /**< LCD is available in this part */ 261 #define LCD_COUNT 1 /**< 1 LCD available */ 262 #define BURTC_PRESENT /**< BURTC is available in this part */ 263 #define BURTC_COUNT 1 /**< 1 BURTC available */ 264 #define HFXTAL_PRESENT /**< HFXTAL is available in this part */ 265 #define HFXTAL_COUNT 1 /**< 1 HFXTAL available */ 266 #define LFXTAL_PRESENT /**< LFXTAL is available in this part */ 267 #define LFXTAL_COUNT 1 /**< 1 LFXTAL available */ 268 #define WDOG_PRESENT /**< WDOG is available in this part */ 269 #define WDOG_COUNT 1 /**< 1 WDOG available */ 270 #define DBG_PRESENT /**< DBG is available in this part */ 271 #define DBG_COUNT 1 /**< 1 DBG available */ 272 #define ETM_PRESENT /**< ETM is available in this part */ 273 #define ETM_COUNT 1 /**< 1 ETM available */ 274 #define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ 275 #define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ 276 #define ANALOG_PRESENT /**< ANALOG is available in this part */ 277 #define ANALOG_COUNT 1 /**< 1 ANALOG available */ 278 279 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 280 #include "system_efm32wg.h" /* System Header */ 281 282 /** @} End of group EFM32WG995F128_Part */ 283 284 /***************************************************************************//** 285 * @defgroup EFM32WG995F128_Peripheral_TypeDefs EFM32WG995F128 Peripheral TypeDefs 286 * @{ 287 * @brief Device Specific Peripheral Register Structures 288 ******************************************************************************/ 289 290 #include "efm32wg_dma_ch.h" 291 #include "efm32wg_dma.h" 292 #include "efm32wg_aes.h" 293 #include "efm32wg_usb_hc.h" 294 #include "efm32wg_usb_diep.h" 295 #include "efm32wg_usb_doep.h" 296 #include "efm32wg_usb.h" 297 #include "efm32wg_msc.h" 298 #include "efm32wg_emu.h" 299 #include "efm32wg_rmu.h" 300 #include "efm32wg_cmu.h" 301 #include "efm32wg_lesense_st.h" 302 #include "efm32wg_lesense_buf.h" 303 #include "efm32wg_lesense_ch.h" 304 #include "efm32wg_lesense.h" 305 #include "efm32wg_ebi.h" 306 #include "efm32wg_fpueh.h" 307 #include "efm32wg_usart.h" 308 #include "efm32wg_timer_cc.h" 309 #include "efm32wg_timer.h" 310 #include "efm32wg_acmp.h" 311 #include "efm32wg_leuart.h" 312 #include "efm32wg_rtc.h" 313 #include "efm32wg_letimer.h" 314 #include "efm32wg_pcnt.h" 315 #include "efm32wg_i2c.h" 316 #include "efm32wg_gpio_p.h" 317 #include "efm32wg_gpio.h" 318 #include "efm32wg_vcmp.h" 319 #include "efm32wg_prs_ch.h" 320 #include "efm32wg_prs.h" 321 #include "efm32wg_adc.h" 322 #include "efm32wg_dac.h" 323 #include "efm32wg_lcd.h" 324 #include "efm32wg_burtc_ret.h" 325 #include "efm32wg_burtc.h" 326 #include "efm32wg_wdog.h" 327 #include "efm32wg_etm.h" 328 #include "efm32wg_dma_descriptor.h" 329 #include "efm32wg_devinfo.h" 330 #include "efm32wg_romtable.h" 331 #include "efm32wg_calibrate.h" 332 333 /** @} End of group EFM32WG995F128_Peripheral_TypeDefs */ 334 335 /***************************************************************************//** 336 * @defgroup EFM32WG995F128_Peripheral_Base EFM32WG995F128 Peripheral Memory Map 337 * @{ 338 ******************************************************************************/ 339 340 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ 341 #define AES_BASE (0x400E0000UL) /**< AES base address */ 342 #define USB_BASE (0x400C4000UL) /**< USB base address */ 343 #define MSC_BASE (0x400C0000UL) /**< MSC base address */ 344 #define EMU_BASE (0x400C6000UL) /**< EMU base address */ 345 #define RMU_BASE (0x400CA000UL) /**< RMU base address */ 346 #define CMU_BASE (0x400C8000UL) /**< CMU base address */ 347 #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */ 348 #define EBI_BASE (0x40008000UL) /**< EBI base address */ 349 #define FPUEH_BASE (0x400C1C00UL) /**< FPUEH base address */ 350 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */ 351 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */ 352 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */ 353 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */ 354 #define UART1_BASE (0x4000E400UL) /**< UART1 base address */ 355 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */ 356 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */ 357 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */ 358 #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */ 359 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */ 360 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */ 361 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */ 362 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */ 363 #define RTC_BASE (0x40080000UL) /**< RTC base address */ 364 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */ 365 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */ 366 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */ 367 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */ 368 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */ 369 #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */ 370 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ 371 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */ 372 #define PRS_BASE (0x400CC000UL) /**< PRS base address */ 373 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ 374 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */ 375 #define LCD_BASE (0x4008A000UL) /**< LCD base address */ 376 #define BURTC_BASE (0x40081000UL) /**< BURTC base address */ 377 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */ 378 #define ETM_BASE (0xE0041000UL) /**< ETM base address */ 379 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */ 380 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ 381 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ 382 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ 383 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ 384 385 /** @} End of group EFM32WG995F128_Peripheral_Base */ 386 387 /***************************************************************************//** 388 * @defgroup EFM32WG995F128_Peripheral_Declaration EFM32WG995F128 Peripheral Declarations 389 * @{ 390 ******************************************************************************/ 391 392 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */ 393 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */ 394 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ 395 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ 396 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ 397 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ 398 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ 399 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ 400 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ 401 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ 402 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ 403 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ 404 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ 405 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ 406 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ 407 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ 408 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ 409 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ 410 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ 411 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ 412 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ 413 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ 414 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ 415 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ 416 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ 417 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ 418 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ 419 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ 420 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ 421 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ 422 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ 423 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */ 424 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ 425 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ 426 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */ 427 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ 428 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ 429 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */ 430 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ 431 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */ 432 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ 433 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ 434 435 /** @} End of group EFM32WG995F128_Peripheral_Declaration */ 436 437 /***************************************************************************//** 438 * @defgroup EFM32WG995F128_BitFields EFM32WG995F128 Bit Fields 439 * @{ 440 ******************************************************************************/ 441 442 #include "efm32wg_prs_signals.h" 443 #include "efm32wg_dmareq.h" 444 #include "efm32wg_dmactrl.h" 445 #include "efm32wg_uart.h" 446 447 /***************************************************************************//** 448 * @defgroup EFM32WG995F128_UNLOCK EFM32WG995F128 Unlock Codes 449 * @{ 450 ******************************************************************************/ 451 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ 452 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ 453 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ 454 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ 455 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ 456 #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */ 457 458 /** @} End of group EFM32WG995F128_UNLOCK */ 459 460 /** @} End of group EFM32WG995F128_BitFields */ 461 462 /***************************************************************************//** 463 * @defgroup EFM32WG995F128_Alternate_Function EFM32WG995F128 Alternate Function 464 * @{ 465 ******************************************************************************/ 466 467 #include "efm32wg_af_ports.h" 468 #include "efm32wg_af_pins.h" 469 470 /** @} End of group EFM32WG995F128_Alternate_Function */ 471 472 /***************************************************************************//** 473 * @brief Set the value of a bit field within a register. 474 * 475 * @param REG 476 * The register to update 477 * @param MASK 478 * The mask for the bit field to update 479 * @param VALUE 480 * The value to write to the bit field 481 * @param OFFSET 482 * The number of bits that the field is offset within the register. 483 * 0 (zero) means LSB. 484 ******************************************************************************/ 485 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ 486 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); 487 488 /** @} End of group EFM32WG995F128 */ 489 490 /** @} End of group Parts */ 491 492 #ifdef __cplusplus 493 } 494 #endif 495 #endif /* EFM32WG995F128_H */ 496
