1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG11B_USART register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG11B_USART USART 43 * @{ 44 * @brief EFM32GG11B_USART Register Declaration 45 ******************************************************************************/ 46 /** USART Register Declaration */ 47 typedef struct { 48 __IOM uint32_t CTRL; /**< Control Register */ 49 __IOM uint32_t FRAME; /**< USART Frame Format Register */ 50 __IOM uint32_t TRIGCTRL; /**< USART Trigger Control Register */ 51 __IOM uint32_t CMD; /**< Command Register */ 52 __IM uint32_t STATUS; /**< USART Status Register */ 53 __IOM uint32_t CLKDIV; /**< Clock Control Register */ 54 __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ 55 __IM uint32_t RXDATA; /**< RX Buffer Data Register */ 56 __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ 57 __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ 58 __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ 59 __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */ 60 __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ 61 __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ 62 __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ 63 __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ 64 __IM uint32_t IF; /**< Interrupt Flag Register */ 65 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 66 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 67 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 68 __IOM uint32_t IRCTRL; /**< IrDA Control Register */ 69 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 70 __IOM uint32_t INPUT; /**< USART Input Register */ 71 __IOM uint32_t I2SCTRL; /**< I2S Control Register */ 72 __IOM uint32_t TIMING; /**< Timing Register */ 73 __IOM uint32_t CTRLX; /**< Control Register Extended */ 74 __IOM uint32_t TIMECMP0; /**< Used to Generate Interrupts and Various Delays */ 75 __IOM uint32_t TIMECMP1; /**< Used to Generate Interrupts and Various Delays */ 76 __IOM uint32_t TIMECMP2; /**< Used to Generate Interrupts and Various Delays */ 77 __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ 78 __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ 79 __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ 80 } USART_TypeDef; /** @} */ 81 82 /***************************************************************************//** 83 * @addtogroup EFM32GG11B_USART 84 * @{ 85 * @defgroup EFM32GG11B_USART_BitFields USART Bit Fields 86 * @{ 87 ******************************************************************************/ 88 89 /* Bit fields for USART CTRL */ 90 #define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ 91 #define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ 92 #define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ 93 #define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ 94 #define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ 95 #define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 96 #define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ 97 #define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ 98 #define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ 99 #define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ 100 #define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 101 #define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ 102 #define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ 103 #define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ 104 #define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ 105 #define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 106 #define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ 107 #define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ 108 #define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ 109 #define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ 110 #define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 111 #define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ 112 #define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ 113 #define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ 114 #define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ 115 #define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 116 #define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ 117 #define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ 118 #define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ 119 #define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 120 #define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ 121 #define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ 122 #define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ 123 #define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ 124 #define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ 125 #define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ 126 #define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ 127 #define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ 128 #define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ 129 #define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ 130 #define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ 131 #define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ 132 #define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 133 #define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ 134 #define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ 135 #define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ 136 #define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ 137 #define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ 138 #define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge for Setup/Sample */ 139 #define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ 140 #define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ 141 #define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 142 #define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ 143 #define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ 144 #define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ 145 #define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ 146 #define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ 147 #define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ 148 #define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ 149 #define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ 150 #define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 151 #define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ 152 #define USART_CTRL_CSMA (0x1UL << 11) /**< Action on Slave-Select in Master Mode */ 153 #define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ 154 #define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ 155 #define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 156 #define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ 157 #define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ 158 #define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ 159 #define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ 160 #define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ 161 #define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ 162 #define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ 163 #define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ 164 #define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 165 #define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ 166 #define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ 167 #define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ 168 #define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ 169 #define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ 170 #define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ 171 #define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ 172 #define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ 173 #define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 174 #define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ 175 #define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter Output Invert */ 176 #define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ 177 #define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ 178 #define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 179 #define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ 180 #define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ 181 #define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ 182 #define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ 183 #define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 184 #define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ 185 #define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ 186 #define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ 187 #define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ 188 #define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 189 #define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ 190 #define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ 191 #define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ 192 #define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ 193 #define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 194 #define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ 195 #define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ 196 #define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ 197 #define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ 198 #define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 199 #define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ 200 #define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ 201 #define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ 202 #define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ 203 #define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 204 #define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ 205 #define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ 206 #define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ 207 #define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ 208 #define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 209 #define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ 210 #define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ 211 #define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ 212 #define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ 213 #define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 214 #define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ 215 #define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA on Error */ 216 #define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ 217 #define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ 218 #define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 219 #define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ 220 #define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX on Error */ 221 #define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ 222 #define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ 223 #define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 224 #define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ 225 #define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX on Error */ 226 #define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ 227 #define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ 228 #define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 229 #define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ 230 #define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */ 231 #define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ 232 #define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ 233 #define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 234 #define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ 235 #define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap in Double Accesses */ 236 #define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ 237 #define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ 238 #define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 239 #define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ 240 #define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ 241 #define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ 242 #define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ 243 #define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 244 #define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ 245 #define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ 246 #define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ 247 #define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ 248 #define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 249 #define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ 250 #define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */ 251 #define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ 252 #define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ 253 #define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ 254 #define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ 255 256 /* Bit fields for USART FRAME */ 257 #define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ 258 #define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ 259 #define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ 260 #define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ 261 #define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ 262 #define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ 263 #define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ 264 #define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ 265 #define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ 266 #define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ 267 #define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ 268 #define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ 269 #define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ 270 #define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ 271 #define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ 272 #define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ 273 #define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ 274 #define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ 275 #define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ 276 #define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ 277 #define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ 278 #define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ 279 #define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ 280 #define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ 281 #define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ 282 #define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ 283 #define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ 284 #define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ 285 #define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ 286 #define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ 287 #define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ 288 #define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ 289 #define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ 290 #define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ 291 #define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ 292 #define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ 293 #define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ 294 #define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ 295 #define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ 296 #define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ 297 #define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ 298 #define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ 299 #define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ 300 #define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ 301 #define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ 302 #define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ 303 #define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ 304 #define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ 305 #define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ 306 #define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ 307 #define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ 308 #define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ 309 #define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ 310 #define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ 311 312 /* Bit fields for USART TRIGCTRL */ 313 #define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ 314 #define _USART_TRIGCTRL_MASK 0x001F1FF0UL /**< Mask for USART_TRIGCTRL */ 315 #define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ 316 #define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ 317 #define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ 318 #define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ 319 #define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ 320 #define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ 321 #define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ 322 #define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ 323 #define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ 324 #define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ 325 #define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ 326 #define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ 327 #define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ 328 #define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ 329 #define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ 330 #define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP0VAL */ 331 #define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ 332 #define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ 333 #define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ 334 #define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ 335 #define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP1VAL */ 336 #define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ 337 #define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ 338 #define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ 339 #define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ 340 #define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger After RX End of Frame Plus TCMP2VAL */ 341 #define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ 342 #define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ 343 #define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ 344 #define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ 345 #define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL0 Baud-times */ 346 #define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ 347 #define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ 348 #define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ 349 #define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ 350 #define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL1 Baud-times */ 351 #define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ 352 #define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ 353 #define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ 354 #define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ 355 #define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger After TX End of Frame Plus TCMPVAL2 Baud-times */ 356 #define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ 357 #define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ 358 #define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ 359 #define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ 360 #define _USART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */ 361 #define _USART_TRIGCTRL_TSEL_MASK 0x1F0000UL /**< Bit mask for USART_TSEL */ 362 #define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ 363 #define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */ 364 #define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */ 365 #define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */ 366 #define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */ 367 #define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */ 368 #define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */ 369 #define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */ 370 #define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */ 371 #define _USART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_TRIGCTRL */ 372 #define _USART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_TRIGCTRL */ 373 #define _USART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_TRIGCTRL */ 374 #define _USART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_TRIGCTRL */ 375 #define _USART_TRIGCTRL_TSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for USART_TRIGCTRL */ 376 #define _USART_TRIGCTRL_TSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for USART_TRIGCTRL */ 377 #define _USART_TRIGCTRL_TSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for USART_TRIGCTRL */ 378 #define _USART_TRIGCTRL_TSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for USART_TRIGCTRL */ 379 #define _USART_TRIGCTRL_TSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for USART_TRIGCTRL */ 380 #define _USART_TRIGCTRL_TSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for USART_TRIGCTRL */ 381 #define _USART_TRIGCTRL_TSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for USART_TRIGCTRL */ 382 #define _USART_TRIGCTRL_TSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for USART_TRIGCTRL */ 383 #define _USART_TRIGCTRL_TSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for USART_TRIGCTRL */ 384 #define _USART_TRIGCTRL_TSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for USART_TRIGCTRL */ 385 #define _USART_TRIGCTRL_TSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for USART_TRIGCTRL */ 386 #define _USART_TRIGCTRL_TSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for USART_TRIGCTRL */ 387 #define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ 388 #define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */ 389 #define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */ 390 #define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */ 391 #define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */ 392 #define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */ 393 #define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */ 394 #define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */ 395 #define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */ 396 #define USART_TRIGCTRL_TSEL_PRSCH8 (_USART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for USART_TRIGCTRL */ 397 #define USART_TRIGCTRL_TSEL_PRSCH9 (_USART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for USART_TRIGCTRL */ 398 #define USART_TRIGCTRL_TSEL_PRSCH10 (_USART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for USART_TRIGCTRL */ 399 #define USART_TRIGCTRL_TSEL_PRSCH11 (_USART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for USART_TRIGCTRL */ 400 #define USART_TRIGCTRL_TSEL_PRSCH12 (_USART_TRIGCTRL_TSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for USART_TRIGCTRL */ 401 #define USART_TRIGCTRL_TSEL_PRSCH13 (_USART_TRIGCTRL_TSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for USART_TRIGCTRL */ 402 #define USART_TRIGCTRL_TSEL_PRSCH14 (_USART_TRIGCTRL_TSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for USART_TRIGCTRL */ 403 #define USART_TRIGCTRL_TSEL_PRSCH15 (_USART_TRIGCTRL_TSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for USART_TRIGCTRL */ 404 #define USART_TRIGCTRL_TSEL_PRSCH16 (_USART_TRIGCTRL_TSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for USART_TRIGCTRL */ 405 #define USART_TRIGCTRL_TSEL_PRSCH17 (_USART_TRIGCTRL_TSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for USART_TRIGCTRL */ 406 #define USART_TRIGCTRL_TSEL_PRSCH18 (_USART_TRIGCTRL_TSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for USART_TRIGCTRL */ 407 #define USART_TRIGCTRL_TSEL_PRSCH19 (_USART_TRIGCTRL_TSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for USART_TRIGCTRL */ 408 #define USART_TRIGCTRL_TSEL_PRSCH20 (_USART_TRIGCTRL_TSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for USART_TRIGCTRL */ 409 #define USART_TRIGCTRL_TSEL_PRSCH21 (_USART_TRIGCTRL_TSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for USART_TRIGCTRL */ 410 #define USART_TRIGCTRL_TSEL_PRSCH22 (_USART_TRIGCTRL_TSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for USART_TRIGCTRL */ 411 #define USART_TRIGCTRL_TSEL_PRSCH23 (_USART_TRIGCTRL_TSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for USART_TRIGCTRL */ 412 413 /* Bit fields for USART CMD */ 414 #define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ 415 #define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ 416 #define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ 417 #define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ 418 #define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ 419 #define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 420 #define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ 421 #define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ 422 #define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ 423 #define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ 424 #define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 425 #define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ 426 #define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ 427 #define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ 428 #define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ 429 #define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 430 #define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ 431 #define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ 432 #define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ 433 #define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ 434 #define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 435 #define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ 436 #define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */ 437 #define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ 438 #define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ 439 #define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 440 #define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ 441 #define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */ 442 #define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ 443 #define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ 444 #define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 445 #define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ 446 #define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ 447 #define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ 448 #define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ 449 #define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 450 #define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ 451 #define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ 452 #define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ 453 #define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ 454 #define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 455 #define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ 456 #define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ 457 #define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ 458 #define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ 459 #define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 460 #define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ 461 #define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ 462 #define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ 463 #define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ 464 #define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 465 #define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ 466 #define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ 467 #define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ 468 #define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ 469 #define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 470 #define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ 471 #define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ 472 #define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ 473 #define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ 474 #define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ 475 #define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ 476 477 /* Bit fields for USART STATUS */ 478 #define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ 479 #define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ 480 #define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ 481 #define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ 482 #define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ 483 #define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 484 #define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ 485 #define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ 486 #define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ 487 #define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ 488 #define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 489 #define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ 490 #define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */ 491 #define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ 492 #define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ 493 #define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 494 #define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ 495 #define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ 496 #define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ 497 #define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ 498 #define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 499 #define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ 500 #define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ 501 #define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ 502 #define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ 503 #define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 504 #define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ 505 #define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ 506 #define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ 507 #define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ 508 #define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 509 #define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ 510 #define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ 511 #define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ 512 #define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ 513 #define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ 514 #define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ 515 #define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ 516 #define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ 517 #define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ 518 #define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 519 #define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ 520 #define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ 521 #define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ 522 #define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ 523 #define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 524 #define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ 525 #define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ 526 #define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ 527 #define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ 528 #define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 529 #define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ 530 #define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ 531 #define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ 532 #define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ 533 #define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 534 #define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ 535 #define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ 536 #define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ 537 #define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ 538 #define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 539 #define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ 540 #define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ 541 #define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ 542 #define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ 543 #define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 544 #define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ 545 #define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ 546 #define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ 547 #define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ 548 #define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ 549 #define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ 550 #define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer Restarted Itself */ 551 #define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ 552 #define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ 553 #define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 554 #define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ 555 #define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ 556 #define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ 557 #define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ 558 #define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ 559 560 /* Bit fields for USART CLKDIV */ 561 #define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ 562 #define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ 563 #define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ 564 #define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ 565 #define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ 566 #define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ 567 #define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD Detection Enable */ 568 #define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ 569 #define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ 570 #define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ 571 #define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ 572 573 /* Bit fields for USART RXDATAX */ 574 #define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ 575 #define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ 576 #define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ 577 #define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ 578 #define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ 579 #define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ 580 #define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ 581 #define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ 582 #define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ 583 #define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ 584 #define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ 585 #define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ 586 #define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ 587 #define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ 588 #define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ 589 #define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ 590 591 /* Bit fields for USART RXDATA */ 592 #define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ 593 #define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ 594 #define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ 595 #define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ 596 #define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ 597 #define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ 598 599 /* Bit fields for USART RXDOUBLEX */ 600 #define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ 601 #define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ 602 #define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ 603 #define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ 604 #define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ 605 #define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ 606 #define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ 607 #define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ 608 #define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ 609 #define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ 610 #define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ 611 #define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ 612 #define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ 613 #define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ 614 #define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ 615 #define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ 616 #define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ 617 #define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ 618 #define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ 619 #define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ 620 #define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ 621 #define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ 622 #define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ 623 #define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ 624 #define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ 625 #define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ 626 #define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ 627 #define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ 628 #define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ 629 #define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ 630 631 /* Bit fields for USART RXDOUBLE */ 632 #define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ 633 #define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ 634 #define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ 635 #define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ 636 #define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ 637 #define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ 638 #define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ 639 #define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ 640 #define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ 641 #define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ 642 643 /* Bit fields for USART RXDATAXP */ 644 #define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ 645 #define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ 646 #define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ 647 #define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ 648 #define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ 649 #define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ 650 #define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ 651 #define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ 652 #define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ 653 #define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ 654 #define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ 655 #define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ 656 #define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ 657 #define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ 658 #define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ 659 #define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ 660 661 /* Bit fields for USART RXDOUBLEXP */ 662 #define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ 663 #define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ 664 #define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ 665 #define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ 666 #define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ 667 #define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ 668 #define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ 669 #define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ 670 #define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ 671 #define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ 672 #define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ 673 #define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ 674 #define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ 675 #define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ 676 #define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ 677 #define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ 678 #define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ 679 #define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ 680 #define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ 681 #define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ 682 #define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ 683 #define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ 684 #define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ 685 #define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ 686 #define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ 687 #define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ 688 #define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ 689 #define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ 690 #define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ 691 #define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ 692 693 /* Bit fields for USART TXDATAX */ 694 #define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ 695 #define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ 696 #define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ 697 #define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ 698 #define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ 699 #define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ 700 #define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ 701 #define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ 702 #define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ 703 #define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ 704 #define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ 705 #define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ 706 #define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ 707 #define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ 708 #define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ 709 #define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ 710 #define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */ 711 #define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ 712 #define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ 713 #define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ 714 #define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ 715 #define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ 716 #define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ 717 #define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ 718 #define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ 719 #define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ 720 #define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ 721 #define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ 722 #define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ 723 #define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ 724 #define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ 725 726 /* Bit fields for USART TXDATA */ 727 #define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ 728 #define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ 729 #define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ 730 #define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ 731 #define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ 732 #define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ 733 734 /* Bit fields for USART TXDOUBLEX */ 735 #define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ 736 #define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ 737 #define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ 738 #define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ 739 #define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 740 #define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 741 #define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ 742 #define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ 743 #define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ 744 #define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 745 #define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 746 #define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ 747 #define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ 748 #define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ 749 #define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 750 #define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 751 #define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data as Break */ 752 #define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ 753 #define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ 754 #define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 755 #define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 756 #define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ 757 #define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ 758 #define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ 759 #define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 760 #define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 761 #define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ 762 #define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ 763 #define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ 764 #define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 765 #define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 766 #define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ 767 #define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ 768 #define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 769 #define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 770 #define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ 771 #define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ 772 #define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ 773 #define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 774 #define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 775 #define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ 776 #define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ 777 #define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ 778 #define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 779 #define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 780 #define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data as Break */ 781 #define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ 782 #define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ 783 #define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 784 #define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 785 #define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ 786 #define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ 787 #define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ 788 #define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 789 #define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 790 #define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ 791 #define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ 792 #define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ 793 #define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ 794 #define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ 795 796 /* Bit fields for USART TXDOUBLE */ 797 #define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ 798 #define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ 799 #define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ 800 #define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ 801 #define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ 802 #define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ 803 #define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ 804 #define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ 805 #define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ 806 #define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ 807 808 /* Bit fields for USART IF */ 809 #define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ 810 #define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ 811 #define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ 812 #define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ 813 #define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ 814 #define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 815 #define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ 816 #define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ 817 #define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ 818 #define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ 819 #define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ 820 #define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ 821 #define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ 822 #define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ 823 #define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ 824 #define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 825 #define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ 826 #define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ 827 #define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ 828 #define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ 829 #define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 830 #define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ 831 #define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ 832 #define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ 833 #define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ 834 #define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 835 #define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ 836 #define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ 837 #define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ 838 #define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ 839 #define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 840 #define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ 841 #define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ 842 #define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ 843 #define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ 844 #define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 845 #define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ 846 #define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ 847 #define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ 848 #define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ 849 #define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 850 #define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ 851 #define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ 852 #define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ 853 #define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ 854 #define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 855 #define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ 856 #define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ 857 #define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ 858 #define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ 859 #define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 860 #define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ 861 #define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */ 862 #define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ 863 #define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ 864 #define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 865 #define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ 866 #define USART_IF_SSM (0x1UL << 11) /**< Slave-Select in Master Mode Interrupt Flag */ 867 #define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ 868 #define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ 869 #define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 870 #define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ 871 #define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ 872 #define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ 873 #define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ 874 #define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 875 #define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ 876 #define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ 877 #define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ 878 #define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ 879 #define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 880 #define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ 881 #define USART_IF_TCMP0 (0x1UL << 14) /**< Timer Comparator 0 Interrupt Flag */ 882 #define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ 883 #define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ 884 #define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 885 #define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ 886 #define USART_IF_TCMP1 (0x1UL << 15) /**< Timer Comparator 1 Interrupt Flag */ 887 #define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ 888 #define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ 889 #define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 890 #define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ 891 #define USART_IF_TCMP2 (0x1UL << 16) /**< Timer Comparator 2 Interrupt Flag */ 892 #define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ 893 #define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ 894 #define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ 895 #define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ 896 897 /* Bit fields for USART IFS */ 898 #define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */ 899 #define _USART_IFS_MASK 0x0001FFF9UL /**< Mask for USART_IFS */ 900 #define USART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ 901 #define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */ 902 #define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ 903 #define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 904 #define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */ 905 #define USART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */ 906 #define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ 907 #define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ 908 #define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 909 #define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */ 910 #define USART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */ 911 #define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ 912 #define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ 913 #define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 914 #define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */ 915 #define USART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */ 916 #define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ 917 #define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ 918 #define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 919 #define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */ 920 #define USART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */ 921 #define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ 922 #define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ 923 #define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 924 #define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */ 925 #define USART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */ 926 #define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ 927 #define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ 928 #define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 929 #define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */ 930 #define USART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */ 931 #define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */ 932 #define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ 933 #define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 934 #define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */ 935 #define USART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */ 936 #define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */ 937 #define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ 938 #define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 939 #define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */ 940 #define USART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */ 941 #define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ 942 #define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ 943 #define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 944 #define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */ 945 #define USART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */ 946 #define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */ 947 #define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ 948 #define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 949 #define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */ 950 #define USART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */ 951 #define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */ 952 #define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ 953 #define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 954 #define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */ 955 #define USART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */ 956 #define _USART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ 957 #define _USART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ 958 #define _USART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 959 #define USART_IFS_TXIDLE_DEFAULT (_USART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFS */ 960 #define USART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */ 961 #define _USART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ 962 #define _USART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ 963 #define _USART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 964 #define USART_IFS_TCMP0_DEFAULT (_USART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFS */ 965 #define USART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */ 966 #define _USART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ 967 #define _USART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ 968 #define _USART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 969 #define USART_IFS_TCMP1_DEFAULT (_USART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFS */ 970 #define USART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */ 971 #define _USART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ 972 #define _USART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ 973 #define _USART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ 974 #define USART_IFS_TCMP2_DEFAULT (_USART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFS */ 975 976 /* Bit fields for USART IFC */ 977 #define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */ 978 #define _USART_IFC_MASK 0x0001FFF9UL /**< Mask for USART_IFC */ 979 #define USART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ 980 #define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */ 981 #define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ 982 #define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 983 #define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */ 984 #define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */ 985 #define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ 986 #define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ 987 #define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 988 #define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */ 989 #define USART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */ 990 #define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ 991 #define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ 992 #define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 993 #define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */ 994 #define USART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */ 995 #define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ 996 #define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ 997 #define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 998 #define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */ 999 #define USART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */ 1000 #define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ 1001 #define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ 1002 #define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 1003 #define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */ 1004 #define USART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */ 1005 #define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ 1006 #define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ 1007 #define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 1008 #define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */ 1009 #define USART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */ 1010 #define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */ 1011 #define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ 1012 #define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 1013 #define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */ 1014 #define USART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */ 1015 #define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */ 1016 #define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ 1017 #define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 1018 #define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */ 1019 #define USART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */ 1020 #define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ 1021 #define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ 1022 #define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 1023 #define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */ 1024 #define USART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */ 1025 #define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */ 1026 #define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ 1027 #define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 1028 #define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */ 1029 #define USART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */ 1030 #define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */ 1031 #define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ 1032 #define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 1033 #define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */ 1034 #define USART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */ 1035 #define _USART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ 1036 #define _USART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ 1037 #define _USART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 1038 #define USART_IFC_TXIDLE_DEFAULT (_USART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFC */ 1039 #define USART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */ 1040 #define _USART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ 1041 #define _USART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ 1042 #define _USART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 1043 #define USART_IFC_TCMP0_DEFAULT (_USART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFC */ 1044 #define USART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */ 1045 #define _USART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ 1046 #define _USART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ 1047 #define _USART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 1048 #define USART_IFC_TCMP1_DEFAULT (_USART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFC */ 1049 #define USART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */ 1050 #define _USART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ 1051 #define _USART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ 1052 #define _USART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ 1053 #define USART_IFC_TCMP2_DEFAULT (_USART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFC */ 1054 1055 /* Bit fields for USART IEN */ 1056 #define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ 1057 #define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ 1058 #define USART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ 1059 #define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ 1060 #define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ 1061 #define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1062 #define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ 1063 #define USART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ 1064 #define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ 1065 #define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ 1066 #define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1067 #define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ 1068 #define USART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ 1069 #define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ 1070 #define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ 1071 #define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1072 #define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ 1073 #define USART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */ 1074 #define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ 1075 #define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ 1076 #define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1077 #define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ 1078 #define USART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */ 1079 #define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ 1080 #define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ 1081 #define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1082 #define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ 1083 #define USART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */ 1084 #define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ 1085 #define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ 1086 #define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1087 #define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ 1088 #define USART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */ 1089 #define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ 1090 #define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ 1091 #define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1092 #define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ 1093 #define USART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */ 1094 #define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ 1095 #define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ 1096 #define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1097 #define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ 1098 #define USART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */ 1099 #define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ 1100 #define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ 1101 #define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1102 #define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ 1103 #define USART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */ 1104 #define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ 1105 #define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ 1106 #define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1107 #define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ 1108 #define USART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */ 1109 #define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ 1110 #define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ 1111 #define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1112 #define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ 1113 #define USART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */ 1114 #define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ 1115 #define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ 1116 #define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1117 #define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ 1118 #define USART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */ 1119 #define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ 1120 #define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ 1121 #define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1122 #define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ 1123 #define USART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */ 1124 #define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ 1125 #define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ 1126 #define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1127 #define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ 1128 #define USART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */ 1129 #define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ 1130 #define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ 1131 #define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1132 #define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ 1133 #define USART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */ 1134 #define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ 1135 #define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ 1136 #define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1137 #define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ 1138 #define USART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */ 1139 #define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ 1140 #define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ 1141 #define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ 1142 #define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ 1143 1144 /* Bit fields for USART IRCTRL */ 1145 #define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ 1146 #define _USART_IRCTRL_MASK 0x00001F8FUL /**< Mask for USART_IRCTRL */ 1147 #define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ 1148 #define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ 1149 #define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ 1150 #define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ 1151 #define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ 1152 #define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ 1153 #define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ 1154 #define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ 1155 #define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ 1156 #define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ 1157 #define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ 1158 #define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ 1159 #define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ 1160 #define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ 1161 #define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ 1162 #define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ 1163 #define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ 1164 #define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ 1165 #define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ 1166 #define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ 1167 #define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ 1168 #define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ 1169 #define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */ 1170 #define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */ 1171 #define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */ 1172 #define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ 1173 #define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */ 1174 #define _USART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */ 1175 #define _USART_IRCTRL_IRPRSSEL_MASK 0x1F00UL /**< Bit mask for USART_IRPRSSEL */ 1176 #define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ 1177 #define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */ 1178 #define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */ 1179 #define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */ 1180 #define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */ 1181 #define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */ 1182 #define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */ 1183 #define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */ 1184 #define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */ 1185 #define _USART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_IRCTRL */ 1186 #define _USART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_IRCTRL */ 1187 #define _USART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_IRCTRL */ 1188 #define _USART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_IRCTRL */ 1189 #define _USART_IRCTRL_IRPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for USART_IRCTRL */ 1190 #define _USART_IRCTRL_IRPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for USART_IRCTRL */ 1191 #define _USART_IRCTRL_IRPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for USART_IRCTRL */ 1192 #define _USART_IRCTRL_IRPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for USART_IRCTRL */ 1193 #define _USART_IRCTRL_IRPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for USART_IRCTRL */ 1194 #define _USART_IRCTRL_IRPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for USART_IRCTRL */ 1195 #define _USART_IRCTRL_IRPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for USART_IRCTRL */ 1196 #define _USART_IRCTRL_IRPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for USART_IRCTRL */ 1197 #define _USART_IRCTRL_IRPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for USART_IRCTRL */ 1198 #define _USART_IRCTRL_IRPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for USART_IRCTRL */ 1199 #define _USART_IRCTRL_IRPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for USART_IRCTRL */ 1200 #define _USART_IRCTRL_IRPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for USART_IRCTRL */ 1201 #define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IRCTRL */ 1202 #define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_IRCTRL */ 1203 #define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_IRCTRL */ 1204 #define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_IRCTRL */ 1205 #define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_IRCTRL */ 1206 #define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_IRCTRL */ 1207 #define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_IRCTRL */ 1208 #define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_IRCTRL */ 1209 #define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_IRCTRL */ 1210 #define USART_IRCTRL_IRPRSSEL_PRSCH8 (_USART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_IRCTRL */ 1211 #define USART_IRCTRL_IRPRSSEL_PRSCH9 (_USART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_IRCTRL */ 1212 #define USART_IRCTRL_IRPRSSEL_PRSCH10 (_USART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_IRCTRL */ 1213 #define USART_IRCTRL_IRPRSSEL_PRSCH11 (_USART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_IRCTRL */ 1214 #define USART_IRCTRL_IRPRSSEL_PRSCH12 (_USART_IRCTRL_IRPRSSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for USART_IRCTRL */ 1215 #define USART_IRCTRL_IRPRSSEL_PRSCH13 (_USART_IRCTRL_IRPRSSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for USART_IRCTRL */ 1216 #define USART_IRCTRL_IRPRSSEL_PRSCH14 (_USART_IRCTRL_IRPRSSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for USART_IRCTRL */ 1217 #define USART_IRCTRL_IRPRSSEL_PRSCH15 (_USART_IRCTRL_IRPRSSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for USART_IRCTRL */ 1218 #define USART_IRCTRL_IRPRSSEL_PRSCH16 (_USART_IRCTRL_IRPRSSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for USART_IRCTRL */ 1219 #define USART_IRCTRL_IRPRSSEL_PRSCH17 (_USART_IRCTRL_IRPRSSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for USART_IRCTRL */ 1220 #define USART_IRCTRL_IRPRSSEL_PRSCH18 (_USART_IRCTRL_IRPRSSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for USART_IRCTRL */ 1221 #define USART_IRCTRL_IRPRSSEL_PRSCH19 (_USART_IRCTRL_IRPRSSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for USART_IRCTRL */ 1222 #define USART_IRCTRL_IRPRSSEL_PRSCH20 (_USART_IRCTRL_IRPRSSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for USART_IRCTRL */ 1223 #define USART_IRCTRL_IRPRSSEL_PRSCH21 (_USART_IRCTRL_IRPRSSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for USART_IRCTRL */ 1224 #define USART_IRCTRL_IRPRSSEL_PRSCH22 (_USART_IRCTRL_IRPRSSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for USART_IRCTRL */ 1225 #define USART_IRCTRL_IRPRSSEL_PRSCH23 (_USART_IRCTRL_IRPRSSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for USART_IRCTRL */ 1226 1227 /* Bit fields for USART INPUT */ 1228 #define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */ 1229 #define _USART_INPUT_MASK 0x00009F9FUL /**< Mask for USART_INPUT */ 1230 #define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */ 1231 #define _USART_INPUT_RXPRSSEL_MASK 0x1FUL /**< Bit mask for USART_RXPRSSEL */ 1232 #define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ 1233 #define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ 1234 #define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ 1235 #define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ 1236 #define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ 1237 #define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ 1238 #define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ 1239 #define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ 1240 #define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ 1241 #define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ 1242 #define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ 1243 #define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ 1244 #define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ 1245 #define _USART_INPUT_RXPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for USART_INPUT */ 1246 #define _USART_INPUT_RXPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for USART_INPUT */ 1247 #define _USART_INPUT_RXPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for USART_INPUT */ 1248 #define _USART_INPUT_RXPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for USART_INPUT */ 1249 #define _USART_INPUT_RXPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for USART_INPUT */ 1250 #define _USART_INPUT_RXPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for USART_INPUT */ 1251 #define _USART_INPUT_RXPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for USART_INPUT */ 1252 #define _USART_INPUT_RXPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for USART_INPUT */ 1253 #define _USART_INPUT_RXPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for USART_INPUT */ 1254 #define _USART_INPUT_RXPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for USART_INPUT */ 1255 #define _USART_INPUT_RXPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for USART_INPUT */ 1256 #define _USART_INPUT_RXPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for USART_INPUT */ 1257 #define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */ 1258 #define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */ 1259 #define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */ 1260 #define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */ 1261 #define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */ 1262 #define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */ 1263 #define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */ 1264 #define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */ 1265 #define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */ 1266 #define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */ 1267 #define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */ 1268 #define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */ 1269 #define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */ 1270 #define USART_INPUT_RXPRSSEL_PRSCH12 (_USART_INPUT_RXPRSSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for USART_INPUT */ 1271 #define USART_INPUT_RXPRSSEL_PRSCH13 (_USART_INPUT_RXPRSSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for USART_INPUT */ 1272 #define USART_INPUT_RXPRSSEL_PRSCH14 (_USART_INPUT_RXPRSSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for USART_INPUT */ 1273 #define USART_INPUT_RXPRSSEL_PRSCH15 (_USART_INPUT_RXPRSSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for USART_INPUT */ 1274 #define USART_INPUT_RXPRSSEL_PRSCH16 (_USART_INPUT_RXPRSSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for USART_INPUT */ 1275 #define USART_INPUT_RXPRSSEL_PRSCH17 (_USART_INPUT_RXPRSSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for USART_INPUT */ 1276 #define USART_INPUT_RXPRSSEL_PRSCH18 (_USART_INPUT_RXPRSSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for USART_INPUT */ 1277 #define USART_INPUT_RXPRSSEL_PRSCH19 (_USART_INPUT_RXPRSSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for USART_INPUT */ 1278 #define USART_INPUT_RXPRSSEL_PRSCH20 (_USART_INPUT_RXPRSSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for USART_INPUT */ 1279 #define USART_INPUT_RXPRSSEL_PRSCH21 (_USART_INPUT_RXPRSSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for USART_INPUT */ 1280 #define USART_INPUT_RXPRSSEL_PRSCH22 (_USART_INPUT_RXPRSSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for USART_INPUT */ 1281 #define USART_INPUT_RXPRSSEL_PRSCH23 (_USART_INPUT_RXPRSSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for USART_INPUT */ 1282 #define USART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */ 1283 #define _USART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */ 1284 #define _USART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */ 1285 #define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ 1286 #define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_INPUT */ 1287 #define _USART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */ 1288 #define _USART_INPUT_CLKPRSSEL_MASK 0x1F00UL /**< Bit mask for USART_CLKPRSSEL */ 1289 #define _USART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ 1290 #define _USART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ 1291 #define _USART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ 1292 #define _USART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ 1293 #define _USART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ 1294 #define _USART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ 1295 #define _USART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ 1296 #define _USART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ 1297 #define _USART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ 1298 #define _USART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ 1299 #define _USART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ 1300 #define _USART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ 1301 #define _USART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ 1302 #define _USART_INPUT_CLKPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for USART_INPUT */ 1303 #define _USART_INPUT_CLKPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for USART_INPUT */ 1304 #define _USART_INPUT_CLKPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for USART_INPUT */ 1305 #define _USART_INPUT_CLKPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for USART_INPUT */ 1306 #define _USART_INPUT_CLKPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for USART_INPUT */ 1307 #define _USART_INPUT_CLKPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for USART_INPUT */ 1308 #define _USART_INPUT_CLKPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for USART_INPUT */ 1309 #define _USART_INPUT_CLKPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for USART_INPUT */ 1310 #define _USART_INPUT_CLKPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for USART_INPUT */ 1311 #define _USART_INPUT_CLKPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for USART_INPUT */ 1312 #define _USART_INPUT_CLKPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for USART_INPUT */ 1313 #define _USART_INPUT_CLKPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for USART_INPUT */ 1314 #define USART_INPUT_CLKPRSSEL_DEFAULT (_USART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_INPUT */ 1315 #define USART_INPUT_CLKPRSSEL_PRSCH0 (_USART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_INPUT */ 1316 #define USART_INPUT_CLKPRSSEL_PRSCH1 (_USART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_INPUT */ 1317 #define USART_INPUT_CLKPRSSEL_PRSCH2 (_USART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_INPUT */ 1318 #define USART_INPUT_CLKPRSSEL_PRSCH3 (_USART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_INPUT */ 1319 #define USART_INPUT_CLKPRSSEL_PRSCH4 (_USART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_INPUT */ 1320 #define USART_INPUT_CLKPRSSEL_PRSCH5 (_USART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_INPUT */ 1321 #define USART_INPUT_CLKPRSSEL_PRSCH6 (_USART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_INPUT */ 1322 #define USART_INPUT_CLKPRSSEL_PRSCH7 (_USART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_INPUT */ 1323 #define USART_INPUT_CLKPRSSEL_PRSCH8 (_USART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_INPUT */ 1324 #define USART_INPUT_CLKPRSSEL_PRSCH9 (_USART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_INPUT */ 1325 #define USART_INPUT_CLKPRSSEL_PRSCH10 (_USART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_INPUT */ 1326 #define USART_INPUT_CLKPRSSEL_PRSCH11 (_USART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_INPUT */ 1327 #define USART_INPUT_CLKPRSSEL_PRSCH12 (_USART_INPUT_CLKPRSSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for USART_INPUT */ 1328 #define USART_INPUT_CLKPRSSEL_PRSCH13 (_USART_INPUT_CLKPRSSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for USART_INPUT */ 1329 #define USART_INPUT_CLKPRSSEL_PRSCH14 (_USART_INPUT_CLKPRSSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for USART_INPUT */ 1330 #define USART_INPUT_CLKPRSSEL_PRSCH15 (_USART_INPUT_CLKPRSSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for USART_INPUT */ 1331 #define USART_INPUT_CLKPRSSEL_PRSCH16 (_USART_INPUT_CLKPRSSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for USART_INPUT */ 1332 #define USART_INPUT_CLKPRSSEL_PRSCH17 (_USART_INPUT_CLKPRSSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for USART_INPUT */ 1333 #define USART_INPUT_CLKPRSSEL_PRSCH18 (_USART_INPUT_CLKPRSSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for USART_INPUT */ 1334 #define USART_INPUT_CLKPRSSEL_PRSCH19 (_USART_INPUT_CLKPRSSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for USART_INPUT */ 1335 #define USART_INPUT_CLKPRSSEL_PRSCH20 (_USART_INPUT_CLKPRSSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for USART_INPUT */ 1336 #define USART_INPUT_CLKPRSSEL_PRSCH21 (_USART_INPUT_CLKPRSSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for USART_INPUT */ 1337 #define USART_INPUT_CLKPRSSEL_PRSCH22 (_USART_INPUT_CLKPRSSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for USART_INPUT */ 1338 #define USART_INPUT_CLKPRSSEL_PRSCH23 (_USART_INPUT_CLKPRSSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for USART_INPUT */ 1339 #define USART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */ 1340 #define _USART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */ 1341 #define _USART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */ 1342 #define _USART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ 1343 #define USART_INPUT_CLKPRS_DEFAULT (_USART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_INPUT */ 1344 1345 /* Bit fields for USART I2SCTRL */ 1346 #define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ 1347 #define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ 1348 #define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ 1349 #define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ 1350 #define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ 1351 #define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ 1352 #define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ 1353 #define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ 1354 #define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ 1355 #define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ 1356 #define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ 1357 #define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ 1358 #define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ 1359 #define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ 1360 #define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ 1361 #define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ 1362 #define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ 1363 #define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ 1364 #define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ 1365 #define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ 1366 #define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ 1367 #define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request for Left/Right Data */ 1368 #define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ 1369 #define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ 1370 #define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ 1371 #define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ 1372 #define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S Data */ 1373 #define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ 1374 #define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ 1375 #define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ 1376 #define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ 1377 #define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ 1378 #define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ 1379 #define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ 1380 #define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ 1381 #define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ 1382 #define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ 1383 #define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ 1384 #define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ 1385 #define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ 1386 #define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ 1387 #define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ 1388 #define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ 1389 #define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ 1390 #define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ 1391 #define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ 1392 #define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ 1393 #define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ 1394 #define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ 1395 #define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ 1396 #define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ 1397 1398 /* Bit fields for USART TIMING */ 1399 #define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ 1400 #define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ 1401 #define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ 1402 #define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ 1403 #define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ 1404 #define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ 1405 #define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ 1406 #define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ 1407 #define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ 1408 #define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ 1409 #define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ 1410 #define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ 1411 #define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ 1412 #define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ 1413 #define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ 1414 #define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ 1415 #define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ 1416 #define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ 1417 #define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ 1418 #define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ 1419 #define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ 1420 #define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ 1421 #define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ 1422 #define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ 1423 #define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ 1424 #define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ 1425 #define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ 1426 #define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ 1427 #define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ 1428 #define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ 1429 #define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ 1430 #define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ 1431 #define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ 1432 #define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ 1433 #define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ 1434 #define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ 1435 #define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ 1436 #define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ 1437 #define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ 1438 #define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ 1439 #define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ 1440 #define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ 1441 #define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ 1442 #define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ 1443 #define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ 1444 #define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ 1445 #define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ 1446 #define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ 1447 #define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ 1448 #define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ 1449 #define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ 1450 #define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ 1451 #define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ 1452 #define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ 1453 #define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ 1454 #define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ 1455 #define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ 1456 #define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ 1457 #define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ 1458 #define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ 1459 #define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ 1460 #define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ 1461 #define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ 1462 #define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ 1463 #define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ 1464 #define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ 1465 #define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ 1466 #define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ 1467 #define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ 1468 #define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ 1469 #define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ 1470 #define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ 1471 #define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ 1472 #define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ 1473 #define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ 1474 #define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ 1475 #define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ 1476 #define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ 1477 #define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ 1478 #define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ 1479 #define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ 1480 #define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ 1481 1482 /* Bit fields for USART CTRLX */ 1483 #define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ 1484 #define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */ 1485 #define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug Halt */ 1486 #define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ 1487 #define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ 1488 #define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ 1489 #define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ 1490 #define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ 1491 #define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ 1492 #define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ 1493 #define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ 1494 #define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ 1495 #define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function Enabled */ 1496 #define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ 1497 #define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ 1498 #define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ 1499 #define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ 1500 #define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ 1501 #define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ 1502 #define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ 1503 #define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ 1504 #define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ 1505 1506 /* Bit fields for USART TIMECMP0 */ 1507 #define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ 1508 #define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ 1509 #define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ 1510 #define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ 1511 #define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ 1512 #define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ 1513 #define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ 1514 #define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ 1515 #define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ 1516 #define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ 1517 #define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ 1518 #define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ 1519 #define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ 1520 #define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ 1521 #define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ 1522 #define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ 1523 #define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ 1524 #define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ 1525 #define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ 1526 #define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ 1527 #define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ 1528 #define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ 1529 #define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ 1530 #define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ 1531 #define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ 1532 #define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ 1533 #define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ 1534 #define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ 1535 #define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ 1536 #define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ 1537 #define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ 1538 #define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ 1539 #define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ 1540 #define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ 1541 #define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ 1542 #define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ 1543 #define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ 1544 1545 /* Bit fields for USART TIMECMP1 */ 1546 #define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ 1547 #define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ 1548 #define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ 1549 #define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ 1550 #define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ 1551 #define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ 1552 #define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ 1553 #define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ 1554 #define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ 1555 #define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ 1556 #define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ 1557 #define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ 1558 #define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ 1559 #define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ 1560 #define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ 1561 #define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ 1562 #define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ 1563 #define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ 1564 #define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ 1565 #define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ 1566 #define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ 1567 #define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ 1568 #define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ 1569 #define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ 1570 #define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ 1571 #define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ 1572 #define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ 1573 #define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ 1574 #define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ 1575 #define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ 1576 #define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ 1577 #define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ 1578 #define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ 1579 #define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ 1580 #define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ 1581 #define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ 1582 #define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ 1583 1584 /* Bit fields for USART TIMECMP2 */ 1585 #define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ 1586 #define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ 1587 #define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ 1588 #define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ 1589 #define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ 1590 #define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ 1591 #define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ 1592 #define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ 1593 #define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ 1594 #define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ 1595 #define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ 1596 #define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ 1597 #define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ 1598 #define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ 1599 #define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ 1600 #define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ 1601 #define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ 1602 #define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ 1603 #define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ 1604 #define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ 1605 #define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ 1606 #define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ 1607 #define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ 1608 #define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ 1609 #define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ 1610 #define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ 1611 #define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ 1612 #define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ 1613 #define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ 1614 #define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ 1615 #define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ 1616 #define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ 1617 #define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ 1618 #define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ 1619 #define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ 1620 #define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ 1621 #define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ 1622 1623 /* Bit fields for USART ROUTEPEN */ 1624 #define _USART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTEPEN */ 1625 #define _USART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for USART_ROUTEPEN */ 1626 #define USART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ 1627 #define _USART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */ 1628 #define _USART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */ 1629 #define _USART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ 1630 #define USART_ROUTEPEN_RXPEN_DEFAULT (_USART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ 1631 #define USART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ 1632 #define _USART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */ 1633 #define _USART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */ 1634 #define _USART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ 1635 #define USART_ROUTEPEN_TXPEN_DEFAULT (_USART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ 1636 #define USART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */ 1637 #define _USART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */ 1638 #define _USART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */ 1639 #define _USART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ 1640 #define USART_ROUTEPEN_CSPEN_DEFAULT (_USART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ 1641 #define USART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */ 1642 #define _USART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */ 1643 #define _USART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */ 1644 #define _USART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ 1645 #define USART_ROUTEPEN_CLKPEN_DEFAULT (_USART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ 1646 #define USART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */ 1647 #define _USART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */ 1648 #define _USART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */ 1649 #define _USART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ 1650 #define USART_ROUTEPEN_CTSPEN_DEFAULT (_USART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ 1651 #define USART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */ 1652 #define _USART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */ 1653 #define _USART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */ 1654 #define _USART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ 1655 #define USART_ROUTEPEN_RTSPEN_DEFAULT (_USART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ 1656 1657 /* Bit fields for USART ROUTELOC0 */ 1658 #define _USART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC0 */ 1659 #define _USART_ROUTELOC0_MASK 0x07070707UL /**< Mask for USART_ROUTELOC0 */ 1660 #define _USART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */ 1661 #define _USART_ROUTELOC0_RXLOC_MASK 0x7UL /**< Bit mask for USART_RXLOC */ 1662 #define _USART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ 1663 #define _USART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ 1664 #define _USART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ 1665 #define _USART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ 1666 #define _USART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ 1667 #define _USART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ 1668 #define _USART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ 1669 #define _USART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ 1670 #define USART_ROUTELOC0_RXLOC_LOC0 (_USART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ 1671 #define USART_ROUTELOC0_RXLOC_DEFAULT (_USART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ 1672 #define USART_ROUTELOC0_RXLOC_LOC1 (_USART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ 1673 #define USART_ROUTELOC0_RXLOC_LOC2 (_USART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ 1674 #define USART_ROUTELOC0_RXLOC_LOC3 (_USART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ 1675 #define USART_ROUTELOC0_RXLOC_LOC4 (_USART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ 1676 #define USART_ROUTELOC0_RXLOC_LOC5 (_USART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ 1677 #define USART_ROUTELOC0_RXLOC_LOC6 (_USART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ 1678 #define _USART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */ 1679 #define _USART_ROUTELOC0_TXLOC_MASK 0x700UL /**< Bit mask for USART_TXLOC */ 1680 #define _USART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ 1681 #define _USART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ 1682 #define _USART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ 1683 #define _USART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ 1684 #define _USART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ 1685 #define _USART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ 1686 #define _USART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ 1687 #define _USART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ 1688 #define USART_ROUTELOC0_TXLOC_LOC0 (_USART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ 1689 #define USART_ROUTELOC0_TXLOC_DEFAULT (_USART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ 1690 #define USART_ROUTELOC0_TXLOC_LOC1 (_USART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ 1691 #define USART_ROUTELOC0_TXLOC_LOC2 (_USART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ 1692 #define USART_ROUTELOC0_TXLOC_LOC3 (_USART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ 1693 #define USART_ROUTELOC0_TXLOC_LOC4 (_USART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ 1694 #define USART_ROUTELOC0_TXLOC_LOC5 (_USART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ 1695 #define USART_ROUTELOC0_TXLOC_LOC6 (_USART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ 1696 #define _USART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */ 1697 #define _USART_ROUTELOC0_CSLOC_MASK 0x70000UL /**< Bit mask for USART_CSLOC */ 1698 #define _USART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ 1699 #define _USART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ 1700 #define _USART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ 1701 #define _USART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ 1702 #define _USART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ 1703 #define _USART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ 1704 #define _USART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ 1705 #define _USART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ 1706 #define USART_ROUTELOC0_CSLOC_LOC0 (_USART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ 1707 #define USART_ROUTELOC0_CSLOC_DEFAULT (_USART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ 1708 #define USART_ROUTELOC0_CSLOC_LOC1 (_USART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ 1709 #define USART_ROUTELOC0_CSLOC_LOC2 (_USART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ 1710 #define USART_ROUTELOC0_CSLOC_LOC3 (_USART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ 1711 #define USART_ROUTELOC0_CSLOC_LOC4 (_USART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ 1712 #define USART_ROUTELOC0_CSLOC_LOC5 (_USART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ 1713 #define USART_ROUTELOC0_CSLOC_LOC6 (_USART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ 1714 #define _USART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */ 1715 #define _USART_ROUTELOC0_CLKLOC_MASK 0x7000000UL /**< Bit mask for USART_CLKLOC */ 1716 #define _USART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ 1717 #define _USART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ 1718 #define _USART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ 1719 #define _USART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ 1720 #define _USART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ 1721 #define _USART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ 1722 #define _USART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ 1723 #define _USART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ 1724 #define USART_ROUTELOC0_CLKLOC_LOC0 (_USART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ 1725 #define USART_ROUTELOC0_CLKLOC_DEFAULT (_USART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ 1726 #define USART_ROUTELOC0_CLKLOC_LOC1 (_USART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ 1727 #define USART_ROUTELOC0_CLKLOC_LOC2 (_USART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ 1728 #define USART_ROUTELOC0_CLKLOC_LOC3 (_USART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ 1729 #define USART_ROUTELOC0_CLKLOC_LOC4 (_USART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ 1730 #define USART_ROUTELOC0_CLKLOC_LOC5 (_USART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ 1731 #define USART_ROUTELOC0_CLKLOC_LOC6 (_USART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ 1732 1733 /* Bit fields for USART ROUTELOC1 */ 1734 #define _USART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC1 */ 1735 #define _USART_ROUTELOC1_MASK 0x00000707UL /**< Mask for USART_ROUTELOC1 */ 1736 #define _USART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */ 1737 #define _USART_ROUTELOC1_CTSLOC_MASK 0x7UL /**< Bit mask for USART_CTSLOC */ 1738 #define _USART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ 1739 #define _USART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ 1740 #define _USART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ 1741 #define _USART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ 1742 #define _USART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ 1743 #define _USART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ 1744 #define _USART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ 1745 #define _USART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ 1746 #define USART_ROUTELOC1_CTSLOC_LOC0 (_USART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ 1747 #define USART_ROUTELOC1_CTSLOC_DEFAULT (_USART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ 1748 #define USART_ROUTELOC1_CTSLOC_LOC1 (_USART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ 1749 #define USART_ROUTELOC1_CTSLOC_LOC2 (_USART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ 1750 #define USART_ROUTELOC1_CTSLOC_LOC3 (_USART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ 1751 #define USART_ROUTELOC1_CTSLOC_LOC4 (_USART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ 1752 #define USART_ROUTELOC1_CTSLOC_LOC5 (_USART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ 1753 #define USART_ROUTELOC1_CTSLOC_LOC6 (_USART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ 1754 #define _USART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */ 1755 #define _USART_ROUTELOC1_RTSLOC_MASK 0x700UL /**< Bit mask for USART_RTSLOC */ 1756 #define _USART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ 1757 #define _USART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ 1758 #define _USART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ 1759 #define _USART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ 1760 #define _USART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ 1761 #define _USART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ 1762 #define _USART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ 1763 #define _USART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ 1764 #define USART_ROUTELOC1_RTSLOC_LOC0 (_USART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ 1765 #define USART_ROUTELOC1_RTSLOC_DEFAULT (_USART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ 1766 #define USART_ROUTELOC1_RTSLOC_LOC1 (_USART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ 1767 #define USART_ROUTELOC1_RTSLOC_LOC2 (_USART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ 1768 #define USART_ROUTELOC1_RTSLOC_LOC3 (_USART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ 1769 #define USART_ROUTELOC1_RTSLOC_LOC4 (_USART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ 1770 #define USART_ROUTELOC1_RTSLOC_LOC5 (_USART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ 1771 #define USART_ROUTELOC1_RTSLOC_LOC6 (_USART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ 1772 1773 /** @} */ 1774 /** @} End of group EFM32GG11B_USART */ 1775 /** @} End of group Parts */ 1776
