1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG11B_QSPI register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG11B_QSPI QSPI 43 * @{ 44 * @brief EFM32GG11B_QSPI Register Declaration 45 ******************************************************************************/ 46 /** QSPI Register Declaration */ 47 typedef struct { 48 __IOM uint32_t CONFIG; /**< Octal-SPI Configuration Register */ 49 __IOM uint32_t DEVINSTRRDCONFIG; /**< Device Read Instruction Configuration Register */ 50 __IOM uint32_t DEVINSTRWRCONFIG; /**< Device Write Instruction Configuration Register */ 51 __IOM uint32_t DEVDELAY; /**< Device Delay Register */ 52 __IOM uint32_t RDDATACAPTURE; /**< Read Data Capture Register */ 53 __IOM uint32_t DEVSIZECONFIG; /**< Device Size Configuration Register */ 54 __IOM uint32_t SRAMPARTITIONCFG; /**< SRAM Partition Configuration Register */ 55 __IOM uint32_t INDAHBADDRTRIGGER; /**< Indirect Address Trigger Register */ 56 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 57 __IOM uint32_t REMAPADDR; /**< Remap Address Register */ 58 __IOM uint32_t MODEBITCONFIG; /**< Mode Bit Configuration Register */ 59 __IM uint32_t SRAMFILL; /**< SRAM Fill Register */ 60 __IOM uint32_t TXTHRESH; /**< TX Threshold Register */ 61 __IOM uint32_t RXTHRESH; /**< RX Threshold Register */ 62 __IOM uint32_t WRITECOMPLETIONCTRL; /**< Write Completion Control Register */ 63 __IOM uint32_t NOOFPOLLSBEFEXP; /**< Polling Expiration Register */ 64 __IOM uint32_t IRQSTATUS; /**< Interrupt Status Register */ 65 __IOM uint32_t IRQMASK; /**< Interrupt Mask */ 66 uint32_t RESERVED1[2U]; /**< Reserved for future use **/ 67 __IOM uint32_t LOWERWRPROT; /**< Lower Write Protection Register */ 68 __IOM uint32_t UPPERWRPROT; /**< Upper Write Protection Register */ 69 __IOM uint32_t WRPROTCTRL; /**< Write Protection Control Register */ 70 uint32_t RESERVED2[1U]; /**< Reserved for future use **/ 71 __IOM uint32_t INDIRECTREADXFERCTRL; /**< Indirect Read Transfer Control Register */ 72 __IOM uint32_t INDIRECTREADXFERWATERMARK; /**< Indirect Read Transfer Watermark Register */ 73 __IOM uint32_t INDIRECTREADXFERSTART; /**< Indirect Read Transfer Start Address Register */ 74 __IOM uint32_t INDIRECTREADXFERNUMBYTES; /**< Indirect Read Transfer Number Bytes Register */ 75 __IOM uint32_t INDIRECTWRITEXFERCTRL; /**< Indirect Write Transfer Control Register */ 76 __IOM uint32_t INDIRECTWRITEXFERWATERMARK; /**< Indirect Write Transfer Watermark Register */ 77 __IOM uint32_t INDIRECTWRITEXFERSTART; /**< Indirect Write Transfer Start Address Register */ 78 __IOM uint32_t INDIRECTWRITEXFERNUMBYTES; /**< Indirect Write Transfer Number Bytes Register */ 79 __IOM uint32_t INDIRECTTRIGGERADDRRANGE; /**< Indirect Trigger Address Range Register */ 80 uint32_t RESERVED3[2U]; /**< Reserved for future use **/ 81 __IOM uint32_t FLASHCOMMANDCTRLMEM; /**< Flash Command Control Memory Register (STIG) */ 82 __IOM uint32_t FLASHCMDCTRL; /**< Flash Command Control Register (STIG) */ 83 __IOM uint32_t FLASHCMDADDR; /**< Flash Command Address Register (STIG) */ 84 uint32_t RESERVED4[2U]; /**< Reserved for future use **/ 85 __IM uint32_t FLASHRDDATALOWER; /**< Flash Command Read Data Register (Lower) (STIG) */ 86 __IM uint32_t FLASHRDDATAUPPER; /**< Flash Command Read Data Register (Upper) (STIG) */ 87 __IOM uint32_t FLASHWRDATALOWER; /**< Flash Command Write Data Register (Lower) (STIG) */ 88 __IOM uint32_t FLASHWRDATAUPPER; /**< Flash Command Write Data Register (Upper) (STIG) */ 89 __IOM uint32_t POLLINGFLASHSTATUS; /**< Polling Flash Status Register */ 90 __IOM uint32_t PHYCONFIGURATION; /**< PHY Configuration Register */ 91 92 uint32_t RESERVED5[10U]; /**< Reserved for future use **/ 93 __IOM uint32_t OPCODEEXTLOWER; /**< Opcode Extension Register (Lower) */ 94 __IOM uint32_t OPCODEEXTUPPER; /**< Opcode Extension Register (Upper) */ 95 uint32_t RESERVED6[5U]; /**< Reserved for future use **/ 96 __IM uint32_t MODULEID; /**< Module ID Register */ 97 98 uint32_t RESERVED7[1U]; /**< Reserved for future use **/ 99 __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ 100 __IOM uint32_t ROUTELOC0; /**< I/O Route Location Register 0 */ 101 } QSPI_TypeDef; /** @} */ 102 103 /***************************************************************************//** 104 * @addtogroup EFM32GG11B_QSPI 105 * @{ 106 * @defgroup EFM32GG11B_QSPI_BitFields QSPI Bit Fields 107 * @{ 108 ******************************************************************************/ 109 110 /* Bit fields for QSPI CONFIG */ 111 #define _QSPI_CONFIG_RESETVALUE 0x80780081UL /**< Default value for QSPI_CONFIG */ 112 #define _QSPI_CONFIG_MASK 0xE3FF4F8FUL /**< Mask for QSPI_CONFIG */ 113 #define QSPI_CONFIG_ENBSPI (0x1UL << 0) /**< QSPI Enable */ 114 #define _QSPI_CONFIG_ENBSPI_SHIFT 0 /**< Shift value for QSPI_ENBSPI */ 115 #define _QSPI_CONFIG_ENBSPI_MASK 0x1UL /**< Bit mask for QSPI_ENBSPI */ 116 #define _QSPI_CONFIG_ENBSPI_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_CONFIG */ 117 #define QSPI_CONFIG_ENBSPI_DEFAULT (_QSPI_CONFIG_ENBSPI_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 118 #define QSPI_CONFIG_SELCLKPOL (0x1UL << 1) /**< Clock Polarity, CPOL */ 119 #define _QSPI_CONFIG_SELCLKPOL_SHIFT 1 /**< Shift value for QSPI_SELCLKPOL */ 120 #define _QSPI_CONFIG_SELCLKPOL_MASK 0x2UL /**< Bit mask for QSPI_SELCLKPOL */ 121 #define _QSPI_CONFIG_SELCLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ 122 #define QSPI_CONFIG_SELCLKPOL_DEFAULT (_QSPI_CONFIG_SELCLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 123 #define QSPI_CONFIG_SELCLKPHASE (0x1UL << 2) /**< Clock Phase, CPHA */ 124 #define _QSPI_CONFIG_SELCLKPHASE_SHIFT 2 /**< Shift value for QSPI_SELCLKPHASE */ 125 #define _QSPI_CONFIG_SELCLKPHASE_MASK 0x4UL /**< Bit mask for QSPI_SELCLKPHASE */ 126 #define _QSPI_CONFIG_SELCLKPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ 127 #define QSPI_CONFIG_SELCLKPHASE_DEFAULT (_QSPI_CONFIG_SELCLKPHASE_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 128 #define QSPI_CONFIG_PHYMODEENABLE (0x1UL << 3) /**< PHY Mode Enable */ 129 #define _QSPI_CONFIG_PHYMODEENABLE_SHIFT 3 /**< Shift value for QSPI_PHYMODEENABLE */ 130 #define _QSPI_CONFIG_PHYMODEENABLE_MASK 0x8UL /**< Bit mask for QSPI_PHYMODEENABLE */ 131 #define _QSPI_CONFIG_PHYMODEENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ 132 #define QSPI_CONFIG_PHYMODEENABLE_DEFAULT (_QSPI_CONFIG_PHYMODEENABLE_DEFAULT << 3) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 133 #define QSPI_CONFIG_ENBDIRACCCTLR (0x1UL << 7) /**< Enable Direct Access Controller */ 134 #define _QSPI_CONFIG_ENBDIRACCCTLR_SHIFT 7 /**< Shift value for QSPI_ENBDIRACCCTLR */ 135 #define _QSPI_CONFIG_ENBDIRACCCTLR_MASK 0x80UL /**< Bit mask for QSPI_ENBDIRACCCTLR */ 136 #define _QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_CONFIG */ 137 #define QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT (_QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT << 7) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 138 #define QSPI_CONFIG_ENBLEGACYIPMODE (0x1UL << 8) /**< Legacy IP Mode Enable */ 139 #define _QSPI_CONFIG_ENBLEGACYIPMODE_SHIFT 8 /**< Shift value for QSPI_ENBLEGACYIPMODE */ 140 #define _QSPI_CONFIG_ENBLEGACYIPMODE_MASK 0x100UL /**< Bit mask for QSPI_ENBLEGACYIPMODE */ 141 #define _QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ 142 #define QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT (_QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 143 #define QSPI_CONFIG_PERIPHSELDEC (0x1UL << 9) /**< Peripheral Select Decode */ 144 #define _QSPI_CONFIG_PERIPHSELDEC_SHIFT 9 /**< Shift value for QSPI_PERIPHSELDEC */ 145 #define _QSPI_CONFIG_PERIPHSELDEC_MASK 0x200UL /**< Bit mask for QSPI_PERIPHSELDEC */ 146 #define _QSPI_CONFIG_PERIPHSELDEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ 147 #define QSPI_CONFIG_PERIPHSELDEC_DEFAULT (_QSPI_CONFIG_PERIPHSELDEC_DEFAULT << 9) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 148 #define _QSPI_CONFIG_PERIPHCSLINES_SHIFT 10 /**< Shift value for QSPI_PERIPHCSLINES */ 149 #define _QSPI_CONFIG_PERIPHCSLINES_MASK 0xC00UL /**< Bit mask for QSPI_PERIPHCSLINES */ 150 #define _QSPI_CONFIG_PERIPHCSLINES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ 151 #define QSPI_CONFIG_PERIPHCSLINES_DEFAULT (_QSPI_CONFIG_PERIPHCSLINES_DEFAULT << 10) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 152 #define QSPI_CONFIG_WRPROTFLASH (0x1UL << 14) /**< Write Protect Flash Pin */ 153 #define _QSPI_CONFIG_WRPROTFLASH_SHIFT 14 /**< Shift value for QSPI_WRPROTFLASH */ 154 #define _QSPI_CONFIG_WRPROTFLASH_MASK 0x4000UL /**< Bit mask for QSPI_WRPROTFLASH */ 155 #define _QSPI_CONFIG_WRPROTFLASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ 156 #define QSPI_CONFIG_WRPROTFLASH_DEFAULT (_QSPI_CONFIG_WRPROTFLASH_DEFAULT << 14) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 157 #define QSPI_CONFIG_ENBAHBADDRREMAP (0x1UL << 16) /**< Enable Address Remapping */ 158 #define _QSPI_CONFIG_ENBAHBADDRREMAP_SHIFT 16 /**< Shift value for QSPI_ENBAHBADDRREMAP */ 159 #define _QSPI_CONFIG_ENBAHBADDRREMAP_MASK 0x10000UL /**< Bit mask for QSPI_ENBAHBADDRREMAP */ 160 #define _QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ 161 #define QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT (_QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 162 #define QSPI_CONFIG_ENTERXIPMODE (0x1UL << 17) /**< Enter XIP Mode on Next READ */ 163 #define _QSPI_CONFIG_ENTERXIPMODE_SHIFT 17 /**< Shift value for QSPI_ENTERXIPMODE */ 164 #define _QSPI_CONFIG_ENTERXIPMODE_MASK 0x20000UL /**< Bit mask for QSPI_ENTERXIPMODE */ 165 #define _QSPI_CONFIG_ENTERXIPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ 166 #define QSPI_CONFIG_ENTERXIPMODE_DEFAULT (_QSPI_CONFIG_ENTERXIPMODE_DEFAULT << 17) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 167 #define QSPI_CONFIG_ENTERXIPMODEIMM (0x1UL << 18) /**< Enter XIP Mode Immediately */ 168 #define _QSPI_CONFIG_ENTERXIPMODEIMM_SHIFT 18 /**< Shift value for QSPI_ENTERXIPMODEIMM */ 169 #define _QSPI_CONFIG_ENTERXIPMODEIMM_MASK 0x40000UL /**< Bit mask for QSPI_ENTERXIPMODEIMM */ 170 #define _QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ 171 #define QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT (_QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT << 18) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 172 #define _QSPI_CONFIG_MSTRBAUDDIV_SHIFT 19 /**< Shift value for QSPI_MSTRBAUDDIV */ 173 #define _QSPI_CONFIG_MSTRBAUDDIV_MASK 0x780000UL /**< Bit mask for QSPI_MSTRBAUDDIV */ 174 #define _QSPI_CONFIG_MSTRBAUDDIV_DEFAULT 0x0000000FUL /**< Mode DEFAULT for QSPI_CONFIG */ 175 #define QSPI_CONFIG_MSTRBAUDDIV_DEFAULT (_QSPI_CONFIG_MSTRBAUDDIV_DEFAULT << 19) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 176 #define QSPI_CONFIG_ENABLEAHBDECODER (0x1UL << 23) /**< Enable Address Decoder */ 177 #define _QSPI_CONFIG_ENABLEAHBDECODER_SHIFT 23 /**< Shift value for QSPI_ENABLEAHBDECODER */ 178 #define _QSPI_CONFIG_ENABLEAHBDECODER_MASK 0x800000UL /**< Bit mask for QSPI_ENABLEAHBDECODER */ 179 #define _QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ 180 #define QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT (_QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT << 23) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 181 #define QSPI_CONFIG_ENABLEDTRPROTOCOL (0x1UL << 24) /**< Enable DTR Protocol */ 182 #define _QSPI_CONFIG_ENABLEDTRPROTOCOL_SHIFT 24 /**< Shift value for QSPI_ENABLEDTRPROTOCOL */ 183 #define _QSPI_CONFIG_ENABLEDTRPROTOCOL_MASK 0x1000000UL /**< Bit mask for QSPI_ENABLEDTRPROTOCOL */ 184 #define _QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ 185 #define QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT (_QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 186 #define QSPI_CONFIG_PIPELINEPHY (0x1UL << 25) /**< Pipeline PHY Mode Enable */ 187 #define _QSPI_CONFIG_PIPELINEPHY_SHIFT 25 /**< Shift value for QSPI_PIPELINEPHY */ 188 #define _QSPI_CONFIG_PIPELINEPHY_MASK 0x2000000UL /**< Bit mask for QSPI_PIPELINEPHY */ 189 #define _QSPI_CONFIG_PIPELINEPHY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ 190 #define QSPI_CONFIG_PIPELINEPHY_DEFAULT (_QSPI_CONFIG_PIPELINEPHY_DEFAULT << 25) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 191 #define QSPI_CONFIG_CRCENABLE (0x1UL << 29) /**< CRC Enable Bit */ 192 #define _QSPI_CONFIG_CRCENABLE_SHIFT 29 /**< Shift value for QSPI_CRCENABLE */ 193 #define _QSPI_CONFIG_CRCENABLE_MASK 0x20000000UL /**< Bit mask for QSPI_CRCENABLE */ 194 #define _QSPI_CONFIG_CRCENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ 195 #define QSPI_CONFIG_CRCENABLE_DEFAULT (_QSPI_CONFIG_CRCENABLE_DEFAULT << 29) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 196 #define QSPI_CONFIG_DUALBYTEOPCODEEN (0x1UL << 30) /**< Dual-byte Opcode Mode Enable Bit */ 197 #define _QSPI_CONFIG_DUALBYTEOPCODEEN_SHIFT 30 /**< Shift value for QSPI_DUALBYTEOPCODEEN */ 198 #define _QSPI_CONFIG_DUALBYTEOPCODEEN_MASK 0x40000000UL /**< Bit mask for QSPI_DUALBYTEOPCODEEN */ 199 #define _QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */ 200 #define QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT (_QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT << 30) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 201 #define QSPI_CONFIG_IDLE (0x1UL << 31) /**< Serial Interface and Low Level SPI Pipeline is IDLE */ 202 #define _QSPI_CONFIG_IDLE_SHIFT 31 /**< Shift value for QSPI_IDLE */ 203 #define _QSPI_CONFIG_IDLE_MASK 0x80000000UL /**< Bit mask for QSPI_IDLE */ 204 #define _QSPI_CONFIG_IDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_CONFIG */ 205 #define QSPI_CONFIG_IDLE_DEFAULT (_QSPI_CONFIG_IDLE_DEFAULT << 31) /**< Shifted mode DEFAULT for QSPI_CONFIG */ 206 207 /* Bit fields for QSPI DEVINSTRRDCONFIG */ 208 #define _QSPI_DEVINSTRRDCONFIG_RESETVALUE 0x00000003UL /**< Default value for QSPI_DEVINSTRRDCONFIG */ 209 #define _QSPI_DEVINSTRRDCONFIG_MASK 0x1F1337FFUL /**< Mask for QSPI_DEVINSTRRDCONFIG */ 210 #define _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_SHIFT 0 /**< Shift value for QSPI_RDOPCODENONXIP */ 211 #define _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_MASK 0xFFUL /**< Bit mask for QSPI_RDOPCODENONXIP */ 212 #define _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT 0x00000003UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ 213 #define QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT (_QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ 214 #define _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_SHIFT 8 /**< Shift value for QSPI_INSTRTYPE */ 215 #define _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_MASK 0x300UL /**< Bit mask for QSPI_INSTRTYPE */ 216 #define _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ 217 #define QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT (_QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ 218 #define QSPI_DEVINSTRRDCONFIG_DDREN (0x1UL << 10) /**< DDR Enable */ 219 #define _QSPI_DEVINSTRRDCONFIG_DDREN_SHIFT 10 /**< Shift value for QSPI_DDREN */ 220 #define _QSPI_DEVINSTRRDCONFIG_DDREN_MASK 0x400UL /**< Bit mask for QSPI_DDREN */ 221 #define _QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ 222 #define QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT (_QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT << 10) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ 223 #define _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_SHIFT 12 /**< Shift value for QSPI_ADDRXFERTYPESTDMODE */ 224 #define _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_MASK 0x3000UL /**< Bit mask for QSPI_ADDRXFERTYPESTDMODE */ 225 #define _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ 226 #define QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT (_QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ 227 #define _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_SHIFT 16 /**< Shift value for QSPI_DATAXFERTYPEEXTMODE */ 228 #define _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_MASK 0x30000UL /**< Bit mask for QSPI_DATAXFERTYPEEXTMODE */ 229 #define _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ 230 #define QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT (_QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ 231 #define QSPI_DEVINSTRRDCONFIG_MODEBITENABLE (0x1UL << 20) /**< Mode Bit Enable */ 232 #define _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_SHIFT 20 /**< Shift value for QSPI_MODEBITENABLE */ 233 #define _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_MASK 0x100000UL /**< Bit mask for QSPI_MODEBITENABLE */ 234 #define _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ 235 #define QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT (_QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT << 20) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ 236 #define _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_SHIFT 24 /**< Shift value for QSPI_DUMMYRDCLKCYCLES */ 237 #define _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_MASK 0x1F000000UL /**< Bit mask for QSPI_DUMMYRDCLKCYCLES */ 238 #define _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ 239 #define QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT (_QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */ 240 241 /* Bit fields for QSPI DEVINSTRWRCONFIG */ 242 #define _QSPI_DEVINSTRWRCONFIG_RESETVALUE 0x00000002UL /**< Default value for QSPI_DEVINSTRWRCONFIG */ 243 #define _QSPI_DEVINSTRWRCONFIG_MASK 0x1F0331FFUL /**< Mask for QSPI_DEVINSTRWRCONFIG */ 244 #define _QSPI_DEVINSTRWRCONFIG_WROPCODE_SHIFT 0 /**< Shift value for QSPI_WROPCODE */ 245 #define _QSPI_DEVINSTRWRCONFIG_WROPCODE_MASK 0xFFUL /**< Bit mask for QSPI_WROPCODE */ 246 #define _QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ 247 #define QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT (_QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ 248 #define QSPI_DEVINSTRWRCONFIG_WELDIS (0x1UL << 8) /**< WEL Disable */ 249 #define _QSPI_DEVINSTRWRCONFIG_WELDIS_SHIFT 8 /**< Shift value for QSPI_WELDIS */ 250 #define _QSPI_DEVINSTRWRCONFIG_WELDIS_MASK 0x100UL /**< Bit mask for QSPI_WELDIS */ 251 #define _QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ 252 #define QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT (_QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ 253 #define _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_SHIFT 12 /**< Shift value for QSPI_ADDRXFERTYPESTDMODE */ 254 #define _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_MASK 0x3000UL /**< Bit mask for QSPI_ADDRXFERTYPESTDMODE */ 255 #define _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ 256 #define QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT (_QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ 257 #define _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_SHIFT 16 /**< Shift value for QSPI_DATAXFERTYPEEXTMODE */ 258 #define _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_MASK 0x30000UL /**< Bit mask for QSPI_DATAXFERTYPEEXTMODE */ 259 #define _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ 260 #define QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT (_QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ 261 #define _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_SHIFT 24 /**< Shift value for QSPI_DUMMYWRCLKCYCLES */ 262 #define _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_MASK 0x1F000000UL /**< Bit mask for QSPI_DUMMYWRCLKCYCLES */ 263 #define _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ 264 #define QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT (_QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG */ 265 266 /* Bit fields for QSPI DEVDELAY */ 267 #define _QSPI_DEVDELAY_RESETVALUE 0x00000000UL /**< Default value for QSPI_DEVDELAY */ 268 #define _QSPI_DEVDELAY_MASK 0xFFFFFFFFUL /**< Mask for QSPI_DEVDELAY */ 269 #define _QSPI_DEVDELAY_DINIT_SHIFT 0 /**< Shift value for QSPI_DINIT */ 270 #define _QSPI_DEVDELAY_DINIT_MASK 0xFFUL /**< Bit mask for QSPI_DINIT */ 271 #define _QSPI_DEVDELAY_DINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVDELAY */ 272 #define QSPI_DEVDELAY_DINIT_DEFAULT (_QSPI_DEVDELAY_DINIT_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_DEVDELAY */ 273 #define _QSPI_DEVDELAY_DAFTER_SHIFT 8 /**< Shift value for QSPI_DAFTER */ 274 #define _QSPI_DEVDELAY_DAFTER_MASK 0xFF00UL /**< Bit mask for QSPI_DAFTER */ 275 #define _QSPI_DEVDELAY_DAFTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVDELAY */ 276 #define QSPI_DEVDELAY_DAFTER_DEFAULT (_QSPI_DEVDELAY_DAFTER_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_DEVDELAY */ 277 #define _QSPI_DEVDELAY_DBTWN_SHIFT 16 /**< Shift value for QSPI_DBTWN */ 278 #define _QSPI_DEVDELAY_DBTWN_MASK 0xFF0000UL /**< Bit mask for QSPI_DBTWN */ 279 #define _QSPI_DEVDELAY_DBTWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVDELAY */ 280 #define QSPI_DEVDELAY_DBTWN_DEFAULT (_QSPI_DEVDELAY_DBTWN_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_DEVDELAY */ 281 #define _QSPI_DEVDELAY_DNSS_SHIFT 24 /**< Shift value for QSPI_DNSS */ 282 #define _QSPI_DEVDELAY_DNSS_MASK 0xFF000000UL /**< Bit mask for QSPI_DNSS */ 283 #define _QSPI_DEVDELAY_DNSS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVDELAY */ 284 #define QSPI_DEVDELAY_DNSS_DEFAULT (_QSPI_DEVDELAY_DNSS_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_DEVDELAY */ 285 286 /* Bit fields for QSPI RDDATACAPTURE */ 287 #define _QSPI_RDDATACAPTURE_RESETVALUE 0x00000001UL /**< Default value for QSPI_RDDATACAPTURE */ 288 #define _QSPI_RDDATACAPTURE_MASK 0x000F011FUL /**< Mask for QSPI_RDDATACAPTURE */ 289 #define QSPI_RDDATACAPTURE_BYPASS (0x1UL << 0) /**< Bypass the Adapted Loopback Clock Circuit */ 290 #define _QSPI_RDDATACAPTURE_BYPASS_SHIFT 0 /**< Shift value for QSPI_BYPASS */ 291 #define _QSPI_RDDATACAPTURE_BYPASS_MASK 0x1UL /**< Bit mask for QSPI_BYPASS */ 292 #define _QSPI_RDDATACAPTURE_BYPASS_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_RDDATACAPTURE */ 293 #define QSPI_RDDATACAPTURE_BYPASS_DEFAULT (_QSPI_RDDATACAPTURE_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_RDDATACAPTURE */ 294 #define _QSPI_RDDATACAPTURE_DELAY_SHIFT 1 /**< Shift value for QSPI_DELAY */ 295 #define _QSPI_RDDATACAPTURE_DELAY_MASK 0x1EUL /**< Bit mask for QSPI_DELAY */ 296 #define _QSPI_RDDATACAPTURE_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_RDDATACAPTURE */ 297 #define QSPI_RDDATACAPTURE_DELAY_DEFAULT (_QSPI_RDDATACAPTURE_DELAY_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_RDDATACAPTURE */ 298 #define QSPI_RDDATACAPTURE_DQSENABLE (0x1UL << 8) /**< DQS Enable Bit */ 299 #define _QSPI_RDDATACAPTURE_DQSENABLE_SHIFT 8 /**< Shift value for QSPI_DQSENABLE */ 300 #define _QSPI_RDDATACAPTURE_DQSENABLE_MASK 0x100UL /**< Bit mask for QSPI_DQSENABLE */ 301 #define _QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_RDDATACAPTURE */ 302 #define QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT (_QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_RDDATACAPTURE */ 303 #define _QSPI_RDDATACAPTURE_DDRREADDELAY_SHIFT 16 /**< Shift value for QSPI_DDRREADDELAY */ 304 #define _QSPI_RDDATACAPTURE_DDRREADDELAY_MASK 0xF0000UL /**< Bit mask for QSPI_DDRREADDELAY */ 305 #define _QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_RDDATACAPTURE */ 306 #define QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT (_QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_RDDATACAPTURE */ 307 308 /* Bit fields for QSPI DEVSIZECONFIG */ 309 #define _QSPI_DEVSIZECONFIG_RESETVALUE 0x00101002UL /**< Default value for QSPI_DEVSIZECONFIG */ 310 #define _QSPI_DEVSIZECONFIG_MASK 0x01FFFFFFUL /**< Mask for QSPI_DEVSIZECONFIG */ 311 #define _QSPI_DEVSIZECONFIG_NUMADDRBYTES_SHIFT 0 /**< Shift value for QSPI_NUMADDRBYTES */ 312 #define _QSPI_DEVSIZECONFIG_NUMADDRBYTES_MASK 0xFUL /**< Bit mask for QSPI_NUMADDRBYTES */ 313 #define _QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT 0x00000002UL /**< Mode DEFAULT for QSPI_DEVSIZECONFIG */ 314 #define QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT (_QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_DEVSIZECONFIG */ 315 #define _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_SHIFT 4 /**< Shift value for QSPI_BYTESPERDEVICEPAGE */ 316 #define _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_MASK 0xFFF0UL /**< Bit mask for QSPI_BYTESPERDEVICEPAGE */ 317 #define _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT 0x00000100UL /**< Mode DEFAULT for QSPI_DEVSIZECONFIG */ 318 #define QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT (_QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT << 4) /**< Shifted mode DEFAULT for QSPI_DEVSIZECONFIG */ 319 #define _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_SHIFT 16 /**< Shift value for QSPI_BYTESPERSUBSECTOR */ 320 #define _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_MASK 0x1F0000UL /**< Bit mask for QSPI_BYTESPERSUBSECTOR */ 321 #define _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT 0x00000010UL /**< Mode DEFAULT for QSPI_DEVSIZECONFIG */ 322 #define QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT (_QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_DEVSIZECONFIG */ 323 #define _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_SHIFT 21 /**< Shift value for QSPI_MEMSIZEONCS0 */ 324 #define _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_MASK 0x600000UL /**< Bit mask for QSPI_MEMSIZEONCS0 */ 325 #define _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVSIZECONFIG */ 326 #define QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT (_QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT << 21) /**< Shifted mode DEFAULT for QSPI_DEVSIZECONFIG */ 327 #define _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_SHIFT 23 /**< Shift value for QSPI_MEMSIZEONCS1 */ 328 #define _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_MASK 0x1800000UL /**< Bit mask for QSPI_MEMSIZEONCS1 */ 329 #define _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVSIZECONFIG */ 330 #define QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT (_QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT << 23) /**< Shifted mode DEFAULT for QSPI_DEVSIZECONFIG */ 331 332 /* Bit fields for QSPI SRAMPARTITIONCFG */ 333 #define _QSPI_SRAMPARTITIONCFG_RESETVALUE 0x00000080UL /**< Default value for QSPI_SRAMPARTITIONCFG */ 334 #define _QSPI_SRAMPARTITIONCFG_MASK 0x000000FFUL /**< Mask for QSPI_SRAMPARTITIONCFG */ 335 #define _QSPI_SRAMPARTITIONCFG_ADDR_SHIFT 0 /**< Shift value for QSPI_ADDR */ 336 #define _QSPI_SRAMPARTITIONCFG_ADDR_MASK 0xFFUL /**< Bit mask for QSPI_ADDR */ 337 #define _QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT 0x00000080UL /**< Mode DEFAULT for QSPI_SRAMPARTITIONCFG */ 338 #define QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT (_QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_SRAMPARTITIONCFG */ 339 340 /* Bit fields for QSPI INDAHBADDRTRIGGER */ 341 #define _QSPI_INDAHBADDRTRIGGER_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDAHBADDRTRIGGER */ 342 #define _QSPI_INDAHBADDRTRIGGER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDAHBADDRTRIGGER */ 343 #define _QSPI_INDAHBADDRTRIGGER_ADDR_SHIFT 0 /**< Shift value for QSPI_ADDR */ 344 #define _QSPI_INDAHBADDRTRIGGER_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_ADDR */ 345 #define _QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDAHBADDRTRIGGER */ 346 #define QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT (_QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDAHBADDRTRIGGER */ 347 348 /* Bit fields for QSPI REMAPADDR */ 349 #define _QSPI_REMAPADDR_RESETVALUE 0x00000000UL /**< Default value for QSPI_REMAPADDR */ 350 #define _QSPI_REMAPADDR_MASK 0xFFFFFFFFUL /**< Mask for QSPI_REMAPADDR */ 351 #define _QSPI_REMAPADDR_VALUE_SHIFT 0 /**< Shift value for QSPI_VALUE */ 352 #define _QSPI_REMAPADDR_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_VALUE */ 353 #define _QSPI_REMAPADDR_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_REMAPADDR */ 354 #define QSPI_REMAPADDR_VALUE_DEFAULT (_QSPI_REMAPADDR_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_REMAPADDR */ 355 356 /* Bit fields for QSPI MODEBITCONFIG */ 357 #define _QSPI_MODEBITCONFIG_RESETVALUE 0x00000200UL /**< Default value for QSPI_MODEBITCONFIG */ 358 #define _QSPI_MODEBITCONFIG_MASK 0xFFFF87FFUL /**< Mask for QSPI_MODEBITCONFIG */ 359 #define _QSPI_MODEBITCONFIG_MODE_SHIFT 0 /**< Shift value for QSPI_MODE */ 360 #define _QSPI_MODEBITCONFIG_MODE_MASK 0xFFUL /**< Bit mask for QSPI_MODE */ 361 #define _QSPI_MODEBITCONFIG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODEBITCONFIG */ 362 #define QSPI_MODEBITCONFIG_MODE_DEFAULT (_QSPI_MODEBITCONFIG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_MODEBITCONFIG */ 363 #define _QSPI_MODEBITCONFIG_CHUNKSIZE_SHIFT 8 /**< Shift value for QSPI_CHUNKSIZE */ 364 #define _QSPI_MODEBITCONFIG_CHUNKSIZE_MASK 0x700UL /**< Bit mask for QSPI_CHUNKSIZE */ 365 #define _QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT 0x00000002UL /**< Mode DEFAULT for QSPI_MODEBITCONFIG */ 366 #define QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT (_QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_MODEBITCONFIG */ 367 #define QSPI_MODEBITCONFIG_CRCOUTENABLE (0x1UL << 15) /**< CRC# Output Enable Bit */ 368 #define _QSPI_MODEBITCONFIG_CRCOUTENABLE_SHIFT 15 /**< Shift value for QSPI_CRCOUTENABLE */ 369 #define _QSPI_MODEBITCONFIG_CRCOUTENABLE_MASK 0x8000UL /**< Bit mask for QSPI_CRCOUTENABLE */ 370 #define _QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODEBITCONFIG */ 371 #define QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT (_QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT << 15) /**< Shifted mode DEFAULT for QSPI_MODEBITCONFIG */ 372 #define _QSPI_MODEBITCONFIG_RXCRCDATAUP_SHIFT 16 /**< Shift value for QSPI_RXCRCDATAUP */ 373 #define _QSPI_MODEBITCONFIG_RXCRCDATAUP_MASK 0xFF0000UL /**< Bit mask for QSPI_RXCRCDATAUP */ 374 #define _QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODEBITCONFIG */ 375 #define QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT (_QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_MODEBITCONFIG */ 376 #define _QSPI_MODEBITCONFIG_RXCRCDATALOW_SHIFT 24 /**< Shift value for QSPI_RXCRCDATALOW */ 377 #define _QSPI_MODEBITCONFIG_RXCRCDATALOW_MASK 0xFF000000UL /**< Bit mask for QSPI_RXCRCDATALOW */ 378 #define _QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODEBITCONFIG */ 379 #define QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT (_QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_MODEBITCONFIG */ 380 381 /* Bit fields for QSPI SRAMFILL */ 382 #define _QSPI_SRAMFILL_RESETVALUE 0x00000000UL /**< Default value for QSPI_SRAMFILL */ 383 #define _QSPI_SRAMFILL_MASK 0xFFFFFFFFUL /**< Mask for QSPI_SRAMFILL */ 384 #define _QSPI_SRAMFILL_SRAMFILLINDACREAD_SHIFT 0 /**< Shift value for QSPI_SRAMFILLINDACREAD */ 385 #define _QSPI_SRAMFILL_SRAMFILLINDACREAD_MASK 0xFFFFUL /**< Bit mask for QSPI_SRAMFILLINDACREAD */ 386 #define _QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_SRAMFILL */ 387 #define QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT (_QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_SRAMFILL */ 388 #define _QSPI_SRAMFILL_SRAMFILLINDACWRITE_SHIFT 16 /**< Shift value for QSPI_SRAMFILLINDACWRITE */ 389 #define _QSPI_SRAMFILL_SRAMFILLINDACWRITE_MASK 0xFFFF0000UL /**< Bit mask for QSPI_SRAMFILLINDACWRITE */ 390 #define _QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_SRAMFILL */ 391 #define QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT (_QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_SRAMFILL */ 392 393 /* Bit fields for QSPI TXTHRESH */ 394 #define _QSPI_TXTHRESH_RESETVALUE 0x00000001UL /**< Default value for QSPI_TXTHRESH */ 395 #define _QSPI_TXTHRESH_MASK 0x0000001FUL /**< Mask for QSPI_TXTHRESH */ 396 #define _QSPI_TXTHRESH_LEVEL_SHIFT 0 /**< Shift value for QSPI_LEVEL */ 397 #define _QSPI_TXTHRESH_LEVEL_MASK 0x1FUL /**< Bit mask for QSPI_LEVEL */ 398 #define _QSPI_TXTHRESH_LEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_TXTHRESH */ 399 #define QSPI_TXTHRESH_LEVEL_DEFAULT (_QSPI_TXTHRESH_LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_TXTHRESH */ 400 401 /* Bit fields for QSPI RXTHRESH */ 402 #define _QSPI_RXTHRESH_RESETVALUE 0x00000001UL /**< Default value for QSPI_RXTHRESH */ 403 #define _QSPI_RXTHRESH_MASK 0x0000001FUL /**< Mask for QSPI_RXTHRESH */ 404 #define _QSPI_RXTHRESH_LEVEL_SHIFT 0 /**< Shift value for QSPI_LEVEL */ 405 #define _QSPI_RXTHRESH_LEVEL_MASK 0x1FUL /**< Bit mask for QSPI_LEVEL */ 406 #define _QSPI_RXTHRESH_LEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_RXTHRESH */ 407 #define QSPI_RXTHRESH_LEVEL_DEFAULT (_QSPI_RXTHRESH_LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_RXTHRESH */ 408 409 /* Bit fields for QSPI WRITECOMPLETIONCTRL */ 410 #define _QSPI_WRITECOMPLETIONCTRL_RESETVALUE 0x00010005UL /**< Default value for QSPI_WRITECOMPLETIONCTRL */ 411 #define _QSPI_WRITECOMPLETIONCTRL_MASK 0xFFFFE7FFUL /**< Mask for QSPI_WRITECOMPLETIONCTRL */ 412 #define _QSPI_WRITECOMPLETIONCTRL_OPCODE_SHIFT 0 /**< Shift value for QSPI_OPCODE */ 413 #define _QSPI_WRITECOMPLETIONCTRL_OPCODE_MASK 0xFFUL /**< Bit mask for QSPI_OPCODE */ 414 #define _QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT 0x00000005UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ 415 #define QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ 416 #define _QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_SHIFT 8 /**< Shift value for QSPI_POLLINGBITINDEX */ 417 #define _QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_MASK 0x700UL /**< Bit mask for QSPI_POLLINGBITINDEX */ 418 #define _QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ 419 #define QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ 420 #define QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY (0x1UL << 13) /**< Polling Polarity */ 421 #define _QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_SHIFT 13 /**< Shift value for QSPI_POLLINGPOLARITY */ 422 #define _QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_MASK 0x2000UL /**< Bit mask for QSPI_POLLINGPOLARITY */ 423 #define _QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ 424 #define QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT << 13) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ 425 #define QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING (0x1UL << 14) /**< Disable Polling */ 426 #define _QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_SHIFT 14 /**< Shift value for QSPI_DISABLEPOLLING */ 427 #define _QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_MASK 0x4000UL /**< Bit mask for QSPI_DISABLEPOLLING */ 428 #define _QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ 429 #define QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT << 14) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ 430 #define QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP (0x1UL << 15) /**< Enable Polling Expiration */ 431 #define _QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_SHIFT 15 /**< Shift value for QSPI_ENABLEPOLLINGEXP */ 432 #define _QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_MASK 0x8000UL /**< Bit mask for QSPI_ENABLEPOLLINGEXP */ 433 #define _QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ 434 #define QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT << 15) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ 435 #define _QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_SHIFT 16 /**< Shift value for QSPI_POLLCOUNT */ 436 #define _QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_MASK 0xFF0000UL /**< Bit mask for QSPI_POLLCOUNT */ 437 #define _QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ 438 #define QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ 439 #define _QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_SHIFT 24 /**< Shift value for QSPI_POLLREPDELAY */ 440 #define _QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_MASK 0xFF000000UL /**< Bit mask for QSPI_POLLREPDELAY */ 441 #define _QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ 442 #define QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */ 443 444 /* Bit fields for QSPI NOOFPOLLSBEFEXP */ 445 #define _QSPI_NOOFPOLLSBEFEXP_RESETVALUE 0xFFFFFFFFUL /**< Default value for QSPI_NOOFPOLLSBEFEXP */ 446 #define _QSPI_NOOFPOLLSBEFEXP_MASK 0xFFFFFFFFUL /**< Mask for QSPI_NOOFPOLLSBEFEXP */ 447 #define _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_SHIFT 0 /**< Shift value for QSPI_NOOFPOLLSBEFEXP */ 448 #define _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_NOOFPOLLSBEFEXP */ 449 #define _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for QSPI_NOOFPOLLSBEFEXP */ 450 #define QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT (_QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_NOOFPOLLSBEFEXP */ 451 452 /* Bit fields for QSPI IRQSTATUS */ 453 #define _QSPI_IRQSTATUS_RESETVALUE 0x00000000UL /**< Default value for QSPI_IRQSTATUS */ 454 #define _QSPI_IRQSTATUS_MASK 0x00077FFFUL /**< Mask for QSPI_IRQSTATUS */ 455 #define QSPI_IRQSTATUS_MODEMFAIL (0x1UL << 0) /**< Mode M Failure */ 456 #define _QSPI_IRQSTATUS_MODEMFAIL_SHIFT 0 /**< Shift value for QSPI_MODEMFAIL */ 457 #define _QSPI_IRQSTATUS_MODEMFAIL_MASK 0x1UL /**< Bit mask for QSPI_MODEMFAIL */ 458 #define _QSPI_IRQSTATUS_MODEMFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 459 #define QSPI_IRQSTATUS_MODEMFAIL_DEFAULT (_QSPI_IRQSTATUS_MODEMFAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 460 #define QSPI_IRQSTATUS_UNDERFLOWDET (0x1UL << 1) /**< Underflow Detected */ 461 #define _QSPI_IRQSTATUS_UNDERFLOWDET_SHIFT 1 /**< Shift value for QSPI_UNDERFLOWDET */ 462 #define _QSPI_IRQSTATUS_UNDERFLOWDET_MASK 0x2UL /**< Bit mask for QSPI_UNDERFLOWDET */ 463 #define _QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 464 #define QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT (_QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 465 #define QSPI_IRQSTATUS_INDIRECTOPDONE (0x1UL << 2) /**< Indirect Operation Complete */ 466 #define _QSPI_IRQSTATUS_INDIRECTOPDONE_SHIFT 2 /**< Shift value for QSPI_INDIRECTOPDONE */ 467 #define _QSPI_IRQSTATUS_INDIRECTOPDONE_MASK 0x4UL /**< Bit mask for QSPI_INDIRECTOPDONE */ 468 #define _QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 469 #define QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT (_QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 470 #define QSPI_IRQSTATUS_INDIRECTREADREJECT (0x1UL << 3) /**< Indirect Operation Was Requested but Could Not Be Accepted */ 471 #define _QSPI_IRQSTATUS_INDIRECTREADREJECT_SHIFT 3 /**< Shift value for QSPI_INDIRECTREADREJECT */ 472 #define _QSPI_IRQSTATUS_INDIRECTREADREJECT_MASK 0x8UL /**< Bit mask for QSPI_INDIRECTREADREJECT */ 473 #define _QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 474 #define QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT (_QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT << 3) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 475 #define QSPI_IRQSTATUS_PROTWRATTEMPT (0x1UL << 4) /**< Write to Protected Area Was Attempted and Rejected */ 476 #define _QSPI_IRQSTATUS_PROTWRATTEMPT_SHIFT 4 /**< Shift value for QSPI_PROTWRATTEMPT */ 477 #define _QSPI_IRQSTATUS_PROTWRATTEMPT_MASK 0x10UL /**< Bit mask for QSPI_PROTWRATTEMPT */ 478 #define _QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 479 #define QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT (_QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT << 4) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 480 #define QSPI_IRQSTATUS_ILLEGALACCESSDET (0x1UL << 5) /**< Illegal Memory Access Has Been Detected */ 481 #define _QSPI_IRQSTATUS_ILLEGALACCESSDET_SHIFT 5 /**< Shift value for QSPI_ILLEGALACCESSDET */ 482 #define _QSPI_IRQSTATUS_ILLEGALACCESSDET_MASK 0x20UL /**< Bit mask for QSPI_ILLEGALACCESSDET */ 483 #define _QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 484 #define QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT (_QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT << 5) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 485 #define QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH (0x1UL << 6) /**< Indirect Transfer Watermark Level Breached */ 486 #define _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_SHIFT 6 /**< Shift value for QSPI_INDIRECTXFERLEVELBREACH */ 487 #define _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_MASK 0x40UL /**< Bit mask for QSPI_INDIRECTXFERLEVELBREACH */ 488 #define _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 489 #define QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT (_QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT << 6) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 490 #define QSPI_IRQSTATUS_RECVOVERFLOW (0x1UL << 7) /**< Receive Overflow */ 491 #define _QSPI_IRQSTATUS_RECVOVERFLOW_SHIFT 7 /**< Shift value for QSPI_RECVOVERFLOW */ 492 #define _QSPI_IRQSTATUS_RECVOVERFLOW_MASK 0x80UL /**< Bit mask for QSPI_RECVOVERFLOW */ 493 #define _QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 494 #define QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT (_QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT << 7) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 495 #define QSPI_IRQSTATUS_TXFIFONOTFULL (0x1UL << 8) /**< Small TX FIFO Not Full */ 496 #define _QSPI_IRQSTATUS_TXFIFONOTFULL_SHIFT 8 /**< Shift value for QSPI_TXFIFONOTFULL */ 497 #define _QSPI_IRQSTATUS_TXFIFONOTFULL_MASK 0x100UL /**< Bit mask for QSPI_TXFIFONOTFULL */ 498 #define _QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 499 #define QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT (_QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 500 #define QSPI_IRQSTATUS_TXFIFOFULL (0x1UL << 9) /**< Small TX FIFO Full */ 501 #define _QSPI_IRQSTATUS_TXFIFOFULL_SHIFT 9 /**< Shift value for QSPI_TXFIFOFULL */ 502 #define _QSPI_IRQSTATUS_TXFIFOFULL_MASK 0x200UL /**< Bit mask for QSPI_TXFIFOFULL */ 503 #define _QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 504 #define QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT (_QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 505 #define QSPI_IRQSTATUS_RXFIFONOTEMPTY (0x1UL << 10) /**< Small RX FIFO Not Empty */ 506 #define _QSPI_IRQSTATUS_RXFIFONOTEMPTY_SHIFT 10 /**< Shift value for QSPI_RXFIFONOTEMPTY */ 507 #define _QSPI_IRQSTATUS_RXFIFONOTEMPTY_MASK 0x400UL /**< Bit mask for QSPI_RXFIFONOTEMPTY */ 508 #define _QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 509 #define QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT (_QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT << 10) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 510 #define QSPI_IRQSTATUS_RXFIFOFULL (0x1UL << 11) /**< Small RX FIFO Full */ 511 #define _QSPI_IRQSTATUS_RXFIFOFULL_SHIFT 11 /**< Shift value for QSPI_RXFIFOFULL */ 512 #define _QSPI_IRQSTATUS_RXFIFOFULL_MASK 0x800UL /**< Bit mask for QSPI_RXFIFOFULL */ 513 #define _QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 514 #define QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT (_QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT << 11) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 515 #define QSPI_IRQSTATUS_INDRDSRAMFULL (0x1UL << 12) /**< Indirect Read Partition Overflow */ 516 #define _QSPI_IRQSTATUS_INDRDSRAMFULL_SHIFT 12 /**< Shift value for QSPI_INDRDSRAMFULL */ 517 #define _QSPI_IRQSTATUS_INDRDSRAMFULL_MASK 0x1000UL /**< Bit mask for QSPI_INDRDSRAMFULL */ 518 #define _QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 519 #define QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT (_QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 520 #define QSPI_IRQSTATUS_POLLEXPINT (0x1UL << 13) /**< The Maximum Number of Programmed Polls Cycles is Expired */ 521 #define _QSPI_IRQSTATUS_POLLEXPINT_SHIFT 13 /**< Shift value for QSPI_POLLEXPINT */ 522 #define _QSPI_IRQSTATUS_POLLEXPINT_MASK 0x2000UL /**< Bit mask for QSPI_POLLEXPINT */ 523 #define _QSPI_IRQSTATUS_POLLEXPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 524 #define QSPI_IRQSTATUS_POLLEXPINT_DEFAULT (_QSPI_IRQSTATUS_POLLEXPINT_DEFAULT << 13) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 525 #define QSPI_IRQSTATUS_STIGREQINT (0x1UL << 14) /**< The Controller is Ready for Getting Another STIG Request */ 526 #define _QSPI_IRQSTATUS_STIGREQINT_SHIFT 14 /**< Shift value for QSPI_STIGREQINT */ 527 #define _QSPI_IRQSTATUS_STIGREQINT_MASK 0x4000UL /**< Bit mask for QSPI_STIGREQINT */ 528 #define _QSPI_IRQSTATUS_STIGREQINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 529 #define QSPI_IRQSTATUS_STIGREQINT_DEFAULT (_QSPI_IRQSTATUS_STIGREQINT_DEFAULT << 14) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 530 #define QSPI_IRQSTATUS_RXCRCDATAERR (0x1UL << 16) /**< RX CRC Data Error */ 531 #define _QSPI_IRQSTATUS_RXCRCDATAERR_SHIFT 16 /**< Shift value for QSPI_RXCRCDATAERR */ 532 #define _QSPI_IRQSTATUS_RXCRCDATAERR_MASK 0x10000UL /**< Bit mask for QSPI_RXCRCDATAERR */ 533 #define _QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 534 #define QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT (_QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 535 #define QSPI_IRQSTATUS_RXCRCDATAVAL (0x1UL << 17) /**< RX CRC Data Valid */ 536 #define _QSPI_IRQSTATUS_RXCRCDATAVAL_SHIFT 17 /**< Shift value for QSPI_RXCRCDATAVAL */ 537 #define _QSPI_IRQSTATUS_RXCRCDATAVAL_MASK 0x20000UL /**< Bit mask for QSPI_RXCRCDATAVAL */ 538 #define _QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 539 #define QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT (_QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT << 17) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 540 #define QSPI_IRQSTATUS_TXCRCCHUNKBRK (0x1UL << 18) /**< TX CRC Chunk Was Broken */ 541 #define _QSPI_IRQSTATUS_TXCRCCHUNKBRK_SHIFT 18 /**< Shift value for QSPI_TXCRCCHUNKBRK */ 542 #define _QSPI_IRQSTATUS_TXCRCCHUNKBRK_MASK 0x40000UL /**< Bit mask for QSPI_TXCRCCHUNKBRK */ 543 #define _QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */ 544 #define QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT (_QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT << 18) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */ 545 546 /* Bit fields for QSPI IRQMASK */ 547 #define _QSPI_IRQMASK_RESETVALUE 0x00000000UL /**< Default value for QSPI_IRQMASK */ 548 #define _QSPI_IRQMASK_MASK 0x00077FFFUL /**< Mask for QSPI_IRQMASK */ 549 #define QSPI_IRQMASK_MODEMFAILMASK (0x1UL << 0) /**< Mode M Failure Mask */ 550 #define _QSPI_IRQMASK_MODEMFAILMASK_SHIFT 0 /**< Shift value for QSPI_MODEMFAILMASK */ 551 #define _QSPI_IRQMASK_MODEMFAILMASK_MASK 0x1UL /**< Bit mask for QSPI_MODEMFAILMASK */ 552 #define _QSPI_IRQMASK_MODEMFAILMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 553 #define QSPI_IRQMASK_MODEMFAILMASK_DEFAULT (_QSPI_IRQMASK_MODEMFAILMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 554 #define QSPI_IRQMASK_UNDERFLOWDETMASK (0x1UL << 1) /**< Underflow Detected Mask */ 555 #define _QSPI_IRQMASK_UNDERFLOWDETMASK_SHIFT 1 /**< Shift value for QSPI_UNDERFLOWDETMASK */ 556 #define _QSPI_IRQMASK_UNDERFLOWDETMASK_MASK 0x2UL /**< Bit mask for QSPI_UNDERFLOWDETMASK */ 557 #define _QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 558 #define QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT (_QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 559 #define QSPI_IRQMASK_INDIRECTOPDONEMASK (0x1UL << 2) /**< Indirect Complete Mask */ 560 #define _QSPI_IRQMASK_INDIRECTOPDONEMASK_SHIFT 2 /**< Shift value for QSPI_INDIRECTOPDONEMASK */ 561 #define _QSPI_IRQMASK_INDIRECTOPDONEMASK_MASK 0x4UL /**< Bit mask for QSPI_INDIRECTOPDONEMASK */ 562 #define _QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 563 #define QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT (_QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 564 #define QSPI_IRQMASK_INDIRECTREADREJECTMASK (0x1UL << 3) /**< Indirect Read Reject Mask */ 565 #define _QSPI_IRQMASK_INDIRECTREADREJECTMASK_SHIFT 3 /**< Shift value for QSPI_INDIRECTREADREJECTMASK */ 566 #define _QSPI_IRQMASK_INDIRECTREADREJECTMASK_MASK 0x8UL /**< Bit mask for QSPI_INDIRECTREADREJECTMASK */ 567 #define _QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 568 #define QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT (_QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT << 3) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 569 #define QSPI_IRQMASK_PROTWRATTEMPTMASK (0x1UL << 4) /**< Protected Area Write Attempt Mask */ 570 #define _QSPI_IRQMASK_PROTWRATTEMPTMASK_SHIFT 4 /**< Shift value for QSPI_PROTWRATTEMPTMASK */ 571 #define _QSPI_IRQMASK_PROTWRATTEMPTMASK_MASK 0x10UL /**< Bit mask for QSPI_PROTWRATTEMPTMASK */ 572 #define _QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 573 #define QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT (_QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT << 4) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 574 #define QSPI_IRQMASK_ILLEGALACCESSDETMASK (0x1UL << 5) /**< Illegal Access Detected Mask */ 575 #define _QSPI_IRQMASK_ILLEGALACCESSDETMASK_SHIFT 5 /**< Shift value for QSPI_ILLEGALACCESSDETMASK */ 576 #define _QSPI_IRQMASK_ILLEGALACCESSDETMASK_MASK 0x20UL /**< Bit mask for QSPI_ILLEGALACCESSDETMASK */ 577 #define _QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 578 #define QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT (_QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 579 #define QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK (0x1UL << 6) /**< Transfer Watermark Breach Mask */ 580 #define _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_SHIFT 6 /**< Shift value for QSPI_INDIRECTXFERLEVELBREACHMASK */ 581 #define _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_MASK 0x40UL /**< Bit mask for QSPI_INDIRECTXFERLEVELBREACHMASK */ 582 #define _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 583 #define QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT (_QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT << 6) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 584 #define QSPI_IRQMASK_RECVOVERFLOWMASK (0x1UL << 7) /**< Receive Overflow Mask */ 585 #define _QSPI_IRQMASK_RECVOVERFLOWMASK_SHIFT 7 /**< Shift value for QSPI_RECVOVERFLOWMASK */ 586 #define _QSPI_IRQMASK_RECVOVERFLOWMASK_MASK 0x80UL /**< Bit mask for QSPI_RECVOVERFLOWMASK */ 587 #define _QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 588 #define QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT (_QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT << 7) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 589 #define QSPI_IRQMASK_TXFIFONOTFULLMASK (0x1UL << 8) /**< Small TX FIFO Not Full Mask */ 590 #define _QSPI_IRQMASK_TXFIFONOTFULLMASK_SHIFT 8 /**< Shift value for QSPI_TXFIFONOTFULLMASK */ 591 #define _QSPI_IRQMASK_TXFIFONOTFULLMASK_MASK 0x100UL /**< Bit mask for QSPI_TXFIFONOTFULLMASK */ 592 #define _QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 593 #define QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT (_QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 594 #define QSPI_IRQMASK_TXFIFOFULLMASK (0x1UL << 9) /**< Small TX FIFO Full Mask */ 595 #define _QSPI_IRQMASK_TXFIFOFULLMASK_SHIFT 9 /**< Shift value for QSPI_TXFIFOFULLMASK */ 596 #define _QSPI_IRQMASK_TXFIFOFULLMASK_MASK 0x200UL /**< Bit mask for QSPI_TXFIFOFULLMASK */ 597 #define _QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 598 #define QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT (_QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT << 9) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 599 #define QSPI_IRQMASK_RXFIFONOTEMPTYMASK (0x1UL << 10) /**< Small RX FIFO Not Empty Mask */ 600 #define _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_SHIFT 10 /**< Shift value for QSPI_RXFIFONOTEMPTYMASK */ 601 #define _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_MASK 0x400UL /**< Bit mask for QSPI_RXFIFONOTEMPTYMASK */ 602 #define _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 603 #define QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT (_QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT << 10) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 604 #define QSPI_IRQMASK_RXFIFOFULLMASK (0x1UL << 11) /**< Small RX FIFO Full Mask */ 605 #define _QSPI_IRQMASK_RXFIFOFULLMASK_SHIFT 11 /**< Shift value for QSPI_RXFIFOFULLMASK */ 606 #define _QSPI_IRQMASK_RXFIFOFULLMASK_MASK 0x800UL /**< Bit mask for QSPI_RXFIFOFULLMASK */ 607 #define _QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 608 #define QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT (_QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT << 11) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 609 #define QSPI_IRQMASK_INDRDSRAMFULLMASK (0x1UL << 12) /**< Indirect Read Partition Overflow Mask */ 610 #define _QSPI_IRQMASK_INDRDSRAMFULLMASK_SHIFT 12 /**< Shift value for QSPI_INDRDSRAMFULLMASK */ 611 #define _QSPI_IRQMASK_INDRDSRAMFULLMASK_MASK 0x1000UL /**< Bit mask for QSPI_INDRDSRAMFULLMASK */ 612 #define _QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 613 #define QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT (_QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 614 #define QSPI_IRQMASK_POLLEXPINTMASK (0x1UL << 13) /**< Polling Expiration Detected Mask */ 615 #define _QSPI_IRQMASK_POLLEXPINTMASK_SHIFT 13 /**< Shift value for QSPI_POLLEXPINTMASK */ 616 #define _QSPI_IRQMASK_POLLEXPINTMASK_MASK 0x2000UL /**< Bit mask for QSPI_POLLEXPINTMASK */ 617 #define _QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 618 #define QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT (_QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT << 13) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 619 #define QSPI_IRQMASK_STIGREQMASK (0x1UL << 14) /**< STIG Request Completion Mask */ 620 #define _QSPI_IRQMASK_STIGREQMASK_SHIFT 14 /**< Shift value for QSPI_STIGREQMASK */ 621 #define _QSPI_IRQMASK_STIGREQMASK_MASK 0x4000UL /**< Bit mask for QSPI_STIGREQMASK */ 622 #define _QSPI_IRQMASK_STIGREQMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 623 #define QSPI_IRQMASK_STIGREQMASK_DEFAULT (_QSPI_IRQMASK_STIGREQMASK_DEFAULT << 14) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 624 #define QSPI_IRQMASK_RXCRCDATAERRMASK (0x1UL << 16) /**< RX CRC Data Error Mask */ 625 #define _QSPI_IRQMASK_RXCRCDATAERRMASK_SHIFT 16 /**< Shift value for QSPI_RXCRCDATAERRMASK */ 626 #define _QSPI_IRQMASK_RXCRCDATAERRMASK_MASK 0x10000UL /**< Bit mask for QSPI_RXCRCDATAERRMASK */ 627 #define _QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 628 #define QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT (_QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 629 #define QSPI_IRQMASK_RXCRCDATAVALMASK (0x1UL << 17) /**< RX CRC Data Valid Mask */ 630 #define _QSPI_IRQMASK_RXCRCDATAVALMASK_SHIFT 17 /**< Shift value for QSPI_RXCRCDATAVALMASK */ 631 #define _QSPI_IRQMASK_RXCRCDATAVALMASK_MASK 0x20000UL /**< Bit mask for QSPI_RXCRCDATAVALMASK */ 632 #define _QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 633 #define QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT (_QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT << 17) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 634 #define QSPI_IRQMASK_TXCRCCHUNKBRKMASK (0x1UL << 18) /**< TX CRC Chunk Was Broken Mask */ 635 #define _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_SHIFT 18 /**< Shift value for QSPI_TXCRCCHUNKBRKMASK */ 636 #define _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_MASK 0x40000UL /**< Bit mask for QSPI_TXCRCCHUNKBRKMASK */ 637 #define _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */ 638 #define QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT (_QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT << 18) /**< Shifted mode DEFAULT for QSPI_IRQMASK */ 639 640 /* Bit fields for QSPI LOWERWRPROT */ 641 #define _QSPI_LOWERWRPROT_RESETVALUE 0x00000000UL /**< Default value for QSPI_LOWERWRPROT */ 642 #define _QSPI_LOWERWRPROT_MASK 0xFFFFFFFFUL /**< Mask for QSPI_LOWERWRPROT */ 643 #define _QSPI_LOWERWRPROT_SUBSECTOR_SHIFT 0 /**< Shift value for QSPI_SUBSECTOR */ 644 #define _QSPI_LOWERWRPROT_SUBSECTOR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_SUBSECTOR */ 645 #define _QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_LOWERWRPROT */ 646 #define QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT (_QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_LOWERWRPROT */ 647 648 /* Bit fields for QSPI UPPERWRPROT */ 649 #define _QSPI_UPPERWRPROT_RESETVALUE 0x00000000UL /**< Default value for QSPI_UPPERWRPROT */ 650 #define _QSPI_UPPERWRPROT_MASK 0xFFFFFFFFUL /**< Mask for QSPI_UPPERWRPROT */ 651 #define _QSPI_UPPERWRPROT_SUBSECTOR_SHIFT 0 /**< Shift value for QSPI_SUBSECTOR */ 652 #define _QSPI_UPPERWRPROT_SUBSECTOR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_SUBSECTOR */ 653 #define _QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_UPPERWRPROT */ 654 #define QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT (_QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_UPPERWRPROT */ 655 656 /* Bit fields for QSPI WRPROTCTRL */ 657 #define _QSPI_WRPROTCTRL_RESETVALUE 0x00000000UL /**< Default value for QSPI_WRPROTCTRL */ 658 #define _QSPI_WRPROTCTRL_MASK 0x00000003UL /**< Mask for QSPI_WRPROTCTRL */ 659 #define QSPI_WRPROTCTRL_INV (0x1UL << 0) /**< Write Protection Inversion Bit */ 660 #define _QSPI_WRPROTCTRL_INV_SHIFT 0 /**< Shift value for QSPI_INV */ 661 #define _QSPI_WRPROTCTRL_INV_MASK 0x1UL /**< Bit mask for QSPI_INV */ 662 #define _QSPI_WRPROTCTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRPROTCTRL */ 663 #define QSPI_WRPROTCTRL_INV_DEFAULT (_QSPI_WRPROTCTRL_INV_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_WRPROTCTRL */ 664 #define QSPI_WRPROTCTRL_ENB (0x1UL << 1) /**< Write Protection Enable Bit */ 665 #define _QSPI_WRPROTCTRL_ENB_SHIFT 1 /**< Shift value for QSPI_ENB */ 666 #define _QSPI_WRPROTCTRL_ENB_MASK 0x2UL /**< Bit mask for QSPI_ENB */ 667 #define _QSPI_WRPROTCTRL_ENB_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRPROTCTRL */ 668 #define QSPI_WRPROTCTRL_ENB_DEFAULT (_QSPI_WRPROTCTRL_ENB_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_WRPROTCTRL */ 669 670 /* Bit fields for QSPI INDIRECTREADXFERCTRL */ 671 #define _QSPI_INDIRECTREADXFERCTRL_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTREADXFERCTRL */ 672 #define _QSPI_INDIRECTREADXFERCTRL_MASK 0x000000FFUL /**< Mask for QSPI_INDIRECTREADXFERCTRL */ 673 #define QSPI_INDIRECTREADXFERCTRL_START (0x1UL << 0) /**< Start Indirect Read */ 674 #define _QSPI_INDIRECTREADXFERCTRL_START_SHIFT 0 /**< Shift value for QSPI_START */ 675 #define _QSPI_INDIRECTREADXFERCTRL_START_MASK 0x1UL /**< Bit mask for QSPI_START */ 676 #define _QSPI_INDIRECTREADXFERCTRL_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ 677 #define QSPI_INDIRECTREADXFERCTRL_START_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_START_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ 678 #define QSPI_INDIRECTREADXFERCTRL_CANCEL (0x1UL << 1) /**< Cancel Indirect Read */ 679 #define _QSPI_INDIRECTREADXFERCTRL_CANCEL_SHIFT 1 /**< Shift value for QSPI_CANCEL */ 680 #define _QSPI_INDIRECTREADXFERCTRL_CANCEL_MASK 0x2UL /**< Bit mask for QSPI_CANCEL */ 681 #define _QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ 682 #define QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ 683 #define QSPI_INDIRECTREADXFERCTRL_RDSTATUS (0x1UL << 2) /**< Indirect Read Status */ 684 #define _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_SHIFT 2 /**< Shift value for QSPI_RDSTATUS */ 685 #define _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_MASK 0x4UL /**< Bit mask for QSPI_RDSTATUS */ 686 #define _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ 687 #define QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ 688 #define QSPI_INDIRECTREADXFERCTRL_SRAMFULL (0x1UL << 3) /**< SRAM Full */ 689 #define _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_SHIFT 3 /**< Shift value for QSPI_SRAMFULL */ 690 #define _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_MASK 0x8UL /**< Bit mask for QSPI_SRAMFULL */ 691 #define _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ 692 #define QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ 693 #define QSPI_INDIRECTREADXFERCTRL_RDQUEUED (0x1UL << 4) /**< Two Indirect Read Operations Have Been Queued */ 694 #define _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_SHIFT 4 /**< Shift value for QSPI_RDQUEUED */ 695 #define _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_MASK 0x10UL /**< Bit mask for QSPI_RDQUEUED */ 696 #define _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ 697 #define QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT << 4) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ 698 #define QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS (0x1UL << 5) /**< Indirect Completion Status */ 699 #define _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_SHIFT 5 /**< Shift value for QSPI_INDOPSDONESTATUS */ 700 #define _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_MASK 0x20UL /**< Bit mask for QSPI_INDOPSDONESTATUS */ 701 #define _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ 702 #define QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ 703 #define _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_SHIFT 6 /**< Shift value for QSPI_NUMINDOPSDONE */ 704 #define _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_MASK 0xC0UL /**< Bit mask for QSPI_NUMINDOPSDONE */ 705 #define _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ 706 #define QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT << 6) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */ 707 708 /* Bit fields for QSPI INDIRECTREADXFERWATERMARK */ 709 #define _QSPI_INDIRECTREADXFERWATERMARK_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTREADXFERWATERMARK */ 710 #define _QSPI_INDIRECTREADXFERWATERMARK_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTREADXFERWATERMARK */ 711 #define _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_SHIFT 0 /**< Shift value for QSPI_LEVEL */ 712 #define _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_LEVEL */ 713 #define _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERWATERMARK */ 714 #define QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT (_QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERWATERMARK */ 715 716 /* Bit fields for QSPI INDIRECTREADXFERSTART */ 717 #define _QSPI_INDIRECTREADXFERSTART_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTREADXFERSTART */ 718 #define _QSPI_INDIRECTREADXFERSTART_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTREADXFERSTART */ 719 #define _QSPI_INDIRECTREADXFERSTART_ADDR_SHIFT 0 /**< Shift value for QSPI_ADDR */ 720 #define _QSPI_INDIRECTREADXFERSTART_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_ADDR */ 721 #define _QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERSTART */ 722 #define QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT (_QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERSTART */ 723 724 /* Bit fields for QSPI INDIRECTREADXFERNUMBYTES */ 725 #define _QSPI_INDIRECTREADXFERNUMBYTES_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTREADXFERNUMBYTES */ 726 #define _QSPI_INDIRECTREADXFERNUMBYTES_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTREADXFERNUMBYTES */ 727 #define _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_SHIFT 0 /**< Shift value for QSPI_VALUE */ 728 #define _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_VALUE */ 729 #define _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERNUMBYTES */ 730 #define QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT (_QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERNUMBYTES */ 731 732 /* Bit fields for QSPI INDIRECTWRITEXFERCTRL */ 733 #define _QSPI_INDIRECTWRITEXFERCTRL_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTWRITEXFERCTRL */ 734 #define _QSPI_INDIRECTWRITEXFERCTRL_MASK 0x000000F7UL /**< Mask for QSPI_INDIRECTWRITEXFERCTRL */ 735 #define QSPI_INDIRECTWRITEXFERCTRL_START (0x1UL << 0) /**< Start Indirect Write */ 736 #define _QSPI_INDIRECTWRITEXFERCTRL_START_SHIFT 0 /**< Shift value for QSPI_START */ 737 #define _QSPI_INDIRECTWRITEXFERCTRL_START_MASK 0x1UL /**< Bit mask for QSPI_START */ 738 #define _QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ 739 #define QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ 740 #define QSPI_INDIRECTWRITEXFERCTRL_CANCEL (0x1UL << 1) /**< Cancel Indirect Write */ 741 #define _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_SHIFT 1 /**< Shift value for QSPI_CANCEL */ 742 #define _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_MASK 0x2UL /**< Bit mask for QSPI_CANCEL */ 743 #define _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ 744 #define QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ 745 #define QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS (0x1UL << 2) /**< Indirect Write Status */ 746 #define _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_SHIFT 2 /**< Shift value for QSPI_WRSTATUS */ 747 #define _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_MASK 0x4UL /**< Bit mask for QSPI_WRSTATUS */ 748 #define _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ 749 #define QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ 750 #define QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED (0x1UL << 4) /**< Two Indirect Write Operations Have Been Queued */ 751 #define _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_SHIFT 4 /**< Shift value for QSPI_WRQUEUED */ 752 #define _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_MASK 0x10UL /**< Bit mask for QSPI_WRQUEUED */ 753 #define _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ 754 #define QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT << 4) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ 755 #define QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS (0x1UL << 5) /**< Indirect Completion Status */ 756 #define _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_SHIFT 5 /**< Shift value for QSPI_INDOPSDONESTATUS */ 757 #define _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_MASK 0x20UL /**< Bit mask for QSPI_INDOPSDONESTATUS */ 758 #define _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ 759 #define QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ 760 #define _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_SHIFT 6 /**< Shift value for QSPI_NUMINDOPSDONE */ 761 #define _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_MASK 0xC0UL /**< Bit mask for QSPI_NUMINDOPSDONE */ 762 #define _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ 763 #define QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT << 6) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */ 764 765 /* Bit fields for QSPI INDIRECTWRITEXFERWATERMARK */ 766 #define _QSPI_INDIRECTWRITEXFERWATERMARK_RESETVALUE 0xFFFFFFFFUL /**< Default value for QSPI_INDIRECTWRITEXFERWATERMARK */ 767 #define _QSPI_INDIRECTWRITEXFERWATERMARK_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTWRITEXFERWATERMARK */ 768 #define _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_SHIFT 0 /**< Shift value for QSPI_LEVEL */ 769 #define _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_LEVEL */ 770 #define _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERWATERMARK */ 771 #define QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT (_QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERWATERMARK */ 772 773 /* Bit fields for QSPI INDIRECTWRITEXFERSTART */ 774 #define _QSPI_INDIRECTWRITEXFERSTART_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTWRITEXFERSTART */ 775 #define _QSPI_INDIRECTWRITEXFERSTART_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTWRITEXFERSTART */ 776 #define _QSPI_INDIRECTWRITEXFERSTART_ADDR_SHIFT 0 /**< Shift value for QSPI_ADDR */ 777 #define _QSPI_INDIRECTWRITEXFERSTART_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_ADDR */ 778 #define _QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERSTART */ 779 #define QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT (_QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERSTART */ 780 781 /* Bit fields for QSPI INDIRECTWRITEXFERNUMBYTES */ 782 #define _QSPI_INDIRECTWRITEXFERNUMBYTES_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTWRITEXFERNUMBYTES */ 783 #define _QSPI_INDIRECTWRITEXFERNUMBYTES_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTWRITEXFERNUMBYTES */ 784 #define _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_SHIFT 0 /**< Shift value for QSPI_VALUE */ 785 #define _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_VALUE */ 786 #define _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERNUMBYTES */ 787 #define QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT (_QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERNUMBYTES */ 788 789 /* Bit fields for QSPI INDIRECTTRIGGERADDRRANGE */ 790 #define _QSPI_INDIRECTTRIGGERADDRRANGE_RESETVALUE 0x00000004UL /**< Default value for QSPI_INDIRECTTRIGGERADDRRANGE */ 791 #define _QSPI_INDIRECTTRIGGERADDRRANGE_MASK 0x0000000FUL /**< Mask for QSPI_INDIRECTTRIGGERADDRRANGE */ 792 #define _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_SHIFT 0 /**< Shift value for QSPI_INDRANGEWIDTH */ 793 #define _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_MASK 0xFUL /**< Bit mask for QSPI_INDRANGEWIDTH */ 794 #define _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT 0x00000004UL /**< Mode DEFAULT for QSPI_INDIRECTTRIGGERADDRRANGE */ 795 #define QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT (_QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTTRIGGERADDRRANGE */ 796 797 /* Bit fields for QSPI FLASHCOMMANDCTRLMEM */ 798 #define _QSPI_FLASHCOMMANDCTRLMEM_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHCOMMANDCTRLMEM */ 799 #define _QSPI_FLASHCOMMANDCTRLMEM_MASK 0x1FF7FF03UL /**< Mask for QSPI_FLASHCOMMANDCTRLMEM */ 800 #define QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ (0x1UL << 0) /**< Trigger the Memory Bank Data Request */ 801 #define _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_SHIFT 0 /**< Shift value for QSPI_TRIGGERMEMBANKREQ */ 802 #define _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_MASK 0x1UL /**< Bit mask for QSPI_TRIGGERMEMBANKREQ */ 803 #define _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ 804 #define QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT (_QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ 805 #define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS (0x1UL << 1) /**< Memory Bank Data Request in Progress */ 806 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_SHIFT 1 /**< Shift value for QSPI_MEMBANKREQINPROGRESS */ 807 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_MASK 0x2UL /**< Bit mask for QSPI_MEMBANKREQINPROGRESS */ 808 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ 809 #define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT (_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ 810 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_SHIFT 8 /**< Shift value for QSPI_MEMBANKREADDATA */ 811 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_MASK 0xFF00UL /**< Bit mask for QSPI_MEMBANKREADDATA */ 812 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ 813 #define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT (_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ 814 #define _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_SHIFT 16 /**< Shift value for QSPI_NBOFSTIGREADBYTES */ 815 #define _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_MASK 0x70000UL /**< Bit mask for QSPI_NBOFSTIGREADBYTES */ 816 #define _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ 817 #define QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT (_QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ 818 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_SHIFT 20 /**< Shift value for QSPI_MEMBANKADDR */ 819 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_MASK 0x1FF00000UL /**< Bit mask for QSPI_MEMBANKADDR */ 820 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ 821 #define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT (_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT << 20) /**< Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */ 822 823 /* Bit fields for QSPI FLASHCMDCTRL */ 824 #define _QSPI_FLASHCMDCTRL_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHCMDCTRL */ 825 #define _QSPI_FLASHCMDCTRL_MASK 0xFFFFFF87UL /**< Mask for QSPI_FLASHCMDCTRL */ 826 #define QSPI_FLASHCMDCTRL_CMDEXEC (0x1UL << 0) /**< Execute the Command */ 827 #define _QSPI_FLASHCMDCTRL_CMDEXEC_SHIFT 0 /**< Shift value for QSPI_CMDEXEC */ 828 #define _QSPI_FLASHCMDCTRL_CMDEXEC_MASK 0x1UL /**< Bit mask for QSPI_CMDEXEC */ 829 #define _QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ 830 #define QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT (_QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ 831 #define QSPI_FLASHCMDCTRL_CMDEXECSTATUS (0x1UL << 1) /**< Command Execution in Progress */ 832 #define _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_SHIFT 1 /**< Shift value for QSPI_CMDEXECSTATUS */ 833 #define _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_MASK 0x2UL /**< Bit mask for QSPI_CMDEXECSTATUS */ 834 #define _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ 835 #define QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT (_QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ 836 #define QSPI_FLASHCMDCTRL_STIGMEMBANKEN (0x1UL << 2) /**< STIG Memory Bank Enable Bit */ 837 #define _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_SHIFT 2 /**< Shift value for QSPI_STIGMEMBANKEN */ 838 #define _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_MASK 0x4UL /**< Bit mask for QSPI_STIGMEMBANKEN */ 839 #define _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ 840 #define QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT (_QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ 841 #define _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_SHIFT 7 /**< Shift value for QSPI_NUMDUMMYCYCLES */ 842 #define _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_MASK 0xF80UL /**< Bit mask for QSPI_NUMDUMMYCYCLES */ 843 #define _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ 844 #define QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT (_QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT << 7) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ 845 #define _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_SHIFT 12 /**< Shift value for QSPI_NUMWRDATABYTES */ 846 #define _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_MASK 0x7000UL /**< Bit mask for QSPI_NUMWRDATABYTES */ 847 #define _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ 848 #define QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT (_QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ 849 #define QSPI_FLASHCMDCTRL_ENBWRITEDATA (0x1UL << 15) /**< Write Data Enable */ 850 #define _QSPI_FLASHCMDCTRL_ENBWRITEDATA_SHIFT 15 /**< Shift value for QSPI_ENBWRITEDATA */ 851 #define _QSPI_FLASHCMDCTRL_ENBWRITEDATA_MASK 0x8000UL /**< Bit mask for QSPI_ENBWRITEDATA */ 852 #define _QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ 853 #define QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT (_QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT << 15) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ 854 #define _QSPI_FLASHCMDCTRL_NUMADDRBYTES_SHIFT 16 /**< Shift value for QSPI_NUMADDRBYTES */ 855 #define _QSPI_FLASHCMDCTRL_NUMADDRBYTES_MASK 0x30000UL /**< Bit mask for QSPI_NUMADDRBYTES */ 856 #define _QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ 857 #define QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT (_QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ 858 #define QSPI_FLASHCMDCTRL_ENBMODEBIT (0x1UL << 18) /**< Mode Bit Enable */ 859 #define _QSPI_FLASHCMDCTRL_ENBMODEBIT_SHIFT 18 /**< Shift value for QSPI_ENBMODEBIT */ 860 #define _QSPI_FLASHCMDCTRL_ENBMODEBIT_MASK 0x40000UL /**< Bit mask for QSPI_ENBMODEBIT */ 861 #define _QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ 862 #define QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT (_QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT << 18) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ 863 #define QSPI_FLASHCMDCTRL_ENBCOMDADDR (0x1UL << 19) /**< Command Address Enable */ 864 #define _QSPI_FLASHCMDCTRL_ENBCOMDADDR_SHIFT 19 /**< Shift value for QSPI_ENBCOMDADDR */ 865 #define _QSPI_FLASHCMDCTRL_ENBCOMDADDR_MASK 0x80000UL /**< Bit mask for QSPI_ENBCOMDADDR */ 866 #define _QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ 867 #define QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT (_QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT << 19) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ 868 #define _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_SHIFT 20 /**< Shift value for QSPI_NUMRDDATABYTES */ 869 #define _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_MASK 0x700000UL /**< Bit mask for QSPI_NUMRDDATABYTES */ 870 #define _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ 871 #define QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT (_QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT << 20) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ 872 #define QSPI_FLASHCMDCTRL_ENBREADDATA (0x1UL << 23) /**< Read Data Enable */ 873 #define _QSPI_FLASHCMDCTRL_ENBREADDATA_SHIFT 23 /**< Shift value for QSPI_ENBREADDATA */ 874 #define _QSPI_FLASHCMDCTRL_ENBREADDATA_MASK 0x800000UL /**< Bit mask for QSPI_ENBREADDATA */ 875 #define _QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ 876 #define QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT (_QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT << 23) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ 877 #define _QSPI_FLASHCMDCTRL_CMDOPCODE_SHIFT 24 /**< Shift value for QSPI_CMDOPCODE */ 878 #define _QSPI_FLASHCMDCTRL_CMDOPCODE_MASK 0xFF000000UL /**< Bit mask for QSPI_CMDOPCODE */ 879 #define _QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */ 880 #define QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT (_QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */ 881 882 /* Bit fields for QSPI FLASHCMDADDR */ 883 #define _QSPI_FLASHCMDADDR_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHCMDADDR */ 884 #define _QSPI_FLASHCMDADDR_MASK 0xFFFFFFFFUL /**< Mask for QSPI_FLASHCMDADDR */ 885 #define _QSPI_FLASHCMDADDR_ADDR_SHIFT 0 /**< Shift value for QSPI_ADDR */ 886 #define _QSPI_FLASHCMDADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_ADDR */ 887 #define _QSPI_FLASHCMDADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDADDR */ 888 #define QSPI_FLASHCMDADDR_ADDR_DEFAULT (_QSPI_FLASHCMDADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHCMDADDR */ 889 890 /* Bit fields for QSPI FLASHRDDATALOWER */ 891 #define _QSPI_FLASHRDDATALOWER_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHRDDATALOWER */ 892 #define _QSPI_FLASHRDDATALOWER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_FLASHRDDATALOWER */ 893 #define _QSPI_FLASHRDDATALOWER_DATA_SHIFT 0 /**< Shift value for QSPI_DATA */ 894 #define _QSPI_FLASHRDDATALOWER_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_DATA */ 895 #define _QSPI_FLASHRDDATALOWER_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHRDDATALOWER */ 896 #define QSPI_FLASHRDDATALOWER_DATA_DEFAULT (_QSPI_FLASHRDDATALOWER_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHRDDATALOWER */ 897 898 /* Bit fields for QSPI FLASHRDDATAUPPER */ 899 #define _QSPI_FLASHRDDATAUPPER_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHRDDATAUPPER */ 900 #define _QSPI_FLASHRDDATAUPPER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_FLASHRDDATAUPPER */ 901 #define _QSPI_FLASHRDDATAUPPER_DATA_SHIFT 0 /**< Shift value for QSPI_DATA */ 902 #define _QSPI_FLASHRDDATAUPPER_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_DATA */ 903 #define _QSPI_FLASHRDDATAUPPER_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHRDDATAUPPER */ 904 #define QSPI_FLASHRDDATAUPPER_DATA_DEFAULT (_QSPI_FLASHRDDATAUPPER_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHRDDATAUPPER */ 905 906 /* Bit fields for QSPI FLASHWRDATALOWER */ 907 #define _QSPI_FLASHWRDATALOWER_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHWRDATALOWER */ 908 #define _QSPI_FLASHWRDATALOWER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_FLASHWRDATALOWER */ 909 #define _QSPI_FLASHWRDATALOWER_DATA_SHIFT 0 /**< Shift value for QSPI_DATA */ 910 #define _QSPI_FLASHWRDATALOWER_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_DATA */ 911 #define _QSPI_FLASHWRDATALOWER_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHWRDATALOWER */ 912 #define QSPI_FLASHWRDATALOWER_DATA_DEFAULT (_QSPI_FLASHWRDATALOWER_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHWRDATALOWER */ 913 914 /* Bit fields for QSPI FLASHWRDATAUPPER */ 915 #define _QSPI_FLASHWRDATAUPPER_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHWRDATAUPPER */ 916 #define _QSPI_FLASHWRDATAUPPER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_FLASHWRDATAUPPER */ 917 #define _QSPI_FLASHWRDATAUPPER_DATA_SHIFT 0 /**< Shift value for QSPI_DATA */ 918 #define _QSPI_FLASHWRDATAUPPER_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_DATA */ 919 #define _QSPI_FLASHWRDATAUPPER_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHWRDATAUPPER */ 920 #define QSPI_FLASHWRDATAUPPER_DATA_DEFAULT (_QSPI_FLASHWRDATAUPPER_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHWRDATAUPPER */ 921 922 /* Bit fields for QSPI POLLINGFLASHSTATUS */ 923 #define _QSPI_POLLINGFLASHSTATUS_RESETVALUE 0x00000000UL /**< Default value for QSPI_POLLINGFLASHSTATUS */ 924 #define _QSPI_POLLINGFLASHSTATUS_MASK 0x000F01FFUL /**< Mask for QSPI_POLLINGFLASHSTATUS */ 925 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_SHIFT 0 /**< Shift value for QSPI_DEVICESTATUS */ 926 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_MASK 0xFFUL /**< Bit mask for QSPI_DEVICESTATUS */ 927 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_POLLINGFLASHSTATUS */ 928 #define QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT (_QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_POLLINGFLASHSTATUS */ 929 #define QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID (0x1UL << 8) /**< Device Status Valid */ 930 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_SHIFT 8 /**< Shift value for QSPI_DEVICESTATUSVALID */ 931 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_MASK 0x100UL /**< Bit mask for QSPI_DEVICESTATUSVALID */ 932 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_POLLINGFLASHSTATUS */ 933 #define QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT (_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_POLLINGFLASHSTATUS */ 934 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_SHIFT 16 /**< Shift value for QSPI_DEVICESTATUSNBDUMMY */ 935 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_MASK 0xF0000UL /**< Bit mask for QSPI_DEVICESTATUSNBDUMMY */ 936 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_POLLINGFLASHSTATUS */ 937 #define QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT (_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_POLLINGFLASHSTATUS */ 938 939 /* Bit fields for QSPI PHYCONFIGURATION */ 940 #define _QSPI_PHYCONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for QSPI_PHYCONFIGURATION */ 941 #define _QSPI_PHYCONFIGURATION_MASK 0x807F007FUL /**< Mask for QSPI_PHYCONFIGURATION */ 942 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_SHIFT 0 /**< Shift value for QSPI_PHYCONFIGRXDLLDELAY */ 943 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_MASK 0x7FUL /**< Bit mask for QSPI_PHYCONFIGRXDLLDELAY */ 944 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_PHYCONFIGURATION */ 945 #define QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT (_QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_PHYCONFIGURATION */ 946 #define _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_SHIFT 16 /**< Shift value for QSPI_PHYCONFIGTXDLLDELAY */ 947 #define _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_MASK 0x7F0000UL /**< Bit mask for QSPI_PHYCONFIGTXDLLDELAY */ 948 #define _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_PHYCONFIGURATION */ 949 #define QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT (_QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_PHYCONFIGURATION */ 950 #define QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC (0x1UL << 31) /**< PHY Config Resync */ 951 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_SHIFT 31 /**< Shift value for QSPI_PHYCONFIGRESYNC */ 952 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_MASK 0x80000000UL /**< Bit mask for QSPI_PHYCONFIGRESYNC */ 953 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_PHYCONFIGURATION */ 954 #define QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT (_QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT << 31) /**< Shifted mode DEFAULT for QSPI_PHYCONFIGURATION */ 955 956 /* Bit fields for QSPI OPCODEEXTLOWER */ 957 #define _QSPI_OPCODEEXTLOWER_RESETVALUE 0x13EDFA00UL /**< Default value for QSPI_OPCODEEXTLOWER */ 958 #define _QSPI_OPCODEEXTLOWER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_OPCODEEXTLOWER */ 959 #define _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_SHIFT 0 /**< Shift value for QSPI_EXTSTIGOPCODE */ 960 #define _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_MASK 0xFFUL /**< Bit mask for QSPI_EXTSTIGOPCODE */ 961 #define _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_OPCODEEXTLOWER */ 962 #define QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT (_QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER */ 963 #define _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_SHIFT 8 /**< Shift value for QSPI_EXTPOLLOPCODE */ 964 #define _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_MASK 0xFF00UL /**< Bit mask for QSPI_EXTPOLLOPCODE */ 965 #define _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT 0x000000FAUL /**< Mode DEFAULT for QSPI_OPCODEEXTLOWER */ 966 #define QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT (_QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER */ 967 #define _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_SHIFT 16 /**< Shift value for QSPI_EXTWRITEOPCODE */ 968 #define _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_MASK 0xFF0000UL /**< Bit mask for QSPI_EXTWRITEOPCODE */ 969 #define _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT 0x000000EDUL /**< Mode DEFAULT for QSPI_OPCODEEXTLOWER */ 970 #define QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT (_QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER */ 971 #define _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_SHIFT 24 /**< Shift value for QSPI_EXTREADOPCODE */ 972 #define _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_MASK 0xFF000000UL /**< Bit mask for QSPI_EXTREADOPCODE */ 973 #define _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT 0x00000013UL /**< Mode DEFAULT for QSPI_OPCODEEXTLOWER */ 974 #define QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT (_QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER */ 975 976 /* Bit fields for QSPI OPCODEEXTUPPER */ 977 #define _QSPI_OPCODEEXTUPPER_RESETVALUE 0x06F90000UL /**< Default value for QSPI_OPCODEEXTUPPER */ 978 #define _QSPI_OPCODEEXTUPPER_MASK 0xFFFF0000UL /**< Mask for QSPI_OPCODEEXTUPPER */ 979 #define _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_SHIFT 16 /**< Shift value for QSPI_EXTWELOPCODE */ 980 #define _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_MASK 0xFF0000UL /**< Bit mask for QSPI_EXTWELOPCODE */ 981 #define _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT 0x000000F9UL /**< Mode DEFAULT for QSPI_OPCODEEXTUPPER */ 982 #define QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT (_QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTUPPER */ 983 #define _QSPI_OPCODEEXTUPPER_WELOPCODE_SHIFT 24 /**< Shift value for QSPI_WELOPCODE */ 984 #define _QSPI_OPCODEEXTUPPER_WELOPCODE_MASK 0xFF000000UL /**< Bit mask for QSPI_WELOPCODE */ 985 #define _QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT 0x00000006UL /**< Mode DEFAULT for QSPI_OPCODEEXTUPPER */ 986 #define QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT (_QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTUPPER */ 987 988 /* Bit fields for QSPI MODULEID */ 989 #define _QSPI_MODULEID_RESETVALUE 0x00000200UL /**< Default value for QSPI_MODULEID */ 990 #define _QSPI_MODULEID_MASK 0xFFFFFF03UL /**< Mask for QSPI_MODULEID */ 991 #define _QSPI_MODULEID_CONF_SHIFT 0 /**< Shift value for QSPI_CONF */ 992 #define _QSPI_MODULEID_CONF_MASK 0x3UL /**< Bit mask for QSPI_CONF */ 993 #define _QSPI_MODULEID_CONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODULEID */ 994 #define QSPI_MODULEID_CONF_DEFAULT (_QSPI_MODULEID_CONF_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_MODULEID */ 995 #define _QSPI_MODULEID_MODULEID_SHIFT 8 /**< Shift value for QSPI_MODULEID */ 996 #define _QSPI_MODULEID_MODULEID_MASK 0xFFFF00UL /**< Bit mask for QSPI_MODULEID */ 997 #define _QSPI_MODULEID_MODULEID_DEFAULT 0x00000002UL /**< Mode DEFAULT for QSPI_MODULEID */ 998 #define QSPI_MODULEID_MODULEID_DEFAULT (_QSPI_MODULEID_MODULEID_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_MODULEID */ 999 #define _QSPI_MODULEID_FIXPATCH_SHIFT 24 /**< Shift value for QSPI_FIXPATCH */ 1000 #define _QSPI_MODULEID_FIXPATCH_MASK 0xFF000000UL /**< Bit mask for QSPI_FIXPATCH */ 1001 #define _QSPI_MODULEID_FIXPATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODULEID */ 1002 #define QSPI_MODULEID_FIXPATCH_DEFAULT (_QSPI_MODULEID_FIXPATCH_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_MODULEID */ 1003 1004 /* Bit fields for QSPI ROUTEPEN */ 1005 #define _QSPI_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for QSPI_ROUTEPEN */ 1006 #define _QSPI_ROUTEPEN_MASK 0x00007FE7UL /**< Mask for QSPI_ROUTEPEN */ 1007 #define QSPI_ROUTEPEN_SCLKPEN (0x1UL << 0) /**< SCLK Pin Enable */ 1008 #define _QSPI_ROUTEPEN_SCLKPEN_SHIFT 0 /**< Shift value for QSPI_SCLKPEN */ 1009 #define _QSPI_ROUTEPEN_SCLKPEN_MASK 0x1UL /**< Bit mask for QSPI_SCLKPEN */ 1010 #define _QSPI_ROUTEPEN_SCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ 1011 #define QSPI_ROUTEPEN_SCLKPEN_DEFAULT (_QSPI_ROUTEPEN_SCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ 1012 #define QSPI_ROUTEPEN_CS0PEN (0x1UL << 1) /**< CS0 Pin Enable */ 1013 #define _QSPI_ROUTEPEN_CS0PEN_SHIFT 1 /**< Shift value for QSPI_CS0PEN */ 1014 #define _QSPI_ROUTEPEN_CS0PEN_MASK 0x2UL /**< Bit mask for QSPI_CS0PEN */ 1015 #define _QSPI_ROUTEPEN_CS0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ 1016 #define QSPI_ROUTEPEN_CS0PEN_DEFAULT (_QSPI_ROUTEPEN_CS0PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ 1017 #define QSPI_ROUTEPEN_CS1PEN (0x1UL << 2) /**< CS1 Pin Enable */ 1018 #define _QSPI_ROUTEPEN_CS1PEN_SHIFT 2 /**< Shift value for QSPI_CS1PEN */ 1019 #define _QSPI_ROUTEPEN_CS1PEN_MASK 0x4UL /**< Bit mask for QSPI_CS1PEN */ 1020 #define _QSPI_ROUTEPEN_CS1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ 1021 #define QSPI_ROUTEPEN_CS1PEN_DEFAULT (_QSPI_ROUTEPEN_CS1PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ 1022 #define QSPI_ROUTEPEN_DQ0PEN (0x1UL << 5) /**< DQ0 Pin Enable */ 1023 #define _QSPI_ROUTEPEN_DQ0PEN_SHIFT 5 /**< Shift value for QSPI_DQ0PEN */ 1024 #define _QSPI_ROUTEPEN_DQ0PEN_MASK 0x20UL /**< Bit mask for QSPI_DQ0PEN */ 1025 #define _QSPI_ROUTEPEN_DQ0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ 1026 #define QSPI_ROUTEPEN_DQ0PEN_DEFAULT (_QSPI_ROUTEPEN_DQ0PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ 1027 #define QSPI_ROUTEPEN_DQ1PEN (0x1UL << 6) /**< DQ1 Pin Enable */ 1028 #define _QSPI_ROUTEPEN_DQ1PEN_SHIFT 6 /**< Shift value for QSPI_DQ1PEN */ 1029 #define _QSPI_ROUTEPEN_DQ1PEN_MASK 0x40UL /**< Bit mask for QSPI_DQ1PEN */ 1030 #define _QSPI_ROUTEPEN_DQ1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ 1031 #define QSPI_ROUTEPEN_DQ1PEN_DEFAULT (_QSPI_ROUTEPEN_DQ1PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ 1032 #define QSPI_ROUTEPEN_DQ2PEN (0x1UL << 7) /**< DQ2 Pin Enable */ 1033 #define _QSPI_ROUTEPEN_DQ2PEN_SHIFT 7 /**< Shift value for QSPI_DQ2PEN */ 1034 #define _QSPI_ROUTEPEN_DQ2PEN_MASK 0x80UL /**< Bit mask for QSPI_DQ2PEN */ 1035 #define _QSPI_ROUTEPEN_DQ2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ 1036 #define QSPI_ROUTEPEN_DQ2PEN_DEFAULT (_QSPI_ROUTEPEN_DQ2PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ 1037 #define QSPI_ROUTEPEN_DQ3PEN (0x1UL << 8) /**< DQ3 Pin Enable */ 1038 #define _QSPI_ROUTEPEN_DQ3PEN_SHIFT 8 /**< Shift value for QSPI_DQ3PEN */ 1039 #define _QSPI_ROUTEPEN_DQ3PEN_MASK 0x100UL /**< Bit mask for QSPI_DQ3PEN */ 1040 #define _QSPI_ROUTEPEN_DQ3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ 1041 #define QSPI_ROUTEPEN_DQ3PEN_DEFAULT (_QSPI_ROUTEPEN_DQ3PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ 1042 #define QSPI_ROUTEPEN_DQ4PEN (0x1UL << 9) /**< DQ4 Pin Enable */ 1043 #define _QSPI_ROUTEPEN_DQ4PEN_SHIFT 9 /**< Shift value for QSPI_DQ4PEN */ 1044 #define _QSPI_ROUTEPEN_DQ4PEN_MASK 0x200UL /**< Bit mask for QSPI_DQ4PEN */ 1045 #define _QSPI_ROUTEPEN_DQ4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ 1046 #define QSPI_ROUTEPEN_DQ4PEN_DEFAULT (_QSPI_ROUTEPEN_DQ4PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ 1047 #define QSPI_ROUTEPEN_DQ5PEN (0x1UL << 10) /**< DQ5 Pin Enable */ 1048 #define _QSPI_ROUTEPEN_DQ5PEN_SHIFT 10 /**< Shift value for QSPI_DQ5PEN */ 1049 #define _QSPI_ROUTEPEN_DQ5PEN_MASK 0x400UL /**< Bit mask for QSPI_DQ5PEN */ 1050 #define _QSPI_ROUTEPEN_DQ5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ 1051 #define QSPI_ROUTEPEN_DQ5PEN_DEFAULT (_QSPI_ROUTEPEN_DQ5PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ 1052 #define QSPI_ROUTEPEN_DQ6PEN (0x1UL << 11) /**< DQ6 Pin Enable */ 1053 #define _QSPI_ROUTEPEN_DQ6PEN_SHIFT 11 /**< Shift value for QSPI_DQ6PEN */ 1054 #define _QSPI_ROUTEPEN_DQ6PEN_MASK 0x800UL /**< Bit mask for QSPI_DQ6PEN */ 1055 #define _QSPI_ROUTEPEN_DQ6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ 1056 #define QSPI_ROUTEPEN_DQ6PEN_DEFAULT (_QSPI_ROUTEPEN_DQ6PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ 1057 #define QSPI_ROUTEPEN_DQ7PEN (0x1UL << 12) /**< DQ7 Pin Enable */ 1058 #define _QSPI_ROUTEPEN_DQ7PEN_SHIFT 12 /**< Shift value for QSPI_DQ7PEN */ 1059 #define _QSPI_ROUTEPEN_DQ7PEN_MASK 0x1000UL /**< Bit mask for QSPI_DQ7PEN */ 1060 #define _QSPI_ROUTEPEN_DQ7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ 1061 #define QSPI_ROUTEPEN_DQ7PEN_DEFAULT (_QSPI_ROUTEPEN_DQ7PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ 1062 #define QSPI_ROUTEPEN_DQSPEN (0x1UL << 13) /**< DQS Pin Enable */ 1063 #define _QSPI_ROUTEPEN_DQSPEN_SHIFT 13 /**< Shift value for QSPI_DQSPEN */ 1064 #define _QSPI_ROUTEPEN_DQSPEN_MASK 0x2000UL /**< Bit mask for QSPI_DQSPEN */ 1065 #define _QSPI_ROUTEPEN_DQSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ 1066 #define QSPI_ROUTEPEN_DQSPEN_DEFAULT (_QSPI_ROUTEPEN_DQSPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ 1067 #define QSPI_ROUTEPEN_SCLKINPEN (0x1UL << 14) /**< SCLKIN Pin Enable */ 1068 #define _QSPI_ROUTEPEN_SCLKINPEN_SHIFT 14 /**< Shift value for QSPI_SCLKINPEN */ 1069 #define _QSPI_ROUTEPEN_SCLKINPEN_MASK 0x4000UL /**< Bit mask for QSPI_SCLKINPEN */ 1070 #define _QSPI_ROUTEPEN_SCLKINPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */ 1071 #define QSPI_ROUTEPEN_SCLKINPEN_DEFAULT (_QSPI_ROUTEPEN_SCLKINPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */ 1072 1073 /* Bit fields for QSPI ROUTELOC0 */ 1074 #define _QSPI_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for QSPI_ROUTELOC0 */ 1075 #define _QSPI_ROUTELOC0_MASK 0x00000003UL /**< Mask for QSPI_ROUTELOC0 */ 1076 #define _QSPI_ROUTELOC0_QSPILOC_SHIFT 0 /**< Shift value for QSPI_QSPILOC */ 1077 #define _QSPI_ROUTELOC0_QSPILOC_MASK 0x3UL /**< Bit mask for QSPI_QSPILOC */ 1078 #define _QSPI_ROUTELOC0_QSPILOC_LOC0 0x00000000UL /**< Mode LOC0 for QSPI_ROUTELOC0 */ 1079 #define _QSPI_ROUTELOC0_QSPILOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTELOC0 */ 1080 #define _QSPI_ROUTELOC0_QSPILOC_LOC1 0x00000001UL /**< Mode LOC1 for QSPI_ROUTELOC0 */ 1081 #define _QSPI_ROUTELOC0_QSPILOC_LOC2 0x00000002UL /**< Mode LOC2 for QSPI_ROUTELOC0 */ 1082 #define QSPI_ROUTELOC0_QSPILOC_LOC0 (_QSPI_ROUTELOC0_QSPILOC_LOC0 << 0) /**< Shifted mode LOC0 for QSPI_ROUTELOC0 */ 1083 #define QSPI_ROUTELOC0_QSPILOC_DEFAULT (_QSPI_ROUTELOC0_QSPILOC_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_ROUTELOC0 */ 1084 #define QSPI_ROUTELOC0_QSPILOC_LOC1 (_QSPI_ROUTELOC0_QSPILOC_LOC1 << 0) /**< Shifted mode LOC1 for QSPI_ROUTELOC0 */ 1085 #define QSPI_ROUTELOC0_QSPILOC_LOC2 (_QSPI_ROUTELOC0_QSPILOC_LOC2 << 0) /**< Shifted mode LOC2 for QSPI_ROUTELOC0 */ 1086 1087 /** @} */ 1088 /** @} End of group EFM32GG11B_QSPI */ 1089 /** @} End of group Parts */ 1090
