1 /**************************************************************************//** 2 * @file 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File 4 * for EFR32MG24A020F768IM40 5 ****************************************************************************** 6 * # License 7 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 8 ****************************************************************************** 9 * 10 * SPDX-License-Identifier: Zlib 11 * 12 * The licensor of this software is Silicon Laboratories Inc. 13 * 14 * This software is provided 'as-is', without any express or implied 15 * warranty. In no event will the authors be held liable for any damages 16 * arising from the use of this software. 17 * 18 * Permission is granted to anyone to use this software for any purpose, 19 * including commercial applications, and to alter it and redistribute it 20 * freely, subject to the following restrictions: 21 * 22 * 1. The origin of this software must not be misrepresented; you must not 23 * claim that you wrote the original software. If you use this software 24 * in a product, an acknowledgment in the product documentation would be 25 * appreciated but is not required. 26 * 2. Altered source versions must be plainly marked as such, and must not be 27 * misrepresented as being the original software. 28 * 3. This notice may not be removed or altered from any source distribution. 29 * 30 *****************************************************************************/ 31 #ifndef EFR32MG24A020F768IM40_H 32 #define EFR32MG24A020F768IM40_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /**************************************************************************//** 39 * @addtogroup Parts 40 * @{ 41 *****************************************************************************/ 42 43 /**************************************************************************//** 44 * @defgroup EFR32MG24A020F768IM40 EFR32MG24A020F768IM40 45 * @{ 46 *****************************************************************************/ 47 48 /** Interrupt Number Definition */ 49 typedef enum IRQn{ 50 /****** Cortex-M Processor Exceptions Numbers ******************************************/ 51 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ 52 HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ 53 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ 54 BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ 55 UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ 56 SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ 57 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ 58 PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ 59 SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ 60 61 /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ 62 63 SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ 64 SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ 65 SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ 66 EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ 67 TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ 68 TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ 69 TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ 70 TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ 71 TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ 72 USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ 73 USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ 74 EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ 75 EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ 76 EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ 77 EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ 78 ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ 79 BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ 80 LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ 81 SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ 82 MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ 83 LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ 84 LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ 85 LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ 86 ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ 87 GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ 88 GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ 89 I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ 90 I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ 91 EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ 92 AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ 93 BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ 94 FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ 95 FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ 96 MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ 97 PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ 98 RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ 99 RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ 100 HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ 101 SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ 102 ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ 103 ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ 104 WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ 105 WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ 106 HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ 107 HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ 108 HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ 109 CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ 110 AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ 111 IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ 112 MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ 113 DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ 114 EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ 115 DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ 116 PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ 117 SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ 118 SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ 119 SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ 120 SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ 121 KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ 122 KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ 123 M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ 124 M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ 125 FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ 126 SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ 127 SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ 128 SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ 129 SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ 130 KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ 131 RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ 132 RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ 133 VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ 134 VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ 135 AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ 136 AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ 137 } IRQn_Type; 138 139 /**************************************************************************//** 140 * @defgroup EFR32MG24A020F768IM40_Core EFR32MG24A020F768IM40 Core 141 * @{ 142 * @brief Processor and Core Peripheral Section 143 *****************************************************************************/ 144 145 #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ 146 #define __DSP_PRESENT 1U /**< Presence of DSP */ 147 #define __FPU_PRESENT 1U /**< Presence of FPU */ 148 #define __MPU_PRESENT 1U /**< Presence of MPU */ 149 #define __SAUREGION_PRESENT 1U /**< Presence of FPU */ 150 #define __TZ_PRESENT 1U /**< Presence of TrustZone */ 151 #define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ 152 #define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ 153 #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ 154 155 /** @} End of group EFR32MG24A020F768IM40_Core */ 156 157 /**************************************************************************//** 158 * @defgroup EFR32MG24A020F768IM40_Part EFR32MG24A020F768IM40 Part 159 * @{ 160 ******************************************************************************/ 161 162 /** Part number */ 163 164 /* If part number is not defined as compiler option, define it */ 165 #if !defined(EFR32MG24A020F768IM40) 166 #define EFR32MG24A020F768IM40 1 /**< FULL Part */ 167 #endif 168 169 /** Configure part number */ 170 #define PART_NUMBER "EFR32MG24A020F768IM40" /**< Part Number */ 171 172 /** Family / Line / Series / Config */ 173 #define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ 174 #define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ 175 #define _EFR_DEVICE 1 /** Product Line Identifier */ 176 #define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ 177 #define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ 178 #define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ 179 #define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ 180 #define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ 181 #define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ 182 #define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ 183 #define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ 184 #define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ 185 #define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ 186 #define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ 187 #define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ 188 #define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ 189 #define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ 190 #define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ 191 #define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ 192 #define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ 193 #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ 194 #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ 195 #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ 196 #define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ 197 #define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ 198 #define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ 199 200 /** Memory Base addresses and limits */ 201 #define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ 202 #define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ 203 #define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ 204 #define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ 205 #define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ 206 #define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ 207 #define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ 208 #define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ 209 #define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ 210 #define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ 211 #define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ 212 #define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ 213 #define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ 214 #define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ 215 #define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ 216 #define USERDATA_BITS (0xBUL) /** USERDATA used bits */ 217 #define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ 218 #define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ 219 #define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ 220 #define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ 221 #define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ 222 #define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ 223 #define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ 224 #define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ 225 #define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ 226 #define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ 227 #define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ 228 #define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ 229 #define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ 230 #define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ 231 #define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ 232 #define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ 233 #define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ 234 #define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ 235 #define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ 236 #define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ 237 #define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ 238 #define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ 239 #define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ 240 #define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ 241 #define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ 242 #define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ 243 #define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ 244 #define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ 245 #define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ 246 #define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ 247 #define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ 248 #define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ 249 #define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ 250 #define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ 251 #define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ 252 #define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ 253 #define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ 254 #define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ 255 #define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ 256 #define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ 257 258 /** Flash and SRAM limits for EFR32MG24A020F768IM40 */ 259 #define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ 260 #define FLASH_SIZE (0x000C0000UL) /**< Available Flash Memory */ 261 #define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ 262 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ 263 #define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */ 264 #define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ 265 #define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ 266 267 /* GPIO Avalibility Info */ 268 #define GPIO_PA_INDEX 0U /**< Index of port PA */ 269 #define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ 270 #define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ 271 #define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ 272 #define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ 273 #define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ 274 #define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ 275 #define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ 276 #define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ 277 #define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ 278 #define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ 279 #define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ 280 #define GPIO_PB_INDEX 1U /**< Index of port PB */ 281 #define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ 282 #define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ 283 #define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ 284 #define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ 285 #define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ 286 #define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ 287 #define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ 288 #define GPIO_PC_INDEX 2U /**< Index of port PC */ 289 #define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ 290 #define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ 291 #define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ 292 #define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ 293 #define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ 294 #define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ 295 #define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ 296 #define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ 297 #define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ 298 #define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ 299 #define GPIO_PD_INDEX 3U /**< Index of port PD */ 300 #define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ 301 #define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ 302 #define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ 303 #define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ 304 #define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ 305 #define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ 306 307 /* Fixed Resource Locations */ 308 #define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ 309 #define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ 310 #define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ 311 #define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ 312 #define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ 313 #define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ 314 #define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ 315 #define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ 316 #define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ 317 #define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ 318 #define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ 319 #define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ 320 #define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ 321 #define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ 322 #define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ 323 #define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ 324 #define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ 325 #define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ 326 #define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ 327 #define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ 328 #define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ 329 #define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ 330 #define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ 331 #define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ 332 #define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ 333 #define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ 334 #define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ 335 #define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ 336 #define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ 337 #define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ 338 #define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ 339 #define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ 340 #define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ 341 #define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ 342 #define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ 343 #define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ 344 #define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ 345 #define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ 346 #define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ 347 #define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ 348 #define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ 349 #define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ 350 #define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ 351 #define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ 352 #define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ 353 #define GPIO_THMSW_HALFSWITCH_PIN 7U /**< Pin of THMSW_HALFSWITCH.*/ 354 #define GPIO_THMSW_HALFSWITCH_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH_PRIMARY.*/ 355 #define GPIO_THMSW_HALFSWITCH_PRIMARY_PIN 9U /**< Pin of THMSW_HALFSWITCH_PRIMARY.*/ 356 #define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ 357 #define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ 358 #define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ 359 #define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ 360 #define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ 361 #define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ 362 #define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ 363 #define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ 364 #define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ 365 #define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ 366 #define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ 367 #define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ 368 #define VDAC1_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ 369 #define VDAC1_CH0_MAIN_OUT_PIN 2U /**< Pin of CH0_MAIN_OUT.*/ 370 #define VDAC1_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ 371 #define VDAC1_CH1_MAIN_OUT_PIN 3U /**< Pin of CH1_MAIN_OUT.*/ 372 373 /* Part number capabilities */ 374 #define ACMP_PRESENT /** ACMP is available in this part */ 375 #define ACMP_COUNT 2 /** 2 ACMPs available */ 376 #define BURAM_PRESENT /** BURAM is available in this part */ 377 #define BURAM_COUNT 1 /** 1 BURAMs available */ 378 #define BURTC_PRESENT /** BURTC is available in this part */ 379 #define BURTC_COUNT 1 /** 1 BURTCs available */ 380 #define CMU_PRESENT /** CMU is available in this part */ 381 #define CMU_COUNT 1 /** 1 CMUs available */ 382 #define DCDC_PRESENT /** DCDC is available in this part */ 383 #define DCDC_COUNT 1 /** 1 DCDCs available */ 384 #define DMEM_PRESENT /** DMEM is available in this part */ 385 #define DMEM_COUNT 1 /** 1 DMEMs available */ 386 #define DPLL_PRESENT /** DPLL is available in this part */ 387 #define DPLL_COUNT 1 /** 1 DPLLs available */ 388 #define EMU_PRESENT /** EMU is available in this part */ 389 #define EMU_COUNT 1 /** 1 EMUs available */ 390 #define EUSART_PRESENT /** EUSART is available in this part */ 391 #define EUSART_COUNT 2 /** 2 EUSARTs available */ 392 #define FSRCO_PRESENT /** FSRCO is available in this part */ 393 #define FSRCO_COUNT 1 /** 1 FSRCOs available */ 394 #define GPCRC_PRESENT /** GPCRC is available in this part */ 395 #define GPCRC_COUNT 1 /** 1 GPCRCs available */ 396 #define GPIO_PRESENT /** GPIO is available in this part */ 397 #define GPIO_COUNT 1 /** 1 GPIOs available */ 398 #define HFRCO_PRESENT /** HFRCO is available in this part */ 399 #define HFRCO_COUNT 1 /** 1 HFRCOs available */ 400 #define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ 401 #define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ 402 #define HFXO_PRESENT /** HFXO is available in this part */ 403 #define HFXO_COUNT 1 /** 1 HFXOs available */ 404 #define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ 405 #define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ 406 #define I2C_PRESENT /** I2C is available in this part */ 407 #define I2C_COUNT 2 /** 2 I2Cs available */ 408 #define IADC_PRESENT /** IADC is available in this part */ 409 #define IADC_COUNT 1 /** 1 IADCs available */ 410 #define ICACHE_PRESENT /** ICACHE is available in this part */ 411 #define ICACHE_COUNT 1 /** 1 ICACHEs available */ 412 #define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ 413 #define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ 414 #define LDMA_PRESENT /** LDMA is available in this part */ 415 #define LDMA_COUNT 1 /** 1 LDMAs available */ 416 #define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ 417 #define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ 418 #define LETIMER_PRESENT /** LETIMER is available in this part */ 419 #define LETIMER_COUNT 1 /** 1 LETIMERs available */ 420 #define LFRCO_PRESENT /** LFRCO is available in this part */ 421 #define LFRCO_COUNT 1 /** 1 LFRCOs available */ 422 #define LFXO_PRESENT /** LFXO is available in this part */ 423 #define LFXO_COUNT 1 /** 1 LFXOs available */ 424 #define MSC_PRESENT /** MSC is available in this part */ 425 #define MSC_COUNT 1 /** 1 MSCs available */ 426 #define PCNT_PRESENT /** PCNT is available in this part */ 427 #define PCNT_COUNT 1 /** 1 PCNTs available */ 428 #define PRS_PRESENT /** PRS is available in this part */ 429 #define PRS_COUNT 1 /** 1 PRSs available */ 430 #define RADIOAES_PRESENT /** RADIOAES is available in this part */ 431 #define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ 432 #define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ 433 #define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ 434 #define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ 435 #define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ 436 #define SMU_PRESENT /** SMU is available in this part */ 437 #define SMU_COUNT 1 /** 1 SMUs available */ 438 #define SYSCFG_PRESENT /** SYSCFG is available in this part */ 439 #define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ 440 #define SYSRTC_PRESENT /** SYSRTC is available in this part */ 441 #define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ 442 #define TIMER_PRESENT /** TIMER is available in this part */ 443 #define TIMER_COUNT 5 /** 5 TIMERs available */ 444 #define ULFRCO_PRESENT /** ULFRCO is available in this part */ 445 #define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ 446 #define USART_PRESENT /** USART is available in this part */ 447 #define USART_COUNT 1 /** 1 USARTs available */ 448 #define VDAC_PRESENT /** VDAC is available in this part */ 449 #define VDAC_COUNT 2 /** 2 VDACs available */ 450 #define WDOG_PRESENT /** WDOG is available in this part */ 451 #define WDOG_COUNT 2 /** 2 WDOGs available */ 452 #define DEVINFO_PRESENT /** DEVINFO is available in this part */ 453 #define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ 454 455 /* Include standard ARM headers for the core */ 456 #include "core_cm33.h" /* Core Header File */ 457 #include "system_efr32mg24.h" /* System Header File */ 458 459 /** @} End of group EFR32MG24A020F768IM40_Part */ 460 461 /**************************************************************************//** 462 * @defgroup EFR32MG24A020F768IM40_Peripheral_TypeDefs EFR32MG24A020F768IM40 Peripheral TypeDefs 463 * @{ 464 * @brief Device Specific Peripheral Register Structures 465 *****************************************************************************/ 466 #include "efr32mg24_scratchpad.h" 467 #include "efr32mg24_emu.h" 468 #include "efr32mg24_cmu.h" 469 #include "efr32mg24_hfrco.h" 470 #include "efr32mg24_fsrco.h" 471 #include "efr32mg24_dpll.h" 472 #include "efr32mg24_lfxo.h" 473 #include "efr32mg24_lfrco.h" 474 #include "efr32mg24_ulfrco.h" 475 #include "efr32mg24_msc.h" 476 #include "efr32mg24_icache.h" 477 #include "efr32mg24_prs.h" 478 #include "efr32mg24_gpio.h" 479 #include "efr32mg24_ldma.h" 480 #include "efr32mg24_ldmaxbar.h" 481 #include "efr32mg24_timer.h" 482 #include "efr32mg24_usart.h" 483 #include "efr32mg24_burtc.h" 484 #include "efr32mg24_i2c.h" 485 #include "efr32mg24_syscfg.h" 486 #include "efr32mg24_buram.h" 487 #include "efr32mg24_gpcrc.h" 488 #include "efr32mg24_dcdc.h" 489 #include "efr32mg24_mailbox.h" 490 #include "efr32mg24_eusart.h" 491 #include "efr32mg24_sysrtc.h" 492 #include "efr32mg24_keyscan.h" 493 #include "efr32mg24_mpahbram.h" 494 #include "efr32mg24_aes.h" 495 #include "efr32mg24_smu.h" 496 #include "efr32mg24_letimer.h" 497 #include "efr32mg24_iadc.h" 498 #include "efr32mg24_acmp.h" 499 #include "efr32mg24_vdac.h" 500 #include "efr32mg24_pcnt.h" 501 #include "efr32mg24_hfxo.h" 502 #include "efr32mg24_wdog.h" 503 #include "efr32mg24_semailbox.h" 504 #include "efr32mg24_devinfo.h" 505 506 /* Custom headers for LDMAXBAR and PRS mappings */ 507 #include "efr32mg24_prs_signals.h" 508 #include "efr32mg24_dma_descriptor.h" 509 #include "efr32mg24_ldmaxbar_defines.h" 510 511 /** @} End of group EFR32MG24A020F768IM40_Peripheral_TypeDefs */ 512 513 /**************************************************************************//** 514 * @defgroup EFR32MG24A020F768IM40_Peripheral_Base EFR32MG24A020F768IM40 Peripheral Memory Map 515 * @{ 516 *****************************************************************************/ 517 518 #define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ 519 #define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ 520 #define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ 521 #define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ 522 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ 523 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ 524 #define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ 525 #define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ 526 #define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ 527 #define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ 528 #define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ 529 #define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ 530 #define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ 531 #define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ 532 #define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ 533 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ 534 #define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ 535 #define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ 536 #define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ 537 #define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ 538 #define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ 539 #define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ 540 #define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ 541 #define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ 542 #define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ 543 #define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ 544 #define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ 545 #define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ 546 #define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ 547 #define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ 548 #define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ 549 #define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ 550 #define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ 551 #define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ 552 #define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ 553 #define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ 554 #define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ 555 #define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ 556 #define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ 557 #define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ 558 #define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ 559 #define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ 560 #define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ 561 #define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ 562 #define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ 563 #define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ 564 #define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ 565 #define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ 566 #define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ 567 #define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ 568 #define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ 569 #define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ 570 #define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ 571 #define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ 572 #define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ 573 #define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ 574 #define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ 575 #define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ 576 #define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ 577 #define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ 578 #define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ 579 #define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ 580 #define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ 581 #define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ 582 #define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ 583 #define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ 584 #define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ 585 #define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ 586 #define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ 587 #define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ 588 #define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ 589 #define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ 590 #define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ 591 #define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ 592 #define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ 593 #define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ 594 #define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ 595 #define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ 596 #define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ 597 #define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ 598 #define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ 599 #define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ 600 #define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ 601 #define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ 602 #define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ 603 #define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ 604 #define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ 605 #define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ 606 #define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ 607 #define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ 608 #define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ 609 #define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ 610 #define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ 611 #define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ 612 #define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ 613 #define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ 614 #define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ 615 #define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ 616 #define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ 617 #define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ 618 619 #if defined(SL_COMPONENT_CATALOG_PRESENT) 620 #include "sl_component_catalog.h" 621 622 #endif 623 #if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) 624 #include "sl_trustzone_secure_config.h" 625 626 #endif 627 628 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) 629 #define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ 630 #else 631 #define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ 632 #endif /* SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S */ 633 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) 634 #define EMU_BASE (EMU_S_BASE) /* EMU base address */ 635 #else 636 #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ 637 #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ 638 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) 639 #define CMU_BASE (CMU_S_BASE) /* CMU base address */ 640 #else 641 #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ 642 #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ 643 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) 644 #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ 645 #else 646 #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ 647 #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ 648 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) 649 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ 650 #else 651 #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ 652 #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ 653 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) 654 #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ 655 #else 656 #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ 657 #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ 658 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) 659 #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ 660 #else 661 #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ 662 #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ 663 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) 664 #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ 665 #else 666 #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ 667 #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ 668 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) 669 #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ 670 #else 671 #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ 672 #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ 673 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) 674 #define MSC_BASE (MSC_S_BASE) /* MSC base address */ 675 #else 676 #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ 677 #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ 678 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) 679 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ 680 #else 681 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ 682 #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ 683 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) 684 #define PRS_BASE (PRS_S_BASE) /* PRS base address */ 685 #else 686 #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ 687 #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ 688 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) 689 #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ 690 #else 691 #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ 692 #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ 693 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) 694 #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ 695 #else 696 #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ 697 #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ 698 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) 699 #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ 700 #else 701 #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ 702 #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ 703 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) 704 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ 705 #else 706 #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ 707 #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ 708 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) 709 #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ 710 #else 711 #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ 712 #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ 713 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) 714 #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ 715 #else 716 #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ 717 #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ 718 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) 719 #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ 720 #else 721 #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ 722 #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ 723 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) 724 #define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ 725 #else 726 #define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ 727 #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER4_S */ 728 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) 729 #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ 730 #else 731 #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ 732 #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ 733 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) 734 #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ 735 #else 736 #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ 737 #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ 738 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) 739 #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ 740 #else 741 #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ 742 #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ 743 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) 744 #define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ 745 #else 746 #define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ 747 #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S */ 748 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) 749 #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ 750 #else 751 #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ 752 #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ 753 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) 754 #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ 755 #else 756 #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ 757 #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ 758 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) 759 #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ 760 #else 761 #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ 762 #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ 763 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) 764 #define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ 765 #else 766 #define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ 767 #endif /* SL_TRUSTZONE_PERIPHERAL_DCDC_S */ 768 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) 769 #define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ 770 #else 771 #define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ 772 #endif /* SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S */ 773 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) 774 #define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ 775 #else 776 #define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ 777 #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART1_S */ 778 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) 779 #define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ 780 #else 781 #define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ 782 #endif /* SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S */ 783 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) 784 #define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ 785 #else 786 #define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ 787 #endif /* SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S */ 788 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) 789 #define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ 790 #else 791 #define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ 792 #endif /* SL_TRUSTZONE_PERIPHERAL_DMEM_S */ 793 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) 794 #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ 795 #else 796 #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ 797 #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ 798 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) 799 #define SMU_BASE (SMU_S_BASE) /* SMU base address */ 800 #else 801 #define SMU_BASE (SMU_S_BASE) /* SMU base address */ 802 #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ 803 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) 804 #define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ 805 #else 806 #define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ 807 #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S */ 808 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) 809 #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ 810 #else 811 #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ 812 #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ 813 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) 814 #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ 815 #else 816 #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ 817 #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ 818 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) 819 #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ 820 #else 821 #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ 822 #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ 823 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) 824 #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ 825 #else 826 #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ 827 #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ 828 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) 829 #define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ 830 #else 831 #define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ 832 #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC0_S */ 833 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) 834 #define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ 835 #else 836 #define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ 837 #endif /* SL_TRUSTZONE_PERIPHERAL_VDAC1_S */ 838 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) 839 #define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ 840 #else 841 #define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ 842 #endif /* SL_TRUSTZONE_PERIPHERAL_PCNT0_S */ 843 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) 844 #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ 845 #else 846 #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ 847 #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ 848 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) 849 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ 850 #else 851 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ 852 #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ 853 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) 854 #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ 855 #else 856 #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ 857 #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ 858 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) 859 #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ 860 #else 861 #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ 862 #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ 863 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) 864 #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ 865 #else 866 #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ 867 #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ 868 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) 869 #define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ 870 #else 871 #define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ 872 #endif /* SL_TRUSTZONE_PERIPHERAL_EUSART0_S */ 873 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) 874 #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ 875 #else 876 #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ 877 #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ 878 879 #define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ 880 /** @} End of group EFR32MG24A020F768IM40_Peripheral_Base */ 881 882 /**************************************************************************//** 883 * @defgroup EFR32MG24A020F768IM40_Peripheral_Declaration EFR32MG24A020F768IM40 Peripheral Declarations Map 884 * @{ 885 *****************************************************************************/ 886 887 #define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ 888 #define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ 889 #define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ 890 #define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ 891 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ 892 #define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ 893 #define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ 894 #define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ 895 #define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ 896 #define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ 897 #define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ 898 #define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ 899 #define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ 900 #define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ 901 #define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ 902 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ 903 #define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ 904 #define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ 905 #define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ 906 #define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ 907 #define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ 908 #define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ 909 #define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ 910 #define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ 911 #define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ 912 #define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ 913 #define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ 914 #define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ 915 #define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ 916 #define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ 917 #define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ 918 #define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ 919 #define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ 920 #define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ 921 #define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ 922 #define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ 923 #define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ 924 #define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ 925 #define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ 926 #define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ 927 #define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ 928 #define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ 929 #define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ 930 #define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ 931 #define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ 932 #define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ 933 #define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ 934 #define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ 935 #define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ 936 #define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ 937 #define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ 938 #define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ 939 #define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ 940 #define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ 941 #define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ 942 #define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ 943 #define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ 944 #define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ 945 #define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ 946 #define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ 947 #define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ 948 #define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ 949 #define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ 950 #define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ 951 #define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ 952 #define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ 953 #define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ 954 #define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ 955 #define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ 956 #define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ 957 #define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ 958 #define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ 959 #define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ 960 #define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ 961 #define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ 962 #define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ 963 #define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ 964 #define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ 965 #define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ 966 #define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ 967 #define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ 968 #define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ 969 #define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ 970 #define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ 971 #define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ 972 #define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ 973 #define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ 974 #define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ 975 #define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ 976 #define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ 977 #define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ 978 #define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ 979 #define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ 980 #define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ 981 #define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ 982 #define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ 983 #define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ 984 #define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ 985 #define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ 986 #define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ 987 #define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ 988 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ 989 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ 990 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ 991 #define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ 992 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ 993 #define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ 994 #define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ 995 #define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ 996 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ 997 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ 998 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ 999 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ 1000 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ 1001 #define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ 1002 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ 1003 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ 1004 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ 1005 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ 1006 #define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ 1007 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ 1008 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ 1009 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ 1010 #define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ 1011 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ 1012 #define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ 1013 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ 1014 #define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ 1015 #define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ 1016 #define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ 1017 #define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ 1018 #define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ 1019 #define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ 1020 #define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ 1021 #define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ 1022 #define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ 1023 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ 1024 #define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ 1025 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ 1026 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ 1027 #define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ 1028 #define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ 1029 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ 1030 #define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ 1031 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ 1032 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ 1033 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ 1034 #define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ 1035 #define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ 1036 #define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ 1037 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ 1038 /** @} End of group EFR32MG24A020F768IM40_Peripheral_Declaration */ 1039 1040 /**************************************************************************//** 1041 * @defgroup EFR32MG24A020F768IM40_Peripheral_Parameters EFR32MG24A020F768IM40 Peripheral Parameters 1042 * @{ 1043 * @brief Device peripheral parameter values 1044 *****************************************************************************/ 1045 1046 /* Common peripheral register block offsets. */ 1047 #define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ 1048 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ 1049 #define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ 1050 #define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ 1051 #define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ 1052 #define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ 1053 #define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ 1054 #define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ 1055 #define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ 1056 #define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ 1057 #define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ 1058 #define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ 1059 #define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ 1060 #define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ 1061 #define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ 1062 #define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ 1063 #define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ 1064 #define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ 1065 #define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ 1066 #define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ 1067 #define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ 1068 #define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ 1069 #define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ 1070 #define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ 1071 #define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ 1072 #define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ 1073 #define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ 1074 #define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ 1075 #define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ 1076 #define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ 1077 #define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ 1078 #define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ 1079 #define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ 1080 #define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ 1081 #define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ 1082 #define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ 1083 #define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ 1084 #define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ 1085 #define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ 1086 #define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ 1087 #define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ 1088 #define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ 1089 #define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ 1090 #define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ 1091 #define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ 1092 #define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ 1093 #define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ 1094 #define LFXO_CTUNE 0x1UL /**> CTUNE Present */ 1095 #define MSC_CDA_PRESENT 0x0UL /**> */ 1096 #define MSC_FDIO_WIDTH 0x40UL /**> None */ 1097 #define MSC_FLASHADDRBITS 0x15UL /**> None */ 1098 #define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ 1099 #define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ 1100 #define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ 1101 #define MSC_INFOADDRBITS 0xEUL /**> None */ 1102 #define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ 1103 #define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ 1104 #define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ 1105 #define MSC_REDUNDANCY 0x2UL /**> None */ 1106 #define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ 1107 #define MSC_UD_PRESENT 0x1UL /**> */ 1108 #define MSC_YADDRBITS 0x6UL /**> */ 1109 #define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ 1110 #define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ 1111 #define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ 1112 #define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ 1113 #define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ 1114 #define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ 1115 #define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ 1116 #define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ 1117 #define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ 1118 #define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ 1119 #define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ 1120 #define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ 1121 #define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ 1122 #define ICACHE0_SET_BITS 0x7UL /**> Set bits */ 1123 #define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ 1124 #define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ 1125 #define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ 1126 #define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ 1127 #define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ 1128 #define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ 1129 #define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ 1130 #define PRS_ASYNC_CH_NUM 0x10UL /**> None */ 1131 #define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ 1132 #define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ 1133 #define PRS_SYNC_CH_NUM 0x4UL /**> None */ 1134 #define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ 1135 #define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ 1136 #define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ 1137 #define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ 1138 #define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ 1139 #define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ 1140 #define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ 1141 #define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ 1142 #define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ 1143 #define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ 1144 #define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ 1145 #define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ 1146 #define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ 1147 #define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ 1148 #define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ 1149 #define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ 1150 #define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ 1151 #define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ 1152 #define GPIO_PORT_A_WL 0x8UL /**> New Param */ 1153 #define GPIO_PORT_A_WU 0x2UL /**> New Param */ 1154 #define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ 1155 #define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ 1156 #define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ 1157 #define GPIO_PORT_B_WL 0x6UL /**> New Param */ 1158 #define GPIO_PORT_B_WU 0x0UL /**> New Param */ 1159 #define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ 1160 #define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ 1161 #define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ 1162 #define GPIO_PORT_C_WL 0x8UL /**> New Param */ 1163 #define GPIO_PORT_C_WU 0x2UL /**> New Param */ 1164 #define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ 1165 #define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ 1166 #define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ 1167 #define GPIO_PORT_D_WL 0x6UL /**> New Param */ 1168 #define GPIO_PORT_D_WU 0x0UL /**> New Param */ 1169 #define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ 1170 #define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ 1171 #define LDMA_CH_BITS 0x5UL /**> New Param */ 1172 #define LDMA_CH_NUM 0x8UL /**> New Param */ 1173 #define LDMA_FIFO_BITS 0x5UL /**> New Param */ 1174 #define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ 1175 #define LDMAXBAR_CH_BITS 0x5UL /**> None */ 1176 #define LDMAXBAR_CH_NUM 0x8UL /**> None */ 1177 #define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ 1178 #define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ 1179 #define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1180 #define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ 1181 #define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ 1182 #define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1183 #define TIMER0_NO_DTI 0x0UL /**> */ 1184 #define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1185 #define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ 1186 #define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ 1187 #define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1188 #define TIMER1_NO_DTI 0x0UL /**> */ 1189 #define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1190 #define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ 1191 #define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ 1192 #define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1193 #define TIMER2_NO_DTI 0x0UL /**> */ 1194 #define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1195 #define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ 1196 #define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ 1197 #define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1198 #define TIMER3_NO_DTI 0x0UL /**> */ 1199 #define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1200 #define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ 1201 #define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ 1202 #define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1203 #define TIMER4_NO_DTI 0x0UL /**> */ 1204 #define USART0_AUTOTX_REG 0x1UL /**> None */ 1205 #define USART0_AUTOTX_REG_B 0x0UL /**> None */ 1206 #define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ 1207 #define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ 1208 #define USART0_CLK_PRS 0x1UL /**> None */ 1209 #define USART0_CLK_PRS_B 0x0UL /**> New Param */ 1210 #define USART0_FLOW_CONTROL 0x1UL /**> None */ 1211 #define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ 1212 #define USART0_I2S 0x1UL /**> None */ 1213 #define USART0_I2S_B 0x0UL /**> New Param */ 1214 #define USART0_IRDA_AVAILABLE 0x1UL /**> None */ 1215 #define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ 1216 #define USART0_MVDIS_FUNC 0x1UL /**> None */ 1217 #define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ 1218 #define USART0_RX_PRS 0x1UL /**> None */ 1219 #define USART0_RX_PRS_B 0x0UL /**> New Param */ 1220 #define USART0_SC_AVAILABLE 0x1UL /**> None */ 1221 #define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ 1222 #define USART0_SYNC_AVAILABLE 0x1UL /**> None */ 1223 #define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ 1224 #define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ 1225 #define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ 1226 #define USART0_TIMER 0x1UL /**> New Param */ 1227 #define USART0_TIMER_B 0x0UL /**> New Param */ 1228 #define BURTC_CNTWIDTH 0x20UL /**> None */ 1229 #define BURTC_PRECNT_WIDTH 0xFUL /**> */ 1230 #define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ 1231 #define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ 1232 #define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ 1233 #define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ 1234 #define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ 1235 #define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ 1236 #define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ 1237 #define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ 1238 #define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ 1239 #define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ 1240 #define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ 1241 #define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ 1242 #define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ 1243 #define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ 1244 #define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ 1245 #define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ 1246 #define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ 1247 #define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ 1248 #define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ 1249 #define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ 1250 #define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ 1251 #define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ 1252 #define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ 1253 #define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ 1254 #define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ 1255 #define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ 1256 #define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ 1257 #define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ 1258 #define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ 1259 #define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ 1260 #define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ 1261 #define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ 1262 #define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ 1263 #define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ 1264 #define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ 1265 #define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ 1266 #define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ 1267 #define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ 1268 #define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ 1269 #define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ 1270 #define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ 1271 #define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ 1272 #define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ 1273 #define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ 1274 #define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ 1275 #define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ 1276 #define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ 1277 #define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ 1278 #define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ 1279 #define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ 1280 #define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ 1281 #define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ 1282 #define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ 1283 #define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ 1284 #define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ 1285 #define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ 1286 #define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ 1287 #define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ 1288 #define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ 1289 #define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ 1290 #define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ 1291 #define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ 1292 #define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ 1293 #define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ 1294 #define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ 1295 #define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ 1296 #define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ 1297 #define IADC0_ENTRIES 0x10UL /**> ENTRIES */ 1298 #define ACMP0_DAC_INPUT 0x1UL /**> None */ 1299 #define ACMP0_EXT_OVR_IF 0x1UL /**> None */ 1300 #define ACMP1_DAC_INPUT 0x1UL /**> None */ 1301 #define ACMP1_EXT_OVR_IF 0x1UL /**> None */ 1302 #define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ 1303 #define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ 1304 #define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ 1305 #define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ 1306 #define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ 1307 #define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ 1308 #define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ 1309 #define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ 1310 #define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ 1311 #define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ 1312 #define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ 1313 #define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ 1314 #define PCNT0_PCNT_WIDTH 0x10UL /**> None */ 1315 #define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ 1316 #define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ 1317 #define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ 1318 #define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ 1319 #define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ 1320 #define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ 1321 #define WDOG0_PCNUM 0x2UL /**> None */ 1322 #define WDOG1_PCNUM 0x2UL /**> None */ 1323 #define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ 1324 #define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ 1325 #define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ 1326 #define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ 1327 #define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ 1328 #define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ 1329 #define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ 1330 #define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ 1331 #define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ 1332 #define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ 1333 #define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ 1334 #define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ 1335 #define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ 1336 #define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ 1337 #define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ 1338 #define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ 1339 #define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ 1340 #define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ 1341 #define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ 1342 #define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ 1343 #define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ 1344 #define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ 1345 #define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ 1346 #define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ 1347 #define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ 1348 #define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ 1349 #define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ 1350 #define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ 1351 #define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ 1352 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ 1353 #define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ 1354 #define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ 1355 #define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ 1356 #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ 1357 1358 /* Instance macros for ACMP */ 1359 #define ACMP(n) (((n) == 0) ? ACMP0 \ 1360 : ((n) == 1) ? ACMP1 \ 1361 : 0x0UL) 1362 #define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ 1363 : ((ref) == ACMP1) ? 1 \ 1364 : -1) 1365 #define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ 1366 : ((n) == 1) ? ACMP1_DAC_INPUT \ 1367 : 0x0UL) 1368 #define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ 1369 : ((n) == 1) ? ACMP1_EXT_OVR_IF \ 1370 : 0x0UL) 1371 1372 /* Instance macros for EUSART */ 1373 #define EUSART(n) (((n) == 0) ? EUSART0 \ 1374 : ((n) == 1) ? EUSART1 \ 1375 : 0x0UL) 1376 #define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ 1377 : ((ref) == EUSART1) ? 1 \ 1378 : -1) 1379 #define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ 1380 : ((n) == 1) ? EUSART1_EM2_CAPABLE \ 1381 : 0x0UL) 1382 #define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ 1383 : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ 1384 : 0x0UL) 1385 1386 /* Instance macros for HFRCO */ 1387 #define HFRCO(n) (((n) == 0) ? HFRCO0 \ 1388 : ((n) == 1) ? HFRCOEM23 \ 1389 : 0x0UL) 1390 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ 1391 : ((ref) == HFRCOEM23) ? 1 \ 1392 : -1) 1393 #define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ 1394 : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ 1395 : 0x0UL) 1396 #define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ 1397 : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ 1398 : 0x0UL) 1399 1400 /* Instance macros for I2C */ 1401 #define I2C(n) (((n) == 0) ? I2C0 \ 1402 : ((n) == 1) ? I2C1 \ 1403 : 0x0UL) 1404 #define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ 1405 : ((ref) == I2C1) ? 1 \ 1406 : -1) 1407 #define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ 1408 : ((n) == 1) ? I2C1_DELAY \ 1409 : 0x0UL) 1410 #define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ 1411 : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ 1412 : 0x0UL) 1413 1414 /* Instance macros for TIMER */ 1415 #define TIMER(n) (((n) == 0) ? TIMER0 \ 1416 : ((n) == 1) ? TIMER1 \ 1417 : ((n) == 2) ? TIMER2 \ 1418 : ((n) == 3) ? TIMER3 \ 1419 : ((n) == 4) ? TIMER4 \ 1420 : 0x0UL) 1421 #define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ 1422 : ((ref) == TIMER1) ? 1 \ 1423 : ((ref) == TIMER2) ? 2 \ 1424 : ((ref) == TIMER3) ? 3 \ 1425 : ((ref) == TIMER4) ? 4 \ 1426 : -1) 1427 #define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ 1428 : ((n) == 1) ? TIMER1_CC_NUM \ 1429 : ((n) == 2) ? TIMER2_CC_NUM \ 1430 : ((n) == 3) ? TIMER3_CC_NUM \ 1431 : ((n) == 4) ? TIMER4_CC_NUM \ 1432 : 0x0UL) 1433 #define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ 1434 : ((n) == 1) ? TIMER1_CNTWIDTH \ 1435 : ((n) == 2) ? TIMER2_CNTWIDTH \ 1436 : ((n) == 3) ? TIMER3_CNTWIDTH \ 1437 : ((n) == 4) ? TIMER4_CNTWIDTH \ 1438 : 0x0UL) 1439 #define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ 1440 : ((n) == 1) ? TIMER1_DTI \ 1441 : ((n) == 2) ? TIMER2_DTI \ 1442 : ((n) == 3) ? TIMER3_DTI \ 1443 : ((n) == 4) ? TIMER4_DTI \ 1444 : 0x0UL) 1445 #define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ 1446 : ((n) == 1) ? TIMER1_DTI_CC_NUM \ 1447 : ((n) == 2) ? TIMER2_DTI_CC_NUM \ 1448 : ((n) == 3) ? TIMER3_DTI_CC_NUM \ 1449 : ((n) == 4) ? TIMER4_DTI_CC_NUM \ 1450 : 0x0UL) 1451 #define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ 1452 : ((n) == 1) ? TIMER1_NO_DTI \ 1453 : ((n) == 2) ? TIMER2_NO_DTI \ 1454 : ((n) == 3) ? TIMER3_NO_DTI \ 1455 : ((n) == 4) ? TIMER4_NO_DTI \ 1456 : 0x0UL) 1457 1458 /* Instance macros for VDAC */ 1459 #define VDAC(n) (((n) == 0) ? VDAC0 \ 1460 : ((n) == 1) ? VDAC1 \ 1461 : 0x0UL) 1462 #define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ 1463 : ((ref) == VDAC1) ? 1 \ 1464 : -1) 1465 #define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ 1466 : ((n) == 1) ? VDAC1_ALT_WIDTH \ 1467 : 0x0UL) 1468 #define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ 1469 : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ 1470 : 0x0UL) 1471 #define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ 1472 : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ 1473 : 0x0UL) 1474 #define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ 1475 : ((n) == 1) ? VDAC1_FIFO_DEPTH \ 1476 : 0x0UL) 1477 #define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ 1478 : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ 1479 : 0x0UL) 1480 #define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ 1481 : ((n) == 1) ? VDAC1_RESOLUTION \ 1482 : 0x0UL) 1483 1484 /* Instance macros for WDOG */ 1485 #define WDOG(n) (((n) == 0) ? WDOG0 \ 1486 : ((n) == 1) ? WDOG1 \ 1487 : 0x0UL) 1488 #define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ 1489 : ((ref) == WDOG1) ? 1 \ 1490 : -1) 1491 #define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ 1492 : ((n) == 1) ? WDOG1_PCNUM \ 1493 : 0x0UL) 1494 1495 /** @} End of group EFR32MG24A020F768IM40_Peripheral_Parameters */ 1496 1497 /** @} End of group EFR32MG24A020F768IM40 */ 1498 /** @}} End of group Parts */ 1499 1500 #ifdef __cplusplus 1501 } 1502 #endif 1503 #endif 1504
