1 /***************************************************************************//** 2 * @file 3 * @brief EFR32FG1P_PRS_SIGNALS register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @addtogroup EFR32FG1P_PRS 43 * @{ 44 * @addtogroup EFR32FG1P_PRS_Signals PRS Signals 45 * @{ 46 * @brief PRS Signal names 47 ******************************************************************************/ 48 #define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ 49 #define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ 50 #define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ 51 #define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ 52 #define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ 53 #define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ 54 #define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ 55 #define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ 56 #define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ 57 #define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ 58 #define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ 59 #define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ 60 #define PRS_ACMP0_OUT ((6 << 8) + 0) /**< PRS Analog comparator output */ 61 #define PRS_ACMP1_OUT ((7 << 8) + 0) /**< PRS Analog comparator output */ 62 #define PRS_ADC0_SINGLE ((8 << 8) + 0) /**< PRS ADC single conversion done */ 63 #define PRS_ADC0_SCAN ((8 << 8) + 1) /**< PRS ADC scan conversion done */ 64 #define PRS_USART0_IRTX ((16 << 8) + 0) /**< PRS USART 0 IRDA out */ 65 #define PRS_USART0_TXC ((16 << 8) + 1) /**< PRS USART 0 TX complete */ 66 #define PRS_USART0_RXDATAV ((16 << 8) + 2) /**< PRS USART 0 RX Data Valid */ 67 #define PRS_USART0_RTS ((16 << 8) + 3) /**< PRS USART 0 RTS */ 68 #define PRS_USART0_TX ((16 << 8) + 5) /**< PRS USART 0 TX */ 69 #define PRS_USART0_CS ((16 << 8) + 6) /**< PRS USART 0 CS */ 70 #define PRS_USART1_TXC ((17 << 8) + 1) /**< PRS USART 1 TX complete */ 71 #define PRS_USART1_RXDATAV ((17 << 8) + 2) /**< PRS USART 1 RX Data Valid */ 72 #define PRS_USART1_RTS ((17 << 8) + 3) /**< PRS USART 0 RTS */ 73 #define PRS_USART1_TX ((17 << 8) + 5) /**< PRS USART 1 TX */ 74 #define PRS_USART1_CS ((17 << 8) + 6) /**< PRS USART 1 CS */ 75 #define PRS_TIMER0_UF ((28 << 8) + 0) /**< PRS Timer 0 Underflow */ 76 #define PRS_TIMER0_OF ((28 << 8) + 1) /**< PRS Timer 0 Overflow */ 77 #define PRS_TIMER0_CC0 ((28 << 8) + 2) /**< PRS Timer 0 Compare/Capture 0 */ 78 #define PRS_TIMER0_CC1 ((28 << 8) + 3) /**< PRS Timer 0 Compare/Capture 1 */ 79 #define PRS_TIMER0_CC2 ((28 << 8) + 4) /**< PRS Timer 0 Compare/Capture 2 */ 80 #define PRS_TIMER1_UF ((29 << 8) + 0) /**< PRS Timer 1 Underflow */ 81 #define PRS_TIMER1_OF ((29 << 8) + 1) /**< PRS Timer 1 Overflow */ 82 #define PRS_TIMER1_CC0 ((29 << 8) + 2) /**< PRS Timer 1 Compare/Capture 0 */ 83 #define PRS_TIMER1_CC1 ((29 << 8) + 3) /**< PRS Timer 1 Compare/Capture 1 */ 84 #define PRS_TIMER1_CC2 ((29 << 8) + 4) /**< PRS Timer 1 Compare/Capture 2 */ 85 #define PRS_TIMER1_CC3 ((29 << 8) + 5) /**< PRS Timer 1 Compare/Capture 3 */ 86 #define PRS_RAC_ACTIVE ((32 << 8) + 0) /**< PRS RAC is active */ 87 #define PRS_RAC_TX ((32 << 8) + 1) /**< PRS RAC is in TX */ 88 #define PRS_RAC_RX ((32 << 8) + 2) /**< PRS RAC is in RX */ 89 #define PRS_RAC_LNAEN ((32 << 8) + 3) /**< PRS LNA enable */ 90 #define PRS_RAC_PAEN ((32 << 8) + 4) /**< PRS PA enable */ 91 #define PRS_PROTIMER_LBTS ((35 << 8) + 5) /**< PRS Listen Before Talk Success */ 92 #define PRS_PROTIMER_LBTR ((35 << 8) + 6) /**< PRS Listen Before Talk Retry */ 93 #define PRS_PROTIMER_LBTF ((35 << 8) + 7) /**< PRS Listen Before Talk Failure */ 94 #define PRS_MODEM_FRAMEDET ((38 << 8) + 0) /**< PRS Frame detected */ 95 #define PRS_MODEM_PREDET ((38 << 8) + 1) /**< PRS Receive preamble detected */ 96 #define PRS_MODEM_TIMDET ((38 << 8) + 2) /**< PRS Receive timing detected */ 97 #define PRS_MODEM_FRAMESENT ((38 << 8) + 3) /**< PRS Entire frame transmitted */ 98 #define PRS_MODEM_SYNCSENT ((38 << 8) + 4) /**< PRS Syncword transmitted */ 99 #define PRS_MODEM_PRESENT ((38 << 8) + 5) /**< PRS Preamble transmitted */ 100 #define PRS_MODEM_ANT0 ((39 << 8) + 5) /**< PRS Antenna 0 select */ 101 #define PRS_MODEM_ANT1 ((39 << 8) + 6) /**< PRS Antenna 1 select */ 102 #define PRS_RTCC_CCV0 ((41 << 8) + 1) /**< PRS RTCC Compare 0 */ 103 #define PRS_RTCC_CCV1 ((41 << 8) + 2) /**< PRS RTCC Compare 1 */ 104 #define PRS_RTCC_CCV2 ((41 << 8) + 3) /**< PRS RTCC Compare 2 */ 105 #define PRS_GPIO_PIN0 ((48 << 8) + 0) /**< PRS GPIO pin 0 */ 106 #define PRS_GPIO_PIN1 ((48 << 8) + 1) /**< PRS GPIO pin 1 */ 107 #define PRS_GPIO_PIN2 ((48 << 8) + 2) /**< PRS GPIO pin 2 */ 108 #define PRS_GPIO_PIN3 ((48 << 8) + 3) /**< PRS GPIO pin 3 */ 109 #define PRS_GPIO_PIN4 ((48 << 8) + 4) /**< PRS GPIO pin 4 */ 110 #define PRS_GPIO_PIN5 ((48 << 8) + 5) /**< PRS GPIO pin 5 */ 111 #define PRS_GPIO_PIN6 ((48 << 8) + 6) /**< PRS GPIO pin 6 */ 112 #define PRS_GPIO_PIN7 ((48 << 8) + 7) /**< PRS GPIO pin 7 */ 113 #define PRS_GPIO_PIN8 ((49 << 8) + 0) /**< PRS GPIO pin 8 */ 114 #define PRS_GPIO_PIN9 ((49 << 8) + 1) /**< PRS GPIO pin 9 */ 115 #define PRS_GPIO_PIN10 ((49 << 8) + 2) /**< PRS GPIO pin 10 */ 116 #define PRS_GPIO_PIN11 ((49 << 8) + 3) /**< PRS GPIO pin 11 */ 117 #define PRS_GPIO_PIN12 ((49 << 8) + 4) /**< PRS GPIO pin 12 */ 118 #define PRS_GPIO_PIN13 ((49 << 8) + 5) /**< PRS GPIO pin 13 */ 119 #define PRS_GPIO_PIN14 ((49 << 8) + 6) /**< PRS GPIO pin 14 */ 120 #define PRS_GPIO_PIN15 ((49 << 8) + 7) /**< PRS GPIO pin 15 */ 121 #define PRS_LETIMER0_CH0 ((52 << 8) + 0) /**< PRS LETIMER CH0 Out */ 122 #define PRS_LETIMER0_CH1 ((52 << 8) + 1) /**< PRS LETIMER CH1 Out */ 123 #define PRS_PCNT0_TCC ((54 << 8) + 0) /**< PRS Triggered compare match */ 124 #define PRS_PCNT0_UFOF ((54 << 8) + 1) /**< PRS Counter overflow or underflow */ 125 #define PRS_PCNT0_DIR ((54 << 8) + 2) /**< PRS Counter direction */ 126 #define PRS_RFSENSE_WU ((59 << 8) + 0) /**< PRS RFSENSE Output */ 127 #define PRS_CRYOTIMER_PERIOD ((60 << 8) + 0) /**< PRS CRYOTIMER Output */ 128 #define PRS_CMU_CLKOUT0 ((61 << 8) + 0) /**< PRS Clock Output 0 */ 129 #define PRS_CMU_CLKOUT1 ((61 << 8) + 1) /**< PRS Clock Output 1 */ 130 #define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ 131 132 /** @} */ 133 /** @} End of group EFR32FG1P_PRS */ 134 /** @} End of group Parts */ 135
