1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG27 WDOG register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG27_WDOG_H 31 #define EFR32BG27_WDOG_H 32 #define WDOG_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG27_WDOG WDOG 40 * @{ 41 * @brief EFR32BG27 WDOG Register Declaration. 42 *****************************************************************************/ 43 44 /** WDOG Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP Version Register */ 47 __IOM uint32_t EN; /**< Enable Register */ 48 __IOM uint32_t CFG; /**< Configuration Register */ 49 __IOM uint32_t CMD; /**< Command Register */ 50 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 51 __IM uint32_t STATUS; /**< Status Register */ 52 __IOM uint32_t IF; /**< Interrupt Flag Register */ 53 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 54 __IOM uint32_t LOCK; /**< Lock Register */ 55 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 56 uint32_t RESERVED1[1014U]; /**< Reserved for future use */ 57 __IM uint32_t IPVERSION_SET; /**< IP Version Register */ 58 __IOM uint32_t EN_SET; /**< Enable Register */ 59 __IOM uint32_t CFG_SET; /**< Configuration Register */ 60 __IOM uint32_t CMD_SET; /**< Command Register */ 61 uint32_t RESERVED2[1U]; /**< Reserved for future use */ 62 __IM uint32_t STATUS_SET; /**< Status Register */ 63 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 64 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 65 __IOM uint32_t LOCK_SET; /**< Lock Register */ 66 __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ 67 uint32_t RESERVED3[1014U]; /**< Reserved for future use */ 68 __IM uint32_t IPVERSION_CLR; /**< IP Version Register */ 69 __IOM uint32_t EN_CLR; /**< Enable Register */ 70 __IOM uint32_t CFG_CLR; /**< Configuration Register */ 71 __IOM uint32_t CMD_CLR; /**< Command Register */ 72 uint32_t RESERVED4[1U]; /**< Reserved for future use */ 73 __IM uint32_t STATUS_CLR; /**< Status Register */ 74 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 75 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 76 __IOM uint32_t LOCK_CLR; /**< Lock Register */ 77 __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ 78 uint32_t RESERVED5[1014U]; /**< Reserved for future use */ 79 __IM uint32_t IPVERSION_TGL; /**< IP Version Register */ 80 __IOM uint32_t EN_TGL; /**< Enable Register */ 81 __IOM uint32_t CFG_TGL; /**< Configuration Register */ 82 __IOM uint32_t CMD_TGL; /**< Command Register */ 83 uint32_t RESERVED6[1U]; /**< Reserved for future use */ 84 __IM uint32_t STATUS_TGL; /**< Status Register */ 85 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 86 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 87 __IOM uint32_t LOCK_TGL; /**< Lock Register */ 88 __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ 89 } WDOG_TypeDef; 90 /** @} End of group EFR32BG27_WDOG */ 91 92 /**************************************************************************//** 93 * @addtogroup EFR32BG27_WDOG 94 * @{ 95 * @defgroup EFR32BG27_WDOG_BitFields WDOG Bit Fields 96 * @{ 97 *****************************************************************************/ 98 99 /* Bit fields for WDOG IPVERSION */ 100 #define _WDOG_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for WDOG_IPVERSION */ 101 #define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */ 102 #define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */ 103 #define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */ 104 #define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IPVERSION */ 105 #define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */ 106 107 /* Bit fields for WDOG EN */ 108 #define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */ 109 #define _WDOG_EN_MASK 0x00000001UL /**< Mask for WDOG_EN */ 110 #define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */ 111 #define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */ 112 #define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ 113 #define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ 114 #define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */ 115 116 /* Bit fields for WDOG CFG */ 117 #define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */ 118 #define _WDOG_CFG_MASK 0x730F071FUL /**< Mask for WDOG_CFG */ 119 #define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */ 120 #define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */ 121 #define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */ 122 #define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ 123 #define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */ 124 #define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */ 125 #define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */ 126 #define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */ 127 #define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */ 128 #define WDOG_CFG_EM2RUN (0x1UL << 1) /**< EM2 Run */ 129 #define _WDOG_CFG_EM2RUN_SHIFT 1 /**< Shift value for WDOG_EM2RUN */ 130 #define _WDOG_CFG_EM2RUN_MASK 0x2UL /**< Bit mask for WDOG_EM2RUN */ 131 #define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ 132 #define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ 133 #define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ 134 #define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */ 135 #define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */ 136 #define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */ 137 #define WDOG_CFG_EM3RUN (0x1UL << 2) /**< EM3 Run */ 138 #define _WDOG_CFG_EM3RUN_SHIFT 2 /**< Shift value for WDOG_EM3RUN */ 139 #define _WDOG_CFG_EM3RUN_MASK 0x4UL /**< Bit mask for WDOG_EM3RUN */ 140 #define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ 141 #define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ 142 #define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ 143 #define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */ 144 #define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */ 145 #define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */ 146 #define WDOG_CFG_EM4BLOCK (0x1UL << 3) /**< EM4 Block */ 147 #define _WDOG_CFG_EM4BLOCK_SHIFT 3 /**< Shift value for WDOG_EM4BLOCK */ 148 #define _WDOG_CFG_EM4BLOCK_MASK 0x8UL /**< Bit mask for WDOG_EM4BLOCK */ 149 #define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ 150 #define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ 151 #define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ 152 #define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */ 153 #define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */ 154 #define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */ 155 #define WDOG_CFG_DEBUGRUN (0x1UL << 4) /**< Debug Mode Run */ 156 #define _WDOG_CFG_DEBUGRUN_SHIFT 4 /**< Shift value for WDOG_DEBUGRUN */ 157 #define _WDOG_CFG_DEBUGRUN_MASK 0x10UL /**< Bit mask for WDOG_DEBUGRUN */ 158 #define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ 159 #define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ 160 #define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ 161 #define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */ 162 #define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */ 163 #define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */ 164 #define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */ 165 #define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */ 166 #define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */ 167 #define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ 168 #define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */ 169 #define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */ 170 #define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */ 171 #define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */ 172 #define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */ 173 #define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */ 174 #define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */ 175 #define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */ 176 #define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ 177 #define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */ 178 #define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */ 179 #define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */ 180 #define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */ 181 #define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ 182 #define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */ 183 #define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */ 184 #define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */ 185 #define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */ 186 #define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */ 187 #define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ 188 #define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ 189 #define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ 190 #define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ 191 #define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ 192 #define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ 193 #define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ 194 #define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */ 195 #define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */ 196 #define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */ 197 #define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */ 198 #define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */ 199 #define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */ 200 #define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */ 201 #define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */ 202 #define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */ 203 #define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */ 204 #define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */ 205 #define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */ 206 #define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */ 207 #define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */ 208 #define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */ 209 #define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */ 210 #define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */ 211 #define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */ 212 #define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */ 213 #define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */ 214 #define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */ 215 #define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */ 216 #define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */ 217 #define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */ 218 #define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */ 219 #define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */ 220 #define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */ 221 #define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ 222 #define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ 223 #define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ 224 #define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ 225 #define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ 226 #define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */ 227 #define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */ 228 #define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */ 229 #define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */ 230 #define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */ 231 #define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */ 232 #define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */ 233 #define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ 234 #define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ 235 #define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ 236 #define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ 237 #define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ 238 #define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ 239 #define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ 240 #define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ 241 #define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ 242 #define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */ 243 #define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */ 244 #define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */ 245 #define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */ 246 #define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */ 247 #define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */ 248 #define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */ 249 #define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */ 250 #define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */ 251 252 /* Bit fields for WDOG CMD */ 253 #define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ 254 #define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ 255 #define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */ 256 #define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ 257 #define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ 258 #define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ 259 #define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ 260 #define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ 261 #define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ 262 #define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ 263 #define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ 264 265 /* Bit fields for WDOG STATUS */ 266 #define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */ 267 #define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */ 268 #define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */ 269 #define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */ 270 #define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */ 271 #define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */ 272 #define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */ 273 #define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */ 274 #define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */ 275 #define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */ 276 #define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */ 277 278 /* Bit fields for WDOG IF */ 279 #define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ 280 #define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ 281 #define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ 282 #define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ 283 #define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ 284 #define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ 285 #define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ 286 #define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ 287 #define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ 288 #define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ 289 #define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ 290 #define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ 291 #define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ 292 #define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ 293 #define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ 294 #define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ 295 #define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ 296 #define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */ 297 #define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ 298 #define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ 299 #define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ 300 #define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ 301 #define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */ 302 #define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ 303 #define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ 304 #define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ 305 #define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ 306 307 /* Bit fields for WDOG IEN */ 308 #define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ 309 #define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ 310 #define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */ 311 #define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ 312 #define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ 313 #define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ 314 #define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ 315 #define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */ 316 #define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ 317 #define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ 318 #define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ 319 #define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ 320 #define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */ 321 #define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ 322 #define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ 323 #define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ 324 #define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ 325 #define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */ 326 #define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ 327 #define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ 328 #define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ 329 #define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ 330 #define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */ 331 #define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ 332 #define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ 333 #define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ 334 #define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ 335 336 /* Bit fields for WDOG LOCK */ 337 #define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */ 338 #define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */ 339 #define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */ 340 #define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */ 341 #define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */ 342 #define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */ 343 #define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */ 344 #define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */ 345 #define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */ 346 #define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */ 347 348 /* Bit fields for WDOG SYNCBUSY */ 349 #define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ 350 #define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */ 351 #define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */ 352 #define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */ 353 #define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */ 354 #define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ 355 #define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ 356 357 /** @} End of group EFR32BG27_WDOG_BitFields */ 358 /** @} End of group EFR32BG27_WDOG */ 359 /** @} End of group Parts */ 360 361 #endif /* EFR32BG27_WDOG_H */ 362
