1 /***************************************************************************//** 2 * @file 3 * @brief EFM32WG_I2C register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32WG_I2C 43 * @{ 44 * @brief EFM32WG_I2C Register Declaration 45 ******************************************************************************/ 46 typedef struct { 47 __IOM uint32_t CTRL; /**< Control Register */ 48 __IOM uint32_t CMD; /**< Command Register */ 49 __IM uint32_t STATE; /**< State Register */ 50 __IM uint32_t STATUS; /**< Status Register */ 51 __IOM uint32_t CLKDIV; /**< Clock Division Register */ 52 __IOM uint32_t SADDR; /**< Slave Address Register */ 53 __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */ 54 __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ 55 __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ 56 __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ 57 __IM uint32_t IF; /**< Interrupt Flag Register */ 58 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 59 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 60 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 61 __IOM uint32_t ROUTE; /**< I/O Routing Register */ 62 } I2C_TypeDef; /**< I2C Register Declaration *//** @} */ 63 64 /***************************************************************************//** 65 * @defgroup EFM32WG_I2C_BitFields 66 * @{ 67 ******************************************************************************/ 68 69 /* Bit fields for I2C CTRL */ 70 #define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ 71 #define _I2C_CTRL_MASK 0x0007B37FUL /**< Mask for I2C_CTRL */ 72 #define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */ 73 #define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */ 74 #define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ 75 #define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 76 #define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ 77 #define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */ 78 #define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ 79 #define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ 80 #define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 81 #define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ 82 #define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ 83 #define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ 84 #define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ 85 #define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 86 #define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ 87 #define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ 88 #define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ 89 #define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ 90 #define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 91 #define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ 92 #define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ 93 #define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ 94 #define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ 95 #define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 96 #define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ 97 #define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ 98 #define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ 99 #define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ 100 #define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 101 #define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ 102 #define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ 103 #define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ 104 #define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ 105 #define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 106 #define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ 107 #define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ 108 #define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ 109 #define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 110 #define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ 111 #define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ 112 #define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ 113 #define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ 114 #define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ 115 #define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ 116 #define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ 117 #define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ 118 #define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ 119 #define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 120 #define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ 121 #define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ 122 #define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ 123 #define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ 124 #define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ 125 #define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ 126 #define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */ 127 #define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */ 128 #define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */ 129 #define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ 130 #define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ 131 #define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ 132 #define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 133 #define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ 134 #define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ 135 #define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ 136 #define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 137 #define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ 138 #define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ 139 #define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ 140 #define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ 141 #define _I2C_CTRL_CLTO_320PPC 0x00000004UL /**< Mode 320PPC for I2C_CTRL */ 142 #define _I2C_CTRL_CLTO_1024PPC 0x00000005UL /**< Mode 1024PPC for I2C_CTRL */ 143 #define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ 144 #define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ 145 #define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */ 146 #define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */ 147 #define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */ 148 #define I2C_CTRL_CLTO_320PPC (_I2C_CTRL_CLTO_320PPC << 16) /**< Shifted mode 320PPC for I2C_CTRL */ 149 #define I2C_CTRL_CLTO_1024PPC (_I2C_CTRL_CLTO_1024PPC << 16) /**< Shifted mode 1024PPC for I2C_CTRL */ 150 151 /* Bit fields for I2C CMD */ 152 #define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ 153 #define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ 154 #define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ 155 #define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ 156 #define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ 157 #define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 158 #define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ 159 #define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ 160 #define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ 161 #define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ 162 #define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 163 #define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ 164 #define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ 165 #define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ 166 #define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ 167 #define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 168 #define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ 169 #define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ 170 #define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ 171 #define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ 172 #define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 173 #define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ 174 #define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ 175 #define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ 176 #define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ 177 #define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 178 #define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ 179 #define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ 180 #define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ 181 #define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ 182 #define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 183 #define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ 184 #define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ 185 #define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ 186 #define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ 187 #define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 188 #define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ 189 #define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ 190 #define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ 191 #define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ 192 #define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 193 #define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ 194 195 /* Bit fields for I2C STATE */ 196 #define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ 197 #define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ 198 #define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ 199 #define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ 200 #define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ 201 #define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ 202 #define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ 203 #define I2C_STATE_MASTER (0x1UL << 1) /**< Master */ 204 #define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ 205 #define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ 206 #define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ 207 #define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ 208 #define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ 209 #define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ 210 #define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ 211 #define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ 212 #define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ 213 #define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ 214 #define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ 215 #define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ 216 #define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ 217 #define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ 218 #define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ 219 #define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ 220 #define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ 221 #define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ 222 #define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ 223 #define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ 224 #define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ 225 #define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ 226 #define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ 227 #define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ 228 #define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ 229 #define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ 230 #define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ 231 #define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ 232 #define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ 233 #define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ 234 #define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ 235 #define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ 236 #define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ 237 #define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ 238 #define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ 239 #define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ 240 #define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ 241 242 /* Bit fields for I2C STATUS */ 243 #define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ 244 #define _I2C_STATUS_MASK 0x000001FFUL /**< Mask for I2C_STATUS */ 245 #define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ 246 #define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ 247 #define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ 248 #define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 249 #define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ 250 #define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ 251 #define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ 252 #define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ 253 #define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 254 #define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ 255 #define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ 256 #define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ 257 #define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ 258 #define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 259 #define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ 260 #define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ 261 #define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ 262 #define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ 263 #define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 264 #define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ 265 #define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ 266 #define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ 267 #define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ 268 #define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 269 #define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ 270 #define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ 271 #define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ 272 #define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ 273 #define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 274 #define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ 275 #define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ 276 #define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ 277 #define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ 278 #define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 279 #define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ 280 #define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ 281 #define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ 282 #define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ 283 #define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ 284 #define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ 285 #define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ 286 #define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ 287 #define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ 288 #define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 289 #define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ 290 291 /* Bit fields for I2C CLKDIV */ 292 #define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ 293 #define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ 294 #define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ 295 #define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ 296 #define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ 297 #define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ 298 299 /* Bit fields for I2C SADDR */ 300 #define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ 301 #define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ 302 #define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ 303 #define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ 304 #define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ 305 #define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ 306 307 /* Bit fields for I2C SADDRMASK */ 308 #define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ 309 #define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ 310 #define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */ 311 #define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */ 312 #define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ 313 #define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ 314 315 /* Bit fields for I2C RXDATA */ 316 #define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ 317 #define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ 318 #define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ 319 #define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ 320 #define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ 321 #define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ 322 323 /* Bit fields for I2C RXDATAP */ 324 #define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ 325 #define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ 326 #define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ 327 #define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ 328 #define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ 329 #define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ 330 331 /* Bit fields for I2C TXDATA */ 332 #define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ 333 #define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ 334 #define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ 335 #define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ 336 #define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ 337 #define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ 338 339 /* Bit fields for I2C IF */ 340 #define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */ 341 #define _I2C_IF_MASK 0x0001FFFFUL /**< Mask for I2C_IF */ 342 #define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ 343 #define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ 344 #define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ 345 #define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 346 #define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ 347 #define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ 348 #define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ 349 #define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ 350 #define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 351 #define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ 352 #define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ 353 #define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ 354 #define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ 355 #define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 356 #define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ 357 #define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ 358 #define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ 359 #define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ 360 #define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 361 #define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ 362 #define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ 363 #define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ 364 #define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ 365 #define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 366 #define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ 367 #define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ 368 #define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ 369 #define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ 370 #define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 371 #define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ 372 #define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ 373 #define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ 374 #define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ 375 #define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 376 #define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ 377 #define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ 378 #define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ 379 #define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ 380 #define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 381 #define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ 382 #define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */ 383 #define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ 384 #define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ 385 #define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 386 #define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ 387 #define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ 388 #define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ 389 #define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ 390 #define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 391 #define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ 392 #define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ 393 #define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ 394 #define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ 395 #define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 396 #define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ 397 #define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ 398 #define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ 399 #define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ 400 #define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 401 #define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ 402 #define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ 403 #define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ 404 #define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ 405 #define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 406 #define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ 407 #define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ 408 #define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ 409 #define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ 410 #define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 411 #define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ 412 #define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ 413 #define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ 414 #define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ 415 #define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 416 #define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ 417 #define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ 418 #define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ 419 #define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ 420 #define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 421 #define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ 422 #define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */ 423 #define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ 424 #define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ 425 #define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 426 #define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ 427 428 /* Bit fields for I2C IFS */ 429 #define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */ 430 #define _I2C_IFS_MASK 0x0001FFCFUL /**< Mask for I2C_IFS */ 431 #define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */ 432 #define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */ 433 #define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */ 434 #define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ 435 #define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */ 436 #define I2C_IFS_RSTART (0x1UL << 1) /**< Set Repeated START Interrupt Flag */ 437 #define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ 438 #define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ 439 #define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ 440 #define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */ 441 #define I2C_IFS_ADDR (0x1UL << 2) /**< Set Address Interrupt Flag */ 442 #define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ 443 #define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ 444 #define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ 445 #define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */ 446 #define I2C_IFS_TXC (0x1UL << 3) /**< Set Transfer Completed Interrupt Flag */ 447 #define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ 448 #define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ 449 #define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ 450 #define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */ 451 #define I2C_IFS_ACK (0x1UL << 6) /**< Set Acknowledge Received Interrupt Flag */ 452 #define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ 453 #define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ 454 #define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ 455 #define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */ 456 #define I2C_IFS_NACK (0x1UL << 7) /**< Set Not Acknowledge Received Interrupt Flag */ 457 #define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ 458 #define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ 459 #define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ 460 #define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */ 461 #define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */ 462 #define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ 463 #define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ 464 #define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ 465 #define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */ 466 #define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set Arbitration Lost Interrupt Flag */ 467 #define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ 468 #define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ 469 #define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ 470 #define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */ 471 #define I2C_IFS_BUSERR (0x1UL << 10) /**< Set Bus Error Interrupt Flag */ 472 #define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ 473 #define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ 474 #define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ 475 #define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */ 476 #define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set Bus Held Interrupt Flag */ 477 #define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ 478 #define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ 479 #define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ 480 #define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */ 481 #define I2C_IFS_TXOF (0x1UL << 12) /**< Set Transmit Buffer Overflow Interrupt Flag */ 482 #define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ 483 #define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ 484 #define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ 485 #define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */ 486 #define I2C_IFS_RXUF (0x1UL << 13) /**< Set Receive Buffer Underflow Interrupt Flag */ 487 #define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ 488 #define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ 489 #define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ 490 #define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */ 491 #define I2C_IFS_BITO (0x1UL << 14) /**< Set Bus Idle Timeout Interrupt Flag */ 492 #define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ 493 #define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ 494 #define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ 495 #define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */ 496 #define I2C_IFS_CLTO (0x1UL << 15) /**< Set Clock Low Interrupt Flag */ 497 #define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ 498 #define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ 499 #define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ 500 #define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */ 501 #define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */ 502 #define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ 503 #define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ 504 #define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ 505 #define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */ 506 507 /* Bit fields for I2C IFC */ 508 #define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */ 509 #define _I2C_IFC_MASK 0x0001FFCFUL /**< Mask for I2C_IFC */ 510 #define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */ 511 #define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */ 512 #define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */ 513 #define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ 514 #define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */ 515 #define I2C_IFC_RSTART (0x1UL << 1) /**< Clear Repeated START Interrupt Flag */ 516 #define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ 517 #define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ 518 #define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ 519 #define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */ 520 #define I2C_IFC_ADDR (0x1UL << 2) /**< Clear Address Interrupt Flag */ 521 #define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ 522 #define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ 523 #define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ 524 #define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */ 525 #define I2C_IFC_TXC (0x1UL << 3) /**< Clear Transfer Completed Interrupt Flag */ 526 #define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ 527 #define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ 528 #define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ 529 #define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */ 530 #define I2C_IFC_ACK (0x1UL << 6) /**< Clear Acknowledge Received Interrupt Flag */ 531 #define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ 532 #define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ 533 #define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ 534 #define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */ 535 #define I2C_IFC_NACK (0x1UL << 7) /**< Clear Not Acknowledge Received Interrupt Flag */ 536 #define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ 537 #define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ 538 #define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ 539 #define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */ 540 #define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */ 541 #define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ 542 #define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ 543 #define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ 544 #define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */ 545 #define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear Arbitration Lost Interrupt Flag */ 546 #define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ 547 #define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ 548 #define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ 549 #define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */ 550 #define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear Bus Error Interrupt Flag */ 551 #define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ 552 #define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ 553 #define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ 554 #define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */ 555 #define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear Bus Held Interrupt Flag */ 556 #define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ 557 #define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ 558 #define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ 559 #define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */ 560 #define I2C_IFC_TXOF (0x1UL << 12) /**< Clear Transmit Buffer Overflow Interrupt Flag */ 561 #define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ 562 #define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ 563 #define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ 564 #define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */ 565 #define I2C_IFC_RXUF (0x1UL << 13) /**< Clear Receive Buffer Underflow Interrupt Flag */ 566 #define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ 567 #define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ 568 #define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ 569 #define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */ 570 #define I2C_IFC_BITO (0x1UL << 14) /**< Clear Bus Idle Timeout Interrupt Flag */ 571 #define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ 572 #define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ 573 #define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ 574 #define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */ 575 #define I2C_IFC_CLTO (0x1UL << 15) /**< Clear Clock Low Interrupt Flag */ 576 #define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ 577 #define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ 578 #define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ 579 #define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */ 580 #define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */ 581 #define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ 582 #define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ 583 #define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ 584 #define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */ 585 586 /* Bit fields for I2C IEN */ 587 #define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ 588 #define _I2C_IEN_MASK 0x0001FFFFUL /**< Mask for I2C_IEN */ 589 #define I2C_IEN_START (0x1UL << 0) /**< START Condition Interrupt Enable */ 590 #define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ 591 #define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ 592 #define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 593 #define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ 594 #define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Enable */ 595 #define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ 596 #define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ 597 #define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 598 #define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ 599 #define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Enable */ 600 #define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ 601 #define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ 602 #define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 603 #define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ 604 #define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Enable */ 605 #define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ 606 #define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ 607 #define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 608 #define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ 609 #define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer level Interrupt Enable */ 610 #define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ 611 #define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ 612 #define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 613 #define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ 614 #define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Enable */ 615 #define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ 616 #define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ 617 #define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 618 #define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ 619 #define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Enable */ 620 #define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ 621 #define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ 622 #define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 623 #define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ 624 #define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Enable */ 625 #define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ 626 #define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ 627 #define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 628 #define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ 629 #define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */ 630 #define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ 631 #define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ 632 #define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 633 #define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ 634 #define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Enable */ 635 #define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ 636 #define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ 637 #define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 638 #define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ 639 #define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Enable */ 640 #define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ 641 #define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ 642 #define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 643 #define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ 644 #define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Enable */ 645 #define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ 646 #define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ 647 #define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 648 #define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ 649 #define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Enable */ 650 #define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ 651 #define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ 652 #define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 653 #define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ 654 #define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Enable */ 655 #define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ 656 #define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ 657 #define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 658 #define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ 659 #define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Enable */ 660 #define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ 661 #define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ 662 #define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 663 #define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ 664 #define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Interrupt Enable */ 665 #define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ 666 #define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ 667 #define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 668 #define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ 669 #define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */ 670 #define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ 671 #define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ 672 #define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 673 #define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ 674 675 /* Bit fields for I2C ROUTE */ 676 #define _I2C_ROUTE_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTE */ 677 #define _I2C_ROUTE_MASK 0x00000703UL /**< Mask for I2C_ROUTE */ 678 #define I2C_ROUTE_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */ 679 #define _I2C_ROUTE_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */ 680 #define _I2C_ROUTE_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */ 681 #define _I2C_ROUTE_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */ 682 #define I2C_ROUTE_SDAPEN_DEFAULT (_I2C_ROUTE_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTE */ 683 #define I2C_ROUTE_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */ 684 #define _I2C_ROUTE_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */ 685 #define _I2C_ROUTE_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */ 686 #define _I2C_ROUTE_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */ 687 #define I2C_ROUTE_SCLPEN_DEFAULT (_I2C_ROUTE_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTE */ 688 #define _I2C_ROUTE_LOCATION_SHIFT 8 /**< Shift value for I2C_LOCATION */ 689 #define _I2C_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for I2C_LOCATION */ 690 #define _I2C_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTE */ 691 #define _I2C_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */ 692 #define _I2C_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTE */ 693 #define _I2C_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTE */ 694 #define _I2C_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTE */ 695 #define _I2C_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTE */ 696 #define _I2C_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTE */ 697 #define _I2C_ROUTE_LOCATION_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTE */ 698 #define I2C_ROUTE_LOCATION_LOC0 (_I2C_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTE */ 699 #define I2C_ROUTE_LOCATION_DEFAULT (_I2C_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTE */ 700 #define I2C_ROUTE_LOCATION_LOC1 (_I2C_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTE */ 701 #define I2C_ROUTE_LOCATION_LOC2 (_I2C_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTE */ 702 #define I2C_ROUTE_LOCATION_LOC3 (_I2C_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTE */ 703 #define I2C_ROUTE_LOCATION_LOC4 (_I2C_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTE */ 704 #define I2C_ROUTE_LOCATION_LOC5 (_I2C_ROUTE_LOCATION_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTE */ 705 #define I2C_ROUTE_LOCATION_LOC6 (_I2C_ROUTE_LOCATION_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTE */ 706 707 /** @} End of group EFM32WG_I2C */ 708 /** @} End of group Parts */ 709
