1 /***************************************************************************//** 2 * @file 3 * @brief EFM32HG_VCMP register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32HG_VCMP 43 * @{ 44 * @brief EFM32HG_VCMP Register Declaration 45 ******************************************************************************/ 46 typedef struct { 47 __IOM uint32_t CTRL; /**< Control Register */ 48 __IOM uint32_t INPUTSEL; /**< Input Selection Register */ 49 __IM uint32_t STATUS; /**< Status Register */ 50 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 51 __IM uint32_t IF; /**< Interrupt Flag Register */ 52 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 53 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 54 } VCMP_TypeDef; /**< VCMP Register Declaration *//** @} */ 55 56 /***************************************************************************//** 57 * @defgroup EFM32HG_VCMP_BitFields 58 * @{ 59 ******************************************************************************/ 60 61 /* Bit fields for VCMP CTRL */ 62 #define _VCMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for VCMP_CTRL */ 63 #define _VCMP_CTRL_MASK 0x4F030715UL /**< Mask for VCMP_CTRL */ 64 #define VCMP_CTRL_EN (0x1UL << 0) /**< Voltage Supply Comparator Enable */ 65 #define _VCMP_CTRL_EN_SHIFT 0 /**< Shift value for VCMP_EN */ 66 #define _VCMP_CTRL_EN_MASK 0x1UL /**< Bit mask for VCMP_EN */ 67 #define _VCMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ 68 #define VCMP_CTRL_EN_DEFAULT (_VCMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_CTRL */ 69 #define VCMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */ 70 #define _VCMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for VCMP_INACTVAL */ 71 #define _VCMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for VCMP_INACTVAL */ 72 #define _VCMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ 73 #define VCMP_CTRL_INACTVAL_DEFAULT (_VCMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for VCMP_CTRL */ 74 #define VCMP_CTRL_HYSTEN (0x1UL << 4) /**< Hysteresis Enable */ 75 #define _VCMP_CTRL_HYSTEN_SHIFT 4 /**< Shift value for VCMP_HYSTEN */ 76 #define _VCMP_CTRL_HYSTEN_MASK 0x10UL /**< Bit mask for VCMP_HYSTEN */ 77 #define _VCMP_CTRL_HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ 78 #define VCMP_CTRL_HYSTEN_DEFAULT (_VCMP_CTRL_HYSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for VCMP_CTRL */ 79 #define _VCMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for VCMP_WARMTIME */ 80 #define _VCMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for VCMP_WARMTIME */ 81 #define _VCMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ 82 #define _VCMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for VCMP_CTRL */ 83 #define _VCMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for VCMP_CTRL */ 84 #define _VCMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for VCMP_CTRL */ 85 #define _VCMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for VCMP_CTRL */ 86 #define _VCMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for VCMP_CTRL */ 87 #define _VCMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for VCMP_CTRL */ 88 #define _VCMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for VCMP_CTRL */ 89 #define _VCMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for VCMP_CTRL */ 90 #define VCMP_CTRL_WARMTIME_DEFAULT (_VCMP_CTRL_WARMTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for VCMP_CTRL */ 91 #define VCMP_CTRL_WARMTIME_4CYCLES (_VCMP_CTRL_WARMTIME_4CYCLES << 8) /**< Shifted mode 4CYCLES for VCMP_CTRL */ 92 #define VCMP_CTRL_WARMTIME_8CYCLES (_VCMP_CTRL_WARMTIME_8CYCLES << 8) /**< Shifted mode 8CYCLES for VCMP_CTRL */ 93 #define VCMP_CTRL_WARMTIME_16CYCLES (_VCMP_CTRL_WARMTIME_16CYCLES << 8) /**< Shifted mode 16CYCLES for VCMP_CTRL */ 94 #define VCMP_CTRL_WARMTIME_32CYCLES (_VCMP_CTRL_WARMTIME_32CYCLES << 8) /**< Shifted mode 32CYCLES for VCMP_CTRL */ 95 #define VCMP_CTRL_WARMTIME_64CYCLES (_VCMP_CTRL_WARMTIME_64CYCLES << 8) /**< Shifted mode 64CYCLES for VCMP_CTRL */ 96 #define VCMP_CTRL_WARMTIME_128CYCLES (_VCMP_CTRL_WARMTIME_128CYCLES << 8) /**< Shifted mode 128CYCLES for VCMP_CTRL */ 97 #define VCMP_CTRL_WARMTIME_256CYCLES (_VCMP_CTRL_WARMTIME_256CYCLES << 8) /**< Shifted mode 256CYCLES for VCMP_CTRL */ 98 #define VCMP_CTRL_WARMTIME_512CYCLES (_VCMP_CTRL_WARMTIME_512CYCLES << 8) /**< Shifted mode 512CYCLES for VCMP_CTRL */ 99 #define VCMP_CTRL_IRISE (0x1UL << 16) /**< Rising Edge Interrupt Sense */ 100 #define _VCMP_CTRL_IRISE_SHIFT 16 /**< Shift value for VCMP_IRISE */ 101 #define _VCMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for VCMP_IRISE */ 102 #define _VCMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ 103 #define VCMP_CTRL_IRISE_DEFAULT (_VCMP_CTRL_IRISE_DEFAULT << 16) /**< Shifted mode DEFAULT for VCMP_CTRL */ 104 #define VCMP_CTRL_IFALL (0x1UL << 17) /**< Falling Edge Interrupt Sense */ 105 #define _VCMP_CTRL_IFALL_SHIFT 17 /**< Shift value for VCMP_IFALL */ 106 #define _VCMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for VCMP_IFALL */ 107 #define _VCMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */ 108 #define VCMP_CTRL_IFALL_DEFAULT (_VCMP_CTRL_IFALL_DEFAULT << 17) /**< Shifted mode DEFAULT for VCMP_CTRL */ 109 #define _VCMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for VCMP_BIASPROG */ 110 #define _VCMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for VCMP_BIASPROG */ 111 #define _VCMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for VCMP_CTRL */ 112 #define VCMP_CTRL_BIASPROG_DEFAULT (_VCMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for VCMP_CTRL */ 113 #define VCMP_CTRL_HALFBIAS (0x1UL << 30) /**< Half Bias Current */ 114 #define _VCMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for VCMP_HALFBIAS */ 115 #define _VCMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for VCMP_HALFBIAS */ 116 #define _VCMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VCMP_CTRL */ 117 #define VCMP_CTRL_HALFBIAS_DEFAULT (_VCMP_CTRL_HALFBIAS_DEFAULT << 30) /**< Shifted mode DEFAULT for VCMP_CTRL */ 118 119 /* Bit fields for VCMP INPUTSEL */ 120 #define _VCMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for VCMP_INPUTSEL */ 121 #define _VCMP_INPUTSEL_MASK 0x0000013FUL /**< Mask for VCMP_INPUTSEL */ 122 #define _VCMP_INPUTSEL_TRIGLEVEL_SHIFT 0 /**< Shift value for VCMP_TRIGLEVEL */ 123 #define _VCMP_INPUTSEL_TRIGLEVEL_MASK 0x3FUL /**< Bit mask for VCMP_TRIGLEVEL */ 124 #define _VCMP_INPUTSEL_TRIGLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */ 125 #define VCMP_INPUTSEL_TRIGLEVEL_DEFAULT (_VCMP_INPUTSEL_TRIGLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */ 126 #define VCMP_INPUTSEL_LPREF (0x1UL << 8) /**< Low Power Reference */ 127 #define _VCMP_INPUTSEL_LPREF_SHIFT 8 /**< Shift value for VCMP_LPREF */ 128 #define _VCMP_INPUTSEL_LPREF_MASK 0x100UL /**< Bit mask for VCMP_LPREF */ 129 #define _VCMP_INPUTSEL_LPREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */ 130 #define VCMP_INPUTSEL_LPREF_DEFAULT (_VCMP_INPUTSEL_LPREF_DEFAULT << 8) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */ 131 132 /* Bit fields for VCMP STATUS */ 133 #define _VCMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for VCMP_STATUS */ 134 #define _VCMP_STATUS_MASK 0x00000003UL /**< Mask for VCMP_STATUS */ 135 #define VCMP_STATUS_VCMPACT (0x1UL << 0) /**< Voltage Supply Comparator Active */ 136 #define _VCMP_STATUS_VCMPACT_SHIFT 0 /**< Shift value for VCMP_VCMPACT */ 137 #define _VCMP_STATUS_VCMPACT_MASK 0x1UL /**< Bit mask for VCMP_VCMPACT */ 138 #define _VCMP_STATUS_VCMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */ 139 #define VCMP_STATUS_VCMPACT_DEFAULT (_VCMP_STATUS_VCMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_STATUS */ 140 #define VCMP_STATUS_VCMPOUT (0x1UL << 1) /**< Voltage Supply Comparator Output */ 141 #define _VCMP_STATUS_VCMPOUT_SHIFT 1 /**< Shift value for VCMP_VCMPOUT */ 142 #define _VCMP_STATUS_VCMPOUT_MASK 0x2UL /**< Bit mask for VCMP_VCMPOUT */ 143 #define _VCMP_STATUS_VCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */ 144 #define VCMP_STATUS_VCMPOUT_DEFAULT (_VCMP_STATUS_VCMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_STATUS */ 145 146 /* Bit fields for VCMP IEN */ 147 #define _VCMP_IEN_RESETVALUE 0x00000000UL /**< Default value for VCMP_IEN */ 148 #define _VCMP_IEN_MASK 0x00000003UL /**< Mask for VCMP_IEN */ 149 #define VCMP_IEN_EDGE (0x1UL << 0) /**< Edge Trigger Interrupt Enable */ 150 #define _VCMP_IEN_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */ 151 #define _VCMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */ 152 #define _VCMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */ 153 #define VCMP_IEN_EDGE_DEFAULT (_VCMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IEN */ 154 #define VCMP_IEN_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Enable */ 155 #define _VCMP_IEN_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */ 156 #define _VCMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */ 157 #define _VCMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */ 158 #define VCMP_IEN_WARMUP_DEFAULT (_VCMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IEN */ 159 160 /* Bit fields for VCMP IF */ 161 #define _VCMP_IF_RESETVALUE 0x00000000UL /**< Default value for VCMP_IF */ 162 #define _VCMP_IF_MASK 0x00000003UL /**< Mask for VCMP_IF */ 163 #define VCMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ 164 #define _VCMP_IF_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */ 165 #define _VCMP_IF_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */ 166 #define _VCMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */ 167 #define VCMP_IF_EDGE_DEFAULT (_VCMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IF */ 168 #define VCMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */ 169 #define _VCMP_IF_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */ 170 #define _VCMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */ 171 #define _VCMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */ 172 #define VCMP_IF_WARMUP_DEFAULT (_VCMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IF */ 173 174 /* Bit fields for VCMP IFS */ 175 #define _VCMP_IFS_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFS */ 176 #define _VCMP_IFS_MASK 0x00000003UL /**< Mask for VCMP_IFS */ 177 #define VCMP_IFS_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Set */ 178 #define _VCMP_IFS_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */ 179 #define _VCMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */ 180 #define _VCMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */ 181 #define VCMP_IFS_EDGE_DEFAULT (_VCMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IFS */ 182 #define VCMP_IFS_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Set */ 183 #define _VCMP_IFS_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */ 184 #define _VCMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */ 185 #define _VCMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */ 186 #define VCMP_IFS_WARMUP_DEFAULT (_VCMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFS */ 187 188 /* Bit fields for VCMP IFC */ 189 #define _VCMP_IFC_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFC */ 190 #define _VCMP_IFC_MASK 0x00000003UL /**< Mask for VCMP_IFC */ 191 #define VCMP_IFC_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Clear */ 192 #define _VCMP_IFC_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */ 193 #define _VCMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */ 194 #define _VCMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */ 195 #define VCMP_IFC_EDGE_DEFAULT (_VCMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IFC */ 196 #define VCMP_IFC_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Clear */ 197 #define _VCMP_IFC_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */ 198 #define _VCMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */ 199 #define _VCMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */ 200 #define VCMP_IFC_WARMUP_DEFAULT (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */ 201 202 /** @} End of group EFM32HG_VCMP */ 203 /** @} End of group Parts */ 204
