1 /***************************************************************************//** 2 * @file 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File 4 * for EFM32HG350F64 5 ******************************************************************************* 6 * # License 7 * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b> 8 ******************************************************************************* 9 * 10 * SPDX-License-Identifier: Zlib 11 * 12 * The licensor of this software is Silicon Laboratories Inc. 13 * 14 * This software is provided 'as-is', without any express or implied 15 * warranty. In no event will the authors be held liable for any damages 16 * arising from the use of this software. 17 * 18 * Permission is granted to anyone to use this software for any purpose, 19 * including commercial applications, and to alter it and redistribute it 20 * freely, subject to the following restrictions: 21 * 22 * 1. The origin of this software must not be misrepresented; you must not 23 * claim that you wrote the original software. If you use this software 24 * in a product, an acknowledgment in the product documentation would be 25 * appreciated but is not required. 26 * 2. Altered source versions must be plainly marked as such, and must not be 27 * misrepresented as being the original software. 28 * 3. This notice may not be removed or altered from any source distribution. 29 * 30 ******************************************************************************/ 31 32 #if defined(__ICCARM__) 33 #pragma system_include /* Treat file as system include file. */ 34 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 35 #pragma clang system_header /* Treat file as system include file. */ 36 #endif 37 38 #ifndef EFM32HG350F64_H 39 #define EFM32HG350F64_H 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /***************************************************************************//** 46 * @addtogroup Parts 47 * @{ 48 ******************************************************************************/ 49 50 /***************************************************************************//** 51 * @defgroup EFM32HG350F64 EFM32HG350F64 52 * @{ 53 ******************************************************************************/ 54 55 /** Interrupt Number Definition */ 56 typedef enum IRQn{ 57 /****** Cortex-M0+ Processor Exceptions Numbers *****************************************/ 58 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M0+ Non Maskable Interrupt */ 59 HardFault_IRQn = -13, /*!< -13 Cortex-M0+ Hard Fault Interrupt */ 60 SVCall_IRQn = -5, /*!< -5 Cortex-M0+ SV Call Interrupt */ 61 PendSV_IRQn = -2, /*!< -2 Cortex-M0+ Pend SV Interrupt */ 62 SysTick_IRQn = -1, /*!< -1 Cortex-M0+ System Tick Interrupt */ 63 64 /****** EFM32HG Peripheral Interrupt Numbers ********************************************/ 65 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */ 66 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */ 67 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */ 68 ACMP0_IRQn = 3, /*!< 3 EFM32 ACMP0 Interrupt */ 69 ADC0_IRQn = 4, /*!< 4 EFM32 ADC0 Interrupt */ 70 I2C0_IRQn = 5, /*!< 5 EFM32 I2C0 Interrupt */ 71 GPIO_ODD_IRQn = 6, /*!< 6 EFM32 GPIO_ODD Interrupt */ 72 TIMER1_IRQn = 7, /*!< 7 EFM32 TIMER1 Interrupt */ 73 USART1_RX_IRQn = 8, /*!< 8 EFM32 USART1_RX Interrupt */ 74 USART1_TX_IRQn = 9, /*!< 9 EFM32 USART1_TX Interrupt */ 75 LEUART0_IRQn = 10, /*!< 10 EFM32 LEUART0 Interrupt */ 76 PCNT0_IRQn = 11, /*!< 11 EFM32 PCNT0 Interrupt */ 77 RTC_IRQn = 12, /*!< 12 EFM32 RTC Interrupt */ 78 CMU_IRQn = 13, /*!< 13 EFM32 CMU Interrupt */ 79 VCMP_IRQn = 14, /*!< 14 EFM32 VCMP Interrupt */ 80 MSC_IRQn = 15, /*!< 15 EFM32 MSC Interrupt */ 81 AES_IRQn = 16, /*!< 16 EFM32 AES Interrupt */ 82 USART0_RX_IRQn = 17, /*!< 17 EFM32 USART0_RX Interrupt */ 83 USART0_TX_IRQn = 18, /*!< 18 EFM32 USART0_TX Interrupt */ 84 USB_IRQn = 19, /*!< 19 EFM32 USB Interrupt */ 85 TIMER2_IRQn = 20, /*!< 20 EFM32 TIMER2 Interrupt */ 86 } IRQn_Type; 87 88 /***************************************************************************//** 89 * @defgroup EFM32HG350F64_Core EFM32HG350F64 Core 90 * @{ 91 * @brief Processor and Core Peripheral Section 92 ******************************************************************************/ 93 #define __MPU_PRESENT 0U /**< MPU not present */ 94 #define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ 95 #define __NVIC_PRIO_BITS 2U /**< NVIC interrupt priority bits */ 96 #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ 97 98 /** @} End of group EFM32HG350F64_Core */ 99 100 /***************************************************************************//** 101 * @defgroup EFM32HG350F64_Part EFM32HG350F64 Part 102 * @{ 103 ******************************************************************************/ 104 105 /** Part family */ 106 #define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ 107 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ 108 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ 109 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ 110 #define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /**< Silicon Labs internal use only, may change any time */ 111 #define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /**< Silicon Labs internal use only, may change any time */ 112 #define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ 113 #define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ 114 115 /* If part number is not defined as compiler option, define it */ 116 #if !defined(EFM32HG350F64) 117 #define EFM32HG350F64 1 /**< Happy Gecko Part */ 118 #endif 119 120 /** Configure part number */ 121 #define PART_NUMBER "EFM32HG350F64" /**< Part Number */ 122 123 /** Memory Base addresses and limits */ 124 #define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ 125 #define RAM_MEM_SIZE (0x40000UL) /**< RAM available address space */ 126 #define RAM_MEM_END (0x2003FFFFUL) /**< RAM end address */ 127 #define RAM_MEM_BITS (0x18UL) /**< RAM used bits */ 128 #define DEVICE_MEM_BASE (0xF0040000UL) /**< DEVICE base address */ 129 #define DEVICE_MEM_SIZE (0x1000UL) /**< DEVICE available address space */ 130 #define DEVICE_MEM_END (0xF0040FFFUL) /**< DEVICE end address */ 131 #define DEVICE_MEM_BITS (0x12UL) /**< DEVICE used bits */ 132 #define USBC_MEM_BASE (0x40100000UL) /**< USBC base address */ 133 #define USBC_MEM_SIZE (0x40000UL) /**< USBC available address space */ 134 #define USBC_MEM_END (0x4013FFFFUL) /**< USBC end address */ 135 #define USBC_MEM_BITS (0x18UL) /**< USBC used bits */ 136 #define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */ 137 #define RAM_CODE_MEM_SIZE (0x20000UL) /**< RAM_CODE available address space */ 138 #define RAM_CODE_MEM_END (0x1001FFFFUL) /**< RAM_CODE end address */ 139 #define RAM_CODE_MEM_BITS (0x17UL) /**< RAM_CODE used bits */ 140 #define PER_MEM_BASE (0x40000000UL) /**< PER base address */ 141 #define PER_MEM_SIZE (0xE0000UL) /**< PER available address space */ 142 #define PER_MEM_END (0x400DFFFFUL) /**< PER end address */ 143 #define PER_MEM_BITS (0x20UL) /**< PER used bits */ 144 #define FLASH_MEM_BASE (0x0UL) /**< FLASH base address */ 145 #define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */ 146 #define FLASH_MEM_END (0xFFFFFFFUL) /**< FLASH end address */ 147 #define FLASH_MEM_BITS (0x28UL) /**< FLASH used bits */ 148 #define AES_MEM_BASE (0x400E0000UL) /**< AES base address */ 149 #define AES_MEM_SIZE (0x400UL) /**< AES available address space */ 150 #define AES_MEM_END (0x400E03FFUL) /**< AES end address */ 151 #define AES_MEM_BITS (0x10UL) /**< AES used bits */ 152 153 /** Flash and SRAM limits for EFM32HG350F64 */ 154 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ 155 #define FLASH_SIZE (0x00010000UL) /**< Available Flash Memory */ 156 #define FLASH_PAGE_SIZE 1024U /**< Flash Memory page size */ 157 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ 158 #define SRAM_SIZE (0x00002000UL) /**< Available SRAM Memory */ 159 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ 160 #define PRS_CHAN_COUNT 6 /**< Number of PRS channels */ 161 #define DMA_CHAN_COUNT 6 /**< Number of DMA channels */ 162 #define EXT_IRQ_COUNT 21 /**< Number of External (NVIC) interrupts */ 163 164 /** AF channels connect the different on-chip peripherals with the af-mux */ 165 #define AFCHAN_MAX 42U 166 #define AFCHANLOC_MAX 7U 167 /** Analog AF channels */ 168 #define AFACHAN_MAX 27U 169 170 /* Part number capabilities */ 171 172 #define TIMER_PRESENT /**< TIMER is available in this part */ 173 #define TIMER_COUNT 3 /**< 3 TIMERs available */ 174 #define ACMP_PRESENT /**< ACMP is available in this part */ 175 #define ACMP_COUNT 1 /**< 1 ACMPs available */ 176 #define USART_PRESENT /**< USART is available in this part */ 177 #define USART_COUNT 2 /**< 2 USARTs available */ 178 #define IDAC_PRESENT /**< IDAC is available in this part */ 179 #define IDAC_COUNT 1 /**< 1 IDACs available */ 180 #define ADC_PRESENT /**< ADC is available in this part */ 181 #define ADC_COUNT 1 /**< 1 ADCs available */ 182 #define LEUART_PRESENT /**< LEUART is available in this part */ 183 #define LEUART_COUNT 1 /**< 1 LEUARTs available */ 184 #define PCNT_PRESENT /**< PCNT is available in this part */ 185 #define PCNT_COUNT 1 /**< 1 PCNTs available */ 186 #define I2C_PRESENT /**< I2C is available in this part */ 187 #define I2C_COUNT 1 /**< 1 I2Cs available */ 188 #define AES_PRESENT /**< AES is available in this part */ 189 #define AES_COUNT 1 /**< 1 AES available */ 190 #define DMA_PRESENT /**< DMA is available in this part */ 191 #define DMA_COUNT 1 /**< 1 DMA available */ 192 #define LE_PRESENT /**< LE is available in this part */ 193 #define LE_COUNT 1 /**< 1 LE available */ 194 #define USBC_PRESENT /**< USBC is available in this part */ 195 #define USBC_COUNT 1 /**< 1 USBC available */ 196 #define USBLE_PRESENT /**< USBLE is available in this part */ 197 #define USBLE_COUNT 1 /**< 1 USBLE available */ 198 #define USB_PRESENT /**< USB is available in this part */ 199 #define USB_COUNT 1 /**< 1 USB available */ 200 #define MSC_PRESENT /**< MSC is available in this part */ 201 #define MSC_COUNT 1 /**< 1 MSC available */ 202 #define EMU_PRESENT /**< EMU is available in this part */ 203 #define EMU_COUNT 1 /**< 1 EMU available */ 204 #define RMU_PRESENT /**< RMU is available in this part */ 205 #define RMU_COUNT 1 /**< 1 RMU available */ 206 #define CMU_PRESENT /**< CMU is available in this part */ 207 #define CMU_COUNT 1 /**< 1 CMU available */ 208 #define PRS_PRESENT /**< PRS is available in this part */ 209 #define PRS_COUNT 1 /**< 1 PRS available */ 210 #define GPIO_PRESENT /**< GPIO is available in this part */ 211 #define GPIO_COUNT 1 /**< 1 GPIO available */ 212 #define VCMP_PRESENT /**< VCMP is available in this part */ 213 #define VCMP_COUNT 1 /**< 1 VCMP available */ 214 #define RTC_PRESENT /**< RTC is available in this part */ 215 #define RTC_COUNT 1 /**< 1 RTC available */ 216 #define HFXTAL_PRESENT /**< HFXTAL is available in this part */ 217 #define HFXTAL_COUNT 1 /**< 1 HFXTAL available */ 218 #define LFXTAL_PRESENT /**< LFXTAL is available in this part */ 219 #define LFXTAL_COUNT 1 /**< 1 LFXTAL available */ 220 #define USHFRCO_PRESENT /**< USHFRCO is available in this part */ 221 #define USHFRCO_COUNT 1 /**< 1 USHFRCO available */ 222 #define WDOG_PRESENT /**< WDOG is available in this part */ 223 #define WDOG_COUNT 1 /**< 1 WDOG available */ 224 #define DBG_PRESENT /**< DBG is available in this part */ 225 #define DBG_COUNT 1 /**< 1 DBG available */ 226 #define MTB_PRESENT /**< MTB is available in this part */ 227 #define MTB_COUNT 1 /**< 1 MTB available */ 228 #define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ 229 #define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ 230 #define ANALOG_PRESENT /**< ANALOG is available in this part */ 231 #define ANALOG_COUNT 1 /**< 1 ANALOG available */ 232 233 /** @} End of group EFM32HG350F64_Part */ 234 235 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ 236 #include "system_efm32hg.h" /* System Header */ 237 238 /***************************************************************************//** 239 * @defgroup EFM32HG350F64_Peripheral_TypeDefs EFM32HG350F64 Peripheral TypeDefs 240 * @{ 241 * @brief Device Specific Peripheral Register Structures 242 ******************************************************************************/ 243 244 #include "efm32hg_aes.h" 245 #include "efm32hg_dma_ch.h" 246 #include "efm32hg_dma.h" 247 #include "efm32hg_usb_diep.h" 248 #include "efm32hg_usb_doep.h" 249 #include "efm32hg_usb.h" 250 #include "efm32hg_msc.h" 251 #include "efm32hg_emu.h" 252 #include "efm32hg_rmu.h" 253 #include "efm32hg_cmu.h" 254 #include "efm32hg_timer_cc.h" 255 #include "efm32hg_timer.h" 256 #include "efm32hg_acmp.h" 257 #include "efm32hg_usart.h" 258 #include "efm32hg_prs_ch.h" 259 #include "efm32hg_prs.h" 260 #include "efm32hg_idac.h" 261 #include "efm32hg_gpio_p.h" 262 #include "efm32hg_gpio.h" 263 #include "efm32hg_vcmp.h" 264 #include "efm32hg_adc.h" 265 #include "efm32hg_leuart.h" 266 #include "efm32hg_pcnt.h" 267 #include "efm32hg_i2c.h" 268 #include "efm32hg_rtc.h" 269 #include "efm32hg_wdog.h" 270 #include "efm32hg_mtb.h" 271 #include "efm32hg_dma_descriptor.h" 272 #include "efm32hg_devinfo.h" 273 #include "efm32hg_romtable.h" 274 #include "efm32hg_calibrate.h" 275 276 /** @} End of group EFM32HG350F64_Peripheral_TypeDefs */ 277 278 /***************************************************************************//** 279 * @defgroup EFM32HG350F64_Peripheral_Base EFM32HG350F64 Peripheral Memory Map 280 * @{ 281 ******************************************************************************/ 282 283 #define AES_BASE (0x400E0000UL) /**< AES base address */ 284 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ 285 #define USB_BASE (0x400C4000UL) /**< USB base address */ 286 #define MSC_BASE (0x400C0000UL) /**< MSC base address */ 287 #define EMU_BASE (0x400C6000UL) /**< EMU base address */ 288 #define RMU_BASE (0x400CA000UL) /**< RMU base address */ 289 #define CMU_BASE (0x400C8000UL) /**< CMU base address */ 290 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */ 291 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */ 292 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */ 293 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */ 294 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */ 295 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */ 296 #define PRS_BASE (0x400CC000UL) /**< PRS base address */ 297 #define IDAC0_BASE (0x40004000UL) /**< IDAC0 base address */ 298 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ 299 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */ 300 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ 301 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */ 302 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */ 303 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */ 304 #define RTC_BASE (0x40080000UL) /**< RTC base address */ 305 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */ 306 #define MTB_BASE (0xF0040000UL) /**< MTB base address */ 307 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */ 308 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ 309 #define ROMTABLE_BASE (0xF00FFFD0UL) /**< ROMTABLE base address */ 310 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ 311 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ 312 313 /** @} End of group EFM32HG350F64_Peripheral_Base */ 314 315 /***************************************************************************//** 316 * @defgroup EFM32HG350F64_Peripheral_Declaration EFM32HG350F64 Peripheral Declarations 317 * @{ 318 ******************************************************************************/ 319 320 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */ 321 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */ 322 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ 323 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ 324 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ 325 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ 326 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ 327 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ 328 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ 329 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ 330 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ 331 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ 332 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ 333 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ 334 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ 335 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ 336 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */ 337 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ 338 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ 339 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ 340 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ 341 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ 342 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */ 343 #define MTB ((MTB_TypeDef *) MTB_BASE) /**< MTB base pointer */ 344 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */ 345 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ 346 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ 347 348 /** @} End of group EFM32HG350F64_Peripheral_Declaration */ 349 350 /***************************************************************************//** 351 * @defgroup EFM32HG350F64_BitFields EFM32HG350F64 Bit Fields 352 * @{ 353 ******************************************************************************/ 354 355 #include "efm32hg_prs_signals.h" 356 #include "efm32hg_dmareq.h" 357 #include "efm32hg_dmactrl.h" 358 359 /***************************************************************************//** 360 * @defgroup EFM32HG350F64_UNLOCK EFM32HG350F64 Unlock Codes 361 * @{ 362 ******************************************************************************/ 363 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ 364 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ 365 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ 366 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ 367 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ 368 369 /** @} End of group EFM32HG350F64_UNLOCK */ 370 371 /** @} End of group EFM32HG350F64_BitFields */ 372 373 /***************************************************************************//** 374 * @defgroup EFM32HG350F64_Alternate_Function EFM32HG350F64 Alternate Function 375 * @{ 376 ******************************************************************************/ 377 378 #include "efm32hg_af_ports.h" 379 #include "efm32hg_af_pins.h" 380 381 /** @} End of group EFM32HG350F64_Alternate_Function */ 382 383 /***************************************************************************//** 384 * @brief Set the value of a bit field within a register. 385 * 386 * @param REG 387 * The register to update 388 * @param MASK 389 * The mask for the bit field to update 390 * @param VALUE 391 * The value to write to the bit field 392 * @param OFFSET 393 * The number of bits that the field is offset within the register. 394 * 0 (zero) means LSB. 395 ******************************************************************************/ 396 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ 397 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); 398 399 /** @} End of group EFM32HG350F64 */ 400 401 /** @} End of group Parts */ 402 403 #ifdef __cplusplus 404 } 405 #endif 406 #endif /* EFM32HG350F64_H */ 407
