1 /***************************************************************************//**
2  * @file
3  * @brief CMSIS Cortex-M Peripheral Access Layer Header File
4  *        for EFM32GG12B310F1024GQ100
5  *******************************************************************************
6  * # License
7  * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b>
8  *******************************************************************************
9  *
10  * SPDX-License-Identifier: Zlib
11  *
12  * The licensor of this software is Silicon Laboratories Inc.
13  *
14  * This software is provided 'as-is', without any express or implied
15  * warranty. In no event will the authors be held liable for any damages
16  * arising from the use of this software.
17  *
18  * Permission is granted to anyone to use this software for any purpose,
19  * including commercial applications, and to alter it and redistribute it
20  * freely, subject to the following restrictions:
21  *
22  * 1. The origin of this software must not be misrepresented; you must not
23  *    claim that you wrote the original software. If you use this software
24  *    in a product, an acknowledgment in the product documentation would be
25  *    appreciated but is not required.
26  * 2. Altered source versions must be plainly marked as such, and must not be
27  *    misrepresented as being the original software.
28  * 3. This notice may not be removed or altered from any source distribution.
29  *
30  ******************************************************************************/
31 
32 #if defined(__ICCARM__)
33 #pragma system_include       /* Treat file as system include file. */
34 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
35 #pragma clang system_header  /* Treat file as system include file. */
36 #endif
37 
38 #ifndef EFM32GG12B310F1024GQ100_H
39 #define EFM32GG12B310F1024GQ100_H
40 
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44 
45 /***************************************************************************//**
46  * @addtogroup Parts
47  * @{
48  ******************************************************************************/
49 
50 /***************************************************************************//**
51  * @defgroup EFM32GG12B310F1024GQ100 EFM32GG12B310F1024GQ100
52  * @{
53  ******************************************************************************/
54 
55 /** Interrupt Number Definition */
56 typedef enum IRQn{
57 /******  Cortex-M4 Processor Exceptions Numbers *******************************************/
58   NonMaskableInt_IRQn   = -14,              /*!< 2 Non Maskable Interrupt                 */
59   HardFault_IRQn        = -13,              /*!< 3  Cortex-M4 Hard Fault Interrupt         */
60   MemoryManagement_IRQn = -12,              /*!< 4  Cortex-M4 Memory Management Interrupt  */
61   BusFault_IRQn         = -11,              /*!< 5  Cortex-M4 Bus Fault Interrupt          */
62   UsageFault_IRQn       = -10,              /*!< 6  Cortex-M4 Usage Fault Interrupt        */
63   SVCall_IRQn           = -5,               /*!< 11 Cortex-M4 SV Call Interrupt           */
64   DebugMonitor_IRQn     = -4,               /*!< 12 Cortex-M4 Debug Monitor Interrupt     */
65   PendSV_IRQn           = -2,               /*!< 14 Cortex-M4 Pend SV Interrupt           */
66   SysTick_IRQn          = -1,               /*!< 15 Cortex-M4 System Tick Interrupt       */
67 
68 /******  EFM32GG12B Peripheral Interrupt Numbers *********************************************/
69 
70   EMU_IRQn              = 0,  /*!< 16+0 EFM32 EMU Interrupt */
71   WDOG0_IRQn            = 1,  /*!< 16+1 EFM32 WDOG0 Interrupt */
72   LDMA_IRQn             = 2,  /*!< 16+2 EFM32 LDMA Interrupt */
73   GPIO_EVEN_IRQn        = 3,  /*!< 16+3 EFM32 GPIO_EVEN Interrupt */
74   SMU_IRQn              = 4,  /*!< 16+4 EFM32 SMU Interrupt */
75   TIMER0_IRQn           = 5,  /*!< 16+5 EFM32 TIMER0 Interrupt */
76   USART0_RX_IRQn        = 6,  /*!< 16+6 EFM32 USART0_RX Interrupt */
77   USART0_TX_IRQn        = 7,  /*!< 16+7 EFM32 USART0_TX Interrupt */
78   ACMP0_IRQn            = 8,  /*!< 16+8 EFM32 ACMP0 Interrupt */
79   ADC0_IRQn             = 9,  /*!< 16+9 EFM32 ADC0 Interrupt */
80   IDAC0_IRQn            = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */
81   I2C0_IRQn             = 11, /*!< 16+11 EFM32 I2C0 Interrupt */
82   I2C1_IRQn             = 12, /*!< 16+12 EFM32 I2C1 Interrupt */
83   GPIO_ODD_IRQn         = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */
84   TIMER1_IRQn           = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */
85   TIMER2_IRQn           = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */
86   TIMER3_IRQn           = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */
87   USART1_RX_IRQn        = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */
88   USART1_TX_IRQn        = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */
89   USART2_RX_IRQn        = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */
90   USART2_TX_IRQn        = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */
91   UART0_RX_IRQn         = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */
92   UART0_TX_IRQn         = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */
93   UART1_RX_IRQn         = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */
94   UART1_TX_IRQn         = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */
95   LEUART0_IRQn          = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */
96   LEUART1_IRQn          = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */
97   LETIMER0_IRQn         = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */
98   PCNT0_IRQn            = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */
99   PCNT1_IRQn            = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */
100   PCNT2_IRQn            = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */
101   RTCC_IRQn             = 31, /*!< 16+31 EFM32 RTCC Interrupt */
102   CMU_IRQn              = 32, /*!< 16+32 EFM32 CMU Interrupt */
103   MSC_IRQn              = 33, /*!< 16+33 EFM32 MSC Interrupt */
104   CRYPTO0_IRQn          = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */
105   CRYOTIMER_IRQn        = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */
106   FPUEH_IRQn            = 36, /*!< 16+36 EFM32 FPUEH Interrupt */
107   USART3_RX_IRQn        = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */
108   USART3_TX_IRQn        = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */
109   USART4_RX_IRQn        = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */
110   USART4_TX_IRQn        = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */
111   WTIMER0_IRQn          = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */
112   WTIMER1_IRQn          = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */
113   VDAC0_IRQn            = 43, /*!< 16+43 EFM32 VDAC0 Interrupt */
114   CSEN_IRQn             = 44, /*!< 16+44 EFM32 CSEN Interrupt */
115   LESENSE_IRQn          = 45, /*!< 16+45 EFM32 LESENSE Interrupt */
116   EBI_IRQn              = 46, /*!< 16+46 EFM32 EBI Interrupt */
117   ACMP2_IRQn            = 47, /*!< 16+47 EFM32 ACMP2 Interrupt */
118   ADC1_IRQn             = 48, /*!< 16+48 EFM32 ADC1 Interrupt */
119   LCD_IRQn              = 49, /*!< 16+49 EFM32 LCD Interrupt */
120   CAN0_IRQn             = 51, /*!< 16+51 EFM32 CAN0 Interrupt */
121   CAN1_IRQn             = 52, /*!< 16+52 EFM32 CAN1 Interrupt */
122   RTC_IRQn              = 54, /*!< 16+54 EFM32 RTC Interrupt */
123   WDOG1_IRQn            = 55, /*!< 16+55 EFM32 WDOG1 Interrupt */
124   LETIMER1_IRQn         = 56, /*!< 16+56 EFM32 LETIMER1 Interrupt */
125   TRNG0_IRQn            = 57, /*!< 16+57 EFM32 TRNG0 Interrupt */
126   PDM_IRQn              = 59, /*!< 16+59 EFM32 PDM Interrupt */
127 } IRQn_Type;
128 
129 /***************************************************************************//**
130  * @defgroup EFM32GG12B310F1024GQ100_Core Core
131  * @{
132  * @brief Processor and Core Peripheral Section
133  ******************************************************************************/
134 #define __MPU_PRESENT             1U /**< Presence of MPU  */
135 #define __FPU_PRESENT             1U /**< Presence of FPU  */
136 #define __VTOR_PRESENT            1U /**< Presence of VTOR register in SCB */
137 #define __NVIC_PRIO_BITS          3U /**< NVIC interrupt priority bits */
138 #define __Vendor_SysTickConfig    0U /**< Is 1 if different SysTick counter is used */
139 
140 /** @} End of group EFM32GG12B310F1024GQ100_Core */
141 
142 /***************************************************************************//**
143  * @defgroup EFM32GG12B310F1024GQ100_Part Part
144  * @{
145  ******************************************************************************/
146 
147 /** Part family */
148 
149 #define _EFM32_GIANT_FAMILY                      1   /**< GIANT Gecko MCU Family  */
150 #define _EFM_DEVICE                                  /**< Silicon Labs EFM-type MCU */
151 #define _SILICON_LABS_32B_SERIES_1                   /**< Silicon Labs series number */
152 #define _SILICON_LABS_32B_SERIES                 1   /**< Silicon Labs series number */
153 #define _SILICON_LABS_32B_SERIES_1_CONFIG_2          /**< Series 1, Configuration 2 */
154 #define _SILICON_LABS_32B_SERIES_1_CONFIG        2   /**< Series 1, Configuration 2 */
155 #define _SILICON_LABS_GECKO_INTERNAL_SDID        106 /**< Silicon Labs internal use only, may change any time */
156 #define _SILICON_LABS_GECKO_INTERNAL_SDID_106        /**< Silicon Labs internal use only, may change any time */
157 #define _SILICON_LABS_32B_PLATFORM_2                 /**< @deprecated Silicon Labs platform name */
158 #define _SILICON_LABS_32B_PLATFORM               2   /**< @deprecated Silicon Labs platform name */
159 #define _SILICON_LABS_32B_PLATFORM_2_GEN_2           /**< @deprecated Platform 2, generation 2 */
160 #define _SILICON_LABS_32B_PLATFORM_2_GEN         2   /**< @deprecated Platform 2, generation 2 */
161 
162 /* If part number is not defined as compiler option, define it */
163 #if !defined(EFM32GG12B310F1024GQ100)
164 #define EFM32GG12B310F1024GQ100    1 /**< GIANT Gecko Part */
165 #endif
166 
167 /** Configure part number */
168 #define PART_NUMBER                "EFM32GG12B310F1024GQ100" /**< Part Number */
169 
170 /** Memory Base addresses and limits */
171 #define RAM1_MEM_BASE              (0x20010000UL) /**< RAM1 base address  */
172 #define RAM1_MEM_SIZE              (0x10000UL)    /**< RAM1 available address space  */
173 #define RAM1_MEM_END               (0x2001FFFFUL) /**< RAM1 end address  */
174 #define RAM1_MEM_BITS              (0x00000010UL) /**< RAM1 used bits  */
175 #define PER1_BITCLR_MEM_BASE       (0x44050000UL) /**< PER1_BITCLR base address  */
176 #define PER1_BITCLR_MEM_SIZE       (0xA0000UL)    /**< PER1_BITCLR available address space  */
177 #define PER1_BITCLR_MEM_END        (0x440EFFFFUL) /**< PER1_BITCLR end address  */
178 #define PER1_BITCLR_MEM_BITS       (0x00000014UL) /**< PER1_BITCLR used bits  */
179 #define RAM2_MEM_BASE              (0x20020000UL) /**< RAM2 base address  */
180 #define RAM2_MEM_SIZE              (0x10000UL)    /**< RAM2 available address space  */
181 #define RAM2_MEM_END               (0x2002FFFFUL) /**< RAM2 end address  */
182 #define RAM2_MEM_BITS              (0x00000010UL) /**< RAM2 used bits  */
183 #define QSPI0_CODE_MEM_BASE        (0x04000000UL) /**< QSPI0_CODE base address  */
184 #define QSPI0_CODE_MEM_SIZE        (0x8000000UL)  /**< QSPI0_CODE available address space  */
185 #define QSPI0_CODE_MEM_END         (0x0BFFFFFFUL) /**< QSPI0_CODE end address  */
186 #define QSPI0_CODE_MEM_BITS        (0x0000001BUL) /**< QSPI0_CODE used bits  */
187 #define PER1_BITSET_MEM_BASE       (0x46050000UL) /**< PER1_BITSET base address  */
188 #define PER1_BITSET_MEM_SIZE       (0xA0000UL)    /**< PER1_BITSET available address space  */
189 #define PER1_BITSET_MEM_END        (0x460EFFFFUL) /**< PER1_BITSET end address  */
190 #define PER1_BITSET_MEM_BITS       (0x00000014UL) /**< PER1_BITSET used bits  */
191 #define CRYPTO0_BITCLR_MEM_BASE    (0x440F0000UL) /**< CRYPTO0_BITCLR base address  */
192 #define CRYPTO0_BITCLR_MEM_SIZE    (0x400UL)      /**< CRYPTO0_BITCLR available address space  */
193 #define CRYPTO0_BITCLR_MEM_END     (0x440F03FFUL) /**< CRYPTO0_BITCLR end address  */
194 #define CRYPTO0_BITCLR_MEM_BITS    (0x0000000AUL) /**< CRYPTO0_BITCLR used bits  */
195 #define USB_MEM_BASE               (0x40100000UL) /**< USB base address  */
196 #define USB_MEM_SIZE               (0x40000UL)    /**< USB available address space  */
197 #define USB_MEM_END                (0x4013FFFFUL) /**< USB end address  */
198 #define USB_MEM_BITS               (0x00000012UL) /**< USB used bits  */
199 #define QSPI0_MEM_BASE             (0xC0000000UL) /**< QSPI0 base address  */
200 #define QSPI0_MEM_SIZE             (0x10000000UL) /**< QSPI0 available address space  */
201 #define QSPI0_MEM_END              (0xCFFFFFFFUL) /**< QSPI0 end address  */
202 #define QSPI0_MEM_BITS             (0x0000001CUL) /**< QSPI0 used bits  */
203 #define CRYPTO0_BITSET_MEM_BASE    (0x460F0000UL) /**< CRYPTO0_BITSET base address  */
204 #define CRYPTO0_BITSET_MEM_SIZE    (0x400UL)      /**< CRYPTO0_BITSET available address space  */
205 #define CRYPTO0_BITSET_MEM_END     (0x460F03FFUL) /**< CRYPTO0_BITSET end address  */
206 #define CRYPTO0_BITSET_MEM_BITS    (0x0000000AUL) /**< CRYPTO0_BITSET used bits  */
207 #define RAM1_CODE_MEM_BASE         (0x10010000UL) /**< RAM1_CODE base address  */
208 #define RAM1_CODE_MEM_SIZE         (0x10000UL)    /**< RAM1_CODE available address space  */
209 #define RAM1_CODE_MEM_END          (0x1001FFFFUL) /**< RAM1_CODE end address  */
210 #define RAM1_CODE_MEM_BITS         (0x00000010UL) /**< RAM1_CODE used bits  */
211 #define EBI_MEM_BASE               (0x80000000UL) /**< EBI base address  */
212 #define EBI_MEM_SIZE               (0x40000000UL) /**< EBI available address space  */
213 #define EBI_MEM_END                (0xBFFFFFFFUL) /**< EBI end address  */
214 #define EBI_MEM_BITS               (0x0000001EUL) /**< EBI used bits  */
215 #define RAM0_CODE_MEM_BASE         (0x10000000UL) /**< RAM0_CODE base address  */
216 #define RAM0_CODE_MEM_SIZE         (0x10000UL)    /**< RAM0_CODE available address space  */
217 #define RAM0_CODE_MEM_END          (0x1000FFFFUL) /**< RAM0_CODE end address  */
218 #define RAM0_CODE_MEM_BITS         (0x00000010UL) /**< RAM0_CODE used bits  */
219 #define FLASH_MEM_BASE             (0x00000000UL) /**< FLASH base address  */
220 #define FLASH_MEM_SIZE             (0x4000000UL)  /**< FLASH available address space  */
221 #define FLASH_MEM_END              (0x03FFFFFFUL) /**< FLASH end address  */
222 #define FLASH_MEM_BITS             (0x0000001AUL) /**< FLASH used bits  */
223 #define FLASH_INFO_MEM_BASE        (0x0F000000UL) /**< FLASH_INFO base address  */
224 #define FLASH_INFO_MEM_SIZE        (0x1000000UL)  /**< FLASH_INFO available address space  */
225 #define FLASH_INFO_MEM_END         (0x0FFFFFFFUL) /**< FLASH_INFO end address  */
226 #define FLASH_INFO_MEM_BITS        (0x00000018UL) /**< FLASH_INFO used bits  */
227 #define SDIO_MEM_BASE              (0x400F1000UL) /**< SDIO base address  */
228 #define SDIO_MEM_SIZE              (0x1000UL)     /**< SDIO available address space  */
229 #define SDIO_MEM_END               (0x400F1FFFUL) /**< SDIO end address  */
230 #define SDIO_MEM_BITS              (0x0000000CUL) /**< SDIO used bits  */
231 #define PER1_MEM_BASE              (0x40050000UL) /**< PER1 base address  */
232 #define PER1_MEM_SIZE              (0xA0000UL)    /**< PER1 available address space  */
233 #define PER1_MEM_END               (0x400EFFFFUL) /**< PER1 end address  */
234 #define PER1_MEM_BITS              (0x00000014UL) /**< PER1 used bits  */
235 #define RAM0_MEM_BASE              (0x20000000UL) /**< RAM0 base address  */
236 #define RAM0_MEM_SIZE              (0x10000UL)    /**< RAM0 available address space  */
237 #define RAM0_MEM_END               (0x2000FFFFUL) /**< RAM0 end address  */
238 #define RAM0_MEM_BITS              (0x00000010UL) /**< RAM0 used bits  */
239 #define CRYPTO0_MEM_BASE           (0x400F0000UL) /**< CRYPTO0 base address  */
240 #define CRYPTO0_MEM_SIZE           (0x400UL)      /**< CRYPTO0 available address space  */
241 #define CRYPTO0_MEM_END            (0x400F03FFUL) /**< CRYPTO0 end address  */
242 #define CRYPTO0_MEM_BITS           (0x0000000AUL) /**< CRYPTO0 used bits  */
243 #define PER_BITSET_MEM_BASE        (0x46000000UL) /**< PER_BITSET base address  */
244 #define PER_BITSET_MEM_SIZE        (0x50000UL)    /**< PER_BITSET available address space  */
245 #define PER_BITSET_MEM_END         (0x4604FFFFUL) /**< PER_BITSET end address  */
246 #define PER_BITSET_MEM_BITS        (0x00000013UL) /**< PER_BITSET used bits  */
247 #define EBI_CODE_MEM_BASE          (0x12000000UL) /**< EBI_CODE base address  */
248 #define EBI_CODE_MEM_SIZE          (0xE000000UL)  /**< EBI_CODE available address space  */
249 #define EBI_CODE_MEM_END           (0x1FFFFFFFUL) /**< EBI_CODE end address  */
250 #define EBI_CODE_MEM_BITS          (0x0000001CUL) /**< EBI_CODE used bits  */
251 #define PER_MEM_BASE               (0x40000000UL) /**< PER base address  */
252 #define PER_MEM_SIZE               (0x50000UL)    /**< PER available address space  */
253 #define PER_MEM_END                (0x4004FFFFUL) /**< PER end address  */
254 #define PER_MEM_BITS               (0x00000013UL) /**< PER used bits  */
255 #define RAM2_CODE_MEM_BASE         (0x10020000UL) /**< RAM2_CODE base address  */
256 #define RAM2_CODE_MEM_SIZE         (0x10000UL)    /**< RAM2_CODE available address space  */
257 #define RAM2_CODE_MEM_END          (0x1002FFFFUL) /**< RAM2_CODE end address  */
258 #define RAM2_CODE_MEM_BITS         (0x00000010UL) /**< RAM2_CODE used bits  */
259 #define PER_BITCLR_MEM_BASE        (0x44000000UL) /**< PER_BITCLR base address  */
260 #define PER_BITCLR_MEM_SIZE        (0x50000UL)    /**< PER_BITCLR available address space  */
261 #define PER_BITCLR_MEM_END         (0x4404FFFFUL) /**< PER_BITCLR end address  */
262 #define PER_BITCLR_MEM_BITS        (0x00000013UL) /**< PER_BITCLR used bits  */
263 
264 /** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */
265 #define RAM_MEM_BASE               (0x20000000UL) /**< RAM base address  */
266 #define RAM_MEM_SIZE               (0x30000UL)    /**< RAM available address space  */
267 #define RAM_MEM_END                (0x2002FFFFUL) /**< RAM end address  */
268 #define RAM_MEM_BITS               (0x00000012UL) /**< RAM used bits  */
269 
270 /** Bit banding area */
271 #define BITBAND_PER_BASE           (0x42000000UL) /**< Peripheral Address Space bit-band area */
272 #define BITBAND_RAM_BASE           (0x22000000UL) /**< SRAM Address Space bit-band area */
273 
274 /** Flash and SRAM limits for EFM32GG12B310F1024GQ100 */
275 #define FLASH_BASE                 (0x00000000UL) /**< Flash Base Address */
276 #define FLASH_SIZE                 (0x00100000UL) /**< Available Flash Memory */
277 #define FLASH_PAGE_SIZE            2048U          /**< Flash Memory page size (interleaving off) */
278 #define SRAM_BASE                  (0x20000000UL) /**< SRAM Base Address */
279 #define SRAM_SIZE                  (0x00030000UL) /**< Available SRAM Memory */
280 #define __CM4_REV                  0x0001U        /**< Cortex-M4 Core revision r0p1 */
281 #define PRS_CHAN_COUNT             16             /**< Number of PRS channels */
282 #define DMA_CHAN_COUNT             12             /**< Number of DMA channels */
283 #define EXT_IRQ_COUNT              60             /**< Number of External (NVIC) interrupts */
284 
285 /** AF channels connect the different on-chip peripherals with the af-mux */
286 #define AFCHAN_MAX                 265U
287 /** AF channel maximum location number */
288 #define AFCHANLOC_MAX              8U
289 /** Analog AF channels */
290 #define AFACHAN_MAX                172U
291 
292 /* Part number capabilities */
293 
294 #define CRYPTO_PRESENT          /**< CRYPTO is available in this part */
295 #define CRYPTO_COUNT          1 /**< 1 CRYPTOs available  */
296 #define CAN_PRESENT             /**< CAN is available in this part */
297 #define CAN_COUNT             2 /**< 2 CANs available  */
298 #define TIMER_PRESENT           /**< TIMER is available in this part */
299 #define TIMER_COUNT           4 /**< 4 TIMERs available  */
300 #define WTIMER_PRESENT          /**< WTIMER is available in this part */
301 #define WTIMER_COUNT          2 /**< 2 WTIMERs available  */
302 #define USART_PRESENT           /**< USART is available in this part */
303 #define USART_COUNT           5 /**< 5 USARTs available  */
304 #define UART_PRESENT            /**< UART is available in this part */
305 #define UART_COUNT            2 /**< 2 UARTs available  */
306 #define LEUART_PRESENT          /**< LEUART is available in this part */
307 #define LEUART_COUNT          2 /**< 2 LEUARTs available  */
308 #define LETIMER_PRESENT         /**< LETIMER is available in this part */
309 #define LETIMER_COUNT         2 /**< 2 LETIMERs available  */
310 #define PCNT_PRESENT            /**< PCNT is available in this part */
311 #define PCNT_COUNT            3 /**< 3 PCNTs available  */
312 #define I2C_PRESENT             /**< I2C is available in this part */
313 #define I2C_COUNT             2 /**< 2 I2Cs available  */
314 #define ADC_PRESENT             /**< ADC is available in this part */
315 #define ADC_COUNT             2 /**< 2 ADCs available  */
316 #define ACMP_PRESENT            /**< ACMP is available in this part */
317 #define ACMP_COUNT            3 /**< 3 ACMPs available  */
318 #define VDAC_PRESENT            /**< VDAC is available in this part */
319 #define VDAC_COUNT            1 /**< 1 VDACs available  */
320 #define IDAC_PRESENT            /**< IDAC is available in this part */
321 #define IDAC_COUNT            1 /**< 1 IDACs available  */
322 #define WDOG_PRESENT            /**< WDOG is available in this part */
323 #define WDOG_COUNT            2 /**< 2 WDOGs available  */
324 #define TRNG_PRESENT            /**< TRNG is available in this part */
325 #define TRNG_COUNT            1 /**< 1 TRNGs available  */
326 #define MSC_PRESENT             /**< MSC is available in this part */
327 #define MSC_COUNT             1 /**< 1 MSC available */
328 #define EMU_PRESENT             /**< EMU is available in this part */
329 #define EMU_COUNT             1 /**< 1 EMU available */
330 #define RMU_PRESENT             /**< RMU is available in this part */
331 #define RMU_COUNT             1 /**< 1 RMU available */
332 #define CMU_PRESENT             /**< CMU is available in this part */
333 #define CMU_COUNT             1 /**< 1 CMU available */
334 #define LESENSE_PRESENT         /**< LESENSE is available in this part */
335 #define LESENSE_COUNT         1 /**< 1 LESENSE available */
336 #define EBI_PRESENT             /**< EBI is available in this part */
337 #define EBI_COUNT             1 /**< 1 EBI available */
338 #define PDM_PRESENT             /**< PDM is available in this part */
339 #define PDM_COUNT             1 /**< 1 PDM available */
340 #define GPIO_PRESENT            /**< GPIO is available in this part */
341 #define GPIO_COUNT            1 /**< 1 GPIO available */
342 #define PRS_PRESENT             /**< PRS is available in this part */
343 #define PRS_COUNT             1 /**< 1 PRS available */
344 #define LDMA_PRESENT            /**< LDMA is available in this part */
345 #define LDMA_COUNT            1 /**< 1 LDMA available */
346 #define FPUEH_PRESENT           /**< FPUEH is available in this part */
347 #define FPUEH_COUNT           1 /**< 1 FPUEH available */
348 #define GPCRC_PRESENT           /**< GPCRC is available in this part */
349 #define GPCRC_COUNT           1 /**< 1 GPCRC available */
350 #define CRYOTIMER_PRESENT       /**< CRYOTIMER is available in this part */
351 #define CRYOTIMER_COUNT       1 /**< 1 CRYOTIMER available */
352 #define BU_PRESENT              /**< BU is available in this part */
353 #define BU_COUNT              1 /**< 1 BU available */
354 #define CSEN_PRESENT            /**< CSEN is available in this part */
355 #define CSEN_COUNT            1 /**< 1 CSEN available */
356 #define LCD_PRESENT             /**< LCD is available in this part */
357 #define LCD_COUNT             1 /**< 1 LCD available */
358 #define RTC_PRESENT             /**< RTC is available in this part */
359 #define RTC_COUNT             1 /**< 1 RTC available */
360 #define RTCC_PRESENT            /**< RTCC is available in this part */
361 #define RTCC_COUNT            1 /**< 1 RTCC available */
362 #define ETM_PRESENT             /**< ETM is available in this part */
363 #define ETM_COUNT             1 /**< 1 ETM available */
364 #define BOOTLOADER_PRESENT      /**< BOOTLOADER is available in this part */
365 #define BOOTLOADER_COUNT      1 /**< 1 BOOTLOADER available */
366 #define SMU_PRESENT             /**< SMU is available in this part */
367 #define SMU_COUNT             1 /**< 1 SMU available */
368 
369 #include "core_cm4.h"           /* Cortex-M4 processor and core peripherals */
370 #include "system_efm32gg12b.h"  /* System Header File */
371 
372 /** @} End of group EFM32GG12B310F1024GQ100_Part */
373 
374 /***************************************************************************//**
375  * @defgroup EFM32GG12B310F1024GQ100_Peripheral_TypeDefs Peripheral TypeDefs
376  * @{
377  * @brief Device Specific Peripheral Register Structures
378  ******************************************************************************/
379 
380 /***************************************************************************//**
381  * @defgroup EFM32GG12B310F1024GQ100_MSC MSC
382  * @{
383  * @brief EFM32GG12B310F1024GQ100_MSC Register Declaration
384  ******************************************************************************/
385 /** MSC Register Declaration */
386 typedef struct {
387   __IOM uint32_t CTRL;           /**< Memory System Control Register  */
388   __IOM uint32_t READCTRL;       /**< Read Control Register  */
389   __IOM uint32_t WRITECTRL;      /**< Write Control Register  */
390   __IOM uint32_t WRITECMD;       /**< Write Command Register  */
391   __IOM uint32_t ADDRB;          /**< Page Erase/Write Address Buffer  */
392   uint32_t       RESERVED0[1U];  /**< Reserved for future use **/
393   __IOM uint32_t WDATA;          /**< Write Data Register  */
394   __IM uint32_t  STATUS;         /**< Status Register  */
395 
396   uint32_t       RESERVED1[4U];  /**< Reserved for future use **/
397   __IM uint32_t  IF;             /**< Interrupt Flag Register  */
398   __IOM uint32_t IFS;            /**< Interrupt Flag Set Register  */
399   __IOM uint32_t IFC;            /**< Interrupt Flag Clear Register  */
400   __IOM uint32_t IEN;            /**< Interrupt Enable Register  */
401   __IOM uint32_t LOCK;           /**< Configuration Lock Register  */
402   __IOM uint32_t CACHECMD;       /**< Flash Cache Command Register  */
403   __IM uint32_t  CACHEHITS;      /**< Cache Hits Performance Counter  */
404   __IM uint32_t  CACHEMISSES;    /**< Cache Misses Performance Counter  */
405 
406   uint32_t       RESERVED2[1U];  /**< Reserved for future use **/
407   __IOM uint32_t MASSLOCK;       /**< Mass Erase Lock Register  */
408 
409   uint32_t       RESERVED3[1U];  /**< Reserved for future use **/
410   __IOM uint32_t STARTUP;        /**< Startup Control  */
411 
412   uint32_t       RESERVED4[4U];  /**< Reserved for future use **/
413   __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register  */
414   __IOM uint32_t CMD;            /**< Command Register  */
415 
416   uint32_t       RESERVED5[6U];  /**< Reserved for future use **/
417   __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register  */
418   __IOM uint32_t AAPUNLOCKCMD;   /**< Software Unlock AAP Command Register  */
419   __IOM uint32_t CACHECONFIG0;   /**< Cache Configuration Register 0  */
420 
421   uint32_t       RESERVED6[25U]; /**< Reserved for future use **/
422   __IOM uint32_t RAMCTRL;        /**< RAM Control Enable Register  */
423   __IOM uint32_t ECCCTRL;        /**< RAM ECC Control Register  */
424   __IM uint32_t  RAMECCADDR;     /**< RAM ECC Error Address Register  */
425   __IM uint32_t  RAM1ECCADDR;    /**< RAM1 ECC Error Address Register  */
426   __IM uint32_t  RAM2ECCADDR;    /**< RAM2 ECC Error Address Register  */
427 } MSC_TypeDef;                   /** @} */
428 
429 /***************************************************************************//**
430  * @defgroup EFM32GG12B310F1024GQ100_EMU EMU
431  * @{
432  * @brief EFM32GG12B310F1024GQ100_EMU Register Declaration
433  ******************************************************************************/
434 /** EMU Register Declaration */
435 typedef struct {
436   __IOM uint32_t CTRL;                  /**< Control Register  */
437   __IM uint32_t  STATUS;                /**< Status Register  */
438   __IOM uint32_t LOCK;                  /**< Configuration Lock Register  */
439   __IOM uint32_t RAM0CTRL;              /**< Memory Control Register  */
440   __IOM uint32_t CMD;                   /**< Command Register  */
441 
442   uint32_t       RESERVED0[1U];         /**< Reserved for future use **/
443   __IOM uint32_t EM4CTRL;               /**< EM4 Control Register  */
444   __IOM uint32_t TEMPLIMITS;            /**< Temperature Limits for Interrupt Generation  */
445   __IM uint32_t  TEMP;                  /**< Value of Last Temperature Measurement  */
446   __IM uint32_t  IF;                    /**< Interrupt Flag Register  */
447   __IOM uint32_t IFS;                   /**< Interrupt Flag Set Register  */
448   __IOM uint32_t IFC;                   /**< Interrupt Flag Clear Register  */
449   __IOM uint32_t IEN;                   /**< Interrupt Enable Register  */
450   __IOM uint32_t PWRLOCK;               /**< Regulator and Supply Lock Register  */
451 
452   uint32_t       RESERVED1[1U];         /**< Reserved for future use **/
453   __IOM uint32_t PWRCTRL;               /**< Power Control Register  */
454   __IOM uint32_t DCDCCTRL;              /**< DCDC Control  */
455 
456   uint32_t       RESERVED2[2U];         /**< Reserved for future use **/
457   __IOM uint32_t DCDCMISCCTRL;          /**< DCDC Miscellaneous Control Register  */
458   __IOM uint32_t DCDCZDETCTRL;          /**< DCDC Power Train NFET Zero Current Detector Control Register  */
459   __IOM uint32_t DCDCCLIMCTRL;          /**< DCDC Power Train PFET Current Limiter Control Register  */
460   __IOM uint32_t DCDCLNCOMPCTRL;        /**< DCDC Low Noise Compensator Control Register  */
461   __IOM uint32_t DCDCLNVCTRL;           /**< DCDC Low Noise Voltage Register  */
462 
463   uint32_t       RESERVED3[1U];         /**< Reserved for future use **/
464   __IOM uint32_t DCDCLPVCTRL;           /**< DCDC Low Power Voltage Register  */
465 
466   uint32_t       RESERVED4[1U];         /**< Reserved for future use **/
467   __IOM uint32_t DCDCLPCTRL;            /**< DCDC Low Power Control Register  */
468   __IOM uint32_t DCDCLNFREQCTRL;        /**< DCDC Low Noise Controller Frequency Control  */
469 
470   uint32_t       RESERVED5[1U];         /**< Reserved for future use **/
471   __IM uint32_t  DCDCSYNC;              /**< DCDC Read Status Register  */
472 
473   uint32_t       RESERVED6[5U];         /**< Reserved for future use **/
474   __IOM uint32_t VMONAVDDCTRL;          /**< VMON AVDD Channel Control  */
475   __IOM uint32_t VMONALTAVDDCTRL;       /**< Alternate VMON AVDD Channel Control  */
476   __IOM uint32_t VMONDVDDCTRL;          /**< VMON DVDD Channel Control  */
477   __IOM uint32_t VMONIO0CTRL;           /**< VMON IOVDD0 Channel Control  */
478   __IOM uint32_t VMONIO1CTRL;           /**< VMON IOVDD1 Channel Control  */
479   __IOM uint32_t VMONBUVDDCTRL;         /**< VMON BUVDD Channel Control  */
480 
481   uint32_t       RESERVED7[3U];         /**< Reserved for future use **/
482   __IOM uint32_t RAM1CTRL;              /**< Memory Control Register  */
483   __IOM uint32_t RAM2CTRL;              /**< Memory Control Register  */
484   __IOM uint32_t BUCTRL;                /**< Backup Power Configuration Register  */
485   uint32_t       RESERVED8[2U];         /**< Reserved for future use **/
486   __IOM uint32_t R5VCTRL;               /**< 5V Regulator Control  */
487   __IOM uint32_t R5VADCCTRL;            /**< 5V Regulator Control  */
488   __IOM uint32_t R5VOUTLEVEL;           /**< 5V Regulator Voltage Select  */
489 
490   uint32_t       RESERVED9[2U];         /**< Reserved for future use **/
491   __IOM uint32_t R5VDETCTRL;            /**< 5V Detector Enables  */
492 
493   uint32_t       RESERVED10[3U];        /**< Reserved for future use **/
494   __IOM uint32_t DCDCLPEM01CFG;         /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01  */
495   __IM uint32_t  R5VSTATUS;             /**< 5V Detector Status Register  */
496 
497   uint32_t       RESERVED11[1U];        /**< Reserved for future use **/
498   __IM uint32_t  R5VSYNC;               /**< 5V Read Status Register  */
499 
500   uint32_t       RESERVED12[1U];        /**< Reserved for future use **/
501   __IOM uint32_t EM23PERNORETAINCMD;    /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral  */
502   __IM uint32_t  EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It  */
503   __IOM uint32_t EM23PERNORETAINCTRL;   /**< When Set Corresponding Peripherals May Get Powered Down in EM23  */
504 } EMU_TypeDef;                          /** @} */
505 
506 #include "efm32gg12b_rmu.h"
507 
508 /***************************************************************************//**
509  * @defgroup EFM32GG12B310F1024GQ100_CMU CMU
510  * @{
511  * @brief EFM32GG12B310F1024GQ100_CMU Register Declaration
512  ******************************************************************************/
513 /** CMU Register Declaration */
514 typedef struct {
515   __IOM uint32_t CTRL;                /**< CMU Control Register  */
516   uint32_t       RESERVED0[1U];       /**< Reserved for future use **/
517   __IOM uint32_t USHFRCOCTRL;         /**< USHFRCO Control Register  */
518 
519   uint32_t       RESERVED1[1U];       /**< Reserved for future use **/
520   __IOM uint32_t HFRCOCTRL;           /**< HFRCO Control Register  */
521 
522   uint32_t       RESERVED2[1U];       /**< Reserved for future use **/
523   __IOM uint32_t AUXHFRCOCTRL;        /**< AUXHFRCO Control Register  */
524 
525   uint32_t       RESERVED3[1U];       /**< Reserved for future use **/
526   __IOM uint32_t LFRCOCTRL;           /**< LFRCO Control Register  */
527   __IOM uint32_t HFXOCTRL;            /**< HFXO Control Register  */
528   __IOM uint32_t HFXOCTRL1;           /**< HFXO Control 1  */
529   __IOM uint32_t HFXOSTARTUPCTRL;     /**< HFXO Startup Control  */
530   __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control  */
531   __IOM uint32_t HFXOTIMEOUTCTRL;     /**< HFXO Timeout Control  */
532   __IOM uint32_t LFXOCTRL;            /**< LFXO Control Register  */
533 
534   uint32_t       RESERVED4[1U];       /**< Reserved for future use **/
535   __IOM uint32_t DPLLCTRL;            /**< DPLL Control Register  */
536   __IOM uint32_t DPLLCTRL1;           /**< DPLL Control Register  */
537   uint32_t       RESERVED5[2U];       /**< Reserved for future use **/
538   __IOM uint32_t CALCTRL;             /**< Calibration Control Register  */
539   __IOM uint32_t CALCNT;              /**< Calibration Counter Register  */
540   uint32_t       RESERVED6[2U];       /**< Reserved for future use **/
541   __IOM uint32_t OSCENCMD;            /**< Oscillator Enable/Disable Command Register  */
542   __IOM uint32_t CMD;                 /**< Command Register  */
543   uint32_t       RESERVED7[2U];       /**< Reserved for future use **/
544   __IOM uint32_t DBGCLKSEL;           /**< Debug Trace Clock Select  */
545   __IOM uint32_t HFCLKSEL;            /**< High Frequency Clock Select Command Register  */
546   uint32_t       RESERVED8[2U];       /**< Reserved for future use **/
547   __IOM uint32_t LFACLKSEL;           /**< Low Frequency A Clock Select Register  */
548   __IOM uint32_t LFBCLKSEL;           /**< Low Frequency B Clock Select Register  */
549   __IOM uint32_t LFECLKSEL;           /**< Low Frequency E Clock Select Register  */
550   __IOM uint32_t LFCCLKSEL;           /**< Low Frequency C Clock Select Register  */
551   __IM uint32_t  STATUS;              /**< Status Register  */
552   __IM uint32_t  HFCLKSTATUS;         /**< HFCLK Status Register  */
553   uint32_t       RESERVED9[1U];       /**< Reserved for future use **/
554   __IM uint32_t  HFXOTRIMSTATUS;      /**< HFXO Trim Status  */
555   __IM uint32_t  IF;                  /**< Interrupt Flag Register  */
556   __IOM uint32_t IFS;                 /**< Interrupt Flag Set Register  */
557   __IOM uint32_t IFC;                 /**< Interrupt Flag Clear Register  */
558   __IOM uint32_t IEN;                 /**< Interrupt Enable Register  */
559   __IOM uint32_t HFBUSCLKEN0;         /**< High Frequency Bus Clock Enable Register 0  */
560 
561   uint32_t       RESERVED10[3U];      /**< Reserved for future use **/
562   __IOM uint32_t HFPERCLKEN0;         /**< High Frequency Peripheral Clock Enable Register 0  */
563   __IOM uint32_t HFPERCLKEN1;         /**< High Frequency Peripheral Clock Enable Register 1  */
564 
565   uint32_t       RESERVED11[6U];      /**< Reserved for future use **/
566   __IOM uint32_t LFACLKEN0;           /**< Low Frequency a Clock Enable Register 0  (Async Reg)  */
567   uint32_t       RESERVED12[1U];      /**< Reserved for future use **/
568   __IOM uint32_t LFBCLKEN0;           /**< Low Frequency B Clock Enable Register 0 (Async Reg)  */
569   __IOM uint32_t LFCCLKEN0;           /**< Low Frequency C Clock Enable Register 0 (Async Reg)  */
570   __IOM uint32_t LFECLKEN0;           /**< Low Frequency E Clock Enable Register 0 (Async Reg)  */
571   uint32_t       RESERVED13[3U];      /**< Reserved for future use **/
572   __IOM uint32_t HFPRESC;             /**< High Frequency Clock Prescaler Register  */
573   __IOM uint32_t HFBUSPRESC;          /**< High Frequency Bus Clock Prescaler Register  */
574   __IOM uint32_t HFCOREPRESC;         /**< High Frequency Core Clock Prescaler Register  */
575   __IOM uint32_t HFPERPRESC;          /**< High Frequency Peripheral Clock Prescaler Register  */
576 
577   uint32_t       RESERVED14[1U];      /**< Reserved for future use **/
578   __IOM uint32_t HFEXPPRESC;          /**< High Frequency Export Clock Prescaler Register  */
579   __IOM uint32_t HFPERPRESCB;         /**< High Frequency Peripheral Clock Prescaler B Register  */
580   __IOM uint32_t HFPERPRESCC;         /**< High Frequency Peripheral Clock Prescaler C Register  */
581   __IOM uint32_t LFAPRESC0;           /**< Low Frequency a Prescaler Register 0 (Async Reg)  */
582   uint32_t       RESERVED15[1U];      /**< Reserved for future use **/
583   __IOM uint32_t LFBPRESC0;           /**< Low Frequency B Prescaler Register 0  (Async Reg)  */
584   uint32_t       RESERVED16[1U];      /**< Reserved for future use **/
585   __IOM uint32_t LFEPRESC0;           /**< Low Frequency E Prescaler Register 0  (Async Reg)  */
586 
587   uint32_t       RESERVED17[3U];      /**< Reserved for future use **/
588   __IM uint32_t  SYNCBUSY;            /**< Synchronization Busy Register  */
589   __IOM uint32_t FREEZE;              /**< Freeze Register  */
590   uint32_t       RESERVED18[2U];      /**< Reserved for future use **/
591   __IOM uint32_t PCNTCTRL;            /**< PCNT Control Register  */
592 
593   uint32_t       RESERVED19[2U];      /**< Reserved for future use **/
594   __IOM uint32_t ADCCTRL;             /**< ADC Control Register  */
595 
596   uint32_t       RESERVED20[2U];      /**< Reserved for future use **/
597   __IOM uint32_t PDMCTRL;             /**< PDM Control Register  */
598   uint32_t       RESERVED21[1U];      /**< Reserved for future use **/
599   __IOM uint32_t ROUTEPEN;            /**< I/O Routing Pin Enable Register  */
600   __IOM uint32_t ROUTELOC0;           /**< I/O Routing Location Register  */
601   __IOM uint32_t ROUTELOC1;           /**< I/O Routing Location Register  */
602   uint32_t       RESERVED22[1U];      /**< Reserved for future use **/
603   __IOM uint32_t LOCK;                /**< Configuration Lock Register  */
604   __IOM uint32_t HFRCOSS;             /**< HFRCO Spread Spectrum Register  */
605 } CMU_TypeDef;                        /** @} */
606 
607 #include "efm32gg12b_crypto.h"
608 #include "efm32gg12b_lesense_st.h"
609 #include "efm32gg12b_lesense_buf.h"
610 #include "efm32gg12b_lesense_ch.h"
611 #include "efm32gg12b_lesense.h"
612 #include "efm32gg12b_ebi.h"
613 #include "efm32gg12b_pdm.h"
614 #include "efm32gg12b_gpio_p.h"
615 #include "efm32gg12b_gpio.h"
616 #include "efm32gg12b_prs_ch.h"
617 
618 /***************************************************************************//**
619  * @defgroup EFM32GG12B310F1024GQ100_PRS PRS
620  * @{
621  * @brief EFM32GG12B310F1024GQ100_PRS Register Declaration
622  ******************************************************************************/
623 /** PRS Register Declaration */
624 typedef struct {
625   __IOM uint32_t SWPULSE;       /**< Software Pulse Register  */
626   __IOM uint32_t SWLEVEL;       /**< Software Level Register  */
627   __IOM uint32_t ROUTEPEN;      /**< I/O Routing Pin Enable Register  */
628   uint32_t       RESERVED0[1U]; /**< Reserved for future use **/
629   __IOM uint32_t ROUTELOC0;     /**< I/O Routing Location Register  */
630   __IOM uint32_t ROUTELOC1;     /**< I/O Routing Location Register  */
631   __IOM uint32_t ROUTELOC2;     /**< I/O Routing Location Register  */
632   __IOM uint32_t ROUTELOC3;     /**< I/O Routing Location Register  */
633 
634   uint32_t       RESERVED1[4U]; /**< Reserved for future use **/
635   __IOM uint32_t CTRL;          /**< Control Register  */
636   __IOM uint32_t DMAREQ0;       /**< DMA Request 0 Register  */
637   __IOM uint32_t DMAREQ1;       /**< DMA Request 1 Register  */
638   uint32_t       RESERVED2[1U]; /**< Reserved for future use **/
639   __IM uint32_t  PEEK;          /**< PRS Channel Values  */
640 
641   uint32_t       RESERVED3[3U]; /**< Reserved registers */
642   PRS_CH_TypeDef CH[16U];       /**< Channel registers */
643 } PRS_TypeDef;                  /** @} */
644 
645 #include "efm32gg12b_ldma_ch.h"
646 #include "efm32gg12b_ldma.h"
647 #include "efm32gg12b_fpueh.h"
648 #include "efm32gg12b_gpcrc.h"
649 #include "efm32gg12b_can_mir.h"
650 #include "efm32gg12b_can.h"
651 #include "efm32gg12b_timer_cc.h"
652 #include "efm32gg12b_timer.h"
653 #include "efm32gg12b_usart.h"
654 #include "efm32gg12b_leuart.h"
655 #include "efm32gg12b_letimer.h"
656 #include "efm32gg12b_cryotimer.h"
657 #include "efm32gg12b_pcnt.h"
658 #include "efm32gg12b_i2c.h"
659 #include "efm32gg12b_adc.h"
660 #include "efm32gg12b_acmp.h"
661 #include "efm32gg12b_vdac_opa.h"
662 #include "efm32gg12b_vdac.h"
663 #include "efm32gg12b_idac.h"
664 #include "efm32gg12b_csen.h"
665 #include "efm32gg12b_lcd.h"
666 #include "efm32gg12b_rtc_comp.h"
667 #include "efm32gg12b_rtc.h"
668 #include "efm32gg12b_rtcc_cc.h"
669 #include "efm32gg12b_rtcc_ret.h"
670 #include "efm32gg12b_rtcc.h"
671 #include "efm32gg12b_wdog_pch.h"
672 #include "efm32gg12b_wdog.h"
673 #include "efm32gg12b_etm.h"
674 
675 /***************************************************************************//**
676  * @defgroup EFM32GG12B310F1024GQ100_SMU SMU
677  * @{
678  * @brief EFM32GG12B310F1024GQ100_SMU Register Declaration
679  ******************************************************************************/
680 /** SMU Register Declaration */
681 typedef struct {
682   uint32_t       RESERVED0[3U];  /**< Reserved for future use **/
683   __IM uint32_t  IF;             /**< Interrupt Flag Register  */
684   __IOM uint32_t IFS;            /**< Interrupt Flag Set Register  */
685   __IOM uint32_t IFC;            /**< Interrupt Flag Clear Register  */
686   __IOM uint32_t IEN;            /**< Interrupt Enable Register  */
687 
688   uint32_t       RESERVED1[9U];  /**< Reserved for future use **/
689   __IOM uint32_t PPUCTRL;        /**< PPU Control Register  */
690   uint32_t       RESERVED2[3U];  /**< Reserved for future use **/
691   __IOM uint32_t PPUPATD0;       /**< PPU Privilege Access Type Descriptor 0  */
692   __IOM uint32_t PPUPATD1;       /**< PPU Privilege Access Type Descriptor 1  */
693   __IOM uint32_t PPUPATD2;       /**< PPU Privilege Access Type Descriptor 2  */
694 
695   uint32_t       RESERVED3[13U]; /**< Reserved for future use **/
696   __IM uint32_t  PPUFS;          /**< PPU Fault Status  */
697 } SMU_TypeDef;                   /** @} */
698 
699 #include "efm32gg12b_trng.h"
700 #include "efm32gg12b_dma_descriptor.h"
701 #include "efm32gg12b_devinfo.h"
702 #include "efm32gg12b_romtable.h"
703 
704 /** @} End of group EFM32GG12B310F1024GQ100_Peripheral_TypeDefs  */
705 
706 /***************************************************************************//**
707  * @defgroup EFM32GG12B310F1024GQ100_Peripheral_Base Peripheral Memory Map
708  * @{
709  ******************************************************************************/
710 
711 #define MSC_BASE          (0x40000000UL) /**< MSC base address  */
712 #define EMU_BASE          (0x400E3000UL) /**< EMU base address  */
713 #define RMU_BASE          (0x400E5000UL) /**< RMU base address  */
714 #define CMU_BASE          (0x400E4000UL) /**< CMU base address  */
715 #define CRYPTO0_BASE      (0x400F0000UL) /**< CRYPTO0 base address  */
716 #define LESENSE_BASE      (0x40055000UL) /**< LESENSE base address  */
717 #define EBI_BASE          (0x4000B000UL) /**< EBI base address  */
718 #define PDM_BASE          (0x40028000UL) /**< PDM base address  */
719 #define GPIO_BASE         (0x40088000UL) /**< GPIO base address  */
720 #define PRS_BASE          (0x400E6000UL) /**< PRS base address  */
721 #define LDMA_BASE         (0x40002000UL) /**< LDMA base address  */
722 #define FPUEH_BASE        (0x40001000UL) /**< FPUEH base address  */
723 #define GPCRC_BASE        (0x4001C000UL) /**< GPCRC base address  */
724 #define CAN0_BASE         (0x40004000UL) /**< CAN0 base address  */
725 #define CAN1_BASE         (0x40004400UL) /**< CAN1 base address  */
726 #define TIMER0_BASE       (0x40018000UL) /**< TIMER0 base address  */
727 #define TIMER1_BASE       (0x40018400UL) /**< TIMER1 base address  */
728 #define TIMER2_BASE       (0x40018800UL) /**< TIMER2 base address  */
729 #define TIMER3_BASE       (0x40018C00UL) /**< TIMER3 base address  */
730 #define WTIMER0_BASE      (0x4001A000UL) /**< WTIMER0 base address  */
731 #define WTIMER1_BASE      (0x4001A400UL) /**< WTIMER1 base address  */
732 #define USART0_BASE       (0x40010000UL) /**< USART0 base address  */
733 #define USART1_BASE       (0x40010400UL) /**< USART1 base address  */
734 #define USART2_BASE       (0x40010800UL) /**< USART2 base address  */
735 #define USART3_BASE       (0x40010C00UL) /**< USART3 base address  */
736 #define USART4_BASE       (0x40011000UL) /**< USART4 base address  */
737 #define UART0_BASE        (0x40014000UL) /**< UART0 base address  */
738 #define UART1_BASE        (0x40014400UL) /**< UART1 base address  */
739 #define LEUART0_BASE      (0x4006A000UL) /**< LEUART0 base address  */
740 #define LEUART1_BASE      (0x4006A400UL) /**< LEUART1 base address  */
741 #define LETIMER0_BASE     (0x40066000UL) /**< LETIMER0 base address  */
742 #define LETIMER1_BASE     (0x40066400UL) /**< LETIMER1 base address  */
743 #define CRYOTIMER_BASE    (0x4008F000UL) /**< CRYOTIMER base address  */
744 #define PCNT0_BASE        (0x4006E000UL) /**< PCNT0 base address  */
745 #define PCNT1_BASE        (0x4006E400UL) /**< PCNT1 base address  */
746 #define PCNT2_BASE        (0x4006E800UL) /**< PCNT2 base address  */
747 #define I2C0_BASE         (0x40089000UL) /**< I2C0 base address  */
748 #define I2C1_BASE         (0x40089400UL) /**< I2C1 base address  */
749 #define ADC0_BASE         (0x40082000UL) /**< ADC0 base address  */
750 #define ADC1_BASE         (0x40082400UL) /**< ADC1 base address  */
751 #define ACMP0_BASE        (0x40080000UL) /**< ACMP0 base address  */
752 #define ACMP1_BASE        (0x40080400UL) /**< ACMP1 base address  */
753 #define ACMP2_BASE        (0x40080800UL) /**< ACMP2 base address  */
754 #define VDAC0_BASE        (0x40086000UL) /**< VDAC0 base address  */
755 #define IDAC0_BASE        (0x40084000UL) /**< IDAC0 base address  */
756 #define CSEN_BASE         (0x4008E000UL) /**< CSEN base address  */
757 #define LCD_BASE          (0x40054000UL) /**< LCD base address  */
758 #define RTC_BASE          (0x40060000UL) /**< RTC base address  */
759 #define RTCC_BASE         (0x40062000UL) /**< RTCC base address  */
760 #define WDOG0_BASE        (0x40052000UL) /**< WDOG0 base address  */
761 #define WDOG1_BASE        (0x40052400UL) /**< WDOG1 base address  */
762 #define ETM_BASE          (0xE0041000UL) /**< ETM base address  */
763 #define SMU_BASE          (0x40020000UL) /**< SMU base address  */
764 #define TRNG0_BASE        (0x4001D000UL) /**< TRNG0 base address  */
765 #define DEVINFO_BASE      (0x0FE081B0UL) /**< DEVINFO base address */
766 #define ROMTABLE_BASE     (0xE00FFFD0UL) /**< ROMTABLE base address */
767 #define LOCKBITS_BASE     (0x0FE04000UL) /**< Lock-bits page base address */
768 #define USERDATA_BASE     (0x0FE00000UL) /**< User data page base address */
769 
770 /** @} End of group EFM32GG12B310F1024GQ100_Peripheral_Base */
771 
772 /***************************************************************************//**
773  * @defgroup EFM32GG12B310F1024GQ100_Peripheral_Declaration Peripheral Declarations
774  * @{
775  ******************************************************************************/
776 
777 #define MSC          ((MSC_TypeDef *) MSC_BASE)             /**< MSC base pointer */
778 #define EMU          ((EMU_TypeDef *) EMU_BASE)             /**< EMU base pointer */
779 #define RMU          ((RMU_TypeDef *) RMU_BASE)             /**< RMU base pointer */
780 #define CMU          ((CMU_TypeDef *) CMU_BASE)             /**< CMU base pointer */
781 #define CRYPTO0      ((CRYPTO_TypeDef *) CRYPTO0_BASE)      /**< CRYPTO0 base pointer */
782 #define LESENSE      ((LESENSE_TypeDef *) LESENSE_BASE)     /**< LESENSE base pointer */
783 #define EBI          ((EBI_TypeDef *) EBI_BASE)             /**< EBI base pointer */
784 #define PDM          ((PDM_TypeDef *) PDM_BASE)             /**< PDM base pointer */
785 #define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           /**< GPIO base pointer */
786 #define PRS          ((PRS_TypeDef *) PRS_BASE)             /**< PRS base pointer */
787 #define LDMA         ((LDMA_TypeDef *) LDMA_BASE)           /**< LDMA base pointer */
788 #define FPUEH        ((FPUEH_TypeDef *) FPUEH_BASE)         /**< FPUEH base pointer */
789 #define GPCRC        ((GPCRC_TypeDef *) GPCRC_BASE)         /**< GPCRC base pointer */
790 #define CAN0         ((CAN_TypeDef *) CAN0_BASE)            /**< CAN0 base pointer */
791 #define CAN1         ((CAN_TypeDef *) CAN1_BASE)            /**< CAN1 base pointer */
792 #define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        /**< TIMER0 base pointer */
793 #define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        /**< TIMER1 base pointer */
794 #define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)        /**< TIMER2 base pointer */
795 #define TIMER3       ((TIMER_TypeDef *) TIMER3_BASE)        /**< TIMER3 base pointer */
796 #define WTIMER0      ((TIMER_TypeDef *) WTIMER0_BASE)       /**< WTIMER0 base pointer */
797 #define WTIMER1      ((TIMER_TypeDef *) WTIMER1_BASE)       /**< WTIMER1 base pointer */
798 #define USART0       ((USART_TypeDef *) USART0_BASE)        /**< USART0 base pointer */
799 #define USART1       ((USART_TypeDef *) USART1_BASE)        /**< USART1 base pointer */
800 #define USART2       ((USART_TypeDef *) USART2_BASE)        /**< USART2 base pointer */
801 #define USART3       ((USART_TypeDef *) USART3_BASE)        /**< USART3 base pointer */
802 #define USART4       ((USART_TypeDef *) USART4_BASE)        /**< USART4 base pointer */
803 #define UART0        ((USART_TypeDef *) UART0_BASE)         /**< UART0 base pointer */
804 #define UART1        ((USART_TypeDef *) UART1_BASE)         /**< UART1 base pointer */
805 #define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      /**< LEUART0 base pointer */
806 #define LEUART1      ((LEUART_TypeDef *) LEUART1_BASE)      /**< LEUART1 base pointer */
807 #define LETIMER0     ((LETIMER_TypeDef *) LETIMER0_BASE)    /**< LETIMER0 base pointer */
808 #define LETIMER1     ((LETIMER_TypeDef *) LETIMER1_BASE)    /**< LETIMER1 base pointer */
809 #define CRYOTIMER    ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */
810 #define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          /**< PCNT0 base pointer */
811 #define PCNT1        ((PCNT_TypeDef *) PCNT1_BASE)          /**< PCNT1 base pointer */
812 #define PCNT2        ((PCNT_TypeDef *) PCNT2_BASE)          /**< PCNT2 base pointer */
813 #define I2C0         ((I2C_TypeDef *) I2C0_BASE)            /**< I2C0 base pointer */
814 #define I2C1         ((I2C_TypeDef *) I2C1_BASE)            /**< I2C1 base pointer */
815 #define ADC0         ((ADC_TypeDef *) ADC0_BASE)            /**< ADC0 base pointer */
816 #define ADC1         ((ADC_TypeDef *) ADC1_BASE)            /**< ADC1 base pointer */
817 #define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          /**< ACMP0 base pointer */
818 #define ACMP1        ((ACMP_TypeDef *) ACMP1_BASE)          /**< ACMP1 base pointer */
819 #define ACMP2        ((ACMP_TypeDef *) ACMP2_BASE)          /**< ACMP2 base pointer */
820 #define VDAC0        ((VDAC_TypeDef *) VDAC0_BASE)          /**< VDAC0 base pointer */
821 #define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          /**< IDAC0 base pointer */
822 #define CSEN         ((CSEN_TypeDef *) CSEN_BASE)           /**< CSEN base pointer */
823 #define LCD          ((LCD_TypeDef *) LCD_BASE)             /**< LCD base pointer */
824 #define RTC          ((RTC_TypeDef *) RTC_BASE)             /**< RTC base pointer */
825 #define RTCC         ((RTCC_TypeDef *) RTCC_BASE)           /**< RTCC base pointer */
826 #define WDOG0        ((WDOG_TypeDef *) WDOG0_BASE)          /**< WDOG0 base pointer */
827 #define WDOG1        ((WDOG_TypeDef *) WDOG1_BASE)          /**< WDOG1 base pointer */
828 #define ETM          ((ETM_TypeDef *) ETM_BASE)             /**< ETM base pointer */
829 #define SMU          ((SMU_TypeDef *) SMU_BASE)             /**< SMU base pointer */
830 #define TRNG0        ((TRNG_TypeDef *) TRNG0_BASE)          /**< TRNG0 base pointer */
831 #define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     /**< DEVINFO base pointer */
832 #define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   /**< ROMTABLE base pointer */
833 
834 /** @} End of group EFM32GG12B310F1024GQ100_Peripheral_Declaration */
835 
836 /***************************************************************************//**
837  * @defgroup EFM32GG12B310F1024GQ100_Peripheral_Offsets Peripheral Offsets
838  * @{
839  ******************************************************************************/
840 
841 #define CRYPTO_OFFSET     0x400 /**< Offset in bytes between CRYPTO instances */
842 #define CAN_OFFSET        0x400 /**< Offset in bytes between CAN instances */
843 #define TIMER_OFFSET      0x400 /**< Offset in bytes between TIMER instances */
844 #define WTIMER_OFFSET     0x400 /**< Offset in bytes between WTIMER instances */
845 #define USART_OFFSET      0x400 /**< Offset in bytes between USART instances */
846 #define UART_OFFSET       0x400 /**< Offset in bytes between UART instances */
847 #define LEUART_OFFSET     0x400 /**< Offset in bytes between LEUART instances */
848 #define LETIMER_OFFSET    0x400 /**< Offset in bytes between LETIMER instances */
849 #define PCNT_OFFSET       0x400 /**< Offset in bytes between PCNT instances */
850 #define I2C_OFFSET        0x400 /**< Offset in bytes between I2C instances */
851 #define ADC_OFFSET        0x400 /**< Offset in bytes between ADC instances */
852 #define ACMP_OFFSET       0x400 /**< Offset in bytes between ACMP instances */
853 #define VDAC_OFFSET       0x400 /**< Offset in bytes between VDAC instances */
854 #define IDAC_OFFSET       0x400 /**< Offset in bytes between IDAC instances */
855 #define WDOG_OFFSET       0x400 /**< Offset in bytes between WDOG instances */
856 #define TRNG_OFFSET       0x400 /**< Offset in bytes between TRNG instances */
857 
858 /** @} End of group EFM32GG12B310F1024GQ100_Peripheral_Offsets */
859 
860 /***************************************************************************//**
861  * @defgroup EFM32GG12B310F1024GQ100_BitFields Bit Fields
862  * @{
863  ******************************************************************************/
864 
865 /***************************************************************************//**
866  * @addtogroup EFM32GG12B310F1024GQ100_PRS
867  * @{
868  * @addtogroup EFM32GG12B310F1024GQ100_PRS_Signals PRS Signals
869  * @{
870  * @brief PRS Signal names
871  ******************************************************************************/
872 #define PRS_PRS_CH0                 ((1 << 8) + 0)   /**< PRS PRS channel 0 */
873 #define PRS_PRS_CH1                 ((1 << 8) + 1)   /**< PRS PRS channel 1 */
874 #define PRS_PRS_CH2                 ((1 << 8) + 2)   /**< PRS PRS channel 2 */
875 #define PRS_PRS_CH3                 ((1 << 8) + 3)   /**< PRS PRS channel 3 */
876 #define PRS_PRS_CH4                 ((1 << 8) + 4)   /**< PRS PRS channel 4 */
877 #define PRS_PRS_CH5                 ((1 << 8) + 5)   /**< PRS PRS channel 5 */
878 #define PRS_PRS_CH6                 ((1 << 8) + 6)   /**< PRS PRS channel 6 */
879 #define PRS_PRS_CH7                 ((1 << 8) + 7)   /**< PRS PRS channel 7 */
880 #define PRS_PRS_CH8                 ((2 << 8) + 0)   /**< PRS PRS channel 8 */
881 #define PRS_PRS_CH9                 ((2 << 8) + 1)   /**< PRS PRS channel 9 */
882 #define PRS_PRS_CH10                ((2 << 8) + 2)   /**< PRS PRS channel 10 */
883 #define PRS_PRS_CH11                ((2 << 8) + 3)   /**< PRS PRS channel 11 */
884 #define PRS_PRS_CH12                ((2 << 8) + 4)   /**< PRS PRS channel 12 */
885 #define PRS_PRS_CH13                ((2 << 8) + 5)   /**< PRS PRS channel 13 */
886 #define PRS_PRS_CH14                ((2 << 8) + 6)   /**< PRS PRS channel 14 */
887 #define PRS_PRS_CH15                ((2 << 8) + 7)   /**< PRS PRS channel 15 */
888 #define PRS_ACMP0_OUT               ((4 << 8) + 0)   /**< PRS Analog comparator output */
889 #define PRS_ACMP1_OUT               ((5 << 8) + 0)   /**< PRS Analog comparator output */
890 #define PRS_ADC0_SINGLE             ((6 << 8) + 0)   /**< PRS ADC single conversion done */
891 #define PRS_ADC0_SCAN               ((6 << 8) + 1)   /**< PRS ADC scan conversion done */
892 #define PRS_RTC_OF                  ((7 << 8) + 0)   /**< PRS RTC Overflow */
893 #define PRS_RTC_COMP0               ((7 << 8) + 1)   /**< PRS RTC Compare 0 */
894 #define PRS_RTC_COMP1               ((7 << 8) + 2)   /**< PRS RTC Compare 1 */
895 #define PRS_RTC_COMP2               ((7 << 8) + 3)   /**< PRS RTC Compare 2 */
896 #define PRS_RTC_COMP3               ((7 << 8) + 4)   /**< PRS RTC Compare 3 */
897 #define PRS_RTC_COMP4               ((7 << 8) + 5)   /**< PRS RTC Compare 4 */
898 #define PRS_RTC_COMP5               ((7 << 8) + 6)   /**< PRS RTC Compare 5 */
899 #define PRS_RTCC_CCV0               ((8 << 8) + 1)   /**< PRS RTCC Compare 0 */
900 #define PRS_RTCC_CCV1               ((8 << 8) + 2)   /**< PRS RTCC Compare 1 */
901 #define PRS_RTCC_CCV2               ((8 << 8) + 3)   /**< PRS RTCC Compare 2 */
902 #define PRS_GPIO_PIN0               ((9 << 8) + 0)   /**< PRS GPIO pin 0 */
903 #define PRS_GPIO_PIN1               ((9 << 8) + 1)   /**< PRS GPIO pin 1 */
904 #define PRS_GPIO_PIN2               ((9 << 8) + 2)   /**< PRS GPIO pin 2 */
905 #define PRS_GPIO_PIN3               ((9 << 8) + 3)   /**< PRS GPIO pin 3 */
906 #define PRS_GPIO_PIN4               ((9 << 8) + 4)   /**< PRS GPIO pin 4 */
907 #define PRS_GPIO_PIN5               ((9 << 8) + 5)   /**< PRS GPIO pin 5 */
908 #define PRS_GPIO_PIN6               ((9 << 8) + 6)   /**< PRS GPIO pin 6 */
909 #define PRS_GPIO_PIN7               ((9 << 8) + 7)   /**< PRS GPIO pin 7 */
910 #define PRS_GPIO_PIN8               ((10 << 8) + 0)  /**< PRS GPIO pin 8 */
911 #define PRS_GPIO_PIN9               ((10 << 8) + 1)  /**< PRS GPIO pin 9 */
912 #define PRS_GPIO_PIN10              ((10 << 8) + 2)  /**< PRS GPIO pin 10 */
913 #define PRS_GPIO_PIN11              ((10 << 8) + 3)  /**< PRS GPIO pin 11 */
914 #define PRS_GPIO_PIN12              ((10 << 8) + 4)  /**< PRS GPIO pin 12 */
915 #define PRS_GPIO_PIN13              ((10 << 8) + 5)  /**< PRS GPIO pin 13 */
916 #define PRS_GPIO_PIN14              ((10 << 8) + 6)  /**< PRS GPIO pin 14 */
917 #define PRS_GPIO_PIN15              ((10 << 8) + 7)  /**< PRS GPIO pin 15 */
918 #define PRS_LETIMER0_CH0            ((11 << 8) + 0)  /**< PRS LETIMER CH0 Out */
919 #define PRS_LETIMER0_CH1            ((11 << 8) + 1)  /**< PRS LETIMER CH1 Out */
920 #define PRS_LETIMER1_CH0            ((12 << 8) + 0)  /**< PRS LETIMER CH0 Out */
921 #define PRS_LETIMER1_CH1            ((12 << 8) + 1)  /**< PRS LETIMER CH1 Out */
922 #define PRS_PCNT0_TCC               ((13 << 8) + 0)  /**< PRS Triggered compare match */
923 #define PRS_PCNT0_UFOF              ((13 << 8) + 1)  /**< PRS Counter overflow or underflow */
924 #define PRS_PCNT0_DIR               ((13 << 8) + 2)  /**< PRS Counter direction */
925 #define PRS_PCNT1_TCC               ((14 << 8) + 0)  /**< PRS Triggered compare match */
926 #define PRS_PCNT1_UFOF              ((14 << 8) + 1)  /**< PRS Counter overflow or underflow */
927 #define PRS_PCNT1_DIR               ((14 << 8) + 2)  /**< PRS Counter direction */
928 #define PRS_PCNT2_TCC               ((15 << 8) + 0)  /**< PRS Triggered compare match */
929 #define PRS_PCNT2_UFOF              ((15 << 8) + 1)  /**< PRS Counter overflow or underflow */
930 #define PRS_PCNT2_DIR               ((15 << 8) + 2)  /**< PRS Counter direction */
931 #define PRS_CRYOTIMER_PERIOD        ((16 << 8) + 0)  /**< PRS CRYOTIMER Output */
932 #define PRS_CMU_CLKOUT0             ((17 << 8) + 0)  /**< PRS Clock Output 0 */
933 #define PRS_CMU_CLKOUT1             ((17 << 8) + 1)  /**< PRS Clock Output 1 */
934 #define PRS_CMU_CLKOUT2             ((17 << 8) + 7)  /**< PRS Clock Output 2 */
935 #define PRS_VDAC0_CH0               ((23 << 8) + 0)  /**< PRS DAC ch0 conversion done */
936 #define PRS_VDAC0_CH1               ((23 << 8) + 1)  /**< PRS DAC ch1 conversion done */
937 #define PRS_VDAC0_OPA0              ((23 << 8) + 2)  /**< PRS OPA0 warmed up. output is valid. */
938 #define PRS_VDAC0_OPA1              ((23 << 8) + 3)  /**< PRS OPA1 warmed up. output is valid. */
939 #define PRS_VDAC0_OPA2              ((23 << 8) + 4)  /**< PRS OPA2 warmed up. output is valid. */
940 #define PRS_VDAC0_OPA3              ((23 << 8) + 5)  /**< PRS OPA3 warmed up. output is valid. */
941 #define PRS_LESENSE_SCANRES0        ((24 << 8) + 0)  /**< PRS LESENSE SCANRES register, bit 0 */
942 #define PRS_LESENSE_SCANRES1        ((24 << 8) + 1)  /**< PRS LESENSE SCANRES register, bit 1 */
943 #define PRS_LESENSE_SCANRES2        ((24 << 8) + 2)  /**< PRS LESENSE SCANRES register, bit 2 */
944 #define PRS_LESENSE_SCANRES3        ((24 << 8) + 3)  /**< PRS LESENSE SCANRES register, bit 3 */
945 #define PRS_LESENSE_SCANRES4        ((24 << 8) + 4)  /**< PRS LESENSE SCANRES register, bit 4 */
946 #define PRS_LESENSE_SCANRES5        ((24 << 8) + 5)  /**< PRS LESENSE SCANRES register, bit 5 */
947 #define PRS_LESENSE_SCANRES6        ((24 << 8) + 6)  /**< PRS LESENSE SCANRES register, bit 6 */
948 #define PRS_LESENSE_SCANRES7        ((24 << 8) + 7)  /**< PRS LESENSE SCANRES register, bit 7 */
949 #define PRS_LESENSE_SCANRES8        ((25 << 8) + 0)  /**< PRS LESENSE SCANRES register, bit 8 */
950 #define PRS_LESENSE_SCANRES9        ((25 << 8) + 1)  /**< PRS LESENSE SCANRES register, bit 9 */
951 #define PRS_LESENSE_SCANRES10       ((25 << 8) + 2)  /**< PRS LESENSE SCANRES register, bit 10 */
952 #define PRS_LESENSE_SCANRES11       ((25 << 8) + 3)  /**< PRS LESENSE SCANRES register, bit 11 */
953 #define PRS_LESENSE_SCANRES12       ((25 << 8) + 4)  /**< PRS LESENSE SCANRES register, bit 12 */
954 #define PRS_LESENSE_SCANRES13       ((25 << 8) + 5)  /**< PRS LESENSE SCANRES register, bit 13 */
955 #define PRS_LESENSE_SCANRES14       ((25 << 8) + 6)  /**< PRS LESENSE SCANRES register, bit 14 */
956 #define PRS_LESENSE_SCANRES15       ((25 << 8) + 7)  /**< PRS LESENSE SCANRES register, bit 15 */
957 #define PRS_LESENSE_DEC0            ((26 << 8) + 0)  /**< PRS LESENSE Decoder PRS out 0 */
958 #define PRS_LESENSE_DEC1            ((26 << 8) + 1)  /**< PRS LESENSE Decoder PRS out 1 */
959 #define PRS_LESENSE_DEC2            ((26 << 8) + 2)  /**< PRS LESENSE Decoder PRS out 2 */
960 #define PRS_LESENSE_DECCMP          ((26 << 8) + 3)  /**< PRS LESENSE Decoder PRS compare value match channel */
961 #define PRS_LESENSE_MEASACT         ((27 << 8) + 0)  /**< PRS LESENSE Measurement active */
962 #define PRS_ACMP2_OUT               ((28 << 8) + 0)  /**< PRS Analog comparator output */
963 #define PRS_ADC1_SINGLE             ((29 << 8) + 0)  /**< PRS ADC single conversion done */
964 #define PRS_ADC1_SCAN               ((29 << 8) + 1)  /**< PRS ADC scan conversion done */
965 #define PRS_USART0_IRTX             ((48 << 8) + 0)  /**< PRS  */
966 #define PRS_USART0_TXC              ((48 << 8) + 1)  /**< PRS  */
967 #define PRS_USART0_RXDATAV          ((48 << 8) + 2)  /**< PRS  */
968 #define PRS_USART0_RTS              ((48 << 8) + 3)  /**< PRS  */
969 #define PRS_USART0_TX               ((48 << 8) + 5)  /**< PRS  */
970 #define PRS_USART0_CS               ((48 << 8) + 6)  /**< PRS  */
971 #define PRS_USART1_TXC              ((49 << 8) + 1)  /**< PRS  */
972 #define PRS_USART1_RXDATAV          ((49 << 8) + 2)  /**< PRS  */
973 #define PRS_USART1_RTS              ((49 << 8) + 3)  /**< PRS  */
974 #define PRS_USART1_TX               ((49 << 8) + 5)  /**< PRS  */
975 #define PRS_USART1_CS               ((49 << 8) + 6)  /**< PRS  */
976 #define PRS_USART2_IRTX             ((50 << 8) + 0)  /**< PRS USART 2 IRDA out */
977 #define PRS_USART2_TXC              ((50 << 8) + 1)  /**< PRS  */
978 #define PRS_USART2_RXDATAV          ((50 << 8) + 2)  /**< PRS  */
979 #define PRS_USART2_RTS              ((50 << 8) + 3)  /**< PRS  */
980 #define PRS_USART2_TX               ((50 << 8) + 5)  /**< PRS  */
981 #define PRS_USART2_CS               ((50 << 8) + 6)  /**< PRS  */
982 #define PRS_USART3_TXC              ((51 << 8) + 1)  /**< PRS  */
983 #define PRS_USART3_RXDATAV          ((51 << 8) + 2)  /**< PRS  */
984 #define PRS_USART3_RTS              ((51 << 8) + 3)  /**< PRS  */
985 #define PRS_USART3_TX               ((51 << 8) + 5)  /**< PRS  */
986 #define PRS_USART3_CS               ((51 << 8) + 6)  /**< PRS  */
987 #define PRS_USART4_TXC              ((52 << 8) + 1)  /**< PRS  */
988 #define PRS_USART4_RXDATAV          ((52 << 8) + 2)  /**< PRS  */
989 #define PRS_USART4_RTS              ((52 << 8) + 3)  /**< PRS  */
990 #define PRS_USART4_TX               ((52 << 8) + 5)  /**< PRS  */
991 #define PRS_USART4_CS               ((52 << 8) + 6)  /**< PRS  */
992 #define PRS_UART0_TXC               ((54 << 8) + 1)  /**< PRS  */
993 #define PRS_UART0_RXDATAV           ((54 << 8) + 2)  /**< PRS  */
994 #define PRS_UART0_RTS               ((54 << 8) + 3)  /**< PRS  */
995 #define PRS_UART0_TX                ((54 << 8) + 5)  /**< PRS  */
996 #define PRS_UART0_CS                ((54 << 8) + 6)  /**< PRS  */
997 #define PRS_UART1_TXC               ((55 << 8) + 1)  /**< PRS  */
998 #define PRS_UART1_RXDATAV           ((55 << 8) + 2)  /**< PRS  */
999 #define PRS_UART1_RTS               ((55 << 8) + 3)  /**< PRS  */
1000 #define PRS_UART1_TX                ((55 << 8) + 5)  /**< PRS  */
1001 #define PRS_UART1_CS                ((55 << 8) + 6)  /**< PRS  */
1002 #define PRS_TIMER0_UF               ((60 << 8) + 0)  /**< PRS  */
1003 #define PRS_TIMER0_OF               ((60 << 8) + 1)  /**< PRS  */
1004 #define PRS_TIMER0_CC0              ((60 << 8) + 2)  /**< PRS  */
1005 #define PRS_TIMER0_CC1              ((60 << 8) + 3)  /**< PRS  */
1006 #define PRS_TIMER0_CC2              ((60 << 8) + 4)  /**< PRS  */
1007 #define PRS_TIMER1_UF               ((61 << 8) + 0)  /**< PRS  */
1008 #define PRS_TIMER1_OF               ((61 << 8) + 1)  /**< PRS  */
1009 #define PRS_TIMER1_CC0              ((61 << 8) + 2)  /**< PRS  */
1010 #define PRS_TIMER1_CC1              ((61 << 8) + 3)  /**< PRS  */
1011 #define PRS_TIMER1_CC2              ((61 << 8) + 4)  /**< PRS  */
1012 #define PRS_TIMER1_CC3              ((61 << 8) + 5)  /**< PRS  */
1013 #define PRS_TIMER2_UF               ((62 << 8) + 0)  /**< PRS  */
1014 #define PRS_TIMER2_OF               ((62 << 8) + 1)  /**< PRS  */
1015 #define PRS_TIMER2_CC0              ((62 << 8) + 2)  /**< PRS  */
1016 #define PRS_TIMER2_CC1              ((62 << 8) + 3)  /**< PRS  */
1017 #define PRS_TIMER2_CC2              ((62 << 8) + 4)  /**< PRS  */
1018 #define PRS_CM4_TXEV                ((67 << 8) + 0)  /**< PRS  */
1019 #define PRS_CM4_ICACHEPCHITSOF      ((67 << 8) + 1)  /**< PRS  */
1020 #define PRS_CM4_ICACHEPCMISSESOF    ((67 << 8) + 2)  /**< PRS  */
1021 #define PRS_TIMER3_UF               ((80 << 8) + 0)  /**< PRS  */
1022 #define PRS_TIMER3_OF               ((80 << 8) + 1)  /**< PRS  */
1023 #define PRS_TIMER3_CC0              ((80 << 8) + 2)  /**< PRS  */
1024 #define PRS_TIMER3_CC1              ((80 << 8) + 3)  /**< PRS  */
1025 #define PRS_TIMER3_CC2              ((80 << 8) + 4)  /**< PRS  */
1026 #define PRS_WTIMER0_UF              ((82 << 8) + 0)  /**< PRS  */
1027 #define PRS_WTIMER0_OF              ((82 << 8) + 1)  /**< PRS  */
1028 #define PRS_WTIMER0_CC0             ((82 << 8) + 2)  /**< PRS  */
1029 #define PRS_WTIMER0_CC1             ((82 << 8) + 3)  /**< PRS  */
1030 #define PRS_WTIMER0_CC2             ((82 << 8) + 4)  /**< PRS  */
1031 #define PRS_WTIMER1_UF              ((83 << 8) + 0)  /**< PRS  */
1032 #define PRS_WTIMER1_OF              ((83 << 8) + 1)  /**< PRS  */
1033 #define PRS_WTIMER1_CC0             ((83 << 8) + 2)  /**< PRS  */
1034 #define PRS_WTIMER1_CC1             ((83 << 8) + 3)  /**< PRS  */
1035 #define PRS_WTIMER1_CC2             ((83 << 8) + 4)  /**< PRS  */
1036 #define PRS_WTIMER1_CC3             ((83 << 8) + 5)  /**< PRS  */
1037 #define PRS_PDM_DSRPULSE            ((121 << 8) + 0) /**< PRS PDM DSR pulse */
1038 
1039 /** @} */
1040 /** @} End of group EFM32GG12B310F1024GQ100_PRS */
1041 
1042 #include "efm32gg12b_dmareq.h"
1043 
1044 /***************************************************************************//**
1045  * @addtogroup EFM32GG12B310F1024GQ100_WTIMER
1046  * @{
1047  * @defgroup EFM32GG12B310F1024GQ100_WTIMER_BitFields  WTIMER Bit Fields
1048  * @{
1049  ******************************************************************************/
1050 
1051 /* Bit fields for WTIMER CTRL */
1052 #define _WTIMER_CTRL_RESETVALUE                     0x00000000UL                              /**< Default value for WTIMER_CTRL */
1053 #define _WTIMER_CTRL_MASK                           0x3F036FFBUL                              /**< Mask for WTIMER_CTRL */
1054 #define _WTIMER_CTRL_MODE_SHIFT                     0                                         /**< Shift value for TIMER_MODE */
1055 #define _WTIMER_CTRL_MODE_MASK                      0x3UL                                     /**< Bit mask for TIMER_MODE */
1056 #define _WTIMER_CTRL_MODE_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
1057 #define _WTIMER_CTRL_MODE_UP                        0x00000000UL                              /**< Mode UP for WTIMER_CTRL */
1058 #define _WTIMER_CTRL_MODE_DOWN                      0x00000001UL                              /**< Mode DOWN for WTIMER_CTRL */
1059 #define _WTIMER_CTRL_MODE_UPDOWN                    0x00000002UL                              /**< Mode UPDOWN for WTIMER_CTRL */
1060 #define _WTIMER_CTRL_MODE_QDEC                      0x00000003UL                              /**< Mode QDEC for WTIMER_CTRL */
1061 #define WTIMER_CTRL_MODE_DEFAULT                    (_WTIMER_CTRL_MODE_DEFAULT << 0)          /**< Shifted mode DEFAULT for WTIMER_CTRL */
1062 #define WTIMER_CTRL_MODE_UP                         (_WTIMER_CTRL_MODE_UP << 0)               /**< Shifted mode UP for WTIMER_CTRL */
1063 #define WTIMER_CTRL_MODE_DOWN                       (_WTIMER_CTRL_MODE_DOWN << 0)             /**< Shifted mode DOWN for WTIMER_CTRL */
1064 #define WTIMER_CTRL_MODE_UPDOWN                     (_WTIMER_CTRL_MODE_UPDOWN << 0)           /**< Shifted mode UPDOWN for WTIMER_CTRL */
1065 #define WTIMER_CTRL_MODE_QDEC                       (_WTIMER_CTRL_MODE_QDEC << 0)             /**< Shifted mode QDEC for WTIMER_CTRL */
1066 #define WTIMER_CTRL_SYNC                            (0x1UL << 3)                              /**< Timer Start/Stop/Reload Synchronization */
1067 #define _WTIMER_CTRL_SYNC_SHIFT                     3                                         /**< Shift value for TIMER_SYNC */
1068 #define _WTIMER_CTRL_SYNC_MASK                      0x8UL                                     /**< Bit mask for TIMER_SYNC */
1069 #define _WTIMER_CTRL_SYNC_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
1070 #define WTIMER_CTRL_SYNC_DEFAULT                    (_WTIMER_CTRL_SYNC_DEFAULT << 3)          /**< Shifted mode DEFAULT for WTIMER_CTRL */
1071 #define WTIMER_CTRL_OSMEN                           (0x1UL << 4)                              /**< One-shot Mode Enable */
1072 #define _WTIMER_CTRL_OSMEN_SHIFT                    4                                         /**< Shift value for TIMER_OSMEN */
1073 #define _WTIMER_CTRL_OSMEN_MASK                     0x10UL                                    /**< Bit mask for TIMER_OSMEN */
1074 #define _WTIMER_CTRL_OSMEN_DEFAULT                  0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
1075 #define WTIMER_CTRL_OSMEN_DEFAULT                   (_WTIMER_CTRL_OSMEN_DEFAULT << 4)         /**< Shifted mode DEFAULT for WTIMER_CTRL */
1076 #define WTIMER_CTRL_QDM                             (0x1UL << 5)                              /**< Quadrature Decoder Mode Selection */
1077 #define _WTIMER_CTRL_QDM_SHIFT                      5                                         /**< Shift value for TIMER_QDM */
1078 #define _WTIMER_CTRL_QDM_MASK                       0x20UL                                    /**< Bit mask for TIMER_QDM */
1079 #define _WTIMER_CTRL_QDM_DEFAULT                    0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
1080 #define _WTIMER_CTRL_QDM_X2                         0x00000000UL                              /**< Mode X2 for WTIMER_CTRL */
1081 #define _WTIMER_CTRL_QDM_X4                         0x00000001UL                              /**< Mode X4 for WTIMER_CTRL */
1082 #define WTIMER_CTRL_QDM_DEFAULT                     (_WTIMER_CTRL_QDM_DEFAULT << 5)           /**< Shifted mode DEFAULT for WTIMER_CTRL */
1083 #define WTIMER_CTRL_QDM_X2                          (_WTIMER_CTRL_QDM_X2 << 5)                /**< Shifted mode X2 for WTIMER_CTRL */
1084 #define WTIMER_CTRL_QDM_X4                          (_WTIMER_CTRL_QDM_X4 << 5)                /**< Shifted mode X4 for WTIMER_CTRL */
1085 #define WTIMER_CTRL_DEBUGRUN                        (0x1UL << 6)                              /**< Debug Mode Run Enable */
1086 #define _WTIMER_CTRL_DEBUGRUN_SHIFT                 6                                         /**< Shift value for TIMER_DEBUGRUN */
1087 #define _WTIMER_CTRL_DEBUGRUN_MASK                  0x40UL                                    /**< Bit mask for TIMER_DEBUGRUN */
1088 #define _WTIMER_CTRL_DEBUGRUN_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
1089 #define WTIMER_CTRL_DEBUGRUN_DEFAULT                (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6)      /**< Shifted mode DEFAULT for WTIMER_CTRL */
1090 #define WTIMER_CTRL_DMACLRACT                       (0x1UL << 7)                              /**< DMA Request Clear on Active */
1091 #define _WTIMER_CTRL_DMACLRACT_SHIFT                7                                         /**< Shift value for TIMER_DMACLRACT */
1092 #define _WTIMER_CTRL_DMACLRACT_MASK                 0x80UL                                    /**< Bit mask for TIMER_DMACLRACT */
1093 #define _WTIMER_CTRL_DMACLRACT_DEFAULT              0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
1094 #define WTIMER_CTRL_DMACLRACT_DEFAULT               (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7)     /**< Shifted mode DEFAULT for WTIMER_CTRL */
1095 #define _WTIMER_CTRL_RISEA_SHIFT                    8                                         /**< Shift value for TIMER_RISEA */
1096 #define _WTIMER_CTRL_RISEA_MASK                     0x300UL                                   /**< Bit mask for TIMER_RISEA */
1097 #define _WTIMER_CTRL_RISEA_DEFAULT                  0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
1098 #define _WTIMER_CTRL_RISEA_NONE                     0x00000000UL                              /**< Mode NONE for WTIMER_CTRL */
1099 #define _WTIMER_CTRL_RISEA_START                    0x00000001UL                              /**< Mode START for WTIMER_CTRL */
1100 #define _WTIMER_CTRL_RISEA_STOP                     0x00000002UL                              /**< Mode STOP for WTIMER_CTRL */
1101 #define _WTIMER_CTRL_RISEA_RELOADSTART              0x00000003UL                              /**< Mode RELOADSTART for WTIMER_CTRL */
1102 #define WTIMER_CTRL_RISEA_DEFAULT                   (_WTIMER_CTRL_RISEA_DEFAULT << 8)         /**< Shifted mode DEFAULT for WTIMER_CTRL */
1103 #define WTIMER_CTRL_RISEA_NONE                      (_WTIMER_CTRL_RISEA_NONE << 8)            /**< Shifted mode NONE for WTIMER_CTRL */
1104 #define WTIMER_CTRL_RISEA_START                     (_WTIMER_CTRL_RISEA_START << 8)           /**< Shifted mode START for WTIMER_CTRL */
1105 #define WTIMER_CTRL_RISEA_STOP                      (_WTIMER_CTRL_RISEA_STOP << 8)            /**< Shifted mode STOP for WTIMER_CTRL */
1106 #define WTIMER_CTRL_RISEA_RELOADSTART               (_WTIMER_CTRL_RISEA_RELOADSTART << 8)     /**< Shifted mode RELOADSTART for WTIMER_CTRL */
1107 #define _WTIMER_CTRL_FALLA_SHIFT                    10                                        /**< Shift value for TIMER_FALLA */
1108 #define _WTIMER_CTRL_FALLA_MASK                     0xC00UL                                   /**< Bit mask for TIMER_FALLA */
1109 #define _WTIMER_CTRL_FALLA_DEFAULT                  0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
1110 #define _WTIMER_CTRL_FALLA_NONE                     0x00000000UL                              /**< Mode NONE for WTIMER_CTRL */
1111 #define _WTIMER_CTRL_FALLA_START                    0x00000001UL                              /**< Mode START for WTIMER_CTRL */
1112 #define _WTIMER_CTRL_FALLA_STOP                     0x00000002UL                              /**< Mode STOP for WTIMER_CTRL */
1113 #define _WTIMER_CTRL_FALLA_RELOADSTART              0x00000003UL                              /**< Mode RELOADSTART for WTIMER_CTRL */
1114 #define WTIMER_CTRL_FALLA_DEFAULT                   (_WTIMER_CTRL_FALLA_DEFAULT << 10)        /**< Shifted mode DEFAULT for WTIMER_CTRL */
1115 #define WTIMER_CTRL_FALLA_NONE                      (_WTIMER_CTRL_FALLA_NONE << 10)           /**< Shifted mode NONE for WTIMER_CTRL */
1116 #define WTIMER_CTRL_FALLA_START                     (_WTIMER_CTRL_FALLA_START << 10)          /**< Shifted mode START for WTIMER_CTRL */
1117 #define WTIMER_CTRL_FALLA_STOP                      (_WTIMER_CTRL_FALLA_STOP << 10)           /**< Shifted mode STOP for WTIMER_CTRL */
1118 #define WTIMER_CTRL_FALLA_RELOADSTART               (_WTIMER_CTRL_FALLA_RELOADSTART << 10)    /**< Shifted mode RELOADSTART for WTIMER_CTRL */
1119 #define WTIMER_CTRL_X2CNT                           (0x1UL << 13)                             /**< 2x Count Mode */
1120 #define _WTIMER_CTRL_X2CNT_SHIFT                    13                                        /**< Shift value for TIMER_X2CNT */
1121 #define _WTIMER_CTRL_X2CNT_MASK                     0x2000UL                                  /**< Bit mask for TIMER_X2CNT */
1122 #define _WTIMER_CTRL_X2CNT_DEFAULT                  0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
1123 #define WTIMER_CTRL_X2CNT_DEFAULT                   (_WTIMER_CTRL_X2CNT_DEFAULT << 13)        /**< Shifted mode DEFAULT for WTIMER_CTRL */
1124 #define WTIMER_CTRL_DISSYNCOUT                      (0x1UL << 14)                             /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */
1125 #define _WTIMER_CTRL_DISSYNCOUT_SHIFT               14                                        /**< Shift value for TIMER_DISSYNCOUT */
1126 #define _WTIMER_CTRL_DISSYNCOUT_MASK                0x4000UL                                  /**< Bit mask for TIMER_DISSYNCOUT */
1127 #define _WTIMER_CTRL_DISSYNCOUT_DEFAULT             0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
1128 #define WTIMER_CTRL_DISSYNCOUT_DEFAULT              (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14)   /**< Shifted mode DEFAULT for WTIMER_CTRL */
1129 #define _WTIMER_CTRL_CLKSEL_SHIFT                   16                                        /**< Shift value for TIMER_CLKSEL */
1130 #define _WTIMER_CTRL_CLKSEL_MASK                    0x30000UL                                 /**< Bit mask for TIMER_CLKSEL */
1131 #define _WTIMER_CTRL_CLKSEL_DEFAULT                 0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
1132 #define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK           0x00000000UL                              /**< Mode PRESCHFPERCLK for WTIMER_CTRL */
1133 #define _WTIMER_CTRL_CLKSEL_CC1                     0x00000001UL                              /**< Mode CC1 for WTIMER_CTRL */
1134 #define _WTIMER_CTRL_CLKSEL_TIMEROUF                0x00000002UL                              /**< Mode TIMEROUF for WTIMER_CTRL */
1135 #define WTIMER_CTRL_CLKSEL_DEFAULT                  (_WTIMER_CTRL_CLKSEL_DEFAULT << 16)       /**< Shifted mode DEFAULT for WTIMER_CTRL */
1136 #define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK            (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */
1137 #define WTIMER_CTRL_CLKSEL_CC1                      (_WTIMER_CTRL_CLKSEL_CC1 << 16)           /**< Shifted mode CC1 for WTIMER_CTRL */
1138 #define WTIMER_CTRL_CLKSEL_TIMEROUF                 (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16)      /**< Shifted mode TIMEROUF for WTIMER_CTRL */
1139 #define _WTIMER_CTRL_PRESC_SHIFT                    24                                        /**< Shift value for TIMER_PRESC */
1140 #define _WTIMER_CTRL_PRESC_MASK                     0xF000000UL                               /**< Bit mask for TIMER_PRESC */
1141 #define _WTIMER_CTRL_PRESC_DEFAULT                  0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
1142 #define _WTIMER_CTRL_PRESC_DIV1                     0x00000000UL                              /**< Mode DIV1 for WTIMER_CTRL */
1143 #define _WTIMER_CTRL_PRESC_DIV2                     0x00000001UL                              /**< Mode DIV2 for WTIMER_CTRL */
1144 #define _WTIMER_CTRL_PRESC_DIV4                     0x00000002UL                              /**< Mode DIV4 for WTIMER_CTRL */
1145 #define _WTIMER_CTRL_PRESC_DIV8                     0x00000003UL                              /**< Mode DIV8 for WTIMER_CTRL */
1146 #define _WTIMER_CTRL_PRESC_DIV16                    0x00000004UL                              /**< Mode DIV16 for WTIMER_CTRL */
1147 #define _WTIMER_CTRL_PRESC_DIV32                    0x00000005UL                              /**< Mode DIV32 for WTIMER_CTRL */
1148 #define _WTIMER_CTRL_PRESC_DIV64                    0x00000006UL                              /**< Mode DIV64 for WTIMER_CTRL */
1149 #define _WTIMER_CTRL_PRESC_DIV128                   0x00000007UL                              /**< Mode DIV128 for WTIMER_CTRL */
1150 #define _WTIMER_CTRL_PRESC_DIV256                   0x00000008UL                              /**< Mode DIV256 for WTIMER_CTRL */
1151 #define _WTIMER_CTRL_PRESC_DIV512                   0x00000009UL                              /**< Mode DIV512 for WTIMER_CTRL */
1152 #define _WTIMER_CTRL_PRESC_DIV1024                  0x0000000AUL                              /**< Mode DIV1024 for WTIMER_CTRL */
1153 #define WTIMER_CTRL_PRESC_DEFAULT                   (_WTIMER_CTRL_PRESC_DEFAULT << 24)        /**< Shifted mode DEFAULT for WTIMER_CTRL */
1154 #define WTIMER_CTRL_PRESC_DIV1                      (_WTIMER_CTRL_PRESC_DIV1 << 24)           /**< Shifted mode DIV1 for WTIMER_CTRL */
1155 #define WTIMER_CTRL_PRESC_DIV2                      (_WTIMER_CTRL_PRESC_DIV2 << 24)           /**< Shifted mode DIV2 for WTIMER_CTRL */
1156 #define WTIMER_CTRL_PRESC_DIV4                      (_WTIMER_CTRL_PRESC_DIV4 << 24)           /**< Shifted mode DIV4 for WTIMER_CTRL */
1157 #define WTIMER_CTRL_PRESC_DIV8                      (_WTIMER_CTRL_PRESC_DIV8 << 24)           /**< Shifted mode DIV8 for WTIMER_CTRL */
1158 #define WTIMER_CTRL_PRESC_DIV16                     (_WTIMER_CTRL_PRESC_DIV16 << 24)          /**< Shifted mode DIV16 for WTIMER_CTRL */
1159 #define WTIMER_CTRL_PRESC_DIV32                     (_WTIMER_CTRL_PRESC_DIV32 << 24)          /**< Shifted mode DIV32 for WTIMER_CTRL */
1160 #define WTIMER_CTRL_PRESC_DIV64                     (_WTIMER_CTRL_PRESC_DIV64 << 24)          /**< Shifted mode DIV64 for WTIMER_CTRL */
1161 #define WTIMER_CTRL_PRESC_DIV128                    (_WTIMER_CTRL_PRESC_DIV128 << 24)         /**< Shifted mode DIV128 for WTIMER_CTRL */
1162 #define WTIMER_CTRL_PRESC_DIV256                    (_WTIMER_CTRL_PRESC_DIV256 << 24)         /**< Shifted mode DIV256 for WTIMER_CTRL */
1163 #define WTIMER_CTRL_PRESC_DIV512                    (_WTIMER_CTRL_PRESC_DIV512 << 24)         /**< Shifted mode DIV512 for WTIMER_CTRL */
1164 #define WTIMER_CTRL_PRESC_DIV1024                   (_WTIMER_CTRL_PRESC_DIV1024 << 24)        /**< Shifted mode DIV1024 for WTIMER_CTRL */
1165 #define WTIMER_CTRL_ATI                             (0x1UL << 28)                             /**< Always Track Inputs */
1166 #define _WTIMER_CTRL_ATI_SHIFT                      28                                        /**< Shift value for TIMER_ATI */
1167 #define _WTIMER_CTRL_ATI_MASK                       0x10000000UL                              /**< Bit mask for TIMER_ATI */
1168 #define _WTIMER_CTRL_ATI_DEFAULT                    0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
1169 #define WTIMER_CTRL_ATI_DEFAULT                     (_WTIMER_CTRL_ATI_DEFAULT << 28)          /**< Shifted mode DEFAULT for WTIMER_CTRL */
1170 #define WTIMER_CTRL_RSSCOIST                        (0x1UL << 29)                             /**< Reload-Start Sets Compare Output Initial State */
1171 #define _WTIMER_CTRL_RSSCOIST_SHIFT                 29                                        /**< Shift value for TIMER_RSSCOIST */
1172 #define _WTIMER_CTRL_RSSCOIST_MASK                  0x20000000UL                              /**< Bit mask for TIMER_RSSCOIST */
1173 #define _WTIMER_CTRL_RSSCOIST_DEFAULT               0x00000000UL                              /**< Mode DEFAULT for WTIMER_CTRL */
1174 #define WTIMER_CTRL_RSSCOIST_DEFAULT                (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29)     /**< Shifted mode DEFAULT for WTIMER_CTRL */
1175 
1176 /* Bit fields for WTIMER CMD */
1177 #define _WTIMER_CMD_RESETVALUE                      0x00000000UL                     /**< Default value for WTIMER_CMD */
1178 #define _WTIMER_CMD_MASK                            0x00000003UL                     /**< Mask for WTIMER_CMD */
1179 #define WTIMER_CMD_START                            (0x1UL << 0)                     /**< Start Timer */
1180 #define _WTIMER_CMD_START_SHIFT                     0                                /**< Shift value for TIMER_START */
1181 #define _WTIMER_CMD_START_MASK                      0x1UL                            /**< Bit mask for TIMER_START */
1182 #define _WTIMER_CMD_START_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for WTIMER_CMD */
1183 #define WTIMER_CMD_START_DEFAULT                    (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */
1184 #define WTIMER_CMD_STOP                             (0x1UL << 1)                     /**< Stop Timer */
1185 #define _WTIMER_CMD_STOP_SHIFT                      1                                /**< Shift value for TIMER_STOP */
1186 #define _WTIMER_CMD_STOP_MASK                       0x2UL                            /**< Bit mask for TIMER_STOP */
1187 #define _WTIMER_CMD_STOP_DEFAULT                    0x00000000UL                     /**< Mode DEFAULT for WTIMER_CMD */
1188 #define WTIMER_CMD_STOP_DEFAULT                     (_WTIMER_CMD_STOP_DEFAULT << 1)  /**< Shifted mode DEFAULT for WTIMER_CMD */
1189 
1190 /* Bit fields for WTIMER STATUS */
1191 #define _WTIMER_STATUS_RESETVALUE                   0x00000000UL                           /**< Default value for WTIMER_STATUS */
1192 #define _WTIMER_STATUS_MASK                         0x0F0F0F07UL                           /**< Mask for WTIMER_STATUS */
1193 #define WTIMER_STATUS_RUNNING                       (0x1UL << 0)                           /**< Running */
1194 #define _WTIMER_STATUS_RUNNING_SHIFT                0                                      /**< Shift value for TIMER_RUNNING */
1195 #define _WTIMER_STATUS_RUNNING_MASK                 0x1UL                                  /**< Bit mask for TIMER_RUNNING */
1196 #define _WTIMER_STATUS_RUNNING_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for WTIMER_STATUS */
1197 #define WTIMER_STATUS_RUNNING_DEFAULT               (_WTIMER_STATUS_RUNNING_DEFAULT << 0)  /**< Shifted mode DEFAULT for WTIMER_STATUS */
1198 #define WTIMER_STATUS_DIR                           (0x1UL << 1)                           /**< Direction */
1199 #define _WTIMER_STATUS_DIR_SHIFT                    1                                      /**< Shift value for TIMER_DIR */
1200 #define _WTIMER_STATUS_DIR_MASK                     0x2UL                                  /**< Bit mask for TIMER_DIR */
1201 #define _WTIMER_STATUS_DIR_DEFAULT                  0x00000000UL                           /**< Mode DEFAULT for WTIMER_STATUS */
1202 #define _WTIMER_STATUS_DIR_UP                       0x00000000UL                           /**< Mode UP for WTIMER_STATUS */
1203 #define _WTIMER_STATUS_DIR_DOWN                     0x00000001UL                           /**< Mode DOWN for WTIMER_STATUS */
1204 #define WTIMER_STATUS_DIR_DEFAULT                   (_WTIMER_STATUS_DIR_DEFAULT << 1)      /**< Shifted mode DEFAULT for WTIMER_STATUS */
1205 #define WTIMER_STATUS_DIR_UP                        (_WTIMER_STATUS_DIR_UP << 1)           /**< Shifted mode UP for WTIMER_STATUS */
1206 #define WTIMER_STATUS_DIR_DOWN                      (_WTIMER_STATUS_DIR_DOWN << 1)         /**< Shifted mode DOWN for WTIMER_STATUS */
1207 #define WTIMER_STATUS_TOPBV                         (0x1UL << 2)                           /**< TOPB Valid */
1208 #define _WTIMER_STATUS_TOPBV_SHIFT                  2                                      /**< Shift value for TIMER_TOPBV */
1209 #define _WTIMER_STATUS_TOPBV_MASK                   0x4UL                                  /**< Bit mask for TIMER_TOPBV */
1210 #define _WTIMER_STATUS_TOPBV_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for WTIMER_STATUS */
1211 #define WTIMER_STATUS_TOPBV_DEFAULT                 (_WTIMER_STATUS_TOPBV_DEFAULT << 2)    /**< Shifted mode DEFAULT for WTIMER_STATUS */
1212 #define WTIMER_STATUS_CCVBV0                        (0x1UL << 8)                           /**< CC0 CCVB Valid */
1213 #define _WTIMER_STATUS_CCVBV0_SHIFT                 8                                      /**< Shift value for TIMER_CCVBV0 */
1214 #define _WTIMER_STATUS_CCVBV0_MASK                  0x100UL                                /**< Bit mask for TIMER_CCVBV0 */
1215 #define _WTIMER_STATUS_CCVBV0_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for WTIMER_STATUS */
1216 #define WTIMER_STATUS_CCVBV0_DEFAULT                (_WTIMER_STATUS_CCVBV0_DEFAULT << 8)   /**< Shifted mode DEFAULT for WTIMER_STATUS */
1217 #define WTIMER_STATUS_CCVBV1                        (0x1UL << 9)                           /**< CC1 CCVB Valid */
1218 #define _WTIMER_STATUS_CCVBV1_SHIFT                 9                                      /**< Shift value for TIMER_CCVBV1 */
1219 #define _WTIMER_STATUS_CCVBV1_MASK                  0x200UL                                /**< Bit mask for TIMER_CCVBV1 */
1220 #define _WTIMER_STATUS_CCVBV1_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for WTIMER_STATUS */
1221 #define WTIMER_STATUS_CCVBV1_DEFAULT                (_WTIMER_STATUS_CCVBV1_DEFAULT << 9)   /**< Shifted mode DEFAULT for WTIMER_STATUS */
1222 #define WTIMER_STATUS_CCVBV2                        (0x1UL << 10)                          /**< CC2 CCVB Valid */
1223 #define _WTIMER_STATUS_CCVBV2_SHIFT                 10                                     /**< Shift value for TIMER_CCVBV2 */
1224 #define _WTIMER_STATUS_CCVBV2_MASK                  0x400UL                                /**< Bit mask for TIMER_CCVBV2 */
1225 #define _WTIMER_STATUS_CCVBV2_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for WTIMER_STATUS */
1226 #define WTIMER_STATUS_CCVBV2_DEFAULT                (_WTIMER_STATUS_CCVBV2_DEFAULT << 10)  /**< Shifted mode DEFAULT for WTIMER_STATUS */
1227 #define WTIMER_STATUS_CCVBV3                        (0x1UL << 11)                          /**< CC3 CCVB Valid */
1228 #define _WTIMER_STATUS_CCVBV3_SHIFT                 11                                     /**< Shift value for TIMER_CCVBV3 */
1229 #define _WTIMER_STATUS_CCVBV3_MASK                  0x800UL                                /**< Bit mask for TIMER_CCVBV3 */
1230 #define _WTIMER_STATUS_CCVBV3_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for WTIMER_STATUS */
1231 #define WTIMER_STATUS_CCVBV3_DEFAULT                (_WTIMER_STATUS_CCVBV3_DEFAULT << 11)  /**< Shifted mode DEFAULT for WTIMER_STATUS */
1232 #define WTIMER_STATUS_ICV0                          (0x1UL << 16)                          /**< CC0 Input Capture Valid */
1233 #define _WTIMER_STATUS_ICV0_SHIFT                   16                                     /**< Shift value for TIMER_ICV0 */
1234 #define _WTIMER_STATUS_ICV0_MASK                    0x10000UL                              /**< Bit mask for TIMER_ICV0 */
1235 #define _WTIMER_STATUS_ICV0_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for WTIMER_STATUS */
1236 #define WTIMER_STATUS_ICV0_DEFAULT                  (_WTIMER_STATUS_ICV0_DEFAULT << 16)    /**< Shifted mode DEFAULT for WTIMER_STATUS */
1237 #define WTIMER_STATUS_ICV1                          (0x1UL << 17)                          /**< CC1 Input Capture Valid */
1238 #define _WTIMER_STATUS_ICV1_SHIFT                   17                                     /**< Shift value for TIMER_ICV1 */
1239 #define _WTIMER_STATUS_ICV1_MASK                    0x20000UL                              /**< Bit mask for TIMER_ICV1 */
1240 #define _WTIMER_STATUS_ICV1_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for WTIMER_STATUS */
1241 #define WTIMER_STATUS_ICV1_DEFAULT                  (_WTIMER_STATUS_ICV1_DEFAULT << 17)    /**< Shifted mode DEFAULT for WTIMER_STATUS */
1242 #define WTIMER_STATUS_ICV2                          (0x1UL << 18)                          /**< CC2 Input Capture Valid */
1243 #define _WTIMER_STATUS_ICV2_SHIFT                   18                                     /**< Shift value for TIMER_ICV2 */
1244 #define _WTIMER_STATUS_ICV2_MASK                    0x40000UL                              /**< Bit mask for TIMER_ICV2 */
1245 #define _WTIMER_STATUS_ICV2_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for WTIMER_STATUS */
1246 #define WTIMER_STATUS_ICV2_DEFAULT                  (_WTIMER_STATUS_ICV2_DEFAULT << 18)    /**< Shifted mode DEFAULT for WTIMER_STATUS */
1247 #define WTIMER_STATUS_ICV3                          (0x1UL << 19)                          /**< CC3 Input Capture Valid */
1248 #define _WTIMER_STATUS_ICV3_SHIFT                   19                                     /**< Shift value for TIMER_ICV3 */
1249 #define _WTIMER_STATUS_ICV3_MASK                    0x80000UL                              /**< Bit mask for TIMER_ICV3 */
1250 #define _WTIMER_STATUS_ICV3_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for WTIMER_STATUS */
1251 #define WTIMER_STATUS_ICV3_DEFAULT                  (_WTIMER_STATUS_ICV3_DEFAULT << 19)    /**< Shifted mode DEFAULT for WTIMER_STATUS */
1252 #define WTIMER_STATUS_CCPOL0                        (0x1UL << 24)                          /**< CC0 Polarity */
1253 #define _WTIMER_STATUS_CCPOL0_SHIFT                 24                                     /**< Shift value for TIMER_CCPOL0 */
1254 #define _WTIMER_STATUS_CCPOL0_MASK                  0x1000000UL                            /**< Bit mask for TIMER_CCPOL0 */
1255 #define _WTIMER_STATUS_CCPOL0_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for WTIMER_STATUS */
1256 #define _WTIMER_STATUS_CCPOL0_LOWRISE               0x00000000UL                           /**< Mode LOWRISE for WTIMER_STATUS */
1257 #define _WTIMER_STATUS_CCPOL0_HIGHFALL              0x00000001UL                           /**< Mode HIGHFALL for WTIMER_STATUS */
1258 #define WTIMER_STATUS_CCPOL0_DEFAULT                (_WTIMER_STATUS_CCPOL0_DEFAULT << 24)  /**< Shifted mode DEFAULT for WTIMER_STATUS */
1259 #define WTIMER_STATUS_CCPOL0_LOWRISE                (_WTIMER_STATUS_CCPOL0_LOWRISE << 24)  /**< Shifted mode LOWRISE for WTIMER_STATUS */
1260 #define WTIMER_STATUS_CCPOL0_HIGHFALL               (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
1261 #define WTIMER_STATUS_CCPOL1                        (0x1UL << 25)                          /**< CC1 Polarity */
1262 #define _WTIMER_STATUS_CCPOL1_SHIFT                 25                                     /**< Shift value for TIMER_CCPOL1 */
1263 #define _WTIMER_STATUS_CCPOL1_MASK                  0x2000000UL                            /**< Bit mask for TIMER_CCPOL1 */
1264 #define _WTIMER_STATUS_CCPOL1_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for WTIMER_STATUS */
1265 #define _WTIMER_STATUS_CCPOL1_LOWRISE               0x00000000UL                           /**< Mode LOWRISE for WTIMER_STATUS */
1266 #define _WTIMER_STATUS_CCPOL1_HIGHFALL              0x00000001UL                           /**< Mode HIGHFALL for WTIMER_STATUS */
1267 #define WTIMER_STATUS_CCPOL1_DEFAULT                (_WTIMER_STATUS_CCPOL1_DEFAULT << 25)  /**< Shifted mode DEFAULT for WTIMER_STATUS */
1268 #define WTIMER_STATUS_CCPOL1_LOWRISE                (_WTIMER_STATUS_CCPOL1_LOWRISE << 25)  /**< Shifted mode LOWRISE for WTIMER_STATUS */
1269 #define WTIMER_STATUS_CCPOL1_HIGHFALL               (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
1270 #define WTIMER_STATUS_CCPOL2                        (0x1UL << 26)                          /**< CC2 Polarity */
1271 #define _WTIMER_STATUS_CCPOL2_SHIFT                 26                                     /**< Shift value for TIMER_CCPOL2 */
1272 #define _WTIMER_STATUS_CCPOL2_MASK                  0x4000000UL                            /**< Bit mask for TIMER_CCPOL2 */
1273 #define _WTIMER_STATUS_CCPOL2_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for WTIMER_STATUS */
1274 #define _WTIMER_STATUS_CCPOL2_LOWRISE               0x00000000UL                           /**< Mode LOWRISE for WTIMER_STATUS */
1275 #define _WTIMER_STATUS_CCPOL2_HIGHFALL              0x00000001UL                           /**< Mode HIGHFALL for WTIMER_STATUS */
1276 #define WTIMER_STATUS_CCPOL2_DEFAULT                (_WTIMER_STATUS_CCPOL2_DEFAULT << 26)  /**< Shifted mode DEFAULT for WTIMER_STATUS */
1277 #define WTIMER_STATUS_CCPOL2_LOWRISE                (_WTIMER_STATUS_CCPOL2_LOWRISE << 26)  /**< Shifted mode LOWRISE for WTIMER_STATUS */
1278 #define WTIMER_STATUS_CCPOL2_HIGHFALL               (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
1279 #define WTIMER_STATUS_CCPOL3                        (0x1UL << 27)                          /**< CC3 Polarity */
1280 #define _WTIMER_STATUS_CCPOL3_SHIFT                 27                                     /**< Shift value for TIMER_CCPOL3 */
1281 #define _WTIMER_STATUS_CCPOL3_MASK                  0x8000000UL                            /**< Bit mask for TIMER_CCPOL3 */
1282 #define _WTIMER_STATUS_CCPOL3_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for WTIMER_STATUS */
1283 #define _WTIMER_STATUS_CCPOL3_LOWRISE               0x00000000UL                           /**< Mode LOWRISE for WTIMER_STATUS */
1284 #define _WTIMER_STATUS_CCPOL3_HIGHFALL              0x00000001UL                           /**< Mode HIGHFALL for WTIMER_STATUS */
1285 #define WTIMER_STATUS_CCPOL3_DEFAULT                (_WTIMER_STATUS_CCPOL3_DEFAULT << 27)  /**< Shifted mode DEFAULT for WTIMER_STATUS */
1286 #define WTIMER_STATUS_CCPOL3_LOWRISE                (_WTIMER_STATUS_CCPOL3_LOWRISE << 27)  /**< Shifted mode LOWRISE for WTIMER_STATUS */
1287 #define WTIMER_STATUS_CCPOL3_HIGHFALL               (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */
1288 
1289 /* Bit fields for WTIMER IF */
1290 #define _WTIMER_IF_RESETVALUE                       0x00000000UL                      /**< Default value for WTIMER_IF */
1291 #define _WTIMER_IF_MASK                             0x00000FF7UL                      /**< Mask for WTIMER_IF */
1292 #define WTIMER_IF_OF                                (0x1UL << 0)                      /**< Overflow Interrupt Flag */
1293 #define _WTIMER_IF_OF_SHIFT                         0                                 /**< Shift value for TIMER_OF */
1294 #define _WTIMER_IF_OF_MASK                          0x1UL                             /**< Bit mask for TIMER_OF */
1295 #define _WTIMER_IF_OF_DEFAULT                       0x00000000UL                      /**< Mode DEFAULT for WTIMER_IF */
1296 #define WTIMER_IF_OF_DEFAULT                        (_WTIMER_IF_OF_DEFAULT << 0)      /**< Shifted mode DEFAULT for WTIMER_IF */
1297 #define WTIMER_IF_UF                                (0x1UL << 1)                      /**< Underflow Interrupt Flag */
1298 #define _WTIMER_IF_UF_SHIFT                         1                                 /**< Shift value for TIMER_UF */
1299 #define _WTIMER_IF_UF_MASK                          0x2UL                             /**< Bit mask for TIMER_UF */
1300 #define _WTIMER_IF_UF_DEFAULT                       0x00000000UL                      /**< Mode DEFAULT for WTIMER_IF */
1301 #define WTIMER_IF_UF_DEFAULT                        (_WTIMER_IF_UF_DEFAULT << 1)      /**< Shifted mode DEFAULT for WTIMER_IF */
1302 #define WTIMER_IF_DIRCHG                            (0x1UL << 2)                      /**< Direction Change Detect Interrupt Flag */
1303 #define _WTIMER_IF_DIRCHG_SHIFT                     2                                 /**< Shift value for TIMER_DIRCHG */
1304 #define _WTIMER_IF_DIRCHG_MASK                      0x4UL                             /**< Bit mask for TIMER_DIRCHG */
1305 #define _WTIMER_IF_DIRCHG_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for WTIMER_IF */
1306 #define WTIMER_IF_DIRCHG_DEFAULT                    (_WTIMER_IF_DIRCHG_DEFAULT << 2)  /**< Shifted mode DEFAULT for WTIMER_IF */
1307 #define WTIMER_IF_CC0                               (0x1UL << 4)                      /**< CC Channel 0 Interrupt Flag */
1308 #define _WTIMER_IF_CC0_SHIFT                        4                                 /**< Shift value for TIMER_CC0 */
1309 #define _WTIMER_IF_CC0_MASK                         0x10UL                            /**< Bit mask for TIMER_CC0 */
1310 #define _WTIMER_IF_CC0_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for WTIMER_IF */
1311 #define WTIMER_IF_CC0_DEFAULT                       (_WTIMER_IF_CC0_DEFAULT << 4)     /**< Shifted mode DEFAULT for WTIMER_IF */
1312 #define WTIMER_IF_CC1                               (0x1UL << 5)                      /**< CC Channel 1 Interrupt Flag */
1313 #define _WTIMER_IF_CC1_SHIFT                        5                                 /**< Shift value for TIMER_CC1 */
1314 #define _WTIMER_IF_CC1_MASK                         0x20UL                            /**< Bit mask for TIMER_CC1 */
1315 #define _WTIMER_IF_CC1_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for WTIMER_IF */
1316 #define WTIMER_IF_CC1_DEFAULT                       (_WTIMER_IF_CC1_DEFAULT << 5)     /**< Shifted mode DEFAULT for WTIMER_IF */
1317 #define WTIMER_IF_CC2                               (0x1UL << 6)                      /**< CC Channel 2 Interrupt Flag */
1318 #define _WTIMER_IF_CC2_SHIFT                        6                                 /**< Shift value for TIMER_CC2 */
1319 #define _WTIMER_IF_CC2_MASK                         0x40UL                            /**< Bit mask for TIMER_CC2 */
1320 #define _WTIMER_IF_CC2_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for WTIMER_IF */
1321 #define WTIMER_IF_CC2_DEFAULT                       (_WTIMER_IF_CC2_DEFAULT << 6)     /**< Shifted mode DEFAULT for WTIMER_IF */
1322 #define WTIMER_IF_CC3                               (0x1UL << 7)                      /**< CC Channel 3 Interrupt Flag */
1323 #define _WTIMER_IF_CC3_SHIFT                        7                                 /**< Shift value for TIMER_CC3 */
1324 #define _WTIMER_IF_CC3_MASK                         0x80UL                            /**< Bit mask for TIMER_CC3 */
1325 #define _WTIMER_IF_CC3_DEFAULT                      0x00000000UL                      /**< Mode DEFAULT for WTIMER_IF */
1326 #define WTIMER_IF_CC3_DEFAULT                       (_WTIMER_IF_CC3_DEFAULT << 7)     /**< Shifted mode DEFAULT for WTIMER_IF */
1327 #define WTIMER_IF_ICBOF0                            (0x1UL << 8)                      /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
1328 #define _WTIMER_IF_ICBOF0_SHIFT                     8                                 /**< Shift value for TIMER_ICBOF0 */
1329 #define _WTIMER_IF_ICBOF0_MASK                      0x100UL                           /**< Bit mask for TIMER_ICBOF0 */
1330 #define _WTIMER_IF_ICBOF0_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for WTIMER_IF */
1331 #define WTIMER_IF_ICBOF0_DEFAULT                    (_WTIMER_IF_ICBOF0_DEFAULT << 8)  /**< Shifted mode DEFAULT for WTIMER_IF */
1332 #define WTIMER_IF_ICBOF1                            (0x1UL << 9)                      /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
1333 #define _WTIMER_IF_ICBOF1_SHIFT                     9                                 /**< Shift value for TIMER_ICBOF1 */
1334 #define _WTIMER_IF_ICBOF1_MASK                      0x200UL                           /**< Bit mask for TIMER_ICBOF1 */
1335 #define _WTIMER_IF_ICBOF1_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for WTIMER_IF */
1336 #define WTIMER_IF_ICBOF1_DEFAULT                    (_WTIMER_IF_ICBOF1_DEFAULT << 9)  /**< Shifted mode DEFAULT for WTIMER_IF */
1337 #define WTIMER_IF_ICBOF2                            (0x1UL << 10)                     /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
1338 #define _WTIMER_IF_ICBOF2_SHIFT                     10                                /**< Shift value for TIMER_ICBOF2 */
1339 #define _WTIMER_IF_ICBOF2_MASK                      0x400UL                           /**< Bit mask for TIMER_ICBOF2 */
1340 #define _WTIMER_IF_ICBOF2_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for WTIMER_IF */
1341 #define WTIMER_IF_ICBOF2_DEFAULT                    (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */
1342 #define WTIMER_IF_ICBOF3                            (0x1UL << 11)                     /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */
1343 #define _WTIMER_IF_ICBOF3_SHIFT                     11                                /**< Shift value for TIMER_ICBOF3 */
1344 #define _WTIMER_IF_ICBOF3_MASK                      0x800UL                           /**< Bit mask for TIMER_ICBOF3 */
1345 #define _WTIMER_IF_ICBOF3_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for WTIMER_IF */
1346 #define WTIMER_IF_ICBOF3_DEFAULT                    (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */
1347 
1348 /* Bit fields for WTIMER IFS */
1349 #define _WTIMER_IFS_RESETVALUE                      0x00000000UL                       /**< Default value for WTIMER_IFS */
1350 #define _WTIMER_IFS_MASK                            0x00000FF7UL                       /**< Mask for WTIMER_IFS */
1351 #define WTIMER_IFS_OF                               (0x1UL << 0)                       /**< Set OF Interrupt Flag */
1352 #define _WTIMER_IFS_OF_SHIFT                        0                                  /**< Shift value for TIMER_OF */
1353 #define _WTIMER_IFS_OF_MASK                         0x1UL                              /**< Bit mask for TIMER_OF */
1354 #define _WTIMER_IFS_OF_DEFAULT                      0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFS */
1355 #define WTIMER_IFS_OF_DEFAULT                       (_WTIMER_IFS_OF_DEFAULT << 0)      /**< Shifted mode DEFAULT for WTIMER_IFS */
1356 #define WTIMER_IFS_UF                               (0x1UL << 1)                       /**< Set UF Interrupt Flag */
1357 #define _WTIMER_IFS_UF_SHIFT                        1                                  /**< Shift value for TIMER_UF */
1358 #define _WTIMER_IFS_UF_MASK                         0x2UL                              /**< Bit mask for TIMER_UF */
1359 #define _WTIMER_IFS_UF_DEFAULT                      0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFS */
1360 #define WTIMER_IFS_UF_DEFAULT                       (_WTIMER_IFS_UF_DEFAULT << 1)      /**< Shifted mode DEFAULT for WTIMER_IFS */
1361 #define WTIMER_IFS_DIRCHG                           (0x1UL << 2)                       /**< Set DIRCHG Interrupt Flag */
1362 #define _WTIMER_IFS_DIRCHG_SHIFT                    2                                  /**< Shift value for TIMER_DIRCHG */
1363 #define _WTIMER_IFS_DIRCHG_MASK                     0x4UL                              /**< Bit mask for TIMER_DIRCHG */
1364 #define _WTIMER_IFS_DIRCHG_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFS */
1365 #define WTIMER_IFS_DIRCHG_DEFAULT                   (_WTIMER_IFS_DIRCHG_DEFAULT << 2)  /**< Shifted mode DEFAULT for WTIMER_IFS */
1366 #define WTIMER_IFS_CC0                              (0x1UL << 4)                       /**< Set CC0 Interrupt Flag */
1367 #define _WTIMER_IFS_CC0_SHIFT                       4                                  /**< Shift value for TIMER_CC0 */
1368 #define _WTIMER_IFS_CC0_MASK                        0x10UL                             /**< Bit mask for TIMER_CC0 */
1369 #define _WTIMER_IFS_CC0_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFS */
1370 #define WTIMER_IFS_CC0_DEFAULT                      (_WTIMER_IFS_CC0_DEFAULT << 4)     /**< Shifted mode DEFAULT for WTIMER_IFS */
1371 #define WTIMER_IFS_CC1                              (0x1UL << 5)                       /**< Set CC1 Interrupt Flag */
1372 #define _WTIMER_IFS_CC1_SHIFT                       5                                  /**< Shift value for TIMER_CC1 */
1373 #define _WTIMER_IFS_CC1_MASK                        0x20UL                             /**< Bit mask for TIMER_CC1 */
1374 #define _WTIMER_IFS_CC1_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFS */
1375 #define WTIMER_IFS_CC1_DEFAULT                      (_WTIMER_IFS_CC1_DEFAULT << 5)     /**< Shifted mode DEFAULT for WTIMER_IFS */
1376 #define WTIMER_IFS_CC2                              (0x1UL << 6)                       /**< Set CC2 Interrupt Flag */
1377 #define _WTIMER_IFS_CC2_SHIFT                       6                                  /**< Shift value for TIMER_CC2 */
1378 #define _WTIMER_IFS_CC2_MASK                        0x40UL                             /**< Bit mask for TIMER_CC2 */
1379 #define _WTIMER_IFS_CC2_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFS */
1380 #define WTIMER_IFS_CC2_DEFAULT                      (_WTIMER_IFS_CC2_DEFAULT << 6)     /**< Shifted mode DEFAULT for WTIMER_IFS */
1381 #define WTIMER_IFS_CC3                              (0x1UL << 7)                       /**< Set CC3 Interrupt Flag */
1382 #define _WTIMER_IFS_CC3_SHIFT                       7                                  /**< Shift value for TIMER_CC3 */
1383 #define _WTIMER_IFS_CC3_MASK                        0x80UL                             /**< Bit mask for TIMER_CC3 */
1384 #define _WTIMER_IFS_CC3_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFS */
1385 #define WTIMER_IFS_CC3_DEFAULT                      (_WTIMER_IFS_CC3_DEFAULT << 7)     /**< Shifted mode DEFAULT for WTIMER_IFS */
1386 #define WTIMER_IFS_ICBOF0                           (0x1UL << 8)                       /**< Set ICBOF0 Interrupt Flag */
1387 #define _WTIMER_IFS_ICBOF0_SHIFT                    8                                  /**< Shift value for TIMER_ICBOF0 */
1388 #define _WTIMER_IFS_ICBOF0_MASK                     0x100UL                            /**< Bit mask for TIMER_ICBOF0 */
1389 #define _WTIMER_IFS_ICBOF0_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFS */
1390 #define WTIMER_IFS_ICBOF0_DEFAULT                   (_WTIMER_IFS_ICBOF0_DEFAULT << 8)  /**< Shifted mode DEFAULT for WTIMER_IFS */
1391 #define WTIMER_IFS_ICBOF1                           (0x1UL << 9)                       /**< Set ICBOF1 Interrupt Flag */
1392 #define _WTIMER_IFS_ICBOF1_SHIFT                    9                                  /**< Shift value for TIMER_ICBOF1 */
1393 #define _WTIMER_IFS_ICBOF1_MASK                     0x200UL                            /**< Bit mask for TIMER_ICBOF1 */
1394 #define _WTIMER_IFS_ICBOF1_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFS */
1395 #define WTIMER_IFS_ICBOF1_DEFAULT                   (_WTIMER_IFS_ICBOF1_DEFAULT << 9)  /**< Shifted mode DEFAULT for WTIMER_IFS */
1396 #define WTIMER_IFS_ICBOF2                           (0x1UL << 10)                      /**< Set ICBOF2 Interrupt Flag */
1397 #define _WTIMER_IFS_ICBOF2_SHIFT                    10                                 /**< Shift value for TIMER_ICBOF2 */
1398 #define _WTIMER_IFS_ICBOF2_MASK                     0x400UL                            /**< Bit mask for TIMER_ICBOF2 */
1399 #define _WTIMER_IFS_ICBOF2_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFS */
1400 #define WTIMER_IFS_ICBOF2_DEFAULT                   (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */
1401 #define WTIMER_IFS_ICBOF3                           (0x1UL << 11)                      /**< Set ICBOF3 Interrupt Flag */
1402 #define _WTIMER_IFS_ICBOF3_SHIFT                    11                                 /**< Shift value for TIMER_ICBOF3 */
1403 #define _WTIMER_IFS_ICBOF3_MASK                     0x800UL                            /**< Bit mask for TIMER_ICBOF3 */
1404 #define _WTIMER_IFS_ICBOF3_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFS */
1405 #define WTIMER_IFS_ICBOF3_DEFAULT                   (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */
1406 
1407 /* Bit fields for WTIMER IFC */
1408 #define _WTIMER_IFC_RESETVALUE                      0x00000000UL                       /**< Default value for WTIMER_IFC */
1409 #define _WTIMER_IFC_MASK                            0x00000FF7UL                       /**< Mask for WTIMER_IFC */
1410 #define WTIMER_IFC_OF                               (0x1UL << 0)                       /**< Clear OF Interrupt Flag */
1411 #define _WTIMER_IFC_OF_SHIFT                        0                                  /**< Shift value for TIMER_OF */
1412 #define _WTIMER_IFC_OF_MASK                         0x1UL                              /**< Bit mask for TIMER_OF */
1413 #define _WTIMER_IFC_OF_DEFAULT                      0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFC */
1414 #define WTIMER_IFC_OF_DEFAULT                       (_WTIMER_IFC_OF_DEFAULT << 0)      /**< Shifted mode DEFAULT for WTIMER_IFC */
1415 #define WTIMER_IFC_UF                               (0x1UL << 1)                       /**< Clear UF Interrupt Flag */
1416 #define _WTIMER_IFC_UF_SHIFT                        1                                  /**< Shift value for TIMER_UF */
1417 #define _WTIMER_IFC_UF_MASK                         0x2UL                              /**< Bit mask for TIMER_UF */
1418 #define _WTIMER_IFC_UF_DEFAULT                      0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFC */
1419 #define WTIMER_IFC_UF_DEFAULT                       (_WTIMER_IFC_UF_DEFAULT << 1)      /**< Shifted mode DEFAULT for WTIMER_IFC */
1420 #define WTIMER_IFC_DIRCHG                           (0x1UL << 2)                       /**< Clear DIRCHG Interrupt Flag */
1421 #define _WTIMER_IFC_DIRCHG_SHIFT                    2                                  /**< Shift value for TIMER_DIRCHG */
1422 #define _WTIMER_IFC_DIRCHG_MASK                     0x4UL                              /**< Bit mask for TIMER_DIRCHG */
1423 #define _WTIMER_IFC_DIRCHG_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFC */
1424 #define WTIMER_IFC_DIRCHG_DEFAULT                   (_WTIMER_IFC_DIRCHG_DEFAULT << 2)  /**< Shifted mode DEFAULT for WTIMER_IFC */
1425 #define WTIMER_IFC_CC0                              (0x1UL << 4)                       /**< Clear CC0 Interrupt Flag */
1426 #define _WTIMER_IFC_CC0_SHIFT                       4                                  /**< Shift value for TIMER_CC0 */
1427 #define _WTIMER_IFC_CC0_MASK                        0x10UL                             /**< Bit mask for TIMER_CC0 */
1428 #define _WTIMER_IFC_CC0_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFC */
1429 #define WTIMER_IFC_CC0_DEFAULT                      (_WTIMER_IFC_CC0_DEFAULT << 4)     /**< Shifted mode DEFAULT for WTIMER_IFC */
1430 #define WTIMER_IFC_CC1                              (0x1UL << 5)                       /**< Clear CC1 Interrupt Flag */
1431 #define _WTIMER_IFC_CC1_SHIFT                       5                                  /**< Shift value for TIMER_CC1 */
1432 #define _WTIMER_IFC_CC1_MASK                        0x20UL                             /**< Bit mask for TIMER_CC1 */
1433 #define _WTIMER_IFC_CC1_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFC */
1434 #define WTIMER_IFC_CC1_DEFAULT                      (_WTIMER_IFC_CC1_DEFAULT << 5)     /**< Shifted mode DEFAULT for WTIMER_IFC */
1435 #define WTIMER_IFC_CC2                              (0x1UL << 6)                       /**< Clear CC2 Interrupt Flag */
1436 #define _WTIMER_IFC_CC2_SHIFT                       6                                  /**< Shift value for TIMER_CC2 */
1437 #define _WTIMER_IFC_CC2_MASK                        0x40UL                             /**< Bit mask for TIMER_CC2 */
1438 #define _WTIMER_IFC_CC2_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFC */
1439 #define WTIMER_IFC_CC2_DEFAULT                      (_WTIMER_IFC_CC2_DEFAULT << 6)     /**< Shifted mode DEFAULT for WTIMER_IFC */
1440 #define WTIMER_IFC_CC3                              (0x1UL << 7)                       /**< Clear CC3 Interrupt Flag */
1441 #define _WTIMER_IFC_CC3_SHIFT                       7                                  /**< Shift value for TIMER_CC3 */
1442 #define _WTIMER_IFC_CC3_MASK                        0x80UL                             /**< Bit mask for TIMER_CC3 */
1443 #define _WTIMER_IFC_CC3_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFC */
1444 #define WTIMER_IFC_CC3_DEFAULT                      (_WTIMER_IFC_CC3_DEFAULT << 7)     /**< Shifted mode DEFAULT for WTIMER_IFC */
1445 #define WTIMER_IFC_ICBOF0                           (0x1UL << 8)                       /**< Clear ICBOF0 Interrupt Flag */
1446 #define _WTIMER_IFC_ICBOF0_SHIFT                    8                                  /**< Shift value for TIMER_ICBOF0 */
1447 #define _WTIMER_IFC_ICBOF0_MASK                     0x100UL                            /**< Bit mask for TIMER_ICBOF0 */
1448 #define _WTIMER_IFC_ICBOF0_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFC */
1449 #define WTIMER_IFC_ICBOF0_DEFAULT                   (_WTIMER_IFC_ICBOF0_DEFAULT << 8)  /**< Shifted mode DEFAULT for WTIMER_IFC */
1450 #define WTIMER_IFC_ICBOF1                           (0x1UL << 9)                       /**< Clear ICBOF1 Interrupt Flag */
1451 #define _WTIMER_IFC_ICBOF1_SHIFT                    9                                  /**< Shift value for TIMER_ICBOF1 */
1452 #define _WTIMER_IFC_ICBOF1_MASK                     0x200UL                            /**< Bit mask for TIMER_ICBOF1 */
1453 #define _WTIMER_IFC_ICBOF1_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFC */
1454 #define WTIMER_IFC_ICBOF1_DEFAULT                   (_WTIMER_IFC_ICBOF1_DEFAULT << 9)  /**< Shifted mode DEFAULT for WTIMER_IFC */
1455 #define WTIMER_IFC_ICBOF2                           (0x1UL << 10)                      /**< Clear ICBOF2 Interrupt Flag */
1456 #define _WTIMER_IFC_ICBOF2_SHIFT                    10                                 /**< Shift value for TIMER_ICBOF2 */
1457 #define _WTIMER_IFC_ICBOF2_MASK                     0x400UL                            /**< Bit mask for TIMER_ICBOF2 */
1458 #define _WTIMER_IFC_ICBOF2_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFC */
1459 #define WTIMER_IFC_ICBOF2_DEFAULT                   (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */
1460 #define WTIMER_IFC_ICBOF3                           (0x1UL << 11)                      /**< Clear ICBOF3 Interrupt Flag */
1461 #define _WTIMER_IFC_ICBOF3_SHIFT                    11                                 /**< Shift value for TIMER_ICBOF3 */
1462 #define _WTIMER_IFC_ICBOF3_MASK                     0x800UL                            /**< Bit mask for TIMER_ICBOF3 */
1463 #define _WTIMER_IFC_ICBOF3_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for WTIMER_IFC */
1464 #define WTIMER_IFC_ICBOF3_DEFAULT                   (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */
1465 
1466 /* Bit fields for WTIMER IEN */
1467 #define _WTIMER_IEN_RESETVALUE                      0x00000000UL                       /**< Default value for WTIMER_IEN */
1468 #define _WTIMER_IEN_MASK                            0x00000FF7UL                       /**< Mask for WTIMER_IEN */
1469 #define WTIMER_IEN_OF                               (0x1UL << 0)                       /**< OF Interrupt Enable */
1470 #define _WTIMER_IEN_OF_SHIFT                        0                                  /**< Shift value for TIMER_OF */
1471 #define _WTIMER_IEN_OF_MASK                         0x1UL                              /**< Bit mask for TIMER_OF */
1472 #define _WTIMER_IEN_OF_DEFAULT                      0x00000000UL                       /**< Mode DEFAULT for WTIMER_IEN */
1473 #define WTIMER_IEN_OF_DEFAULT                       (_WTIMER_IEN_OF_DEFAULT << 0)      /**< Shifted mode DEFAULT for WTIMER_IEN */
1474 #define WTIMER_IEN_UF                               (0x1UL << 1)                       /**< UF Interrupt Enable */
1475 #define _WTIMER_IEN_UF_SHIFT                        1                                  /**< Shift value for TIMER_UF */
1476 #define _WTIMER_IEN_UF_MASK                         0x2UL                              /**< Bit mask for TIMER_UF */
1477 #define _WTIMER_IEN_UF_DEFAULT                      0x00000000UL                       /**< Mode DEFAULT for WTIMER_IEN */
1478 #define WTIMER_IEN_UF_DEFAULT                       (_WTIMER_IEN_UF_DEFAULT << 1)      /**< Shifted mode DEFAULT for WTIMER_IEN */
1479 #define WTIMER_IEN_DIRCHG                           (0x1UL << 2)                       /**< DIRCHG Interrupt Enable */
1480 #define _WTIMER_IEN_DIRCHG_SHIFT                    2                                  /**< Shift value for TIMER_DIRCHG */
1481 #define _WTIMER_IEN_DIRCHG_MASK                     0x4UL                              /**< Bit mask for TIMER_DIRCHG */
1482 #define _WTIMER_IEN_DIRCHG_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for WTIMER_IEN */
1483 #define WTIMER_IEN_DIRCHG_DEFAULT                   (_WTIMER_IEN_DIRCHG_DEFAULT << 2)  /**< Shifted mode DEFAULT for WTIMER_IEN */
1484 #define WTIMER_IEN_CC0                              (0x1UL << 4)                       /**< CC0 Interrupt Enable */
1485 #define _WTIMER_IEN_CC0_SHIFT                       4                                  /**< Shift value for TIMER_CC0 */
1486 #define _WTIMER_IEN_CC0_MASK                        0x10UL                             /**< Bit mask for TIMER_CC0 */
1487 #define _WTIMER_IEN_CC0_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for WTIMER_IEN */
1488 #define WTIMER_IEN_CC0_DEFAULT                      (_WTIMER_IEN_CC0_DEFAULT << 4)     /**< Shifted mode DEFAULT for WTIMER_IEN */
1489 #define WTIMER_IEN_CC1                              (0x1UL << 5)                       /**< CC1 Interrupt Enable */
1490 #define _WTIMER_IEN_CC1_SHIFT                       5                                  /**< Shift value for TIMER_CC1 */
1491 #define _WTIMER_IEN_CC1_MASK                        0x20UL                             /**< Bit mask for TIMER_CC1 */
1492 #define _WTIMER_IEN_CC1_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for WTIMER_IEN */
1493 #define WTIMER_IEN_CC1_DEFAULT                      (_WTIMER_IEN_CC1_DEFAULT << 5)     /**< Shifted mode DEFAULT for WTIMER_IEN */
1494 #define WTIMER_IEN_CC2                              (0x1UL << 6)                       /**< CC2 Interrupt Enable */
1495 #define _WTIMER_IEN_CC2_SHIFT                       6                                  /**< Shift value for TIMER_CC2 */
1496 #define _WTIMER_IEN_CC2_MASK                        0x40UL                             /**< Bit mask for TIMER_CC2 */
1497 #define _WTIMER_IEN_CC2_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for WTIMER_IEN */
1498 #define WTIMER_IEN_CC2_DEFAULT                      (_WTIMER_IEN_CC2_DEFAULT << 6)     /**< Shifted mode DEFAULT for WTIMER_IEN */
1499 #define WTIMER_IEN_CC3                              (0x1UL << 7)                       /**< CC3 Interrupt Enable */
1500 #define _WTIMER_IEN_CC3_SHIFT                       7                                  /**< Shift value for TIMER_CC3 */
1501 #define _WTIMER_IEN_CC3_MASK                        0x80UL                             /**< Bit mask for TIMER_CC3 */
1502 #define _WTIMER_IEN_CC3_DEFAULT                     0x00000000UL                       /**< Mode DEFAULT for WTIMER_IEN */
1503 #define WTIMER_IEN_CC3_DEFAULT                      (_WTIMER_IEN_CC3_DEFAULT << 7)     /**< Shifted mode DEFAULT for WTIMER_IEN */
1504 #define WTIMER_IEN_ICBOF0                           (0x1UL << 8)                       /**< ICBOF0 Interrupt Enable */
1505 #define _WTIMER_IEN_ICBOF0_SHIFT                    8                                  /**< Shift value for TIMER_ICBOF0 */
1506 #define _WTIMER_IEN_ICBOF0_MASK                     0x100UL                            /**< Bit mask for TIMER_ICBOF0 */
1507 #define _WTIMER_IEN_ICBOF0_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for WTIMER_IEN */
1508 #define WTIMER_IEN_ICBOF0_DEFAULT                   (_WTIMER_IEN_ICBOF0_DEFAULT << 8)  /**< Shifted mode DEFAULT for WTIMER_IEN */
1509 #define WTIMER_IEN_ICBOF1                           (0x1UL << 9)                       /**< ICBOF1 Interrupt Enable */
1510 #define _WTIMER_IEN_ICBOF1_SHIFT                    9                                  /**< Shift value for TIMER_ICBOF1 */
1511 #define _WTIMER_IEN_ICBOF1_MASK                     0x200UL                            /**< Bit mask for TIMER_ICBOF1 */
1512 #define _WTIMER_IEN_ICBOF1_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for WTIMER_IEN */
1513 #define WTIMER_IEN_ICBOF1_DEFAULT                   (_WTIMER_IEN_ICBOF1_DEFAULT << 9)  /**< Shifted mode DEFAULT for WTIMER_IEN */
1514 #define WTIMER_IEN_ICBOF2                           (0x1UL << 10)                      /**< ICBOF2 Interrupt Enable */
1515 #define _WTIMER_IEN_ICBOF2_SHIFT                    10                                 /**< Shift value for TIMER_ICBOF2 */
1516 #define _WTIMER_IEN_ICBOF2_MASK                     0x400UL                            /**< Bit mask for TIMER_ICBOF2 */
1517 #define _WTIMER_IEN_ICBOF2_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for WTIMER_IEN */
1518 #define WTIMER_IEN_ICBOF2_DEFAULT                   (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */
1519 #define WTIMER_IEN_ICBOF3                           (0x1UL << 11)                      /**< ICBOF3 Interrupt Enable */
1520 #define _WTIMER_IEN_ICBOF3_SHIFT                    11                                 /**< Shift value for TIMER_ICBOF3 */
1521 #define _WTIMER_IEN_ICBOF3_MASK                     0x800UL                            /**< Bit mask for TIMER_ICBOF3 */
1522 #define _WTIMER_IEN_ICBOF3_DEFAULT                  0x00000000UL                       /**< Mode DEFAULT for WTIMER_IEN */
1523 #define WTIMER_IEN_ICBOF3_DEFAULT                   (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */
1524 
1525 /* Bit fields for WTIMER TOP */
1526 #define _WTIMER_TOP_RESETVALUE                      0x0000FFFFUL                   /**< Default value for WTIMER_TOP */
1527 #define _WTIMER_TOP_MASK                            0xFFFFFFFFUL                   /**< Mask for WTIMER_TOP */
1528 #define _WTIMER_TOP_TOP_SHIFT                       0                              /**< Shift value for TIMER_TOP */
1529 #define _WTIMER_TOP_TOP_MASK                        0xFFFFFFFFUL                   /**< Bit mask for TIMER_TOP */
1530 #define _WTIMER_TOP_TOP_DEFAULT                     0x0000FFFFUL                   /**< Mode DEFAULT for WTIMER_TOP */
1531 #define WTIMER_TOP_TOP_DEFAULT                      (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */
1532 
1533 /* Bit fields for WTIMER TOPB */
1534 #define _WTIMER_TOPB_RESETVALUE                     0x00000000UL                     /**< Default value for WTIMER_TOPB */
1535 #define _WTIMER_TOPB_MASK                           0xFFFFFFFFUL                     /**< Mask for WTIMER_TOPB */
1536 #define _WTIMER_TOPB_TOPB_SHIFT                     0                                /**< Shift value for TIMER_TOPB */
1537 #define _WTIMER_TOPB_TOPB_MASK                      0xFFFFFFFFUL                     /**< Bit mask for TIMER_TOPB */
1538 #define _WTIMER_TOPB_TOPB_DEFAULT                   0x00000000UL                     /**< Mode DEFAULT for WTIMER_TOPB */
1539 #define WTIMER_TOPB_TOPB_DEFAULT                    (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */
1540 
1541 /* Bit fields for WTIMER CNT */
1542 #define _WTIMER_CNT_RESETVALUE                      0x00000000UL                   /**< Default value for WTIMER_CNT */
1543 #define _WTIMER_CNT_MASK                            0xFFFFFFFFUL                   /**< Mask for WTIMER_CNT */
1544 #define _WTIMER_CNT_CNT_SHIFT                       0                              /**< Shift value for TIMER_CNT */
1545 #define _WTIMER_CNT_CNT_MASK                        0xFFFFFFFFUL                   /**< Bit mask for TIMER_CNT */
1546 #define _WTIMER_CNT_CNT_DEFAULT                     0x00000000UL                   /**< Mode DEFAULT for WTIMER_CNT */
1547 #define WTIMER_CNT_CNT_DEFAULT                      (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */
1548 
1549 /* Bit fields for WTIMER LOCK */
1550 #define _WTIMER_LOCK_RESETVALUE                     0x00000000UL                              /**< Default value for WTIMER_LOCK */
1551 #define _WTIMER_LOCK_MASK                           0x0000FFFFUL                              /**< Mask for WTIMER_LOCK */
1552 #define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT             0                                         /**< Shift value for TIMER_TIMERLOCKKEY */
1553 #define _WTIMER_LOCK_TIMERLOCKKEY_MASK              0xFFFFUL                                  /**< Bit mask for TIMER_TIMERLOCKKEY */
1554 #define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT           0x00000000UL                              /**< Mode DEFAULT for WTIMER_LOCK */
1555 #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED          0x00000000UL                              /**< Mode UNLOCKED for WTIMER_LOCK */
1556 #define _WTIMER_LOCK_TIMERLOCKKEY_LOCK              0x00000000UL                              /**< Mode LOCK for WTIMER_LOCK */
1557 #define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED            0x00000001UL                              /**< Mode LOCKED for WTIMER_LOCK */
1558 #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK            0x0000CE80UL                              /**< Mode UNLOCK for WTIMER_LOCK */
1559 #define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT            (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for WTIMER_LOCK */
1560 #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED           (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */
1561 #define WTIMER_LOCK_TIMERLOCKKEY_LOCK               (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for WTIMER_LOCK */
1562 #define WTIMER_LOCK_TIMERLOCKKEY_LOCKED             (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for WTIMER_LOCK */
1563 #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK             (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for WTIMER_LOCK */
1564 
1565 /* Bit fields for WTIMER ROUTEPEN */
1566 #define _WTIMER_ROUTEPEN_RESETVALUE                 0x00000000UL                              /**< Default value for WTIMER_ROUTEPEN */
1567 #define _WTIMER_ROUTEPEN_MASK                       0x0000070FUL                              /**< Mask for WTIMER_ROUTEPEN */
1568 #define WTIMER_ROUTEPEN_CC0PEN                      (0x1UL << 0)                              /**< CC Channel 0 Pin Enable */
1569 #define _WTIMER_ROUTEPEN_CC0PEN_SHIFT               0                                         /**< Shift value for TIMER_CC0PEN */
1570 #define _WTIMER_ROUTEPEN_CC0PEN_MASK                0x1UL                                     /**< Bit mask for TIMER_CC0PEN */
1571 #define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT             0x00000000UL                              /**< Mode DEFAULT for WTIMER_ROUTEPEN */
1572 #define WTIMER_ROUTEPEN_CC0PEN_DEFAULT              (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0)    /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
1573 #define WTIMER_ROUTEPEN_CC1PEN                      (0x1UL << 1)                              /**< CC Channel 1 Pin Enable */
1574 #define _WTIMER_ROUTEPEN_CC1PEN_SHIFT               1                                         /**< Shift value for TIMER_CC1PEN */
1575 #define _WTIMER_ROUTEPEN_CC1PEN_MASK                0x2UL                                     /**< Bit mask for TIMER_CC1PEN */
1576 #define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT             0x00000000UL                              /**< Mode DEFAULT for WTIMER_ROUTEPEN */
1577 #define WTIMER_ROUTEPEN_CC1PEN_DEFAULT              (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1)    /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
1578 #define WTIMER_ROUTEPEN_CC2PEN                      (0x1UL << 2)                              /**< CC Channel 2 Pin Enable */
1579 #define _WTIMER_ROUTEPEN_CC2PEN_SHIFT               2                                         /**< Shift value for TIMER_CC2PEN */
1580 #define _WTIMER_ROUTEPEN_CC2PEN_MASK                0x4UL                                     /**< Bit mask for TIMER_CC2PEN */
1581 #define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT             0x00000000UL                              /**< Mode DEFAULT for WTIMER_ROUTEPEN */
1582 #define WTIMER_ROUTEPEN_CC2PEN_DEFAULT              (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2)    /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
1583 #define WTIMER_ROUTEPEN_CC3PEN                      (0x1UL << 3)                              /**< CC Channel 3 Pin Enable */
1584 #define _WTIMER_ROUTEPEN_CC3PEN_SHIFT               3                                         /**< Shift value for TIMER_CC3PEN */
1585 #define _WTIMER_ROUTEPEN_CC3PEN_MASK                0x8UL                                     /**< Bit mask for TIMER_CC3PEN */
1586 #define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT             0x00000000UL                              /**< Mode DEFAULT for WTIMER_ROUTEPEN */
1587 #define WTIMER_ROUTEPEN_CC3PEN_DEFAULT              (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3)    /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
1588 #define WTIMER_ROUTEPEN_CDTI0PEN                    (0x1UL << 8)                              /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */
1589 #define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT             8                                         /**< Shift value for TIMER_CDTI0PEN */
1590 #define _WTIMER_ROUTEPEN_CDTI0PEN_MASK              0x100UL                                   /**< Bit mask for TIMER_CDTI0PEN */
1591 #define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT           0x00000000UL                              /**< Mode DEFAULT for WTIMER_ROUTEPEN */
1592 #define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT            (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8)  /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
1593 #define WTIMER_ROUTEPEN_CDTI1PEN                    (0x1UL << 9)                              /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */
1594 #define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT             9                                         /**< Shift value for TIMER_CDTI1PEN */
1595 #define _WTIMER_ROUTEPEN_CDTI1PEN_MASK              0x200UL                                   /**< Bit mask for TIMER_CDTI1PEN */
1596 #define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT           0x00000000UL                              /**< Mode DEFAULT for WTIMER_ROUTEPEN */
1597 #define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT            (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9)  /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
1598 #define WTIMER_ROUTEPEN_CDTI2PEN                    (0x1UL << 10)                             /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */
1599 #define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT             10                                        /**< Shift value for TIMER_CDTI2PEN */
1600 #define _WTIMER_ROUTEPEN_CDTI2PEN_MASK              0x400UL                                   /**< Bit mask for TIMER_CDTI2PEN */
1601 #define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT           0x00000000UL                              /**< Mode DEFAULT for WTIMER_ROUTEPEN */
1602 #define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT            (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */
1603 
1604 /* Bit fields for WTIMER ROUTELOC0 */
1605 #define _WTIMER_ROUTELOC0_RESETVALUE                0x00000000UL                             /**< Default value for WTIMER_ROUTELOC0 */
1606 #define _WTIMER_ROUTELOC0_MASK                      0x07070707UL                             /**< Mask for WTIMER_ROUTELOC0 */
1607 #define _WTIMER_ROUTELOC0_CC0LOC_SHIFT              0                                        /**< Shift value for TIMER_CC0LOC */
1608 #define _WTIMER_ROUTELOC0_CC0LOC_MASK               0x7UL                                    /**< Bit mask for TIMER_CC0LOC */
1609 #define _WTIMER_ROUTELOC0_CC0LOC_LOC0               0x00000000UL                             /**< Mode LOC0 for WTIMER_ROUTELOC0 */
1610 #define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
1611 #define _WTIMER_ROUTELOC0_CC0LOC_LOC1               0x00000001UL                             /**< Mode LOC1 for WTIMER_ROUTELOC0 */
1612 #define _WTIMER_ROUTELOC0_CC0LOC_LOC2               0x00000002UL                             /**< Mode LOC2 for WTIMER_ROUTELOC0 */
1613 #define _WTIMER_ROUTELOC0_CC0LOC_LOC3               0x00000003UL                             /**< Mode LOC3 for WTIMER_ROUTELOC0 */
1614 #define _WTIMER_ROUTELOC0_CC0LOC_LOC4               0x00000004UL                             /**< Mode LOC4 for WTIMER_ROUTELOC0 */
1615 #define _WTIMER_ROUTELOC0_CC0LOC_LOC5               0x00000005UL                             /**< Mode LOC5 for WTIMER_ROUTELOC0 */
1616 #define _WTIMER_ROUTELOC0_CC0LOC_LOC6               0x00000006UL                             /**< Mode LOC6 for WTIMER_ROUTELOC0 */
1617 #define _WTIMER_ROUTELOC0_CC0LOC_LOC7               0x00000007UL                             /**< Mode LOC7 for WTIMER_ROUTELOC0 */
1618 #define WTIMER_ROUTELOC0_CC0LOC_LOC0                (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0)     /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
1619 #define WTIMER_ROUTELOC0_CC0LOC_DEFAULT             (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0)  /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
1620 #define WTIMER_ROUTELOC0_CC0LOC_LOC1                (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0)     /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
1621 #define WTIMER_ROUTELOC0_CC0LOC_LOC2                (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0)     /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
1622 #define WTIMER_ROUTELOC0_CC0LOC_LOC3                (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0)     /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
1623 #define WTIMER_ROUTELOC0_CC0LOC_LOC4                (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0)     /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
1624 #define WTIMER_ROUTELOC0_CC0LOC_LOC5                (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0)     /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
1625 #define WTIMER_ROUTELOC0_CC0LOC_LOC6                (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0)     /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
1626 #define WTIMER_ROUTELOC0_CC0LOC_LOC7                (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0)     /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
1627 #define _WTIMER_ROUTELOC0_CC1LOC_SHIFT              8                                        /**< Shift value for TIMER_CC1LOC */
1628 #define _WTIMER_ROUTELOC0_CC1LOC_MASK               0x700UL                                  /**< Bit mask for TIMER_CC1LOC */
1629 #define _WTIMER_ROUTELOC0_CC1LOC_LOC0               0x00000000UL                             /**< Mode LOC0 for WTIMER_ROUTELOC0 */
1630 #define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
1631 #define _WTIMER_ROUTELOC0_CC1LOC_LOC1               0x00000001UL                             /**< Mode LOC1 for WTIMER_ROUTELOC0 */
1632 #define _WTIMER_ROUTELOC0_CC1LOC_LOC2               0x00000002UL                             /**< Mode LOC2 for WTIMER_ROUTELOC0 */
1633 #define _WTIMER_ROUTELOC0_CC1LOC_LOC3               0x00000003UL                             /**< Mode LOC3 for WTIMER_ROUTELOC0 */
1634 #define _WTIMER_ROUTELOC0_CC1LOC_LOC4               0x00000004UL                             /**< Mode LOC4 for WTIMER_ROUTELOC0 */
1635 #define _WTIMER_ROUTELOC0_CC1LOC_LOC5               0x00000005UL                             /**< Mode LOC5 for WTIMER_ROUTELOC0 */
1636 #define _WTIMER_ROUTELOC0_CC1LOC_LOC6               0x00000006UL                             /**< Mode LOC6 for WTIMER_ROUTELOC0 */
1637 #define _WTIMER_ROUTELOC0_CC1LOC_LOC7               0x00000007UL                             /**< Mode LOC7 for WTIMER_ROUTELOC0 */
1638 #define WTIMER_ROUTELOC0_CC1LOC_LOC0                (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8)     /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
1639 #define WTIMER_ROUTELOC0_CC1LOC_DEFAULT             (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8)  /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
1640 #define WTIMER_ROUTELOC0_CC1LOC_LOC1                (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8)     /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
1641 #define WTIMER_ROUTELOC0_CC1LOC_LOC2                (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8)     /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
1642 #define WTIMER_ROUTELOC0_CC1LOC_LOC3                (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8)     /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
1643 #define WTIMER_ROUTELOC0_CC1LOC_LOC4                (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8)     /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
1644 #define WTIMER_ROUTELOC0_CC1LOC_LOC5                (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8)     /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
1645 #define WTIMER_ROUTELOC0_CC1LOC_LOC6                (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8)     /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
1646 #define WTIMER_ROUTELOC0_CC1LOC_LOC7                (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8)     /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
1647 #define _WTIMER_ROUTELOC0_CC2LOC_SHIFT              16                                       /**< Shift value for TIMER_CC2LOC */
1648 #define _WTIMER_ROUTELOC0_CC2LOC_MASK               0x70000UL                                /**< Bit mask for TIMER_CC2LOC */
1649 #define _WTIMER_ROUTELOC0_CC2LOC_LOC0               0x00000000UL                             /**< Mode LOC0 for WTIMER_ROUTELOC0 */
1650 #define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
1651 #define _WTIMER_ROUTELOC0_CC2LOC_LOC1               0x00000001UL                             /**< Mode LOC1 for WTIMER_ROUTELOC0 */
1652 #define _WTIMER_ROUTELOC0_CC2LOC_LOC2               0x00000002UL                             /**< Mode LOC2 for WTIMER_ROUTELOC0 */
1653 #define _WTIMER_ROUTELOC0_CC2LOC_LOC3               0x00000003UL                             /**< Mode LOC3 for WTIMER_ROUTELOC0 */
1654 #define _WTIMER_ROUTELOC0_CC2LOC_LOC4               0x00000004UL                             /**< Mode LOC4 for WTIMER_ROUTELOC0 */
1655 #define _WTIMER_ROUTELOC0_CC2LOC_LOC5               0x00000005UL                             /**< Mode LOC5 for WTIMER_ROUTELOC0 */
1656 #define _WTIMER_ROUTELOC0_CC2LOC_LOC6               0x00000006UL                             /**< Mode LOC6 for WTIMER_ROUTELOC0 */
1657 #define _WTIMER_ROUTELOC0_CC2LOC_LOC7               0x00000007UL                             /**< Mode LOC7 for WTIMER_ROUTELOC0 */
1658 #define WTIMER_ROUTELOC0_CC2LOC_LOC0                (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16)    /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
1659 #define WTIMER_ROUTELOC0_CC2LOC_DEFAULT             (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
1660 #define WTIMER_ROUTELOC0_CC2LOC_LOC1                (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16)    /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
1661 #define WTIMER_ROUTELOC0_CC2LOC_LOC2                (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16)    /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
1662 #define WTIMER_ROUTELOC0_CC2LOC_LOC3                (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16)    /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
1663 #define WTIMER_ROUTELOC0_CC2LOC_LOC4                (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16)    /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
1664 #define WTIMER_ROUTELOC0_CC2LOC_LOC5                (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16)    /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
1665 #define WTIMER_ROUTELOC0_CC2LOC_LOC6                (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16)    /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
1666 #define WTIMER_ROUTELOC0_CC2LOC_LOC7                (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16)    /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */
1667 #define _WTIMER_ROUTELOC0_CC3LOC_SHIFT              24                                       /**< Shift value for TIMER_CC3LOC */
1668 #define _WTIMER_ROUTELOC0_CC3LOC_MASK               0x7000000UL                              /**< Bit mask for TIMER_CC3LOC */
1669 #define _WTIMER_ROUTELOC0_CC3LOC_LOC0               0x00000000UL                             /**< Mode LOC0 for WTIMER_ROUTELOC0 */
1670 #define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for WTIMER_ROUTELOC0 */
1671 #define _WTIMER_ROUTELOC0_CC3LOC_LOC1               0x00000001UL                             /**< Mode LOC1 for WTIMER_ROUTELOC0 */
1672 #define _WTIMER_ROUTELOC0_CC3LOC_LOC2               0x00000002UL                             /**< Mode LOC2 for WTIMER_ROUTELOC0 */
1673 #define _WTIMER_ROUTELOC0_CC3LOC_LOC3               0x00000003UL                             /**< Mode LOC3 for WTIMER_ROUTELOC0 */
1674 #define _WTIMER_ROUTELOC0_CC3LOC_LOC4               0x00000004UL                             /**< Mode LOC4 for WTIMER_ROUTELOC0 */
1675 #define _WTIMER_ROUTELOC0_CC3LOC_LOC5               0x00000005UL                             /**< Mode LOC5 for WTIMER_ROUTELOC0 */
1676 #define _WTIMER_ROUTELOC0_CC3LOC_LOC6               0x00000006UL                             /**< Mode LOC6 for WTIMER_ROUTELOC0 */
1677 #define WTIMER_ROUTELOC0_CC3LOC_LOC0                (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24)    /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */
1678 #define WTIMER_ROUTELOC0_CC3LOC_DEFAULT             (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */
1679 #define WTIMER_ROUTELOC0_CC3LOC_LOC1                (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24)    /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */
1680 #define WTIMER_ROUTELOC0_CC3LOC_LOC2                (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24)    /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */
1681 #define WTIMER_ROUTELOC0_CC3LOC_LOC3                (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24)    /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */
1682 #define WTIMER_ROUTELOC0_CC3LOC_LOC4                (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24)    /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */
1683 #define WTIMER_ROUTELOC0_CC3LOC_LOC5                (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24)    /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */
1684 #define WTIMER_ROUTELOC0_CC3LOC_LOC6                (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24)    /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */
1685 
1686 /* Bit fields for WTIMER ROUTELOC2 */
1687 #define _WTIMER_ROUTELOC2_RESETVALUE                0x00000000UL                               /**< Default value for WTIMER_ROUTELOC2 */
1688 #define _WTIMER_ROUTELOC2_MASK                      0x00070707UL                               /**< Mask for WTIMER_ROUTELOC2 */
1689 #define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT            0                                          /**< Shift value for TIMER_CDTI0LOC */
1690 #define _WTIMER_ROUTELOC2_CDTI0LOC_MASK             0x7UL                                      /**< Bit mask for TIMER_CDTI0LOC */
1691 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0             0x00000000UL                               /**< Mode LOC0 for WTIMER_ROUTELOC2 */
1692 #define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT          0x00000000UL                               /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
1693 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1             0x00000001UL                               /**< Mode LOC1 for WTIMER_ROUTELOC2 */
1694 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2             0x00000002UL                               /**< Mode LOC2 for WTIMER_ROUTELOC2 */
1695 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3             0x00000003UL                               /**< Mode LOC3 for WTIMER_ROUTELOC2 */
1696 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4             0x00000004UL                               /**< Mode LOC4 for WTIMER_ROUTELOC2 */
1697 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC0              (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0)     /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
1698 #define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT           (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0)  /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
1699 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC1              (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0)     /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
1700 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC2              (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0)     /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
1701 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC3              (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0)     /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
1702 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC4              (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0)     /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
1703 #define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT            8                                          /**< Shift value for TIMER_CDTI1LOC */
1704 #define _WTIMER_ROUTELOC2_CDTI1LOC_MASK             0x700UL                                    /**< Bit mask for TIMER_CDTI1LOC */
1705 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0             0x00000000UL                               /**< Mode LOC0 for WTIMER_ROUTELOC2 */
1706 #define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT          0x00000000UL                               /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
1707 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1             0x00000001UL                               /**< Mode LOC1 for WTIMER_ROUTELOC2 */
1708 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2             0x00000002UL                               /**< Mode LOC2 for WTIMER_ROUTELOC2 */
1709 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3             0x00000003UL                               /**< Mode LOC3 for WTIMER_ROUTELOC2 */
1710 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4             0x00000004UL                               /**< Mode LOC4 for WTIMER_ROUTELOC2 */
1711 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC0              (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8)     /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
1712 #define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT           (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8)  /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
1713 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC1              (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8)     /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
1714 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC2              (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8)     /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
1715 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC3              (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8)     /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
1716 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC4              (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8)     /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
1717 #define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT            16                                         /**< Shift value for TIMER_CDTI2LOC */
1718 #define _WTIMER_ROUTELOC2_CDTI2LOC_MASK             0x70000UL                                  /**< Bit mask for TIMER_CDTI2LOC */
1719 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0             0x00000000UL                               /**< Mode LOC0 for WTIMER_ROUTELOC2 */
1720 #define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT          0x00000000UL                               /**< Mode DEFAULT for WTIMER_ROUTELOC2 */
1721 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1             0x00000001UL                               /**< Mode LOC1 for WTIMER_ROUTELOC2 */
1722 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2             0x00000002UL                               /**< Mode LOC2 for WTIMER_ROUTELOC2 */
1723 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3             0x00000003UL                               /**< Mode LOC3 for WTIMER_ROUTELOC2 */
1724 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4             0x00000004UL                               /**< Mode LOC4 for WTIMER_ROUTELOC2 */
1725 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC0              (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16)    /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */
1726 #define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT           (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */
1727 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC1              (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16)    /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */
1728 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC2              (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16)    /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */
1729 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC3              (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16)    /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */
1730 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC4              (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16)    /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */
1731 
1732 /* Bit fields for WTIMER CC_CTRL */
1733 #define _WTIMER_CC_CTRL_RESETVALUE                  0x00000000UL                                     /**< Default value for WTIMER_CC_CTRL */
1734 #define _WTIMER_CC_CTRL_MASK                        0x7F0F3F17UL                                     /**< Mask for WTIMER_CC_CTRL */
1735 #define _WTIMER_CC_CTRL_MODE_SHIFT                  0                                                /**< Shift value for TIMER_MODE */
1736 #define _WTIMER_CC_CTRL_MODE_MASK                   0x3UL                                            /**< Bit mask for TIMER_MODE */
1737 #define _WTIMER_CC_CTRL_MODE_DEFAULT                0x00000000UL                                     /**< Mode DEFAULT for WTIMER_CC_CTRL */
1738 #define _WTIMER_CC_CTRL_MODE_OFF                    0x00000000UL                                     /**< Mode OFF for WTIMER_CC_CTRL */
1739 #define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE           0x00000001UL                                     /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */
1740 #define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE          0x00000002UL                                     /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */
1741 #define _WTIMER_CC_CTRL_MODE_PWM                    0x00000003UL                                     /**< Mode PWM for WTIMER_CC_CTRL */
1742 #define WTIMER_CC_CTRL_MODE_DEFAULT                 (_WTIMER_CC_CTRL_MODE_DEFAULT << 0)              /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
1743 #define WTIMER_CC_CTRL_MODE_OFF                     (_WTIMER_CC_CTRL_MODE_OFF << 0)                  /**< Shifted mode OFF for WTIMER_CC_CTRL */
1744 #define WTIMER_CC_CTRL_MODE_INPUTCAPTURE            (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0)         /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */
1745 #define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE           (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0)        /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */
1746 #define WTIMER_CC_CTRL_MODE_PWM                     (_WTIMER_CC_CTRL_MODE_PWM << 0)                  /**< Shifted mode PWM for WTIMER_CC_CTRL */
1747 #define WTIMER_CC_CTRL_OUTINV                       (0x1UL << 2)                                     /**< Output Invert */
1748 #define _WTIMER_CC_CTRL_OUTINV_SHIFT                2                                                /**< Shift value for TIMER_OUTINV */
1749 #define _WTIMER_CC_CTRL_OUTINV_MASK                 0x4UL                                            /**< Bit mask for TIMER_OUTINV */
1750 #define _WTIMER_CC_CTRL_OUTINV_DEFAULT              0x00000000UL                                     /**< Mode DEFAULT for WTIMER_CC_CTRL */
1751 #define WTIMER_CC_CTRL_OUTINV_DEFAULT               (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2)            /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
1752 #define WTIMER_CC_CTRL_COIST                        (0x1UL << 4)                                     /**< Compare Output Initial State */
1753 #define _WTIMER_CC_CTRL_COIST_SHIFT                 4                                                /**< Shift value for TIMER_COIST */
1754 #define _WTIMER_CC_CTRL_COIST_MASK                  0x10UL                                           /**< Bit mask for TIMER_COIST */
1755 #define _WTIMER_CC_CTRL_COIST_DEFAULT               0x00000000UL                                     /**< Mode DEFAULT for WTIMER_CC_CTRL */
1756 #define WTIMER_CC_CTRL_COIST_DEFAULT                (_WTIMER_CC_CTRL_COIST_DEFAULT << 4)             /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
1757 #define _WTIMER_CC_CTRL_CMOA_SHIFT                  8                                                /**< Shift value for TIMER_CMOA */
1758 #define _WTIMER_CC_CTRL_CMOA_MASK                   0x300UL                                          /**< Bit mask for TIMER_CMOA */
1759 #define _WTIMER_CC_CTRL_CMOA_DEFAULT                0x00000000UL                                     /**< Mode DEFAULT for WTIMER_CC_CTRL */
1760 #define _WTIMER_CC_CTRL_CMOA_NONE                   0x00000000UL                                     /**< Mode NONE for WTIMER_CC_CTRL */
1761 #define _WTIMER_CC_CTRL_CMOA_TOGGLE                 0x00000001UL                                     /**< Mode TOGGLE for WTIMER_CC_CTRL */
1762 #define _WTIMER_CC_CTRL_CMOA_CLEAR                  0x00000002UL                                     /**< Mode CLEAR for WTIMER_CC_CTRL */
1763 #define _WTIMER_CC_CTRL_CMOA_SET                    0x00000003UL                                     /**< Mode SET for WTIMER_CC_CTRL */
1764 #define WTIMER_CC_CTRL_CMOA_DEFAULT                 (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8)              /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
1765 #define WTIMER_CC_CTRL_CMOA_NONE                    (_WTIMER_CC_CTRL_CMOA_NONE << 8)                 /**< Shifted mode NONE for WTIMER_CC_CTRL */
1766 #define WTIMER_CC_CTRL_CMOA_TOGGLE                  (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8)               /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
1767 #define WTIMER_CC_CTRL_CMOA_CLEAR                   (_WTIMER_CC_CTRL_CMOA_CLEAR << 8)                /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
1768 #define WTIMER_CC_CTRL_CMOA_SET                     (_WTIMER_CC_CTRL_CMOA_SET << 8)                  /**< Shifted mode SET for WTIMER_CC_CTRL */
1769 #define _WTIMER_CC_CTRL_COFOA_SHIFT                 10                                               /**< Shift value for TIMER_COFOA */
1770 #define _WTIMER_CC_CTRL_COFOA_MASK                  0xC00UL                                          /**< Bit mask for TIMER_COFOA */
1771 #define _WTIMER_CC_CTRL_COFOA_DEFAULT               0x00000000UL                                     /**< Mode DEFAULT for WTIMER_CC_CTRL */
1772 #define _WTIMER_CC_CTRL_COFOA_NONE                  0x00000000UL                                     /**< Mode NONE for WTIMER_CC_CTRL */
1773 #define _WTIMER_CC_CTRL_COFOA_TOGGLE                0x00000001UL                                     /**< Mode TOGGLE for WTIMER_CC_CTRL */
1774 #define _WTIMER_CC_CTRL_COFOA_CLEAR                 0x00000002UL                                     /**< Mode CLEAR for WTIMER_CC_CTRL */
1775 #define _WTIMER_CC_CTRL_COFOA_SET                   0x00000003UL                                     /**< Mode SET for WTIMER_CC_CTRL */
1776 #define WTIMER_CC_CTRL_COFOA_DEFAULT                (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10)            /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
1777 #define WTIMER_CC_CTRL_COFOA_NONE                   (_WTIMER_CC_CTRL_COFOA_NONE << 10)               /**< Shifted mode NONE for WTIMER_CC_CTRL */
1778 #define WTIMER_CC_CTRL_COFOA_TOGGLE                 (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10)             /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
1779 #define WTIMER_CC_CTRL_COFOA_CLEAR                  (_WTIMER_CC_CTRL_COFOA_CLEAR << 10)              /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
1780 #define WTIMER_CC_CTRL_COFOA_SET                    (_WTIMER_CC_CTRL_COFOA_SET << 10)                /**< Shifted mode SET for WTIMER_CC_CTRL */
1781 #define _WTIMER_CC_CTRL_CUFOA_SHIFT                 12                                               /**< Shift value for TIMER_CUFOA */
1782 #define _WTIMER_CC_CTRL_CUFOA_MASK                  0x3000UL                                         /**< Bit mask for TIMER_CUFOA */
1783 #define _WTIMER_CC_CTRL_CUFOA_DEFAULT               0x00000000UL                                     /**< Mode DEFAULT for WTIMER_CC_CTRL */
1784 #define _WTIMER_CC_CTRL_CUFOA_NONE                  0x00000000UL                                     /**< Mode NONE for WTIMER_CC_CTRL */
1785 #define _WTIMER_CC_CTRL_CUFOA_TOGGLE                0x00000001UL                                     /**< Mode TOGGLE for WTIMER_CC_CTRL */
1786 #define _WTIMER_CC_CTRL_CUFOA_CLEAR                 0x00000002UL                                     /**< Mode CLEAR for WTIMER_CC_CTRL */
1787 #define _WTIMER_CC_CTRL_CUFOA_SET                   0x00000003UL                                     /**< Mode SET for WTIMER_CC_CTRL */
1788 #define WTIMER_CC_CTRL_CUFOA_DEFAULT                (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12)            /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
1789 #define WTIMER_CC_CTRL_CUFOA_NONE                   (_WTIMER_CC_CTRL_CUFOA_NONE << 12)               /**< Shifted mode NONE for WTIMER_CC_CTRL */
1790 #define WTIMER_CC_CTRL_CUFOA_TOGGLE                 (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12)             /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */
1791 #define WTIMER_CC_CTRL_CUFOA_CLEAR                  (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12)              /**< Shifted mode CLEAR for WTIMER_CC_CTRL */
1792 #define WTIMER_CC_CTRL_CUFOA_SET                    (_WTIMER_CC_CTRL_CUFOA_SET << 12)                /**< Shifted mode SET for WTIMER_CC_CTRL */
1793 #define _WTIMER_CC_CTRL_PRSSEL_SHIFT                16                                               /**< Shift value for TIMER_PRSSEL */
1794 #define _WTIMER_CC_CTRL_PRSSEL_MASK                 0xF0000UL                                        /**< Bit mask for TIMER_PRSSEL */
1795 #define _WTIMER_CC_CTRL_PRSSEL_DEFAULT              0x00000000UL                                     /**< Mode DEFAULT for WTIMER_CC_CTRL */
1796 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH0               0x00000000UL                                     /**< Mode PRSCH0 for WTIMER_CC_CTRL */
1797 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH1               0x00000001UL                                     /**< Mode PRSCH1 for WTIMER_CC_CTRL */
1798 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH2               0x00000002UL                                     /**< Mode PRSCH2 for WTIMER_CC_CTRL */
1799 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH3               0x00000003UL                                     /**< Mode PRSCH3 for WTIMER_CC_CTRL */
1800 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH4               0x00000004UL                                     /**< Mode PRSCH4 for WTIMER_CC_CTRL */
1801 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH5               0x00000005UL                                     /**< Mode PRSCH5 for WTIMER_CC_CTRL */
1802 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH6               0x00000006UL                                     /**< Mode PRSCH6 for WTIMER_CC_CTRL */
1803 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH7               0x00000007UL                                     /**< Mode PRSCH7 for WTIMER_CC_CTRL */
1804 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH8               0x00000008UL                                     /**< Mode PRSCH8 for WTIMER_CC_CTRL */
1805 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH9               0x00000009UL                                     /**< Mode PRSCH9 for WTIMER_CC_CTRL */
1806 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH10              0x0000000AUL                                     /**< Mode PRSCH10 for WTIMER_CC_CTRL */
1807 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH11              0x0000000BUL                                     /**< Mode PRSCH11 for WTIMER_CC_CTRL */
1808 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH12              0x0000000CUL                                     /**< Mode PRSCH12 for WTIMER_CC_CTRL */
1809 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH13              0x0000000DUL                                     /**< Mode PRSCH13 for WTIMER_CC_CTRL */
1810 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH14              0x0000000EUL                                     /**< Mode PRSCH14 for WTIMER_CC_CTRL */
1811 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH15              0x0000000FUL                                     /**< Mode PRSCH15 for WTIMER_CC_CTRL */
1812 #define WTIMER_CC_CTRL_PRSSEL_DEFAULT               (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16)           /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
1813 #define WTIMER_CC_CTRL_PRSSEL_PRSCH0                (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16)            /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */
1814 #define WTIMER_CC_CTRL_PRSSEL_PRSCH1                (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16)            /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */
1815 #define WTIMER_CC_CTRL_PRSSEL_PRSCH2                (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16)            /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */
1816 #define WTIMER_CC_CTRL_PRSSEL_PRSCH3                (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16)            /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */
1817 #define WTIMER_CC_CTRL_PRSSEL_PRSCH4                (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16)            /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */
1818 #define WTIMER_CC_CTRL_PRSSEL_PRSCH5                (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16)            /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */
1819 #define WTIMER_CC_CTRL_PRSSEL_PRSCH6                (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16)            /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */
1820 #define WTIMER_CC_CTRL_PRSSEL_PRSCH7                (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16)            /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */
1821 #define WTIMER_CC_CTRL_PRSSEL_PRSCH8                (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16)            /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */
1822 #define WTIMER_CC_CTRL_PRSSEL_PRSCH9                (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16)            /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */
1823 #define WTIMER_CC_CTRL_PRSSEL_PRSCH10               (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16)           /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */
1824 #define WTIMER_CC_CTRL_PRSSEL_PRSCH11               (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16)           /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */
1825 #define WTIMER_CC_CTRL_PRSSEL_PRSCH12               (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16)           /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */
1826 #define WTIMER_CC_CTRL_PRSSEL_PRSCH13               (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16)           /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */
1827 #define WTIMER_CC_CTRL_PRSSEL_PRSCH14               (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16)           /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */
1828 #define WTIMER_CC_CTRL_PRSSEL_PRSCH15               (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16)           /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */
1829 #define _WTIMER_CC_CTRL_ICEDGE_SHIFT                24                                               /**< Shift value for TIMER_ICEDGE */
1830 #define _WTIMER_CC_CTRL_ICEDGE_MASK                 0x3000000UL                                      /**< Bit mask for TIMER_ICEDGE */
1831 #define _WTIMER_CC_CTRL_ICEDGE_DEFAULT              0x00000000UL                                     /**< Mode DEFAULT for WTIMER_CC_CTRL */
1832 #define _WTIMER_CC_CTRL_ICEDGE_RISING               0x00000000UL                                     /**< Mode RISING for WTIMER_CC_CTRL */
1833 #define _WTIMER_CC_CTRL_ICEDGE_FALLING              0x00000001UL                                     /**< Mode FALLING for WTIMER_CC_CTRL */
1834 #define _WTIMER_CC_CTRL_ICEDGE_BOTH                 0x00000002UL                                     /**< Mode BOTH for WTIMER_CC_CTRL */
1835 #define _WTIMER_CC_CTRL_ICEDGE_NONE                 0x00000003UL                                     /**< Mode NONE for WTIMER_CC_CTRL */
1836 #define WTIMER_CC_CTRL_ICEDGE_DEFAULT               (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24)           /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
1837 #define WTIMER_CC_CTRL_ICEDGE_RISING                (_WTIMER_CC_CTRL_ICEDGE_RISING << 24)            /**< Shifted mode RISING for WTIMER_CC_CTRL */
1838 #define WTIMER_CC_CTRL_ICEDGE_FALLING               (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24)           /**< Shifted mode FALLING for WTIMER_CC_CTRL */
1839 #define WTIMER_CC_CTRL_ICEDGE_BOTH                  (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24)              /**< Shifted mode BOTH for WTIMER_CC_CTRL */
1840 #define WTIMER_CC_CTRL_ICEDGE_NONE                  (_WTIMER_CC_CTRL_ICEDGE_NONE << 24)              /**< Shifted mode NONE for WTIMER_CC_CTRL */
1841 #define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT              26                                               /**< Shift value for TIMER_ICEVCTRL */
1842 #define _WTIMER_CC_CTRL_ICEVCTRL_MASK               0xC000000UL                                      /**< Bit mask for TIMER_ICEVCTRL */
1843 #define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT            0x00000000UL                                     /**< Mode DEFAULT for WTIMER_CC_CTRL */
1844 #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE          0x00000000UL                                     /**< Mode EVERYEDGE for WTIMER_CC_CTRL */
1845 #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE    0x00000001UL                                     /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */
1846 #define _WTIMER_CC_CTRL_ICEVCTRL_RISING             0x00000002UL                                     /**< Mode RISING for WTIMER_CC_CTRL */
1847 #define _WTIMER_CC_CTRL_ICEVCTRL_FALLING            0x00000003UL                                     /**< Mode FALLING for WTIMER_CC_CTRL */
1848 #define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT             (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26)         /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
1849 #define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE           (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26)       /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */
1850 #define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE     (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */
1851 #define WTIMER_CC_CTRL_ICEVCTRL_RISING              (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26)          /**< Shifted mode RISING for WTIMER_CC_CTRL */
1852 #define WTIMER_CC_CTRL_ICEVCTRL_FALLING             (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26)         /**< Shifted mode FALLING for WTIMER_CC_CTRL */
1853 #define WTIMER_CC_CTRL_PRSCONF                      (0x1UL << 28)                                    /**< PRS Configuration */
1854 #define _WTIMER_CC_CTRL_PRSCONF_SHIFT               28                                               /**< Shift value for TIMER_PRSCONF */
1855 #define _WTIMER_CC_CTRL_PRSCONF_MASK                0x10000000UL                                     /**< Bit mask for TIMER_PRSCONF */
1856 #define _WTIMER_CC_CTRL_PRSCONF_DEFAULT             0x00000000UL                                     /**< Mode DEFAULT for WTIMER_CC_CTRL */
1857 #define _WTIMER_CC_CTRL_PRSCONF_PULSE               0x00000000UL                                     /**< Mode PULSE for WTIMER_CC_CTRL */
1858 #define _WTIMER_CC_CTRL_PRSCONF_LEVEL               0x00000001UL                                     /**< Mode LEVEL for WTIMER_CC_CTRL */
1859 #define WTIMER_CC_CTRL_PRSCONF_DEFAULT              (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28)          /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
1860 #define WTIMER_CC_CTRL_PRSCONF_PULSE                (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28)            /**< Shifted mode PULSE for WTIMER_CC_CTRL */
1861 #define WTIMER_CC_CTRL_PRSCONF_LEVEL                (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28)            /**< Shifted mode LEVEL for WTIMER_CC_CTRL */
1862 #define WTIMER_CC_CTRL_INSEL                        (0x1UL << 29)                                    /**< Input Selection */
1863 #define _WTIMER_CC_CTRL_INSEL_SHIFT                 29                                               /**< Shift value for TIMER_INSEL */
1864 #define _WTIMER_CC_CTRL_INSEL_MASK                  0x20000000UL                                     /**< Bit mask for TIMER_INSEL */
1865 #define _WTIMER_CC_CTRL_INSEL_DEFAULT               0x00000000UL                                     /**< Mode DEFAULT for WTIMER_CC_CTRL */
1866 #define _WTIMER_CC_CTRL_INSEL_PIN                   0x00000000UL                                     /**< Mode PIN for WTIMER_CC_CTRL */
1867 #define _WTIMER_CC_CTRL_INSEL_PRS                   0x00000001UL                                     /**< Mode PRS for WTIMER_CC_CTRL */
1868 #define WTIMER_CC_CTRL_INSEL_DEFAULT                (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29)            /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
1869 #define WTIMER_CC_CTRL_INSEL_PIN                    (_WTIMER_CC_CTRL_INSEL_PIN << 29)                /**< Shifted mode PIN for WTIMER_CC_CTRL */
1870 #define WTIMER_CC_CTRL_INSEL_PRS                    (_WTIMER_CC_CTRL_INSEL_PRS << 29)                /**< Shifted mode PRS for WTIMER_CC_CTRL */
1871 #define WTIMER_CC_CTRL_FILT                         (0x1UL << 30)                                    /**< Digital Filter */
1872 #define _WTIMER_CC_CTRL_FILT_SHIFT                  30                                               /**< Shift value for TIMER_FILT */
1873 #define _WTIMER_CC_CTRL_FILT_MASK                   0x40000000UL                                     /**< Bit mask for TIMER_FILT */
1874 #define _WTIMER_CC_CTRL_FILT_DEFAULT                0x00000000UL                                     /**< Mode DEFAULT for WTIMER_CC_CTRL */
1875 #define _WTIMER_CC_CTRL_FILT_DISABLE                0x00000000UL                                     /**< Mode DISABLE for WTIMER_CC_CTRL */
1876 #define _WTIMER_CC_CTRL_FILT_ENABLE                 0x00000001UL                                     /**< Mode ENABLE for WTIMER_CC_CTRL */
1877 #define WTIMER_CC_CTRL_FILT_DEFAULT                 (_WTIMER_CC_CTRL_FILT_DEFAULT << 30)             /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */
1878 #define WTIMER_CC_CTRL_FILT_DISABLE                 (_WTIMER_CC_CTRL_FILT_DISABLE << 30)             /**< Shifted mode DISABLE for WTIMER_CC_CTRL */
1879 #define WTIMER_CC_CTRL_FILT_ENABLE                  (_WTIMER_CC_CTRL_FILT_ENABLE << 30)              /**< Shifted mode ENABLE for WTIMER_CC_CTRL */
1880 
1881 /* Bit fields for WTIMER CC_CCV */
1882 #define _WTIMER_CC_CCV_RESETVALUE                   0x00000000UL                      /**< Default value for WTIMER_CC_CCV */
1883 #define _WTIMER_CC_CCV_MASK                         0xFFFFFFFFUL                      /**< Mask for WTIMER_CC_CCV */
1884 #define _WTIMER_CC_CCV_CCV_SHIFT                    0                                 /**< Shift value for TIMER_CCV */
1885 #define _WTIMER_CC_CCV_CCV_MASK                     0xFFFFFFFFUL                      /**< Bit mask for TIMER_CCV */
1886 #define _WTIMER_CC_CCV_CCV_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for WTIMER_CC_CCV */
1887 #define WTIMER_CC_CCV_CCV_DEFAULT                   (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */
1888 
1889 /* Bit fields for WTIMER CC_CCVP */
1890 #define _WTIMER_CC_CCVP_RESETVALUE                  0x00000000UL                        /**< Default value for WTIMER_CC_CCVP */
1891 #define _WTIMER_CC_CCVP_MASK                        0xFFFFFFFFUL                        /**< Mask for WTIMER_CC_CCVP */
1892 #define _WTIMER_CC_CCVP_CCVP_SHIFT                  0                                   /**< Shift value for TIMER_CCVP */
1893 #define _WTIMER_CC_CCVP_CCVP_MASK                   0xFFFFFFFFUL                        /**< Bit mask for TIMER_CCVP */
1894 #define _WTIMER_CC_CCVP_CCVP_DEFAULT                0x00000000UL                        /**< Mode DEFAULT for WTIMER_CC_CCVP */
1895 #define WTIMER_CC_CCVP_CCVP_DEFAULT                 (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */
1896 
1897 /* Bit fields for WTIMER CC_CCVB */
1898 #define _WTIMER_CC_CCVB_RESETVALUE                  0x00000000UL                        /**< Default value for WTIMER_CC_CCVB */
1899 #define _WTIMER_CC_CCVB_MASK                        0xFFFFFFFFUL                        /**< Mask for WTIMER_CC_CCVB */
1900 #define _WTIMER_CC_CCVB_CCVB_SHIFT                  0                                   /**< Shift value for TIMER_CCVB */
1901 #define _WTIMER_CC_CCVB_CCVB_MASK                   0xFFFFFFFFUL                        /**< Bit mask for TIMER_CCVB */
1902 #define _WTIMER_CC_CCVB_CCVB_DEFAULT                0x00000000UL                        /**< Mode DEFAULT for WTIMER_CC_CCVB */
1903 #define WTIMER_CC_CCVB_CCVB_DEFAULT                 (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */
1904 
1905 /* Bit fields for WTIMER DTCTRL */
1906 #define _WTIMER_DTCTRL_RESETVALUE                   0x00000000UL                           /**< Default value for WTIMER_DTCTRL */
1907 #define _WTIMER_DTCTRL_MASK                         0x010006FFUL                           /**< Mask for WTIMER_DTCTRL */
1908 #define WTIMER_DTCTRL_DTEN                          (0x1UL << 0)                           /**< DTI Enable */
1909 #define _WTIMER_DTCTRL_DTEN_SHIFT                   0                                      /**< Shift value for TIMER_DTEN */
1910 #define _WTIMER_DTCTRL_DTEN_MASK                    0x1UL                                  /**< Bit mask for TIMER_DTEN */
1911 #define _WTIMER_DTCTRL_DTEN_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for WTIMER_DTCTRL */
1912 #define WTIMER_DTCTRL_DTEN_DEFAULT                  (_WTIMER_DTCTRL_DTEN_DEFAULT << 0)     /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
1913 #define WTIMER_DTCTRL_DTDAS                         (0x1UL << 1)                           /**< DTI Automatic Start-up Functionality */
1914 #define _WTIMER_DTCTRL_DTDAS_SHIFT                  1                                      /**< Shift value for TIMER_DTDAS */
1915 #define _WTIMER_DTCTRL_DTDAS_MASK                   0x2UL                                  /**< Bit mask for TIMER_DTDAS */
1916 #define _WTIMER_DTCTRL_DTDAS_DEFAULT                0x00000000UL                           /**< Mode DEFAULT for WTIMER_DTCTRL */
1917 #define _WTIMER_DTCTRL_DTDAS_NORESTART              0x00000000UL                           /**< Mode NORESTART for WTIMER_DTCTRL */
1918 #define _WTIMER_DTCTRL_DTDAS_RESTART                0x00000001UL                           /**< Mode RESTART for WTIMER_DTCTRL */
1919 #define WTIMER_DTCTRL_DTDAS_DEFAULT                 (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1)    /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
1920 #define WTIMER_DTCTRL_DTDAS_NORESTART               (_WTIMER_DTCTRL_DTDAS_NORESTART << 1)  /**< Shifted mode NORESTART for WTIMER_DTCTRL */
1921 #define WTIMER_DTCTRL_DTDAS_RESTART                 (_WTIMER_DTCTRL_DTDAS_RESTART << 1)    /**< Shifted mode RESTART for WTIMER_DTCTRL */
1922 #define WTIMER_DTCTRL_DTIPOL                        (0x1UL << 2)                           /**< DTI Inactive Polarity */
1923 #define _WTIMER_DTCTRL_DTIPOL_SHIFT                 2                                      /**< Shift value for TIMER_DTIPOL */
1924 #define _WTIMER_DTCTRL_DTIPOL_MASK                  0x4UL                                  /**< Bit mask for TIMER_DTIPOL */
1925 #define _WTIMER_DTCTRL_DTIPOL_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for WTIMER_DTCTRL */
1926 #define WTIMER_DTCTRL_DTIPOL_DEFAULT                (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2)   /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
1927 #define WTIMER_DTCTRL_DTCINV                        (0x1UL << 3)                           /**< DTI Complementary Output Invert */
1928 #define _WTIMER_DTCTRL_DTCINV_SHIFT                 3                                      /**< Shift value for TIMER_DTCINV */
1929 #define _WTIMER_DTCTRL_DTCINV_MASK                  0x8UL                                  /**< Bit mask for TIMER_DTCINV */
1930 #define _WTIMER_DTCTRL_DTCINV_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for WTIMER_DTCTRL */
1931 #define WTIMER_DTCTRL_DTCINV_DEFAULT                (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3)   /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
1932 #define _WTIMER_DTCTRL_DTPRSSEL_SHIFT               4                                      /**< Shift value for TIMER_DTPRSSEL */
1933 #define _WTIMER_DTCTRL_DTPRSSEL_MASK                0xF0UL                                 /**< Bit mask for TIMER_DTPRSSEL */
1934 #define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for WTIMER_DTCTRL */
1935 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0              0x00000000UL                           /**< Mode PRSCH0 for WTIMER_DTCTRL */
1936 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1              0x00000001UL                           /**< Mode PRSCH1 for WTIMER_DTCTRL */
1937 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2              0x00000002UL                           /**< Mode PRSCH2 for WTIMER_DTCTRL */
1938 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3              0x00000003UL                           /**< Mode PRSCH3 for WTIMER_DTCTRL */
1939 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4              0x00000004UL                           /**< Mode PRSCH4 for WTIMER_DTCTRL */
1940 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5              0x00000005UL                           /**< Mode PRSCH5 for WTIMER_DTCTRL */
1941 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6              0x00000006UL                           /**< Mode PRSCH6 for WTIMER_DTCTRL */
1942 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7              0x00000007UL                           /**< Mode PRSCH7 for WTIMER_DTCTRL */
1943 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8              0x00000008UL                           /**< Mode PRSCH8 for WTIMER_DTCTRL */
1944 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9              0x00000009UL                           /**< Mode PRSCH9 for WTIMER_DTCTRL */
1945 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10             0x0000000AUL                           /**< Mode PRSCH10 for WTIMER_DTCTRL */
1946 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11             0x0000000BUL                           /**< Mode PRSCH11 for WTIMER_DTCTRL */
1947 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12             0x0000000CUL                           /**< Mode PRSCH12 for WTIMER_DTCTRL */
1948 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13             0x0000000DUL                           /**< Mode PRSCH13 for WTIMER_DTCTRL */
1949 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14             0x0000000EUL                           /**< Mode PRSCH14 for WTIMER_DTCTRL */
1950 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15             0x0000000FUL                           /**< Mode PRSCH15 for WTIMER_DTCTRL */
1951 #define WTIMER_DTCTRL_DTPRSSEL_DEFAULT              (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
1952 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH0               (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4)  /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */
1953 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH1               (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4)  /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */
1954 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH2               (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4)  /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */
1955 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH3               (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4)  /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */
1956 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH4               (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4)  /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */
1957 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH5               (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4)  /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */
1958 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH6               (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4)  /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */
1959 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH7               (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4)  /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */
1960 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH8               (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4)  /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */
1961 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH9               (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4)  /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */
1962 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH10              (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */
1963 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH11              (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */
1964 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH12              (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */
1965 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH13              (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */
1966 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH14              (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */
1967 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH15              (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */
1968 #define WTIMER_DTCTRL_DTAR                          (0x1UL << 9)                           /**< DTI Always Run */
1969 #define _WTIMER_DTCTRL_DTAR_SHIFT                   9                                      /**< Shift value for TIMER_DTAR */
1970 #define _WTIMER_DTCTRL_DTAR_MASK                    0x200UL                                /**< Bit mask for TIMER_DTAR */
1971 #define _WTIMER_DTCTRL_DTAR_DEFAULT                 0x00000000UL                           /**< Mode DEFAULT for WTIMER_DTCTRL */
1972 #define WTIMER_DTCTRL_DTAR_DEFAULT                  (_WTIMER_DTCTRL_DTAR_DEFAULT << 9)     /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
1973 #define WTIMER_DTCTRL_DTFATS                        (0x1UL << 10)                          /**< DTI Fault Action on Timer Stop */
1974 #define _WTIMER_DTCTRL_DTFATS_SHIFT                 10                                     /**< Shift value for TIMER_DTFATS */
1975 #define _WTIMER_DTCTRL_DTFATS_MASK                  0x400UL                                /**< Bit mask for TIMER_DTFATS */
1976 #define _WTIMER_DTCTRL_DTFATS_DEFAULT               0x00000000UL                           /**< Mode DEFAULT for WTIMER_DTCTRL */
1977 #define WTIMER_DTCTRL_DTFATS_DEFAULT                (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10)  /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
1978 #define WTIMER_DTCTRL_DTPRSEN                       (0x1UL << 24)                          /**< DTI PRS Source Enable */
1979 #define _WTIMER_DTCTRL_DTPRSEN_SHIFT                24                                     /**< Shift value for TIMER_DTPRSEN */
1980 #define _WTIMER_DTCTRL_DTPRSEN_MASK                 0x1000000UL                            /**< Bit mask for TIMER_DTPRSEN */
1981 #define _WTIMER_DTCTRL_DTPRSEN_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for WTIMER_DTCTRL */
1982 #define WTIMER_DTCTRL_DTPRSEN_DEFAULT               (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */
1983 
1984 /* Bit fields for WTIMER DTTIME */
1985 #define _WTIMER_DTTIME_RESETVALUE                   0x00000000UL                           /**< Default value for WTIMER_DTTIME */
1986 #define _WTIMER_DTTIME_MASK                         0x003F3F0FUL                           /**< Mask for WTIMER_DTTIME */
1987 #define _WTIMER_DTTIME_DTPRESC_SHIFT                0                                      /**< Shift value for TIMER_DTPRESC */
1988 #define _WTIMER_DTTIME_DTPRESC_MASK                 0xFUL                                  /**< Bit mask for TIMER_DTPRESC */
1989 #define _WTIMER_DTTIME_DTPRESC_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for WTIMER_DTTIME */
1990 #define _WTIMER_DTTIME_DTPRESC_DIV1                 0x00000000UL                           /**< Mode DIV1 for WTIMER_DTTIME */
1991 #define _WTIMER_DTTIME_DTPRESC_DIV2                 0x00000001UL                           /**< Mode DIV2 for WTIMER_DTTIME */
1992 #define _WTIMER_DTTIME_DTPRESC_DIV4                 0x00000002UL                           /**< Mode DIV4 for WTIMER_DTTIME */
1993 #define _WTIMER_DTTIME_DTPRESC_DIV8                 0x00000003UL                           /**< Mode DIV8 for WTIMER_DTTIME */
1994 #define _WTIMER_DTTIME_DTPRESC_DIV16                0x00000004UL                           /**< Mode DIV16 for WTIMER_DTTIME */
1995 #define _WTIMER_DTTIME_DTPRESC_DIV32                0x00000005UL                           /**< Mode DIV32 for WTIMER_DTTIME */
1996 #define _WTIMER_DTTIME_DTPRESC_DIV64                0x00000006UL                           /**< Mode DIV64 for WTIMER_DTTIME */
1997 #define _WTIMER_DTTIME_DTPRESC_DIV128               0x00000007UL                           /**< Mode DIV128 for WTIMER_DTTIME */
1998 #define _WTIMER_DTTIME_DTPRESC_DIV256               0x00000008UL                           /**< Mode DIV256 for WTIMER_DTTIME */
1999 #define _WTIMER_DTTIME_DTPRESC_DIV512               0x00000009UL                           /**< Mode DIV512 for WTIMER_DTTIME */
2000 #define _WTIMER_DTTIME_DTPRESC_DIV1024              0x0000000AUL                           /**< Mode DIV1024 for WTIMER_DTTIME */
2001 #define WTIMER_DTTIME_DTPRESC_DEFAULT               (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0)  /**< Shifted mode DEFAULT for WTIMER_DTTIME */
2002 #define WTIMER_DTTIME_DTPRESC_DIV1                  (_WTIMER_DTTIME_DTPRESC_DIV1 << 0)     /**< Shifted mode DIV1 for WTIMER_DTTIME */
2003 #define WTIMER_DTTIME_DTPRESC_DIV2                  (_WTIMER_DTTIME_DTPRESC_DIV2 << 0)     /**< Shifted mode DIV2 for WTIMER_DTTIME */
2004 #define WTIMER_DTTIME_DTPRESC_DIV4                  (_WTIMER_DTTIME_DTPRESC_DIV4 << 0)     /**< Shifted mode DIV4 for WTIMER_DTTIME */
2005 #define WTIMER_DTTIME_DTPRESC_DIV8                  (_WTIMER_DTTIME_DTPRESC_DIV8 << 0)     /**< Shifted mode DIV8 for WTIMER_DTTIME */
2006 #define WTIMER_DTTIME_DTPRESC_DIV16                 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0)    /**< Shifted mode DIV16 for WTIMER_DTTIME */
2007 #define WTIMER_DTTIME_DTPRESC_DIV32                 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0)    /**< Shifted mode DIV32 for WTIMER_DTTIME */
2008 #define WTIMER_DTTIME_DTPRESC_DIV64                 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0)    /**< Shifted mode DIV64 for WTIMER_DTTIME */
2009 #define WTIMER_DTTIME_DTPRESC_DIV128                (_WTIMER_DTTIME_DTPRESC_DIV128 << 0)   /**< Shifted mode DIV128 for WTIMER_DTTIME */
2010 #define WTIMER_DTTIME_DTPRESC_DIV256                (_WTIMER_DTTIME_DTPRESC_DIV256 << 0)   /**< Shifted mode DIV256 for WTIMER_DTTIME */
2011 #define WTIMER_DTTIME_DTPRESC_DIV512                (_WTIMER_DTTIME_DTPRESC_DIV512 << 0)   /**< Shifted mode DIV512 for WTIMER_DTTIME */
2012 #define WTIMER_DTTIME_DTPRESC_DIV1024               (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0)  /**< Shifted mode DIV1024 for WTIMER_DTTIME */
2013 #define _WTIMER_DTTIME_DTRISET_SHIFT                8                                      /**< Shift value for TIMER_DTRISET */
2014 #define _WTIMER_DTTIME_DTRISET_MASK                 0x3F00UL                               /**< Bit mask for TIMER_DTRISET */
2015 #define _WTIMER_DTTIME_DTRISET_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for WTIMER_DTTIME */
2016 #define WTIMER_DTTIME_DTRISET_DEFAULT               (_WTIMER_DTTIME_DTRISET_DEFAULT << 8)  /**< Shifted mode DEFAULT for WTIMER_DTTIME */
2017 #define _WTIMER_DTTIME_DTFALLT_SHIFT                16                                     /**< Shift value for TIMER_DTFALLT */
2018 #define _WTIMER_DTTIME_DTFALLT_MASK                 0x3F0000UL                             /**< Bit mask for TIMER_DTFALLT */
2019 #define _WTIMER_DTTIME_DTFALLT_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for WTIMER_DTTIME */
2020 #define WTIMER_DTTIME_DTFALLT_DEFAULT               (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */
2021 
2022 /* Bit fields for WTIMER DTFC */
2023 #define _WTIMER_DTFC_RESETVALUE                     0x00000000UL                             /**< Default value for WTIMER_DTFC */
2024 #define _WTIMER_DTFC_MASK                           0x0F030F0FUL                             /**< Mask for WTIMER_DTFC */
2025 #define _WTIMER_DTFC_DTPRS0FSEL_SHIFT               0                                        /**< Shift value for TIMER_DTPRS0FSEL */
2026 #define _WTIMER_DTFC_DTPRS0FSEL_MASK                0xFUL                                    /**< Bit mask for TIMER_DTPRS0FSEL */
2027 #define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for WTIMER_DTFC */
2028 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0              0x00000000UL                             /**< Mode PRSCH0 for WTIMER_DTFC */
2029 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1              0x00000001UL                             /**< Mode PRSCH1 for WTIMER_DTFC */
2030 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2              0x00000002UL                             /**< Mode PRSCH2 for WTIMER_DTFC */
2031 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3              0x00000003UL                             /**< Mode PRSCH3 for WTIMER_DTFC */
2032 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4              0x00000004UL                             /**< Mode PRSCH4 for WTIMER_DTFC */
2033 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5              0x00000005UL                             /**< Mode PRSCH5 for WTIMER_DTFC */
2034 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6              0x00000006UL                             /**< Mode PRSCH6 for WTIMER_DTFC */
2035 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7              0x00000007UL                             /**< Mode PRSCH7 for WTIMER_DTFC */
2036 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8              0x00000008UL                             /**< Mode PRSCH8 for WTIMER_DTFC */
2037 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9              0x00000009UL                             /**< Mode PRSCH9 for WTIMER_DTFC */
2038 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10             0x0000000AUL                             /**< Mode PRSCH10 for WTIMER_DTFC */
2039 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11             0x0000000BUL                             /**< Mode PRSCH11 for WTIMER_DTFC */
2040 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12             0x0000000CUL                             /**< Mode PRSCH12 for WTIMER_DTFC */
2041 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13             0x0000000DUL                             /**< Mode PRSCH13 for WTIMER_DTFC */
2042 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14             0x0000000EUL                             /**< Mode PRSCH14 for WTIMER_DTFC */
2043 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15             0x0000000FUL                             /**< Mode PRSCH15 for WTIMER_DTFC */
2044 #define WTIMER_DTFC_DTPRS0FSEL_DEFAULT              (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0)   /**< Shifted mode DEFAULT for WTIMER_DTFC */
2045 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH0               (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0)    /**< Shifted mode PRSCH0 for WTIMER_DTFC */
2046 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH1               (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0)    /**< Shifted mode PRSCH1 for WTIMER_DTFC */
2047 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH2               (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0)    /**< Shifted mode PRSCH2 for WTIMER_DTFC */
2048 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH3               (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0)    /**< Shifted mode PRSCH3 for WTIMER_DTFC */
2049 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH4               (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0)    /**< Shifted mode PRSCH4 for WTIMER_DTFC */
2050 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH5               (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0)    /**< Shifted mode PRSCH5 for WTIMER_DTFC */
2051 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH6               (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0)    /**< Shifted mode PRSCH6 for WTIMER_DTFC */
2052 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH7               (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0)    /**< Shifted mode PRSCH7 for WTIMER_DTFC */
2053 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH8               (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0)    /**< Shifted mode PRSCH8 for WTIMER_DTFC */
2054 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH9               (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0)    /**< Shifted mode PRSCH9 for WTIMER_DTFC */
2055 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH10              (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0)   /**< Shifted mode PRSCH10 for WTIMER_DTFC */
2056 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH11              (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0)   /**< Shifted mode PRSCH11 for WTIMER_DTFC */
2057 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH12              (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0)   /**< Shifted mode PRSCH12 for WTIMER_DTFC */
2058 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH13              (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0)   /**< Shifted mode PRSCH13 for WTIMER_DTFC */
2059 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH14              (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0)   /**< Shifted mode PRSCH14 for WTIMER_DTFC */
2060 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH15              (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0)   /**< Shifted mode PRSCH15 for WTIMER_DTFC */
2061 #define _WTIMER_DTFC_DTPRS1FSEL_SHIFT               8                                        /**< Shift value for TIMER_DTPRS1FSEL */
2062 #define _WTIMER_DTFC_DTPRS1FSEL_MASK                0xF00UL                                  /**< Bit mask for TIMER_DTPRS1FSEL */
2063 #define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for WTIMER_DTFC */
2064 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0              0x00000000UL                             /**< Mode PRSCH0 for WTIMER_DTFC */
2065 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1              0x00000001UL                             /**< Mode PRSCH1 for WTIMER_DTFC */
2066 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2              0x00000002UL                             /**< Mode PRSCH2 for WTIMER_DTFC */
2067 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3              0x00000003UL                             /**< Mode PRSCH3 for WTIMER_DTFC */
2068 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4              0x00000004UL                             /**< Mode PRSCH4 for WTIMER_DTFC */
2069 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5              0x00000005UL                             /**< Mode PRSCH5 for WTIMER_DTFC */
2070 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6              0x00000006UL                             /**< Mode PRSCH6 for WTIMER_DTFC */
2071 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7              0x00000007UL                             /**< Mode PRSCH7 for WTIMER_DTFC */
2072 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8              0x00000008UL                             /**< Mode PRSCH8 for WTIMER_DTFC */
2073 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9              0x00000009UL                             /**< Mode PRSCH9 for WTIMER_DTFC */
2074 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10             0x0000000AUL                             /**< Mode PRSCH10 for WTIMER_DTFC */
2075 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11             0x0000000BUL                             /**< Mode PRSCH11 for WTIMER_DTFC */
2076 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12             0x0000000CUL                             /**< Mode PRSCH12 for WTIMER_DTFC */
2077 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13             0x0000000DUL                             /**< Mode PRSCH13 for WTIMER_DTFC */
2078 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14             0x0000000EUL                             /**< Mode PRSCH14 for WTIMER_DTFC */
2079 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15             0x0000000FUL                             /**< Mode PRSCH15 for WTIMER_DTFC */
2080 #define WTIMER_DTFC_DTPRS1FSEL_DEFAULT              (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8)   /**< Shifted mode DEFAULT for WTIMER_DTFC */
2081 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH0               (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8)    /**< Shifted mode PRSCH0 for WTIMER_DTFC */
2082 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH1               (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8)    /**< Shifted mode PRSCH1 for WTIMER_DTFC */
2083 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH2               (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8)    /**< Shifted mode PRSCH2 for WTIMER_DTFC */
2084 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH3               (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8)    /**< Shifted mode PRSCH3 for WTIMER_DTFC */
2085 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH4               (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8)    /**< Shifted mode PRSCH4 for WTIMER_DTFC */
2086 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH5               (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8)    /**< Shifted mode PRSCH5 for WTIMER_DTFC */
2087 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH6               (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8)    /**< Shifted mode PRSCH6 for WTIMER_DTFC */
2088 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH7               (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8)    /**< Shifted mode PRSCH7 for WTIMER_DTFC */
2089 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH8               (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8)    /**< Shifted mode PRSCH8 for WTIMER_DTFC */
2090 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH9               (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8)    /**< Shifted mode PRSCH9 for WTIMER_DTFC */
2091 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH10              (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8)   /**< Shifted mode PRSCH10 for WTIMER_DTFC */
2092 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH11              (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8)   /**< Shifted mode PRSCH11 for WTIMER_DTFC */
2093 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH12              (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8)   /**< Shifted mode PRSCH12 for WTIMER_DTFC */
2094 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH13              (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8)   /**< Shifted mode PRSCH13 for WTIMER_DTFC */
2095 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH14              (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8)   /**< Shifted mode PRSCH14 for WTIMER_DTFC */
2096 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH15              (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8)   /**< Shifted mode PRSCH15 for WTIMER_DTFC */
2097 #define _WTIMER_DTFC_DTFA_SHIFT                     16                                       /**< Shift value for TIMER_DTFA */
2098 #define _WTIMER_DTFC_DTFA_MASK                      0x30000UL                                /**< Bit mask for TIMER_DTFA */
2099 #define _WTIMER_DTFC_DTFA_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for WTIMER_DTFC */
2100 #define _WTIMER_DTFC_DTFA_NONE                      0x00000000UL                             /**< Mode NONE for WTIMER_DTFC */
2101 #define _WTIMER_DTFC_DTFA_INACTIVE                  0x00000001UL                             /**< Mode INACTIVE for WTIMER_DTFC */
2102 #define _WTIMER_DTFC_DTFA_CLEAR                     0x00000002UL                             /**< Mode CLEAR for WTIMER_DTFC */
2103 #define _WTIMER_DTFC_DTFA_TRISTATE                  0x00000003UL                             /**< Mode TRISTATE for WTIMER_DTFC */
2104 #define WTIMER_DTFC_DTFA_DEFAULT                    (_WTIMER_DTFC_DTFA_DEFAULT << 16)        /**< Shifted mode DEFAULT for WTIMER_DTFC */
2105 #define WTIMER_DTFC_DTFA_NONE                       (_WTIMER_DTFC_DTFA_NONE << 16)           /**< Shifted mode NONE for WTIMER_DTFC */
2106 #define WTIMER_DTFC_DTFA_INACTIVE                   (_WTIMER_DTFC_DTFA_INACTIVE << 16)       /**< Shifted mode INACTIVE for WTIMER_DTFC */
2107 #define WTIMER_DTFC_DTFA_CLEAR                      (_WTIMER_DTFC_DTFA_CLEAR << 16)          /**< Shifted mode CLEAR for WTIMER_DTFC */
2108 #define WTIMER_DTFC_DTFA_TRISTATE                   (_WTIMER_DTFC_DTFA_TRISTATE << 16)       /**< Shifted mode TRISTATE for WTIMER_DTFC */
2109 #define WTIMER_DTFC_DTPRS0FEN                       (0x1UL << 24)                            /**< DTI PRS 0 Fault Enable */
2110 #define _WTIMER_DTFC_DTPRS0FEN_SHIFT                24                                       /**< Shift value for TIMER_DTPRS0FEN */
2111 #define _WTIMER_DTFC_DTPRS0FEN_MASK                 0x1000000UL                              /**< Bit mask for TIMER_DTPRS0FEN */
2112 #define _WTIMER_DTFC_DTPRS0FEN_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for WTIMER_DTFC */
2113 #define WTIMER_DTFC_DTPRS0FEN_DEFAULT               (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24)   /**< Shifted mode DEFAULT for WTIMER_DTFC */
2114 #define WTIMER_DTFC_DTPRS1FEN                       (0x1UL << 25)                            /**< DTI PRS 1 Fault Enable */
2115 #define _WTIMER_DTFC_DTPRS1FEN_SHIFT                25                                       /**< Shift value for TIMER_DTPRS1FEN */
2116 #define _WTIMER_DTFC_DTPRS1FEN_MASK                 0x2000000UL                              /**< Bit mask for TIMER_DTPRS1FEN */
2117 #define _WTIMER_DTFC_DTPRS1FEN_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for WTIMER_DTFC */
2118 #define WTIMER_DTFC_DTPRS1FEN_DEFAULT               (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25)   /**< Shifted mode DEFAULT for WTIMER_DTFC */
2119 #define WTIMER_DTFC_DTDBGFEN                        (0x1UL << 26)                            /**< DTI Debugger Fault Enable */
2120 #define _WTIMER_DTFC_DTDBGFEN_SHIFT                 26                                       /**< Shift value for TIMER_DTDBGFEN */
2121 #define _WTIMER_DTFC_DTDBGFEN_MASK                  0x4000000UL                              /**< Bit mask for TIMER_DTDBGFEN */
2122 #define _WTIMER_DTFC_DTDBGFEN_DEFAULT               0x00000000UL                             /**< Mode DEFAULT for WTIMER_DTFC */
2123 #define WTIMER_DTFC_DTDBGFEN_DEFAULT                (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26)    /**< Shifted mode DEFAULT for WTIMER_DTFC */
2124 #define WTIMER_DTFC_DTLOCKUPFEN                     (0x1UL << 27)                            /**< DTI Lockup Fault Enable */
2125 #define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT              27                                       /**< Shift value for TIMER_DTLOCKUPFEN */
2126 #define _WTIMER_DTFC_DTLOCKUPFEN_MASK               0x8000000UL                              /**< Bit mask for TIMER_DTLOCKUPFEN */
2127 #define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT            0x00000000UL                             /**< Mode DEFAULT for WTIMER_DTFC */
2128 #define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT             (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */
2129 
2130 /* Bit fields for WTIMER DTOGEN */
2131 #define _WTIMER_DTOGEN_RESETVALUE                   0x00000000UL                              /**< Default value for WTIMER_DTOGEN */
2132 #define _WTIMER_DTOGEN_MASK                         0x0000003FUL                              /**< Mask for WTIMER_DTOGEN */
2133 #define WTIMER_DTOGEN_DTOGCC0EN                     (0x1UL << 0)                              /**< DTI CC0 Output Generation Enable */
2134 #define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT              0                                         /**< Shift value for TIMER_DTOGCC0EN */
2135 #define _WTIMER_DTOGEN_DTOGCC0EN_MASK               0x1UL                                     /**< Bit mask for TIMER_DTOGCC0EN */
2136 #define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for WTIMER_DTOGEN */
2137 #define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT             (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0)   /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
2138 #define WTIMER_DTOGEN_DTOGCC1EN                     (0x1UL << 1)                              /**< DTI CC1 Output Generation Enable */
2139 #define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT              1                                         /**< Shift value for TIMER_DTOGCC1EN */
2140 #define _WTIMER_DTOGEN_DTOGCC1EN_MASK               0x2UL                                     /**< Bit mask for TIMER_DTOGCC1EN */
2141 #define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for WTIMER_DTOGEN */
2142 #define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT             (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1)   /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
2143 #define WTIMER_DTOGEN_DTOGCC2EN                     (0x1UL << 2)                              /**< DTI CC2 Output Generation Enable */
2144 #define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT              2                                         /**< Shift value for TIMER_DTOGCC2EN */
2145 #define _WTIMER_DTOGEN_DTOGCC2EN_MASK               0x4UL                                     /**< Bit mask for TIMER_DTOGCC2EN */
2146 #define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for WTIMER_DTOGEN */
2147 #define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT             (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2)   /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
2148 #define WTIMER_DTOGEN_DTOGCDTI0EN                   (0x1UL << 3)                              /**< DTI CDTI0 Output Generation Enable */
2149 #define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT            3                                         /**< Shift value for TIMER_DTOGCDTI0EN */
2150 #define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK             0x8UL                                     /**< Bit mask for TIMER_DTOGCDTI0EN */
2151 #define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT          0x00000000UL                              /**< Mode DEFAULT for WTIMER_DTOGEN */
2152 #define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT           (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
2153 #define WTIMER_DTOGEN_DTOGCDTI1EN                   (0x1UL << 4)                              /**< DTI CDTI1 Output Generation Enable */
2154 #define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT            4                                         /**< Shift value for TIMER_DTOGCDTI1EN */
2155 #define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK             0x10UL                                    /**< Bit mask for TIMER_DTOGCDTI1EN */
2156 #define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT          0x00000000UL                              /**< Mode DEFAULT for WTIMER_DTOGEN */
2157 #define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT           (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
2158 #define WTIMER_DTOGEN_DTOGCDTI2EN                   (0x1UL << 5)                              /**< DTI CDTI2 Output Generation Enable */
2159 #define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT            5                                         /**< Shift value for TIMER_DTOGCDTI2EN */
2160 #define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK             0x20UL                                    /**< Bit mask for TIMER_DTOGCDTI2EN */
2161 #define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT          0x00000000UL                              /**< Mode DEFAULT for WTIMER_DTOGEN */
2162 #define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT           (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */
2163 
2164 /* Bit fields for WTIMER DTFAULT */
2165 #define _WTIMER_DTFAULT_RESETVALUE                  0x00000000UL                             /**< Default value for WTIMER_DTFAULT */
2166 #define _WTIMER_DTFAULT_MASK                        0x0000000FUL                             /**< Mask for WTIMER_DTFAULT */
2167 #define WTIMER_DTFAULT_DTPRS0F                      (0x1UL << 0)                             /**< DTI PRS 0 Fault */
2168 #define _WTIMER_DTFAULT_DTPRS0F_SHIFT               0                                        /**< Shift value for TIMER_DTPRS0F */
2169 #define _WTIMER_DTFAULT_DTPRS0F_MASK                0x1UL                                    /**< Bit mask for TIMER_DTPRS0F */
2170 #define _WTIMER_DTFAULT_DTPRS0F_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for WTIMER_DTFAULT */
2171 #define WTIMER_DTFAULT_DTPRS0F_DEFAULT              (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0)   /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
2172 #define WTIMER_DTFAULT_DTPRS1F                      (0x1UL << 1)                             /**< DTI PRS 1 Fault */
2173 #define _WTIMER_DTFAULT_DTPRS1F_SHIFT               1                                        /**< Shift value for TIMER_DTPRS1F */
2174 #define _WTIMER_DTFAULT_DTPRS1F_MASK                0x2UL                                    /**< Bit mask for TIMER_DTPRS1F */
2175 #define _WTIMER_DTFAULT_DTPRS1F_DEFAULT             0x00000000UL                             /**< Mode DEFAULT for WTIMER_DTFAULT */
2176 #define WTIMER_DTFAULT_DTPRS1F_DEFAULT              (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1)   /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
2177 #define WTIMER_DTFAULT_DTDBGF                       (0x1UL << 2)                             /**< DTI Debugger Fault */
2178 #define _WTIMER_DTFAULT_DTDBGF_SHIFT                2                                        /**< Shift value for TIMER_DTDBGF */
2179 #define _WTIMER_DTFAULT_DTDBGF_MASK                 0x4UL                                    /**< Bit mask for TIMER_DTDBGF */
2180 #define _WTIMER_DTFAULT_DTDBGF_DEFAULT              0x00000000UL                             /**< Mode DEFAULT for WTIMER_DTFAULT */
2181 #define WTIMER_DTFAULT_DTDBGF_DEFAULT               (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2)    /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
2182 #define WTIMER_DTFAULT_DTLOCKUPF                    (0x1UL << 3)                             /**< DTI Lockup Fault */
2183 #define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT             3                                        /**< Shift value for TIMER_DTLOCKUPF */
2184 #define _WTIMER_DTFAULT_DTLOCKUPF_MASK              0x8UL                                    /**< Bit mask for TIMER_DTLOCKUPF */
2185 #define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT           0x00000000UL                             /**< Mode DEFAULT for WTIMER_DTFAULT */
2186 #define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT            (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */
2187 
2188 /* Bit fields for WTIMER DTFAULTC */
2189 #define _WTIMER_DTFAULTC_RESETVALUE                 0x00000000UL                              /**< Default value for WTIMER_DTFAULTC */
2190 #define _WTIMER_DTFAULTC_MASK                       0x0000000FUL                              /**< Mask for WTIMER_DTFAULTC */
2191 #define WTIMER_DTFAULTC_DTPRS0FC                    (0x1UL << 0)                              /**< DTI PRS0 Fault Clear */
2192 #define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT             0                                         /**< Shift value for TIMER_DTPRS0FC */
2193 #define _WTIMER_DTFAULTC_DTPRS0FC_MASK              0x1UL                                     /**< Bit mask for TIMER_DTPRS0FC */
2194 #define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT           0x00000000UL                              /**< Mode DEFAULT for WTIMER_DTFAULTC */
2195 #define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT            (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0)  /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
2196 #define WTIMER_DTFAULTC_DTPRS1FC                    (0x1UL << 1)                              /**< DTI PRS1 Fault Clear */
2197 #define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT             1                                         /**< Shift value for TIMER_DTPRS1FC */
2198 #define _WTIMER_DTFAULTC_DTPRS1FC_MASK              0x2UL                                     /**< Bit mask for TIMER_DTPRS1FC */
2199 #define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT           0x00000000UL                              /**< Mode DEFAULT for WTIMER_DTFAULTC */
2200 #define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT            (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1)  /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
2201 #define WTIMER_DTFAULTC_DTDBGFC                     (0x1UL << 2)                              /**< DTI Debugger Fault Clear */
2202 #define _WTIMER_DTFAULTC_DTDBGFC_SHIFT              2                                         /**< Shift value for TIMER_DTDBGFC */
2203 #define _WTIMER_DTFAULTC_DTDBGFC_MASK               0x4UL                                     /**< Bit mask for TIMER_DTDBGFC */
2204 #define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT            0x00000000UL                              /**< Mode DEFAULT for WTIMER_DTFAULTC */
2205 #define WTIMER_DTFAULTC_DTDBGFC_DEFAULT             (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2)   /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
2206 #define WTIMER_DTFAULTC_TLOCKUPFC                   (0x1UL << 3)                              /**< DTI Lockup Fault Clear */
2207 #define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT            3                                         /**< Shift value for TIMER_TLOCKUPFC */
2208 #define _WTIMER_DTFAULTC_TLOCKUPFC_MASK             0x8UL                                     /**< Bit mask for TIMER_TLOCKUPFC */
2209 #define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT          0x00000000UL                              /**< Mode DEFAULT for WTIMER_DTFAULTC */
2210 #define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT           (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */
2211 
2212 /* Bit fields for WTIMER DTLOCK */
2213 #define _WTIMER_DTLOCK_RESETVALUE                   0x00000000UL                           /**< Default value for WTIMER_DTLOCK */
2214 #define _WTIMER_DTLOCK_MASK                         0x0000FFFFUL                           /**< Mask for WTIMER_DTLOCK */
2215 #define _WTIMER_DTLOCK_LOCKKEY_SHIFT                0                                      /**< Shift value for TIMER_LOCKKEY */
2216 #define _WTIMER_DTLOCK_LOCKKEY_MASK                 0xFFFFUL                               /**< Bit mask for TIMER_LOCKKEY */
2217 #define _WTIMER_DTLOCK_LOCKKEY_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for WTIMER_DTLOCK */
2218 #define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED             0x00000000UL                           /**< Mode UNLOCKED for WTIMER_DTLOCK */
2219 #define _WTIMER_DTLOCK_LOCKKEY_LOCK                 0x00000000UL                           /**< Mode LOCK for WTIMER_DTLOCK */
2220 #define _WTIMER_DTLOCK_LOCKKEY_LOCKED               0x00000001UL                           /**< Mode LOCKED for WTIMER_DTLOCK */
2221 #define _WTIMER_DTLOCK_LOCKKEY_UNLOCK               0x0000CE80UL                           /**< Mode UNLOCK for WTIMER_DTLOCK */
2222 #define WTIMER_DTLOCK_LOCKKEY_DEFAULT               (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for WTIMER_DTLOCK */
2223 #define WTIMER_DTLOCK_LOCKKEY_UNLOCKED              (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */
2224 #define WTIMER_DTLOCK_LOCKKEY_LOCK                  (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for WTIMER_DTLOCK */
2225 #define WTIMER_DTLOCK_LOCKKEY_LOCKED                (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for WTIMER_DTLOCK */
2226 #define WTIMER_DTLOCK_LOCKKEY_UNLOCK                (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for WTIMER_DTLOCK */
2227 
2228 /** @} */
2229 /** @} End of group EFM32GG12B310F1024GQ100_WTIMER */
2230 
2231 #include "efm32gg12b_uart.h"
2232 
2233 /***************************************************************************//**
2234  * @addtogroup EFM32GG12B310F1024GQ100_MSC
2235  * @{
2236  * @defgroup EFM32GG12B310F1024GQ100_MSC_BitFields  MSC Bit Fields
2237  * @{
2238  ******************************************************************************/
2239 
2240 /* Bit fields for MSC CTRL */
2241 #define _MSC_CTRL_RESETVALUE                              0x00000021UL                              /**< Default value for MSC_CTRL */
2242 #define _MSC_CTRL_MASK                                    0x0000107FUL                              /**< Mask for MSC_CTRL */
2243 #define MSC_CTRL_ADDRFAULTEN                              (0x1UL << 0)                              /**< Invalid Address Bus Fault Response Enable */
2244 #define _MSC_CTRL_ADDRFAULTEN_SHIFT                       0                                         /**< Shift value for MSC_ADDRFAULTEN */
2245 #define _MSC_CTRL_ADDRFAULTEN_MASK                        0x1UL                                     /**< Bit mask for MSC_ADDRFAULTEN */
2246 #define _MSC_CTRL_ADDRFAULTEN_DEFAULT                     0x00000001UL                              /**< Mode DEFAULT for MSC_CTRL */
2247 #define MSC_CTRL_ADDRFAULTEN_DEFAULT                      (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0)      /**< Shifted mode DEFAULT for MSC_CTRL */
2248 #define MSC_CTRL_CLKDISFAULTEN                            (0x1UL << 1)                              /**< Clock-disabled Bus Fault Response Enable */
2249 #define _MSC_CTRL_CLKDISFAULTEN_SHIFT                     1                                         /**< Shift value for MSC_CLKDISFAULTEN */
2250 #define _MSC_CTRL_CLKDISFAULTEN_MASK                      0x2UL                                     /**< Bit mask for MSC_CLKDISFAULTEN */
2251 #define _MSC_CTRL_CLKDISFAULTEN_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for MSC_CTRL */
2252 #define MSC_CTRL_CLKDISFAULTEN_DEFAULT                    (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1)    /**< Shifted mode DEFAULT for MSC_CTRL */
2253 #define MSC_CTRL_PWRUPONDEMAND                            (0x1UL << 2)                              /**< Power Up on Demand During Wake Up */
2254 #define _MSC_CTRL_PWRUPONDEMAND_SHIFT                     2                                         /**< Shift value for MSC_PWRUPONDEMAND */
2255 #define _MSC_CTRL_PWRUPONDEMAND_MASK                      0x4UL                                     /**< Bit mask for MSC_PWRUPONDEMAND */
2256 #define _MSC_CTRL_PWRUPONDEMAND_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for MSC_CTRL */
2257 #define MSC_CTRL_PWRUPONDEMAND_DEFAULT                    (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2)    /**< Shifted mode DEFAULT for MSC_CTRL */
2258 #define MSC_CTRL_IFCREADCLEAR                             (0x1UL << 3)                              /**< IFC Read Clears IF */
2259 #define _MSC_CTRL_IFCREADCLEAR_SHIFT                      3                                         /**< Shift value for MSC_IFCREADCLEAR */
2260 #define _MSC_CTRL_IFCREADCLEAR_MASK                       0x8UL                                     /**< Bit mask for MSC_IFCREADCLEAR */
2261 #define _MSC_CTRL_IFCREADCLEAR_DEFAULT                    0x00000000UL                              /**< Mode DEFAULT for MSC_CTRL */
2262 #define MSC_CTRL_IFCREADCLEAR_DEFAULT                     (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3)     /**< Shifted mode DEFAULT for MSC_CTRL */
2263 #define MSC_CTRL_TIMEOUTFAULTEN                           (0x1UL << 4)                              /**< Timeout Bus Fault Response Enable */
2264 #define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT                    4                                         /**< Shift value for MSC_TIMEOUTFAULTEN */
2265 #define _MSC_CTRL_TIMEOUTFAULTEN_MASK                     0x10UL                                    /**< Bit mask for MSC_TIMEOUTFAULTEN */
2266 #define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT                  0x00000000UL                              /**< Mode DEFAULT for MSC_CTRL */
2267 #define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT                   (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4)   /**< Shifted mode DEFAULT for MSC_CTRL */
2268 #define MSC_CTRL_RAMECCERRFAULTEN                         (0x1UL << 5)                              /**< Two Bit ECC Error Bus Fault Response Enable */
2269 #define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT                  5                                         /**< Shift value for MSC_RAMECCERRFAULTEN */
2270 #define _MSC_CTRL_RAMECCERRFAULTEN_MASK                   0x20UL                                    /**< Bit mask for MSC_RAMECCERRFAULTEN */
2271 #define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT                0x00000001UL                              /**< Mode DEFAULT for MSC_CTRL */
2272 #define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT                 (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */
2273 #define MSC_CTRL_EBIFAULTEN                               (0x1UL << 6)                              /**< EBI Bus Fault Response Enable */
2274 #define _MSC_CTRL_EBIFAULTEN_SHIFT                        6                                         /**< Shift value for MSC_EBIFAULTEN */
2275 #define _MSC_CTRL_EBIFAULTEN_MASK                         0x40UL                                    /**< Bit mask for MSC_EBIFAULTEN */
2276 #define _MSC_CTRL_EBIFAULTEN_DEFAULT                      0x00000000UL                              /**< Mode DEFAULT for MSC_CTRL */
2277 #define MSC_CTRL_EBIFAULTEN_DEFAULT                       (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6)       /**< Shifted mode DEFAULT for MSC_CTRL */
2278 #define MSC_CTRL_WAITMODE                                 (0x1UL << 12)                             /**< Peripheral Access Wait Mode */
2279 #define _MSC_CTRL_WAITMODE_SHIFT                          12                                        /**< Shift value for MSC_WAITMODE */
2280 #define _MSC_CTRL_WAITMODE_MASK                           0x1000UL                                  /**< Bit mask for MSC_WAITMODE */
2281 #define _MSC_CTRL_WAITMODE_DEFAULT                        0x00000000UL                              /**< Mode DEFAULT for MSC_CTRL */
2282 #define _MSC_CTRL_WAITMODE_WS0                            0x00000000UL                              /**< Mode WS0 for MSC_CTRL */
2283 #define _MSC_CTRL_WAITMODE_WS1                            0x00000001UL                              /**< Mode WS1 for MSC_CTRL */
2284 #define MSC_CTRL_WAITMODE_DEFAULT                         (_MSC_CTRL_WAITMODE_DEFAULT << 12)        /**< Shifted mode DEFAULT for MSC_CTRL */
2285 #define MSC_CTRL_WAITMODE_WS0                             (_MSC_CTRL_WAITMODE_WS0 << 12)            /**< Shifted mode WS0 for MSC_CTRL */
2286 #define MSC_CTRL_WAITMODE_WS1                             (_MSC_CTRL_WAITMODE_WS1 << 12)            /**< Shifted mode WS1 for MSC_CTRL */
2287 
2288 /* Bit fields for MSC READCTRL */
2289 #define _MSC_READCTRL_RESETVALUE                          0x01000100UL                          /**< Default value for MSC_READCTRL */
2290 #define _MSC_READCTRL_MASK                                0x13000378UL                          /**< Mask for MSC_READCTRL */
2291 #define MSC_READCTRL_IFCDIS                               (0x1UL << 3)                          /**< Internal Flash Cache Disable */
2292 #define _MSC_READCTRL_IFCDIS_SHIFT                        3                                     /**< Shift value for MSC_IFCDIS */
2293 #define _MSC_READCTRL_IFCDIS_MASK                         0x8UL                                 /**< Bit mask for MSC_IFCDIS */
2294 #define _MSC_READCTRL_IFCDIS_DEFAULT                      0x00000000UL                          /**< Mode DEFAULT for MSC_READCTRL */
2295 #define MSC_READCTRL_IFCDIS_DEFAULT                       (_MSC_READCTRL_IFCDIS_DEFAULT << 3)   /**< Shifted mode DEFAULT for MSC_READCTRL */
2296 #define MSC_READCTRL_AIDIS                                (0x1UL << 4)                          /**< Automatic Invalidate Disable */
2297 #define _MSC_READCTRL_AIDIS_SHIFT                         4                                     /**< Shift value for MSC_AIDIS */
2298 #define _MSC_READCTRL_AIDIS_MASK                          0x10UL                                /**< Bit mask for MSC_AIDIS */
2299 #define _MSC_READCTRL_AIDIS_DEFAULT                       0x00000000UL                          /**< Mode DEFAULT for MSC_READCTRL */
2300 #define MSC_READCTRL_AIDIS_DEFAULT                        (_MSC_READCTRL_AIDIS_DEFAULT << 4)    /**< Shifted mode DEFAULT for MSC_READCTRL */
2301 #define MSC_READCTRL_ICCDIS                               (0x1UL << 5)                          /**< Interrupt Context Cache Disable */
2302 #define _MSC_READCTRL_ICCDIS_SHIFT                        5                                     /**< Shift value for MSC_ICCDIS */
2303 #define _MSC_READCTRL_ICCDIS_MASK                         0x20UL                                /**< Bit mask for MSC_ICCDIS */
2304 #define _MSC_READCTRL_ICCDIS_DEFAULT                      0x00000000UL                          /**< Mode DEFAULT for MSC_READCTRL */
2305 #define MSC_READCTRL_ICCDIS_DEFAULT                       (_MSC_READCTRL_ICCDIS_DEFAULT << 5)   /**< Shifted mode DEFAULT for MSC_READCTRL */
2306 #define MSC_READCTRL_EBICDIS                              (0x1UL << 6)                          /**< External Bus Interface Cache Disable */
2307 #define _MSC_READCTRL_EBICDIS_SHIFT                       6                                     /**< Shift value for MSC_EBICDIS */
2308 #define _MSC_READCTRL_EBICDIS_MASK                        0x40UL                                /**< Bit mask for MSC_EBICDIS */
2309 #define _MSC_READCTRL_EBICDIS_DEFAULT                     0x00000000UL                          /**< Mode DEFAULT for MSC_READCTRL */
2310 #define MSC_READCTRL_EBICDIS_DEFAULT                      (_MSC_READCTRL_EBICDIS_DEFAULT << 6)  /**< Shifted mode DEFAULT for MSC_READCTRL */
2311 #define MSC_READCTRL_PREFETCH                             (0x1UL << 8)                          /**< Prefetch Mode */
2312 #define _MSC_READCTRL_PREFETCH_SHIFT                      8                                     /**< Shift value for MSC_PREFETCH */
2313 #define _MSC_READCTRL_PREFETCH_MASK                       0x100UL                               /**< Bit mask for MSC_PREFETCH */
2314 #define _MSC_READCTRL_PREFETCH_DEFAULT                    0x00000001UL                          /**< Mode DEFAULT for MSC_READCTRL */
2315 #define MSC_READCTRL_PREFETCH_DEFAULT                     (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */
2316 #define MSC_READCTRL_USEHPROT                             (0x1UL << 9)                          /**< AHB_HPROT Mode */
2317 #define _MSC_READCTRL_USEHPROT_SHIFT                      9                                     /**< Shift value for MSC_USEHPROT */
2318 #define _MSC_READCTRL_USEHPROT_MASK                       0x200UL                               /**< Bit mask for MSC_USEHPROT */
2319 #define _MSC_READCTRL_USEHPROT_DEFAULT                    0x00000000UL                          /**< Mode DEFAULT for MSC_READCTRL */
2320 #define MSC_READCTRL_USEHPROT_DEFAULT                     (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */
2321 #define _MSC_READCTRL_MODE_SHIFT                          24                                    /**< Shift value for MSC_MODE */
2322 #define _MSC_READCTRL_MODE_MASK                           0x3000000UL                           /**< Bit mask for MSC_MODE */
2323 #define _MSC_READCTRL_MODE_WS0                            0x00000000UL                          /**< Mode WS0 for MSC_READCTRL */
2324 #define _MSC_READCTRL_MODE_DEFAULT                        0x00000001UL                          /**< Mode DEFAULT for MSC_READCTRL */
2325 #define _MSC_READCTRL_MODE_WS1                            0x00000001UL                          /**< Mode WS1 for MSC_READCTRL */
2326 #define _MSC_READCTRL_MODE_WS2                            0x00000002UL                          /**< Mode WS2 for MSC_READCTRL */
2327 #define _MSC_READCTRL_MODE_WS3                            0x00000003UL                          /**< Mode WS3 for MSC_READCTRL */
2328 #define MSC_READCTRL_MODE_WS0                             (_MSC_READCTRL_MODE_WS0 << 24)        /**< Shifted mode WS0 for MSC_READCTRL */
2329 #define MSC_READCTRL_MODE_DEFAULT                         (_MSC_READCTRL_MODE_DEFAULT << 24)    /**< Shifted mode DEFAULT for MSC_READCTRL */
2330 #define MSC_READCTRL_MODE_WS1                             (_MSC_READCTRL_MODE_WS1 << 24)        /**< Shifted mode WS1 for MSC_READCTRL */
2331 #define MSC_READCTRL_MODE_WS2                             (_MSC_READCTRL_MODE_WS2 << 24)        /**< Shifted mode WS2 for MSC_READCTRL */
2332 #define MSC_READCTRL_MODE_WS3                             (_MSC_READCTRL_MODE_WS3 << 24)        /**< Shifted mode WS3 for MSC_READCTRL */
2333 #define MSC_READCTRL_SCBTP                                (0x1UL << 28)                         /**< Suppress Conditional Branch Target Perfetch */
2334 #define _MSC_READCTRL_SCBTP_SHIFT                         28                                    /**< Shift value for MSC_SCBTP */
2335 #define _MSC_READCTRL_SCBTP_MASK                          0x10000000UL                          /**< Bit mask for MSC_SCBTP */
2336 #define _MSC_READCTRL_SCBTP_DEFAULT                       0x00000000UL                          /**< Mode DEFAULT for MSC_READCTRL */
2337 #define MSC_READCTRL_SCBTP_DEFAULT                        (_MSC_READCTRL_SCBTP_DEFAULT << 28)   /**< Shifted mode DEFAULT for MSC_READCTRL */
2338 
2339 /* Bit fields for MSC WRITECTRL */
2340 #define _MSC_WRITECTRL_RESETVALUE                         0x00000000UL                                /**< Default value for MSC_WRITECTRL */
2341 #define _MSC_WRITECTRL_MASK                               0x00000023UL                                /**< Mask for MSC_WRITECTRL */
2342 #define MSC_WRITECTRL_WREN                                (0x1UL << 0)                                /**< Enable Write/Erase Controller */
2343 #define _MSC_WRITECTRL_WREN_SHIFT                         0                                           /**< Shift value for MSC_WREN */
2344 #define _MSC_WRITECTRL_WREN_MASK                          0x1UL                                       /**< Bit mask for MSC_WREN */
2345 #define _MSC_WRITECTRL_WREN_DEFAULT                       0x00000000UL                                /**< Mode DEFAULT for MSC_WRITECTRL */
2346 #define MSC_WRITECTRL_WREN_DEFAULT                        (_MSC_WRITECTRL_WREN_DEFAULT << 0)          /**< Shifted mode DEFAULT for MSC_WRITECTRL */
2347 #define MSC_WRITECTRL_IRQERASEABORT                       (0x1UL << 1)                                /**< Abort Page Erase on Interrupt */
2348 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT                1                                           /**< Shift value for MSC_IRQERASEABORT */
2349 #define _MSC_WRITECTRL_IRQERASEABORT_MASK                 0x2UL                                       /**< Bit mask for MSC_IRQERASEABORT */
2350 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT              0x00000000UL                                /**< Mode DEFAULT for MSC_WRITECTRL */
2351 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT               (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
2352 #define MSC_WRITECTRL_RWWEN                               (0x1UL << 5)                                /**< Read-While-Write Enable */
2353 #define _MSC_WRITECTRL_RWWEN_SHIFT                        5                                           /**< Shift value for MSC_RWWEN */
2354 #define _MSC_WRITECTRL_RWWEN_MASK                         0x20UL                                      /**< Bit mask for MSC_RWWEN */
2355 #define _MSC_WRITECTRL_RWWEN_DEFAULT                      0x00000000UL                                /**< Mode DEFAULT for MSC_WRITECTRL */
2356 #define MSC_WRITECTRL_RWWEN_DEFAULT                       (_MSC_WRITECTRL_RWWEN_DEFAULT << 5)         /**< Shifted mode DEFAULT for MSC_WRITECTRL */
2357 
2358 /* Bit fields for MSC WRITECMD */
2359 #define _MSC_WRITECMD_RESETVALUE                          0x00000000UL                             /**< Default value for MSC_WRITECMD */
2360 #define _MSC_WRITECMD_MASK                                0x0000133FUL                             /**< Mask for MSC_WRITECMD */
2361 #define MSC_WRITECMD_LADDRIM                              (0x1UL << 0)                             /**< Load MSC_ADDRB Into ADDR */
2362 #define _MSC_WRITECMD_LADDRIM_SHIFT                       0                                        /**< Shift value for MSC_LADDRIM */
2363 #define _MSC_WRITECMD_LADDRIM_MASK                        0x1UL                                    /**< Bit mask for MSC_LADDRIM */
2364 #define _MSC_WRITECMD_LADDRIM_DEFAULT                     0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
2365 #define MSC_WRITECMD_LADDRIM_DEFAULT                      (_MSC_WRITECMD_LADDRIM_DEFAULT << 0)     /**< Shifted mode DEFAULT for MSC_WRITECMD */
2366 #define MSC_WRITECMD_ERASEPAGE                            (0x1UL << 1)                             /**< Erase Page */
2367 #define _MSC_WRITECMD_ERASEPAGE_SHIFT                     1                                        /**< Shift value for MSC_ERASEPAGE */
2368 #define _MSC_WRITECMD_ERASEPAGE_MASK                      0x2UL                                    /**< Bit mask for MSC_ERASEPAGE */
2369 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
2370 #define MSC_WRITECMD_ERASEPAGE_DEFAULT                    (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1)   /**< Shifted mode DEFAULT for MSC_WRITECMD */
2371 #define MSC_WRITECMD_WRITEEND                             (0x1UL << 2)                             /**< End Write Mode */
2372 #define _MSC_WRITECMD_WRITEEND_SHIFT                      2                                        /**< Shift value for MSC_WRITEEND */
2373 #define _MSC_WRITECMD_WRITEEND_MASK                       0x4UL                                    /**< Bit mask for MSC_WRITEEND */
2374 #define _MSC_WRITECMD_WRITEEND_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
2375 #define MSC_WRITECMD_WRITEEND_DEFAULT                     (_MSC_WRITECMD_WRITEEND_DEFAULT << 2)    /**< Shifted mode DEFAULT for MSC_WRITECMD */
2376 #define MSC_WRITECMD_WRITEONCE                            (0x1UL << 3)                             /**< Word Write-Once Trigger */
2377 #define _MSC_WRITECMD_WRITEONCE_SHIFT                     3                                        /**< Shift value for MSC_WRITEONCE */
2378 #define _MSC_WRITECMD_WRITEONCE_MASK                      0x8UL                                    /**< Bit mask for MSC_WRITEONCE */
2379 #define _MSC_WRITECMD_WRITEONCE_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
2380 #define MSC_WRITECMD_WRITEONCE_DEFAULT                    (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3)   /**< Shifted mode DEFAULT for MSC_WRITECMD */
2381 #define MSC_WRITECMD_WRITETRIG                            (0x1UL << 4)                             /**< Word Write Sequence Trigger */
2382 #define _MSC_WRITECMD_WRITETRIG_SHIFT                     4                                        /**< Shift value for MSC_WRITETRIG */
2383 #define _MSC_WRITECMD_WRITETRIG_MASK                      0x10UL                                   /**< Bit mask for MSC_WRITETRIG */
2384 #define _MSC_WRITECMD_WRITETRIG_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
2385 #define MSC_WRITECMD_WRITETRIG_DEFAULT                    (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4)   /**< Shifted mode DEFAULT for MSC_WRITECMD */
2386 #define MSC_WRITECMD_ERASEABORT                           (0x1UL << 5)                             /**< Abort Erase Sequence */
2387 #define _MSC_WRITECMD_ERASEABORT_SHIFT                    5                                        /**< Shift value for MSC_ERASEABORT */
2388 #define _MSC_WRITECMD_ERASEABORT_MASK                     0x20UL                                   /**< Bit mask for MSC_ERASEABORT */
2389 #define _MSC_WRITECMD_ERASEABORT_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
2390 #define MSC_WRITECMD_ERASEABORT_DEFAULT                   (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5)  /**< Shifted mode DEFAULT for MSC_WRITECMD */
2391 #define MSC_WRITECMD_ERASEMAIN0                           (0x1UL << 8)                             /**< Mass Erase Region 0 */
2392 #define _MSC_WRITECMD_ERASEMAIN0_SHIFT                    8                                        /**< Shift value for MSC_ERASEMAIN0 */
2393 #define _MSC_WRITECMD_ERASEMAIN0_MASK                     0x100UL                                  /**< Bit mask for MSC_ERASEMAIN0 */
2394 #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
2395 #define MSC_WRITECMD_ERASEMAIN0_DEFAULT                   (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8)  /**< Shifted mode DEFAULT for MSC_WRITECMD */
2396 #define MSC_WRITECMD_ERASEMAIN1                           (0x1UL << 9)                             /**< Mass Erase Region 1 */
2397 #define _MSC_WRITECMD_ERASEMAIN1_SHIFT                    9                                        /**< Shift value for MSC_ERASEMAIN1 */
2398 #define _MSC_WRITECMD_ERASEMAIN1_MASK                     0x200UL                                  /**< Bit mask for MSC_ERASEMAIN1 */
2399 #define _MSC_WRITECMD_ERASEMAIN1_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
2400 #define MSC_WRITECMD_ERASEMAIN1_DEFAULT                   (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9)  /**< Shifted mode DEFAULT for MSC_WRITECMD */
2401 #define MSC_WRITECMD_CLEARWDATA                           (0x1UL << 12)                            /**< Clear WDATA State */
2402 #define _MSC_WRITECMD_CLEARWDATA_SHIFT                    12                                       /**< Shift value for MSC_CLEARWDATA */
2403 #define _MSC_WRITECMD_CLEARWDATA_MASK                     0x1000UL                                 /**< Bit mask for MSC_CLEARWDATA */
2404 #define _MSC_WRITECMD_CLEARWDATA_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for MSC_WRITECMD */
2405 #define MSC_WRITECMD_CLEARWDATA_DEFAULT                   (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
2406 
2407 /* Bit fields for MSC ADDRB */
2408 #define _MSC_ADDRB_RESETVALUE                             0x00000000UL                    /**< Default value for MSC_ADDRB */
2409 #define _MSC_ADDRB_MASK                                   0xFFFFFFFFUL                    /**< Mask for MSC_ADDRB */
2410 #define _MSC_ADDRB_ADDRB_SHIFT                            0                               /**< Shift value for MSC_ADDRB */
2411 #define _MSC_ADDRB_ADDRB_MASK                             0xFFFFFFFFUL                    /**< Bit mask for MSC_ADDRB */
2412 #define _MSC_ADDRB_ADDRB_DEFAULT                          0x00000000UL                    /**< Mode DEFAULT for MSC_ADDRB */
2413 #define MSC_ADDRB_ADDRB_DEFAULT                           (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
2414 
2415 /* Bit fields for MSC WDATA */
2416 #define _MSC_WDATA_RESETVALUE                             0x00000000UL                    /**< Default value for MSC_WDATA */
2417 #define _MSC_WDATA_MASK                                   0xFFFFFFFFUL                    /**< Mask for MSC_WDATA */
2418 #define _MSC_WDATA_WDATA_SHIFT                            0                               /**< Shift value for MSC_WDATA */
2419 #define _MSC_WDATA_WDATA_MASK                             0xFFFFFFFFUL                    /**< Bit mask for MSC_WDATA */
2420 #define _MSC_WDATA_WDATA_DEFAULT                          0x00000000UL                    /**< Mode DEFAULT for MSC_WDATA */
2421 #define MSC_WDATA_WDATA_DEFAULT                           (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
2422 
2423 /* Bit fields for MSC STATUS */
2424 #define _MSC_STATUS_RESETVALUE                            0x00000008UL                                   /**< Default value for MSC_STATUS */
2425 #define _MSC_STATUS_MASK                                  0xFF0000FFUL                                   /**< Mask for MSC_STATUS */
2426 #define MSC_STATUS_BUSY                                   (0x1UL << 0)                                   /**< Erase/Write Busy */
2427 #define _MSC_STATUS_BUSY_SHIFT                            0                                              /**< Shift value for MSC_BUSY */
2428 #define _MSC_STATUS_BUSY_MASK                             0x1UL                                          /**< Bit mask for MSC_BUSY */
2429 #define _MSC_STATUS_BUSY_DEFAULT                          0x00000000UL                                   /**< Mode DEFAULT for MSC_STATUS */
2430 #define MSC_STATUS_BUSY_DEFAULT                           (_MSC_STATUS_BUSY_DEFAULT << 0)                /**< Shifted mode DEFAULT for MSC_STATUS */
2431 #define MSC_STATUS_LOCKED                                 (0x1UL << 1)                                   /**< Access Locked */
2432 #define _MSC_STATUS_LOCKED_SHIFT                          1                                              /**< Shift value for MSC_LOCKED */
2433 #define _MSC_STATUS_LOCKED_MASK                           0x2UL                                          /**< Bit mask for MSC_LOCKED */
2434 #define _MSC_STATUS_LOCKED_DEFAULT                        0x00000000UL                                   /**< Mode DEFAULT for MSC_STATUS */
2435 #define MSC_STATUS_LOCKED_DEFAULT                         (_MSC_STATUS_LOCKED_DEFAULT << 1)              /**< Shifted mode DEFAULT for MSC_STATUS */
2436 #define MSC_STATUS_INVADDR                                (0x1UL << 2)                                   /**< Invalid Write Address or Erase Page */
2437 #define _MSC_STATUS_INVADDR_SHIFT                         2                                              /**< Shift value for MSC_INVADDR */
2438 #define _MSC_STATUS_INVADDR_MASK                          0x4UL                                          /**< Bit mask for MSC_INVADDR */
2439 #define _MSC_STATUS_INVADDR_DEFAULT                       0x00000000UL                                   /**< Mode DEFAULT for MSC_STATUS */
2440 #define MSC_STATUS_INVADDR_DEFAULT                        (_MSC_STATUS_INVADDR_DEFAULT << 2)             /**< Shifted mode DEFAULT for MSC_STATUS */
2441 #define MSC_STATUS_WDATAREADY                             (0x1UL << 3)                                   /**< WDATA Write Ready */
2442 #define _MSC_STATUS_WDATAREADY_SHIFT                      3                                              /**< Shift value for MSC_WDATAREADY */
2443 #define _MSC_STATUS_WDATAREADY_MASK                       0x8UL                                          /**< Bit mask for MSC_WDATAREADY */
2444 #define _MSC_STATUS_WDATAREADY_DEFAULT                    0x00000001UL                                   /**< Mode DEFAULT for MSC_STATUS */
2445 #define MSC_STATUS_WDATAREADY_DEFAULT                     (_MSC_STATUS_WDATAREADY_DEFAULT << 3)          /**< Shifted mode DEFAULT for MSC_STATUS */
2446 #define MSC_STATUS_WORDTIMEOUT                            (0x1UL << 4)                                   /**< Flash Write Word Timeout */
2447 #define _MSC_STATUS_WORDTIMEOUT_SHIFT                     4                                              /**< Shift value for MSC_WORDTIMEOUT */
2448 #define _MSC_STATUS_WORDTIMEOUT_MASK                      0x10UL                                         /**< Bit mask for MSC_WORDTIMEOUT */
2449 #define _MSC_STATUS_WORDTIMEOUT_DEFAULT                   0x00000000UL                                   /**< Mode DEFAULT for MSC_STATUS */
2450 #define MSC_STATUS_WORDTIMEOUT_DEFAULT                    (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4)         /**< Shifted mode DEFAULT for MSC_STATUS */
2451 #define MSC_STATUS_ERASEABORTED                           (0x1UL << 5)                                   /**< The Current Flash Erase Operation Aborted */
2452 #define _MSC_STATUS_ERASEABORTED_SHIFT                    5                                              /**< Shift value for MSC_ERASEABORTED */
2453 #define _MSC_STATUS_ERASEABORTED_MASK                     0x20UL                                         /**< Bit mask for MSC_ERASEABORTED */
2454 #define _MSC_STATUS_ERASEABORTED_DEFAULT                  0x00000000UL                                   /**< Mode DEFAULT for MSC_STATUS */
2455 #define MSC_STATUS_ERASEABORTED_DEFAULT                   (_MSC_STATUS_ERASEABORTED_DEFAULT << 5)        /**< Shifted mode DEFAULT for MSC_STATUS */
2456 #define MSC_STATUS_PCRUNNING                              (0x1UL << 6)                                   /**< Performance Counters Running */
2457 #define _MSC_STATUS_PCRUNNING_SHIFT                       6                                              /**< Shift value for MSC_PCRUNNING */
2458 #define _MSC_STATUS_PCRUNNING_MASK                        0x40UL                                         /**< Bit mask for MSC_PCRUNNING */
2459 #define _MSC_STATUS_PCRUNNING_DEFAULT                     0x00000000UL                                   /**< Mode DEFAULT for MSC_STATUS */
2460 #define MSC_STATUS_PCRUNNING_DEFAULT                      (_MSC_STATUS_PCRUNNING_DEFAULT << 6)           /**< Shifted mode DEFAULT for MSC_STATUS */
2461 #define MSC_STATUS_BANKSWITCHED                           (0x1UL << 7)                                   /**< BANK SWITCHING STATUS */
2462 #define _MSC_STATUS_BANKSWITCHED_SHIFT                    7                                              /**< Shift value for MSC_BANKSWITCHED */
2463 #define _MSC_STATUS_BANKSWITCHED_MASK                     0x80UL                                         /**< Bit mask for MSC_BANKSWITCHED */
2464 #define _MSC_STATUS_BANKSWITCHED_DEFAULT                  0x00000000UL                                   /**< Mode DEFAULT for MSC_STATUS */
2465 #define MSC_STATUS_BANKSWITCHED_DEFAULT                   (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7)        /**< Shifted mode DEFAULT for MSC_STATUS */
2466 #define _MSC_STATUS_WDATAVALID_SHIFT                      24                                             /**< Shift value for MSC_WDATAVALID */
2467 #define _MSC_STATUS_WDATAVALID_MASK                       0xF000000UL                                    /**< Bit mask for MSC_WDATAVALID */
2468 #define _MSC_STATUS_WDATAVALID_DEFAULT                    0x00000000UL                                   /**< Mode DEFAULT for MSC_STATUS */
2469 #define MSC_STATUS_WDATAVALID_DEFAULT                     (_MSC_STATUS_WDATAVALID_DEFAULT << 24)         /**< Shifted mode DEFAULT for MSC_STATUS */
2470 #define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT              28                                             /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */
2471 #define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK               0xF0000000UL                                   /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */
2472 #define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT            0x00000000UL                                   /**< Mode DEFAULT for MSC_STATUS */
2473 #define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT             (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */
2474 
2475 /* Bit fields for MSC IF */
2476 #define _MSC_IF_RESETVALUE                                0x00000000UL                      /**< Default value for MSC_IF */
2477 #define _MSC_IF_MASK                                      0x003F017FUL                      /**< Mask for MSC_IF */
2478 #define MSC_IF_ERASE                                      (0x1UL << 0)                      /**< Erase Done Interrupt Read Flag */
2479 #define _MSC_IF_ERASE_SHIFT                               0                                 /**< Shift value for MSC_ERASE */
2480 #define _MSC_IF_ERASE_MASK                                0x1UL                             /**< Bit mask for MSC_ERASE */
2481 #define _MSC_IF_ERASE_DEFAULT                             0x00000000UL                      /**< Mode DEFAULT for MSC_IF */
2482 #define MSC_IF_ERASE_DEFAULT                              (_MSC_IF_ERASE_DEFAULT << 0)      /**< Shifted mode DEFAULT for MSC_IF */
2483 #define MSC_IF_WRITE                                      (0x1UL << 1)                      /**< Write Done Interrupt Read Flag */
2484 #define _MSC_IF_WRITE_SHIFT                               1                                 /**< Shift value for MSC_WRITE */
2485 #define _MSC_IF_WRITE_MASK                                0x2UL                             /**< Bit mask for MSC_WRITE */
2486 #define _MSC_IF_WRITE_DEFAULT                             0x00000000UL                      /**< Mode DEFAULT for MSC_IF */
2487 #define MSC_IF_WRITE_DEFAULT                              (_MSC_IF_WRITE_DEFAULT << 1)      /**< Shifted mode DEFAULT for MSC_IF */
2488 #define MSC_IF_CHOF                                       (0x1UL << 2)                      /**< Cache Hits Overflow Interrupt Flag */
2489 #define _MSC_IF_CHOF_SHIFT                                2                                 /**< Shift value for MSC_CHOF */
2490 #define _MSC_IF_CHOF_MASK                                 0x4UL                             /**< Bit mask for MSC_CHOF */
2491 #define _MSC_IF_CHOF_DEFAULT                              0x00000000UL                      /**< Mode DEFAULT for MSC_IF */
2492 #define MSC_IF_CHOF_DEFAULT                               (_MSC_IF_CHOF_DEFAULT << 2)       /**< Shifted mode DEFAULT for MSC_IF */
2493 #define MSC_IF_CMOF                                       (0x1UL << 3)                      /**< Cache Misses Overflow Interrupt Flag */
2494 #define _MSC_IF_CMOF_SHIFT                                3                                 /**< Shift value for MSC_CMOF */
2495 #define _MSC_IF_CMOF_MASK                                 0x8UL                             /**< Bit mask for MSC_CMOF */
2496 #define _MSC_IF_CMOF_DEFAULT                              0x00000000UL                      /**< Mode DEFAULT for MSC_IF */
2497 #define MSC_IF_CMOF_DEFAULT                               (_MSC_IF_CMOF_DEFAULT << 3)       /**< Shifted mode DEFAULT for MSC_IF */
2498 #define MSC_IF_PWRUPF                                     (0x1UL << 4)                      /**< Flash Power Up Sequence Complete Flag */
2499 #define _MSC_IF_PWRUPF_SHIFT                              4                                 /**< Shift value for MSC_PWRUPF */
2500 #define _MSC_IF_PWRUPF_MASK                               0x10UL                            /**< Bit mask for MSC_PWRUPF */
2501 #define _MSC_IF_PWRUPF_DEFAULT                            0x00000000UL                      /**< Mode DEFAULT for MSC_IF */
2502 #define MSC_IF_PWRUPF_DEFAULT                             (_MSC_IF_PWRUPF_DEFAULT << 4)     /**< Shifted mode DEFAULT for MSC_IF */
2503 #define MSC_IF_ICACHERR                                   (0x1UL << 5)                      /**< ICache RAM Parity Error Flag */
2504 #define _MSC_IF_ICACHERR_SHIFT                            5                                 /**< Shift value for MSC_ICACHERR */
2505 #define _MSC_IF_ICACHERR_MASK                             0x20UL                            /**< Bit mask for MSC_ICACHERR */
2506 #define _MSC_IF_ICACHERR_DEFAULT                          0x00000000UL                      /**< Mode DEFAULT for MSC_IF */
2507 #define MSC_IF_ICACHERR_DEFAULT                           (_MSC_IF_ICACHERR_DEFAULT << 5)   /**< Shifted mode DEFAULT for MSC_IF */
2508 #define MSC_IF_WDATAOV                                    (0x1UL << 6)                      /**< Flash Controller Write Buffer Overflow */
2509 #define _MSC_IF_WDATAOV_SHIFT                             6                                 /**< Shift value for MSC_WDATAOV */
2510 #define _MSC_IF_WDATAOV_MASK                              0x40UL                            /**< Bit mask for MSC_WDATAOV */
2511 #define _MSC_IF_WDATAOV_DEFAULT                           0x00000000UL                      /**< Mode DEFAULT for MSC_IF */
2512 #define MSC_IF_WDATAOV_DEFAULT                            (_MSC_IF_WDATAOV_DEFAULT << 6)    /**< Shifted mode DEFAULT for MSC_IF */
2513 #define MSC_IF_LVEWRITE                                   (0x1UL << 8)                      /**< Flash LVE Write Error Flag */
2514 #define _MSC_IF_LVEWRITE_SHIFT                            8                                 /**< Shift value for MSC_LVEWRITE */
2515 #define _MSC_IF_LVEWRITE_MASK                             0x100UL                           /**< Bit mask for MSC_LVEWRITE */
2516 #define _MSC_IF_LVEWRITE_DEFAULT                          0x00000000UL                      /**< Mode DEFAULT for MSC_IF */
2517 #define MSC_IF_LVEWRITE_DEFAULT                           (_MSC_IF_LVEWRITE_DEFAULT << 8)   /**< Shifted mode DEFAULT for MSC_IF */
2518 #define MSC_IF_RAMERR1B                                   (0x1UL << 16)                     /**< RAM 1-bit ECC Error Interrupt Flag */
2519 #define _MSC_IF_RAMERR1B_SHIFT                            16                                /**< Shift value for MSC_RAMERR1B */
2520 #define _MSC_IF_RAMERR1B_MASK                             0x10000UL                         /**< Bit mask for MSC_RAMERR1B */
2521 #define _MSC_IF_RAMERR1B_DEFAULT                          0x00000000UL                      /**< Mode DEFAULT for MSC_IF */
2522 #define MSC_IF_RAMERR1B_DEFAULT                           (_MSC_IF_RAMERR1B_DEFAULT << 16)  /**< Shifted mode DEFAULT for MSC_IF */
2523 #define MSC_IF_RAMERR2B                                   (0x1UL << 17)                     /**< RAM 2-bit ECC Error Interrupt Flag */
2524 #define _MSC_IF_RAMERR2B_SHIFT                            17                                /**< Shift value for MSC_RAMERR2B */
2525 #define _MSC_IF_RAMERR2B_MASK                             0x20000UL                         /**< Bit mask for MSC_RAMERR2B */
2526 #define _MSC_IF_RAMERR2B_DEFAULT                          0x00000000UL                      /**< Mode DEFAULT for MSC_IF */
2527 #define MSC_IF_RAMERR2B_DEFAULT                           (_MSC_IF_RAMERR2B_DEFAULT << 17)  /**< Shifted mode DEFAULT for MSC_IF */
2528 #define MSC_IF_RAM1ERR1B                                  (0x1UL << 18)                     /**< RAM1 1-bit ECC Error Interrupt Flag */
2529 #define _MSC_IF_RAM1ERR1B_SHIFT                           18                                /**< Shift value for MSC_RAM1ERR1B */
2530 #define _MSC_IF_RAM1ERR1B_MASK                            0x40000UL                         /**< Bit mask for MSC_RAM1ERR1B */
2531 #define _MSC_IF_RAM1ERR1B_DEFAULT                         0x00000000UL                      /**< Mode DEFAULT for MSC_IF */
2532 #define MSC_IF_RAM1ERR1B_DEFAULT                          (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */
2533 #define MSC_IF_RAM1ERR2B                                  (0x1UL << 19)                     /**< RAM1 2-bit ECC Error Interrupt Flag */
2534 #define _MSC_IF_RAM1ERR2B_SHIFT                           19                                /**< Shift value for MSC_RAM1ERR2B */
2535 #define _MSC_IF_RAM1ERR2B_MASK                            0x80000UL                         /**< Bit mask for MSC_RAM1ERR2B */
2536 #define _MSC_IF_RAM1ERR2B_DEFAULT                         0x00000000UL                      /**< Mode DEFAULT for MSC_IF */
2537 #define MSC_IF_RAM1ERR2B_DEFAULT                          (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */
2538 #define MSC_IF_RAM2ERR1B                                  (0x1UL << 20)                     /**< RAM2 1-bit ECC Error Interrupt Flag */
2539 #define _MSC_IF_RAM2ERR1B_SHIFT                           20                                /**< Shift value for MSC_RAM2ERR1B */
2540 #define _MSC_IF_RAM2ERR1B_MASK                            0x100000UL                        /**< Bit mask for MSC_RAM2ERR1B */
2541 #define _MSC_IF_RAM2ERR1B_DEFAULT                         0x00000000UL                      /**< Mode DEFAULT for MSC_IF */
2542 #define MSC_IF_RAM2ERR1B_DEFAULT                          (_MSC_IF_RAM2ERR1B_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_IF */
2543 #define MSC_IF_RAM2ERR2B                                  (0x1UL << 21)                     /**< RAM2 2-bit ECC Error Interrupt Flag */
2544 #define _MSC_IF_RAM2ERR2B_SHIFT                           21                                /**< Shift value for MSC_RAM2ERR2B */
2545 #define _MSC_IF_RAM2ERR2B_MASK                            0x200000UL                        /**< Bit mask for MSC_RAM2ERR2B */
2546 #define _MSC_IF_RAM2ERR2B_DEFAULT                         0x00000000UL                      /**< Mode DEFAULT for MSC_IF */
2547 #define MSC_IF_RAM2ERR2B_DEFAULT                          (_MSC_IF_RAM2ERR2B_DEFAULT << 21) /**< Shifted mode DEFAULT for MSC_IF */
2548 
2549 /* Bit fields for MSC IFS */
2550 #define _MSC_IFS_RESETVALUE                               0x00000000UL                       /**< Default value for MSC_IFS */
2551 #define _MSC_IFS_MASK                                     0x003F017FUL                       /**< Mask for MSC_IFS */
2552 #define MSC_IFS_ERASE                                     (0x1UL << 0)                       /**< Set ERASE Interrupt Flag */
2553 #define _MSC_IFS_ERASE_SHIFT                              0                                  /**< Shift value for MSC_ERASE */
2554 #define _MSC_IFS_ERASE_MASK                               0x1UL                              /**< Bit mask for MSC_ERASE */
2555 #define _MSC_IFS_ERASE_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for MSC_IFS */
2556 #define MSC_IFS_ERASE_DEFAULT                             (_MSC_IFS_ERASE_DEFAULT << 0)      /**< Shifted mode DEFAULT for MSC_IFS */
2557 #define MSC_IFS_WRITE                                     (0x1UL << 1)                       /**< Set WRITE Interrupt Flag */
2558 #define _MSC_IFS_WRITE_SHIFT                              1                                  /**< Shift value for MSC_WRITE */
2559 #define _MSC_IFS_WRITE_MASK                               0x2UL                              /**< Bit mask for MSC_WRITE */
2560 #define _MSC_IFS_WRITE_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for MSC_IFS */
2561 #define MSC_IFS_WRITE_DEFAULT                             (_MSC_IFS_WRITE_DEFAULT << 1)      /**< Shifted mode DEFAULT for MSC_IFS */
2562 #define MSC_IFS_CHOF                                      (0x1UL << 2)                       /**< Set CHOF Interrupt Flag */
2563 #define _MSC_IFS_CHOF_SHIFT                               2                                  /**< Shift value for MSC_CHOF */
2564 #define _MSC_IFS_CHOF_MASK                                0x4UL                              /**< Bit mask for MSC_CHOF */
2565 #define _MSC_IFS_CHOF_DEFAULT                             0x00000000UL                       /**< Mode DEFAULT for MSC_IFS */
2566 #define MSC_IFS_CHOF_DEFAULT                              (_MSC_IFS_CHOF_DEFAULT << 2)       /**< Shifted mode DEFAULT for MSC_IFS */
2567 #define MSC_IFS_CMOF                                      (0x1UL << 3)                       /**< Set CMOF Interrupt Flag */
2568 #define _MSC_IFS_CMOF_SHIFT                               3                                  /**< Shift value for MSC_CMOF */
2569 #define _MSC_IFS_CMOF_MASK                                0x8UL                              /**< Bit mask for MSC_CMOF */
2570 #define _MSC_IFS_CMOF_DEFAULT                             0x00000000UL                       /**< Mode DEFAULT for MSC_IFS */
2571 #define MSC_IFS_CMOF_DEFAULT                              (_MSC_IFS_CMOF_DEFAULT << 3)       /**< Shifted mode DEFAULT for MSC_IFS */
2572 #define MSC_IFS_PWRUPF                                    (0x1UL << 4)                       /**< Set PWRUPF Interrupt Flag */
2573 #define _MSC_IFS_PWRUPF_SHIFT                             4                                  /**< Shift value for MSC_PWRUPF */
2574 #define _MSC_IFS_PWRUPF_MASK                              0x10UL                             /**< Bit mask for MSC_PWRUPF */
2575 #define _MSC_IFS_PWRUPF_DEFAULT                           0x00000000UL                       /**< Mode DEFAULT for MSC_IFS */
2576 #define MSC_IFS_PWRUPF_DEFAULT                            (_MSC_IFS_PWRUPF_DEFAULT << 4)     /**< Shifted mode DEFAULT for MSC_IFS */
2577 #define MSC_IFS_ICACHERR                                  (0x1UL << 5)                       /**< Set ICACHERR Interrupt Flag */
2578 #define _MSC_IFS_ICACHERR_SHIFT                           5                                  /**< Shift value for MSC_ICACHERR */
2579 #define _MSC_IFS_ICACHERR_MASK                            0x20UL                             /**< Bit mask for MSC_ICACHERR */
2580 #define _MSC_IFS_ICACHERR_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for MSC_IFS */
2581 #define MSC_IFS_ICACHERR_DEFAULT                          (_MSC_IFS_ICACHERR_DEFAULT << 5)   /**< Shifted mode DEFAULT for MSC_IFS */
2582 #define MSC_IFS_WDATAOV                                   (0x1UL << 6)                       /**< Set WDATAOV Interrupt Flag */
2583 #define _MSC_IFS_WDATAOV_SHIFT                            6                                  /**< Shift value for MSC_WDATAOV */
2584 #define _MSC_IFS_WDATAOV_MASK                             0x40UL                             /**< Bit mask for MSC_WDATAOV */
2585 #define _MSC_IFS_WDATAOV_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for MSC_IFS */
2586 #define MSC_IFS_WDATAOV_DEFAULT                           (_MSC_IFS_WDATAOV_DEFAULT << 6)    /**< Shifted mode DEFAULT for MSC_IFS */
2587 #define MSC_IFS_LVEWRITE                                  (0x1UL << 8)                       /**< Set LVEWRITE Interrupt Flag */
2588 #define _MSC_IFS_LVEWRITE_SHIFT                           8                                  /**< Shift value for MSC_LVEWRITE */
2589 #define _MSC_IFS_LVEWRITE_MASK                            0x100UL                            /**< Bit mask for MSC_LVEWRITE */
2590 #define _MSC_IFS_LVEWRITE_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for MSC_IFS */
2591 #define MSC_IFS_LVEWRITE_DEFAULT                          (_MSC_IFS_LVEWRITE_DEFAULT << 8)   /**< Shifted mode DEFAULT for MSC_IFS */
2592 #define MSC_IFS_RAMERR1B                                  (0x1UL << 16)                      /**< Set RAMERR1B Interrupt Flag */
2593 #define _MSC_IFS_RAMERR1B_SHIFT                           16                                 /**< Shift value for MSC_RAMERR1B */
2594 #define _MSC_IFS_RAMERR1B_MASK                            0x10000UL                          /**< Bit mask for MSC_RAMERR1B */
2595 #define _MSC_IFS_RAMERR1B_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for MSC_IFS */
2596 #define MSC_IFS_RAMERR1B_DEFAULT                          (_MSC_IFS_RAMERR1B_DEFAULT << 16)  /**< Shifted mode DEFAULT for MSC_IFS */
2597 #define MSC_IFS_RAMERR2B                                  (0x1UL << 17)                      /**< Set RAMERR2B Interrupt Flag */
2598 #define _MSC_IFS_RAMERR2B_SHIFT                           17                                 /**< Shift value for MSC_RAMERR2B */
2599 #define _MSC_IFS_RAMERR2B_MASK                            0x20000UL                          /**< Bit mask for MSC_RAMERR2B */
2600 #define _MSC_IFS_RAMERR2B_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for MSC_IFS */
2601 #define MSC_IFS_RAMERR2B_DEFAULT                          (_MSC_IFS_RAMERR2B_DEFAULT << 17)  /**< Shifted mode DEFAULT for MSC_IFS */
2602 #define MSC_IFS_RAM1ERR1B                                 (0x1UL << 18)                      /**< Set RAM1ERR1B Interrupt Flag */
2603 #define _MSC_IFS_RAM1ERR1B_SHIFT                          18                                 /**< Shift value for MSC_RAM1ERR1B */
2604 #define _MSC_IFS_RAM1ERR1B_MASK                           0x40000UL                          /**< Bit mask for MSC_RAM1ERR1B */
2605 #define _MSC_IFS_RAM1ERR1B_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for MSC_IFS */
2606 #define MSC_IFS_RAM1ERR1B_DEFAULT                         (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */
2607 #define MSC_IFS_RAM1ERR2B                                 (0x1UL << 19)                      /**< Set RAM1ERR2B Interrupt Flag */
2608 #define _MSC_IFS_RAM1ERR2B_SHIFT                          19                                 /**< Shift value for MSC_RAM1ERR2B */
2609 #define _MSC_IFS_RAM1ERR2B_MASK                           0x80000UL                          /**< Bit mask for MSC_RAM1ERR2B */
2610 #define _MSC_IFS_RAM1ERR2B_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for MSC_IFS */
2611 #define MSC_IFS_RAM1ERR2B_DEFAULT                         (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */
2612 #define MSC_IFS_RAM2ERR1B                                 (0x1UL << 20)                      /**< Set RAM2ERR1B Interrupt Flag */
2613 #define _MSC_IFS_RAM2ERR1B_SHIFT                          20                                 /**< Shift value for MSC_RAM2ERR1B */
2614 #define _MSC_IFS_RAM2ERR1B_MASK                           0x100000UL                         /**< Bit mask for MSC_RAM2ERR1B */
2615 #define _MSC_IFS_RAM2ERR1B_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for MSC_IFS */
2616 #define MSC_IFS_RAM2ERR1B_DEFAULT                         (_MSC_IFS_RAM2ERR1B_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_IFS */
2617 #define MSC_IFS_RAM2ERR2B                                 (0x1UL << 21)                      /**< Set RAM2ERR2B Interrupt Flag */
2618 #define _MSC_IFS_RAM2ERR2B_SHIFT                          21                                 /**< Shift value for MSC_RAM2ERR2B */
2619 #define _MSC_IFS_RAM2ERR2B_MASK                           0x200000UL                         /**< Bit mask for MSC_RAM2ERR2B */
2620 #define _MSC_IFS_RAM2ERR2B_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for MSC_IFS */
2621 #define MSC_IFS_RAM2ERR2B_DEFAULT                         (_MSC_IFS_RAM2ERR2B_DEFAULT << 21) /**< Shifted mode DEFAULT for MSC_IFS */
2622 
2623 /* Bit fields for MSC IFC */
2624 #define _MSC_IFC_RESETVALUE                               0x00000000UL                       /**< Default value for MSC_IFC */
2625 #define _MSC_IFC_MASK                                     0x003F017FUL                       /**< Mask for MSC_IFC */
2626 #define MSC_IFC_ERASE                                     (0x1UL << 0)                       /**< Clear ERASE Interrupt Flag */
2627 #define _MSC_IFC_ERASE_SHIFT                              0                                  /**< Shift value for MSC_ERASE */
2628 #define _MSC_IFC_ERASE_MASK                               0x1UL                              /**< Bit mask for MSC_ERASE */
2629 #define _MSC_IFC_ERASE_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for MSC_IFC */
2630 #define MSC_IFC_ERASE_DEFAULT                             (_MSC_IFC_ERASE_DEFAULT << 0)      /**< Shifted mode DEFAULT for MSC_IFC */
2631 #define MSC_IFC_WRITE                                     (0x1UL << 1)                       /**< Clear WRITE Interrupt Flag */
2632 #define _MSC_IFC_WRITE_SHIFT                              1                                  /**< Shift value for MSC_WRITE */
2633 #define _MSC_IFC_WRITE_MASK                               0x2UL                              /**< Bit mask for MSC_WRITE */
2634 #define _MSC_IFC_WRITE_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for MSC_IFC */
2635 #define MSC_IFC_WRITE_DEFAULT                             (_MSC_IFC_WRITE_DEFAULT << 1)      /**< Shifted mode DEFAULT for MSC_IFC */
2636 #define MSC_IFC_CHOF                                      (0x1UL << 2)                       /**< Clear CHOF Interrupt Flag */
2637 #define _MSC_IFC_CHOF_SHIFT                               2                                  /**< Shift value for MSC_CHOF */
2638 #define _MSC_IFC_CHOF_MASK                                0x4UL                              /**< Bit mask for MSC_CHOF */
2639 #define _MSC_IFC_CHOF_DEFAULT                             0x00000000UL                       /**< Mode DEFAULT for MSC_IFC */
2640 #define MSC_IFC_CHOF_DEFAULT                              (_MSC_IFC_CHOF_DEFAULT << 2)       /**< Shifted mode DEFAULT for MSC_IFC */
2641 #define MSC_IFC_CMOF                                      (0x1UL << 3)                       /**< Clear CMOF Interrupt Flag */
2642 #define _MSC_IFC_CMOF_SHIFT                               3                                  /**< Shift value for MSC_CMOF */
2643 #define _MSC_IFC_CMOF_MASK                                0x8UL                              /**< Bit mask for MSC_CMOF */
2644 #define _MSC_IFC_CMOF_DEFAULT                             0x00000000UL                       /**< Mode DEFAULT for MSC_IFC */
2645 #define MSC_IFC_CMOF_DEFAULT                              (_MSC_IFC_CMOF_DEFAULT << 3)       /**< Shifted mode DEFAULT for MSC_IFC */
2646 #define MSC_IFC_PWRUPF                                    (0x1UL << 4)                       /**< Clear PWRUPF Interrupt Flag */
2647 #define _MSC_IFC_PWRUPF_SHIFT                             4                                  /**< Shift value for MSC_PWRUPF */
2648 #define _MSC_IFC_PWRUPF_MASK                              0x10UL                             /**< Bit mask for MSC_PWRUPF */
2649 #define _MSC_IFC_PWRUPF_DEFAULT                           0x00000000UL                       /**< Mode DEFAULT for MSC_IFC */
2650 #define MSC_IFC_PWRUPF_DEFAULT                            (_MSC_IFC_PWRUPF_DEFAULT << 4)     /**< Shifted mode DEFAULT for MSC_IFC */
2651 #define MSC_IFC_ICACHERR                                  (0x1UL << 5)                       /**< Clear ICACHERR Interrupt Flag */
2652 #define _MSC_IFC_ICACHERR_SHIFT                           5                                  /**< Shift value for MSC_ICACHERR */
2653 #define _MSC_IFC_ICACHERR_MASK                            0x20UL                             /**< Bit mask for MSC_ICACHERR */
2654 #define _MSC_IFC_ICACHERR_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for MSC_IFC */
2655 #define MSC_IFC_ICACHERR_DEFAULT                          (_MSC_IFC_ICACHERR_DEFAULT << 5)   /**< Shifted mode DEFAULT for MSC_IFC */
2656 #define MSC_IFC_WDATAOV                                   (0x1UL << 6)                       /**< Clear WDATAOV Interrupt Flag */
2657 #define _MSC_IFC_WDATAOV_SHIFT                            6                                  /**< Shift value for MSC_WDATAOV */
2658 #define _MSC_IFC_WDATAOV_MASK                             0x40UL                             /**< Bit mask for MSC_WDATAOV */
2659 #define _MSC_IFC_WDATAOV_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for MSC_IFC */
2660 #define MSC_IFC_WDATAOV_DEFAULT                           (_MSC_IFC_WDATAOV_DEFAULT << 6)    /**< Shifted mode DEFAULT for MSC_IFC */
2661 #define MSC_IFC_LVEWRITE                                  (0x1UL << 8)                       /**< Clear LVEWRITE Interrupt Flag */
2662 #define _MSC_IFC_LVEWRITE_SHIFT                           8                                  /**< Shift value for MSC_LVEWRITE */
2663 #define _MSC_IFC_LVEWRITE_MASK                            0x100UL                            /**< Bit mask for MSC_LVEWRITE */
2664 #define _MSC_IFC_LVEWRITE_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for MSC_IFC */
2665 #define MSC_IFC_LVEWRITE_DEFAULT                          (_MSC_IFC_LVEWRITE_DEFAULT << 8)   /**< Shifted mode DEFAULT for MSC_IFC */
2666 #define MSC_IFC_RAMERR1B                                  (0x1UL << 16)                      /**< Clear RAMERR1B Interrupt Flag */
2667 #define _MSC_IFC_RAMERR1B_SHIFT                           16                                 /**< Shift value for MSC_RAMERR1B */
2668 #define _MSC_IFC_RAMERR1B_MASK                            0x10000UL                          /**< Bit mask for MSC_RAMERR1B */
2669 #define _MSC_IFC_RAMERR1B_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for MSC_IFC */
2670 #define MSC_IFC_RAMERR1B_DEFAULT                          (_MSC_IFC_RAMERR1B_DEFAULT << 16)  /**< Shifted mode DEFAULT for MSC_IFC */
2671 #define MSC_IFC_RAMERR2B                                  (0x1UL << 17)                      /**< Clear RAMERR2B Interrupt Flag */
2672 #define _MSC_IFC_RAMERR2B_SHIFT                           17                                 /**< Shift value for MSC_RAMERR2B */
2673 #define _MSC_IFC_RAMERR2B_MASK                            0x20000UL                          /**< Bit mask for MSC_RAMERR2B */
2674 #define _MSC_IFC_RAMERR2B_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for MSC_IFC */
2675 #define MSC_IFC_RAMERR2B_DEFAULT                          (_MSC_IFC_RAMERR2B_DEFAULT << 17)  /**< Shifted mode DEFAULT for MSC_IFC */
2676 #define MSC_IFC_RAM1ERR1B                                 (0x1UL << 18)                      /**< Clear RAM1ERR1B Interrupt Flag */
2677 #define _MSC_IFC_RAM1ERR1B_SHIFT                          18                                 /**< Shift value for MSC_RAM1ERR1B */
2678 #define _MSC_IFC_RAM1ERR1B_MASK                           0x40000UL                          /**< Bit mask for MSC_RAM1ERR1B */
2679 #define _MSC_IFC_RAM1ERR1B_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for MSC_IFC */
2680 #define MSC_IFC_RAM1ERR1B_DEFAULT                         (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */
2681 #define MSC_IFC_RAM1ERR2B                                 (0x1UL << 19)                      /**< Clear RAM1ERR2B Interrupt Flag */
2682 #define _MSC_IFC_RAM1ERR2B_SHIFT                          19                                 /**< Shift value for MSC_RAM1ERR2B */
2683 #define _MSC_IFC_RAM1ERR2B_MASK                           0x80000UL                          /**< Bit mask for MSC_RAM1ERR2B */
2684 #define _MSC_IFC_RAM1ERR2B_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for MSC_IFC */
2685 #define MSC_IFC_RAM1ERR2B_DEFAULT                         (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */
2686 #define MSC_IFC_RAM2ERR1B                                 (0x1UL << 20)                      /**< Clear RAM2ERR1B Interrupt Flag */
2687 #define _MSC_IFC_RAM2ERR1B_SHIFT                          20                                 /**< Shift value for MSC_RAM2ERR1B */
2688 #define _MSC_IFC_RAM2ERR1B_MASK                           0x100000UL                         /**< Bit mask for MSC_RAM2ERR1B */
2689 #define _MSC_IFC_RAM2ERR1B_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for MSC_IFC */
2690 #define MSC_IFC_RAM2ERR1B_DEFAULT                         (_MSC_IFC_RAM2ERR1B_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_IFC */
2691 #define MSC_IFC_RAM2ERR2B                                 (0x1UL << 21)                      /**< Clear RAM2ERR2B Interrupt Flag */
2692 #define _MSC_IFC_RAM2ERR2B_SHIFT                          21                                 /**< Shift value for MSC_RAM2ERR2B */
2693 #define _MSC_IFC_RAM2ERR2B_MASK                           0x200000UL                         /**< Bit mask for MSC_RAM2ERR2B */
2694 #define _MSC_IFC_RAM2ERR2B_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for MSC_IFC */
2695 #define MSC_IFC_RAM2ERR2B_DEFAULT                         (_MSC_IFC_RAM2ERR2B_DEFAULT << 21) /**< Shifted mode DEFAULT for MSC_IFC */
2696 
2697 /* Bit fields for MSC IEN */
2698 #define _MSC_IEN_RESETVALUE                               0x00000000UL                       /**< Default value for MSC_IEN */
2699 #define _MSC_IEN_MASK                                     0x003F017FUL                       /**< Mask for MSC_IEN */
2700 #define MSC_IEN_ERASE                                     (0x1UL << 0)                       /**< ERASE Interrupt Enable */
2701 #define _MSC_IEN_ERASE_SHIFT                              0                                  /**< Shift value for MSC_ERASE */
2702 #define _MSC_IEN_ERASE_MASK                               0x1UL                              /**< Bit mask for MSC_ERASE */
2703 #define _MSC_IEN_ERASE_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for MSC_IEN */
2704 #define MSC_IEN_ERASE_DEFAULT                             (_MSC_IEN_ERASE_DEFAULT << 0)      /**< Shifted mode DEFAULT for MSC_IEN */
2705 #define MSC_IEN_WRITE                                     (0x1UL << 1)                       /**< WRITE Interrupt Enable */
2706 #define _MSC_IEN_WRITE_SHIFT                              1                                  /**< Shift value for MSC_WRITE */
2707 #define _MSC_IEN_WRITE_MASK                               0x2UL                              /**< Bit mask for MSC_WRITE */
2708 #define _MSC_IEN_WRITE_DEFAULT                            0x00000000UL                       /**< Mode DEFAULT for MSC_IEN */
2709 #define MSC_IEN_WRITE_DEFAULT                             (_MSC_IEN_WRITE_DEFAULT << 1)      /**< Shifted mode DEFAULT for MSC_IEN */
2710 #define MSC_IEN_CHOF                                      (0x1UL << 2)                       /**< CHOF Interrupt Enable */
2711 #define _MSC_IEN_CHOF_SHIFT                               2                                  /**< Shift value for MSC_CHOF */
2712 #define _MSC_IEN_CHOF_MASK                                0x4UL                              /**< Bit mask for MSC_CHOF */
2713 #define _MSC_IEN_CHOF_DEFAULT                             0x00000000UL                       /**< Mode DEFAULT for MSC_IEN */
2714 #define MSC_IEN_CHOF_DEFAULT                              (_MSC_IEN_CHOF_DEFAULT << 2)       /**< Shifted mode DEFAULT for MSC_IEN */
2715 #define MSC_IEN_CMOF                                      (0x1UL << 3)                       /**< CMOF Interrupt Enable */
2716 #define _MSC_IEN_CMOF_SHIFT                               3                                  /**< Shift value for MSC_CMOF */
2717 #define _MSC_IEN_CMOF_MASK                                0x8UL                              /**< Bit mask for MSC_CMOF */
2718 #define _MSC_IEN_CMOF_DEFAULT                             0x00000000UL                       /**< Mode DEFAULT for MSC_IEN */
2719 #define MSC_IEN_CMOF_DEFAULT                              (_MSC_IEN_CMOF_DEFAULT << 3)       /**< Shifted mode DEFAULT for MSC_IEN */
2720 #define MSC_IEN_PWRUPF                                    (0x1UL << 4)                       /**< PWRUPF Interrupt Enable */
2721 #define _MSC_IEN_PWRUPF_SHIFT                             4                                  /**< Shift value for MSC_PWRUPF */
2722 #define _MSC_IEN_PWRUPF_MASK                              0x10UL                             /**< Bit mask for MSC_PWRUPF */
2723 #define _MSC_IEN_PWRUPF_DEFAULT                           0x00000000UL                       /**< Mode DEFAULT for MSC_IEN */
2724 #define MSC_IEN_PWRUPF_DEFAULT                            (_MSC_IEN_PWRUPF_DEFAULT << 4)     /**< Shifted mode DEFAULT for MSC_IEN */
2725 #define MSC_IEN_ICACHERR                                  (0x1UL << 5)                       /**< ICACHERR Interrupt Enable */
2726 #define _MSC_IEN_ICACHERR_SHIFT                           5                                  /**< Shift value for MSC_ICACHERR */
2727 #define _MSC_IEN_ICACHERR_MASK                            0x20UL                             /**< Bit mask for MSC_ICACHERR */
2728 #define _MSC_IEN_ICACHERR_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for MSC_IEN */
2729 #define MSC_IEN_ICACHERR_DEFAULT                          (_MSC_IEN_ICACHERR_DEFAULT << 5)   /**< Shifted mode DEFAULT for MSC_IEN */
2730 #define MSC_IEN_WDATAOV                                   (0x1UL << 6)                       /**< WDATAOV Interrupt Enable */
2731 #define _MSC_IEN_WDATAOV_SHIFT                            6                                  /**< Shift value for MSC_WDATAOV */
2732 #define _MSC_IEN_WDATAOV_MASK                             0x40UL                             /**< Bit mask for MSC_WDATAOV */
2733 #define _MSC_IEN_WDATAOV_DEFAULT                          0x00000000UL                       /**< Mode DEFAULT for MSC_IEN */
2734 #define MSC_IEN_WDATAOV_DEFAULT                           (_MSC_IEN_WDATAOV_DEFAULT << 6)    /**< Shifted mode DEFAULT for MSC_IEN */
2735 #define MSC_IEN_LVEWRITE                                  (0x1UL << 8)                       /**< LVEWRITE Interrupt Enable */
2736 #define _MSC_IEN_LVEWRITE_SHIFT                           8                                  /**< Shift value for MSC_LVEWRITE */
2737 #define _MSC_IEN_LVEWRITE_MASK                            0x100UL                            /**< Bit mask for MSC_LVEWRITE */
2738 #define _MSC_IEN_LVEWRITE_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for MSC_IEN */
2739 #define MSC_IEN_LVEWRITE_DEFAULT                          (_MSC_IEN_LVEWRITE_DEFAULT << 8)   /**< Shifted mode DEFAULT for MSC_IEN */
2740 #define MSC_IEN_RAMERR1B                                  (0x1UL << 16)                      /**< RAMERR1B Interrupt Enable */
2741 #define _MSC_IEN_RAMERR1B_SHIFT                           16                                 /**< Shift value for MSC_RAMERR1B */
2742 #define _MSC_IEN_RAMERR1B_MASK                            0x10000UL                          /**< Bit mask for MSC_RAMERR1B */
2743 #define _MSC_IEN_RAMERR1B_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for MSC_IEN */
2744 #define MSC_IEN_RAMERR1B_DEFAULT                          (_MSC_IEN_RAMERR1B_DEFAULT << 16)  /**< Shifted mode DEFAULT for MSC_IEN */
2745 #define MSC_IEN_RAMERR2B                                  (0x1UL << 17)                      /**< RAMERR2B Interrupt Enable */
2746 #define _MSC_IEN_RAMERR2B_SHIFT                           17                                 /**< Shift value for MSC_RAMERR2B */
2747 #define _MSC_IEN_RAMERR2B_MASK                            0x20000UL                          /**< Bit mask for MSC_RAMERR2B */
2748 #define _MSC_IEN_RAMERR2B_DEFAULT                         0x00000000UL                       /**< Mode DEFAULT for MSC_IEN */
2749 #define MSC_IEN_RAMERR2B_DEFAULT                          (_MSC_IEN_RAMERR2B_DEFAULT << 17)  /**< Shifted mode DEFAULT for MSC_IEN */
2750 #define MSC_IEN_RAM1ERR1B                                 (0x1UL << 18)                      /**< RAM1ERR1B Interrupt Enable */
2751 #define _MSC_IEN_RAM1ERR1B_SHIFT                          18                                 /**< Shift value for MSC_RAM1ERR1B */
2752 #define _MSC_IEN_RAM1ERR1B_MASK                           0x40000UL                          /**< Bit mask for MSC_RAM1ERR1B */
2753 #define _MSC_IEN_RAM1ERR1B_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for MSC_IEN */
2754 #define MSC_IEN_RAM1ERR1B_DEFAULT                         (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */
2755 #define MSC_IEN_RAM1ERR2B                                 (0x1UL << 19)                      /**< RAM1ERR2B Interrupt Enable */
2756 #define _MSC_IEN_RAM1ERR2B_SHIFT                          19                                 /**< Shift value for MSC_RAM1ERR2B */
2757 #define _MSC_IEN_RAM1ERR2B_MASK                           0x80000UL                          /**< Bit mask for MSC_RAM1ERR2B */
2758 #define _MSC_IEN_RAM1ERR2B_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for MSC_IEN */
2759 #define MSC_IEN_RAM1ERR2B_DEFAULT                         (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */
2760 #define MSC_IEN_RAM2ERR1B                                 (0x1UL << 20)                      /**< RAM2ERR1B Interrupt Enable */
2761 #define _MSC_IEN_RAM2ERR1B_SHIFT                          20                                 /**< Shift value for MSC_RAM2ERR1B */
2762 #define _MSC_IEN_RAM2ERR1B_MASK                           0x100000UL                         /**< Bit mask for MSC_RAM2ERR1B */
2763 #define _MSC_IEN_RAM2ERR1B_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for MSC_IEN */
2764 #define MSC_IEN_RAM2ERR1B_DEFAULT                         (_MSC_IEN_RAM2ERR1B_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_IEN */
2765 #define MSC_IEN_RAM2ERR2B                                 (0x1UL << 21)                      /**< RAM2ERR2B Interrupt Enable */
2766 #define _MSC_IEN_RAM2ERR2B_SHIFT                          21                                 /**< Shift value for MSC_RAM2ERR2B */
2767 #define _MSC_IEN_RAM2ERR2B_MASK                           0x200000UL                         /**< Bit mask for MSC_RAM2ERR2B */
2768 #define _MSC_IEN_RAM2ERR2B_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for MSC_IEN */
2769 #define MSC_IEN_RAM2ERR2B_DEFAULT                         (_MSC_IEN_RAM2ERR2B_DEFAULT << 21) /**< Shifted mode DEFAULT for MSC_IEN */
2770 
2771 /* Bit fields for MSC LOCK */
2772 #define _MSC_LOCK_RESETVALUE                              0x00000000UL                      /**< Default value for MSC_LOCK */
2773 #define _MSC_LOCK_MASK                                    0x0000FFFFUL                      /**< Mask for MSC_LOCK */
2774 #define _MSC_LOCK_LOCKKEY_SHIFT                           0                                 /**< Shift value for MSC_LOCKKEY */
2775 #define _MSC_LOCK_LOCKKEY_MASK                            0xFFFFUL                          /**< Bit mask for MSC_LOCKKEY */
2776 #define _MSC_LOCK_LOCKKEY_DEFAULT                         0x00000000UL                      /**< Mode DEFAULT for MSC_LOCK */
2777 #define _MSC_LOCK_LOCKKEY_UNLOCKED                        0x00000000UL                      /**< Mode UNLOCKED for MSC_LOCK */
2778 #define _MSC_LOCK_LOCKKEY_LOCK                            0x00000000UL                      /**< Mode LOCK for MSC_LOCK */
2779 #define _MSC_LOCK_LOCKKEY_LOCKED                          0x00000001UL                      /**< Mode LOCKED for MSC_LOCK */
2780 #define _MSC_LOCK_LOCKKEY_UNLOCK                          0x00001B71UL                      /**< Mode UNLOCK for MSC_LOCK */
2781 #define MSC_LOCK_LOCKKEY_DEFAULT                          (_MSC_LOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for MSC_LOCK */
2782 #define MSC_LOCK_LOCKKEY_UNLOCKED                         (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
2783 #define MSC_LOCK_LOCKKEY_LOCK                             (_MSC_LOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for MSC_LOCK */
2784 #define MSC_LOCK_LOCKKEY_LOCKED                           (_MSC_LOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for MSC_LOCK */
2785 #define MSC_LOCK_LOCKKEY_UNLOCK                           (_MSC_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for MSC_LOCK */
2786 
2787 /* Bit fields for MSC CACHECMD */
2788 #define _MSC_CACHECMD_RESETVALUE                          0x00000000UL                          /**< Default value for MSC_CACHECMD */
2789 #define _MSC_CACHECMD_MASK                                0x00000007UL                          /**< Mask for MSC_CACHECMD */
2790 #define MSC_CACHECMD_INVCACHE                             (0x1UL << 0)                          /**< Invalidate Instruction Cache */
2791 #define _MSC_CACHECMD_INVCACHE_SHIFT                      0                                     /**< Shift value for MSC_INVCACHE */
2792 #define _MSC_CACHECMD_INVCACHE_MASK                       0x1UL                                 /**< Bit mask for MSC_INVCACHE */
2793 #define _MSC_CACHECMD_INVCACHE_DEFAULT                    0x00000000UL                          /**< Mode DEFAULT for MSC_CACHECMD */
2794 #define MSC_CACHECMD_INVCACHE_DEFAULT                     (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */
2795 #define MSC_CACHECMD_STARTPC                              (0x1UL << 1)                          /**< Start Performance Counters */
2796 #define _MSC_CACHECMD_STARTPC_SHIFT                       1                                     /**< Shift value for MSC_STARTPC */
2797 #define _MSC_CACHECMD_STARTPC_MASK                        0x2UL                                 /**< Bit mask for MSC_STARTPC */
2798 #define _MSC_CACHECMD_STARTPC_DEFAULT                     0x00000000UL                          /**< Mode DEFAULT for MSC_CACHECMD */
2799 #define MSC_CACHECMD_STARTPC_DEFAULT                      (_MSC_CACHECMD_STARTPC_DEFAULT << 1)  /**< Shifted mode DEFAULT for MSC_CACHECMD */
2800 #define MSC_CACHECMD_STOPPC                               (0x1UL << 2)                          /**< Stop Performance Counters */
2801 #define _MSC_CACHECMD_STOPPC_SHIFT                        2                                     /**< Shift value for MSC_STOPPC */
2802 #define _MSC_CACHECMD_STOPPC_MASK                         0x4UL                                 /**< Bit mask for MSC_STOPPC */
2803 #define _MSC_CACHECMD_STOPPC_DEFAULT                      0x00000000UL                          /**< Mode DEFAULT for MSC_CACHECMD */
2804 #define MSC_CACHECMD_STOPPC_DEFAULT                       (_MSC_CACHECMD_STOPPC_DEFAULT << 2)   /**< Shifted mode DEFAULT for MSC_CACHECMD */
2805 
2806 /* Bit fields for MSC CACHEHITS */
2807 #define _MSC_CACHEHITS_RESETVALUE                         0x00000000UL                            /**< Default value for MSC_CACHEHITS */
2808 #define _MSC_CACHEHITS_MASK                               0x000FFFFFUL                            /**< Mask for MSC_CACHEHITS */
2809 #define _MSC_CACHEHITS_CACHEHITS_SHIFT                    0                                       /**< Shift value for MSC_CACHEHITS */
2810 #define _MSC_CACHEHITS_CACHEHITS_MASK                     0xFFFFFUL                               /**< Bit mask for MSC_CACHEHITS */
2811 #define _MSC_CACHEHITS_CACHEHITS_DEFAULT                  0x00000000UL                            /**< Mode DEFAULT for MSC_CACHEHITS */
2812 #define MSC_CACHEHITS_CACHEHITS_DEFAULT                   (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */
2813 
2814 /* Bit fields for MSC CACHEMISSES */
2815 #define _MSC_CACHEMISSES_RESETVALUE                       0x00000000UL                                /**< Default value for MSC_CACHEMISSES */
2816 #define _MSC_CACHEMISSES_MASK                             0x000FFFFFUL                                /**< Mask for MSC_CACHEMISSES */
2817 #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT                0                                           /**< Shift value for MSC_CACHEMISSES */
2818 #define _MSC_CACHEMISSES_CACHEMISSES_MASK                 0xFFFFFUL                                   /**< Bit mask for MSC_CACHEMISSES */
2819 #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT              0x00000000UL                                /**< Mode DEFAULT for MSC_CACHEMISSES */
2820 #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT               (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */
2821 
2822 /* Bit fields for MSC MASSLOCK */
2823 #define _MSC_MASSLOCK_RESETVALUE                          0x00000001UL                          /**< Default value for MSC_MASSLOCK */
2824 #define _MSC_MASSLOCK_MASK                                0x0000FFFFUL                          /**< Mask for MSC_MASSLOCK */
2825 #define _MSC_MASSLOCK_LOCKKEY_SHIFT                       0                                     /**< Shift value for MSC_LOCKKEY */
2826 #define _MSC_MASSLOCK_LOCKKEY_MASK                        0xFFFFUL                              /**< Bit mask for MSC_LOCKKEY */
2827 #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED                    0x00000000UL                          /**< Mode UNLOCKED for MSC_MASSLOCK */
2828 #define _MSC_MASSLOCK_LOCKKEY_LOCK                        0x00000000UL                          /**< Mode LOCK for MSC_MASSLOCK */
2829 #define _MSC_MASSLOCK_LOCKKEY_DEFAULT                     0x00000001UL                          /**< Mode DEFAULT for MSC_MASSLOCK */
2830 #define _MSC_MASSLOCK_LOCKKEY_LOCKED                      0x00000001UL                          /**< Mode LOCKED for MSC_MASSLOCK */
2831 #define _MSC_MASSLOCK_LOCKKEY_UNLOCK                      0x0000631AUL                          /**< Mode UNLOCK for MSC_MASSLOCK */
2832 #define MSC_MASSLOCK_LOCKKEY_UNLOCKED                     (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
2833 #define MSC_MASSLOCK_LOCKKEY_LOCK                         (_MSC_MASSLOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for MSC_MASSLOCK */
2834 #define MSC_MASSLOCK_LOCKKEY_DEFAULT                      (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for MSC_MASSLOCK */
2835 #define MSC_MASSLOCK_LOCKKEY_LOCKED                       (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for MSC_MASSLOCK */
2836 #define MSC_MASSLOCK_LOCKKEY_UNLOCK                       (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for MSC_MASSLOCK */
2837 
2838 /* Bit fields for MSC STARTUP */
2839 #define _MSC_STARTUP_RESETVALUE                           0x1300104DUL                         /**< Default value for MSC_STARTUP */
2840 #define _MSC_STARTUP_MASK                                 0x773FF3FFUL                         /**< Mask for MSC_STARTUP */
2841 #define _MSC_STARTUP_STDLY0_SHIFT                         0                                    /**< Shift value for MSC_STDLY0 */
2842 #define _MSC_STARTUP_STDLY0_MASK                          0x3FFUL                              /**< Bit mask for MSC_STDLY0 */
2843 #define _MSC_STARTUP_STDLY0_DEFAULT                       0x0000004DUL                         /**< Mode DEFAULT for MSC_STARTUP */
2844 #define MSC_STARTUP_STDLY0_DEFAULT                        (_MSC_STARTUP_STDLY0_DEFAULT << 0)   /**< Shifted mode DEFAULT for MSC_STARTUP */
2845 #define _MSC_STARTUP_STDLY1_SHIFT                         12                                   /**< Shift value for MSC_STDLY1 */
2846 #define _MSC_STARTUP_STDLY1_MASK                          0x3FF000UL                           /**< Bit mask for MSC_STDLY1 */
2847 #define _MSC_STARTUP_STDLY1_DEFAULT                       0x00000001UL                         /**< Mode DEFAULT for MSC_STARTUP */
2848 #define MSC_STARTUP_STDLY1_DEFAULT                        (_MSC_STARTUP_STDLY1_DEFAULT << 12)  /**< Shifted mode DEFAULT for MSC_STARTUP */
2849 #define MSC_STARTUP_ASTWAIT                               (0x1UL << 24)                        /**< Active Startup Wait */
2850 #define _MSC_STARTUP_ASTWAIT_SHIFT                        24                                   /**< Shift value for MSC_ASTWAIT */
2851 #define _MSC_STARTUP_ASTWAIT_MASK                         0x1000000UL                          /**< Bit mask for MSC_ASTWAIT */
2852 #define _MSC_STARTUP_ASTWAIT_DEFAULT                      0x00000001UL                         /**< Mode DEFAULT for MSC_STARTUP */
2853 #define MSC_STARTUP_ASTWAIT_DEFAULT                       (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */
2854 #define MSC_STARTUP_STWSEN                                (0x1UL << 25)                        /**< Startup Waitstates Enable */
2855 #define _MSC_STARTUP_STWSEN_SHIFT                         25                                   /**< Shift value for MSC_STWSEN */
2856 #define _MSC_STARTUP_STWSEN_MASK                          0x2000000UL                          /**< Bit mask for MSC_STWSEN */
2857 #define _MSC_STARTUP_STWSEN_DEFAULT                       0x00000001UL                         /**< Mode DEFAULT for MSC_STARTUP */
2858 #define MSC_STARTUP_STWSEN_DEFAULT                        (_MSC_STARTUP_STWSEN_DEFAULT << 25)  /**< Shifted mode DEFAULT for MSC_STARTUP */
2859 #define MSC_STARTUP_STWSAEN                               (0x1UL << 26)                        /**< Startup Waitstates Always Enable */
2860 #define _MSC_STARTUP_STWSAEN_SHIFT                        26                                   /**< Shift value for MSC_STWSAEN */
2861 #define _MSC_STARTUP_STWSAEN_MASK                         0x4000000UL                          /**< Bit mask for MSC_STWSAEN */
2862 #define _MSC_STARTUP_STWSAEN_DEFAULT                      0x00000000UL                         /**< Mode DEFAULT for MSC_STARTUP */
2863 #define MSC_STARTUP_STWSAEN_DEFAULT                       (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */
2864 #define _MSC_STARTUP_STWS_SHIFT                           28                                   /**< Shift value for MSC_STWS */
2865 #define _MSC_STARTUP_STWS_MASK                            0x70000000UL                         /**< Bit mask for MSC_STWS */
2866 #define _MSC_STARTUP_STWS_DEFAULT                         0x00000001UL                         /**< Mode DEFAULT for MSC_STARTUP */
2867 #define MSC_STARTUP_STWS_DEFAULT                          (_MSC_STARTUP_STWS_DEFAULT << 28)    /**< Shifted mode DEFAULT for MSC_STARTUP */
2868 
2869 /* Bit fields for MSC BANKSWITCHLOCK */
2870 #define _MSC_BANKSWITCHLOCK_RESETVALUE                    0x00000001UL                                          /**< Default value for MSC_BANKSWITCHLOCK */
2871 #define _MSC_BANKSWITCHLOCK_MASK                          0x0000FFFFUL                                          /**< Mask for MSC_BANKSWITCHLOCK */
2872 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT       0                                                     /**< Shift value for MSC_BANKSWITCHLOCKKEY */
2873 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK        0xFFFFUL                                              /**< Bit mask for MSC_BANKSWITCHLOCKKEY */
2874 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED    0x00000000UL                                          /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */
2875 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK        0x00000000UL                                          /**< Mode LOCK for MSC_BANKSWITCHLOCK */
2876 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT     0x00000001UL                                          /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */
2877 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED      0x00000001UL                                          /**< Mode LOCKED for MSC_BANKSWITCHLOCK */
2878 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK      0x00007C2BUL                                          /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */
2879 #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED     (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */
2880 #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK         (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */
2881 #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT      (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */
2882 #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED       (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */
2883 #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK       (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */
2884 
2885 /* Bit fields for MSC CMD */
2886 #define _MSC_CMD_RESETVALUE                               0x00000000UL                          /**< Default value for MSC_CMD */
2887 #define _MSC_CMD_MASK                                     0x00000003UL                          /**< Mask for MSC_CMD */
2888 #define MSC_CMD_PWRUP                                     (0x1UL << 0)                          /**< Flash Power Up Command */
2889 #define _MSC_CMD_PWRUP_SHIFT                              0                                     /**< Shift value for MSC_PWRUP */
2890 #define _MSC_CMD_PWRUP_MASK                               0x1UL                                 /**< Bit mask for MSC_PWRUP */
2891 #define _MSC_CMD_PWRUP_DEFAULT                            0x00000000UL                          /**< Mode DEFAULT for MSC_CMD */
2892 #define MSC_CMD_PWRUP_DEFAULT                             (_MSC_CMD_PWRUP_DEFAULT << 0)         /**< Shifted mode DEFAULT for MSC_CMD */
2893 #define MSC_CMD_SWITCHINGBANK                             (0x1UL << 1)                          /**< BANK SWITCHING COMMAND */
2894 #define _MSC_CMD_SWITCHINGBANK_SHIFT                      1                                     /**< Shift value for MSC_SWITCHINGBANK */
2895 #define _MSC_CMD_SWITCHINGBANK_MASK                       0x2UL                                 /**< Bit mask for MSC_SWITCHINGBANK */
2896 #define _MSC_CMD_SWITCHINGBANK_DEFAULT                    0x00000000UL                          /**< Mode DEFAULT for MSC_CMD */
2897 #define MSC_CMD_SWITCHINGBANK_DEFAULT                     (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */
2898 
2899 /* Bit fields for MSC BOOTLOADERCTRL */
2900 #define _MSC_BOOTLOADERCTRL_RESETVALUE                    0x00000000UL                              /**< Default value for MSC_BOOTLOADERCTRL */
2901 #define _MSC_BOOTLOADERCTRL_MASK                          0x00000003UL                              /**< Mask for MSC_BOOTLOADERCTRL */
2902 #define MSC_BOOTLOADERCTRL_BLRDIS                         (0x1UL << 0)                              /**< Flash Bootloader Read Disable */
2903 #define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT                  0                                         /**< Shift value for MSC_BLRDIS */
2904 #define _MSC_BOOTLOADERCTRL_BLRDIS_MASK                   0x1UL                                     /**< Bit mask for MSC_BLRDIS */
2905 #define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */
2906 #define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT                 (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */
2907 #define MSC_BOOTLOADERCTRL_BLWDIS                         (0x1UL << 1)                              /**< Flash Bootloader Write/Erase Disable */
2908 #define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT                  1                                         /**< Shift value for MSC_BLWDIS */
2909 #define _MSC_BOOTLOADERCTRL_BLWDIS_MASK                   0x2UL                                     /**< Bit mask for MSC_BLWDIS */
2910 #define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */
2911 #define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT                 (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */
2912 
2913 /* Bit fields for MSC AAPUNLOCKCMD */
2914 #define _MSC_AAPUNLOCKCMD_RESETVALUE                      0x00000000UL                               /**< Default value for MSC_AAPUNLOCKCMD */
2915 #define _MSC_AAPUNLOCKCMD_MASK                            0x00000001UL                               /**< Mask for MSC_AAPUNLOCKCMD */
2916 #define MSC_AAPUNLOCKCMD_UNLOCKAAP                        (0x1UL << 0)                               /**< Software Unlock AAP Command */
2917 #define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT                 0                                          /**< Shift value for MSC_UNLOCKAAP */
2918 #define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK                  0x1UL                                      /**< Bit mask for MSC_UNLOCKAAP */
2919 #define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT               0x00000000UL                               /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */
2920 #define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT                (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */
2921 
2922 /* Bit fields for MSC CACHECONFIG0 */
2923 #define _MSC_CACHECONFIG0_RESETVALUE                      0x00000003UL                                      /**< Default value for MSC_CACHECONFIG0 */
2924 #define _MSC_CACHECONFIG0_MASK                            0x00000003UL                                      /**< Mask for MSC_CACHECONFIG0 */
2925 #define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT              0                                                 /**< Shift value for MSC_CACHELPLEVEL */
2926 #define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK               0x3UL                                             /**< Bit mask for MSC_CACHELPLEVEL */
2927 #define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE               0x00000000UL                                      /**< Mode BASE for MSC_CACHECONFIG0 */
2928 #define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED           0x00000001UL                                      /**< Mode ADVANCED for MSC_CACHECONFIG0 */
2929 #define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT            0x00000003UL                                      /**< Mode DEFAULT for MSC_CACHECONFIG0 */
2930 #define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY        0x00000003UL                                      /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */
2931 #define MSC_CACHECONFIG0_CACHELPLEVEL_BASE                (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0)        /**< Shifted mode BASE for MSC_CACHECONFIG0 */
2932 #define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED            (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0)    /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */
2933 #define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT             (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0)     /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */
2934 #define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY         (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */
2935 
2936 /* Bit fields for MSC RAMCTRL */
2937 #define _MSC_RAMCTRL_RESETVALUE                           0x00000000UL                                /**< Default value for MSC_RAMCTRL */
2938 #define _MSC_RAMCTRL_MASK                                 0x00060606UL                                /**< Mask for MSC_RAMCTRL */
2939 #define MSC_RAMCTRL_RAMWSEN                               (0x1UL << 1)                                /**< RAM WAIT STATE Enable */
2940 #define _MSC_RAMCTRL_RAMWSEN_SHIFT                        1                                           /**< Shift value for MSC_RAMWSEN */
2941 #define _MSC_RAMCTRL_RAMWSEN_MASK                         0x2UL                                       /**< Bit mask for MSC_RAMWSEN */
2942 #define _MSC_RAMCTRL_RAMWSEN_DEFAULT                      0x00000000UL                                /**< Mode DEFAULT for MSC_RAMCTRL */
2943 #define MSC_RAMCTRL_RAMWSEN_DEFAULT                       (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1)         /**< Shifted mode DEFAULT for MSC_RAMCTRL */
2944 #define MSC_RAMCTRL_RAMPREFETCHEN                         (0x1UL << 2)                                /**< RAM Prefetch Enable */
2945 #define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT                  2                                           /**< Shift value for MSC_RAMPREFETCHEN */
2946 #define _MSC_RAMCTRL_RAMPREFETCHEN_MASK                   0x4UL                                       /**< Bit mask for MSC_RAMPREFETCHEN */
2947 #define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT                0x00000000UL                                /**< Mode DEFAULT for MSC_RAMCTRL */
2948 #define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT                 (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2)   /**< Shifted mode DEFAULT for MSC_RAMCTRL */
2949 #define MSC_RAMCTRL_RAM1WSEN                              (0x1UL << 9)                                /**< RAM1 WAIT STATE Enable */
2950 #define _MSC_RAMCTRL_RAM1WSEN_SHIFT                       9                                           /**< Shift value for MSC_RAM1WSEN */
2951 #define _MSC_RAMCTRL_RAM1WSEN_MASK                        0x200UL                                     /**< Bit mask for MSC_RAM1WSEN */
2952 #define _MSC_RAMCTRL_RAM1WSEN_DEFAULT                     0x00000000UL                                /**< Mode DEFAULT for MSC_RAMCTRL */
2953 #define MSC_RAMCTRL_RAM1WSEN_DEFAULT                      (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9)        /**< Shifted mode DEFAULT for MSC_RAMCTRL */
2954 #define MSC_RAMCTRL_RAM1PREFETCHEN                        (0x1UL << 10)                               /**< RAM1 Prefetch Enable */
2955 #define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT                 10                                          /**< Shift value for MSC_RAM1PREFETCHEN */
2956 #define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK                  0x400UL                                     /**< Bit mask for MSC_RAM1PREFETCHEN */
2957 #define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT               0x00000000UL                                /**< Mode DEFAULT for MSC_RAMCTRL */
2958 #define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT                (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
2959 #define MSC_RAMCTRL_RAM2WSEN                              (0x1UL << 17)                               /**< RAM2 WAIT STATE Enable */
2960 #define _MSC_RAMCTRL_RAM2WSEN_SHIFT                       17                                          /**< Shift value for MSC_RAM2WSEN */
2961 #define _MSC_RAMCTRL_RAM2WSEN_MASK                        0x20000UL                                   /**< Bit mask for MSC_RAM2WSEN */
2962 #define _MSC_RAMCTRL_RAM2WSEN_DEFAULT                     0x00000000UL                                /**< Mode DEFAULT for MSC_RAMCTRL */
2963 #define MSC_RAMCTRL_RAM2WSEN_DEFAULT                      (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17)       /**< Shifted mode DEFAULT for MSC_RAMCTRL */
2964 #define MSC_RAMCTRL_RAM2PREFETCHEN                        (0x1UL << 18)                               /**< RAM2 Prefetch Enable */
2965 #define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT                 18                                          /**< Shift value for MSC_RAM2PREFETCHEN */
2966 #define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK                  0x40000UL                                   /**< Bit mask for MSC_RAM2PREFETCHEN */
2967 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT               0x00000000UL                                /**< Mode DEFAULT for MSC_RAMCTRL */
2968 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT                (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
2969 
2970 /* Bit fields for MSC ECCCTRL */
2971 #define _MSC_ECCCTRL_RESETVALUE                           0x00000000UL                             /**< Default value for MSC_ECCCTRL */
2972 #define _MSC_ECCCTRL_MASK                                 0x0000003FUL                             /**< Mask for MSC_ECCCTRL */
2973 #define MSC_ECCCTRL_RAMECCEWEN                            (0x1UL << 0)                             /**< RAM ECC Write Enable */
2974 #define _MSC_ECCCTRL_RAMECCEWEN_SHIFT                     0                                        /**< Shift value for MSC_RAMECCEWEN */
2975 #define _MSC_ECCCTRL_RAMECCEWEN_MASK                      0x1UL                                    /**< Bit mask for MSC_RAMECCEWEN */
2976 #define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for MSC_ECCCTRL */
2977 #define MSC_ECCCTRL_RAMECCEWEN_DEFAULT                    (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0)   /**< Shifted mode DEFAULT for MSC_ECCCTRL */
2978 #define MSC_ECCCTRL_RAMECCCHKEN                           (0x1UL << 1)                             /**< RAM ECC Check Enable */
2979 #define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT                    1                                        /**< Shift value for MSC_RAMECCCHKEN */
2980 #define _MSC_ECCCTRL_RAMECCCHKEN_MASK                     0x2UL                                    /**< Bit mask for MSC_RAMECCCHKEN */
2981 #define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for MSC_ECCCTRL */
2982 #define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT                   (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1)  /**< Shifted mode DEFAULT for MSC_ECCCTRL */
2983 #define MSC_ECCCTRL_RAM1ECCEWEN                           (0x1UL << 2)                             /**< RAM1 ECC Write Enable */
2984 #define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT                    2                                        /**< Shift value for MSC_RAM1ECCEWEN */
2985 #define _MSC_ECCCTRL_RAM1ECCEWEN_MASK                     0x4UL                                    /**< Bit mask for MSC_RAM1ECCEWEN */
2986 #define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for MSC_ECCCTRL */
2987 #define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT                   (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2)  /**< Shifted mode DEFAULT for MSC_ECCCTRL */
2988 #define MSC_ECCCTRL_RAM1ECCCHKEN                          (0x1UL << 3)                             /**< RAM1 ECC Check Enable */
2989 #define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT                   3                                        /**< Shift value for MSC_RAM1ECCCHKEN */
2990 #define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK                    0x8UL                                    /**< Bit mask for MSC_RAM1ECCCHKEN */
2991 #define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for MSC_ECCCTRL */
2992 #define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT                  (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */
2993 #define MSC_ECCCTRL_RAM2ECCEWEN                           (0x1UL << 4)                             /**< RAM2 ECC Write Enable */
2994 #define _MSC_ECCCTRL_RAM2ECCEWEN_SHIFT                    4                                        /**< Shift value for MSC_RAM2ECCEWEN */
2995 #define _MSC_ECCCTRL_RAM2ECCEWEN_MASK                     0x10UL                                   /**< Bit mask for MSC_RAM2ECCEWEN */
2996 #define _MSC_ECCCTRL_RAM2ECCEWEN_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for MSC_ECCCTRL */
2997 #define MSC_ECCCTRL_RAM2ECCEWEN_DEFAULT                   (_MSC_ECCCTRL_RAM2ECCEWEN_DEFAULT << 4)  /**< Shifted mode DEFAULT for MSC_ECCCTRL */
2998 #define MSC_ECCCTRL_RAM2ECCCHKEN                          (0x1UL << 5)                             /**< RAM2 ECC Check Enable */
2999 #define _MSC_ECCCTRL_RAM2ECCCHKEN_SHIFT                   5                                        /**< Shift value for MSC_RAM2ECCCHKEN */
3000 #define _MSC_ECCCTRL_RAM2ECCCHKEN_MASK                    0x20UL                                   /**< Bit mask for MSC_RAM2ECCCHKEN */
3001 #define _MSC_ECCCTRL_RAM2ECCCHKEN_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for MSC_ECCCTRL */
3002 #define MSC_ECCCTRL_RAM2ECCCHKEN_DEFAULT                  (_MSC_ECCCTRL_RAM2ECCCHKEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_ECCCTRL */
3003 
3004 /* Bit fields for MSC RAMECCADDR */
3005 #define _MSC_RAMECCADDR_RESETVALUE                        0x00000000UL                              /**< Default value for MSC_RAMECCADDR */
3006 #define _MSC_RAMECCADDR_MASK                              0xFFFFFFFFUL                              /**< Mask for MSC_RAMECCADDR */
3007 #define _MSC_RAMECCADDR_RAMECCADDR_SHIFT                  0                                         /**< Shift value for MSC_RAMECCADDR */
3008 #define _MSC_RAMECCADDR_RAMECCADDR_MASK                   0xFFFFFFFFUL                              /**< Bit mask for MSC_RAMECCADDR */
3009 #define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT                0x00000000UL                              /**< Mode DEFAULT for MSC_RAMECCADDR */
3010 #define MSC_RAMECCADDR_RAMECCADDR_DEFAULT                 (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */
3011 
3012 /* Bit fields for MSC RAM1ECCADDR */
3013 #define _MSC_RAM1ECCADDR_RESETVALUE                       0x00000000UL                                /**< Default value for MSC_RAM1ECCADDR */
3014 #define _MSC_RAM1ECCADDR_MASK                             0xFFFFFFFFUL                                /**< Mask for MSC_RAM1ECCADDR */
3015 #define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT                0                                           /**< Shift value for MSC_RAM1ECCADDR */
3016 #define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK                 0xFFFFFFFFUL                                /**< Bit mask for MSC_RAM1ECCADDR */
3017 #define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT              0x00000000UL                                /**< Mode DEFAULT for MSC_RAM1ECCADDR */
3018 #define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT               (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */
3019 
3020 /* Bit fields for MSC RAM2ECCADDR */
3021 #define _MSC_RAM2ECCADDR_RESETVALUE                       0x00000000UL                                /**< Default value for MSC_RAM2ECCADDR */
3022 #define _MSC_RAM2ECCADDR_MASK                             0xFFFFFFFFUL                                /**< Mask for MSC_RAM2ECCADDR */
3023 #define _MSC_RAM2ECCADDR_RAM2ECCADDR_SHIFT                0                                           /**< Shift value for MSC_RAM2ECCADDR */
3024 #define _MSC_RAM2ECCADDR_RAM2ECCADDR_MASK                 0xFFFFFFFFUL                                /**< Bit mask for MSC_RAM2ECCADDR */
3025 #define _MSC_RAM2ECCADDR_RAM2ECCADDR_DEFAULT              0x00000000UL                                /**< Mode DEFAULT for MSC_RAM2ECCADDR */
3026 #define MSC_RAM2ECCADDR_RAM2ECCADDR_DEFAULT               (_MSC_RAM2ECCADDR_RAM2ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM2ECCADDR */
3027 
3028 /** @} */
3029 /** @} End of group EFM32GG12B310F1024GQ100_MSC */
3030 
3031 /***************************************************************************//**
3032  * @addtogroup EFM32GG12B310F1024GQ100_EMU
3033  * @{
3034  * @defgroup EFM32GG12B310F1024GQ100_EMU_BitFields  EMU Bit Fields
3035  * @{
3036  ******************************************************************************/
3037 
3038 /* Bit fields for EMU CTRL */
3039 #define _EMU_CTRL_RESETVALUE                                 0x00000000UL                                /**< Default value for EMU_CTRL */
3040 #define _EMU_CTRL_MASK                                       0x0003031EUL                                /**< Mask for EMU_CTRL */
3041 #define EMU_CTRL_EM2BLOCK                                    (0x1UL << 1)                                /**< Energy Mode 2 Block */
3042 #define _EMU_CTRL_EM2BLOCK_SHIFT                             1                                           /**< Shift value for EMU_EM2BLOCK */
3043 #define _EMU_CTRL_EM2BLOCK_MASK                              0x2UL                                       /**< Bit mask for EMU_EM2BLOCK */
3044 #define _EMU_CTRL_EM2BLOCK_DEFAULT                           0x00000000UL                                /**< Mode DEFAULT for EMU_CTRL */
3045 #define EMU_CTRL_EM2BLOCK_DEFAULT                            (_EMU_CTRL_EM2BLOCK_DEFAULT << 1)           /**< Shifted mode DEFAULT for EMU_CTRL */
3046 #define EMU_CTRL_EM2BODDIS                                   (0x1UL << 2)                                /**< Disable BOD in EM2 */
3047 #define _EMU_CTRL_EM2BODDIS_SHIFT                            2                                           /**< Shift value for EMU_EM2BODDIS */
3048 #define _EMU_CTRL_EM2BODDIS_MASK                             0x4UL                                       /**< Bit mask for EMU_EM2BODDIS */
3049 #define _EMU_CTRL_EM2BODDIS_DEFAULT                          0x00000000UL                                /**< Mode DEFAULT for EMU_CTRL */
3050 #define EMU_CTRL_EM2BODDIS_DEFAULT                           (_EMU_CTRL_EM2BODDIS_DEFAULT << 2)          /**< Shifted mode DEFAULT for EMU_CTRL */
3051 #define EMU_CTRL_EM01LD                                      (0x1UL << 3)                                /**< Reserved for internal use. Do not change. */
3052 #define _EMU_CTRL_EM01LD_SHIFT                               3                                           /**< Shift value for EMU_EM01LD */
3053 #define _EMU_CTRL_EM01LD_MASK                                0x8UL                                       /**< Bit mask for EMU_EM01LD */
3054 #define _EMU_CTRL_EM01LD_DEFAULT                             0x00000000UL                                /**< Mode DEFAULT for EMU_CTRL */
3055 #define EMU_CTRL_EM01LD_DEFAULT                              (_EMU_CTRL_EM01LD_DEFAULT << 3)             /**< Shifted mode DEFAULT for EMU_CTRL */
3056 #define EMU_CTRL_EM23VSCALEAUTOWSEN                          (0x1UL << 4)                                /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */
3057 #define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT                   4                                           /**< Shift value for EMU_EM23VSCALEAUTOWSEN */
3058 #define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK                    0x10UL                                      /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */
3059 #define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT                 0x00000000UL                                /**< Mode DEFAULT for EMU_CTRL */
3060 #define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT                  (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */
3061 #define _EMU_CTRL_EM23VSCALE_SHIFT                           8                                           /**< Shift value for EMU_EM23VSCALE */
3062 #define _EMU_CTRL_EM23VSCALE_MASK                            0x300UL                                     /**< Bit mask for EMU_EM23VSCALE */
3063 #define _EMU_CTRL_EM23VSCALE_DEFAULT                         0x00000000UL                                /**< Mode DEFAULT for EMU_CTRL */
3064 #define _EMU_CTRL_EM23VSCALE_VSCALE2                         0x00000000UL                                /**< Mode VSCALE2 for EMU_CTRL */
3065 #define _EMU_CTRL_EM23VSCALE_VSCALE0                         0x00000002UL                                /**< Mode VSCALE0 for EMU_CTRL */
3066 #define _EMU_CTRL_EM23VSCALE_RESV                            0x00000003UL                                /**< Mode RESV for EMU_CTRL */
3067 #define EMU_CTRL_EM23VSCALE_DEFAULT                          (_EMU_CTRL_EM23VSCALE_DEFAULT << 8)         /**< Shifted mode DEFAULT for EMU_CTRL */
3068 #define EMU_CTRL_EM23VSCALE_VSCALE2                          (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8)         /**< Shifted mode VSCALE2 for EMU_CTRL */
3069 #define EMU_CTRL_EM23VSCALE_VSCALE0                          (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8)         /**< Shifted mode VSCALE0 for EMU_CTRL */
3070 #define EMU_CTRL_EM23VSCALE_RESV                             (_EMU_CTRL_EM23VSCALE_RESV << 8)            /**< Shifted mode RESV for EMU_CTRL */
3071 #define _EMU_CTRL_EM4HVSCALE_SHIFT                           16                                          /**< Shift value for EMU_EM4HVSCALE */
3072 #define _EMU_CTRL_EM4HVSCALE_MASK                            0x30000UL                                   /**< Bit mask for EMU_EM4HVSCALE */
3073 #define _EMU_CTRL_EM4HVSCALE_DEFAULT                         0x00000000UL                                /**< Mode DEFAULT for EMU_CTRL */
3074 #define _EMU_CTRL_EM4HVSCALE_VSCALE2                         0x00000000UL                                /**< Mode VSCALE2 for EMU_CTRL */
3075 #define _EMU_CTRL_EM4HVSCALE_VSCALE0                         0x00000002UL                                /**< Mode VSCALE0 for EMU_CTRL */
3076 #define _EMU_CTRL_EM4HVSCALE_RESV                            0x00000003UL                                /**< Mode RESV for EMU_CTRL */
3077 #define EMU_CTRL_EM4HVSCALE_DEFAULT                          (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16)        /**< Shifted mode DEFAULT for EMU_CTRL */
3078 #define EMU_CTRL_EM4HVSCALE_VSCALE2                          (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16)        /**< Shifted mode VSCALE2 for EMU_CTRL */
3079 #define EMU_CTRL_EM4HVSCALE_VSCALE0                          (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16)        /**< Shifted mode VSCALE0 for EMU_CTRL */
3080 #define EMU_CTRL_EM4HVSCALE_RESV                             (_EMU_CTRL_EM4HVSCALE_RESV << 16)           /**< Shifted mode RESV for EMU_CTRL */
3081 
3082 /* Bit fields for EMU STATUS */
3083 #define _EMU_STATUS_RESETVALUE                               0x00000000UL                           /**< Default value for EMU_STATUS */
3084 #define _EMU_STATUS_MASK                                     0x041710BFUL                           /**< Mask for EMU_STATUS */
3085 #define EMU_STATUS_VMONRDY                                   (0x1UL << 0)                           /**< VMON Ready */
3086 #define _EMU_STATUS_VMONRDY_SHIFT                            0                                      /**< Shift value for EMU_VMONRDY */
3087 #define _EMU_STATUS_VMONRDY_MASK                             0x1UL                                  /**< Bit mask for EMU_VMONRDY */
3088 #define _EMU_STATUS_VMONRDY_DEFAULT                          0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
3089 #define EMU_STATUS_VMONRDY_DEFAULT                           (_EMU_STATUS_VMONRDY_DEFAULT << 0)     /**< Shifted mode DEFAULT for EMU_STATUS */
3090 #define EMU_STATUS_VMONAVDD                                  (0x1UL << 1)                           /**< VMON AVDD Channel */
3091 #define _EMU_STATUS_VMONAVDD_SHIFT                           1                                      /**< Shift value for EMU_VMONAVDD */
3092 #define _EMU_STATUS_VMONAVDD_MASK                            0x2UL                                  /**< Bit mask for EMU_VMONAVDD */
3093 #define _EMU_STATUS_VMONAVDD_DEFAULT                         0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
3094 #define EMU_STATUS_VMONAVDD_DEFAULT                          (_EMU_STATUS_VMONAVDD_DEFAULT << 1)    /**< Shifted mode DEFAULT for EMU_STATUS */
3095 #define EMU_STATUS_VMONALTAVDD                               (0x1UL << 2)                           /**< Alternate VMON AVDD Channel */
3096 #define _EMU_STATUS_VMONALTAVDD_SHIFT                        2                                      /**< Shift value for EMU_VMONALTAVDD */
3097 #define _EMU_STATUS_VMONALTAVDD_MASK                         0x4UL                                  /**< Bit mask for EMU_VMONALTAVDD */
3098 #define _EMU_STATUS_VMONALTAVDD_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
3099 #define EMU_STATUS_VMONALTAVDD_DEFAULT                       (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */
3100 #define EMU_STATUS_VMONDVDD                                  (0x1UL << 3)                           /**< VMON DVDD Channel */
3101 #define _EMU_STATUS_VMONDVDD_SHIFT                           3                                      /**< Shift value for EMU_VMONDVDD */
3102 #define _EMU_STATUS_VMONDVDD_MASK                            0x8UL                                  /**< Bit mask for EMU_VMONDVDD */
3103 #define _EMU_STATUS_VMONDVDD_DEFAULT                         0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
3104 #define EMU_STATUS_VMONDVDD_DEFAULT                          (_EMU_STATUS_VMONDVDD_DEFAULT << 3)    /**< Shifted mode DEFAULT for EMU_STATUS */
3105 #define EMU_STATUS_VMONIO0                                   (0x1UL << 4)                           /**< VMON IOVDD0 Channel */
3106 #define _EMU_STATUS_VMONIO0_SHIFT                            4                                      /**< Shift value for EMU_VMONIO0 */
3107 #define _EMU_STATUS_VMONIO0_MASK                             0x10UL                                 /**< Bit mask for EMU_VMONIO0 */
3108 #define _EMU_STATUS_VMONIO0_DEFAULT                          0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
3109 #define EMU_STATUS_VMONIO0_DEFAULT                           (_EMU_STATUS_VMONIO0_DEFAULT << 4)     /**< Shifted mode DEFAULT for EMU_STATUS */
3110 #define EMU_STATUS_VMONIO1                                   (0x1UL << 5)                           /**< VMON IOVDD1 Channel */
3111 #define _EMU_STATUS_VMONIO1_SHIFT                            5                                      /**< Shift value for EMU_VMONIO1 */
3112 #define _EMU_STATUS_VMONIO1_MASK                             0x20UL                                 /**< Bit mask for EMU_VMONIO1 */
3113 #define _EMU_STATUS_VMONIO1_DEFAULT                          0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
3114 #define EMU_STATUS_VMONIO1_DEFAULT                           (_EMU_STATUS_VMONIO1_DEFAULT << 5)     /**< Shifted mode DEFAULT for EMU_STATUS */
3115 #define EMU_STATUS_VMONBUVDD                                 (0x1UL << 7)                           /**< VMON BUVDD Channel */
3116 #define _EMU_STATUS_VMONBUVDD_SHIFT                          7                                      /**< Shift value for EMU_VMONBUVDD */
3117 #define _EMU_STATUS_VMONBUVDD_MASK                           0x80UL                                 /**< Bit mask for EMU_VMONBUVDD */
3118 #define _EMU_STATUS_VMONBUVDD_DEFAULT                        0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
3119 #define EMU_STATUS_VMONBUVDD_DEFAULT                         (_EMU_STATUS_VMONBUVDD_DEFAULT << 7)   /**< Shifted mode DEFAULT for EMU_STATUS */
3120 #define EMU_STATUS_BURDY                                     (0x1UL << 12)                          /**< Backup Mode Ready */
3121 #define _EMU_STATUS_BURDY_SHIFT                              12                                     /**< Shift value for EMU_BURDY */
3122 #define _EMU_STATUS_BURDY_MASK                               0x1000UL                               /**< Bit mask for EMU_BURDY */
3123 #define _EMU_STATUS_BURDY_DEFAULT                            0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
3124 #define EMU_STATUS_BURDY_DEFAULT                             (_EMU_STATUS_BURDY_DEFAULT << 12)      /**< Shifted mode DEFAULT for EMU_STATUS */
3125 #define _EMU_STATUS_VSCALE_SHIFT                             16                                     /**< Shift value for EMU_VSCALE */
3126 #define _EMU_STATUS_VSCALE_MASK                              0x30000UL                              /**< Bit mask for EMU_VSCALE */
3127 #define _EMU_STATUS_VSCALE_DEFAULT                           0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
3128 #define _EMU_STATUS_VSCALE_VSCALE2                           0x00000000UL                           /**< Mode VSCALE2 for EMU_STATUS */
3129 #define _EMU_STATUS_VSCALE_VSCALE0                           0x00000002UL                           /**< Mode VSCALE0 for EMU_STATUS */
3130 #define _EMU_STATUS_VSCALE_RESV                              0x00000003UL                           /**< Mode RESV for EMU_STATUS */
3131 #define EMU_STATUS_VSCALE_DEFAULT                            (_EMU_STATUS_VSCALE_DEFAULT << 16)     /**< Shifted mode DEFAULT for EMU_STATUS */
3132 #define EMU_STATUS_VSCALE_VSCALE2                            (_EMU_STATUS_VSCALE_VSCALE2 << 16)     /**< Shifted mode VSCALE2 for EMU_STATUS */
3133 #define EMU_STATUS_VSCALE_VSCALE0                            (_EMU_STATUS_VSCALE_VSCALE0 << 16)     /**< Shifted mode VSCALE0 for EMU_STATUS */
3134 #define EMU_STATUS_VSCALE_RESV                               (_EMU_STATUS_VSCALE_RESV << 16)        /**< Shifted mode RESV for EMU_STATUS */
3135 #define EMU_STATUS_VSCALEBUSY                                (0x1UL << 18)                          /**< System is Busy Scaling Voltage */
3136 #define _EMU_STATUS_VSCALEBUSY_SHIFT                         18                                     /**< Shift value for EMU_VSCALEBUSY */
3137 #define _EMU_STATUS_VSCALEBUSY_MASK                          0x40000UL                              /**< Bit mask for EMU_VSCALEBUSY */
3138 #define _EMU_STATUS_VSCALEBUSY_DEFAULT                       0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
3139 #define EMU_STATUS_VSCALEBUSY_DEFAULT                        (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */
3140 #define EMU_STATUS_EM4IORET                                  (0x1UL << 20)                          /**< IO Retention Status */
3141 #define _EMU_STATUS_EM4IORET_SHIFT                           20                                     /**< Shift value for EMU_EM4IORET */
3142 #define _EMU_STATUS_EM4IORET_MASK                            0x100000UL                             /**< Bit mask for EMU_EM4IORET */
3143 #define _EMU_STATUS_EM4IORET_DEFAULT                         0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
3144 #define _EMU_STATUS_EM4IORET_DISABLED                        0x00000000UL                           /**< Mode DISABLED for EMU_STATUS */
3145 #define _EMU_STATUS_EM4IORET_ENABLED                         0x00000001UL                           /**< Mode ENABLED for EMU_STATUS */
3146 #define EMU_STATUS_EM4IORET_DEFAULT                          (_EMU_STATUS_EM4IORET_DEFAULT << 20)   /**< Shifted mode DEFAULT for EMU_STATUS */
3147 #define EMU_STATUS_EM4IORET_DISABLED                         (_EMU_STATUS_EM4IORET_DISABLED << 20)  /**< Shifted mode DISABLED for EMU_STATUS */
3148 #define EMU_STATUS_EM4IORET_ENABLED                          (_EMU_STATUS_EM4IORET_ENABLED << 20)   /**< Shifted mode ENABLED for EMU_STATUS */
3149 #define EMU_STATUS_TEMPACTIVE                                (0x1UL << 26)                          /**< Temperature Measurement Active */
3150 #define _EMU_STATUS_TEMPACTIVE_SHIFT                         26                                     /**< Shift value for EMU_TEMPACTIVE */
3151 #define _EMU_STATUS_TEMPACTIVE_MASK                          0x4000000UL                            /**< Bit mask for EMU_TEMPACTIVE */
3152 #define _EMU_STATUS_TEMPACTIVE_DEFAULT                       0x00000000UL                           /**< Mode DEFAULT for EMU_STATUS */
3153 #define EMU_STATUS_TEMPACTIVE_DEFAULT                        (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */
3154 
3155 /* Bit fields for EMU LOCK */
3156 #define _EMU_LOCK_RESETVALUE                                 0x00000000UL                      /**< Default value for EMU_LOCK */
3157 #define _EMU_LOCK_MASK                                       0x0000FFFFUL                      /**< Mask for EMU_LOCK */
3158 #define _EMU_LOCK_LOCKKEY_SHIFT                              0                                 /**< Shift value for EMU_LOCKKEY */
3159 #define _EMU_LOCK_LOCKKEY_MASK                               0xFFFFUL                          /**< Bit mask for EMU_LOCKKEY */
3160 #define _EMU_LOCK_LOCKKEY_DEFAULT                            0x00000000UL                      /**< Mode DEFAULT for EMU_LOCK */
3161 #define _EMU_LOCK_LOCKKEY_UNLOCKED                           0x00000000UL                      /**< Mode UNLOCKED for EMU_LOCK */
3162 #define _EMU_LOCK_LOCKKEY_LOCK                               0x00000000UL                      /**< Mode LOCK for EMU_LOCK */
3163 #define _EMU_LOCK_LOCKKEY_LOCKED                             0x00000001UL                      /**< Mode LOCKED for EMU_LOCK */
3164 #define _EMU_LOCK_LOCKKEY_UNLOCK                             0x0000ADE8UL                      /**< Mode UNLOCK for EMU_LOCK */
3165 #define EMU_LOCK_LOCKKEY_DEFAULT                             (_EMU_LOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for EMU_LOCK */
3166 #define EMU_LOCK_LOCKKEY_UNLOCKED                            (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
3167 #define EMU_LOCK_LOCKKEY_LOCK                                (_EMU_LOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for EMU_LOCK */
3168 #define EMU_LOCK_LOCKKEY_LOCKED                              (_EMU_LOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for EMU_LOCK */
3169 #define EMU_LOCK_LOCKKEY_UNLOCK                              (_EMU_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for EMU_LOCK */
3170 
3171 /* Bit fields for EMU RAM0CTRL */
3172 #define _EMU_RAM0CTRL_RESETVALUE                             0x00000000UL                              /**< Default value for EMU_RAM0CTRL */
3173 #define _EMU_RAM0CTRL_MASK                                   0x00000007UL                              /**< Mask for EMU_RAM0CTRL */
3174 #define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT                     0                                         /**< Shift value for EMU_RAMPOWERDOWN */
3175 #define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK                      0x7UL                                     /**< Bit mask for EMU_RAMPOWERDOWN */
3176 #define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for EMU_RAM0CTRL */
3177 #define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE                      0x00000000UL                              /**< Mode NONE for EMU_RAM0CTRL */
3178 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3                      0x00000004UL                              /**< Mode BLK3 for EMU_RAM0CTRL */
3179 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO3                   0x00000006UL                              /**< Mode BLK2TO3 for EMU_RAM0CTRL */
3180 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO3                   0x00000007UL                              /**< Mode BLK1TO3 for EMU_RAM0CTRL */
3181 #define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT                    (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */
3182 #define EMU_RAM0CTRL_RAMPOWERDOWN_NONE                       (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0)    /**< Shifted mode NONE for EMU_RAM0CTRL */
3183 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3                       (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3 << 0)    /**< Shifted mode BLK3 for EMU_RAM0CTRL */
3184 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO3                    (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM0CTRL */
3185 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO3                    (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM0CTRL */
3186 
3187 /* Bit fields for EMU CMD */
3188 #define _EMU_CMD_RESETVALUE                                  0x00000000UL                        /**< Default value for EMU_CMD */
3189 #define _EMU_CMD_MASK                                        0x00000051UL                        /**< Mask for EMU_CMD */
3190 #define EMU_CMD_EM4UNLATCH                                   (0x1UL << 0)                        /**< EM4 Unlatch */
3191 #define _EMU_CMD_EM4UNLATCH_SHIFT                            0                                   /**< Shift value for EMU_EM4UNLATCH */
3192 #define _EMU_CMD_EM4UNLATCH_MASK                             0x1UL                               /**< Bit mask for EMU_EM4UNLATCH */
3193 #define _EMU_CMD_EM4UNLATCH_DEFAULT                          0x00000000UL                        /**< Mode DEFAULT for EMU_CMD */
3194 #define EMU_CMD_EM4UNLATCH_DEFAULT                           (_EMU_CMD_EM4UNLATCH_DEFAULT << 0)  /**< Shifted mode DEFAULT for EMU_CMD */
3195 #define EMU_CMD_EM01VSCALE0                                  (0x1UL << 4)                        /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */
3196 #define _EMU_CMD_EM01VSCALE0_SHIFT                           4                                   /**< Shift value for EMU_EM01VSCALE0 */
3197 #define _EMU_CMD_EM01VSCALE0_MASK                            0x10UL                              /**< Bit mask for EMU_EM01VSCALE0 */
3198 #define _EMU_CMD_EM01VSCALE0_DEFAULT                         0x00000000UL                        /**< Mode DEFAULT for EMU_CMD */
3199 #define EMU_CMD_EM01VSCALE0_DEFAULT                          (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */
3200 #define EMU_CMD_EM01VSCALE2                                  (0x1UL << 6)                        /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */
3201 #define _EMU_CMD_EM01VSCALE2_SHIFT                           6                                   /**< Shift value for EMU_EM01VSCALE2 */
3202 #define _EMU_CMD_EM01VSCALE2_MASK                            0x40UL                              /**< Bit mask for EMU_EM01VSCALE2 */
3203 #define _EMU_CMD_EM01VSCALE2_DEFAULT                         0x00000000UL                        /**< Mode DEFAULT for EMU_CMD */
3204 #define EMU_CMD_EM01VSCALE2_DEFAULT                          (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */
3205 
3206 /* Bit fields for EMU EM4CTRL */
3207 #define _EMU_EM4CTRL_RESETVALUE                              0x00000000UL                               /**< Default value for EMU_EM4CTRL */
3208 #define _EMU_EM4CTRL_MASK                                    0x0003003FUL                               /**< Mask for EMU_EM4CTRL */
3209 #define EMU_EM4CTRL_EM4STATE                                 (0x1UL << 0)                               /**< Energy Mode 4 State */
3210 #define _EMU_EM4CTRL_EM4STATE_SHIFT                          0                                          /**< Shift value for EMU_EM4STATE */
3211 #define _EMU_EM4CTRL_EM4STATE_MASK                           0x1UL                                      /**< Bit mask for EMU_EM4STATE */
3212 #define _EMU_EM4CTRL_EM4STATE_DEFAULT                        0x00000000UL                               /**< Mode DEFAULT for EMU_EM4CTRL */
3213 #define _EMU_EM4CTRL_EM4STATE_EM4S                           0x00000000UL                               /**< Mode EM4S for EMU_EM4CTRL */
3214 #define _EMU_EM4CTRL_EM4STATE_EM4H                           0x00000001UL                               /**< Mode EM4H for EMU_EM4CTRL */
3215 #define EMU_EM4CTRL_EM4STATE_DEFAULT                         (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0)       /**< Shifted mode DEFAULT for EMU_EM4CTRL */
3216 #define EMU_EM4CTRL_EM4STATE_EM4S                            (_EMU_EM4CTRL_EM4STATE_EM4S << 0)          /**< Shifted mode EM4S for EMU_EM4CTRL */
3217 #define EMU_EM4CTRL_EM4STATE_EM4H                            (_EMU_EM4CTRL_EM4STATE_EM4H << 0)          /**< Shifted mode EM4H for EMU_EM4CTRL */
3218 #define EMU_EM4CTRL_RETAINLFRCO                              (0x1UL << 1)                               /**< LFRCO Retain During EM4 */
3219 #define _EMU_EM4CTRL_RETAINLFRCO_SHIFT                       1                                          /**< Shift value for EMU_RETAINLFRCO */
3220 #define _EMU_EM4CTRL_RETAINLFRCO_MASK                        0x2UL                                      /**< Bit mask for EMU_RETAINLFRCO */
3221 #define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for EMU_EM4CTRL */
3222 #define EMU_EM4CTRL_RETAINLFRCO_DEFAULT                      (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1)    /**< Shifted mode DEFAULT for EMU_EM4CTRL */
3223 #define EMU_EM4CTRL_RETAINLFXO                               (0x1UL << 2)                               /**< LFXO Retain During EM4 */
3224 #define _EMU_EM4CTRL_RETAINLFXO_SHIFT                        2                                          /**< Shift value for EMU_RETAINLFXO */
3225 #define _EMU_EM4CTRL_RETAINLFXO_MASK                         0x4UL                                      /**< Bit mask for EMU_RETAINLFXO */
3226 #define _EMU_EM4CTRL_RETAINLFXO_DEFAULT                      0x00000000UL                               /**< Mode DEFAULT for EMU_EM4CTRL */
3227 #define EMU_EM4CTRL_RETAINLFXO_DEFAULT                       (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2)     /**< Shifted mode DEFAULT for EMU_EM4CTRL */
3228 #define EMU_EM4CTRL_RETAINULFRCO                             (0x1UL << 3)                               /**< ULFRCO Retain During EM4S */
3229 #define _EMU_EM4CTRL_RETAINULFRCO_SHIFT                      3                                          /**< Shift value for EMU_RETAINULFRCO */
3230 #define _EMU_EM4CTRL_RETAINULFRCO_MASK                       0x8UL                                      /**< Bit mask for EMU_RETAINULFRCO */
3231 #define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for EMU_EM4CTRL */
3232 #define EMU_EM4CTRL_RETAINULFRCO_DEFAULT                     (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3)   /**< Shifted mode DEFAULT for EMU_EM4CTRL */
3233 #define _EMU_EM4CTRL_EM4IORETMODE_SHIFT                      4                                          /**< Shift value for EMU_EM4IORETMODE */
3234 #define _EMU_EM4CTRL_EM4IORETMODE_MASK                       0x30UL                                     /**< Bit mask for EMU_EM4IORETMODE */
3235 #define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for EMU_EM4CTRL */
3236 #define _EMU_EM4CTRL_EM4IORETMODE_DISABLE                    0x00000000UL                               /**< Mode DISABLE for EMU_EM4CTRL */
3237 #define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT                    0x00000001UL                               /**< Mode EM4EXIT for EMU_EM4CTRL */
3238 #define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH                  0x00000002UL                               /**< Mode SWUNLATCH for EMU_EM4CTRL */
3239 #define EMU_EM4CTRL_EM4IORETMODE_DEFAULT                     (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4)   /**< Shifted mode DEFAULT for EMU_EM4CTRL */
3240 #define EMU_EM4CTRL_EM4IORETMODE_DISABLE                     (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4)   /**< Shifted mode DISABLE for EMU_EM4CTRL */
3241 #define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT                     (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4)   /**< Shifted mode EM4EXIT for EMU_EM4CTRL */
3242 #define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH                   (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */
3243 #define _EMU_EM4CTRL_EM4ENTRY_SHIFT                          16                                         /**< Shift value for EMU_EM4ENTRY */
3244 #define _EMU_EM4CTRL_EM4ENTRY_MASK                           0x30000UL                                  /**< Bit mask for EMU_EM4ENTRY */
3245 #define _EMU_EM4CTRL_EM4ENTRY_DEFAULT                        0x00000000UL                               /**< Mode DEFAULT for EMU_EM4CTRL */
3246 #define EMU_EM4CTRL_EM4ENTRY_DEFAULT                         (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16)      /**< Shifted mode DEFAULT for EMU_EM4CTRL */
3247 
3248 /* Bit fields for EMU TEMPLIMITS */
3249 #define _EMU_TEMPLIMITS_RESETVALUE                           0x0000FF00UL                            /**< Default value for EMU_TEMPLIMITS */
3250 #define _EMU_TEMPLIMITS_MASK                                 0x0001FFFFUL                            /**< Mask for EMU_TEMPLIMITS */
3251 #define _EMU_TEMPLIMITS_TEMPLOW_SHIFT                        0                                       /**< Shift value for EMU_TEMPLOW */
3252 #define _EMU_TEMPLIMITS_TEMPLOW_MASK                         0xFFUL                                  /**< Bit mask for EMU_TEMPLOW */
3253 #define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT                      0x00000000UL                            /**< Mode DEFAULT for EMU_TEMPLIMITS */
3254 #define EMU_TEMPLIMITS_TEMPLOW_DEFAULT                       (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0)  /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
3255 #define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT                       8                                       /**< Shift value for EMU_TEMPHIGH */
3256 #define _EMU_TEMPLIMITS_TEMPHIGH_MASK                        0xFF00UL                                /**< Bit mask for EMU_TEMPHIGH */
3257 #define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT                     0x000000FFUL                            /**< Mode DEFAULT for EMU_TEMPLIMITS */
3258 #define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT                      (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
3259 #define EMU_TEMPLIMITS_EM4WUEN                               (0x1UL << 16)                           /**< Enable EM4 Wakeup Due to Low/high Temperature */
3260 #define _EMU_TEMPLIMITS_EM4WUEN_SHIFT                        16                                      /**< Shift value for EMU_EM4WUEN */
3261 #define _EMU_TEMPLIMITS_EM4WUEN_MASK                         0x10000UL                               /**< Bit mask for EMU_EM4WUEN */
3262 #define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT                      0x00000000UL                            /**< Mode DEFAULT for EMU_TEMPLIMITS */
3263 #define EMU_TEMPLIMITS_EM4WUEN_DEFAULT                       (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
3264 
3265 /* Bit fields for EMU TEMP */
3266 #define _EMU_TEMP_RESETVALUE                                 0x00000000UL                  /**< Default value for EMU_TEMP */
3267 #define _EMU_TEMP_MASK                                       0x000000FFUL                  /**< Mask for EMU_TEMP */
3268 #define _EMU_TEMP_TEMP_SHIFT                                 0                             /**< Shift value for EMU_TEMP */
3269 #define _EMU_TEMP_TEMP_MASK                                  0xFFUL                        /**< Bit mask for EMU_TEMP */
3270 #define _EMU_TEMP_TEMP_DEFAULT                               0x00000000UL                  /**< Mode DEFAULT for EMU_TEMP */
3271 #define EMU_TEMP_TEMP_DEFAULT                                (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */
3272 
3273 /* Bit fields for EMU IF */
3274 #define _EMU_IF_RESETVALUE                                   0x00000000UL                                 /**< Default value for EMU_IF */
3275 #define _EMU_IF_MASK                                         0xE3DF37FFUL                                 /**< Mask for EMU_IF */
3276 #define EMU_IF_VMONAVDDFALL                                  (0x1UL << 0)                                 /**< VMON AVDD Channel Fall */
3277 #define _EMU_IF_VMONAVDDFALL_SHIFT                           0                                            /**< Shift value for EMU_VMONAVDDFALL */
3278 #define _EMU_IF_VMONAVDDFALL_MASK                            0x1UL                                        /**< Bit mask for EMU_VMONAVDDFALL */
3279 #define _EMU_IF_VMONAVDDFALL_DEFAULT                         0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3280 #define EMU_IF_VMONAVDDFALL_DEFAULT                          (_EMU_IF_VMONAVDDFALL_DEFAULT << 0)          /**< Shifted mode DEFAULT for EMU_IF */
3281 #define EMU_IF_VMONAVDDRISE                                  (0x1UL << 1)                                 /**< VMON AVDD Channel Rise */
3282 #define _EMU_IF_VMONAVDDRISE_SHIFT                           1                                            /**< Shift value for EMU_VMONAVDDRISE */
3283 #define _EMU_IF_VMONAVDDRISE_MASK                            0x2UL                                        /**< Bit mask for EMU_VMONAVDDRISE */
3284 #define _EMU_IF_VMONAVDDRISE_DEFAULT                         0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3285 #define EMU_IF_VMONAVDDRISE_DEFAULT                          (_EMU_IF_VMONAVDDRISE_DEFAULT << 1)          /**< Shifted mode DEFAULT for EMU_IF */
3286 #define EMU_IF_VMONALTAVDDFALL                               (0x1UL << 2)                                 /**< Alternate VMON AVDD Channel Fall */
3287 #define _EMU_IF_VMONALTAVDDFALL_SHIFT                        2                                            /**< Shift value for EMU_VMONALTAVDDFALL */
3288 #define _EMU_IF_VMONALTAVDDFALL_MASK                         0x4UL                                        /**< Bit mask for EMU_VMONALTAVDDFALL */
3289 #define _EMU_IF_VMONALTAVDDFALL_DEFAULT                      0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3290 #define EMU_IF_VMONALTAVDDFALL_DEFAULT                       (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_IF */
3291 #define EMU_IF_VMONALTAVDDRISE                               (0x1UL << 3)                                 /**< Alternate VMON AVDD Channel Rise */
3292 #define _EMU_IF_VMONALTAVDDRISE_SHIFT                        3                                            /**< Shift value for EMU_VMONALTAVDDRISE */
3293 #define _EMU_IF_VMONALTAVDDRISE_MASK                         0x8UL                                        /**< Bit mask for EMU_VMONALTAVDDRISE */
3294 #define _EMU_IF_VMONALTAVDDRISE_DEFAULT                      0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3295 #define EMU_IF_VMONALTAVDDRISE_DEFAULT                       (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_IF */
3296 #define EMU_IF_VMONDVDDFALL                                  (0x1UL << 4)                                 /**< VMON DVDD Channel Fall */
3297 #define _EMU_IF_VMONDVDDFALL_SHIFT                           4                                            /**< Shift value for EMU_VMONDVDDFALL */
3298 #define _EMU_IF_VMONDVDDFALL_MASK                            0x10UL                                       /**< Bit mask for EMU_VMONDVDDFALL */
3299 #define _EMU_IF_VMONDVDDFALL_DEFAULT                         0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3300 #define EMU_IF_VMONDVDDFALL_DEFAULT                          (_EMU_IF_VMONDVDDFALL_DEFAULT << 4)          /**< Shifted mode DEFAULT for EMU_IF */
3301 #define EMU_IF_VMONDVDDRISE                                  (0x1UL << 5)                                 /**< VMON DVDD Channel Rise */
3302 #define _EMU_IF_VMONDVDDRISE_SHIFT                           5                                            /**< Shift value for EMU_VMONDVDDRISE */
3303 #define _EMU_IF_VMONDVDDRISE_MASK                            0x20UL                                       /**< Bit mask for EMU_VMONDVDDRISE */
3304 #define _EMU_IF_VMONDVDDRISE_DEFAULT                         0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3305 #define EMU_IF_VMONDVDDRISE_DEFAULT                          (_EMU_IF_VMONDVDDRISE_DEFAULT << 5)          /**< Shifted mode DEFAULT for EMU_IF */
3306 #define EMU_IF_VMONIO0FALL                                   (0x1UL << 6)                                 /**< VMON IOVDD0 Channel Fall */
3307 #define _EMU_IF_VMONIO0FALL_SHIFT                            6                                            /**< Shift value for EMU_VMONIO0FALL */
3308 #define _EMU_IF_VMONIO0FALL_MASK                             0x40UL                                       /**< Bit mask for EMU_VMONIO0FALL */
3309 #define _EMU_IF_VMONIO0FALL_DEFAULT                          0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3310 #define EMU_IF_VMONIO0FALL_DEFAULT                           (_EMU_IF_VMONIO0FALL_DEFAULT << 6)           /**< Shifted mode DEFAULT for EMU_IF */
3311 #define EMU_IF_VMONIO0RISE                                   (0x1UL << 7)                                 /**< VMON IOVDD0 Channel Rise */
3312 #define _EMU_IF_VMONIO0RISE_SHIFT                            7                                            /**< Shift value for EMU_VMONIO0RISE */
3313 #define _EMU_IF_VMONIO0RISE_MASK                             0x80UL                                       /**< Bit mask for EMU_VMONIO0RISE */
3314 #define _EMU_IF_VMONIO0RISE_DEFAULT                          0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3315 #define EMU_IF_VMONIO0RISE_DEFAULT                           (_EMU_IF_VMONIO0RISE_DEFAULT << 7)           /**< Shifted mode DEFAULT for EMU_IF */
3316 #define EMU_IF_VMONIO1FALL                                   (0x1UL << 8)                                 /**< VMON IOVDD1 Channel Fall */
3317 #define _EMU_IF_VMONIO1FALL_SHIFT                            8                                            /**< Shift value for EMU_VMONIO1FALL */
3318 #define _EMU_IF_VMONIO1FALL_MASK                             0x100UL                                      /**< Bit mask for EMU_VMONIO1FALL */
3319 #define _EMU_IF_VMONIO1FALL_DEFAULT                          0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3320 #define EMU_IF_VMONIO1FALL_DEFAULT                           (_EMU_IF_VMONIO1FALL_DEFAULT << 8)           /**< Shifted mode DEFAULT for EMU_IF */
3321 #define EMU_IF_VMONIO1RISE                                   (0x1UL << 9)                                 /**< VMON IOVDD1 Channel Rise */
3322 #define _EMU_IF_VMONIO1RISE_SHIFT                            9                                            /**< Shift value for EMU_VMONIO1RISE */
3323 #define _EMU_IF_VMONIO1RISE_MASK                             0x200UL                                      /**< Bit mask for EMU_VMONIO1RISE */
3324 #define _EMU_IF_VMONIO1RISE_DEFAULT                          0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3325 #define EMU_IF_VMONIO1RISE_DEFAULT                           (_EMU_IF_VMONIO1RISE_DEFAULT << 9)           /**< Shifted mode DEFAULT for EMU_IF */
3326 #define EMU_IF_R5VREADY                                      (0x1UL << 10)                                /**< 5V Regulator is Ready to Use */
3327 #define _EMU_IF_R5VREADY_SHIFT                               10                                           /**< Shift value for EMU_R5VREADY */
3328 #define _EMU_IF_R5VREADY_MASK                                0x400UL                                      /**< Bit mask for EMU_R5VREADY */
3329 #define _EMU_IF_R5VREADY_DEFAULT                             0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3330 #define EMU_IF_R5VREADY_DEFAULT                              (_EMU_IF_R5VREADY_DEFAULT << 10)             /**< Shifted mode DEFAULT for EMU_IF */
3331 #define EMU_IF_VMONBUVDDFALL                                 (0x1UL << 12)                                /**< VMON BACKUP Channel Fall */
3332 #define _EMU_IF_VMONBUVDDFALL_SHIFT                          12                                           /**< Shift value for EMU_VMONBUVDDFALL */
3333 #define _EMU_IF_VMONBUVDDFALL_MASK                           0x1000UL                                     /**< Bit mask for EMU_VMONBUVDDFALL */
3334 #define _EMU_IF_VMONBUVDDFALL_DEFAULT                        0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3335 #define EMU_IF_VMONBUVDDFALL_DEFAULT                         (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12)        /**< Shifted mode DEFAULT for EMU_IF */
3336 #define EMU_IF_VMONBUVDDRISE                                 (0x1UL << 13)                                /**< VMON BUVDD Channel Rise */
3337 #define _EMU_IF_VMONBUVDDRISE_SHIFT                          13                                           /**< Shift value for EMU_VMONBUVDDRISE */
3338 #define _EMU_IF_VMONBUVDDRISE_MASK                           0x2000UL                                     /**< Bit mask for EMU_VMONBUVDDRISE */
3339 #define _EMU_IF_VMONBUVDDRISE_DEFAULT                        0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3340 #define EMU_IF_VMONBUVDDRISE_DEFAULT                         (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13)        /**< Shifted mode DEFAULT for EMU_IF */
3341 #define EMU_IF_PFETOVERCURRENTLIMIT                          (0x1UL << 16)                                /**< PFET Current Limit Hit */
3342 #define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT                   16                                           /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
3343 #define _EMU_IF_PFETOVERCURRENTLIMIT_MASK                    0x10000UL                                    /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
3344 #define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT                 0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3345 #define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT                  (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */
3346 #define EMU_IF_NFETOVERCURRENTLIMIT                          (0x1UL << 17)                                /**< NFET Current Limit Hit */
3347 #define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT                   17                                           /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
3348 #define _EMU_IF_NFETOVERCURRENTLIMIT_MASK                    0x20000UL                                    /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
3349 #define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT                 0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3350 #define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT                  (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */
3351 #define EMU_IF_DCDCLPRUNNING                                 (0x1UL << 18)                                /**< LP Mode is Running */
3352 #define _EMU_IF_DCDCLPRUNNING_SHIFT                          18                                           /**< Shift value for EMU_DCDCLPRUNNING */
3353 #define _EMU_IF_DCDCLPRUNNING_MASK                           0x40000UL                                    /**< Bit mask for EMU_DCDCLPRUNNING */
3354 #define _EMU_IF_DCDCLPRUNNING_DEFAULT                        0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3355 #define EMU_IF_DCDCLPRUNNING_DEFAULT                         (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18)        /**< Shifted mode DEFAULT for EMU_IF */
3356 #define EMU_IF_DCDCLNRUNNING                                 (0x1UL << 19)                                /**< LN Mode is Running */
3357 #define _EMU_IF_DCDCLNRUNNING_SHIFT                          19                                           /**< Shift value for EMU_DCDCLNRUNNING */
3358 #define _EMU_IF_DCDCLNRUNNING_MASK                           0x80000UL                                    /**< Bit mask for EMU_DCDCLNRUNNING */
3359 #define _EMU_IF_DCDCLNRUNNING_DEFAULT                        0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3360 #define EMU_IF_DCDCLNRUNNING_DEFAULT                         (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19)        /**< Shifted mode DEFAULT for EMU_IF */
3361 #define EMU_IF_DCDCINBYPASS                                  (0x1UL << 20)                                /**< DCDC is in Bypass */
3362 #define _EMU_IF_DCDCINBYPASS_SHIFT                           20                                           /**< Shift value for EMU_DCDCINBYPASS */
3363 #define _EMU_IF_DCDCINBYPASS_MASK                            0x100000UL                                   /**< Bit mask for EMU_DCDCINBYPASS */
3364 #define _EMU_IF_DCDCINBYPASS_DEFAULT                         0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3365 #define EMU_IF_DCDCINBYPASS_DEFAULT                          (_EMU_IF_DCDCINBYPASS_DEFAULT << 20)         /**< Shifted mode DEFAULT for EMU_IF */
3366 #define EMU_IF_BURDY                                         (0x1UL << 22)                                /**< Backup Functionality Ready Interrupt Flag */
3367 #define _EMU_IF_BURDY_SHIFT                                  22                                           /**< Shift value for EMU_BURDY */
3368 #define _EMU_IF_BURDY_MASK                                   0x400000UL                                   /**< Bit mask for EMU_BURDY */
3369 #define _EMU_IF_BURDY_DEFAULT                                0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3370 #define EMU_IF_BURDY_DEFAULT                                 (_EMU_IF_BURDY_DEFAULT << 22)                /**< Shifted mode DEFAULT for EMU_IF */
3371 #define EMU_IF_R5VVSINT                                      (0x1UL << 23)                                /**< 5V Regulator Voltage Update Done */
3372 #define _EMU_IF_R5VVSINT_SHIFT                               23                                           /**< Shift value for EMU_R5VVSINT */
3373 #define _EMU_IF_R5VVSINT_MASK                                0x800000UL                                   /**< Bit mask for EMU_R5VVSINT */
3374 #define _EMU_IF_R5VVSINT_DEFAULT                             0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3375 #define EMU_IF_R5VVSINT_DEFAULT                              (_EMU_IF_R5VVSINT_DEFAULT << 23)             /**< Shifted mode DEFAULT for EMU_IF */
3376 #define EMU_IF_EM23WAKEUP                                    (0x1UL << 24)                                /**< Wakeup IRQ From EM2 and EM3 */
3377 #define _EMU_IF_EM23WAKEUP_SHIFT                             24                                           /**< Shift value for EMU_EM23WAKEUP */
3378 #define _EMU_IF_EM23WAKEUP_MASK                              0x1000000UL                                  /**< Bit mask for EMU_EM23WAKEUP */
3379 #define _EMU_IF_EM23WAKEUP_DEFAULT                           0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3380 #define EMU_IF_EM23WAKEUP_DEFAULT                            (_EMU_IF_EM23WAKEUP_DEFAULT << 24)           /**< Shifted mode DEFAULT for EMU_IF */
3381 #define EMU_IF_VSCALEDONE                                    (0x1UL << 25)                                /**< Voltage Scale Steps Done IRQ */
3382 #define _EMU_IF_VSCALEDONE_SHIFT                             25                                           /**< Shift value for EMU_VSCALEDONE */
3383 #define _EMU_IF_VSCALEDONE_MASK                              0x2000000UL                                  /**< Bit mask for EMU_VSCALEDONE */
3384 #define _EMU_IF_VSCALEDONE_DEFAULT                           0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3385 #define EMU_IF_VSCALEDONE_DEFAULT                            (_EMU_IF_VSCALEDONE_DEFAULT << 25)           /**< Shifted mode DEFAULT for EMU_IF */
3386 #define EMU_IF_TEMP                                          (0x1UL << 29)                                /**< New Temperature Measurement Valid */
3387 #define _EMU_IF_TEMP_SHIFT                                   29                                           /**< Shift value for EMU_TEMP */
3388 #define _EMU_IF_TEMP_MASK                                    0x20000000UL                                 /**< Bit mask for EMU_TEMP */
3389 #define _EMU_IF_TEMP_DEFAULT                                 0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3390 #define EMU_IF_TEMP_DEFAULT                                  (_EMU_IF_TEMP_DEFAULT << 29)                 /**< Shifted mode DEFAULT for EMU_IF */
3391 #define EMU_IF_TEMPLOW                                       (0x1UL << 30)                                /**< Temperature Low Limit Reached */
3392 #define _EMU_IF_TEMPLOW_SHIFT                                30                                           /**< Shift value for EMU_TEMPLOW */
3393 #define _EMU_IF_TEMPLOW_MASK                                 0x40000000UL                                 /**< Bit mask for EMU_TEMPLOW */
3394 #define _EMU_IF_TEMPLOW_DEFAULT                              0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3395 #define EMU_IF_TEMPLOW_DEFAULT                               (_EMU_IF_TEMPLOW_DEFAULT << 30)              /**< Shifted mode DEFAULT for EMU_IF */
3396 #define EMU_IF_TEMPHIGH                                      (0x1UL << 31)                                /**< Temperature High Limit Reached */
3397 #define _EMU_IF_TEMPHIGH_SHIFT                               31                                           /**< Shift value for EMU_TEMPHIGH */
3398 #define _EMU_IF_TEMPHIGH_MASK                                0x80000000UL                                 /**< Bit mask for EMU_TEMPHIGH */
3399 #define _EMU_IF_TEMPHIGH_DEFAULT                             0x00000000UL                                 /**< Mode DEFAULT for EMU_IF */
3400 #define EMU_IF_TEMPHIGH_DEFAULT                              (_EMU_IF_TEMPHIGH_DEFAULT << 31)             /**< Shifted mode DEFAULT for EMU_IF */
3401 
3402 /* Bit fields for EMU IFS */
3403 #define _EMU_IFS_RESETVALUE                                  0x00000000UL                                  /**< Default value for EMU_IFS */
3404 #define _EMU_IFS_MASK                                        0xE3DF37FFUL                                  /**< Mask for EMU_IFS */
3405 #define EMU_IFS_VMONAVDDFALL                                 (0x1UL << 0)                                  /**< Set VMONAVDDFALL Interrupt Flag */
3406 #define _EMU_IFS_VMONAVDDFALL_SHIFT                          0                                             /**< Shift value for EMU_VMONAVDDFALL */
3407 #define _EMU_IFS_VMONAVDDFALL_MASK                           0x1UL                                         /**< Bit mask for EMU_VMONAVDDFALL */
3408 #define _EMU_IFS_VMONAVDDFALL_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3409 #define EMU_IFS_VMONAVDDFALL_DEFAULT                         (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0)          /**< Shifted mode DEFAULT for EMU_IFS */
3410 #define EMU_IFS_VMONAVDDRISE                                 (0x1UL << 1)                                  /**< Set VMONAVDDRISE Interrupt Flag */
3411 #define _EMU_IFS_VMONAVDDRISE_SHIFT                          1                                             /**< Shift value for EMU_VMONAVDDRISE */
3412 #define _EMU_IFS_VMONAVDDRISE_MASK                           0x2UL                                         /**< Bit mask for EMU_VMONAVDDRISE */
3413 #define _EMU_IFS_VMONAVDDRISE_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3414 #define EMU_IFS_VMONAVDDRISE_DEFAULT                         (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1)          /**< Shifted mode DEFAULT for EMU_IFS */
3415 #define EMU_IFS_VMONALTAVDDFALL                              (0x1UL << 2)                                  /**< Set VMONALTAVDDFALL Interrupt Flag */
3416 #define _EMU_IFS_VMONALTAVDDFALL_SHIFT                       2                                             /**< Shift value for EMU_VMONALTAVDDFALL */
3417 #define _EMU_IFS_VMONALTAVDDFALL_MASK                        0x4UL                                         /**< Bit mask for EMU_VMONALTAVDDFALL */
3418 #define _EMU_IFS_VMONALTAVDDFALL_DEFAULT                     0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3419 #define EMU_IFS_VMONALTAVDDFALL_DEFAULT                      (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_IFS */
3420 #define EMU_IFS_VMONALTAVDDRISE                              (0x1UL << 3)                                  /**< Set VMONALTAVDDRISE Interrupt Flag */
3421 #define _EMU_IFS_VMONALTAVDDRISE_SHIFT                       3                                             /**< Shift value for EMU_VMONALTAVDDRISE */
3422 #define _EMU_IFS_VMONALTAVDDRISE_MASK                        0x8UL                                         /**< Bit mask for EMU_VMONALTAVDDRISE */
3423 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT                     0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3424 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT                      (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_IFS */
3425 #define EMU_IFS_VMONDVDDFALL                                 (0x1UL << 4)                                  /**< Set VMONDVDDFALL Interrupt Flag */
3426 #define _EMU_IFS_VMONDVDDFALL_SHIFT                          4                                             /**< Shift value for EMU_VMONDVDDFALL */
3427 #define _EMU_IFS_VMONDVDDFALL_MASK                           0x10UL                                        /**< Bit mask for EMU_VMONDVDDFALL */
3428 #define _EMU_IFS_VMONDVDDFALL_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3429 #define EMU_IFS_VMONDVDDFALL_DEFAULT                         (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4)          /**< Shifted mode DEFAULT for EMU_IFS */
3430 #define EMU_IFS_VMONDVDDRISE                                 (0x1UL << 5)                                  /**< Set VMONDVDDRISE Interrupt Flag */
3431 #define _EMU_IFS_VMONDVDDRISE_SHIFT                          5                                             /**< Shift value for EMU_VMONDVDDRISE */
3432 #define _EMU_IFS_VMONDVDDRISE_MASK                           0x20UL                                        /**< Bit mask for EMU_VMONDVDDRISE */
3433 #define _EMU_IFS_VMONDVDDRISE_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3434 #define EMU_IFS_VMONDVDDRISE_DEFAULT                         (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5)          /**< Shifted mode DEFAULT for EMU_IFS */
3435 #define EMU_IFS_VMONIO0FALL                                  (0x1UL << 6)                                  /**< Set VMONIO0FALL Interrupt Flag */
3436 #define _EMU_IFS_VMONIO0FALL_SHIFT                           6                                             /**< Shift value for EMU_VMONIO0FALL */
3437 #define _EMU_IFS_VMONIO0FALL_MASK                            0x40UL                                        /**< Bit mask for EMU_VMONIO0FALL */
3438 #define _EMU_IFS_VMONIO0FALL_DEFAULT                         0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3439 #define EMU_IFS_VMONIO0FALL_DEFAULT                          (_EMU_IFS_VMONIO0FALL_DEFAULT << 6)           /**< Shifted mode DEFAULT for EMU_IFS */
3440 #define EMU_IFS_VMONIO0RISE                                  (0x1UL << 7)                                  /**< Set VMONIO0RISE Interrupt Flag */
3441 #define _EMU_IFS_VMONIO0RISE_SHIFT                           7                                             /**< Shift value for EMU_VMONIO0RISE */
3442 #define _EMU_IFS_VMONIO0RISE_MASK                            0x80UL                                        /**< Bit mask for EMU_VMONIO0RISE */
3443 #define _EMU_IFS_VMONIO0RISE_DEFAULT                         0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3444 #define EMU_IFS_VMONIO0RISE_DEFAULT                          (_EMU_IFS_VMONIO0RISE_DEFAULT << 7)           /**< Shifted mode DEFAULT for EMU_IFS */
3445 #define EMU_IFS_VMONIO1FALL                                  (0x1UL << 8)                                  /**< Set VMONIO1FALL Interrupt Flag */
3446 #define _EMU_IFS_VMONIO1FALL_SHIFT                           8                                             /**< Shift value for EMU_VMONIO1FALL */
3447 #define _EMU_IFS_VMONIO1FALL_MASK                            0x100UL                                       /**< Bit mask for EMU_VMONIO1FALL */
3448 #define _EMU_IFS_VMONIO1FALL_DEFAULT                         0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3449 #define EMU_IFS_VMONIO1FALL_DEFAULT                          (_EMU_IFS_VMONIO1FALL_DEFAULT << 8)           /**< Shifted mode DEFAULT for EMU_IFS */
3450 #define EMU_IFS_VMONIO1RISE                                  (0x1UL << 9)                                  /**< Set VMONIO1RISE Interrupt Flag */
3451 #define _EMU_IFS_VMONIO1RISE_SHIFT                           9                                             /**< Shift value for EMU_VMONIO1RISE */
3452 #define _EMU_IFS_VMONIO1RISE_MASK                            0x200UL                                       /**< Bit mask for EMU_VMONIO1RISE */
3453 #define _EMU_IFS_VMONIO1RISE_DEFAULT                         0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3454 #define EMU_IFS_VMONIO1RISE_DEFAULT                          (_EMU_IFS_VMONIO1RISE_DEFAULT << 9)           /**< Shifted mode DEFAULT for EMU_IFS */
3455 #define EMU_IFS_R5VREADY                                     (0x1UL << 10)                                 /**< Set R5VREADY Interrupt Flag */
3456 #define _EMU_IFS_R5VREADY_SHIFT                              10                                            /**< Shift value for EMU_R5VREADY */
3457 #define _EMU_IFS_R5VREADY_MASK                               0x400UL                                       /**< Bit mask for EMU_R5VREADY */
3458 #define _EMU_IFS_R5VREADY_DEFAULT                            0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3459 #define EMU_IFS_R5VREADY_DEFAULT                             (_EMU_IFS_R5VREADY_DEFAULT << 10)             /**< Shifted mode DEFAULT for EMU_IFS */
3460 #define EMU_IFS_VMONBUVDDFALL                                (0x1UL << 12)                                 /**< Set VMONBUVDDFALL Interrupt Flag */
3461 #define _EMU_IFS_VMONBUVDDFALL_SHIFT                         12                                            /**< Shift value for EMU_VMONBUVDDFALL */
3462 #define _EMU_IFS_VMONBUVDDFALL_MASK                          0x1000UL                                      /**< Bit mask for EMU_VMONBUVDDFALL */
3463 #define _EMU_IFS_VMONBUVDDFALL_DEFAULT                       0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3464 #define EMU_IFS_VMONBUVDDFALL_DEFAULT                        (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12)        /**< Shifted mode DEFAULT for EMU_IFS */
3465 #define EMU_IFS_VMONBUVDDRISE                                (0x1UL << 13)                                 /**< Set VMONBUVDDRISE Interrupt Flag */
3466 #define _EMU_IFS_VMONBUVDDRISE_SHIFT                         13                                            /**< Shift value for EMU_VMONBUVDDRISE */
3467 #define _EMU_IFS_VMONBUVDDRISE_MASK                          0x2000UL                                      /**< Bit mask for EMU_VMONBUVDDRISE */
3468 #define _EMU_IFS_VMONBUVDDRISE_DEFAULT                       0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3469 #define EMU_IFS_VMONBUVDDRISE_DEFAULT                        (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13)        /**< Shifted mode DEFAULT for EMU_IFS */
3470 #define EMU_IFS_PFETOVERCURRENTLIMIT                         (0x1UL << 16)                                 /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */
3471 #define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT                  16                                            /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
3472 #define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK                   0x10000UL                                     /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
3473 #define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3474 #define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT                 (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */
3475 #define EMU_IFS_NFETOVERCURRENTLIMIT                         (0x1UL << 17)                                 /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */
3476 #define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT                  17                                            /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
3477 #define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK                   0x20000UL                                     /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
3478 #define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3479 #define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT                 (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */
3480 #define EMU_IFS_DCDCLPRUNNING                                (0x1UL << 18)                                 /**< Set DCDCLPRUNNING Interrupt Flag */
3481 #define _EMU_IFS_DCDCLPRUNNING_SHIFT                         18                                            /**< Shift value for EMU_DCDCLPRUNNING */
3482 #define _EMU_IFS_DCDCLPRUNNING_MASK                          0x40000UL                                     /**< Bit mask for EMU_DCDCLPRUNNING */
3483 #define _EMU_IFS_DCDCLPRUNNING_DEFAULT                       0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3484 #define EMU_IFS_DCDCLPRUNNING_DEFAULT                        (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18)        /**< Shifted mode DEFAULT for EMU_IFS */
3485 #define EMU_IFS_DCDCLNRUNNING                                (0x1UL << 19)                                 /**< Set DCDCLNRUNNING Interrupt Flag */
3486 #define _EMU_IFS_DCDCLNRUNNING_SHIFT                         19                                            /**< Shift value for EMU_DCDCLNRUNNING */
3487 #define _EMU_IFS_DCDCLNRUNNING_MASK                          0x80000UL                                     /**< Bit mask for EMU_DCDCLNRUNNING */
3488 #define _EMU_IFS_DCDCLNRUNNING_DEFAULT                       0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3489 #define EMU_IFS_DCDCLNRUNNING_DEFAULT                        (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19)        /**< Shifted mode DEFAULT for EMU_IFS */
3490 #define EMU_IFS_DCDCINBYPASS                                 (0x1UL << 20)                                 /**< Set DCDCINBYPASS Interrupt Flag */
3491 #define _EMU_IFS_DCDCINBYPASS_SHIFT                          20                                            /**< Shift value for EMU_DCDCINBYPASS */
3492 #define _EMU_IFS_DCDCINBYPASS_MASK                           0x100000UL                                    /**< Bit mask for EMU_DCDCINBYPASS */
3493 #define _EMU_IFS_DCDCINBYPASS_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3494 #define EMU_IFS_DCDCINBYPASS_DEFAULT                         (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20)         /**< Shifted mode DEFAULT for EMU_IFS */
3495 #define EMU_IFS_BURDY                                        (0x1UL << 22)                                 /**< Set BURDY Interrupt Flag */
3496 #define _EMU_IFS_BURDY_SHIFT                                 22                                            /**< Shift value for EMU_BURDY */
3497 #define _EMU_IFS_BURDY_MASK                                  0x400000UL                                    /**< Bit mask for EMU_BURDY */
3498 #define _EMU_IFS_BURDY_DEFAULT                               0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3499 #define EMU_IFS_BURDY_DEFAULT                                (_EMU_IFS_BURDY_DEFAULT << 22)                /**< Shifted mode DEFAULT for EMU_IFS */
3500 #define EMU_IFS_R5VVSINT                                     (0x1UL << 23)                                 /**< Set R5VVSINT Interrupt Flag */
3501 #define _EMU_IFS_R5VVSINT_SHIFT                              23                                            /**< Shift value for EMU_R5VVSINT */
3502 #define _EMU_IFS_R5VVSINT_MASK                               0x800000UL                                    /**< Bit mask for EMU_R5VVSINT */
3503 #define _EMU_IFS_R5VVSINT_DEFAULT                            0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3504 #define EMU_IFS_R5VVSINT_DEFAULT                             (_EMU_IFS_R5VVSINT_DEFAULT << 23)             /**< Shifted mode DEFAULT for EMU_IFS */
3505 #define EMU_IFS_EM23WAKEUP                                   (0x1UL << 24)                                 /**< Set EM23WAKEUP Interrupt Flag */
3506 #define _EMU_IFS_EM23WAKEUP_SHIFT                            24                                            /**< Shift value for EMU_EM23WAKEUP */
3507 #define _EMU_IFS_EM23WAKEUP_MASK                             0x1000000UL                                   /**< Bit mask for EMU_EM23WAKEUP */
3508 #define _EMU_IFS_EM23WAKEUP_DEFAULT                          0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3509 #define EMU_IFS_EM23WAKEUP_DEFAULT                           (_EMU_IFS_EM23WAKEUP_DEFAULT << 24)           /**< Shifted mode DEFAULT for EMU_IFS */
3510 #define EMU_IFS_VSCALEDONE                                   (0x1UL << 25)                                 /**< Set VSCALEDONE Interrupt Flag */
3511 #define _EMU_IFS_VSCALEDONE_SHIFT                            25                                            /**< Shift value for EMU_VSCALEDONE */
3512 #define _EMU_IFS_VSCALEDONE_MASK                             0x2000000UL                                   /**< Bit mask for EMU_VSCALEDONE */
3513 #define _EMU_IFS_VSCALEDONE_DEFAULT                          0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3514 #define EMU_IFS_VSCALEDONE_DEFAULT                           (_EMU_IFS_VSCALEDONE_DEFAULT << 25)           /**< Shifted mode DEFAULT for EMU_IFS */
3515 #define EMU_IFS_TEMP                                         (0x1UL << 29)                                 /**< Set TEMP Interrupt Flag */
3516 #define _EMU_IFS_TEMP_SHIFT                                  29                                            /**< Shift value for EMU_TEMP */
3517 #define _EMU_IFS_TEMP_MASK                                   0x20000000UL                                  /**< Bit mask for EMU_TEMP */
3518 #define _EMU_IFS_TEMP_DEFAULT                                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3519 #define EMU_IFS_TEMP_DEFAULT                                 (_EMU_IFS_TEMP_DEFAULT << 29)                 /**< Shifted mode DEFAULT for EMU_IFS */
3520 #define EMU_IFS_TEMPLOW                                      (0x1UL << 30)                                 /**< Set TEMPLOW Interrupt Flag */
3521 #define _EMU_IFS_TEMPLOW_SHIFT                               30                                            /**< Shift value for EMU_TEMPLOW */
3522 #define _EMU_IFS_TEMPLOW_MASK                                0x40000000UL                                  /**< Bit mask for EMU_TEMPLOW */
3523 #define _EMU_IFS_TEMPLOW_DEFAULT                             0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3524 #define EMU_IFS_TEMPLOW_DEFAULT                              (_EMU_IFS_TEMPLOW_DEFAULT << 30)              /**< Shifted mode DEFAULT for EMU_IFS */
3525 #define EMU_IFS_TEMPHIGH                                     (0x1UL << 31)                                 /**< Set TEMPHIGH Interrupt Flag */
3526 #define _EMU_IFS_TEMPHIGH_SHIFT                              31                                            /**< Shift value for EMU_TEMPHIGH */
3527 #define _EMU_IFS_TEMPHIGH_MASK                               0x80000000UL                                  /**< Bit mask for EMU_TEMPHIGH */
3528 #define _EMU_IFS_TEMPHIGH_DEFAULT                            0x00000000UL                                  /**< Mode DEFAULT for EMU_IFS */
3529 #define EMU_IFS_TEMPHIGH_DEFAULT                             (_EMU_IFS_TEMPHIGH_DEFAULT << 31)             /**< Shifted mode DEFAULT for EMU_IFS */
3530 
3531 /* Bit fields for EMU IFC */
3532 #define _EMU_IFC_RESETVALUE                                  0x00000000UL                                  /**< Default value for EMU_IFC */
3533 #define _EMU_IFC_MASK                                        0xE3DF37FFUL                                  /**< Mask for EMU_IFC */
3534 #define EMU_IFC_VMONAVDDFALL                                 (0x1UL << 0)                                  /**< Clear VMONAVDDFALL Interrupt Flag */
3535 #define _EMU_IFC_VMONAVDDFALL_SHIFT                          0                                             /**< Shift value for EMU_VMONAVDDFALL */
3536 #define _EMU_IFC_VMONAVDDFALL_MASK                           0x1UL                                         /**< Bit mask for EMU_VMONAVDDFALL */
3537 #define _EMU_IFC_VMONAVDDFALL_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3538 #define EMU_IFC_VMONAVDDFALL_DEFAULT                         (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0)          /**< Shifted mode DEFAULT for EMU_IFC */
3539 #define EMU_IFC_VMONAVDDRISE                                 (0x1UL << 1)                                  /**< Clear VMONAVDDRISE Interrupt Flag */
3540 #define _EMU_IFC_VMONAVDDRISE_SHIFT                          1                                             /**< Shift value for EMU_VMONAVDDRISE */
3541 #define _EMU_IFC_VMONAVDDRISE_MASK                           0x2UL                                         /**< Bit mask for EMU_VMONAVDDRISE */
3542 #define _EMU_IFC_VMONAVDDRISE_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3543 #define EMU_IFC_VMONAVDDRISE_DEFAULT                         (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1)          /**< Shifted mode DEFAULT for EMU_IFC */
3544 #define EMU_IFC_VMONALTAVDDFALL                              (0x1UL << 2)                                  /**< Clear VMONALTAVDDFALL Interrupt Flag */
3545 #define _EMU_IFC_VMONALTAVDDFALL_SHIFT                       2                                             /**< Shift value for EMU_VMONALTAVDDFALL */
3546 #define _EMU_IFC_VMONALTAVDDFALL_MASK                        0x4UL                                         /**< Bit mask for EMU_VMONALTAVDDFALL */
3547 #define _EMU_IFC_VMONALTAVDDFALL_DEFAULT                     0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3548 #define EMU_IFC_VMONALTAVDDFALL_DEFAULT                      (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_IFC */
3549 #define EMU_IFC_VMONALTAVDDRISE                              (0x1UL << 3)                                  /**< Clear VMONALTAVDDRISE Interrupt Flag */
3550 #define _EMU_IFC_VMONALTAVDDRISE_SHIFT                       3                                             /**< Shift value for EMU_VMONALTAVDDRISE */
3551 #define _EMU_IFC_VMONALTAVDDRISE_MASK                        0x8UL                                         /**< Bit mask for EMU_VMONALTAVDDRISE */
3552 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT                     0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3553 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT                      (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_IFC */
3554 #define EMU_IFC_VMONDVDDFALL                                 (0x1UL << 4)                                  /**< Clear VMONDVDDFALL Interrupt Flag */
3555 #define _EMU_IFC_VMONDVDDFALL_SHIFT                          4                                             /**< Shift value for EMU_VMONDVDDFALL */
3556 #define _EMU_IFC_VMONDVDDFALL_MASK                           0x10UL                                        /**< Bit mask for EMU_VMONDVDDFALL */
3557 #define _EMU_IFC_VMONDVDDFALL_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3558 #define EMU_IFC_VMONDVDDFALL_DEFAULT                         (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4)          /**< Shifted mode DEFAULT for EMU_IFC */
3559 #define EMU_IFC_VMONDVDDRISE                                 (0x1UL << 5)                                  /**< Clear VMONDVDDRISE Interrupt Flag */
3560 #define _EMU_IFC_VMONDVDDRISE_SHIFT                          5                                             /**< Shift value for EMU_VMONDVDDRISE */
3561 #define _EMU_IFC_VMONDVDDRISE_MASK                           0x20UL                                        /**< Bit mask for EMU_VMONDVDDRISE */
3562 #define _EMU_IFC_VMONDVDDRISE_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3563 #define EMU_IFC_VMONDVDDRISE_DEFAULT                         (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5)          /**< Shifted mode DEFAULT for EMU_IFC */
3564 #define EMU_IFC_VMONIO0FALL                                  (0x1UL << 6)                                  /**< Clear VMONIO0FALL Interrupt Flag */
3565 #define _EMU_IFC_VMONIO0FALL_SHIFT                           6                                             /**< Shift value for EMU_VMONIO0FALL */
3566 #define _EMU_IFC_VMONIO0FALL_MASK                            0x40UL                                        /**< Bit mask for EMU_VMONIO0FALL */
3567 #define _EMU_IFC_VMONIO0FALL_DEFAULT                         0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3568 #define EMU_IFC_VMONIO0FALL_DEFAULT                          (_EMU_IFC_VMONIO0FALL_DEFAULT << 6)           /**< Shifted mode DEFAULT for EMU_IFC */
3569 #define EMU_IFC_VMONIO0RISE                                  (0x1UL << 7)                                  /**< Clear VMONIO0RISE Interrupt Flag */
3570 #define _EMU_IFC_VMONIO0RISE_SHIFT                           7                                             /**< Shift value for EMU_VMONIO0RISE */
3571 #define _EMU_IFC_VMONIO0RISE_MASK                            0x80UL                                        /**< Bit mask for EMU_VMONIO0RISE */
3572 #define _EMU_IFC_VMONIO0RISE_DEFAULT                         0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3573 #define EMU_IFC_VMONIO0RISE_DEFAULT                          (_EMU_IFC_VMONIO0RISE_DEFAULT << 7)           /**< Shifted mode DEFAULT for EMU_IFC */
3574 #define EMU_IFC_VMONIO1FALL                                  (0x1UL << 8)                                  /**< Clear VMONIO1FALL Interrupt Flag */
3575 #define _EMU_IFC_VMONIO1FALL_SHIFT                           8                                             /**< Shift value for EMU_VMONIO1FALL */
3576 #define _EMU_IFC_VMONIO1FALL_MASK                            0x100UL                                       /**< Bit mask for EMU_VMONIO1FALL */
3577 #define _EMU_IFC_VMONIO1FALL_DEFAULT                         0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3578 #define EMU_IFC_VMONIO1FALL_DEFAULT                          (_EMU_IFC_VMONIO1FALL_DEFAULT << 8)           /**< Shifted mode DEFAULT for EMU_IFC */
3579 #define EMU_IFC_VMONIO1RISE                                  (0x1UL << 9)                                  /**< Clear VMONIO1RISE Interrupt Flag */
3580 #define _EMU_IFC_VMONIO1RISE_SHIFT                           9                                             /**< Shift value for EMU_VMONIO1RISE */
3581 #define _EMU_IFC_VMONIO1RISE_MASK                            0x200UL                                       /**< Bit mask for EMU_VMONIO1RISE */
3582 #define _EMU_IFC_VMONIO1RISE_DEFAULT                         0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3583 #define EMU_IFC_VMONIO1RISE_DEFAULT                          (_EMU_IFC_VMONIO1RISE_DEFAULT << 9)           /**< Shifted mode DEFAULT for EMU_IFC */
3584 #define EMU_IFC_R5VREADY                                     (0x1UL << 10)                                 /**< Clear R5VREADY Interrupt Flag */
3585 #define _EMU_IFC_R5VREADY_SHIFT                              10                                            /**< Shift value for EMU_R5VREADY */
3586 #define _EMU_IFC_R5VREADY_MASK                               0x400UL                                       /**< Bit mask for EMU_R5VREADY */
3587 #define _EMU_IFC_R5VREADY_DEFAULT                            0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3588 #define EMU_IFC_R5VREADY_DEFAULT                             (_EMU_IFC_R5VREADY_DEFAULT << 10)             /**< Shifted mode DEFAULT for EMU_IFC */
3589 #define EMU_IFC_VMONBUVDDFALL                                (0x1UL << 12)                                 /**< Clear VMONBUVDDFALL Interrupt Flag */
3590 #define _EMU_IFC_VMONBUVDDFALL_SHIFT                         12                                            /**< Shift value for EMU_VMONBUVDDFALL */
3591 #define _EMU_IFC_VMONBUVDDFALL_MASK                          0x1000UL                                      /**< Bit mask for EMU_VMONBUVDDFALL */
3592 #define _EMU_IFC_VMONBUVDDFALL_DEFAULT                       0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3593 #define EMU_IFC_VMONBUVDDFALL_DEFAULT                        (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12)        /**< Shifted mode DEFAULT for EMU_IFC */
3594 #define EMU_IFC_VMONBUVDDRISE                                (0x1UL << 13)                                 /**< Clear VMONBUVDDRISE Interrupt Flag */
3595 #define _EMU_IFC_VMONBUVDDRISE_SHIFT                         13                                            /**< Shift value for EMU_VMONBUVDDRISE */
3596 #define _EMU_IFC_VMONBUVDDRISE_MASK                          0x2000UL                                      /**< Bit mask for EMU_VMONBUVDDRISE */
3597 #define _EMU_IFC_VMONBUVDDRISE_DEFAULT                       0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3598 #define EMU_IFC_VMONBUVDDRISE_DEFAULT                        (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13)        /**< Shifted mode DEFAULT for EMU_IFC */
3599 #define EMU_IFC_PFETOVERCURRENTLIMIT                         (0x1UL << 16)                                 /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */
3600 #define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT                  16                                            /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
3601 #define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK                   0x10000UL                                     /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
3602 #define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3603 #define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT                 (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */
3604 #define EMU_IFC_NFETOVERCURRENTLIMIT                         (0x1UL << 17)                                 /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */
3605 #define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT                  17                                            /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
3606 #define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK                   0x20000UL                                     /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
3607 #define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3608 #define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT                 (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */
3609 #define EMU_IFC_DCDCLPRUNNING                                (0x1UL << 18)                                 /**< Clear DCDCLPRUNNING Interrupt Flag */
3610 #define _EMU_IFC_DCDCLPRUNNING_SHIFT                         18                                            /**< Shift value for EMU_DCDCLPRUNNING */
3611 #define _EMU_IFC_DCDCLPRUNNING_MASK                          0x40000UL                                     /**< Bit mask for EMU_DCDCLPRUNNING */
3612 #define _EMU_IFC_DCDCLPRUNNING_DEFAULT                       0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3613 #define EMU_IFC_DCDCLPRUNNING_DEFAULT                        (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18)        /**< Shifted mode DEFAULT for EMU_IFC */
3614 #define EMU_IFC_DCDCLNRUNNING                                (0x1UL << 19)                                 /**< Clear DCDCLNRUNNING Interrupt Flag */
3615 #define _EMU_IFC_DCDCLNRUNNING_SHIFT                         19                                            /**< Shift value for EMU_DCDCLNRUNNING */
3616 #define _EMU_IFC_DCDCLNRUNNING_MASK                          0x80000UL                                     /**< Bit mask for EMU_DCDCLNRUNNING */
3617 #define _EMU_IFC_DCDCLNRUNNING_DEFAULT                       0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3618 #define EMU_IFC_DCDCLNRUNNING_DEFAULT                        (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19)        /**< Shifted mode DEFAULT for EMU_IFC */
3619 #define EMU_IFC_DCDCINBYPASS                                 (0x1UL << 20)                                 /**< Clear DCDCINBYPASS Interrupt Flag */
3620 #define _EMU_IFC_DCDCINBYPASS_SHIFT                          20                                            /**< Shift value for EMU_DCDCINBYPASS */
3621 #define _EMU_IFC_DCDCINBYPASS_MASK                           0x100000UL                                    /**< Bit mask for EMU_DCDCINBYPASS */
3622 #define _EMU_IFC_DCDCINBYPASS_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3623 #define EMU_IFC_DCDCINBYPASS_DEFAULT                         (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20)         /**< Shifted mode DEFAULT for EMU_IFC */
3624 #define EMU_IFC_BURDY                                        (0x1UL << 22)                                 /**< Clear BURDY Interrupt Flag */
3625 #define _EMU_IFC_BURDY_SHIFT                                 22                                            /**< Shift value for EMU_BURDY */
3626 #define _EMU_IFC_BURDY_MASK                                  0x400000UL                                    /**< Bit mask for EMU_BURDY */
3627 #define _EMU_IFC_BURDY_DEFAULT                               0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3628 #define EMU_IFC_BURDY_DEFAULT                                (_EMU_IFC_BURDY_DEFAULT << 22)                /**< Shifted mode DEFAULT for EMU_IFC */
3629 #define EMU_IFC_R5VVSINT                                     (0x1UL << 23)                                 /**< Clear R5VVSINT Interrupt Flag */
3630 #define _EMU_IFC_R5VVSINT_SHIFT                              23                                            /**< Shift value for EMU_R5VVSINT */
3631 #define _EMU_IFC_R5VVSINT_MASK                               0x800000UL                                    /**< Bit mask for EMU_R5VVSINT */
3632 #define _EMU_IFC_R5VVSINT_DEFAULT                            0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3633 #define EMU_IFC_R5VVSINT_DEFAULT                             (_EMU_IFC_R5VVSINT_DEFAULT << 23)             /**< Shifted mode DEFAULT for EMU_IFC */
3634 #define EMU_IFC_EM23WAKEUP                                   (0x1UL << 24)                                 /**< Clear EM23WAKEUP Interrupt Flag */
3635 #define _EMU_IFC_EM23WAKEUP_SHIFT                            24                                            /**< Shift value for EMU_EM23WAKEUP */
3636 #define _EMU_IFC_EM23WAKEUP_MASK                             0x1000000UL                                   /**< Bit mask for EMU_EM23WAKEUP */
3637 #define _EMU_IFC_EM23WAKEUP_DEFAULT                          0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3638 #define EMU_IFC_EM23WAKEUP_DEFAULT                           (_EMU_IFC_EM23WAKEUP_DEFAULT << 24)           /**< Shifted mode DEFAULT for EMU_IFC */
3639 #define EMU_IFC_VSCALEDONE                                   (0x1UL << 25)                                 /**< Clear VSCALEDONE Interrupt Flag */
3640 #define _EMU_IFC_VSCALEDONE_SHIFT                            25                                            /**< Shift value for EMU_VSCALEDONE */
3641 #define _EMU_IFC_VSCALEDONE_MASK                             0x2000000UL                                   /**< Bit mask for EMU_VSCALEDONE */
3642 #define _EMU_IFC_VSCALEDONE_DEFAULT                          0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3643 #define EMU_IFC_VSCALEDONE_DEFAULT                           (_EMU_IFC_VSCALEDONE_DEFAULT << 25)           /**< Shifted mode DEFAULT for EMU_IFC */
3644 #define EMU_IFC_TEMP                                         (0x1UL << 29)                                 /**< Clear TEMP Interrupt Flag */
3645 #define _EMU_IFC_TEMP_SHIFT                                  29                                            /**< Shift value for EMU_TEMP */
3646 #define _EMU_IFC_TEMP_MASK                                   0x20000000UL                                  /**< Bit mask for EMU_TEMP */
3647 #define _EMU_IFC_TEMP_DEFAULT                                0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3648 #define EMU_IFC_TEMP_DEFAULT                                 (_EMU_IFC_TEMP_DEFAULT << 29)                 /**< Shifted mode DEFAULT for EMU_IFC */
3649 #define EMU_IFC_TEMPLOW                                      (0x1UL << 30)                                 /**< Clear TEMPLOW Interrupt Flag */
3650 #define _EMU_IFC_TEMPLOW_SHIFT                               30                                            /**< Shift value for EMU_TEMPLOW */
3651 #define _EMU_IFC_TEMPLOW_MASK                                0x40000000UL                                  /**< Bit mask for EMU_TEMPLOW */
3652 #define _EMU_IFC_TEMPLOW_DEFAULT                             0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3653 #define EMU_IFC_TEMPLOW_DEFAULT                              (_EMU_IFC_TEMPLOW_DEFAULT << 30)              /**< Shifted mode DEFAULT for EMU_IFC */
3654 #define EMU_IFC_TEMPHIGH                                     (0x1UL << 31)                                 /**< Clear TEMPHIGH Interrupt Flag */
3655 #define _EMU_IFC_TEMPHIGH_SHIFT                              31                                            /**< Shift value for EMU_TEMPHIGH */
3656 #define _EMU_IFC_TEMPHIGH_MASK                               0x80000000UL                                  /**< Bit mask for EMU_TEMPHIGH */
3657 #define _EMU_IFC_TEMPHIGH_DEFAULT                            0x00000000UL                                  /**< Mode DEFAULT for EMU_IFC */
3658 #define EMU_IFC_TEMPHIGH_DEFAULT                             (_EMU_IFC_TEMPHIGH_DEFAULT << 31)             /**< Shifted mode DEFAULT for EMU_IFC */
3659 
3660 /* Bit fields for EMU IEN */
3661 #define _EMU_IEN_RESETVALUE                                  0x00000000UL                                  /**< Default value for EMU_IEN */
3662 #define _EMU_IEN_MASK                                        0xE3DF37FFUL                                  /**< Mask for EMU_IEN */
3663 #define EMU_IEN_VMONAVDDFALL                                 (0x1UL << 0)                                  /**< VMONAVDDFALL Interrupt Enable */
3664 #define _EMU_IEN_VMONAVDDFALL_SHIFT                          0                                             /**< Shift value for EMU_VMONAVDDFALL */
3665 #define _EMU_IEN_VMONAVDDFALL_MASK                           0x1UL                                         /**< Bit mask for EMU_VMONAVDDFALL */
3666 #define _EMU_IEN_VMONAVDDFALL_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3667 #define EMU_IEN_VMONAVDDFALL_DEFAULT                         (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0)          /**< Shifted mode DEFAULT for EMU_IEN */
3668 #define EMU_IEN_VMONAVDDRISE                                 (0x1UL << 1)                                  /**< VMONAVDDRISE Interrupt Enable */
3669 #define _EMU_IEN_VMONAVDDRISE_SHIFT                          1                                             /**< Shift value for EMU_VMONAVDDRISE */
3670 #define _EMU_IEN_VMONAVDDRISE_MASK                           0x2UL                                         /**< Bit mask for EMU_VMONAVDDRISE */
3671 #define _EMU_IEN_VMONAVDDRISE_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3672 #define EMU_IEN_VMONAVDDRISE_DEFAULT                         (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1)          /**< Shifted mode DEFAULT for EMU_IEN */
3673 #define EMU_IEN_VMONALTAVDDFALL                              (0x1UL << 2)                                  /**< VMONALTAVDDFALL Interrupt Enable */
3674 #define _EMU_IEN_VMONALTAVDDFALL_SHIFT                       2                                             /**< Shift value for EMU_VMONALTAVDDFALL */
3675 #define _EMU_IEN_VMONALTAVDDFALL_MASK                        0x4UL                                         /**< Bit mask for EMU_VMONALTAVDDFALL */
3676 #define _EMU_IEN_VMONALTAVDDFALL_DEFAULT                     0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3677 #define EMU_IEN_VMONALTAVDDFALL_DEFAULT                      (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_IEN */
3678 #define EMU_IEN_VMONALTAVDDRISE                              (0x1UL << 3)                                  /**< VMONALTAVDDRISE Interrupt Enable */
3679 #define _EMU_IEN_VMONALTAVDDRISE_SHIFT                       3                                             /**< Shift value for EMU_VMONALTAVDDRISE */
3680 #define _EMU_IEN_VMONALTAVDDRISE_MASK                        0x8UL                                         /**< Bit mask for EMU_VMONALTAVDDRISE */
3681 #define _EMU_IEN_VMONALTAVDDRISE_DEFAULT                     0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3682 #define EMU_IEN_VMONALTAVDDRISE_DEFAULT                      (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_IEN */
3683 #define EMU_IEN_VMONDVDDFALL                                 (0x1UL << 4)                                  /**< VMONDVDDFALL Interrupt Enable */
3684 #define _EMU_IEN_VMONDVDDFALL_SHIFT                          4                                             /**< Shift value for EMU_VMONDVDDFALL */
3685 #define _EMU_IEN_VMONDVDDFALL_MASK                           0x10UL                                        /**< Bit mask for EMU_VMONDVDDFALL */
3686 #define _EMU_IEN_VMONDVDDFALL_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3687 #define EMU_IEN_VMONDVDDFALL_DEFAULT                         (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4)          /**< Shifted mode DEFAULT for EMU_IEN */
3688 #define EMU_IEN_VMONDVDDRISE                                 (0x1UL << 5)                                  /**< VMONDVDDRISE Interrupt Enable */
3689 #define _EMU_IEN_VMONDVDDRISE_SHIFT                          5                                             /**< Shift value for EMU_VMONDVDDRISE */
3690 #define _EMU_IEN_VMONDVDDRISE_MASK                           0x20UL                                        /**< Bit mask for EMU_VMONDVDDRISE */
3691 #define _EMU_IEN_VMONDVDDRISE_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3692 #define EMU_IEN_VMONDVDDRISE_DEFAULT                         (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5)          /**< Shifted mode DEFAULT for EMU_IEN */
3693 #define EMU_IEN_VMONIO0FALL                                  (0x1UL << 6)                                  /**< VMONIO0FALL Interrupt Enable */
3694 #define _EMU_IEN_VMONIO0FALL_SHIFT                           6                                             /**< Shift value for EMU_VMONIO0FALL */
3695 #define _EMU_IEN_VMONIO0FALL_MASK                            0x40UL                                        /**< Bit mask for EMU_VMONIO0FALL */
3696 #define _EMU_IEN_VMONIO0FALL_DEFAULT                         0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3697 #define EMU_IEN_VMONIO0FALL_DEFAULT                          (_EMU_IEN_VMONIO0FALL_DEFAULT << 6)           /**< Shifted mode DEFAULT for EMU_IEN */
3698 #define EMU_IEN_VMONIO0RISE                                  (0x1UL << 7)                                  /**< VMONIO0RISE Interrupt Enable */
3699 #define _EMU_IEN_VMONIO0RISE_SHIFT                           7                                             /**< Shift value for EMU_VMONIO0RISE */
3700 #define _EMU_IEN_VMONIO0RISE_MASK                            0x80UL                                        /**< Bit mask for EMU_VMONIO0RISE */
3701 #define _EMU_IEN_VMONIO0RISE_DEFAULT                         0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3702 #define EMU_IEN_VMONIO0RISE_DEFAULT                          (_EMU_IEN_VMONIO0RISE_DEFAULT << 7)           /**< Shifted mode DEFAULT for EMU_IEN */
3703 #define EMU_IEN_VMONIO1FALL                                  (0x1UL << 8)                                  /**< VMONIO1FALL Interrupt Enable */
3704 #define _EMU_IEN_VMONIO1FALL_SHIFT                           8                                             /**< Shift value for EMU_VMONIO1FALL */
3705 #define _EMU_IEN_VMONIO1FALL_MASK                            0x100UL                                       /**< Bit mask for EMU_VMONIO1FALL */
3706 #define _EMU_IEN_VMONIO1FALL_DEFAULT                         0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3707 #define EMU_IEN_VMONIO1FALL_DEFAULT                          (_EMU_IEN_VMONIO1FALL_DEFAULT << 8)           /**< Shifted mode DEFAULT for EMU_IEN */
3708 #define EMU_IEN_VMONIO1RISE                                  (0x1UL << 9)                                  /**< VMONIO1RISE Interrupt Enable */
3709 #define _EMU_IEN_VMONIO1RISE_SHIFT                           9                                             /**< Shift value for EMU_VMONIO1RISE */
3710 #define _EMU_IEN_VMONIO1RISE_MASK                            0x200UL                                       /**< Bit mask for EMU_VMONIO1RISE */
3711 #define _EMU_IEN_VMONIO1RISE_DEFAULT                         0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3712 #define EMU_IEN_VMONIO1RISE_DEFAULT                          (_EMU_IEN_VMONIO1RISE_DEFAULT << 9)           /**< Shifted mode DEFAULT for EMU_IEN */
3713 #define EMU_IEN_R5VREADY                                     (0x1UL << 10)                                 /**< R5VREADY Interrupt Enable */
3714 #define _EMU_IEN_R5VREADY_SHIFT                              10                                            /**< Shift value for EMU_R5VREADY */
3715 #define _EMU_IEN_R5VREADY_MASK                               0x400UL                                       /**< Bit mask for EMU_R5VREADY */
3716 #define _EMU_IEN_R5VREADY_DEFAULT                            0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3717 #define EMU_IEN_R5VREADY_DEFAULT                             (_EMU_IEN_R5VREADY_DEFAULT << 10)             /**< Shifted mode DEFAULT for EMU_IEN */
3718 #define EMU_IEN_VMONBUVDDFALL                                (0x1UL << 12)                                 /**< VMONBUVDDFALL Interrupt Enable */
3719 #define _EMU_IEN_VMONBUVDDFALL_SHIFT                         12                                            /**< Shift value for EMU_VMONBUVDDFALL */
3720 #define _EMU_IEN_VMONBUVDDFALL_MASK                          0x1000UL                                      /**< Bit mask for EMU_VMONBUVDDFALL */
3721 #define _EMU_IEN_VMONBUVDDFALL_DEFAULT                       0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3722 #define EMU_IEN_VMONBUVDDFALL_DEFAULT                        (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12)        /**< Shifted mode DEFAULT for EMU_IEN */
3723 #define EMU_IEN_VMONBUVDDRISE                                (0x1UL << 13)                                 /**< VMONBUVDDRISE Interrupt Enable */
3724 #define _EMU_IEN_VMONBUVDDRISE_SHIFT                         13                                            /**< Shift value for EMU_VMONBUVDDRISE */
3725 #define _EMU_IEN_VMONBUVDDRISE_MASK                          0x2000UL                                      /**< Bit mask for EMU_VMONBUVDDRISE */
3726 #define _EMU_IEN_VMONBUVDDRISE_DEFAULT                       0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3727 #define EMU_IEN_VMONBUVDDRISE_DEFAULT                        (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13)        /**< Shifted mode DEFAULT for EMU_IEN */
3728 #define EMU_IEN_PFETOVERCURRENTLIMIT                         (0x1UL << 16)                                 /**< PFETOVERCURRENTLIMIT Interrupt Enable */
3729 #define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT                  16                                            /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
3730 #define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK                   0x10000UL                                     /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
3731 #define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3732 #define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT                 (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */
3733 #define EMU_IEN_NFETOVERCURRENTLIMIT                         (0x1UL << 17)                                 /**< NFETOVERCURRENTLIMIT Interrupt Enable */
3734 #define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT                  17                                            /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
3735 #define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK                   0x20000UL                                     /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
3736 #define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3737 #define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT                 (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */
3738 #define EMU_IEN_DCDCLPRUNNING                                (0x1UL << 18)                                 /**< DCDCLPRUNNING Interrupt Enable */
3739 #define _EMU_IEN_DCDCLPRUNNING_SHIFT                         18                                            /**< Shift value for EMU_DCDCLPRUNNING */
3740 #define _EMU_IEN_DCDCLPRUNNING_MASK                          0x40000UL                                     /**< Bit mask for EMU_DCDCLPRUNNING */
3741 #define _EMU_IEN_DCDCLPRUNNING_DEFAULT                       0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3742 #define EMU_IEN_DCDCLPRUNNING_DEFAULT                        (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18)        /**< Shifted mode DEFAULT for EMU_IEN */
3743 #define EMU_IEN_DCDCLNRUNNING                                (0x1UL << 19)                                 /**< DCDCLNRUNNING Interrupt Enable */
3744 #define _EMU_IEN_DCDCLNRUNNING_SHIFT                         19                                            /**< Shift value for EMU_DCDCLNRUNNING */
3745 #define _EMU_IEN_DCDCLNRUNNING_MASK                          0x80000UL                                     /**< Bit mask for EMU_DCDCLNRUNNING */
3746 #define _EMU_IEN_DCDCLNRUNNING_DEFAULT                       0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3747 #define EMU_IEN_DCDCLNRUNNING_DEFAULT                        (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19)        /**< Shifted mode DEFAULT for EMU_IEN */
3748 #define EMU_IEN_DCDCINBYPASS                                 (0x1UL << 20)                                 /**< DCDCINBYPASS Interrupt Enable */
3749 #define _EMU_IEN_DCDCINBYPASS_SHIFT                          20                                            /**< Shift value for EMU_DCDCINBYPASS */
3750 #define _EMU_IEN_DCDCINBYPASS_MASK                           0x100000UL                                    /**< Bit mask for EMU_DCDCINBYPASS */
3751 #define _EMU_IEN_DCDCINBYPASS_DEFAULT                        0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3752 #define EMU_IEN_DCDCINBYPASS_DEFAULT                         (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20)         /**< Shifted mode DEFAULT for EMU_IEN */
3753 #define EMU_IEN_BURDY                                        (0x1UL << 22)                                 /**< BURDY Interrupt Enable */
3754 #define _EMU_IEN_BURDY_SHIFT                                 22                                            /**< Shift value for EMU_BURDY */
3755 #define _EMU_IEN_BURDY_MASK                                  0x400000UL                                    /**< Bit mask for EMU_BURDY */
3756 #define _EMU_IEN_BURDY_DEFAULT                               0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3757 #define EMU_IEN_BURDY_DEFAULT                                (_EMU_IEN_BURDY_DEFAULT << 22)                /**< Shifted mode DEFAULT for EMU_IEN */
3758 #define EMU_IEN_R5VVSINT                                     (0x1UL << 23)                                 /**< R5VVSINT Interrupt Enable */
3759 #define _EMU_IEN_R5VVSINT_SHIFT                              23                                            /**< Shift value for EMU_R5VVSINT */
3760 #define _EMU_IEN_R5VVSINT_MASK                               0x800000UL                                    /**< Bit mask for EMU_R5VVSINT */
3761 #define _EMU_IEN_R5VVSINT_DEFAULT                            0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3762 #define EMU_IEN_R5VVSINT_DEFAULT                             (_EMU_IEN_R5VVSINT_DEFAULT << 23)             /**< Shifted mode DEFAULT for EMU_IEN */
3763 #define EMU_IEN_EM23WAKEUP                                   (0x1UL << 24)                                 /**< EM23WAKEUP Interrupt Enable */
3764 #define _EMU_IEN_EM23WAKEUP_SHIFT                            24                                            /**< Shift value for EMU_EM23WAKEUP */
3765 #define _EMU_IEN_EM23WAKEUP_MASK                             0x1000000UL                                   /**< Bit mask for EMU_EM23WAKEUP */
3766 #define _EMU_IEN_EM23WAKEUP_DEFAULT                          0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3767 #define EMU_IEN_EM23WAKEUP_DEFAULT                           (_EMU_IEN_EM23WAKEUP_DEFAULT << 24)           /**< Shifted mode DEFAULT for EMU_IEN */
3768 #define EMU_IEN_VSCALEDONE                                   (0x1UL << 25)                                 /**< VSCALEDONE Interrupt Enable */
3769 #define _EMU_IEN_VSCALEDONE_SHIFT                            25                                            /**< Shift value for EMU_VSCALEDONE */
3770 #define _EMU_IEN_VSCALEDONE_MASK                             0x2000000UL                                   /**< Bit mask for EMU_VSCALEDONE */
3771 #define _EMU_IEN_VSCALEDONE_DEFAULT                          0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3772 #define EMU_IEN_VSCALEDONE_DEFAULT                           (_EMU_IEN_VSCALEDONE_DEFAULT << 25)           /**< Shifted mode DEFAULT for EMU_IEN */
3773 #define EMU_IEN_TEMP                                         (0x1UL << 29)                                 /**< TEMP Interrupt Enable */
3774 #define _EMU_IEN_TEMP_SHIFT                                  29                                            /**< Shift value for EMU_TEMP */
3775 #define _EMU_IEN_TEMP_MASK                                   0x20000000UL                                  /**< Bit mask for EMU_TEMP */
3776 #define _EMU_IEN_TEMP_DEFAULT                                0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3777 #define EMU_IEN_TEMP_DEFAULT                                 (_EMU_IEN_TEMP_DEFAULT << 29)                 /**< Shifted mode DEFAULT for EMU_IEN */
3778 #define EMU_IEN_TEMPLOW                                      (0x1UL << 30)                                 /**< TEMPLOW Interrupt Enable */
3779 #define _EMU_IEN_TEMPLOW_SHIFT                               30                                            /**< Shift value for EMU_TEMPLOW */
3780 #define _EMU_IEN_TEMPLOW_MASK                                0x40000000UL                                  /**< Bit mask for EMU_TEMPLOW */
3781 #define _EMU_IEN_TEMPLOW_DEFAULT                             0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3782 #define EMU_IEN_TEMPLOW_DEFAULT                              (_EMU_IEN_TEMPLOW_DEFAULT << 30)              /**< Shifted mode DEFAULT for EMU_IEN */
3783 #define EMU_IEN_TEMPHIGH                                     (0x1UL << 31)                                 /**< TEMPHIGH Interrupt Enable */
3784 #define _EMU_IEN_TEMPHIGH_SHIFT                              31                                            /**< Shift value for EMU_TEMPHIGH */
3785 #define _EMU_IEN_TEMPHIGH_MASK                               0x80000000UL                                  /**< Bit mask for EMU_TEMPHIGH */
3786 #define _EMU_IEN_TEMPHIGH_DEFAULT                            0x00000000UL                                  /**< Mode DEFAULT for EMU_IEN */
3787 #define EMU_IEN_TEMPHIGH_DEFAULT                             (_EMU_IEN_TEMPHIGH_DEFAULT << 31)             /**< Shifted mode DEFAULT for EMU_IEN */
3788 
3789 /* Bit fields for EMU PWRLOCK */
3790 #define _EMU_PWRLOCK_RESETVALUE                              0x00000000UL                         /**< Default value for EMU_PWRLOCK */
3791 #define _EMU_PWRLOCK_MASK                                    0x0000FFFFUL                         /**< Mask for EMU_PWRLOCK */
3792 #define _EMU_PWRLOCK_LOCKKEY_SHIFT                           0                                    /**< Shift value for EMU_LOCKKEY */
3793 #define _EMU_PWRLOCK_LOCKKEY_MASK                            0xFFFFUL                             /**< Bit mask for EMU_LOCKKEY */
3794 #define _EMU_PWRLOCK_LOCKKEY_DEFAULT                         0x00000000UL                         /**< Mode DEFAULT for EMU_PWRLOCK */
3795 #define _EMU_PWRLOCK_LOCKKEY_UNLOCKED                        0x00000000UL                         /**< Mode UNLOCKED for EMU_PWRLOCK */
3796 #define _EMU_PWRLOCK_LOCKKEY_LOCK                            0x00000000UL                         /**< Mode LOCK for EMU_PWRLOCK */
3797 #define _EMU_PWRLOCK_LOCKKEY_LOCKED                          0x00000001UL                         /**< Mode LOCKED for EMU_PWRLOCK */
3798 #define _EMU_PWRLOCK_LOCKKEY_UNLOCK                          0x0000ADE8UL                         /**< Mode UNLOCK for EMU_PWRLOCK */
3799 #define EMU_PWRLOCK_LOCKKEY_DEFAULT                          (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for EMU_PWRLOCK */
3800 #define EMU_PWRLOCK_LOCKKEY_UNLOCKED                         (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */
3801 #define EMU_PWRLOCK_LOCKKEY_LOCK                             (_EMU_PWRLOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for EMU_PWRLOCK */
3802 #define EMU_PWRLOCK_LOCKKEY_LOCKED                           (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for EMU_PWRLOCK */
3803 #define EMU_PWRLOCK_LOCKKEY_UNLOCK                           (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for EMU_PWRLOCK */
3804 
3805 /* Bit fields for EMU PWRCTRL */
3806 #define _EMU_PWRCTRL_RESETVALUE                              0x00000000UL                                    /**< Default value for EMU_PWRCTRL */
3807 #define _EMU_PWRCTRL_MASK                                    0x00002420UL                                    /**< Mask for EMU_PWRCTRL */
3808 #define EMU_PWRCTRL_ANASW                                    (0x1UL << 5)                                    /**< Analog Switch Selection */
3809 #define _EMU_PWRCTRL_ANASW_SHIFT                             5                                               /**< Shift value for EMU_ANASW */
3810 #define _EMU_PWRCTRL_ANASW_MASK                              0x20UL                                          /**< Bit mask for EMU_ANASW */
3811 #define _EMU_PWRCTRL_ANASW_DEFAULT                           0x00000000UL                                    /**< Mode DEFAULT for EMU_PWRCTRL */
3812 #define _EMU_PWRCTRL_ANASW_AVDD                              0x00000000UL                                    /**< Mode AVDD for EMU_PWRCTRL */
3813 #define _EMU_PWRCTRL_ANASW_DVDD                              0x00000001UL                                    /**< Mode DVDD for EMU_PWRCTRL */
3814 #define EMU_PWRCTRL_ANASW_DEFAULT                            (_EMU_PWRCTRL_ANASW_DEFAULT << 5)               /**< Shifted mode DEFAULT for EMU_PWRCTRL */
3815 #define EMU_PWRCTRL_ANASW_AVDD                               (_EMU_PWRCTRL_ANASW_AVDD << 5)                  /**< Shifted mode AVDD for EMU_PWRCTRL */
3816 #define EMU_PWRCTRL_ANASW_DVDD                               (_EMU_PWRCTRL_ANASW_DVDD << 5)                  /**< Shifted mode DVDD for EMU_PWRCTRL */
3817 #define EMU_PWRCTRL_REGPWRSEL                                (0x1UL << 10)                                   /**< This Field Selects the Input Supply Pin for the Digital LDO */
3818 #define _EMU_PWRCTRL_REGPWRSEL_SHIFT                         10                                              /**< Shift value for EMU_REGPWRSEL */
3819 #define _EMU_PWRCTRL_REGPWRSEL_MASK                          0x400UL                                         /**< Bit mask for EMU_REGPWRSEL */
3820 #define _EMU_PWRCTRL_REGPWRSEL_DEFAULT                       0x00000000UL                                    /**< Mode DEFAULT for EMU_PWRCTRL */
3821 #define _EMU_PWRCTRL_REGPWRSEL_AVDD                          0x00000000UL                                    /**< Mode AVDD for EMU_PWRCTRL */
3822 #define _EMU_PWRCTRL_REGPWRSEL_DVDD                          0x00000001UL                                    /**< Mode DVDD for EMU_PWRCTRL */
3823 #define EMU_PWRCTRL_REGPWRSEL_DEFAULT                        (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10)          /**< Shifted mode DEFAULT for EMU_PWRCTRL */
3824 #define EMU_PWRCTRL_REGPWRSEL_AVDD                           (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10)             /**< Shifted mode AVDD for EMU_PWRCTRL */
3825 #define EMU_PWRCTRL_REGPWRSEL_DVDD                           (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10)             /**< Shifted mode DVDD for EMU_PWRCTRL */
3826 #define EMU_PWRCTRL_IMMEDIATEPWRSWITCH                       (0x1UL << 13)                                   /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */
3827 #define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT                13                                              /**< Shift value for EMU_IMMEDIATEPWRSWITCH */
3828 #define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK                 0x2000UL                                        /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */
3829 #define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT              0x00000000UL                                    /**< Mode DEFAULT for EMU_PWRCTRL */
3830 #define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT               (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */
3831 
3832 /* Bit fields for EMU DCDCCTRL */
3833 #define _EMU_DCDCCTRL_RESETVALUE                             0x00000033UL                                   /**< Default value for EMU_DCDCCTRL */
3834 #define _EMU_DCDCCTRL_MASK                                   0x00000033UL                                   /**< Mask for EMU_DCDCCTRL */
3835 #define _EMU_DCDCCTRL_DCDCMODE_SHIFT                         0                                              /**< Shift value for EMU_DCDCMODE */
3836 #define _EMU_DCDCCTRL_DCDCMODE_MASK                          0x3UL                                          /**< Bit mask for EMU_DCDCMODE */
3837 #define _EMU_DCDCCTRL_DCDCMODE_BYPASS                        0x00000000UL                                   /**< Mode BYPASS for EMU_DCDCCTRL */
3838 #define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE                      0x00000001UL                                   /**< Mode LOWNOISE for EMU_DCDCCTRL */
3839 #define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER                      0x00000002UL                                   /**< Mode LOWPOWER for EMU_DCDCCTRL */
3840 #define _EMU_DCDCCTRL_DCDCMODE_DEFAULT                       0x00000003UL                                   /**< Mode DEFAULT for EMU_DCDCCTRL */
3841 #define _EMU_DCDCCTRL_DCDCMODE_OFF                           0x00000003UL                                   /**< Mode OFF for EMU_DCDCCTRL */
3842 #define EMU_DCDCCTRL_DCDCMODE_BYPASS                         (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0)           /**< Shifted mode BYPASS for EMU_DCDCCTRL */
3843 #define EMU_DCDCCTRL_DCDCMODE_LOWNOISE                       (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0)         /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */
3844 #define EMU_DCDCCTRL_DCDCMODE_LOWPOWER                       (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0)         /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */
3845 #define EMU_DCDCCTRL_DCDCMODE_DEFAULT                        (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0)          /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
3846 #define EMU_DCDCCTRL_DCDCMODE_OFF                            (_EMU_DCDCCTRL_DCDCMODE_OFF << 0)              /**< Shifted mode OFF for EMU_DCDCCTRL */
3847 #define EMU_DCDCCTRL_DCDCMODEEM23                            (0x1UL << 4)                                   /**< DCDC Mode EM23 */
3848 #define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT                     4                                              /**< Shift value for EMU_DCDCMODEEM23 */
3849 #define _EMU_DCDCCTRL_DCDCMODEEM23_MASK                      0x10UL                                         /**< Bit mask for EMU_DCDCMODEEM23 */
3850 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW                    0x00000000UL                                   /**< Mode EM23SW for EMU_DCDCCTRL */
3851 #define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT                   0x00000001UL                                   /**< Mode DEFAULT for EMU_DCDCCTRL */
3852 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER              0x00000001UL                                   /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */
3853 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW                     (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4)       /**< Shifted mode EM23SW for EMU_DCDCCTRL */
3854 #define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT                    (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4)      /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
3855 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER               (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */
3856 #define EMU_DCDCCTRL_DCDCMODEEM4                             (0x1UL << 5)                                   /**< DCDC Mode EM4H */
3857 #define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT                      5                                              /**< Shift value for EMU_DCDCMODEEM4 */
3858 #define _EMU_DCDCCTRL_DCDCMODEEM4_MASK                       0x20UL                                         /**< Bit mask for EMU_DCDCMODEEM4 */
3859 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW                      0x00000000UL                                   /**< Mode EM4SW for EMU_DCDCCTRL */
3860 #define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT                    0x00000001UL                                   /**< Mode DEFAULT for EMU_DCDCCTRL */
3861 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER                0x00000001UL                                   /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */
3862 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW                       (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5)         /**< Shifted mode EM4SW for EMU_DCDCCTRL */
3863 #define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT                     (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5)       /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
3864 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER                 (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5)   /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */
3865 
3866 /* Bit fields for EMU DCDCMISCCTRL */
3867 #define _EMU_DCDCMISCCTRL_RESETVALUE                         0x03107706UL                                      /**< Default value for EMU_DCDCMISCCTRL */
3868 #define _EMU_DCDCMISCCTRL_MASK                               0x377FFF27UL                                      /**< Mask for EMU_DCDCMISCCTRL */
3869 #define EMU_DCDCMISCCTRL_LNFORCECCM                          (0x1UL << 0)                                      /**< Force DCDC Into CCM Mode in Low Noise Operation */
3870 #define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT                   0                                                 /**< Shift value for EMU_LNFORCECCM */
3871 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK                    0x1UL                                             /**< Bit mask for EMU_LNFORCECCM */
3872 #define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT                 0x00000000UL                                      /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
3873 #define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT                  (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0)       /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
3874 #define EMU_DCDCMISCCTRL_LPCMPHYSDIS                         (0x1UL << 1)                                      /**< Disable LP Mode Hysteresis in the State Machine Control */
3875 #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT                  1                                                 /**< Shift value for EMU_LPCMPHYSDIS */
3876 #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK                   0x2UL                                             /**< Bit mask for EMU_LPCMPHYSDIS */
3877 #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT                0x00000001UL                                      /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
3878 #define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT                 (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1)      /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
3879 #define EMU_DCDCMISCCTRL_LPCMPHYSHI                          (0x1UL << 2)                                      /**< Comparator Threshold on the High Side */
3880 #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT                   2                                                 /**< Shift value for EMU_LPCMPHYSHI */
3881 #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK                    0x4UL                                             /**< Bit mask for EMU_LPCMPHYSHI */
3882 #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT                 0x00000001UL                                      /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
3883 #define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT                  (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
3884 #define EMU_DCDCMISCCTRL_LNFORCECCMIMM                       (0x1UL << 5)                                      /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */
3885 #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT                5                                                 /**< Shift value for EMU_LNFORCECCMIMM */
3886 #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK                 0x20UL                                            /**< Bit mask for EMU_LNFORCECCMIMM */
3887 #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT              0x00000000UL                                      /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
3888 #define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT               (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5)    /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
3889 #define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT                      8                                                 /**< Shift value for EMU_PFETCNT */
3890 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK                       0xF00UL                                           /**< Bit mask for EMU_PFETCNT */
3891 #define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT                    0x00000007UL                                      /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
3892 #define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT                     (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8)          /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
3893 #define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT                      12                                                /**< Shift value for EMU_NFETCNT */
3894 #define _EMU_DCDCMISCCTRL_NFETCNT_MASK                       0xF000UL                                          /**< Bit mask for EMU_NFETCNT */
3895 #define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT                    0x00000007UL                                      /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
3896 #define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT                     (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12)         /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
3897 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT                    16                                                /**< Shift value for EMU_BYPLIMSEL */
3898 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK                     0xF0000UL                                         /**< Bit mask for EMU_BYPLIMSEL */
3899 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT                  0x00000000UL                                      /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
3900 #define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT                   (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16)       /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
3901 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT                20                                                /**< Shift value for EMU_LPCLIMILIMSEL */
3902 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK                 0x700000UL                                        /**< Bit mask for EMU_LPCLIMILIMSEL */
3903 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT              0x00000001UL                                      /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
3904 #define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT               (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20)   /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
3905 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT                24                                                /**< Shift value for EMU_LNCLIMILIMSEL */
3906 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK                 0x7000000UL                                       /**< Bit mask for EMU_LNCLIMILIMSEL */
3907 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT              0x00000003UL                                      /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
3908 #define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT               (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24)   /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
3909 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT              28                                                /**< Shift value for EMU_LPCMPBIASEM234H */
3910 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK               0x30000000UL                                      /**< Bit mask for EMU_LPCMPBIASEM234H */
3911 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT            0x00000000UL                                      /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
3912 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0              0x00000000UL                                      /**< Mode BIAS0 for EMU_DCDCMISCCTRL */
3913 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1              0x00000001UL                                      /**< Mode BIAS1 for EMU_DCDCMISCCTRL */
3914 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2              0x00000002UL                                      /**< Mode BIAS2 for EMU_DCDCMISCCTRL */
3915 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3              0x00000003UL                                      /**< Mode BIAS3 for EMU_DCDCMISCCTRL */
3916 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT             (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
3917 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0               (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28)   /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */
3918 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1               (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28)   /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */
3919 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2               (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28)   /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */
3920 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3               (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28)   /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */
3921 
3922 /* Bit fields for EMU DCDCZDETCTRL */
3923 #define _EMU_DCDCZDETCTRL_RESETVALUE                         0x00000150UL                                  /**< Default value for EMU_DCDCZDETCTRL */
3924 #define _EMU_DCDCZDETCTRL_MASK                               0x00000370UL                                  /**< Mask for EMU_DCDCZDETCTRL */
3925 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT                  4                                             /**< Shift value for EMU_ZDETILIMSEL */
3926 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK                   0x70UL                                        /**< Bit mask for EMU_ZDETILIMSEL */
3927 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT                0x00000005UL                                  /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
3928 #define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT                 (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4)  /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
3929 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT                 8                                             /**< Shift value for EMU_ZDETBLANKDLY */
3930 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK                  0x300UL                                       /**< Bit mask for EMU_ZDETBLANKDLY */
3931 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT               0x00000001UL                                  /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
3932 #define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT                (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
3933 
3934 /* Bit fields for EMU DCDCCLIMCTRL */
3935 #define _EMU_DCDCCLIMCTRL_RESETVALUE                         0x00000100UL                                  /**< Default value for EMU_DCDCCLIMCTRL */
3936 #define _EMU_DCDCCLIMCTRL_MASK                               0x00002300UL                                  /**< Mask for EMU_DCDCCLIMCTRL */
3937 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT                 8                                             /**< Shift value for EMU_CLIMBLANKDLY */
3938 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK                  0x300UL                                       /**< Bit mask for EMU_CLIMBLANKDLY */
3939 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT               0x00000001UL                                  /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
3940 #define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT                (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
3941 #define EMU_DCDCCLIMCTRL_BYPLIMEN                            (0x1UL << 13)                                 /**< Bypass Current Limit Enable */
3942 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT                     13                                            /**< Shift value for EMU_BYPLIMEN */
3943 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK                      0x2000UL                                      /**< Bit mask for EMU_BYPLIMEN */
3944 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT                   0x00000000UL                                  /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
3945 #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT                    (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13)    /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
3946 
3947 /* Bit fields for EMU DCDCLNCOMPCTRL */
3948 #define _EMU_DCDCLNCOMPCTRL_RESETVALUE                       0x57204077UL                                 /**< Default value for EMU_DCDCLNCOMPCTRL */
3949 #define _EMU_DCDCLNCOMPCTRL_MASK                             0xF730F1F7UL                                 /**< Mask for EMU_DCDCLNCOMPCTRL */
3950 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT                   0                                            /**< Shift value for EMU_COMPENR1 */
3951 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK                    0x7UL                                        /**< Bit mask for EMU_COMPENR1 */
3952 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT                 0x00000007UL                                 /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
3953 #define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT                  (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0)  /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
3954 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT                   4                                            /**< Shift value for EMU_COMPENR2 */
3955 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK                    0x1F0UL                                      /**< Bit mask for EMU_COMPENR2 */
3956 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT                 0x00000007UL                                 /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
3957 #define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT                  (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4)  /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
3958 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT                   12                                           /**< Shift value for EMU_COMPENR3 */
3959 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK                    0xF000UL                                     /**< Bit mask for EMU_COMPENR3 */
3960 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT                 0x00000004UL                                 /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
3961 #define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT                  (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
3962 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT                   20                                           /**< Shift value for EMU_COMPENC1 */
3963 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK                    0x300000UL                                   /**< Bit mask for EMU_COMPENC1 */
3964 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT                 0x00000002UL                                 /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
3965 #define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT                  (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
3966 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT                   24                                           /**< Shift value for EMU_COMPENC2 */
3967 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK                    0x7000000UL                                  /**< Bit mask for EMU_COMPENC2 */
3968 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT                 0x00000007UL                                 /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
3969 #define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT                  (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
3970 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT                   28                                           /**< Shift value for EMU_COMPENC3 */
3971 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK                    0xF0000000UL                                 /**< Bit mask for EMU_COMPENC3 */
3972 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT                 0x00000005UL                                 /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
3973 #define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT                  (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
3974 
3975 /* Bit fields for EMU DCDCLNVCTRL */
3976 #define _EMU_DCDCLNVCTRL_RESETVALUE                          0x00007100UL                           /**< Default value for EMU_DCDCLNVCTRL */
3977 #define _EMU_DCDCLNVCTRL_MASK                                0x00007F02UL                           /**< Mask for EMU_DCDCLNVCTRL */
3978 #define EMU_DCDCLNVCTRL_LNATT                                (0x1UL << 1)                           /**< Low Noise Mode Feedback Attenuation */
3979 #define _EMU_DCDCLNVCTRL_LNATT_SHIFT                         1                                      /**< Shift value for EMU_LNATT */
3980 #define _EMU_DCDCLNVCTRL_LNATT_MASK                          0x2UL                                  /**< Bit mask for EMU_LNATT */
3981 #define _EMU_DCDCLNVCTRL_LNATT_DEFAULT                       0x00000000UL                           /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
3982 #define _EMU_DCDCLNVCTRL_LNATT_DIV3                          0x00000000UL                           /**< Mode DIV3 for EMU_DCDCLNVCTRL */
3983 #define _EMU_DCDCLNVCTRL_LNATT_DIV6                          0x00000001UL                           /**< Mode DIV6 for EMU_DCDCLNVCTRL */
3984 #define EMU_DCDCLNVCTRL_LNATT_DEFAULT                        (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1)  /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
3985 #define EMU_DCDCLNVCTRL_LNATT_DIV3                           (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1)     /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */
3986 #define EMU_DCDCLNVCTRL_LNATT_DIV6                           (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1)     /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */
3987 #define _EMU_DCDCLNVCTRL_LNVREF_SHIFT                        8                                      /**< Shift value for EMU_LNVREF */
3988 #define _EMU_DCDCLNVCTRL_LNVREF_MASK                         0x7F00UL                               /**< Bit mask for EMU_LNVREF */
3989 #define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT                      0x00000071UL                           /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
3990 #define EMU_DCDCLNVCTRL_LNVREF_DEFAULT                       (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
3991 
3992 /* Bit fields for EMU DCDCLPVCTRL */
3993 #define _EMU_DCDCLPVCTRL_RESETVALUE                          0x00000168UL                           /**< Default value for EMU_DCDCLPVCTRL */
3994 #define _EMU_DCDCLPVCTRL_MASK                                0x000001FFUL                           /**< Mask for EMU_DCDCLPVCTRL */
3995 #define EMU_DCDCLPVCTRL_LPATT                                (0x1UL << 0)                           /**< Low Power Feedback Attenuation */
3996 #define _EMU_DCDCLPVCTRL_LPATT_SHIFT                         0                                      /**< Shift value for EMU_LPATT */
3997 #define _EMU_DCDCLPVCTRL_LPATT_MASK                          0x1UL                                  /**< Bit mask for EMU_LPATT */
3998 #define _EMU_DCDCLPVCTRL_LPATT_DEFAULT                       0x00000000UL                           /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
3999 #define _EMU_DCDCLPVCTRL_LPATT_DIV4                          0x00000000UL                           /**< Mode DIV4 for EMU_DCDCLPVCTRL */
4000 #define _EMU_DCDCLPVCTRL_LPATT_DIV8                          0x00000001UL                           /**< Mode DIV8 for EMU_DCDCLPVCTRL */
4001 #define EMU_DCDCLPVCTRL_LPATT_DEFAULT                        (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0)  /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
4002 #define EMU_DCDCLPVCTRL_LPATT_DIV4                           (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0)     /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */
4003 #define EMU_DCDCLPVCTRL_LPATT_DIV8                           (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0)     /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */
4004 #define _EMU_DCDCLPVCTRL_LPVREF_SHIFT                        1                                      /**< Shift value for EMU_LPVREF */
4005 #define _EMU_DCDCLPVCTRL_LPVREF_MASK                         0x1FEUL                                /**< Bit mask for EMU_LPVREF */
4006 #define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT                      0x000000B4UL                           /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
4007 #define EMU_DCDCLPVCTRL_LPVREF_DEFAULT                       (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
4008 
4009 /* Bit fields for EMU DCDCLPCTRL */
4010 #define _EMU_DCDCLPCTRL_RESETVALUE                           0x03000000UL                                      /**< Default value for EMU_DCDCLPCTRL */
4011 #define _EMU_DCDCLPCTRL_MASK                                 0x0700F000UL                                      /**< Mask for EMU_DCDCLPCTRL */
4012 #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT              12                                                /**< Shift value for EMU_LPCMPHYSSELEM234H */
4013 #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK               0xF000UL                                          /**< Bit mask for EMU_LPCMPHYSSELEM234H */
4014 #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT            0x00000000UL                                      /**< Mode DEFAULT for EMU_DCDCLPCTRL */
4015 #define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT             (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
4016 #define EMU_DCDCLPCTRL_LPVREFDUTYEN                          (0x1UL << 24)                                     /**< LP Mode Duty Cycling Enable */
4017 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT                   24                                                /**< Shift value for EMU_LPVREFDUTYEN */
4018 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK                    0x1000000UL                                       /**< Bit mask for EMU_LPVREFDUTYEN */
4019 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT                 0x00000001UL                                      /**< Mode DEFAULT for EMU_DCDCLPCTRL */
4020 #define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT                  (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24)      /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
4021 #define _EMU_DCDCLPCTRL_LPBLANK_SHIFT                        25                                                /**< Shift value for EMU_LPBLANK */
4022 #define _EMU_DCDCLPCTRL_LPBLANK_MASK                         0x6000000UL                                       /**< Bit mask for EMU_LPBLANK */
4023 #define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT                      0x00000001UL                                      /**< Mode DEFAULT for EMU_DCDCLPCTRL */
4024 #define EMU_DCDCLPCTRL_LPBLANK_DEFAULT                       (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25)           /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
4025 
4026 /* Bit fields for EMU DCDCLNFREQCTRL */
4027 #define _EMU_DCDCLNFREQCTRL_RESETVALUE                       0x10000000UL                                /**< Default value for EMU_DCDCLNFREQCTRL */
4028 #define _EMU_DCDCLNFREQCTRL_MASK                             0x1F000007UL                                /**< Mask for EMU_DCDCLNFREQCTRL */
4029 #define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT                    0                                           /**< Shift value for EMU_RCOBAND */
4030 #define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK                     0x7UL                                       /**< Bit mask for EMU_RCOBAND */
4031 #define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT                  0x00000000UL                                /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
4032 #define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT                   (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0)  /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
4033 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT                    24                                          /**< Shift value for EMU_RCOTRIM */
4034 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK                     0x1F000000UL                                /**< Bit mask for EMU_RCOTRIM */
4035 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT                  0x00000010UL                                /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
4036 #define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT                   (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
4037 
4038 /* Bit fields for EMU DCDCSYNC */
4039 #define _EMU_DCDCSYNC_RESETVALUE                             0x00000000UL                              /**< Default value for EMU_DCDCSYNC */
4040 #define _EMU_DCDCSYNC_MASK                                   0x00000001UL                              /**< Mask for EMU_DCDCSYNC */
4041 #define EMU_DCDCSYNC_DCDCCTRLBUSY                            (0x1UL << 0)                              /**< DCDC CTRL Register Transfer Busy */
4042 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT                     0                                         /**< Shift value for EMU_DCDCCTRLBUSY */
4043 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK                      0x1UL                                     /**< Bit mask for EMU_DCDCCTRLBUSY */
4044 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for EMU_DCDCSYNC */
4045 #define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT                    (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */
4046 
4047 /* Bit fields for EMU VMONAVDDCTRL */
4048 #define _EMU_VMONAVDDCTRL_RESETVALUE                         0x00000000UL                                      /**< Default value for EMU_VMONAVDDCTRL */
4049 #define _EMU_VMONAVDDCTRL_MASK                               0x00FFFF0DUL                                      /**< Mask for EMU_VMONAVDDCTRL */
4050 #define EMU_VMONAVDDCTRL_EN                                  (0x1UL << 0)                                      /**< Enable */
4051 #define _EMU_VMONAVDDCTRL_EN_SHIFT                           0                                                 /**< Shift value for EMU_EN */
4052 #define _EMU_VMONAVDDCTRL_EN_MASK                            0x1UL                                             /**< Bit mask for EMU_EN */
4053 #define _EMU_VMONAVDDCTRL_EN_DEFAULT                         0x00000000UL                                      /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
4054 #define EMU_VMONAVDDCTRL_EN_DEFAULT                          (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0)               /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
4055 #define EMU_VMONAVDDCTRL_RISEWU                              (0x1UL << 2)                                      /**< Rise Wakeup */
4056 #define _EMU_VMONAVDDCTRL_RISEWU_SHIFT                       2                                                 /**< Shift value for EMU_RISEWU */
4057 #define _EMU_VMONAVDDCTRL_RISEWU_MASK                        0x4UL                                             /**< Bit mask for EMU_RISEWU */
4058 #define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT                     0x00000000UL                                      /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
4059 #define EMU_VMONAVDDCTRL_RISEWU_DEFAULT                      (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2)           /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
4060 #define EMU_VMONAVDDCTRL_FALLWU                              (0x1UL << 3)                                      /**< Fall Wakeup */
4061 #define _EMU_VMONAVDDCTRL_FALLWU_SHIFT                       3                                                 /**< Shift value for EMU_FALLWU */
4062 #define _EMU_VMONAVDDCTRL_FALLWU_MASK                        0x8UL                                             /**< Bit mask for EMU_FALLWU */
4063 #define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT                     0x00000000UL                                      /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
4064 #define EMU_VMONAVDDCTRL_FALLWU_DEFAULT                      (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3)           /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
4065 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT                8                                                 /**< Shift value for EMU_FALLTHRESFINE */
4066 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK                 0xF00UL                                           /**< Bit mask for EMU_FALLTHRESFINE */
4067 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT              0x00000000UL                                      /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
4068 #define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT               (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8)    /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
4069 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT              12                                                /**< Shift value for EMU_FALLTHRESCOARSE */
4070 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK               0xF000UL                                          /**< Bit mask for EMU_FALLTHRESCOARSE */
4071 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT            0x00000000UL                                      /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
4072 #define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT             (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
4073 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT                16                                                /**< Shift value for EMU_RISETHRESFINE */
4074 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK                 0xF0000UL                                         /**< Bit mask for EMU_RISETHRESFINE */
4075 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT              0x00000000UL                                      /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
4076 #define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT               (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16)   /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
4077 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT              20                                                /**< Shift value for EMU_RISETHRESCOARSE */
4078 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK               0xF00000UL                                        /**< Bit mask for EMU_RISETHRESCOARSE */
4079 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT            0x00000000UL                                      /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
4080 #define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT             (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
4081 
4082 /* Bit fields for EMU VMONALTAVDDCTRL */
4083 #define _EMU_VMONALTAVDDCTRL_RESETVALUE                      0x00000000UL                                     /**< Default value for EMU_VMONALTAVDDCTRL */
4084 #define _EMU_VMONALTAVDDCTRL_MASK                            0x0000FF0DUL                                     /**< Mask for EMU_VMONALTAVDDCTRL */
4085 #define EMU_VMONALTAVDDCTRL_EN                               (0x1UL << 0)                                     /**< Enable */
4086 #define _EMU_VMONALTAVDDCTRL_EN_SHIFT                        0                                                /**< Shift value for EMU_EN */
4087 #define _EMU_VMONALTAVDDCTRL_EN_MASK                         0x1UL                                            /**< Bit mask for EMU_EN */
4088 #define _EMU_VMONALTAVDDCTRL_EN_DEFAULT                      0x00000000UL                                     /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
4089 #define EMU_VMONALTAVDDCTRL_EN_DEFAULT                       (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0)           /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
4090 #define EMU_VMONALTAVDDCTRL_RISEWU                           (0x1UL << 2)                                     /**< Rise Wakeup */
4091 #define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT                    2                                                /**< Shift value for EMU_RISEWU */
4092 #define _EMU_VMONALTAVDDCTRL_RISEWU_MASK                     0x4UL                                            /**< Bit mask for EMU_RISEWU */
4093 #define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT                  0x00000000UL                                     /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
4094 #define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT                   (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
4095 #define EMU_VMONALTAVDDCTRL_FALLWU                           (0x1UL << 3)                                     /**< Fall Wakeup */
4096 #define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT                    3                                                /**< Shift value for EMU_FALLWU */
4097 #define _EMU_VMONALTAVDDCTRL_FALLWU_MASK                     0x8UL                                            /**< Bit mask for EMU_FALLWU */
4098 #define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT                  0x00000000UL                                     /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
4099 #define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT                   (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
4100 #define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT                 8                                                /**< Shift value for EMU_THRESFINE */
4101 #define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK                  0xF00UL                                          /**< Bit mask for EMU_THRESFINE */
4102 #define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT               0x00000000UL                                     /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
4103 #define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT                (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8)    /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
4104 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT               12                                               /**< Shift value for EMU_THRESCOARSE */
4105 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK                0xF000UL                                         /**< Bit mask for EMU_THRESCOARSE */
4106 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT             0x00000000UL                                     /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
4107 #define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT              (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
4108 
4109 /* Bit fields for EMU VMONDVDDCTRL */
4110 #define _EMU_VMONDVDDCTRL_RESETVALUE                         0x00000000UL                                  /**< Default value for EMU_VMONDVDDCTRL */
4111 #define _EMU_VMONDVDDCTRL_MASK                               0x0000FF0DUL                                  /**< Mask for EMU_VMONDVDDCTRL */
4112 #define EMU_VMONDVDDCTRL_EN                                  (0x1UL << 0)                                  /**< Enable */
4113 #define _EMU_VMONDVDDCTRL_EN_SHIFT                           0                                             /**< Shift value for EMU_EN */
4114 #define _EMU_VMONDVDDCTRL_EN_MASK                            0x1UL                                         /**< Bit mask for EMU_EN */
4115 #define _EMU_VMONDVDDCTRL_EN_DEFAULT                         0x00000000UL                                  /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
4116 #define EMU_VMONDVDDCTRL_EN_DEFAULT                          (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0)           /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
4117 #define EMU_VMONDVDDCTRL_RISEWU                              (0x1UL << 2)                                  /**< Rise Wakeup */
4118 #define _EMU_VMONDVDDCTRL_RISEWU_SHIFT                       2                                             /**< Shift value for EMU_RISEWU */
4119 #define _EMU_VMONDVDDCTRL_RISEWU_MASK                        0x4UL                                         /**< Bit mask for EMU_RISEWU */
4120 #define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT                     0x00000000UL                                  /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
4121 #define EMU_VMONDVDDCTRL_RISEWU_DEFAULT                      (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
4122 #define EMU_VMONDVDDCTRL_FALLWU                              (0x1UL << 3)                                  /**< Fall Wakeup */
4123 #define _EMU_VMONDVDDCTRL_FALLWU_SHIFT                       3                                             /**< Shift value for EMU_FALLWU */
4124 #define _EMU_VMONDVDDCTRL_FALLWU_MASK                        0x8UL                                         /**< Bit mask for EMU_FALLWU */
4125 #define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT                     0x00000000UL                                  /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
4126 #define EMU_VMONDVDDCTRL_FALLWU_DEFAULT                      (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
4127 #define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT                    8                                             /**< Shift value for EMU_THRESFINE */
4128 #define _EMU_VMONDVDDCTRL_THRESFINE_MASK                     0xF00UL                                       /**< Bit mask for EMU_THRESFINE */
4129 #define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT                  0x00000000UL                                  /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
4130 #define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT                   (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8)    /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
4131 #define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT                  12                                            /**< Shift value for EMU_THRESCOARSE */
4132 #define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK                   0xF000UL                                      /**< Bit mask for EMU_THRESCOARSE */
4133 #define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT                0x00000000UL                                  /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
4134 #define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT                 (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
4135 
4136 /* Bit fields for EMU VMONIO0CTRL */
4137 #define _EMU_VMONIO0CTRL_RESETVALUE                          0x00000000UL                                 /**< Default value for EMU_VMONIO0CTRL */
4138 #define _EMU_VMONIO0CTRL_MASK                                0x0000FF1DUL                                 /**< Mask for EMU_VMONIO0CTRL */
4139 #define EMU_VMONIO0CTRL_EN                                   (0x1UL << 0)                                 /**< Enable */
4140 #define _EMU_VMONIO0CTRL_EN_SHIFT                            0                                            /**< Shift value for EMU_EN */
4141 #define _EMU_VMONIO0CTRL_EN_MASK                             0x1UL                                        /**< Bit mask for EMU_EN */
4142 #define _EMU_VMONIO0CTRL_EN_DEFAULT                          0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO0CTRL */
4143 #define EMU_VMONIO0CTRL_EN_DEFAULT                           (_EMU_VMONIO0CTRL_EN_DEFAULT << 0)           /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
4144 #define EMU_VMONIO0CTRL_RISEWU                               (0x1UL << 2)                                 /**< Rise Wakeup */
4145 #define _EMU_VMONIO0CTRL_RISEWU_SHIFT                        2                                            /**< Shift value for EMU_RISEWU */
4146 #define _EMU_VMONIO0CTRL_RISEWU_MASK                         0x4UL                                        /**< Bit mask for EMU_RISEWU */
4147 #define _EMU_VMONIO0CTRL_RISEWU_DEFAULT                      0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO0CTRL */
4148 #define EMU_VMONIO0CTRL_RISEWU_DEFAULT                       (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
4149 #define EMU_VMONIO0CTRL_FALLWU                               (0x1UL << 3)                                 /**< Fall Wakeup */
4150 #define _EMU_VMONIO0CTRL_FALLWU_SHIFT                        3                                            /**< Shift value for EMU_FALLWU */
4151 #define _EMU_VMONIO0CTRL_FALLWU_MASK                         0x8UL                                        /**< Bit mask for EMU_FALLWU */
4152 #define _EMU_VMONIO0CTRL_FALLWU_DEFAULT                      0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO0CTRL */
4153 #define EMU_VMONIO0CTRL_FALLWU_DEFAULT                       (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
4154 #define EMU_VMONIO0CTRL_RETDIS                               (0x1UL << 4)                                 /**< EM4 IO0 Retention Disable */
4155 #define _EMU_VMONIO0CTRL_RETDIS_SHIFT                        4                                            /**< Shift value for EMU_RETDIS */
4156 #define _EMU_VMONIO0CTRL_RETDIS_MASK                         0x10UL                                       /**< Bit mask for EMU_RETDIS */
4157 #define _EMU_VMONIO0CTRL_RETDIS_DEFAULT                      0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO0CTRL */
4158 #define EMU_VMONIO0CTRL_RETDIS_DEFAULT                       (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4)       /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
4159 #define _EMU_VMONIO0CTRL_THRESFINE_SHIFT                     8                                            /**< Shift value for EMU_THRESFINE */
4160 #define _EMU_VMONIO0CTRL_THRESFINE_MASK                      0xF00UL                                      /**< Bit mask for EMU_THRESFINE */
4161 #define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT                   0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO0CTRL */
4162 #define EMU_VMONIO0CTRL_THRESFINE_DEFAULT                    (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8)    /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
4163 #define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT                   12                                           /**< Shift value for EMU_THRESCOARSE */
4164 #define _EMU_VMONIO0CTRL_THRESCOARSE_MASK                    0xF000UL                                     /**< Bit mask for EMU_THRESCOARSE */
4165 #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT                 0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO0CTRL */
4166 #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT                  (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
4167 
4168 /* Bit fields for EMU VMONIO1CTRL */
4169 #define _EMU_VMONIO1CTRL_RESETVALUE                          0x00000000UL                                 /**< Default value for EMU_VMONIO1CTRL */
4170 #define _EMU_VMONIO1CTRL_MASK                                0x0000FF1DUL                                 /**< Mask for EMU_VMONIO1CTRL */
4171 #define EMU_VMONIO1CTRL_EN                                   (0x1UL << 0)                                 /**< Enable */
4172 #define _EMU_VMONIO1CTRL_EN_SHIFT                            0                                            /**< Shift value for EMU_EN */
4173 #define _EMU_VMONIO1CTRL_EN_MASK                             0x1UL                                        /**< Bit mask for EMU_EN */
4174 #define _EMU_VMONIO1CTRL_EN_DEFAULT                          0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO1CTRL */
4175 #define EMU_VMONIO1CTRL_EN_DEFAULT                           (_EMU_VMONIO1CTRL_EN_DEFAULT << 0)           /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */
4176 #define EMU_VMONIO1CTRL_RISEWU                               (0x1UL << 2)                                 /**< Rise Wakeup */
4177 #define _EMU_VMONIO1CTRL_RISEWU_SHIFT                        2                                            /**< Shift value for EMU_RISEWU */
4178 #define _EMU_VMONIO1CTRL_RISEWU_MASK                         0x4UL                                        /**< Bit mask for EMU_RISEWU */
4179 #define _EMU_VMONIO1CTRL_RISEWU_DEFAULT                      0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO1CTRL */
4180 #define EMU_VMONIO1CTRL_RISEWU_DEFAULT                       (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */
4181 #define EMU_VMONIO1CTRL_FALLWU                               (0x1UL << 3)                                 /**< Fall Wakeup */
4182 #define _EMU_VMONIO1CTRL_FALLWU_SHIFT                        3                                            /**< Shift value for EMU_FALLWU */
4183 #define _EMU_VMONIO1CTRL_FALLWU_MASK                         0x8UL                                        /**< Bit mask for EMU_FALLWU */
4184 #define _EMU_VMONIO1CTRL_FALLWU_DEFAULT                      0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO1CTRL */
4185 #define EMU_VMONIO1CTRL_FALLWU_DEFAULT                       (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */
4186 #define EMU_VMONIO1CTRL_RETDIS                               (0x1UL << 4)                                 /**< EM4 IO1 Retention Disable */
4187 #define _EMU_VMONIO1CTRL_RETDIS_SHIFT                        4                                            /**< Shift value for EMU_RETDIS */
4188 #define _EMU_VMONIO1CTRL_RETDIS_MASK                         0x10UL                                       /**< Bit mask for EMU_RETDIS */
4189 #define _EMU_VMONIO1CTRL_RETDIS_DEFAULT                      0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO1CTRL */
4190 #define EMU_VMONIO1CTRL_RETDIS_DEFAULT                       (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4)       /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */
4191 #define _EMU_VMONIO1CTRL_THRESFINE_SHIFT                     8                                            /**< Shift value for EMU_THRESFINE */
4192 #define _EMU_VMONIO1CTRL_THRESFINE_MASK                      0xF00UL                                      /**< Bit mask for EMU_THRESFINE */
4193 #define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT                   0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO1CTRL */
4194 #define EMU_VMONIO1CTRL_THRESFINE_DEFAULT                    (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8)    /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */
4195 #define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT                   12                                           /**< Shift value for EMU_THRESCOARSE */
4196 #define _EMU_VMONIO1CTRL_THRESCOARSE_MASK                    0xF000UL                                     /**< Bit mask for EMU_THRESCOARSE */
4197 #define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT                 0x00000000UL                                 /**< Mode DEFAULT for EMU_VMONIO1CTRL */
4198 #define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT                  (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */
4199 
4200 /* Bit fields for EMU VMONBUVDDCTRL */
4201 #define _EMU_VMONBUVDDCTRL_RESETVALUE                        0x00000000UL                                   /**< Default value for EMU_VMONBUVDDCTRL */
4202 #define _EMU_VMONBUVDDCTRL_MASK                              0x0000FF0DUL                                   /**< Mask for EMU_VMONBUVDDCTRL */
4203 #define EMU_VMONBUVDDCTRL_EN                                 (0x1UL << 0)                                   /**< Enable */
4204 #define _EMU_VMONBUVDDCTRL_EN_SHIFT                          0                                              /**< Shift value for EMU_EN */
4205 #define _EMU_VMONBUVDDCTRL_EN_MASK                           0x1UL                                          /**< Bit mask for EMU_EN */
4206 #define _EMU_VMONBUVDDCTRL_EN_DEFAULT                        0x00000000UL                                   /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */
4207 #define EMU_VMONBUVDDCTRL_EN_DEFAULT                         (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0)           /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */
4208 #define EMU_VMONBUVDDCTRL_RISEWU                             (0x1UL << 2)                                   /**< Rise Wakeup */
4209 #define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT                      2                                              /**< Shift value for EMU_RISEWU */
4210 #define _EMU_VMONBUVDDCTRL_RISEWU_MASK                       0x4UL                                          /**< Bit mask for EMU_RISEWU */
4211 #define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT                    0x00000000UL                                   /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */
4212 #define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT                     (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2)       /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */
4213 #define EMU_VMONBUVDDCTRL_FALLWU                             (0x1UL << 3)                                   /**< Fall Wakeup */
4214 #define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT                      3                                              /**< Shift value for EMU_FALLWU */
4215 #define _EMU_VMONBUVDDCTRL_FALLWU_MASK                       0x8UL                                          /**< Bit mask for EMU_FALLWU */
4216 #define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT                    0x00000000UL                                   /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */
4217 #define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT                     (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3)       /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */
4218 #define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT                   8                                              /**< Shift value for EMU_THRESFINE */
4219 #define _EMU_VMONBUVDDCTRL_THRESFINE_MASK                    0xF00UL                                        /**< Bit mask for EMU_THRESFINE */
4220 #define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT                 0x00000000UL                                   /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */
4221 #define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT                  (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8)    /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */
4222 #define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT                 12                                             /**< Shift value for EMU_THRESCOARSE */
4223 #define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK                  0xF000UL                                       /**< Bit mask for EMU_THRESCOARSE */
4224 #define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT               0x00000000UL                                   /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */
4225 #define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT                (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */
4226 
4227 /* Bit fields for EMU RAM1CTRL */
4228 #define _EMU_RAM1CTRL_RESETVALUE                             0x00000000UL                              /**< Default value for EMU_RAM1CTRL */
4229 #define _EMU_RAM1CTRL_MASK                                   0x0000000FUL                              /**< Mask for EMU_RAM1CTRL */
4230 #define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT                     0                                         /**< Shift value for EMU_RAMPOWERDOWN */
4231 #define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK                      0xFUL                                     /**< Bit mask for EMU_RAMPOWERDOWN */
4232 #define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for EMU_RAM1CTRL */
4233 #define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE                      0x00000000UL                              /**< Mode NONE for EMU_RAM1CTRL */
4234 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3                      0x00000008UL                              /**< Mode BLK3 for EMU_RAM1CTRL */
4235 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO3                   0x0000000CUL                              /**< Mode BLK2TO3 for EMU_RAM1CTRL */
4236 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO3                   0x0000000EUL                              /**< Mode BLK1TO3 for EMU_RAM1CTRL */
4237 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO3                   0x0000000FUL                              /**< Mode BLK0TO3 for EMU_RAM1CTRL */
4238 #define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT                    (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */
4239 #define EMU_RAM1CTRL_RAMPOWERDOWN_NONE                       (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0)    /**< Shifted mode NONE for EMU_RAM1CTRL */
4240 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3                       (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3 << 0)    /**< Shifted mode BLK3 for EMU_RAM1CTRL */
4241 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO3                    (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM1CTRL */
4242 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO3                    (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM1CTRL */
4243 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO3                    (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM1CTRL */
4244 
4245 /* Bit fields for EMU RAM2CTRL */
4246 #define _EMU_RAM2CTRL_RESETVALUE                             0x00000000UL                              /**< Default value for EMU_RAM2CTRL */
4247 #define _EMU_RAM2CTRL_MASK                                   0x0000000FUL                              /**< Mask for EMU_RAM2CTRL */
4248 #define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT                     0                                         /**< Shift value for EMU_RAMPOWERDOWN */
4249 #define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK                      0xFUL                                     /**< Bit mask for EMU_RAMPOWERDOWN */
4250 #define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for EMU_RAM2CTRL */
4251 #define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE                      0x00000000UL                              /**< Mode NONE for EMU_RAM2CTRL */
4252 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3                      0x00000008UL                              /**< Mode BLK3 for EMU_RAM2CTRL */
4253 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3                   0x0000000CUL                              /**< Mode BLK2TO3 for EMU_RAM2CTRL */
4254 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3                   0x0000000EUL                              /**< Mode BLK1TO3 for EMU_RAM2CTRL */
4255 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3                   0x0000000FUL                              /**< Mode BLK0TO3 for EMU_RAM2CTRL */
4256 #define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT                    (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */
4257 #define EMU_RAM2CTRL_RAMPOWERDOWN_NONE                       (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0)    /**< Shifted mode NONE for EMU_RAM2CTRL */
4258 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3                       (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0)    /**< Shifted mode BLK3 for EMU_RAM2CTRL */
4259 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3                    (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */
4260 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3                    (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */
4261 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3                    (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */
4262 
4263 /* Bit fields for EMU BUCTRL */
4264 #define _EMU_BUCTRL_RESETVALUE                               0x00000000UL                              /**< Default value for EMU_BUCTRL */
4265 #define _EMU_BUCTRL_MASK                                     0x80333307UL                              /**< Mask for EMU_BUCTRL */
4266 #define EMU_BUCTRL_EN                                        (0x1UL << 0)                              /**< Enable Backup Mode */
4267 #define _EMU_BUCTRL_EN_SHIFT                                 0                                         /**< Shift value for EMU_EN */
4268 #define _EMU_BUCTRL_EN_MASK                                  0x1UL                                     /**< Bit mask for EMU_EN */
4269 #define _EMU_BUCTRL_EN_DEFAULT                               0x00000000UL                              /**< Mode DEFAULT for EMU_BUCTRL */
4270 #define EMU_BUCTRL_EN_DEFAULT                                (_EMU_BUCTRL_EN_DEFAULT << 0)             /**< Shifted mode DEFAULT for EMU_BUCTRL */
4271 #define EMU_BUCTRL_STATEN                                    (0x1UL << 1)                              /**< Enable Backup Mode Status Export */
4272 #define _EMU_BUCTRL_STATEN_SHIFT                             1                                         /**< Shift value for EMU_STATEN */
4273 #define _EMU_BUCTRL_STATEN_MASK                              0x2UL                                     /**< Bit mask for EMU_STATEN */
4274 #define _EMU_BUCTRL_STATEN_DEFAULT                           0x00000000UL                              /**< Mode DEFAULT for EMU_BUCTRL */
4275 #define EMU_BUCTRL_STATEN_DEFAULT                            (_EMU_BUCTRL_STATEN_DEFAULT << 1)         /**< Shifted mode DEFAULT for EMU_BUCTRL */
4276 #define EMU_BUCTRL_BUVINPROBEEN                              (0x1UL << 2)                              /**< Enable BU_VIN Probing */
4277 #define _EMU_BUCTRL_BUVINPROBEEN_SHIFT                       2                                         /**< Shift value for EMU_BUVINPROBEEN */
4278 #define _EMU_BUCTRL_BUVINPROBEEN_MASK                        0x4UL                                     /**< Bit mask for EMU_BUVINPROBEEN */
4279 #define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT                     0x00000000UL                              /**< Mode DEFAULT for EMU_BUCTRL */
4280 #define EMU_BUCTRL_BUVINPROBEEN_DEFAULT                      (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2)   /**< Shifted mode DEFAULT for EMU_BUCTRL */
4281 #define _EMU_BUCTRL_VOUTRES_SHIFT                            8                                         /**< Shift value for EMU_VOUTRES */
4282 #define _EMU_BUCTRL_VOUTRES_MASK                             0x300UL                                   /**< Bit mask for EMU_VOUTRES */
4283 #define _EMU_BUCTRL_VOUTRES_DEFAULT                          0x00000000UL                              /**< Mode DEFAULT for EMU_BUCTRL */
4284 #define _EMU_BUCTRL_VOUTRES_DIS                              0x00000000UL                              /**< Mode DIS for EMU_BUCTRL */
4285 #define _EMU_BUCTRL_VOUTRES_WEAK                             0x00000001UL                              /**< Mode WEAK for EMU_BUCTRL */
4286 #define _EMU_BUCTRL_VOUTRES_MED                              0x00000002UL                              /**< Mode MED for EMU_BUCTRL */
4287 #define _EMU_BUCTRL_VOUTRES_STRONG                           0x00000003UL                              /**< Mode STRONG for EMU_BUCTRL */
4288 #define EMU_BUCTRL_VOUTRES_DEFAULT                           (_EMU_BUCTRL_VOUTRES_DEFAULT << 8)        /**< Shifted mode DEFAULT for EMU_BUCTRL */
4289 #define EMU_BUCTRL_VOUTRES_DIS                               (_EMU_BUCTRL_VOUTRES_DIS << 8)            /**< Shifted mode DIS for EMU_BUCTRL */
4290 #define EMU_BUCTRL_VOUTRES_WEAK                              (_EMU_BUCTRL_VOUTRES_WEAK << 8)           /**< Shifted mode WEAK for EMU_BUCTRL */
4291 #define EMU_BUCTRL_VOUTRES_MED                               (_EMU_BUCTRL_VOUTRES_MED << 8)            /**< Shifted mode MED for EMU_BUCTRL */
4292 #define EMU_BUCTRL_VOUTRES_STRONG                            (_EMU_BUCTRL_VOUTRES_STRONG << 8)         /**< Shifted mode STRONG for EMU_BUCTRL */
4293 #define _EMU_BUCTRL_PWRRES_SHIFT                             12                                        /**< Shift value for EMU_PWRRES */
4294 #define _EMU_BUCTRL_PWRRES_MASK                              0x3000UL                                  /**< Bit mask for EMU_PWRRES */
4295 #define _EMU_BUCTRL_PWRRES_DEFAULT                           0x00000000UL                              /**< Mode DEFAULT for EMU_BUCTRL */
4296 #define _EMU_BUCTRL_PWRRES_RES0                              0x00000000UL                              /**< Mode RES0 for EMU_BUCTRL */
4297 #define _EMU_BUCTRL_PWRRES_RES1                              0x00000001UL                              /**< Mode RES1 for EMU_BUCTRL */
4298 #define _EMU_BUCTRL_PWRRES_RES2                              0x00000002UL                              /**< Mode RES2 for EMU_BUCTRL */
4299 #define _EMU_BUCTRL_PWRRES_RES3                              0x00000003UL                              /**< Mode RES3 for EMU_BUCTRL */
4300 #define EMU_BUCTRL_PWRRES_DEFAULT                            (_EMU_BUCTRL_PWRRES_DEFAULT << 12)        /**< Shifted mode DEFAULT for EMU_BUCTRL */
4301 #define EMU_BUCTRL_PWRRES_RES0                               (_EMU_BUCTRL_PWRRES_RES0 << 12)           /**< Shifted mode RES0 for EMU_BUCTRL */
4302 #define EMU_BUCTRL_PWRRES_RES1                               (_EMU_BUCTRL_PWRRES_RES1 << 12)           /**< Shifted mode RES1 for EMU_BUCTRL */
4303 #define EMU_BUCTRL_PWRRES_RES2                               (_EMU_BUCTRL_PWRRES_RES2 << 12)           /**< Shifted mode RES2 for EMU_BUCTRL */
4304 #define EMU_BUCTRL_PWRRES_RES3                               (_EMU_BUCTRL_PWRRES_RES3 << 12)           /**< Shifted mode RES3 for EMU_BUCTRL */
4305 #define _EMU_BUCTRL_BUACTPWRCON_SHIFT                        16                                        /**< Shift value for EMU_BUACTPWRCON */
4306 #define _EMU_BUCTRL_BUACTPWRCON_MASK                         0x30000UL                                 /**< Bit mask for EMU_BUACTPWRCON */
4307 #define _EMU_BUCTRL_BUACTPWRCON_DEFAULT                      0x00000000UL                              /**< Mode DEFAULT for EMU_BUCTRL */
4308 #define _EMU_BUCTRL_BUACTPWRCON_NONE                         0x00000000UL                              /**< Mode NONE for EMU_BUCTRL */
4309 #define _EMU_BUCTRL_BUACTPWRCON_MAINBU                       0x00000001UL                              /**< Mode MAINBU for EMU_BUCTRL */
4310 #define _EMU_BUCTRL_BUACTPWRCON_BUMAIN                       0x00000002UL                              /**< Mode BUMAIN for EMU_BUCTRL */
4311 #define _EMU_BUCTRL_BUACTPWRCON_NODIODE                      0x00000003UL                              /**< Mode NODIODE for EMU_BUCTRL */
4312 #define EMU_BUCTRL_BUACTPWRCON_DEFAULT                       (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16)   /**< Shifted mode DEFAULT for EMU_BUCTRL */
4313 #define EMU_BUCTRL_BUACTPWRCON_NONE                          (_EMU_BUCTRL_BUACTPWRCON_NONE << 16)      /**< Shifted mode NONE for EMU_BUCTRL */
4314 #define EMU_BUCTRL_BUACTPWRCON_MAINBU                        (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16)    /**< Shifted mode MAINBU for EMU_BUCTRL */
4315 #define EMU_BUCTRL_BUACTPWRCON_BUMAIN                        (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16)    /**< Shifted mode BUMAIN for EMU_BUCTRL */
4316 #define EMU_BUCTRL_BUACTPWRCON_NODIODE                       (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16)   /**< Shifted mode NODIODE for EMU_BUCTRL */
4317 #define _EMU_BUCTRL_BUINACTPWRCON_SHIFT                      20                                        /**< Shift value for EMU_BUINACTPWRCON */
4318 #define _EMU_BUCTRL_BUINACTPWRCON_MASK                       0x300000UL                                /**< Bit mask for EMU_BUINACTPWRCON */
4319 #define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT                    0x00000000UL                              /**< Mode DEFAULT for EMU_BUCTRL */
4320 #define _EMU_BUCTRL_BUINACTPWRCON_NONE                       0x00000000UL                              /**< Mode NONE for EMU_BUCTRL */
4321 #define _EMU_BUCTRL_BUINACTPWRCON_MAINBU                     0x00000001UL                              /**< Mode MAINBU for EMU_BUCTRL */
4322 #define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN                     0x00000002UL                              /**< Mode BUMAIN for EMU_BUCTRL */
4323 #define _EMU_BUCTRL_BUINACTPWRCON_NODIODE                    0x00000003UL                              /**< Mode NODIODE for EMU_BUCTRL */
4324 #define EMU_BUCTRL_BUINACTPWRCON_DEFAULT                     (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */
4325 #define EMU_BUCTRL_BUINACTPWRCON_NONE                        (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20)    /**< Shifted mode NONE for EMU_BUCTRL */
4326 #define EMU_BUCTRL_BUINACTPWRCON_MAINBU                      (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20)  /**< Shifted mode MAINBU for EMU_BUCTRL */
4327 #define EMU_BUCTRL_BUINACTPWRCON_BUMAIN                      (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20)  /**< Shifted mode BUMAIN for EMU_BUCTRL */
4328 #define EMU_BUCTRL_BUINACTPWRCON_NODIODE                     (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */
4329 #define EMU_BUCTRL_DISMAXCOMP                                (0x1UL << 31)                             /**< Disable MAIN-BU Comparator */
4330 #define _EMU_BUCTRL_DISMAXCOMP_SHIFT                         31                                        /**< Shift value for EMU_DISMAXCOMP */
4331 #define _EMU_BUCTRL_DISMAXCOMP_MASK                          0x80000000UL                              /**< Bit mask for EMU_DISMAXCOMP */
4332 #define _EMU_BUCTRL_DISMAXCOMP_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for EMU_BUCTRL */
4333 #define EMU_BUCTRL_DISMAXCOMP_DEFAULT                        (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31)    /**< Shifted mode DEFAULT for EMU_BUCTRL */
4334 
4335 /* Bit fields for EMU R5VCTRL */
4336 #define _EMU_R5VCTRL_RESETVALUE                              0x00000000UL                          /**< Default value for EMU_R5VCTRL */
4337 #define _EMU_R5VCTRL_MASK                                    0x00000307UL                          /**< Mask for EMU_R5VCTRL */
4338 #define EMU_R5VCTRL_BYPASS                                   (0x1UL << 0)                          /**< 5V Regulator Bypass */
4339 #define _EMU_R5VCTRL_BYPASS_SHIFT                            0                                     /**< Shift value for EMU_BYPASS */
4340 #define _EMU_R5VCTRL_BYPASS_MASK                             0x1UL                                 /**< Bit mask for EMU_BYPASS */
4341 #define _EMU_R5VCTRL_BYPASS_DEFAULT                          0x00000000UL                          /**< Mode DEFAULT for EMU_R5VCTRL */
4342 #define EMU_R5VCTRL_BYPASS_DEFAULT                           (_EMU_R5VCTRL_BYPASS_DEFAULT << 0)    /**< Shifted mode DEFAULT for EMU_R5VCTRL */
4343 #define EMU_R5VCTRL_EM4WUEN                                  (0x1UL << 1)                          /**< Enable EM4 Wakeup Due to VBUS Detection */
4344 #define _EMU_R5VCTRL_EM4WUEN_SHIFT                           1                                     /**< Shift value for EMU_EM4WUEN */
4345 #define _EMU_R5VCTRL_EM4WUEN_MASK                            0x2UL                                 /**< Bit mask for EMU_EM4WUEN */
4346 #define _EMU_R5VCTRL_EM4WUEN_DEFAULT                         0x00000000UL                          /**< Mode DEFAULT for EMU_R5VCTRL */
4347 #define EMU_R5VCTRL_EM4WUEN_DEFAULT                          (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1)   /**< Shifted mode DEFAULT for EMU_R5VCTRL */
4348 #define EMU_R5VCTRL_IMONEN                                   (0x1UL << 2)                          /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */
4349 #define _EMU_R5VCTRL_IMONEN_SHIFT                            2                                     /**< Shift value for EMU_IMONEN */
4350 #define _EMU_R5VCTRL_IMONEN_MASK                             0x4UL                                 /**< Bit mask for EMU_IMONEN */
4351 #define _EMU_R5VCTRL_IMONEN_DEFAULT                          0x00000000UL                          /**< Mode DEFAULT for EMU_R5VCTRL */
4352 #define EMU_R5VCTRL_IMONEN_DEFAULT                           (_EMU_R5VCTRL_IMONEN_DEFAULT << 2)    /**< Shifted mode DEFAULT for EMU_R5VCTRL */
4353 #define _EMU_R5VCTRL_INPUTMODE_SHIFT                         8                                     /**< Shift value for EMU_INPUTMODE */
4354 #define _EMU_R5VCTRL_INPUTMODE_MASK                          0x300UL                               /**< Bit mask for EMU_INPUTMODE */
4355 #define _EMU_R5VCTRL_INPUTMODE_DEFAULT                       0x00000000UL                          /**< Mode DEFAULT for EMU_R5VCTRL */
4356 #define _EMU_R5VCTRL_INPUTMODE_AUTO                          0x00000000UL                          /**< Mode AUTO for EMU_R5VCTRL */
4357 #define _EMU_R5VCTRL_INPUTMODE_VBUS                          0x00000001UL                          /**< Mode VBUS for EMU_R5VCTRL */
4358 #define _EMU_R5VCTRL_INPUTMODE_VREGI                         0x00000002UL                          /**< Mode VREGI for EMU_R5VCTRL */
4359 #define EMU_R5VCTRL_INPUTMODE_DEFAULT                        (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */
4360 #define EMU_R5VCTRL_INPUTMODE_AUTO                           (_EMU_R5VCTRL_INPUTMODE_AUTO << 8)    /**< Shifted mode AUTO for EMU_R5VCTRL */
4361 #define EMU_R5VCTRL_INPUTMODE_VBUS                           (_EMU_R5VCTRL_INPUTMODE_VBUS << 8)    /**< Shifted mode VBUS for EMU_R5VCTRL */
4362 #define EMU_R5VCTRL_INPUTMODE_VREGI                          (_EMU_R5VCTRL_INPUTMODE_VREGI << 8)   /**< Shifted mode VREGI for EMU_R5VCTRL */
4363 
4364 /* Bit fields for EMU R5VADCCTRL */
4365 #define _EMU_R5VADCCTRL_RESETVALUE                           0x00000000UL                               /**< Default value for EMU_R5VADCCTRL */
4366 #define _EMU_R5VADCCTRL_MASK                                 0x0000F001UL                               /**< Mask for EMU_R5VADCCTRL */
4367 #define EMU_R5VADCCTRL_ENAMUX                                (0x1UL << 0)                               /**< Enable the 5V Subsystem ADC MUX */
4368 #define _EMU_R5VADCCTRL_ENAMUX_SHIFT                         0                                          /**< Shift value for EMU_ENAMUX */
4369 #define _EMU_R5VADCCTRL_ENAMUX_MASK                          0x1UL                                      /**< Bit mask for EMU_ENAMUX */
4370 #define _EMU_R5VADCCTRL_ENAMUX_DEFAULT                       0x00000000UL                               /**< Mode DEFAULT for EMU_R5VADCCTRL */
4371 #define EMU_R5VADCCTRL_ENAMUX_DEFAULT                        (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0)      /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */
4372 #define _EMU_R5VADCCTRL_AMUXSEL_SHIFT                        12                                         /**< Shift value for EMU_AMUXSEL */
4373 #define _EMU_R5VADCCTRL_AMUXSEL_MASK                         0xF000UL                                   /**< Bit mask for EMU_AMUXSEL */
4374 #define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT                      0x00000000UL                               /**< Mode DEFAULT for EMU_R5VADCCTRL */
4375 #define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10                    0x00000000UL                               /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */
4376 #define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10                   0x00000001UL                               /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */
4377 #define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6                    0x00000002UL                               /**< Mode VREGODIV6 for EMU_R5VADCCTRL */
4378 #define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON                    0x00000003UL                               /**< Mode VREGIIMON for EMU_R5VADCCTRL */
4379 #define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON                     0x00000004UL                               /**< Mode VBUSIMON for EMU_R5VADCCTRL */
4380 #define EMU_R5VADCCTRL_AMUXSEL_DEFAULT                       (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12)    /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */
4381 #define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10                     (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12)  /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */
4382 #define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10                    (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */
4383 #define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6                     (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12)  /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */
4384 #define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON                     (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12)  /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */
4385 #define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON                      (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12)   /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */
4386 
4387 /* Bit fields for EMU R5VOUTLEVEL */
4388 #define _EMU_R5VOUTLEVEL_RESETVALUE                          0x00000001UL                             /**< Default value for EMU_R5VOUTLEVEL */
4389 #define _EMU_R5VOUTLEVEL_MASK                                0x0000000FUL                             /**< Mask for EMU_R5VOUTLEVEL */
4390 #define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT                      0                                        /**< Shift value for EMU_OUTLEVEL */
4391 #define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK                       0xFUL                                    /**< Bit mask for EMU_OUTLEVEL */
4392 #define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT                    0x00000001UL                             /**< Mode DEFAULT for EMU_R5VOUTLEVEL */
4393 #define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT                     (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */
4394 
4395 /* Bit fields for EMU R5VDETCTRL */
4396 #define _EMU_R5VDETCTRL_RESETVALUE                           0x00000000UL                               /**< Default value for EMU_R5VDETCTRL */
4397 #define _EMU_R5VDETCTRL_MASK                                 0x00000007UL                               /**< Mask for EMU_R5VDETCTRL */
4398 #define EMU_R5VDETCTRL_VREGIDETDIS                           (0x1UL << 0)                               /**< VREGI Detector Disable */
4399 #define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT                    0                                          /**< Shift value for EMU_VREGIDETDIS */
4400 #define _EMU_R5VDETCTRL_VREGIDETDIS_MASK                     0x1UL                                      /**< Bit mask for EMU_VREGIDETDIS */
4401 #define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT                  0x00000000UL                               /**< Mode DEFAULT for EMU_R5VDETCTRL */
4402 #define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT                   (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */
4403 #define EMU_R5VDETCTRL_VBUSDETDIS                            (0x1UL << 1)                               /**< VBUS Detector Disable */
4404 #define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT                     1                                          /**< Shift value for EMU_VBUSDETDIS */
4405 #define _EMU_R5VDETCTRL_VBUSDETDIS_MASK                      0x2UL                                      /**< Bit mask for EMU_VBUSDETDIS */
4406 #define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for EMU_R5VDETCTRL */
4407 #define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT                    (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1)  /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */
4408 #define EMU_R5VDETCTRL_VREGODETDIS                           (0x1UL << 2)                               /**< VREGO Detector Disable */
4409 #define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT                    2                                          /**< Shift value for EMU_VREGODETDIS */
4410 #define _EMU_R5VDETCTRL_VREGODETDIS_MASK                     0x4UL                                      /**< Bit mask for EMU_VREGODETDIS */
4411 #define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT                  0x00000000UL                               /**< Mode DEFAULT for EMU_R5VDETCTRL */
4412 #define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT                   (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */
4413 
4414 /* Bit fields for EMU DCDCLPEM01CFG */
4415 #define _EMU_DCDCLPEM01CFG_RESETVALUE                        0x00000300UL                                       /**< Default value for EMU_DCDCLPEM01CFG */
4416 #define _EMU_DCDCLPEM01CFG_MASK                              0x0000F300UL                                       /**< Mask for EMU_DCDCLPEM01CFG */
4417 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT               8                                                  /**< Shift value for EMU_LPCMPBIASEM01 */
4418 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK                0x300UL                                            /**< Bit mask for EMU_LPCMPBIASEM01 */
4419 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0               0x00000000UL                                       /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */
4420 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1               0x00000001UL                                       /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */
4421 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2               0x00000002UL                                       /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */
4422 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT             0x00000003UL                                       /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */
4423 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3               0x00000003UL                                       /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */
4424 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0                (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8)      /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */
4425 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1                (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8)      /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */
4426 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2                (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8)      /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */
4427 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT              (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8)    /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */
4428 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3                (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8)      /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */
4429 #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT             12                                                 /**< Shift value for EMU_LPCMPHYSSELEM01 */
4430 #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK              0xF000UL                                           /**< Bit mask for EMU_LPCMPHYSSELEM01 */
4431 #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT           0x00000000UL                                       /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */
4432 #define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT            (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */
4433 
4434 /* Bit fields for EMU R5VSTATUS */
4435 #define _EMU_R5VSTATUS_RESETVALUE                            0x00000020UL                                /**< Default value for EMU_R5VSTATUS */
4436 #define _EMU_R5VSTATUS_MASK                                  0x0000003DUL                                /**< Mask for EMU_R5VSTATUS */
4437 #define EMU_R5VSTATUS_VREGIDET                               (0x1UL << 0)                                /**< VREGI Detected */
4438 #define _EMU_R5VSTATUS_VREGIDET_SHIFT                        0                                           /**< Shift value for EMU_VREGIDET */
4439 #define _EMU_R5VSTATUS_VREGIDET_MASK                         0x1UL                                       /**< Bit mask for EMU_VREGIDET */
4440 #define _EMU_R5VSTATUS_VREGIDET_DEFAULT                      0x00000000UL                                /**< Mode DEFAULT for EMU_R5VSTATUS */
4441 #define EMU_R5VSTATUS_VREGIDET_DEFAULT                       (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0)      /**< Shifted mode DEFAULT for EMU_R5VSTATUS */
4442 #define EMU_R5VSTATUS_VREGODET                               (0x1UL << 2)                                /**< VREGO Detected */
4443 #define _EMU_R5VSTATUS_VREGODET_SHIFT                        2                                           /**< Shift value for EMU_VREGODET */
4444 #define _EMU_R5VSTATUS_VREGODET_MASK                         0x4UL                                       /**< Bit mask for EMU_VREGODET */
4445 #define _EMU_R5VSTATUS_VREGODET_DEFAULT                      0x00000000UL                                /**< Mode DEFAULT for EMU_R5VSTATUS */
4446 #define EMU_R5VSTATUS_VREGODET_DEFAULT                       (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2)      /**< Shifted mode DEFAULT for EMU_R5VSTATUS */
4447 #define EMU_R5VSTATUS_VBUSGTVREGI                            (0x1UL << 3)                                /**< Output of the Supply Comparator Between VBUS and VREGI */
4448 #define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT                     3                                           /**< Shift value for EMU_VBUSGTVREGI */
4449 #define _EMU_R5VSTATUS_VBUSGTVREGI_MASK                      0x8UL                                       /**< Bit mask for EMU_VBUSGTVREGI */
4450 #define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT                   0x00000000UL                                /**< Mode DEFAULT for EMU_R5VSTATUS */
4451 #define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT                    (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3)   /**< Shifted mode DEFAULT for EMU_R5VSTATUS */
4452 #define EMU_R5VSTATUS_LDODROPOUTDET                          (0x1UL << 4)                                /**< Regulator Dropout Detection */
4453 #define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT                   4                                           /**< Shift value for EMU_LDODROPOUTDET */
4454 #define _EMU_R5VSTATUS_LDODROPOUTDET_MASK                    0x10UL                                      /**< Bit mask for EMU_LDODROPOUTDET */
4455 #define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT                 0x00000000UL                                /**< Mode DEFAULT for EMU_R5VSTATUS */
4456 #define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT                  (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */
4457 #define EMU_R5VSTATUS_COLDSTART                              (0x1UL << 5)                                /**< Indicates If the Regulator is Going Through a Cold Start */
4458 #define _EMU_R5VSTATUS_COLDSTART_SHIFT                       5                                           /**< Shift value for EMU_COLDSTART */
4459 #define _EMU_R5VSTATUS_COLDSTART_MASK                        0x20UL                                      /**< Bit mask for EMU_COLDSTART */
4460 #define _EMU_R5VSTATUS_COLDSTART_DEFAULT                     0x00000001UL                                /**< Mode DEFAULT for EMU_R5VSTATUS */
4461 #define EMU_R5VSTATUS_COLDSTART_DEFAULT                      (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5)     /**< Shifted mode DEFAULT for EMU_R5VSTATUS */
4462 
4463 /* Bit fields for EMU R5VSYNC */
4464 #define _EMU_R5VSYNC_RESETVALUE                              0x00000000UL                             /**< Default value for EMU_R5VSYNC */
4465 #define _EMU_R5VSYNC_MASK                                    0x00000001UL                             /**< Mask for EMU_R5VSYNC */
4466 #define EMU_R5VSYNC_OUTLEVELBUSY                             (0x1UL << 0)                             /**< 5V Regulator Voltage Register Transfer Busy */
4467 #define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT                      0                                        /**< Shift value for EMU_OUTLEVELBUSY */
4468 #define _EMU_R5VSYNC_OUTLEVELBUSY_MASK                       0x1UL                                    /**< Bit mask for EMU_OUTLEVELBUSY */
4469 #define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for EMU_R5VSYNC */
4470 #define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT                     (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */
4471 
4472 /* Bit fields for EMU EM23PERNORETAINCMD */
4473 #define _EMU_EM23PERNORETAINCMD_RESETVALUE                   0x00000000UL                                           /**< Default value for EMU_EM23PERNORETAINCMD */
4474 #define _EMU_EM23PERNORETAINCMD_MASK                         0x00B7FFFFUL                                           /**< Mask for EMU_EM23PERNORETAINCMD */
4475 #define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK                   (0x1UL << 0)                                           /**< Clears Status Bit of ACMP0 and Unlocks Access to It */
4476 #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT            0                                                      /**< Shift value for EMU_ACMP0UNLOCK */
4477 #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK             0x1UL                                                  /**< Bit mask for EMU_ACMP0UNLOCK */
4478 #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT          0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4479 #define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT           (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4480 #define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK                   (0x1UL << 1)                                           /**< Clears Status Bit of ACMP1 and Unlocks Access to It */
4481 #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT            1                                                      /**< Shift value for EMU_ACMP1UNLOCK */
4482 #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK             0x2UL                                                  /**< Bit mask for EMU_ACMP1UNLOCK */
4483 #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT          0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4484 #define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT           (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4485 #define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK                   (0x1UL << 2)                                           /**< Clears Status Bit of PCNT0 and Unlocks Access to It */
4486 #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT            2                                                      /**< Shift value for EMU_PCNT0UNLOCK */
4487 #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK             0x4UL                                                  /**< Bit mask for EMU_PCNT0UNLOCK */
4488 #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT          0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4489 #define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT           (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4490 #define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK                   (0x1UL << 3)                                           /**< Clears Status Bit of PCNT1 and Unlocks Access to It */
4491 #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT            3                                                      /**< Shift value for EMU_PCNT1UNLOCK */
4492 #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK             0x8UL                                                  /**< Bit mask for EMU_PCNT1UNLOCK */
4493 #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT          0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4494 #define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT           (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4495 #define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK                   (0x1UL << 4)                                           /**< Clears Status Bit of PCNT2 and Unlocks Access to It */
4496 #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT            4                                                      /**< Shift value for EMU_PCNT2UNLOCK */
4497 #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK             0x10UL                                                 /**< Bit mask for EMU_PCNT2UNLOCK */
4498 #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT          0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4499 #define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT           (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4500 #define EMU_EM23PERNORETAINCMD_I2C0UNLOCK                    (0x1UL << 5)                                           /**< Clears Status Bit of I2C0 and Unlocks Access to It */
4501 #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT             5                                                      /**< Shift value for EMU_I2C0UNLOCK */
4502 #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK              0x20UL                                                 /**< Bit mask for EMU_I2C0UNLOCK */
4503 #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT           0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4504 #define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT            (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4505 #define EMU_EM23PERNORETAINCMD_I2C1UNLOCK                    (0x1UL << 6)                                           /**< Clears Status Bit of I2C1 and Unlocks Access to It */
4506 #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT             6                                                      /**< Shift value for EMU_I2C1UNLOCK */
4507 #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK              0x40UL                                                 /**< Bit mask for EMU_I2C1UNLOCK */
4508 #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT           0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4509 #define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT            (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4510 #define EMU_EM23PERNORETAINCMD_DAC0UNLOCK                    (0x1UL << 7)                                           /**< Clears Status Bit of DAC0 and Unlocks Access to It */
4511 #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT             7                                                      /**< Shift value for EMU_DAC0UNLOCK */
4512 #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK              0x80UL                                                 /**< Bit mask for EMU_DAC0UNLOCK */
4513 #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT           0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4514 #define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT            (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4515 #define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK                   (0x1UL << 8)                                           /**< Clears Status Bit of IDAC0 and Unlocks Access to It */
4516 #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT            8                                                      /**< Shift value for EMU_IDAC0UNLOCK */
4517 #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK             0x100UL                                                /**< Bit mask for EMU_IDAC0UNLOCK */
4518 #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT          0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4519 #define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT           (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4520 #define EMU_EM23PERNORETAINCMD_ADC0UNLOCK                    (0x1UL << 9)                                           /**< Clears Status Bit of ADC0 and Unlocks Access to It */
4521 #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT             9                                                      /**< Shift value for EMU_ADC0UNLOCK */
4522 #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK              0x200UL                                                /**< Bit mask for EMU_ADC0UNLOCK */
4523 #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT           0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4524 #define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT            (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4525 #define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK                (0x1UL << 10)                                          /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */
4526 #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT         10                                                     /**< Shift value for EMU_LETIMER0UNLOCK */
4527 #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK          0x400UL                                                /**< Bit mask for EMU_LETIMER0UNLOCK */
4528 #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT       0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4529 #define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT        (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4530 #define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK                   (0x1UL << 11)                                          /**< Clears Status Bit of WDOG0 and Unlocks Access to It */
4531 #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT            11                                                     /**< Shift value for EMU_WDOG0UNLOCK */
4532 #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK             0x800UL                                                /**< Bit mask for EMU_WDOG0UNLOCK */
4533 #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT          0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4534 #define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT           (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11)    /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4535 #define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK                   (0x1UL << 12)                                          /**< Clears Status Bit of WDOG1 and Unlocks Access to It */
4536 #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT            12                                                     /**< Shift value for EMU_WDOG1UNLOCK */
4537 #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK             0x1000UL                                               /**< Bit mask for EMU_WDOG1UNLOCK */
4538 #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT          0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4539 #define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT           (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12)    /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4540 #define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK                (0x1UL << 13)                                          /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */
4541 #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT         13                                                     /**< Shift value for EMU_LESENSE0UNLOCK */
4542 #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK          0x2000UL                                               /**< Bit mask for EMU_LESENSE0UNLOCK */
4543 #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT       0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4544 #define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT        (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4545 #define EMU_EM23PERNORETAINCMD_CSENUNLOCK                    (0x1UL << 14)                                          /**< Clears Status Bit of CSEN and Unlocks Access to It */
4546 #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT             14                                                     /**< Shift value for EMU_CSENUNLOCK */
4547 #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK              0x4000UL                                               /**< Bit mask for EMU_CSENUNLOCK */
4548 #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT           0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4549 #define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT            (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4550 #define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK                 (0x1UL << 15)                                          /**< Clears Status Bit of LEUART0 and Unlocks Access to It */
4551 #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT          15                                                     /**< Shift value for EMU_LEUART0UNLOCK */
4552 #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK           0x8000UL                                               /**< Bit mask for EMU_LEUART0UNLOCK */
4553 #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT        0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4554 #define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT         (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15)  /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4555 #define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK                 (0x1UL << 16)                                          /**< Clears Status Bit of LEUART1 and Unlocks Access to It */
4556 #define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT          16                                                     /**< Shift value for EMU_LEUART1UNLOCK */
4557 #define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK           0x10000UL                                              /**< Bit mask for EMU_LEUART1UNLOCK */
4558 #define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT        0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4559 #define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT         (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16)  /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4560 #define EMU_EM23PERNORETAINCMD_LCDUNLOCK                     (0x1UL << 17)                                          /**< Clears Status Bit of LCD and Unlocks Access to It */
4561 #define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT              17                                                     /**< Shift value for EMU_LCDUNLOCK */
4562 #define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK               0x20000UL                                              /**< Bit mask for EMU_LCDUNLOCK */
4563 #define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT            0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4564 #define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT             (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4565 #define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK                (0x1UL << 18)                                          /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */
4566 #define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT         18                                                     /**< Shift value for EMU_LETIMER1UNLOCK */
4567 #define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK          0x40000UL                                              /**< Bit mask for EMU_LETIMER1UNLOCK */
4568 #define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT       0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4569 #define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT        (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4570 #define EMU_EM23PERNORETAINCMD_ADC1UNLOCK                    (0x1UL << 20)                                          /**< Clears Status Bit of ADC1 and Unlocks Access to It */
4571 #define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT             20                                                     /**< Shift value for EMU_ADC1UNLOCK */
4572 #define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK              0x100000UL                                             /**< Bit mask for EMU_ADC1UNLOCK */
4573 #define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT           0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4574 #define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT            (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4575 #define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK                   (0x1UL << 21)                                          /**< Clears Status Bit of ACMP2 and Unlocks Access to It */
4576 #define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT            21                                                     /**< Shift value for EMU_ACMP2UNLOCK */
4577 #define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK             0x200000UL                                             /**< Bit mask for EMU_ACMP2UNLOCK */
4578 #define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT          0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4579 #define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT           (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21)    /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4580 #define EMU_EM23PERNORETAINCMD_RTCUNLOCK                     (0x1UL << 23)                                          /**< Clears Status Bit of RTC and Unlocks Access to It */
4581 #define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT              23                                                     /**< Shift value for EMU_RTCUNLOCK */
4582 #define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK               0x800000UL                                             /**< Bit mask for EMU_RTCUNLOCK */
4583 #define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT            0x00000000UL                                           /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
4584 #define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT             (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
4585 
4586 /* Bit fields for EMU EM23PERNORETAINSTATUS */
4587 #define _EMU_EM23PERNORETAINSTATUS_RESETVALUE                0x00000000UL                                              /**< Default value for EMU_EM23PERNORETAINSTATUS */
4588 #define _EMU_EM23PERNORETAINSTATUS_MASK                      0x00B7FFFFUL                                              /**< Mask for EMU_EM23PERNORETAINSTATUS */
4589 #define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED                (0x1UL << 0)                                              /**< Indicates If ACMP0 Powered Down During EM23 */
4590 #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT         0                                                         /**< Shift value for EMU_ACMP0LOCKED */
4591 #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK          0x1UL                                                     /**< Bit mask for EMU_ACMP0LOCKED */
4592 #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT       0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4593 #define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT        (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4594 #define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED                (0x1UL << 1)                                              /**< Indicates If ACMP1 Powered Down During EM23 */
4595 #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT         1                                                         /**< Shift value for EMU_ACMP1LOCKED */
4596 #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK          0x2UL                                                     /**< Bit mask for EMU_ACMP1LOCKED */
4597 #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT       0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4598 #define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT        (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4599 #define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED                (0x1UL << 2)                                              /**< Indicates If PCNT0 Powered Down During EM23 */
4600 #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT         2                                                         /**< Shift value for EMU_PCNT0LOCKED */
4601 #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK          0x4UL                                                     /**< Bit mask for EMU_PCNT0LOCKED */
4602 #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT       0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4603 #define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT        (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4604 #define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED                (0x1UL << 3)                                              /**< Indicates If PCNT1 Powered Down During EM23 */
4605 #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT         3                                                         /**< Shift value for EMU_PCNT1LOCKED */
4606 #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK          0x8UL                                                     /**< Bit mask for EMU_PCNT1LOCKED */
4607 #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT       0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4608 #define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT        (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4609 #define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED                (0x1UL << 4)                                              /**< Indicates If PCNT2 Powered Down During EM23 */
4610 #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT         4                                                         /**< Shift value for EMU_PCNT2LOCKED */
4611 #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK          0x10UL                                                    /**< Bit mask for EMU_PCNT2LOCKED */
4612 #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT       0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4613 #define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT        (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4614 #define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED                 (0x1UL << 5)                                              /**< Indicates If I2C0 Powered Down During EM23 */
4615 #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT          5                                                         /**< Shift value for EMU_I2C0LOCKED */
4616 #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK           0x20UL                                                    /**< Bit mask for EMU_I2C0LOCKED */
4617 #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT        0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4618 #define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT         (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4619 #define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED                 (0x1UL << 6)                                              /**< Indicates If I2C1 Powered Down During EM23 */
4620 #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT          6                                                         /**< Shift value for EMU_I2C1LOCKED */
4621 #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK           0x40UL                                                    /**< Bit mask for EMU_I2C1LOCKED */
4622 #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT        0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4623 #define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT         (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4624 #define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED                 (0x1UL << 7)                                              /**< Indicates If DAC0 Powered Down During EM23 */
4625 #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT          7                                                         /**< Shift value for EMU_DAC0LOCKED */
4626 #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK           0x80UL                                                    /**< Bit mask for EMU_DAC0LOCKED */
4627 #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT        0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4628 #define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT         (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4629 #define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED                (0x1UL << 8)                                              /**< Indicates If IDAC0 Powered Down During EM23 */
4630 #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT         8                                                         /**< Shift value for EMU_IDAC0LOCKED */
4631 #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK          0x100UL                                                   /**< Bit mask for EMU_IDAC0LOCKED */
4632 #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT       0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4633 #define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT        (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4634 #define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED                 (0x1UL << 9)                                              /**< Indicates If ADC0 Powered Down During EM23 */
4635 #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT          9                                                         /**< Shift value for EMU_ADC0LOCKED */
4636 #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK           0x200UL                                                   /**< Bit mask for EMU_ADC0LOCKED */
4637 #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT        0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4638 #define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT         (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4639 #define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED             (0x1UL << 10)                                             /**< Indicates If LETIMER0 Powered Down During EM23 */
4640 #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT      10                                                        /**< Shift value for EMU_LETIMER0LOCKED */
4641 #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK       0x400UL                                                   /**< Bit mask for EMU_LETIMER0LOCKED */
4642 #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT    0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4643 #define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT     (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4644 #define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED                (0x1UL << 11)                                             /**< Indicates If WDOG0 Powered Down During EM23 */
4645 #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT         11                                                        /**< Shift value for EMU_WDOG0LOCKED */
4646 #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK          0x800UL                                                   /**< Bit mask for EMU_WDOG0LOCKED */
4647 #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT       0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4648 #define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT        (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11)    /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4649 #define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED                (0x1UL << 12)                                             /**< Indicates If WDOG1 Powered Down During EM23 */
4650 #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT         12                                                        /**< Shift value for EMU_WDOG1LOCKED */
4651 #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK          0x1000UL                                                  /**< Bit mask for EMU_WDOG1LOCKED */
4652 #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT       0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4653 #define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT        (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12)    /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4654 #define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED             (0x1UL << 13)                                             /**< Indicates If LESENSE0 Powered Down During EM23 */
4655 #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT      13                                                        /**< Shift value for EMU_LESENSE0LOCKED */
4656 #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK       0x2000UL                                                  /**< Bit mask for EMU_LESENSE0LOCKED */
4657 #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT    0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4658 #define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT     (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4659 #define EMU_EM23PERNORETAINSTATUS_CSENLOCKED                 (0x1UL << 14)                                             /**< Indicates If CSEN Powered Down During EM23 */
4660 #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT          14                                                        /**< Shift value for EMU_CSENLOCKED */
4661 #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK           0x4000UL                                                  /**< Bit mask for EMU_CSENLOCKED */
4662 #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT        0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4663 #define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT         (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4664 #define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED              (0x1UL << 15)                                             /**< Indicates If LEUART0 Powered Down During EM23 */
4665 #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT       15                                                        /**< Shift value for EMU_LEUART0LOCKED */
4666 #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK        0x8000UL                                                  /**< Bit mask for EMU_LEUART0LOCKED */
4667 #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT     0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4668 #define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT      (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15)  /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4669 #define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED              (0x1UL << 16)                                             /**< Indicates If LEUART1 Powered Down During EM23 */
4670 #define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT       16                                                        /**< Shift value for EMU_LEUART1LOCKED */
4671 #define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK        0x10000UL                                                 /**< Bit mask for EMU_LEUART1LOCKED */
4672 #define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT     0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4673 #define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT      (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16)  /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4674 #define EMU_EM23PERNORETAINSTATUS_LCDLOCKED                  (0x1UL << 17)                                             /**< Indicates If LCD Powered Down During EM23 */
4675 #define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT           17                                                        /**< Shift value for EMU_LCDLOCKED */
4676 #define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK            0x20000UL                                                 /**< Bit mask for EMU_LCDLOCKED */
4677 #define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT         0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4678 #define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT          (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4679 #define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED             (0x1UL << 18)                                             /**< Indicates If LETIMER1 Powered Down During EM23 */
4680 #define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT      18                                                        /**< Shift value for EMU_LETIMER1LOCKED */
4681 #define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK       0x40000UL                                                 /**< Bit mask for EMU_LETIMER1LOCKED */
4682 #define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT    0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4683 #define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT     (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4684 #define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED                 (0x1UL << 20)                                             /**< Indicates If ADC1 Powered Down During EM23 */
4685 #define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT          20                                                        /**< Shift value for EMU_ADC1LOCKED */
4686 #define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK           0x100000UL                                                /**< Bit mask for EMU_ADC1LOCKED */
4687 #define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT        0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4688 #define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT         (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4689 #define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED                (0x1UL << 21)                                             /**< Indicates If ACMP2 Powered Down During EM23 */
4690 #define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT         21                                                        /**< Shift value for EMU_ACMP2LOCKED */
4691 #define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK          0x200000UL                                                /**< Bit mask for EMU_ACMP2LOCKED */
4692 #define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT       0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4693 #define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT        (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21)    /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4694 #define EMU_EM23PERNORETAINSTATUS_RTCLOCKED                  (0x1UL << 23)                                             /**< Indicates If RTC Powered Down During EM23 */
4695 #define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT           23                                                        /**< Shift value for EMU_RTCLOCKED */
4696 #define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK            0x800000UL                                                /**< Bit mask for EMU_RTCLOCKED */
4697 #define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT         0x00000000UL                                              /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4698 #define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT          (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
4699 
4700 /* Bit fields for EMU EM23PERNORETAINCTRL */
4701 #define _EMU_EM23PERNORETAINCTRL_RESETVALUE                  0x00000000UL                                         /**< Default value for EMU_EM23PERNORETAINCTRL */
4702 #define _EMU_EM23PERNORETAINCTRL_MASK                        0x00B7FFFFUL                                         /**< Mask for EMU_EM23PERNORETAINCTRL */
4703 #define EMU_EM23PERNORETAINCTRL_ACMP0DIS                     (0x1UL << 0)                                         /**< Allow Power Down of ACMP0 During EM23 */
4704 #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT              0                                                    /**< Shift value for EMU_ACMP0DIS */
4705 #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK               0x1UL                                                /**< Bit mask for EMU_ACMP0DIS */
4706 #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT            0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4707 #define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT             (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4708 #define EMU_EM23PERNORETAINCTRL_ACMP1DIS                     (0x1UL << 1)                                         /**< Allow Power Down of ACMP1 During EM23 */
4709 #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT              1                                                    /**< Shift value for EMU_ACMP1DIS */
4710 #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK               0x2UL                                                /**< Bit mask for EMU_ACMP1DIS */
4711 #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT            0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4712 #define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT             (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4713 #define EMU_EM23PERNORETAINCTRL_PCNT0DIS                     (0x1UL << 2)                                         /**< Allow Power Down of PCNT0 During EM23 */
4714 #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT              2                                                    /**< Shift value for EMU_PCNT0DIS */
4715 #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK               0x4UL                                                /**< Bit mask for EMU_PCNT0DIS */
4716 #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT            0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4717 #define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT             (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4718 #define EMU_EM23PERNORETAINCTRL_PCNT1DIS                     (0x1UL << 3)                                         /**< Allow Power Down of PCNT1 During EM23 */
4719 #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT              3                                                    /**< Shift value for EMU_PCNT1DIS */
4720 #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK               0x8UL                                                /**< Bit mask for EMU_PCNT1DIS */
4721 #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT            0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4722 #define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT             (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4723 #define EMU_EM23PERNORETAINCTRL_PCNT2DIS                     (0x1UL << 4)                                         /**< Allow Power Down of PCNT2 During EM23 */
4724 #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT              4                                                    /**< Shift value for EMU_PCNT2DIS */
4725 #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK               0x10UL                                               /**< Bit mask for EMU_PCNT2DIS */
4726 #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT            0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4727 #define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT             (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4728 #define EMU_EM23PERNORETAINCTRL_I2C0DIS                      (0x1UL << 5)                                         /**< Allow Power Down of I2C0 During EM23 */
4729 #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT               5                                                    /**< Shift value for EMU_I2C0DIS */
4730 #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK                0x20UL                                               /**< Bit mask for EMU_I2C0DIS */
4731 #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT             0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4732 #define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT              (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4733 #define EMU_EM23PERNORETAINCTRL_I2C1DIS                      (0x1UL << 6)                                         /**< Allow Power Down of I2C1 During EM23 */
4734 #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT               6                                                    /**< Shift value for EMU_I2C1DIS */
4735 #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK                0x40UL                                               /**< Bit mask for EMU_I2C1DIS */
4736 #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT             0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4737 #define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT              (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4738 #define EMU_EM23PERNORETAINCTRL_VDAC0DIS                     (0x1UL << 7)                                         /**< Allow Power Down of DAC0 During EM23 */
4739 #define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT              7                                                    /**< Shift value for EMU_VDAC0DIS */
4740 #define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK               0x80UL                                               /**< Bit mask for EMU_VDAC0DIS */
4741 #define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT            0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4742 #define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT             (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4743 #define EMU_EM23PERNORETAINCTRL_IDAC0DIS                     (0x1UL << 8)                                         /**< Allow Power Down of IDAC0 During EM23 */
4744 #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT              8                                                    /**< Shift value for EMU_IDAC0DIS */
4745 #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK               0x100UL                                              /**< Bit mask for EMU_IDAC0DIS */
4746 #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT            0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4747 #define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT             (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4748 #define EMU_EM23PERNORETAINCTRL_ADC0DIS                      (0x1UL << 9)                                         /**< Allow Power Down of ADC0 During EM23 */
4749 #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT               9                                                    /**< Shift value for EMU_ADC0DIS */
4750 #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK                0x200UL                                              /**< Bit mask for EMU_ADC0DIS */
4751 #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT             0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4752 #define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT              (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4753 #define EMU_EM23PERNORETAINCTRL_LETIMER0DIS                  (0x1UL << 10)                                        /**< Allow Power Down of LETIMER0 During EM23 */
4754 #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT           10                                                   /**< Shift value for EMU_LETIMER0DIS */
4755 #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK            0x400UL                                              /**< Bit mask for EMU_LETIMER0DIS */
4756 #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT         0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4757 #define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT          (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4758 #define EMU_EM23PERNORETAINCTRL_WDOG0DIS                     (0x1UL << 11)                                        /**< Allow Power Down of WDOG0 During EM23 */
4759 #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT              11                                                   /**< Shift value for EMU_WDOG0DIS */
4760 #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK               0x800UL                                              /**< Bit mask for EMU_WDOG0DIS */
4761 #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT            0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4762 #define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT             (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11)    /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4763 #define EMU_EM23PERNORETAINCTRL_WDOG1DIS                     (0x1UL << 12)                                        /**< Allow Power Down of WDOG1 During EM23 */
4764 #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT              12                                                   /**< Shift value for EMU_WDOG1DIS */
4765 #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK               0x1000UL                                             /**< Bit mask for EMU_WDOG1DIS */
4766 #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT            0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4767 #define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT             (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12)    /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4768 #define EMU_EM23PERNORETAINCTRL_LESENSE0DIS                  (0x1UL << 13)                                        /**< Allow Power Down of LESENSE0 During EM23 */
4769 #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT           13                                                   /**< Shift value for EMU_LESENSE0DIS */
4770 #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK            0x2000UL                                             /**< Bit mask for EMU_LESENSE0DIS */
4771 #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT         0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4772 #define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT          (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4773 #define EMU_EM23PERNORETAINCTRL_CSENDIS                      (0x1UL << 14)                                        /**< Allow Power Down of CSEN During EM23 */
4774 #define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT               14                                                   /**< Shift value for EMU_CSENDIS */
4775 #define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK                0x4000UL                                             /**< Bit mask for EMU_CSENDIS */
4776 #define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT             0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4777 #define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT              (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4778 #define EMU_EM23PERNORETAINCTRL_LEUART0DIS                   (0x1UL << 15)                                        /**< Allow Power Down of LEUART0 During EM23 */
4779 #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT            15                                                   /**< Shift value for EMU_LEUART0DIS */
4780 #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK             0x8000UL                                             /**< Bit mask for EMU_LEUART0DIS */
4781 #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT          0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4782 #define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT           (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15)  /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4783 #define EMU_EM23PERNORETAINCTRL_LEUART1DIS                   (0x1UL << 16)                                        /**< Allow Power Down of LEUART1 During EM23 */
4784 #define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT            16                                                   /**< Shift value for EMU_LEUART1DIS */
4785 #define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK             0x10000UL                                            /**< Bit mask for EMU_LEUART1DIS */
4786 #define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT          0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4787 #define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT           (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16)  /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4788 #define EMU_EM23PERNORETAINCTRL_LCDDIS                       (0x1UL << 17)                                        /**< Allow Power Down of LCD During EM23 */
4789 #define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT                17                                                   /**< Shift value for EMU_LCDDIS */
4790 #define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK                 0x20000UL                                            /**< Bit mask for EMU_LCDDIS */
4791 #define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT              0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4792 #define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT               (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4793 #define EMU_EM23PERNORETAINCTRL_LETIMER1DIS                  (0x1UL << 18)                                        /**< Allow Power Down of LETIMER1 During EM23 */
4794 #define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT           18                                                   /**< Shift value for EMU_LETIMER1DIS */
4795 #define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK            0x40000UL                                            /**< Bit mask for EMU_LETIMER1DIS */
4796 #define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT         0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4797 #define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT          (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4798 #define EMU_EM23PERNORETAINCTRL_ADC1DIS                      (0x1UL << 20)                                        /**< Allow Power Down of ADC1 During EM23 */
4799 #define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT               20                                                   /**< Shift value for EMU_ADC1DIS */
4800 #define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK                0x100000UL                                           /**< Bit mask for EMU_ADC1DIS */
4801 #define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT             0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4802 #define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT              (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20)     /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4803 #define EMU_EM23PERNORETAINCTRL_ACMP2DIS                     (0x1UL << 21)                                        /**< Allow Power Down of ACMP2 During EM23 */
4804 #define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT              21                                                   /**< Shift value for EMU_ACMP2DIS */
4805 #define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK               0x200000UL                                           /**< Bit mask for EMU_ACMP2DIS */
4806 #define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT            0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4807 #define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT             (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21)    /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4808 #define EMU_EM23PERNORETAINCTRL_RTCDIS                       (0x1UL << 23)                                        /**< Allow Power Down of RTC During EM23 */
4809 #define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT                23                                                   /**< Shift value for EMU_RTCDIS */
4810 #define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK                 0x800000UL                                           /**< Bit mask for EMU_RTCDIS */
4811 #define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT              0x00000000UL                                         /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4812 #define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT               (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23)      /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
4813 
4814 /** @} */
4815 /** @} End of group EFM32GG12B310F1024GQ100_EMU */
4816 
4817 /***************************************************************************//**
4818  * @addtogroup EFM32GG12B310F1024GQ100_CMU
4819  * @{
4820  * @defgroup EFM32GG12B310F1024GQ100_CMU_BitFields  CMU Bit Fields
4821  * @{
4822  ******************************************************************************/
4823 
4824 /* Bit fields for CMU CTRL */
4825 #define _CMU_CTRL_RESETVALUE                              0x00100000UL                           /**< Default value for CMU_CTRL */
4826 #define _CMU_CTRL_MASK                                    0x00117FFFUL                           /**< Mask for CMU_CTRL */
4827 #define _CMU_CTRL_CLKOUTSEL0_SHIFT                        0                                      /**< Shift value for CMU_CLKOUTSEL0 */
4828 #define _CMU_CTRL_CLKOUTSEL0_MASK                         0x1FUL                                 /**< Bit mask for CMU_CLKOUTSEL0 */
4829 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for CMU_CTRL */
4830 #define _CMU_CTRL_CLKOUTSEL0_DISABLED                     0x00000000UL                           /**< Mode DISABLED for CMU_CTRL */
4831 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO                       0x00000001UL                           /**< Mode ULFRCO for CMU_CTRL */
4832 #define _CMU_CTRL_CLKOUTSEL0_LFRCO                        0x00000002UL                           /**< Mode LFRCO for CMU_CTRL */
4833 #define _CMU_CTRL_CLKOUTSEL0_LFXO                         0x00000003UL                           /**< Mode LFXO for CMU_CTRL */
4834 #define _CMU_CTRL_CLKOUTSEL0_HFXO                         0x00000006UL                           /**< Mode HFXO for CMU_CTRL */
4835 #define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK                     0x00000007UL                           /**< Mode HFEXPCLK for CMU_CTRL */
4836 #define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ                      0x00000009UL                           /**< Mode ULFRCOQ for CMU_CTRL */
4837 #define _CMU_CTRL_CLKOUTSEL0_LFRCOQ                       0x0000000AUL                           /**< Mode LFRCOQ for CMU_CTRL */
4838 #define _CMU_CTRL_CLKOUTSEL0_LFXOQ                        0x0000000BUL                           /**< Mode LFXOQ for CMU_CTRL */
4839 #define _CMU_CTRL_CLKOUTSEL0_HFRCOQ                       0x0000000CUL                           /**< Mode HFRCOQ for CMU_CTRL */
4840 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ                    0x0000000DUL                           /**< Mode AUXHFRCOQ for CMU_CTRL */
4841 #define _CMU_CTRL_CLKOUTSEL0_HFXOQ                        0x0000000EUL                           /**< Mode HFXOQ for CMU_CTRL */
4842 #define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK                     0x0000000FUL                           /**< Mode HFSRCCLK for CMU_CTRL */
4843 #define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ                     0x00000012UL                           /**< Mode USHFRCOQ for CMU_CTRL */
4844 #define CMU_CTRL_CLKOUTSEL0_DEFAULT                       (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0)    /**< Shifted mode DEFAULT for CMU_CTRL */
4845 #define CMU_CTRL_CLKOUTSEL0_DISABLED                      (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0)   /**< Shifted mode DISABLED for CMU_CTRL */
4846 #define CMU_CTRL_CLKOUTSEL0_ULFRCO                        (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0)     /**< Shifted mode ULFRCO for CMU_CTRL */
4847 #define CMU_CTRL_CLKOUTSEL0_LFRCO                         (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0)      /**< Shifted mode LFRCO for CMU_CTRL */
4848 #define CMU_CTRL_CLKOUTSEL0_LFXO                          (_CMU_CTRL_CLKOUTSEL0_LFXO << 0)       /**< Shifted mode LFXO for CMU_CTRL */
4849 #define CMU_CTRL_CLKOUTSEL0_HFXO                          (_CMU_CTRL_CLKOUTSEL0_HFXO << 0)       /**< Shifted mode HFXO for CMU_CTRL */
4850 #define CMU_CTRL_CLKOUTSEL0_HFEXPCLK                      (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0)   /**< Shifted mode HFEXPCLK for CMU_CTRL */
4851 #define CMU_CTRL_CLKOUTSEL0_ULFRCOQ                       (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0)    /**< Shifted mode ULFRCOQ for CMU_CTRL */
4852 #define CMU_CTRL_CLKOUTSEL0_LFRCOQ                        (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0)     /**< Shifted mode LFRCOQ for CMU_CTRL */
4853 #define CMU_CTRL_CLKOUTSEL0_LFXOQ                         (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0)      /**< Shifted mode LFXOQ for CMU_CTRL */
4854 #define CMU_CTRL_CLKOUTSEL0_HFRCOQ                        (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0)     /**< Shifted mode HFRCOQ for CMU_CTRL */
4855 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ                     (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0)  /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
4856 #define CMU_CTRL_CLKOUTSEL0_HFXOQ                         (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0)      /**< Shifted mode HFXOQ for CMU_CTRL */
4857 #define CMU_CTRL_CLKOUTSEL0_HFSRCCLK                      (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0)   /**< Shifted mode HFSRCCLK for CMU_CTRL */
4858 #define CMU_CTRL_CLKOUTSEL0_USHFRCOQ                      (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0)   /**< Shifted mode USHFRCOQ for CMU_CTRL */
4859 #define _CMU_CTRL_CLKOUTSEL1_SHIFT                        5                                      /**< Shift value for CMU_CLKOUTSEL1 */
4860 #define _CMU_CTRL_CLKOUTSEL1_MASK                         0x3E0UL                                /**< Bit mask for CMU_CLKOUTSEL1 */
4861 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for CMU_CTRL */
4862 #define _CMU_CTRL_CLKOUTSEL1_DISABLED                     0x00000000UL                           /**< Mode DISABLED for CMU_CTRL */
4863 #define _CMU_CTRL_CLKOUTSEL1_ULFRCO                       0x00000001UL                           /**< Mode ULFRCO for CMU_CTRL */
4864 #define _CMU_CTRL_CLKOUTSEL1_LFRCO                        0x00000002UL                           /**< Mode LFRCO for CMU_CTRL */
4865 #define _CMU_CTRL_CLKOUTSEL1_LFXO                         0x00000003UL                           /**< Mode LFXO for CMU_CTRL */
4866 #define _CMU_CTRL_CLKOUTSEL1_HFXO                         0x00000006UL                           /**< Mode HFXO for CMU_CTRL */
4867 #define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK                     0x00000007UL                           /**< Mode HFEXPCLK for CMU_CTRL */
4868 #define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ                      0x00000009UL                           /**< Mode ULFRCOQ for CMU_CTRL */
4869 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ                       0x0000000AUL                           /**< Mode LFRCOQ for CMU_CTRL */
4870 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ                        0x0000000BUL                           /**< Mode LFXOQ for CMU_CTRL */
4871 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ                       0x0000000CUL                           /**< Mode HFRCOQ for CMU_CTRL */
4872 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ                    0x0000000DUL                           /**< Mode AUXHFRCOQ for CMU_CTRL */
4873 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ                        0x0000000EUL                           /**< Mode HFXOQ for CMU_CTRL */
4874 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK                     0x0000000FUL                           /**< Mode HFSRCCLK for CMU_CTRL */
4875 #define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ                     0x00000012UL                           /**< Mode USHFRCOQ for CMU_CTRL */
4876 #define CMU_CTRL_CLKOUTSEL1_DEFAULT                       (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5)    /**< Shifted mode DEFAULT for CMU_CTRL */
4877 #define CMU_CTRL_CLKOUTSEL1_DISABLED                      (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5)   /**< Shifted mode DISABLED for CMU_CTRL */
4878 #define CMU_CTRL_CLKOUTSEL1_ULFRCO                        (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5)     /**< Shifted mode ULFRCO for CMU_CTRL */
4879 #define CMU_CTRL_CLKOUTSEL1_LFRCO                         (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5)      /**< Shifted mode LFRCO for CMU_CTRL */
4880 #define CMU_CTRL_CLKOUTSEL1_LFXO                          (_CMU_CTRL_CLKOUTSEL1_LFXO << 5)       /**< Shifted mode LFXO for CMU_CTRL */
4881 #define CMU_CTRL_CLKOUTSEL1_HFXO                          (_CMU_CTRL_CLKOUTSEL1_HFXO << 5)       /**< Shifted mode HFXO for CMU_CTRL */
4882 #define CMU_CTRL_CLKOUTSEL1_HFEXPCLK                      (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5)   /**< Shifted mode HFEXPCLK for CMU_CTRL */
4883 #define CMU_CTRL_CLKOUTSEL1_ULFRCOQ                       (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5)    /**< Shifted mode ULFRCOQ for CMU_CTRL */
4884 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ                        (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5)     /**< Shifted mode LFRCOQ for CMU_CTRL */
4885 #define CMU_CTRL_CLKOUTSEL1_LFXOQ                         (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5)      /**< Shifted mode LFXOQ for CMU_CTRL */
4886 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ                        (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5)     /**< Shifted mode HFRCOQ for CMU_CTRL */
4887 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ                     (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5)  /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
4888 #define CMU_CTRL_CLKOUTSEL1_HFXOQ                         (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5)      /**< Shifted mode HFXOQ for CMU_CTRL */
4889 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK                      (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5)   /**< Shifted mode HFSRCCLK for CMU_CTRL */
4890 #define CMU_CTRL_CLKOUTSEL1_USHFRCOQ                      (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5)   /**< Shifted mode USHFRCOQ for CMU_CTRL */
4891 #define _CMU_CTRL_CLKOUTSEL2_SHIFT                        10                                     /**< Shift value for CMU_CLKOUTSEL2 */
4892 #define _CMU_CTRL_CLKOUTSEL2_MASK                         0x7C00UL                               /**< Bit mask for CMU_CLKOUTSEL2 */
4893 #define _CMU_CTRL_CLKOUTSEL2_DEFAULT                      0x00000000UL                           /**< Mode DEFAULT for CMU_CTRL */
4894 #define _CMU_CTRL_CLKOUTSEL2_DISABLED                     0x00000000UL                           /**< Mode DISABLED for CMU_CTRL */
4895 #define _CMU_CTRL_CLKOUTSEL2_ULFRCO                       0x00000001UL                           /**< Mode ULFRCO for CMU_CTRL */
4896 #define _CMU_CTRL_CLKOUTSEL2_LFRCO                        0x00000002UL                           /**< Mode LFRCO for CMU_CTRL */
4897 #define _CMU_CTRL_CLKOUTSEL2_LFXO                         0x00000003UL                           /**< Mode LFXO for CMU_CTRL */
4898 #define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q                    0x00000005UL                           /**< Mode HFXODIV2Q for CMU_CTRL */
4899 #define _CMU_CTRL_CLKOUTSEL2_HFXO                         0x00000006UL                           /**< Mode HFXO for CMU_CTRL */
4900 #define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK                     0x00000007UL                           /**< Mode HFEXPCLK for CMU_CTRL */
4901 #define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q                      0x00000008UL                           /**< Mode HFXOX2Q for CMU_CTRL */
4902 #define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ                      0x00000009UL                           /**< Mode ULFRCOQ for CMU_CTRL */
4903 #define _CMU_CTRL_CLKOUTSEL2_LFRCOQ                       0x0000000AUL                           /**< Mode LFRCOQ for CMU_CTRL */
4904 #define _CMU_CTRL_CLKOUTSEL2_LFXOQ                        0x0000000BUL                           /**< Mode LFXOQ for CMU_CTRL */
4905 #define _CMU_CTRL_CLKOUTSEL2_HFRCOQ                       0x0000000CUL                           /**< Mode HFRCOQ for CMU_CTRL */
4906 #define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ                    0x0000000DUL                           /**< Mode AUXHFRCOQ for CMU_CTRL */
4907 #define _CMU_CTRL_CLKOUTSEL2_HFXOQ                        0x0000000EUL                           /**< Mode HFXOQ for CMU_CTRL */
4908 #define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK                     0x0000000FUL                           /**< Mode HFSRCCLK for CMU_CTRL */
4909 #define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ                     0x00000012UL                           /**< Mode USHFRCOQ for CMU_CTRL */
4910 #define CMU_CTRL_CLKOUTSEL2_DEFAULT                       (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10)   /**< Shifted mode DEFAULT for CMU_CTRL */
4911 #define CMU_CTRL_CLKOUTSEL2_DISABLED                      (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10)  /**< Shifted mode DISABLED for CMU_CTRL */
4912 #define CMU_CTRL_CLKOUTSEL2_ULFRCO                        (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10)    /**< Shifted mode ULFRCO for CMU_CTRL */
4913 #define CMU_CTRL_CLKOUTSEL2_LFRCO                         (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10)     /**< Shifted mode LFRCO for CMU_CTRL */
4914 #define CMU_CTRL_CLKOUTSEL2_LFXO                          (_CMU_CTRL_CLKOUTSEL2_LFXO << 10)      /**< Shifted mode LFXO for CMU_CTRL */
4915 #define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q                     (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */
4916 #define CMU_CTRL_CLKOUTSEL2_HFXO                          (_CMU_CTRL_CLKOUTSEL2_HFXO << 10)      /**< Shifted mode HFXO for CMU_CTRL */
4917 #define CMU_CTRL_CLKOUTSEL2_HFEXPCLK                      (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10)  /**< Shifted mode HFEXPCLK for CMU_CTRL */
4918 #define CMU_CTRL_CLKOUTSEL2_HFXOX2Q                       (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10)   /**< Shifted mode HFXOX2Q for CMU_CTRL */
4919 #define CMU_CTRL_CLKOUTSEL2_ULFRCOQ                       (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10)   /**< Shifted mode ULFRCOQ for CMU_CTRL */
4920 #define CMU_CTRL_CLKOUTSEL2_LFRCOQ                        (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10)    /**< Shifted mode LFRCOQ for CMU_CTRL */
4921 #define CMU_CTRL_CLKOUTSEL2_LFXOQ                         (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10)     /**< Shifted mode LFXOQ for CMU_CTRL */
4922 #define CMU_CTRL_CLKOUTSEL2_HFRCOQ                        (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10)    /**< Shifted mode HFRCOQ for CMU_CTRL */
4923 #define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ                     (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
4924 #define CMU_CTRL_CLKOUTSEL2_HFXOQ                         (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10)     /**< Shifted mode HFXOQ for CMU_CTRL */
4925 #define CMU_CTRL_CLKOUTSEL2_HFSRCCLK                      (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10)  /**< Shifted mode HFSRCCLK for CMU_CTRL */
4926 #define CMU_CTRL_CLKOUTSEL2_USHFRCOQ                      (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10)  /**< Shifted mode USHFRCOQ for CMU_CTRL */
4927 #define CMU_CTRL_WSHFLE                                   (0x1UL << 16)                          /**< Wait State for High-Frequency LE Interface */
4928 #define _CMU_CTRL_WSHFLE_SHIFT                            16                                     /**< Shift value for CMU_WSHFLE */
4929 #define _CMU_CTRL_WSHFLE_MASK                             0x10000UL                              /**< Bit mask for CMU_WSHFLE */
4930 #define _CMU_CTRL_WSHFLE_DEFAULT                          0x00000000UL                           /**< Mode DEFAULT for CMU_CTRL */
4931 #define CMU_CTRL_WSHFLE_DEFAULT                           (_CMU_CTRL_WSHFLE_DEFAULT << 16)       /**< Shifted mode DEFAULT for CMU_CTRL */
4932 #define CMU_CTRL_HFPERCLKEN                               (0x1UL << 20)                          /**< HFPERCLK Enable */
4933 #define _CMU_CTRL_HFPERCLKEN_SHIFT                        20                                     /**< Shift value for CMU_HFPERCLKEN */
4934 #define _CMU_CTRL_HFPERCLKEN_MASK                         0x100000UL                             /**< Bit mask for CMU_HFPERCLKEN */
4935 #define _CMU_CTRL_HFPERCLKEN_DEFAULT                      0x00000001UL                           /**< Mode DEFAULT for CMU_CTRL */
4936 #define CMU_CTRL_HFPERCLKEN_DEFAULT                       (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20)   /**< Shifted mode DEFAULT for CMU_CTRL */
4937 
4938 /* Bit fields for CMU USHFRCOCTRL */
4939 #define _CMU_USHFRCOCTRL_RESETVALUE                       0xB1481F7FUL                                  /**< Default value for CMU_USHFRCOCTRL */
4940 #define _CMU_USHFRCOCTRL_MASK                             0xFFFF3F7FUL                                  /**< Mask for CMU_USHFRCOCTRL */
4941 #define _CMU_USHFRCOCTRL_TUNING_SHIFT                     0                                             /**< Shift value for CMU_TUNING */
4942 #define _CMU_USHFRCOCTRL_TUNING_MASK                      0x7FUL                                        /**< Bit mask for CMU_TUNING */
4943 #define _CMU_USHFRCOCTRL_TUNING_DEFAULT                   0x0000007FUL                                  /**< Mode DEFAULT for CMU_USHFRCOCTRL */
4944 #define CMU_USHFRCOCTRL_TUNING_DEFAULT                    (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0)        /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
4945 #define _CMU_USHFRCOCTRL_FINETUNING_SHIFT                 8                                             /**< Shift value for CMU_FINETUNING */
4946 #define _CMU_USHFRCOCTRL_FINETUNING_MASK                  0x3F00UL                                      /**< Bit mask for CMU_FINETUNING */
4947 #define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT               0x0000001FUL                                  /**< Mode DEFAULT for CMU_USHFRCOCTRL */
4948 #define CMU_USHFRCOCTRL_FINETUNING_DEFAULT                (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8)    /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
4949 #define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT                  16                                            /**< Shift value for CMU_FREQRANGE */
4950 #define _CMU_USHFRCOCTRL_FREQRANGE_MASK                   0x1F0000UL                                    /**< Bit mask for CMU_FREQRANGE */
4951 #define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT                0x00000008UL                                  /**< Mode DEFAULT for CMU_USHFRCOCTRL */
4952 #define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT                 (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16)    /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
4953 #define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT                    21                                            /**< Shift value for CMU_CMPBIAS */
4954 #define _CMU_USHFRCOCTRL_CMPBIAS_MASK                     0xE00000UL                                    /**< Bit mask for CMU_CMPBIAS */
4955 #define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT                  0x00000002UL                                  /**< Mode DEFAULT for CMU_USHFRCOCTRL */
4956 #define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT                   (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21)      /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
4957 #define CMU_USHFRCOCTRL_LDOHP                             (0x1UL << 24)                                 /**< USHFRCO LDO High Power Mode */
4958 #define _CMU_USHFRCOCTRL_LDOHP_SHIFT                      24                                            /**< Shift value for CMU_LDOHP */
4959 #define _CMU_USHFRCOCTRL_LDOHP_MASK                       0x1000000UL                                   /**< Bit mask for CMU_LDOHP */
4960 #define _CMU_USHFRCOCTRL_LDOHP_DEFAULT                    0x00000001UL                                  /**< Mode DEFAULT for CMU_USHFRCOCTRL */
4961 #define CMU_USHFRCOCTRL_LDOHP_DEFAULT                     (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24)        /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
4962 #define _CMU_USHFRCOCTRL_CLKDIV_SHIFT                     25                                            /**< Shift value for CMU_CLKDIV */
4963 #define _CMU_USHFRCOCTRL_CLKDIV_MASK                      0x6000000UL                                   /**< Bit mask for CMU_CLKDIV */
4964 #define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT                   0x00000000UL                                  /**< Mode DEFAULT for CMU_USHFRCOCTRL */
4965 #define _CMU_USHFRCOCTRL_CLKDIV_DIV1                      0x00000000UL                                  /**< Mode DIV1 for CMU_USHFRCOCTRL */
4966 #define _CMU_USHFRCOCTRL_CLKDIV_DIV2                      0x00000001UL                                  /**< Mode DIV2 for CMU_USHFRCOCTRL */
4967 #define _CMU_USHFRCOCTRL_CLKDIV_DIV4                      0x00000002UL                                  /**< Mode DIV4 for CMU_USHFRCOCTRL */
4968 #define CMU_USHFRCOCTRL_CLKDIV_DEFAULT                    (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25)       /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
4969 #define CMU_USHFRCOCTRL_CLKDIV_DIV1                       (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25)          /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */
4970 #define CMU_USHFRCOCTRL_CLKDIV_DIV2                       (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25)          /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */
4971 #define CMU_USHFRCOCTRL_CLKDIV_DIV4                       (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25)          /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */
4972 #define CMU_USHFRCOCTRL_FINETUNINGEN                      (0x1UL << 27)                                 /**< Enable Reference for Fine Tuning */
4973 #define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT               27                                            /**< Shift value for CMU_FINETUNINGEN */
4974 #define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK                0x8000000UL                                   /**< Bit mask for CMU_FINETUNINGEN */
4975 #define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT             0x00000000UL                                  /**< Mode DEFAULT for CMU_USHFRCOCTRL */
4976 #define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT              (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
4977 #define _CMU_USHFRCOCTRL_VREFTC_SHIFT                     28                                            /**< Shift value for CMU_VREFTC */
4978 #define _CMU_USHFRCOCTRL_VREFTC_MASK                      0xF0000000UL                                  /**< Bit mask for CMU_VREFTC */
4979 #define _CMU_USHFRCOCTRL_VREFTC_DEFAULT                   0x0000000BUL                                  /**< Mode DEFAULT for CMU_USHFRCOCTRL */
4980 #define CMU_USHFRCOCTRL_VREFTC_DEFAULT                    (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28)       /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
4981 
4982 /* Bit fields for CMU HFRCOCTRL */
4983 #define _CMU_HFRCOCTRL_RESETVALUE                         0xB1481F7FUL                                /**< Default value for CMU_HFRCOCTRL */
4984 #define _CMU_HFRCOCTRL_MASK                               0xFFFF3F7FUL                                /**< Mask for CMU_HFRCOCTRL */
4985 #define _CMU_HFRCOCTRL_TUNING_SHIFT                       0                                           /**< Shift value for CMU_TUNING */
4986 #define _CMU_HFRCOCTRL_TUNING_MASK                        0x7FUL                                      /**< Bit mask for CMU_TUNING */
4987 #define _CMU_HFRCOCTRL_TUNING_DEFAULT                     0x0000007FUL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
4988 #define CMU_HFRCOCTRL_TUNING_DEFAULT                      (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)        /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
4989 #define _CMU_HFRCOCTRL_FINETUNING_SHIFT                   8                                           /**< Shift value for CMU_FINETUNING */
4990 #define _CMU_HFRCOCTRL_FINETUNING_MASK                    0x3F00UL                                    /**< Bit mask for CMU_FINETUNING */
4991 #define _CMU_HFRCOCTRL_FINETUNING_DEFAULT                 0x0000001FUL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
4992 #define CMU_HFRCOCTRL_FINETUNING_DEFAULT                  (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8)    /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
4993 #define _CMU_HFRCOCTRL_FREQRANGE_SHIFT                    16                                          /**< Shift value for CMU_FREQRANGE */
4994 #define _CMU_HFRCOCTRL_FREQRANGE_MASK                     0x1F0000UL                                  /**< Bit mask for CMU_FREQRANGE */
4995 #define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT                  0x00000008UL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
4996 #define CMU_HFRCOCTRL_FREQRANGE_DEFAULT                   (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16)    /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
4997 #define _CMU_HFRCOCTRL_CMPBIAS_SHIFT                      21                                          /**< Shift value for CMU_CMPBIAS */
4998 #define _CMU_HFRCOCTRL_CMPBIAS_MASK                       0xE00000UL                                  /**< Bit mask for CMU_CMPBIAS */
4999 #define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT                    0x00000002UL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
5000 #define CMU_HFRCOCTRL_CMPBIAS_DEFAULT                     (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21)      /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
5001 #define CMU_HFRCOCTRL_LDOHP                               (0x1UL << 24)                               /**< HFRCO LDO High Power Mode */
5002 #define _CMU_HFRCOCTRL_LDOHP_SHIFT                        24                                          /**< Shift value for CMU_LDOHP */
5003 #define _CMU_HFRCOCTRL_LDOHP_MASK                         0x1000000UL                                 /**< Bit mask for CMU_LDOHP */
5004 #define _CMU_HFRCOCTRL_LDOHP_DEFAULT                      0x00000001UL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
5005 #define CMU_HFRCOCTRL_LDOHP_DEFAULT                       (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24)        /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
5006 #define _CMU_HFRCOCTRL_CLKDIV_SHIFT                       25                                          /**< Shift value for CMU_CLKDIV */
5007 #define _CMU_HFRCOCTRL_CLKDIV_MASK                        0x6000000UL                                 /**< Bit mask for CMU_CLKDIV */
5008 #define _CMU_HFRCOCTRL_CLKDIV_DEFAULT                     0x00000000UL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
5009 #define _CMU_HFRCOCTRL_CLKDIV_DIV1                        0x00000000UL                                /**< Mode DIV1 for CMU_HFRCOCTRL */
5010 #define _CMU_HFRCOCTRL_CLKDIV_DIV2                        0x00000001UL                                /**< Mode DIV2 for CMU_HFRCOCTRL */
5011 #define _CMU_HFRCOCTRL_CLKDIV_DIV4                        0x00000002UL                                /**< Mode DIV4 for CMU_HFRCOCTRL */
5012 #define CMU_HFRCOCTRL_CLKDIV_DEFAULT                      (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25)       /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
5013 #define CMU_HFRCOCTRL_CLKDIV_DIV1                         (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25)          /**< Shifted mode DIV1 for CMU_HFRCOCTRL */
5014 #define CMU_HFRCOCTRL_CLKDIV_DIV2                         (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25)          /**< Shifted mode DIV2 for CMU_HFRCOCTRL */
5015 #define CMU_HFRCOCTRL_CLKDIV_DIV4                         (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25)          /**< Shifted mode DIV4 for CMU_HFRCOCTRL */
5016 #define CMU_HFRCOCTRL_FINETUNINGEN                        (0x1UL << 27)                               /**< Enable Reference for Fine Tuning */
5017 #define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT                 27                                          /**< Shift value for CMU_FINETUNINGEN */
5018 #define _CMU_HFRCOCTRL_FINETUNINGEN_MASK                  0x8000000UL                                 /**< Bit mask for CMU_FINETUNINGEN */
5019 #define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT               0x00000000UL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
5020 #define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT                (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
5021 #define _CMU_HFRCOCTRL_VREFTC_SHIFT                       28                                          /**< Shift value for CMU_VREFTC */
5022 #define _CMU_HFRCOCTRL_VREFTC_MASK                        0xF0000000UL                                /**< Bit mask for CMU_VREFTC */
5023 #define _CMU_HFRCOCTRL_VREFTC_DEFAULT                     0x0000000BUL                                /**< Mode DEFAULT for CMU_HFRCOCTRL */
5024 #define CMU_HFRCOCTRL_VREFTC_DEFAULT                      (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28)       /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
5025 
5026 /* Bit fields for CMU AUXHFRCOCTRL */
5027 #define _CMU_AUXHFRCOCTRL_RESETVALUE                      0xB1481F7FUL                                   /**< Default value for CMU_AUXHFRCOCTRL */
5028 #define _CMU_AUXHFRCOCTRL_MASK                            0xFFFF3F7FUL                                   /**< Mask for CMU_AUXHFRCOCTRL */
5029 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT                    0                                              /**< Shift value for CMU_TUNING */
5030 #define _CMU_AUXHFRCOCTRL_TUNING_MASK                     0x7FUL                                         /**< Bit mask for CMU_TUNING */
5031 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT                  0x0000007FUL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
5032 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT                   (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)        /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
5033 #define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT                8                                              /**< Shift value for CMU_FINETUNING */
5034 #define _CMU_AUXHFRCOCTRL_FINETUNING_MASK                 0x3F00UL                                       /**< Bit mask for CMU_FINETUNING */
5035 #define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT              0x0000001FUL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
5036 #define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT               (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8)    /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
5037 #define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT                 16                                             /**< Shift value for CMU_FREQRANGE */
5038 #define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK                  0x1F0000UL                                     /**< Bit mask for CMU_FREQRANGE */
5039 #define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT               0x00000008UL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
5040 #define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT                (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16)    /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
5041 #define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT                   21                                             /**< Shift value for CMU_CMPBIAS */
5042 #define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK                    0xE00000UL                                     /**< Bit mask for CMU_CMPBIAS */
5043 #define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT                 0x00000002UL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
5044 #define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT                  (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21)      /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
5045 #define CMU_AUXHFRCOCTRL_LDOHP                            (0x1UL << 24)                                  /**< AUXHFRCO LDO High Power Mode */
5046 #define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT                     24                                             /**< Shift value for CMU_LDOHP */
5047 #define _CMU_AUXHFRCOCTRL_LDOHP_MASK                      0x1000000UL                                    /**< Bit mask for CMU_LDOHP */
5048 #define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT                   0x00000001UL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
5049 #define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT                    (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24)        /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
5050 #define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT                    25                                             /**< Shift value for CMU_CLKDIV */
5051 #define _CMU_AUXHFRCOCTRL_CLKDIV_MASK                     0x6000000UL                                    /**< Bit mask for CMU_CLKDIV */
5052 #define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT                  0x00000000UL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
5053 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1                     0x00000000UL                                   /**< Mode DIV1 for CMU_AUXHFRCOCTRL */
5054 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2                     0x00000001UL                                   /**< Mode DIV2 for CMU_AUXHFRCOCTRL */
5055 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4                     0x00000002UL                                   /**< Mode DIV4 for CMU_AUXHFRCOCTRL */
5056 #define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT                   (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25)       /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
5057 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV1                      (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25)          /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */
5058 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV2                      (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25)          /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */
5059 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV4                      (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25)          /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */
5060 #define CMU_AUXHFRCOCTRL_FINETUNINGEN                     (0x1UL << 27)                                  /**< Enable Reference for Fine Tuning */
5061 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT              27                                             /**< Shift value for CMU_FINETUNINGEN */
5062 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK               0x8000000UL                                    /**< Bit mask for CMU_FINETUNINGEN */
5063 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT            0x00000000UL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
5064 #define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT             (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
5065 #define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT                    28                                             /**< Shift value for CMU_VREFTC */
5066 #define _CMU_AUXHFRCOCTRL_VREFTC_MASK                     0xF0000000UL                                   /**< Bit mask for CMU_VREFTC */
5067 #define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT                  0x0000000BUL                                   /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
5068 #define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT                   (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28)       /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
5069 
5070 /* Bit fields for CMU LFRCOCTRL */
5071 #define _CMU_LFRCOCTRL_RESETVALUE                         0x81160100UL                                /**< Default value for CMU_LFRCOCTRL */
5072 #define _CMU_LFRCOCTRL_MASK                               0xF33701FFUL                                /**< Mask for CMU_LFRCOCTRL */
5073 #define _CMU_LFRCOCTRL_TUNING_SHIFT                       0                                           /**< Shift value for CMU_TUNING */
5074 #define _CMU_LFRCOCTRL_TUNING_MASK                        0x1FFUL                                     /**< Bit mask for CMU_TUNING */
5075 #define _CMU_LFRCOCTRL_TUNING_DEFAULT                     0x00000100UL                                /**< Mode DEFAULT for CMU_LFRCOCTRL */
5076 #define CMU_LFRCOCTRL_TUNING_DEFAULT                      (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)        /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
5077 #define CMU_LFRCOCTRL_ENVREF                              (0x1UL << 16)                               /**< Enable Duty Cycling of Vref */
5078 #define _CMU_LFRCOCTRL_ENVREF_SHIFT                       16                                          /**< Shift value for CMU_ENVREF */
5079 #define _CMU_LFRCOCTRL_ENVREF_MASK                        0x10000UL                                   /**< Bit mask for CMU_ENVREF */
5080 #define _CMU_LFRCOCTRL_ENVREF_DEFAULT                     0x00000000UL                                /**< Mode DEFAULT for CMU_LFRCOCTRL */
5081 #define CMU_LFRCOCTRL_ENVREF_DEFAULT                      (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16)       /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
5082 #define CMU_LFRCOCTRL_ENCHOP                              (0x1UL << 17)                               /**< Enable Comparator Chopping */
5083 #define _CMU_LFRCOCTRL_ENCHOP_SHIFT                       17                                          /**< Shift value for CMU_ENCHOP */
5084 #define _CMU_LFRCOCTRL_ENCHOP_MASK                        0x20000UL                                   /**< Bit mask for CMU_ENCHOP */
5085 #define _CMU_LFRCOCTRL_ENCHOP_DEFAULT                     0x00000001UL                                /**< Mode DEFAULT for CMU_LFRCOCTRL */
5086 #define CMU_LFRCOCTRL_ENCHOP_DEFAULT                      (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17)       /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
5087 #define CMU_LFRCOCTRL_ENDEM                               (0x1UL << 18)                               /**< Enable Dynamic Element Matching */
5088 #define _CMU_LFRCOCTRL_ENDEM_SHIFT                        18                                          /**< Shift value for CMU_ENDEM */
5089 #define _CMU_LFRCOCTRL_ENDEM_MASK                         0x40000UL                                   /**< Bit mask for CMU_ENDEM */
5090 #define _CMU_LFRCOCTRL_ENDEM_DEFAULT                      0x00000001UL                                /**< Mode DEFAULT for CMU_LFRCOCTRL */
5091 #define CMU_LFRCOCTRL_ENDEM_DEFAULT                       (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18)        /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
5092 #define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT                   20                                          /**< Shift value for CMU_VREFUPDATE */
5093 #define _CMU_LFRCOCTRL_VREFUPDATE_MASK                    0x300000UL                                  /**< Bit mask for CMU_VREFUPDATE */
5094 #define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES                0x00000000UL                                /**< Mode 32CYCLES for CMU_LFRCOCTRL */
5095 #define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT                 0x00000001UL                                /**< Mode DEFAULT for CMU_LFRCOCTRL */
5096 #define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES                0x00000001UL                                /**< Mode 64CYCLES for CMU_LFRCOCTRL */
5097 #define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES               0x00000002UL                                /**< Mode 128CYCLES for CMU_LFRCOCTRL */
5098 #define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES               0x00000003UL                                /**< Mode 256CYCLES for CMU_LFRCOCTRL */
5099 #define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES                 (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20)  /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */
5100 #define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT                  (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20)   /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
5101 #define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES                 (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20)  /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */
5102 #define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES                (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */
5103 #define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES                (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */
5104 #define _CMU_LFRCOCTRL_TIMEOUT_SHIFT                      24                                          /**< Shift value for CMU_TIMEOUT */
5105 #define _CMU_LFRCOCTRL_TIMEOUT_MASK                       0x3000000UL                                 /**< Bit mask for CMU_TIMEOUT */
5106 #define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES                    0x00000000UL                                /**< Mode 2CYCLES for CMU_LFRCOCTRL */
5107 #define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT                    0x00000001UL                                /**< Mode DEFAULT for CMU_LFRCOCTRL */
5108 #define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES                   0x00000001UL                                /**< Mode 16CYCLES for CMU_LFRCOCTRL */
5109 #define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES                   0x00000002UL                                /**< Mode 32CYCLES for CMU_LFRCOCTRL */
5110 #define CMU_LFRCOCTRL_TIMEOUT_2CYCLES                     (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24)      /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */
5111 #define CMU_LFRCOCTRL_TIMEOUT_DEFAULT                     (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24)      /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
5112 #define CMU_LFRCOCTRL_TIMEOUT_16CYCLES                    (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24)     /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */
5113 #define CMU_LFRCOCTRL_TIMEOUT_32CYCLES                    (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24)     /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */
5114 #define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT                   28                                          /**< Shift value for CMU_GMCCURTUNE */
5115 #define _CMU_LFRCOCTRL_GMCCURTUNE_MASK                    0xF0000000UL                                /**< Bit mask for CMU_GMCCURTUNE */
5116 #define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT                 0x00000008UL                                /**< Mode DEFAULT for CMU_LFRCOCTRL */
5117 #define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT                  (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28)   /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
5118 
5119 /* Bit fields for CMU HFXOCTRL */
5120 #define _CMU_HFXOCTRL_RESETVALUE                          0x00000008UL                                     /**< Default value for CMU_HFXOCTRL */
5121 #define _CMU_HFXOCTRL_MASK                                0x3700003BUL                                     /**< Mask for CMU_HFXOCTRL */
5122 #define _CMU_HFXOCTRL_MODE_SHIFT                          0                                                /**< Shift value for CMU_MODE */
5123 #define _CMU_HFXOCTRL_MODE_MASK                           0x3UL                                            /**< Bit mask for CMU_MODE */
5124 #define _CMU_HFXOCTRL_MODE_DEFAULT                        0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
5125 #define _CMU_HFXOCTRL_MODE_XTAL                           0x00000000UL                                     /**< Mode XTAL for CMU_HFXOCTRL */
5126 #define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK                    0x00000001UL                                     /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */
5127 #define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK                    0x00000002UL                                     /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */
5128 #define _CMU_HFXOCTRL_MODE_DIGEXTCLK                      0x00000003UL                                     /**< Mode DIGEXTCLK for CMU_HFXOCTRL */
5129 #define CMU_HFXOCTRL_MODE_DEFAULT                         (_CMU_HFXOCTRL_MODE_DEFAULT << 0)                /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
5130 #define CMU_HFXOCTRL_MODE_XTAL                            (_CMU_HFXOCTRL_MODE_XTAL << 0)                   /**< Shifted mode XTAL for CMU_HFXOCTRL */
5131 #define CMU_HFXOCTRL_MODE_ACBUFEXTCLK                     (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0)            /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */
5132 #define CMU_HFXOCTRL_MODE_DCBUFEXTCLK                     (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0)            /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */
5133 #define CMU_HFXOCTRL_MODE_DIGEXTCLK                       (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0)              /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */
5134 #define CMU_HFXOCTRL_HFXOX2EN                             (0x1UL << 3)                                     /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */
5135 #define _CMU_HFXOCTRL_HFXOX2EN_SHIFT                      3                                                /**< Shift value for CMU_HFXOX2EN */
5136 #define _CMU_HFXOCTRL_HFXOX2EN_MASK                       0x8UL                                            /**< Bit mask for CMU_HFXOX2EN */
5137 #define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT                    0x00000001UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
5138 #define CMU_HFXOCTRL_HFXOX2EN_DEFAULT                     (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3)            /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
5139 #define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT                   4                                                /**< Shift value for CMU_PEAKDETMODE */
5140 #define _CMU_HFXOCTRL_PEAKDETMODE_MASK                    0x30UL                                           /**< Bit mask for CMU_PEAKDETMODE */
5141 #define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT                 0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
5142 #define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD                 0x00000000UL                                     /**< Mode ONCECMD for CMU_HFXOCTRL */
5143 #define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD                 0x00000001UL                                     /**< Mode AUTOCMD for CMU_HFXOCTRL */
5144 #define _CMU_HFXOCTRL_PEAKDETMODE_CMD                     0x00000002UL                                     /**< Mode CMD for CMU_HFXOCTRL */
5145 #define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL                  0x00000003UL                                     /**< Mode MANUAL for CMU_HFXOCTRL */
5146 #define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT                  (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4)         /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
5147 #define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD                  (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4)         /**< Shifted mode ONCECMD for CMU_HFXOCTRL */
5148 #define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD                  (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4)         /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */
5149 #define CMU_HFXOCTRL_PEAKDETMODE_CMD                      (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4)             /**< Shifted mode CMD for CMU_HFXOCTRL */
5150 #define CMU_HFXOCTRL_PEAKDETMODE_MANUAL                   (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4)          /**< Shifted mode MANUAL for CMU_HFXOCTRL */
5151 #define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT                     24                                               /**< Shift value for CMU_LFTIMEOUT */
5152 #define _CMU_HFXOCTRL_LFTIMEOUT_MASK                      0x7000000UL                                      /**< Bit mask for CMU_LFTIMEOUT */
5153 #define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT                   0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
5154 #define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES                   0x00000000UL                                     /**< Mode 0CYCLES for CMU_HFXOCTRL */
5155 #define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES                   0x00000001UL                                     /**< Mode 2CYCLES for CMU_HFXOCTRL */
5156 #define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES                   0x00000002UL                                     /**< Mode 4CYCLES for CMU_HFXOCTRL */
5157 #define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES                  0x00000003UL                                     /**< Mode 16CYCLES for CMU_HFXOCTRL */
5158 #define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES                  0x00000004UL                                     /**< Mode 32CYCLES for CMU_HFXOCTRL */
5159 #define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES                  0x00000005UL                                     /**< Mode 64CYCLES for CMU_HFXOCTRL */
5160 #define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES                  0x00000006UL                                     /**< Mode 1KCYCLES for CMU_HFXOCTRL */
5161 #define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES                  0x00000007UL                                     /**< Mode 4KCYCLES for CMU_HFXOCTRL */
5162 #define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT                    (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24)          /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
5163 #define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES                    (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24)          /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */
5164 #define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES                    (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24)          /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */
5165 #define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES                    (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24)          /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */
5166 #define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES                   (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24)         /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */
5167 #define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES                   (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24)         /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */
5168 #define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES                   (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24)         /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */
5169 #define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES                   (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24)         /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */
5170 #define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES                   (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24)         /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */
5171 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1                      (0x1UL << 28)                                    /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */
5172 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT               28                                               /**< Shift value for CMU_AUTOSTARTEM0EM1 */
5173 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK                0x10000000UL                                     /**< Bit mask for CMU_AUTOSTARTEM0EM1 */
5174 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT             0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
5175 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT              (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28)    /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
5176 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1                   (0x1UL << 29)                                    /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */
5177 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT            29                                               /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */
5178 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK             0x20000000UL                                     /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */
5179 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT          0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOCTRL */
5180 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT           (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */
5181 
5182 /* Bit fields for CMU HFXOCTRL1 */
5183 #define _CMU_HFXOCTRL1_RESETVALUE                         0x00002000UL                              /**< Default value for CMU_HFXOCTRL1 */
5184 #define _CMU_HFXOCTRL1_MASK                               0x00007000UL                              /**< Mask for CMU_HFXOCTRL1 */
5185 #define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT                   12                                        /**< Shift value for CMU_PEAKDETTHR */
5186 #define _CMU_HFXOCTRL1_PEAKDETTHR_MASK                    0x7000UL                                  /**< Bit mask for CMU_PEAKDETTHR */
5187 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR0                    0x00000000UL                              /**< Mode THR0 for CMU_HFXOCTRL1 */
5188 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR1                    0x00000001UL                              /**< Mode THR1 for CMU_HFXOCTRL1 */
5189 #define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT                 0x00000002UL                              /**< Mode DEFAULT for CMU_HFXOCTRL1 */
5190 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR2                    0x00000002UL                              /**< Mode THR2 for CMU_HFXOCTRL1 */
5191 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR3                    0x00000003UL                              /**< Mode THR3 for CMU_HFXOCTRL1 */
5192 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR4                    0x00000004UL                              /**< Mode THR4 for CMU_HFXOCTRL1 */
5193 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR5                    0x00000005UL                              /**< Mode THR5 for CMU_HFXOCTRL1 */
5194 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR6                    0x00000006UL                              /**< Mode THR6 for CMU_HFXOCTRL1 */
5195 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR7                    0x00000007UL                              /**< Mode THR7 for CMU_HFXOCTRL1 */
5196 #define CMU_HFXOCTRL1_PEAKDETTHR_THR0                     (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12)    /**< Shifted mode THR0 for CMU_HFXOCTRL1 */
5197 #define CMU_HFXOCTRL1_PEAKDETTHR_THR1                     (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12)    /**< Shifted mode THR1 for CMU_HFXOCTRL1 */
5198 #define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT                  (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */
5199 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2                     (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12)    /**< Shifted mode THR2 for CMU_HFXOCTRL1 */
5200 #define CMU_HFXOCTRL1_PEAKDETTHR_THR3                     (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12)    /**< Shifted mode THR3 for CMU_HFXOCTRL1 */
5201 #define CMU_HFXOCTRL1_PEAKDETTHR_THR4                     (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12)    /**< Shifted mode THR4 for CMU_HFXOCTRL1 */
5202 #define CMU_HFXOCTRL1_PEAKDETTHR_THR5                     (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12)    /**< Shifted mode THR5 for CMU_HFXOCTRL1 */
5203 #define CMU_HFXOCTRL1_PEAKDETTHR_THR6                     (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12)    /**< Shifted mode THR6 for CMU_HFXOCTRL1 */
5204 #define CMU_HFXOCTRL1_PEAKDETTHR_THR7                     (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12)    /**< Shifted mode THR7 for CMU_HFXOCTRL1 */
5205 
5206 /* Bit fields for CMU HFXOSTARTUPCTRL */
5207 #define _CMU_HFXOSTARTUPCTRL_RESETVALUE                   0x00000600UL                                     /**< Default value for CMU_HFXOSTARTUPCTRL */
5208 #define _CMU_HFXOSTARTUPCTRL_MASK                         0x000FFFFFUL                                     /**< Mask for CMU_HFXOSTARTUPCTRL */
5209 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT           0                                                /**< Shift value for CMU_IBTRIMXOCORE */
5210 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK            0x7FFUL                                          /**< Bit mask for CMU_IBTRIMXOCORE */
5211 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT         0x00000600UL                                     /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
5212 #define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT          (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
5213 #define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT                  11                                               /**< Shift value for CMU_CTUNE */
5214 #define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK                   0xFF800UL                                        /**< Bit mask for CMU_CTUNE */
5215 #define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT                0x00000000UL                                     /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */
5216 #define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT                 (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11)       /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */
5217 
5218 /* Bit fields for CMU HFXOSTEADYSTATECTRL */
5219 #define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE               0x08000100UL                                         /**< Default value for CMU_HFXOSTEADYSTATECTRL */
5220 #define _CMU_HFXOSTEADYSTATECTRL_MASK                     0x0C0FFFFFUL                                         /**< Mask for CMU_HFXOSTEADYSTATECTRL */
5221 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT       0                                                    /**< Shift value for CMU_IBTRIMXOCORE */
5222 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK        0x7FFUL                                              /**< Bit mask for CMU_IBTRIMXOCORE */
5223 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT     0x00000100UL                                         /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
5224 #define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT      (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
5225 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT              11                                                   /**< Shift value for CMU_CTUNE */
5226 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK               0xFF800UL                                            /**< Bit mask for CMU_CTUNE */
5227 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT            0x00000000UL                                         /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
5228 #define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT             (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11)       /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
5229 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN                 (0x1UL << 26)                                        /**< Enables Oscillator Peak Detectors */
5230 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT          26                                                   /**< Shift value for CMU_PEAKDETEN */
5231 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK           0x4000000UL                                          /**< Bit mask for CMU_PEAKDETEN */
5232 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT        0x00000000UL                                         /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
5233 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT         (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26)   /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
5234 #define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN                 (0x1UL << 27)                                        /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */
5235 #define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT          27                                                   /**< Shift value for CMU_PEAKMONEN */
5236 #define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK           0x8000000UL                                          /**< Bit mask for CMU_PEAKMONEN */
5237 #define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT        0x00000001UL                                         /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
5238 #define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT         (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27)   /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */
5239 
5240 /* Bit fields for CMU HFXOTIMEOUTCTRL */
5241 #define _CMU_HFXOTIMEOUTCTRL_RESETVALUE                   0x0000D08EUL                                           /**< Default value for CMU_HFXOTIMEOUTCTRL */
5242 #define _CMU_HFXOTIMEOUTCTRL_MASK                         0x0000F0FFUL                                           /**< Mask for CMU_HFXOTIMEOUTCTRL */
5243 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT         0                                                      /**< Shift value for CMU_STARTUPTIMEOUT */
5244 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK          0xFUL                                                  /**< Bit mask for CMU_STARTUPTIMEOUT */
5245 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES       0x00000000UL                                           /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
5246 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES       0x00000001UL                                           /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
5247 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES      0x00000002UL                                           /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
5248 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES      0x00000003UL                                           /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
5249 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES      0x00000004UL                                           /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */
5250 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES     0x00000005UL                                           /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */
5251 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES     0x00000006UL                                           /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
5252 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES      0x00000007UL                                           /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
5253 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES      0x00000008UL                                           /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
5254 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES      0x00000009UL                                           /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
5255 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES      0x0000000AUL                                           /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
5256 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES     0x0000000BUL                                           /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
5257 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES     0x0000000CUL                                           /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
5258 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES     0x0000000DUL                                           /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */
5259 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT       0x0000000EUL                                           /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
5260 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES    0x0000000EUL                                           /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */
5261 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES        (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0)     /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
5262 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES        (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0)     /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
5263 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES       (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0)    /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
5264 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES       (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0)    /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
5265 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES       (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0)    /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */
5266 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES      (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0)   /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */
5267 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES      (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0)   /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
5268 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES       (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0)    /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
5269 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES       (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0)    /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
5270 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES       (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0)    /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
5271 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES       (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0)    /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
5272 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES      (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0)   /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
5273 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES      (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0)   /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
5274 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES      (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0)   /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */
5275 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT        (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
5276 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES     (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0)  /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */
5277 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT          4                                                      /**< Shift value for CMU_STEADYTIMEOUT */
5278 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK           0xF0UL                                                 /**< Bit mask for CMU_STEADYTIMEOUT */
5279 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES        0x00000000UL                                           /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
5280 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES        0x00000001UL                                           /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
5281 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES       0x00000002UL                                           /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
5282 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES       0x00000003UL                                           /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
5283 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES       0x00000004UL                                           /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */
5284 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES      0x00000005UL                                           /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */
5285 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES      0x00000006UL                                           /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
5286 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES       0x00000007UL                                           /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
5287 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT        0x00000008UL                                           /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
5288 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES       0x00000008UL                                           /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
5289 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES       0x00000009UL                                           /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
5290 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES       0x0000000AUL                                           /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
5291 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES      0x0000000BUL                                           /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
5292 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES      0x0000000CUL                                           /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
5293 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES      0x0000000DUL                                           /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */
5294 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES     0x0000000EUL                                           /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */
5295 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES         (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4)      /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
5296 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES         (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4)      /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
5297 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES        (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4)     /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
5298 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES        (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4)     /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
5299 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES        (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4)     /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */
5300 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES       (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4)    /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */
5301 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES       (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4)    /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
5302 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES        (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4)     /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
5303 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT         (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4)      /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
5304 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES        (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4)     /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
5305 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES        (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4)     /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
5306 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES        (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4)     /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
5307 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES       (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4)    /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
5308 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES       (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4)    /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
5309 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES       (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4)    /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */
5310 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES      (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4)   /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */
5311 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT         12                                                     /**< Shift value for CMU_PEAKDETTIMEOUT */
5312 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK          0xF000UL                                               /**< Bit mask for CMU_PEAKDETTIMEOUT */
5313 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES       0x00000000UL                                           /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
5314 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES       0x00000001UL                                           /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
5315 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES      0x00000002UL                                           /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
5316 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES      0x00000003UL                                           /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
5317 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES      0x00000004UL                                           /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */
5318 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES     0x00000005UL                                           /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */
5319 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES     0x00000006UL                                           /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
5320 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES      0x00000007UL                                           /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
5321 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES      0x00000008UL                                           /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
5322 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES      0x00000009UL                                           /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
5323 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES      0x0000000AUL                                           /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
5324 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES     0x0000000BUL                                           /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
5325 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES     0x0000000CUL                                           /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
5326 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT       0x0000000DUL                                           /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
5327 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES     0x0000000DUL                                           /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */
5328 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES    0x0000000EUL                                           /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */
5329 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES        (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12)    /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */
5330 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES        (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12)    /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */
5331 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES       (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12)   /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */
5332 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES       (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12)   /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */
5333 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES       (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12)   /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */
5334 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES      (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12)  /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */
5335 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES      (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12)  /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */
5336 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES       (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12)   /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */
5337 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES       (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12)   /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */
5338 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES       (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12)   /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */
5339 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES       (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12)   /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */
5340 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES      (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12)  /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */
5341 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES      (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12)  /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */
5342 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT        (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12)    /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */
5343 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES      (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12)  /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */
5344 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES     (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */
5345 
5346 /* Bit fields for CMU LFXOCTRL */
5347 #define _CMU_LFXOCTRL_RESETVALUE                          0x07009000UL                            /**< Default value for CMU_LFXOCTRL */
5348 #define _CMU_LFXOCTRL_MASK                                0x0713DB7FUL                            /**< Mask for CMU_LFXOCTRL */
5349 #define _CMU_LFXOCTRL_TUNING_SHIFT                        0                                       /**< Shift value for CMU_TUNING */
5350 #define _CMU_LFXOCTRL_TUNING_MASK                         0x7FUL                                  /**< Bit mask for CMU_TUNING */
5351 #define _CMU_LFXOCTRL_TUNING_DEFAULT                      0x00000000UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
5352 #define CMU_LFXOCTRL_TUNING_DEFAULT                       (_CMU_LFXOCTRL_TUNING_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
5353 #define _CMU_LFXOCTRL_MODE_SHIFT                          8                                       /**< Shift value for CMU_MODE */
5354 #define _CMU_LFXOCTRL_MODE_MASK                           0x300UL                                 /**< Bit mask for CMU_MODE */
5355 #define _CMU_LFXOCTRL_MODE_DEFAULT                        0x00000000UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
5356 #define _CMU_LFXOCTRL_MODE_XTAL                           0x00000000UL                            /**< Mode XTAL for CMU_LFXOCTRL */
5357 #define _CMU_LFXOCTRL_MODE_BUFEXTCLK                      0x00000001UL                            /**< Mode BUFEXTCLK for CMU_LFXOCTRL */
5358 #define _CMU_LFXOCTRL_MODE_DIGEXTCLK                      0x00000002UL                            /**< Mode DIGEXTCLK for CMU_LFXOCTRL */
5359 #define CMU_LFXOCTRL_MODE_DEFAULT                         (_CMU_LFXOCTRL_MODE_DEFAULT << 8)       /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
5360 #define CMU_LFXOCTRL_MODE_XTAL                            (_CMU_LFXOCTRL_MODE_XTAL << 8)          /**< Shifted mode XTAL for CMU_LFXOCTRL */
5361 #define CMU_LFXOCTRL_MODE_BUFEXTCLK                       (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8)     /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */
5362 #define CMU_LFXOCTRL_MODE_DIGEXTCLK                       (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8)     /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */
5363 #define _CMU_LFXOCTRL_GAIN_SHIFT                          11                                      /**< Shift value for CMU_GAIN */
5364 #define _CMU_LFXOCTRL_GAIN_MASK                           0x1800UL                                /**< Bit mask for CMU_GAIN */
5365 #define _CMU_LFXOCTRL_GAIN_DEFAULT                        0x00000002UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
5366 #define CMU_LFXOCTRL_GAIN_DEFAULT                         (_CMU_LFXOCTRL_GAIN_DEFAULT << 11)      /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
5367 #define CMU_LFXOCTRL_HIGHAMPL                             (0x1UL << 14)                           /**< LFXO High XTAL Oscillation Amplitude Enable */
5368 #define _CMU_LFXOCTRL_HIGHAMPL_SHIFT                      14                                      /**< Shift value for CMU_HIGHAMPL */
5369 #define _CMU_LFXOCTRL_HIGHAMPL_MASK                       0x4000UL                                /**< Bit mask for CMU_HIGHAMPL */
5370 #define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT                    0x00000000UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
5371 #define CMU_LFXOCTRL_HIGHAMPL_DEFAULT                     (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14)  /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
5372 #define CMU_LFXOCTRL_AGC                                  (0x1UL << 15)                           /**< LFXO AGC Enable */
5373 #define _CMU_LFXOCTRL_AGC_SHIFT                           15                                      /**< Shift value for CMU_AGC */
5374 #define _CMU_LFXOCTRL_AGC_MASK                            0x8000UL                                /**< Bit mask for CMU_AGC */
5375 #define _CMU_LFXOCTRL_AGC_DEFAULT                         0x00000001UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
5376 #define CMU_LFXOCTRL_AGC_DEFAULT                          (_CMU_LFXOCTRL_AGC_DEFAULT << 15)       /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
5377 #define _CMU_LFXOCTRL_CUR_SHIFT                           16                                      /**< Shift value for CMU_CUR */
5378 #define _CMU_LFXOCTRL_CUR_MASK                            0x30000UL                               /**< Bit mask for CMU_CUR */
5379 #define _CMU_LFXOCTRL_CUR_DEFAULT                         0x00000000UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
5380 #define CMU_LFXOCTRL_CUR_DEFAULT                          (_CMU_LFXOCTRL_CUR_DEFAULT << 16)       /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
5381 #define CMU_LFXOCTRL_BUFCUR                               (0x1UL << 20)                           /**< LFXO Buffer Bias Current */
5382 #define _CMU_LFXOCTRL_BUFCUR_SHIFT                        20                                      /**< Shift value for CMU_BUFCUR */
5383 #define _CMU_LFXOCTRL_BUFCUR_MASK                         0x100000UL                              /**< Bit mask for CMU_BUFCUR */
5384 #define _CMU_LFXOCTRL_BUFCUR_DEFAULT                      0x00000000UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
5385 #define CMU_LFXOCTRL_BUFCUR_DEFAULT                       (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20)    /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
5386 #define _CMU_LFXOCTRL_TIMEOUT_SHIFT                       24                                      /**< Shift value for CMU_TIMEOUT */
5387 #define _CMU_LFXOCTRL_TIMEOUT_MASK                        0x7000000UL                             /**< Bit mask for CMU_TIMEOUT */
5388 #define _CMU_LFXOCTRL_TIMEOUT_2CYCLES                     0x00000000UL                            /**< Mode 2CYCLES for CMU_LFXOCTRL */
5389 #define _CMU_LFXOCTRL_TIMEOUT_256CYCLES                   0x00000001UL                            /**< Mode 256CYCLES for CMU_LFXOCTRL */
5390 #define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES                    0x00000002UL                            /**< Mode 1KCYCLES for CMU_LFXOCTRL */
5391 #define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES                    0x00000003UL                            /**< Mode 2KCYCLES for CMU_LFXOCTRL */
5392 #define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES                    0x00000004UL                            /**< Mode 4KCYCLES for CMU_LFXOCTRL */
5393 #define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES                    0x00000005UL                            /**< Mode 8KCYCLES for CMU_LFXOCTRL */
5394 #define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES                   0x00000006UL                            /**< Mode 16KCYCLES for CMU_LFXOCTRL */
5395 #define _CMU_LFXOCTRL_TIMEOUT_DEFAULT                     0x00000007UL                            /**< Mode DEFAULT for CMU_LFXOCTRL */
5396 #define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES                   0x00000007UL                            /**< Mode 32KCYCLES for CMU_LFXOCTRL */
5397 #define CMU_LFXOCTRL_TIMEOUT_2CYCLES                      (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24)   /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */
5398 #define CMU_LFXOCTRL_TIMEOUT_256CYCLES                    (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */
5399 #define CMU_LFXOCTRL_TIMEOUT_1KCYCLES                     (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24)  /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */
5400 #define CMU_LFXOCTRL_TIMEOUT_2KCYCLES                     (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24)  /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */
5401 #define CMU_LFXOCTRL_TIMEOUT_4KCYCLES                     (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24)  /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */
5402 #define CMU_LFXOCTRL_TIMEOUT_8KCYCLES                     (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24)  /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */
5403 #define CMU_LFXOCTRL_TIMEOUT_16KCYCLES                    (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */
5404 #define CMU_LFXOCTRL_TIMEOUT_DEFAULT                      (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24)   /**< Shifted mode DEFAULT for CMU_LFXOCTRL */
5405 #define CMU_LFXOCTRL_TIMEOUT_32KCYCLES                    (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */
5406 
5407 /* Bit fields for CMU DPLLCTRL */
5408 #define _CMU_DPLLCTRL_RESETVALUE                          0x00000000UL                             /**< Default value for CMU_DPLLCTRL */
5409 #define _CMU_DPLLCTRL_MASK                                0x0000005FUL                             /**< Mask for CMU_DPLLCTRL */
5410 #define CMU_DPLLCTRL_MODE                                 (0x1UL << 0)                             /**< Operating Mode Control */
5411 #define _CMU_DPLLCTRL_MODE_SHIFT                          0                                        /**< Shift value for CMU_MODE */
5412 #define _CMU_DPLLCTRL_MODE_MASK                           0x1UL                                    /**< Bit mask for CMU_MODE */
5413 #define _CMU_DPLLCTRL_MODE_DEFAULT                        0x00000000UL                             /**< Mode DEFAULT for CMU_DPLLCTRL */
5414 #define _CMU_DPLLCTRL_MODE_FREQLL                         0x00000000UL                             /**< Mode FREQLL for CMU_DPLLCTRL */
5415 #define _CMU_DPLLCTRL_MODE_PHASELL                        0x00000001UL                             /**< Mode PHASELL for CMU_DPLLCTRL */
5416 #define CMU_DPLLCTRL_MODE_DEFAULT                         (_CMU_DPLLCTRL_MODE_DEFAULT << 0)        /**< Shifted mode DEFAULT for CMU_DPLLCTRL */
5417 #define CMU_DPLLCTRL_MODE_FREQLL                          (_CMU_DPLLCTRL_MODE_FREQLL << 0)         /**< Shifted mode FREQLL for CMU_DPLLCTRL */
5418 #define CMU_DPLLCTRL_MODE_PHASELL                         (_CMU_DPLLCTRL_MODE_PHASELL << 0)        /**< Shifted mode PHASELL for CMU_DPLLCTRL */
5419 #define CMU_DPLLCTRL_EDGESEL                              (0x1UL << 1)                             /**< Reference Edge Select */
5420 #define _CMU_DPLLCTRL_EDGESEL_SHIFT                       1                                        /**< Shift value for CMU_EDGESEL */
5421 #define _CMU_DPLLCTRL_EDGESEL_MASK                        0x2UL                                    /**< Bit mask for CMU_EDGESEL */
5422 #define _CMU_DPLLCTRL_EDGESEL_DEFAULT                     0x00000000UL                             /**< Mode DEFAULT for CMU_DPLLCTRL */
5423 #define _CMU_DPLLCTRL_EDGESEL_FALL                        0x00000000UL                             /**< Mode FALL for CMU_DPLLCTRL */
5424 #define _CMU_DPLLCTRL_EDGESEL_RISE                        0x00000001UL                             /**< Mode RISE for CMU_DPLLCTRL */
5425 #define CMU_DPLLCTRL_EDGESEL_DEFAULT                      (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1)     /**< Shifted mode DEFAULT for CMU_DPLLCTRL */
5426 #define CMU_DPLLCTRL_EDGESEL_FALL                         (_CMU_DPLLCTRL_EDGESEL_FALL << 1)        /**< Shifted mode FALL for CMU_DPLLCTRL */
5427 #define CMU_DPLLCTRL_EDGESEL_RISE                         (_CMU_DPLLCTRL_EDGESEL_RISE << 1)        /**< Shifted mode RISE for CMU_DPLLCTRL */
5428 #define CMU_DPLLCTRL_AUTORECOVER                          (0x1UL << 2)                             /**< Automatic Recovery Ctrl */
5429 #define _CMU_DPLLCTRL_AUTORECOVER_SHIFT                   2                                        /**< Shift value for CMU_AUTORECOVER */
5430 #define _CMU_DPLLCTRL_AUTORECOVER_MASK                    0x4UL                                    /**< Bit mask for CMU_AUTORECOVER */
5431 #define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for CMU_DPLLCTRL */
5432 #define CMU_DPLLCTRL_AUTORECOVER_DEFAULT                  (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */
5433 #define _CMU_DPLLCTRL_REFSEL_SHIFT                        3                                        /**< Shift value for CMU_REFSEL */
5434 #define _CMU_DPLLCTRL_REFSEL_MASK                         0x18UL                                   /**< Bit mask for CMU_REFSEL */
5435 #define _CMU_DPLLCTRL_REFSEL_DEFAULT                      0x00000000UL                             /**< Mode DEFAULT for CMU_DPLLCTRL */
5436 #define _CMU_DPLLCTRL_REFSEL_HFXO                         0x00000000UL                             /**< Mode HFXO for CMU_DPLLCTRL */
5437 #define _CMU_DPLLCTRL_REFSEL_LFXO                         0x00000001UL                             /**< Mode LFXO for CMU_DPLLCTRL */
5438 #define _CMU_DPLLCTRL_REFSEL_USHFRCO                      0x00000002UL                             /**< Mode USHFRCO for CMU_DPLLCTRL */
5439 #define _CMU_DPLLCTRL_REFSEL_CLKIN0                       0x00000003UL                             /**< Mode CLKIN0 for CMU_DPLLCTRL */
5440 #define CMU_DPLLCTRL_REFSEL_DEFAULT                       (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3)      /**< Shifted mode DEFAULT for CMU_DPLLCTRL */
5441 #define CMU_DPLLCTRL_REFSEL_HFXO                          (_CMU_DPLLCTRL_REFSEL_HFXO << 3)         /**< Shifted mode HFXO for CMU_DPLLCTRL */
5442 #define CMU_DPLLCTRL_REFSEL_LFXO                          (_CMU_DPLLCTRL_REFSEL_LFXO << 3)         /**< Shifted mode LFXO for CMU_DPLLCTRL */
5443 #define CMU_DPLLCTRL_REFSEL_USHFRCO                       (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3)      /**< Shifted mode USHFRCO for CMU_DPLLCTRL */
5444 #define CMU_DPLLCTRL_REFSEL_CLKIN0                        (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3)       /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */
5445 #define CMU_DPLLCTRL_DITHEN                               (0x1UL << 6)                             /**< Dither Enable Control */
5446 #define _CMU_DPLLCTRL_DITHEN_SHIFT                        6                                        /**< Shift value for CMU_DITHEN */
5447 #define _CMU_DPLLCTRL_DITHEN_MASK                         0x40UL                                   /**< Bit mask for CMU_DITHEN */
5448 #define _CMU_DPLLCTRL_DITHEN_DEFAULT                      0x00000000UL                             /**< Mode DEFAULT for CMU_DPLLCTRL */
5449 #define CMU_DPLLCTRL_DITHEN_DEFAULT                       (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6)      /**< Shifted mode DEFAULT for CMU_DPLLCTRL */
5450 
5451 /* Bit fields for CMU DPLLCTRL1 */
5452 #define _CMU_DPLLCTRL1_RESETVALUE                         0x00000000UL                     /**< Default value for CMU_DPLLCTRL1 */
5453 #define _CMU_DPLLCTRL1_MASK                               0x0FFF0FFFUL                     /**< Mask for CMU_DPLLCTRL1 */
5454 #define _CMU_DPLLCTRL1_M_SHIFT                            0                                /**< Shift value for CMU_M */
5455 #define _CMU_DPLLCTRL1_M_MASK                             0xFFFUL                          /**< Bit mask for CMU_M */
5456 #define _CMU_DPLLCTRL1_M_DEFAULT                          0x00000000UL                     /**< Mode DEFAULT for CMU_DPLLCTRL1 */
5457 #define CMU_DPLLCTRL1_M_DEFAULT                           (_CMU_DPLLCTRL1_M_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */
5458 #define _CMU_DPLLCTRL1_N_SHIFT                            16                               /**< Shift value for CMU_N */
5459 #define _CMU_DPLLCTRL1_N_MASK                             0xFFF0000UL                      /**< Bit mask for CMU_N */
5460 #define _CMU_DPLLCTRL1_N_DEFAULT                          0x00000000UL                     /**< Mode DEFAULT for CMU_DPLLCTRL1 */
5461 #define CMU_DPLLCTRL1_N_DEFAULT                           (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */
5462 
5463 /* Bit fields for CMU CALCTRL */
5464 #define _CMU_CALCTRL_RESETVALUE                           0x00000000UL                            /**< Default value for CMU_CALCTRL */
5465 #define _CMU_CALCTRL_MASK                                 0x0F0F01F7UL                            /**< Mask for CMU_CALCTRL */
5466 #define _CMU_CALCTRL_UPSEL_SHIFT                          0                                       /**< Shift value for CMU_UPSEL */
5467 #define _CMU_CALCTRL_UPSEL_MASK                           0x7UL                                   /**< Bit mask for CMU_UPSEL */
5468 #define _CMU_CALCTRL_UPSEL_DEFAULT                        0x00000000UL                            /**< Mode DEFAULT for CMU_CALCTRL */
5469 #define _CMU_CALCTRL_UPSEL_HFXO                           0x00000000UL                            /**< Mode HFXO for CMU_CALCTRL */
5470 #define _CMU_CALCTRL_UPSEL_LFXO                           0x00000001UL                            /**< Mode LFXO for CMU_CALCTRL */
5471 #define _CMU_CALCTRL_UPSEL_HFRCO                          0x00000002UL                            /**< Mode HFRCO for CMU_CALCTRL */
5472 #define _CMU_CALCTRL_UPSEL_LFRCO                          0x00000003UL                            /**< Mode LFRCO for CMU_CALCTRL */
5473 #define _CMU_CALCTRL_UPSEL_AUXHFRCO                       0x00000004UL                            /**< Mode AUXHFRCO for CMU_CALCTRL */
5474 #define _CMU_CALCTRL_UPSEL_PRS                            0x00000005UL                            /**< Mode PRS for CMU_CALCTRL */
5475 #define _CMU_CALCTRL_UPSEL_USHFRCO                        0x00000007UL                            /**< Mode USHFRCO for CMU_CALCTRL */
5476 #define CMU_CALCTRL_UPSEL_DEFAULT                         (_CMU_CALCTRL_UPSEL_DEFAULT << 0)       /**< Shifted mode DEFAULT for CMU_CALCTRL */
5477 #define CMU_CALCTRL_UPSEL_HFXO                            (_CMU_CALCTRL_UPSEL_HFXO << 0)          /**< Shifted mode HFXO for CMU_CALCTRL */
5478 #define CMU_CALCTRL_UPSEL_LFXO                            (_CMU_CALCTRL_UPSEL_LFXO << 0)          /**< Shifted mode LFXO for CMU_CALCTRL */
5479 #define CMU_CALCTRL_UPSEL_HFRCO                           (_CMU_CALCTRL_UPSEL_HFRCO << 0)         /**< Shifted mode HFRCO for CMU_CALCTRL */
5480 #define CMU_CALCTRL_UPSEL_LFRCO                           (_CMU_CALCTRL_UPSEL_LFRCO << 0)         /**< Shifted mode LFRCO for CMU_CALCTRL */
5481 #define CMU_CALCTRL_UPSEL_AUXHFRCO                        (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)      /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
5482 #define CMU_CALCTRL_UPSEL_PRS                             (_CMU_CALCTRL_UPSEL_PRS << 0)           /**< Shifted mode PRS for CMU_CALCTRL */
5483 #define CMU_CALCTRL_UPSEL_USHFRCO                         (_CMU_CALCTRL_UPSEL_USHFRCO << 0)       /**< Shifted mode USHFRCO for CMU_CALCTRL */
5484 #define _CMU_CALCTRL_DOWNSEL_SHIFT                        4                                       /**< Shift value for CMU_DOWNSEL */
5485 #define _CMU_CALCTRL_DOWNSEL_MASK                         0xF0UL                                  /**< Bit mask for CMU_DOWNSEL */
5486 #define _CMU_CALCTRL_DOWNSEL_DEFAULT                      0x00000000UL                            /**< Mode DEFAULT for CMU_CALCTRL */
5487 #define _CMU_CALCTRL_DOWNSEL_HFCLK                        0x00000000UL                            /**< Mode HFCLK for CMU_CALCTRL */
5488 #define _CMU_CALCTRL_DOWNSEL_HFXO                         0x00000001UL                            /**< Mode HFXO for CMU_CALCTRL */
5489 #define _CMU_CALCTRL_DOWNSEL_LFXO                         0x00000002UL                            /**< Mode LFXO for CMU_CALCTRL */
5490 #define _CMU_CALCTRL_DOWNSEL_HFRCO                        0x00000003UL                            /**< Mode HFRCO for CMU_CALCTRL */
5491 #define _CMU_CALCTRL_DOWNSEL_LFRCO                        0x00000004UL                            /**< Mode LFRCO for CMU_CALCTRL */
5492 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO                     0x00000005UL                            /**< Mode AUXHFRCO for CMU_CALCTRL */
5493 #define _CMU_CALCTRL_DOWNSEL_PRS                          0x00000006UL                            /**< Mode PRS for CMU_CALCTRL */
5494 #define _CMU_CALCTRL_DOWNSEL_USHFRCO                      0x00000008UL                            /**< Mode USHFRCO for CMU_CALCTRL */
5495 #define CMU_CALCTRL_DOWNSEL_DEFAULT                       (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4)     /**< Shifted mode DEFAULT for CMU_CALCTRL */
5496 #define CMU_CALCTRL_DOWNSEL_HFCLK                         (_CMU_CALCTRL_DOWNSEL_HFCLK << 4)       /**< Shifted mode HFCLK for CMU_CALCTRL */
5497 #define CMU_CALCTRL_DOWNSEL_HFXO                          (_CMU_CALCTRL_DOWNSEL_HFXO << 4)        /**< Shifted mode HFXO for CMU_CALCTRL */
5498 #define CMU_CALCTRL_DOWNSEL_LFXO                          (_CMU_CALCTRL_DOWNSEL_LFXO << 4)        /**< Shifted mode LFXO for CMU_CALCTRL */
5499 #define CMU_CALCTRL_DOWNSEL_HFRCO                         (_CMU_CALCTRL_DOWNSEL_HFRCO << 4)       /**< Shifted mode HFRCO for CMU_CALCTRL */
5500 #define CMU_CALCTRL_DOWNSEL_LFRCO                         (_CMU_CALCTRL_DOWNSEL_LFRCO << 4)       /**< Shifted mode LFRCO for CMU_CALCTRL */
5501 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO                      (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4)    /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
5502 #define CMU_CALCTRL_DOWNSEL_PRS                           (_CMU_CALCTRL_DOWNSEL_PRS << 4)         /**< Shifted mode PRS for CMU_CALCTRL */
5503 #define CMU_CALCTRL_DOWNSEL_USHFRCO                       (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4)     /**< Shifted mode USHFRCO for CMU_CALCTRL */
5504 #define CMU_CALCTRL_CONT                                  (0x1UL << 8)                            /**< Continuous Calibration */
5505 #define _CMU_CALCTRL_CONT_SHIFT                           8                                       /**< Shift value for CMU_CONT */
5506 #define _CMU_CALCTRL_CONT_MASK                            0x100UL                                 /**< Bit mask for CMU_CONT */
5507 #define _CMU_CALCTRL_CONT_DEFAULT                         0x00000000UL                            /**< Mode DEFAULT for CMU_CALCTRL */
5508 #define CMU_CALCTRL_CONT_DEFAULT                          (_CMU_CALCTRL_CONT_DEFAULT << 8)        /**< Shifted mode DEFAULT for CMU_CALCTRL */
5509 #define _CMU_CALCTRL_PRSUPSEL_SHIFT                       16                                      /**< Shift value for CMU_PRSUPSEL */
5510 #define _CMU_CALCTRL_PRSUPSEL_MASK                        0xF0000UL                               /**< Bit mask for CMU_PRSUPSEL */
5511 #define _CMU_CALCTRL_PRSUPSEL_DEFAULT                     0x00000000UL                            /**< Mode DEFAULT for CMU_CALCTRL */
5512 #define _CMU_CALCTRL_PRSUPSEL_PRSCH0                      0x00000000UL                            /**< Mode PRSCH0 for CMU_CALCTRL */
5513 #define _CMU_CALCTRL_PRSUPSEL_PRSCH1                      0x00000001UL                            /**< Mode PRSCH1 for CMU_CALCTRL */
5514 #define _CMU_CALCTRL_PRSUPSEL_PRSCH2                      0x00000002UL                            /**< Mode PRSCH2 for CMU_CALCTRL */
5515 #define _CMU_CALCTRL_PRSUPSEL_PRSCH3                      0x00000003UL                            /**< Mode PRSCH3 for CMU_CALCTRL */
5516 #define _CMU_CALCTRL_PRSUPSEL_PRSCH4                      0x00000004UL                            /**< Mode PRSCH4 for CMU_CALCTRL */
5517 #define _CMU_CALCTRL_PRSUPSEL_PRSCH5                      0x00000005UL                            /**< Mode PRSCH5 for CMU_CALCTRL */
5518 #define _CMU_CALCTRL_PRSUPSEL_PRSCH6                      0x00000006UL                            /**< Mode PRSCH6 for CMU_CALCTRL */
5519 #define _CMU_CALCTRL_PRSUPSEL_PRSCH7                      0x00000007UL                            /**< Mode PRSCH7 for CMU_CALCTRL */
5520 #define _CMU_CALCTRL_PRSUPSEL_PRSCH8                      0x00000008UL                            /**< Mode PRSCH8 for CMU_CALCTRL */
5521 #define _CMU_CALCTRL_PRSUPSEL_PRSCH9                      0x00000009UL                            /**< Mode PRSCH9 for CMU_CALCTRL */
5522 #define _CMU_CALCTRL_PRSUPSEL_PRSCH10                     0x0000000AUL                            /**< Mode PRSCH10 for CMU_CALCTRL */
5523 #define _CMU_CALCTRL_PRSUPSEL_PRSCH11                     0x0000000BUL                            /**< Mode PRSCH11 for CMU_CALCTRL */
5524 #define _CMU_CALCTRL_PRSUPSEL_PRSCH12                     0x0000000CUL                            /**< Mode PRSCH12 for CMU_CALCTRL */
5525 #define _CMU_CALCTRL_PRSUPSEL_PRSCH13                     0x0000000DUL                            /**< Mode PRSCH13 for CMU_CALCTRL */
5526 #define _CMU_CALCTRL_PRSUPSEL_PRSCH14                     0x0000000EUL                            /**< Mode PRSCH14 for CMU_CALCTRL */
5527 #define _CMU_CALCTRL_PRSUPSEL_PRSCH15                     0x0000000FUL                            /**< Mode PRSCH15 for CMU_CALCTRL */
5528 #define CMU_CALCTRL_PRSUPSEL_DEFAULT                      (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16)   /**< Shifted mode DEFAULT for CMU_CALCTRL */
5529 #define CMU_CALCTRL_PRSUPSEL_PRSCH0                       (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16)    /**< Shifted mode PRSCH0 for CMU_CALCTRL */
5530 #define CMU_CALCTRL_PRSUPSEL_PRSCH1                       (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16)    /**< Shifted mode PRSCH1 for CMU_CALCTRL */
5531 #define CMU_CALCTRL_PRSUPSEL_PRSCH2                       (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16)    /**< Shifted mode PRSCH2 for CMU_CALCTRL */
5532 #define CMU_CALCTRL_PRSUPSEL_PRSCH3                       (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16)    /**< Shifted mode PRSCH3 for CMU_CALCTRL */
5533 #define CMU_CALCTRL_PRSUPSEL_PRSCH4                       (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16)    /**< Shifted mode PRSCH4 for CMU_CALCTRL */
5534 #define CMU_CALCTRL_PRSUPSEL_PRSCH5                       (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16)    /**< Shifted mode PRSCH5 for CMU_CALCTRL */
5535 #define CMU_CALCTRL_PRSUPSEL_PRSCH6                       (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16)    /**< Shifted mode PRSCH6 for CMU_CALCTRL */
5536 #define CMU_CALCTRL_PRSUPSEL_PRSCH7                       (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16)    /**< Shifted mode PRSCH7 for CMU_CALCTRL */
5537 #define CMU_CALCTRL_PRSUPSEL_PRSCH8                       (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16)    /**< Shifted mode PRSCH8 for CMU_CALCTRL */
5538 #define CMU_CALCTRL_PRSUPSEL_PRSCH9                       (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16)    /**< Shifted mode PRSCH9 for CMU_CALCTRL */
5539 #define CMU_CALCTRL_PRSUPSEL_PRSCH10                      (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16)   /**< Shifted mode PRSCH10 for CMU_CALCTRL */
5540 #define CMU_CALCTRL_PRSUPSEL_PRSCH11                      (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16)   /**< Shifted mode PRSCH11 for CMU_CALCTRL */
5541 #define CMU_CALCTRL_PRSUPSEL_PRSCH12                      (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16)   /**< Shifted mode PRSCH12 for CMU_CALCTRL */
5542 #define CMU_CALCTRL_PRSUPSEL_PRSCH13                      (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16)   /**< Shifted mode PRSCH13 for CMU_CALCTRL */
5543 #define CMU_CALCTRL_PRSUPSEL_PRSCH14                      (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16)   /**< Shifted mode PRSCH14 for CMU_CALCTRL */
5544 #define CMU_CALCTRL_PRSUPSEL_PRSCH15                      (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16)   /**< Shifted mode PRSCH15 for CMU_CALCTRL */
5545 #define _CMU_CALCTRL_PRSDOWNSEL_SHIFT                     24                                      /**< Shift value for CMU_PRSDOWNSEL */
5546 #define _CMU_CALCTRL_PRSDOWNSEL_MASK                      0xF000000UL                             /**< Bit mask for CMU_PRSDOWNSEL */
5547 #define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT                   0x00000000UL                            /**< Mode DEFAULT for CMU_CALCTRL */
5548 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0                    0x00000000UL                            /**< Mode PRSCH0 for CMU_CALCTRL */
5549 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1                    0x00000001UL                            /**< Mode PRSCH1 for CMU_CALCTRL */
5550 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2                    0x00000002UL                            /**< Mode PRSCH2 for CMU_CALCTRL */
5551 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3                    0x00000003UL                            /**< Mode PRSCH3 for CMU_CALCTRL */
5552 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4                    0x00000004UL                            /**< Mode PRSCH4 for CMU_CALCTRL */
5553 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5                    0x00000005UL                            /**< Mode PRSCH5 for CMU_CALCTRL */
5554 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6                    0x00000006UL                            /**< Mode PRSCH6 for CMU_CALCTRL */
5555 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7                    0x00000007UL                            /**< Mode PRSCH7 for CMU_CALCTRL */
5556 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8                    0x00000008UL                            /**< Mode PRSCH8 for CMU_CALCTRL */
5557 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9                    0x00000009UL                            /**< Mode PRSCH9 for CMU_CALCTRL */
5558 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10                   0x0000000AUL                            /**< Mode PRSCH10 for CMU_CALCTRL */
5559 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11                   0x0000000BUL                            /**< Mode PRSCH11 for CMU_CALCTRL */
5560 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12                   0x0000000CUL                            /**< Mode PRSCH12 for CMU_CALCTRL */
5561 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13                   0x0000000DUL                            /**< Mode PRSCH13 for CMU_CALCTRL */
5562 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14                   0x0000000EUL                            /**< Mode PRSCH14 for CMU_CALCTRL */
5563 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15                   0x0000000FUL                            /**< Mode PRSCH15 for CMU_CALCTRL */
5564 #define CMU_CALCTRL_PRSDOWNSEL_DEFAULT                    (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */
5565 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH0                     (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24)  /**< Shifted mode PRSCH0 for CMU_CALCTRL */
5566 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH1                     (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24)  /**< Shifted mode PRSCH1 for CMU_CALCTRL */
5567 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH2                     (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24)  /**< Shifted mode PRSCH2 for CMU_CALCTRL */
5568 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH3                     (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24)  /**< Shifted mode PRSCH3 for CMU_CALCTRL */
5569 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH4                     (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24)  /**< Shifted mode PRSCH4 for CMU_CALCTRL */
5570 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH5                     (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24)  /**< Shifted mode PRSCH5 for CMU_CALCTRL */
5571 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH6                     (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24)  /**< Shifted mode PRSCH6 for CMU_CALCTRL */
5572 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH7                     (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24)  /**< Shifted mode PRSCH7 for CMU_CALCTRL */
5573 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH8                     (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24)  /**< Shifted mode PRSCH8 for CMU_CALCTRL */
5574 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH9                     (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24)  /**< Shifted mode PRSCH9 for CMU_CALCTRL */
5575 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH10                    (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */
5576 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH11                    (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */
5577 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH12                    (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */
5578 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH13                    (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */
5579 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH14                    (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */
5580 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH15                    (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */
5581 
5582 /* Bit fields for CMU CALCNT */
5583 #define _CMU_CALCNT_RESETVALUE                            0x00000000UL                      /**< Default value for CMU_CALCNT */
5584 #define _CMU_CALCNT_MASK                                  0x000FFFFFUL                      /**< Mask for CMU_CALCNT */
5585 #define _CMU_CALCNT_CALCNT_SHIFT                          0                                 /**< Shift value for CMU_CALCNT */
5586 #define _CMU_CALCNT_CALCNT_MASK                           0xFFFFFUL                         /**< Bit mask for CMU_CALCNT */
5587 #define _CMU_CALCNT_CALCNT_DEFAULT                        0x00000000UL                      /**< Mode DEFAULT for CMU_CALCNT */
5588 #define CMU_CALCNT_CALCNT_DEFAULT                         (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
5589 
5590 /* Bit fields for CMU OSCENCMD */
5591 #define _CMU_OSCENCMD_RESETVALUE                          0x00000000UL                             /**< Default value for CMU_OSCENCMD */
5592 #define _CMU_OSCENCMD_MASK                                0x00003FFFUL                             /**< Mask for CMU_OSCENCMD */
5593 #define CMU_OSCENCMD_HFRCOEN                              (0x1UL << 0)                             /**< HFRCO Enable */
5594 #define _CMU_OSCENCMD_HFRCOEN_SHIFT                       0                                        /**< Shift value for CMU_HFRCOEN */
5595 #define _CMU_OSCENCMD_HFRCOEN_MASK                        0x1UL                                    /**< Bit mask for CMU_HFRCOEN */
5596 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT                     0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
5597 #define CMU_OSCENCMD_HFRCOEN_DEFAULT                      (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
5598 #define CMU_OSCENCMD_HFRCODIS                             (0x1UL << 1)                             /**< HFRCO Disable */
5599 #define _CMU_OSCENCMD_HFRCODIS_SHIFT                      1                                        /**< Shift value for CMU_HFRCODIS */
5600 #define _CMU_OSCENCMD_HFRCODIS_MASK                       0x2UL                                    /**< Bit mask for CMU_HFRCODIS */
5601 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
5602 #define CMU_OSCENCMD_HFRCODIS_DEFAULT                     (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)    /**< Shifted mode DEFAULT for CMU_OSCENCMD */
5603 #define CMU_OSCENCMD_HFXOEN                               (0x1UL << 2)                             /**< HFXO Enable */
5604 #define _CMU_OSCENCMD_HFXOEN_SHIFT                        2                                        /**< Shift value for CMU_HFXOEN */
5605 #define _CMU_OSCENCMD_HFXOEN_MASK                         0x4UL                                    /**< Bit mask for CMU_HFXOEN */
5606 #define _CMU_OSCENCMD_HFXOEN_DEFAULT                      0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
5607 #define CMU_OSCENCMD_HFXOEN_DEFAULT                       (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)      /**< Shifted mode DEFAULT for CMU_OSCENCMD */
5608 #define CMU_OSCENCMD_HFXODIS                              (0x1UL << 3)                             /**< HFXO Disable */
5609 #define _CMU_OSCENCMD_HFXODIS_SHIFT                       3                                        /**< Shift value for CMU_HFXODIS */
5610 #define _CMU_OSCENCMD_HFXODIS_MASK                        0x8UL                                    /**< Bit mask for CMU_HFXODIS */
5611 #define _CMU_OSCENCMD_HFXODIS_DEFAULT                     0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
5612 #define CMU_OSCENCMD_HFXODIS_DEFAULT                      (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
5613 #define CMU_OSCENCMD_AUXHFRCOEN                           (0x1UL << 4)                             /**< AUXHFRCO Enable */
5614 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT                    4                                        /**< Shift value for CMU_AUXHFRCOEN */
5615 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK                     0x10UL                                   /**< Bit mask for CMU_AUXHFRCOEN */
5616 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
5617 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT                   (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)  /**< Shifted mode DEFAULT for CMU_OSCENCMD */
5618 #define CMU_OSCENCMD_AUXHFRCODIS                          (0x1UL << 5)                             /**< AUXHFRCO Disable */
5619 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT                   5                                        /**< Shift value for CMU_AUXHFRCODIS */
5620 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK                    0x20UL                                   /**< Bit mask for CMU_AUXHFRCODIS */
5621 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
5622 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT                  (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
5623 #define CMU_OSCENCMD_LFRCOEN                              (0x1UL << 6)                             /**< LFRCO Enable */
5624 #define _CMU_OSCENCMD_LFRCOEN_SHIFT                       6                                        /**< Shift value for CMU_LFRCOEN */
5625 #define _CMU_OSCENCMD_LFRCOEN_MASK                        0x40UL                                   /**< Bit mask for CMU_LFRCOEN */
5626 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT                     0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
5627 #define CMU_OSCENCMD_LFRCOEN_DEFAULT                      (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
5628 #define CMU_OSCENCMD_LFRCODIS                             (0x1UL << 7)                             /**< LFRCO Disable */
5629 #define _CMU_OSCENCMD_LFRCODIS_SHIFT                      7                                        /**< Shift value for CMU_LFRCODIS */
5630 #define _CMU_OSCENCMD_LFRCODIS_MASK                       0x80UL                                   /**< Bit mask for CMU_LFRCODIS */
5631 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
5632 #define CMU_OSCENCMD_LFRCODIS_DEFAULT                     (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)    /**< Shifted mode DEFAULT for CMU_OSCENCMD */
5633 #define CMU_OSCENCMD_LFXOEN                               (0x1UL << 8)                             /**< LFXO Enable */
5634 #define _CMU_OSCENCMD_LFXOEN_SHIFT                        8                                        /**< Shift value for CMU_LFXOEN */
5635 #define _CMU_OSCENCMD_LFXOEN_MASK                         0x100UL                                  /**< Bit mask for CMU_LFXOEN */
5636 #define _CMU_OSCENCMD_LFXOEN_DEFAULT                      0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
5637 #define CMU_OSCENCMD_LFXOEN_DEFAULT                       (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)      /**< Shifted mode DEFAULT for CMU_OSCENCMD */
5638 #define CMU_OSCENCMD_LFXODIS                              (0x1UL << 9)                             /**< LFXO Disable */
5639 #define _CMU_OSCENCMD_LFXODIS_SHIFT                       9                                        /**< Shift value for CMU_LFXODIS */
5640 #define _CMU_OSCENCMD_LFXODIS_MASK                        0x200UL                                  /**< Bit mask for CMU_LFXODIS */
5641 #define _CMU_OSCENCMD_LFXODIS_DEFAULT                     0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
5642 #define CMU_OSCENCMD_LFXODIS_DEFAULT                      (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
5643 #define CMU_OSCENCMD_USHFRCOEN                            (0x1UL << 10)                            /**< USHFRCO Enable */
5644 #define _CMU_OSCENCMD_USHFRCOEN_SHIFT                     10                                       /**< Shift value for CMU_USHFRCOEN */
5645 #define _CMU_OSCENCMD_USHFRCOEN_MASK                      0x400UL                                  /**< Bit mask for CMU_USHFRCOEN */
5646 #define _CMU_OSCENCMD_USHFRCOEN_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
5647 #define CMU_OSCENCMD_USHFRCOEN_DEFAULT                    (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10)  /**< Shifted mode DEFAULT for CMU_OSCENCMD */
5648 #define CMU_OSCENCMD_USHFRCODIS                           (0x1UL << 11)                            /**< USHFRCO Disable */
5649 #define _CMU_OSCENCMD_USHFRCODIS_SHIFT                    11                                       /**< Shift value for CMU_USHFRCODIS */
5650 #define _CMU_OSCENCMD_USHFRCODIS_MASK                     0x800UL                                  /**< Bit mask for CMU_USHFRCODIS */
5651 #define _CMU_OSCENCMD_USHFRCODIS_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
5652 #define CMU_OSCENCMD_USHFRCODIS_DEFAULT                   (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
5653 #define CMU_OSCENCMD_DPLLEN                               (0x1UL << 12)                            /**< DPLL Enable */
5654 #define _CMU_OSCENCMD_DPLLEN_SHIFT                        12                                       /**< Shift value for CMU_DPLLEN */
5655 #define _CMU_OSCENCMD_DPLLEN_MASK                         0x1000UL                                 /**< Bit mask for CMU_DPLLEN */
5656 #define _CMU_OSCENCMD_DPLLEN_DEFAULT                      0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
5657 #define CMU_OSCENCMD_DPLLEN_DEFAULT                       (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12)     /**< Shifted mode DEFAULT for CMU_OSCENCMD */
5658 #define CMU_OSCENCMD_DPLLDIS                              (0x1UL << 13)                            /**< DPLL Disable */
5659 #define _CMU_OSCENCMD_DPLLDIS_SHIFT                       13                                       /**< Shift value for CMU_DPLLDIS */
5660 #define _CMU_OSCENCMD_DPLLDIS_MASK                        0x2000UL                                 /**< Bit mask for CMU_DPLLDIS */
5661 #define _CMU_OSCENCMD_DPLLDIS_DEFAULT                     0x00000000UL                             /**< Mode DEFAULT for CMU_OSCENCMD */
5662 #define CMU_OSCENCMD_DPLLDIS_DEFAULT                      (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13)    /**< Shifted mode DEFAULT for CMU_OSCENCMD */
5663 
5664 /* Bit fields for CMU CMD */
5665 #define _CMU_CMD_RESETVALUE                               0x00000000UL                             /**< Default value for CMU_CMD */
5666 #define _CMU_CMD_MASK                                     0x00000013UL                             /**< Mask for CMU_CMD */
5667 #define CMU_CMD_CALSTART                                  (0x1UL << 0)                             /**< Calibration Start */
5668 #define _CMU_CMD_CALSTART_SHIFT                           0                                        /**< Shift value for CMU_CALSTART */
5669 #define _CMU_CMD_CALSTART_MASK                            0x1UL                                    /**< Bit mask for CMU_CALSTART */
5670 #define _CMU_CMD_CALSTART_DEFAULT                         0x00000000UL                             /**< Mode DEFAULT for CMU_CMD */
5671 #define CMU_CMD_CALSTART_DEFAULT                          (_CMU_CMD_CALSTART_DEFAULT << 0)         /**< Shifted mode DEFAULT for CMU_CMD */
5672 #define CMU_CMD_CALSTOP                                   (0x1UL << 1)                             /**< Calibration Stop */
5673 #define _CMU_CMD_CALSTOP_SHIFT                            1                                        /**< Shift value for CMU_CALSTOP */
5674 #define _CMU_CMD_CALSTOP_MASK                             0x2UL                                    /**< Bit mask for CMU_CALSTOP */
5675 #define _CMU_CMD_CALSTOP_DEFAULT                          0x00000000UL                             /**< Mode DEFAULT for CMU_CMD */
5676 #define CMU_CMD_CALSTOP_DEFAULT                           (_CMU_CMD_CALSTOP_DEFAULT << 1)          /**< Shifted mode DEFAULT for CMU_CMD */
5677 #define CMU_CMD_HFXOPEAKDETSTART                          (0x1UL << 4)                             /**< HFXO Peak Detection Start */
5678 #define _CMU_CMD_HFXOPEAKDETSTART_SHIFT                   4                                        /**< Shift value for CMU_HFXOPEAKDETSTART */
5679 #define _CMU_CMD_HFXOPEAKDETSTART_MASK                    0x10UL                                   /**< Bit mask for CMU_HFXOPEAKDETSTART */
5680 #define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for CMU_CMD */
5681 #define CMU_CMD_HFXOPEAKDETSTART_DEFAULT                  (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */
5682 
5683 /* Bit fields for CMU DBGCLKSEL */
5684 #define _CMU_DBGCLKSEL_RESETVALUE                         0x00000000UL                        /**< Default value for CMU_DBGCLKSEL */
5685 #define _CMU_DBGCLKSEL_MASK                               0x00000003UL                        /**< Mask for CMU_DBGCLKSEL */
5686 #define _CMU_DBGCLKSEL_DBG_SHIFT                          0                                   /**< Shift value for CMU_DBG */
5687 #define _CMU_DBGCLKSEL_DBG_MASK                           0x3UL                               /**< Bit mask for CMU_DBG */
5688 #define _CMU_DBGCLKSEL_DBG_DEFAULT                        0x00000000UL                        /**< Mode DEFAULT for CMU_DBGCLKSEL */
5689 #define _CMU_DBGCLKSEL_DBG_AUXHFRCO                       0x00000000UL                        /**< Mode AUXHFRCO for CMU_DBGCLKSEL */
5690 #define _CMU_DBGCLKSEL_DBG_HFCLK                          0x00000001UL                        /**< Mode HFCLK for CMU_DBGCLKSEL */
5691 #define _CMU_DBGCLKSEL_DBG_HFRCODIV2                      0x00000002UL                        /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */
5692 #define CMU_DBGCLKSEL_DBG_DEFAULT                         (_CMU_DBGCLKSEL_DBG_DEFAULT << 0)   /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */
5693 #define CMU_DBGCLKSEL_DBG_AUXHFRCO                        (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0)  /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */
5694 #define CMU_DBGCLKSEL_DBG_HFCLK                           (_CMU_DBGCLKSEL_DBG_HFCLK << 0)     /**< Shifted mode HFCLK for CMU_DBGCLKSEL */
5695 #define CMU_DBGCLKSEL_DBG_HFRCODIV2                       (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */
5696 
5697 /* Bit fields for CMU HFCLKSEL */
5698 #define _CMU_HFCLKSEL_RESETVALUE                          0x00000000UL                      /**< Default value for CMU_HFCLKSEL */
5699 #define _CMU_HFCLKSEL_MASK                                0x00000007UL                      /**< Mask for CMU_HFCLKSEL */
5700 #define _CMU_HFCLKSEL_HF_SHIFT                            0                                 /**< Shift value for CMU_HF */
5701 #define _CMU_HFCLKSEL_HF_MASK                             0x7UL                             /**< Bit mask for CMU_HF */
5702 #define _CMU_HFCLKSEL_HF_DEFAULT                          0x00000000UL                      /**< Mode DEFAULT for CMU_HFCLKSEL */
5703 #define _CMU_HFCLKSEL_HF_HFRCO                            0x00000001UL                      /**< Mode HFRCO for CMU_HFCLKSEL */
5704 #define _CMU_HFCLKSEL_HF_HFXO                             0x00000002UL                      /**< Mode HFXO for CMU_HFCLKSEL */
5705 #define _CMU_HFCLKSEL_HF_LFRCO                            0x00000003UL                      /**< Mode LFRCO for CMU_HFCLKSEL */
5706 #define _CMU_HFCLKSEL_HF_LFXO                             0x00000004UL                      /**< Mode LFXO for CMU_HFCLKSEL */
5707 #define _CMU_HFCLKSEL_HF_HFRCODIV2                        0x00000005UL                      /**< Mode HFRCODIV2 for CMU_HFCLKSEL */
5708 #define _CMU_HFCLKSEL_HF_USHFRCO                          0x00000006UL                      /**< Mode USHFRCO for CMU_HFCLKSEL */
5709 #define _CMU_HFCLKSEL_HF_CLKIN0                           0x00000007UL                      /**< Mode CLKIN0 for CMU_HFCLKSEL */
5710 #define CMU_HFCLKSEL_HF_DEFAULT                           (_CMU_HFCLKSEL_HF_DEFAULT << 0)   /**< Shifted mode DEFAULT for CMU_HFCLKSEL */
5711 #define CMU_HFCLKSEL_HF_HFRCO                             (_CMU_HFCLKSEL_HF_HFRCO << 0)     /**< Shifted mode HFRCO for CMU_HFCLKSEL */
5712 #define CMU_HFCLKSEL_HF_HFXO                              (_CMU_HFCLKSEL_HF_HFXO << 0)      /**< Shifted mode HFXO for CMU_HFCLKSEL */
5713 #define CMU_HFCLKSEL_HF_LFRCO                             (_CMU_HFCLKSEL_HF_LFRCO << 0)     /**< Shifted mode LFRCO for CMU_HFCLKSEL */
5714 #define CMU_HFCLKSEL_HF_LFXO                              (_CMU_HFCLKSEL_HF_LFXO << 0)      /**< Shifted mode LFXO for CMU_HFCLKSEL */
5715 #define CMU_HFCLKSEL_HF_HFRCODIV2                         (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */
5716 #define CMU_HFCLKSEL_HF_USHFRCO                           (_CMU_HFCLKSEL_HF_USHFRCO << 0)   /**< Shifted mode USHFRCO for CMU_HFCLKSEL */
5717 #define CMU_HFCLKSEL_HF_CLKIN0                            (_CMU_HFCLKSEL_HF_CLKIN0 << 0)    /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */
5718 
5719 /* Bit fields for CMU LFACLKSEL */
5720 #define _CMU_LFACLKSEL_RESETVALUE                         0x00000000UL                       /**< Default value for CMU_LFACLKSEL */
5721 #define _CMU_LFACLKSEL_MASK                               0x00000007UL                       /**< Mask for CMU_LFACLKSEL */
5722 #define _CMU_LFACLKSEL_LFA_SHIFT                          0                                  /**< Shift value for CMU_LFA */
5723 #define _CMU_LFACLKSEL_LFA_MASK                           0x7UL                              /**< Bit mask for CMU_LFA */
5724 #define _CMU_LFACLKSEL_LFA_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for CMU_LFACLKSEL */
5725 #define _CMU_LFACLKSEL_LFA_DISABLED                       0x00000000UL                       /**< Mode DISABLED for CMU_LFACLKSEL */
5726 #define _CMU_LFACLKSEL_LFA_LFRCO                          0x00000001UL                       /**< Mode LFRCO for CMU_LFACLKSEL */
5727 #define _CMU_LFACLKSEL_LFA_LFXO                           0x00000002UL                       /**< Mode LFXO for CMU_LFACLKSEL */
5728 #define _CMU_LFACLKSEL_LFA_ULFRCO                         0x00000004UL                       /**< Mode ULFRCO for CMU_LFACLKSEL */
5729 #define CMU_LFACLKSEL_LFA_DEFAULT                         (_CMU_LFACLKSEL_LFA_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_LFACLKSEL */
5730 #define CMU_LFACLKSEL_LFA_DISABLED                        (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */
5731 #define CMU_LFACLKSEL_LFA_LFRCO                           (_CMU_LFACLKSEL_LFA_LFRCO << 0)    /**< Shifted mode LFRCO for CMU_LFACLKSEL */
5732 #define CMU_LFACLKSEL_LFA_LFXO                            (_CMU_LFACLKSEL_LFA_LFXO << 0)     /**< Shifted mode LFXO for CMU_LFACLKSEL */
5733 #define CMU_LFACLKSEL_LFA_ULFRCO                          (_CMU_LFACLKSEL_LFA_ULFRCO << 0)   /**< Shifted mode ULFRCO for CMU_LFACLKSEL */
5734 
5735 /* Bit fields for CMU LFBCLKSEL */
5736 #define _CMU_LFBCLKSEL_RESETVALUE                         0x00000000UL                       /**< Default value for CMU_LFBCLKSEL */
5737 #define _CMU_LFBCLKSEL_MASK                               0x00000007UL                       /**< Mask for CMU_LFBCLKSEL */
5738 #define _CMU_LFBCLKSEL_LFB_SHIFT                          0                                  /**< Shift value for CMU_LFB */
5739 #define _CMU_LFBCLKSEL_LFB_MASK                           0x7UL                              /**< Bit mask for CMU_LFB */
5740 #define _CMU_LFBCLKSEL_LFB_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for CMU_LFBCLKSEL */
5741 #define _CMU_LFBCLKSEL_LFB_DISABLED                       0x00000000UL                       /**< Mode DISABLED for CMU_LFBCLKSEL */
5742 #define _CMU_LFBCLKSEL_LFB_LFRCO                          0x00000001UL                       /**< Mode LFRCO for CMU_LFBCLKSEL */
5743 #define _CMU_LFBCLKSEL_LFB_LFXO                           0x00000002UL                       /**< Mode LFXO for CMU_LFBCLKSEL */
5744 #define _CMU_LFBCLKSEL_LFB_HFCLKLE                        0x00000003UL                       /**< Mode HFCLKLE for CMU_LFBCLKSEL */
5745 #define _CMU_LFBCLKSEL_LFB_ULFRCO                         0x00000004UL                       /**< Mode ULFRCO for CMU_LFBCLKSEL */
5746 #define CMU_LFBCLKSEL_LFB_DEFAULT                         (_CMU_LFBCLKSEL_LFB_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */
5747 #define CMU_LFBCLKSEL_LFB_DISABLED                        (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */
5748 #define CMU_LFBCLKSEL_LFB_LFRCO                           (_CMU_LFBCLKSEL_LFB_LFRCO << 0)    /**< Shifted mode LFRCO for CMU_LFBCLKSEL */
5749 #define CMU_LFBCLKSEL_LFB_LFXO                            (_CMU_LFBCLKSEL_LFB_LFXO << 0)     /**< Shifted mode LFXO for CMU_LFBCLKSEL */
5750 #define CMU_LFBCLKSEL_LFB_HFCLKLE                         (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0)  /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */
5751 #define CMU_LFBCLKSEL_LFB_ULFRCO                          (_CMU_LFBCLKSEL_LFB_ULFRCO << 0)   /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */
5752 
5753 /* Bit fields for CMU LFECLKSEL */
5754 #define _CMU_LFECLKSEL_RESETVALUE                         0x00000000UL                       /**< Default value for CMU_LFECLKSEL */
5755 #define _CMU_LFECLKSEL_MASK                               0x00000007UL                       /**< Mask for CMU_LFECLKSEL */
5756 #define _CMU_LFECLKSEL_LFE_SHIFT                          0                                  /**< Shift value for CMU_LFE */
5757 #define _CMU_LFECLKSEL_LFE_MASK                           0x7UL                              /**< Bit mask for CMU_LFE */
5758 #define _CMU_LFECLKSEL_LFE_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for CMU_LFECLKSEL */
5759 #define _CMU_LFECLKSEL_LFE_DISABLED                       0x00000000UL                       /**< Mode DISABLED for CMU_LFECLKSEL */
5760 #define _CMU_LFECLKSEL_LFE_LFRCO                          0x00000001UL                       /**< Mode LFRCO for CMU_LFECLKSEL */
5761 #define _CMU_LFECLKSEL_LFE_LFXO                           0x00000002UL                       /**< Mode LFXO for CMU_LFECLKSEL */
5762 #define _CMU_LFECLKSEL_LFE_ULFRCO                         0x00000004UL                       /**< Mode ULFRCO for CMU_LFECLKSEL */
5763 #define CMU_LFECLKSEL_LFE_DEFAULT                         (_CMU_LFECLKSEL_LFE_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_LFECLKSEL */
5764 #define CMU_LFECLKSEL_LFE_DISABLED                        (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */
5765 #define CMU_LFECLKSEL_LFE_LFRCO                           (_CMU_LFECLKSEL_LFE_LFRCO << 0)    /**< Shifted mode LFRCO for CMU_LFECLKSEL */
5766 #define CMU_LFECLKSEL_LFE_LFXO                            (_CMU_LFECLKSEL_LFE_LFXO << 0)     /**< Shifted mode LFXO for CMU_LFECLKSEL */
5767 #define CMU_LFECLKSEL_LFE_ULFRCO                          (_CMU_LFECLKSEL_LFE_ULFRCO << 0)   /**< Shifted mode ULFRCO for CMU_LFECLKSEL */
5768 
5769 /* Bit fields for CMU LFCCLKSEL */
5770 #define _CMU_LFCCLKSEL_RESETVALUE                         0x00000000UL                       /**< Default value for CMU_LFCCLKSEL */
5771 #define _CMU_LFCCLKSEL_MASK                               0x00000007UL                       /**< Mask for CMU_LFCCLKSEL */
5772 #define _CMU_LFCCLKSEL_LFC_SHIFT                          0                                  /**< Shift value for CMU_LFC */
5773 #define _CMU_LFCCLKSEL_LFC_MASK                           0x7UL                              /**< Bit mask for CMU_LFC */
5774 #define _CMU_LFCCLKSEL_LFC_DEFAULT                        0x00000000UL                       /**< Mode DEFAULT for CMU_LFCCLKSEL */
5775 #define _CMU_LFCCLKSEL_LFC_DISABLED                       0x00000000UL                       /**< Mode DISABLED for CMU_LFCCLKSEL */
5776 #define _CMU_LFCCLKSEL_LFC_LFRCO                          0x00000001UL                       /**< Mode LFRCO for CMU_LFCCLKSEL */
5777 #define _CMU_LFCCLKSEL_LFC_LFXO                           0x00000002UL                       /**< Mode LFXO for CMU_LFCCLKSEL */
5778 #define _CMU_LFCCLKSEL_LFC_ULFRCO                         0x00000004UL                       /**< Mode ULFRCO for CMU_LFCCLKSEL */
5779 #define CMU_LFCCLKSEL_LFC_DEFAULT                         (_CMU_LFCCLKSEL_LFC_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */
5780 #define CMU_LFCCLKSEL_LFC_DISABLED                        (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */
5781 #define CMU_LFCCLKSEL_LFC_LFRCO                           (_CMU_LFCCLKSEL_LFC_LFRCO << 0)    /**< Shifted mode LFRCO for CMU_LFCCLKSEL */
5782 #define CMU_LFCCLKSEL_LFC_LFXO                            (_CMU_LFCCLKSEL_LFC_LFXO << 0)     /**< Shifted mode LFXO for CMU_LFCCLKSEL */
5783 #define CMU_LFCCLKSEL_LFC_ULFRCO                          (_CMU_LFCCLKSEL_LFC_ULFRCO << 0)   /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */
5784 
5785 /* Bit fields for CMU STATUS */
5786 #define _CMU_STATUS_RESETVALUE                            0x00010003UL                               /**< Default value for CMU_STATUS */
5787 #define _CMU_STATUS_MASK                                  0x3A493FFFUL                               /**< Mask for CMU_STATUS */
5788 #define CMU_STATUS_HFRCOENS                               (0x1UL << 0)                               /**< HFRCO Enable Status */
5789 #define _CMU_STATUS_HFRCOENS_SHIFT                        0                                          /**< Shift value for CMU_HFRCOENS */
5790 #define _CMU_STATUS_HFRCOENS_MASK                         0x1UL                                      /**< Bit mask for CMU_HFRCOENS */
5791 #define _CMU_STATUS_HFRCOENS_DEFAULT                      0x00000001UL                               /**< Mode DEFAULT for CMU_STATUS */
5792 #define CMU_STATUS_HFRCOENS_DEFAULT                       (_CMU_STATUS_HFRCOENS_DEFAULT << 0)        /**< Shifted mode DEFAULT for CMU_STATUS */
5793 #define CMU_STATUS_HFRCORDY                               (0x1UL << 1)                               /**< HFRCO Ready */
5794 #define _CMU_STATUS_HFRCORDY_SHIFT                        1                                          /**< Shift value for CMU_HFRCORDY */
5795 #define _CMU_STATUS_HFRCORDY_MASK                         0x2UL                                      /**< Bit mask for CMU_HFRCORDY */
5796 #define _CMU_STATUS_HFRCORDY_DEFAULT                      0x00000001UL                               /**< Mode DEFAULT for CMU_STATUS */
5797 #define CMU_STATUS_HFRCORDY_DEFAULT                       (_CMU_STATUS_HFRCORDY_DEFAULT << 1)        /**< Shifted mode DEFAULT for CMU_STATUS */
5798 #define CMU_STATUS_HFXOENS                                (0x1UL << 2)                               /**< HFXO Enable Status */
5799 #define _CMU_STATUS_HFXOENS_SHIFT                         2                                          /**< Shift value for CMU_HFXOENS */
5800 #define _CMU_STATUS_HFXOENS_MASK                          0x4UL                                      /**< Bit mask for CMU_HFXOENS */
5801 #define _CMU_STATUS_HFXOENS_DEFAULT                       0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5802 #define CMU_STATUS_HFXOENS_DEFAULT                        (_CMU_STATUS_HFXOENS_DEFAULT << 2)         /**< Shifted mode DEFAULT for CMU_STATUS */
5803 #define CMU_STATUS_HFXORDY                                (0x1UL << 3)                               /**< HFXO Ready */
5804 #define _CMU_STATUS_HFXORDY_SHIFT                         3                                          /**< Shift value for CMU_HFXORDY */
5805 #define _CMU_STATUS_HFXORDY_MASK                          0x8UL                                      /**< Bit mask for CMU_HFXORDY */
5806 #define _CMU_STATUS_HFXORDY_DEFAULT                       0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5807 #define CMU_STATUS_HFXORDY_DEFAULT                        (_CMU_STATUS_HFXORDY_DEFAULT << 3)         /**< Shifted mode DEFAULT for CMU_STATUS */
5808 #define CMU_STATUS_AUXHFRCOENS                            (0x1UL << 4)                               /**< AUXHFRCO Enable Status */
5809 #define _CMU_STATUS_AUXHFRCOENS_SHIFT                     4                                          /**< Shift value for CMU_AUXHFRCOENS */
5810 #define _CMU_STATUS_AUXHFRCOENS_MASK                      0x10UL                                     /**< Bit mask for CMU_AUXHFRCOENS */
5811 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5812 #define CMU_STATUS_AUXHFRCOENS_DEFAULT                    (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)     /**< Shifted mode DEFAULT for CMU_STATUS */
5813 #define CMU_STATUS_AUXHFRCORDY                            (0x1UL << 5)                               /**< AUXHFRCO Ready */
5814 #define _CMU_STATUS_AUXHFRCORDY_SHIFT                     5                                          /**< Shift value for CMU_AUXHFRCORDY */
5815 #define _CMU_STATUS_AUXHFRCORDY_MASK                      0x20UL                                     /**< Bit mask for CMU_AUXHFRCORDY */
5816 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5817 #define CMU_STATUS_AUXHFRCORDY_DEFAULT                    (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)     /**< Shifted mode DEFAULT for CMU_STATUS */
5818 #define CMU_STATUS_LFRCOENS                               (0x1UL << 6)                               /**< LFRCO Enable Status */
5819 #define _CMU_STATUS_LFRCOENS_SHIFT                        6                                          /**< Shift value for CMU_LFRCOENS */
5820 #define _CMU_STATUS_LFRCOENS_MASK                         0x40UL                                     /**< Bit mask for CMU_LFRCOENS */
5821 #define _CMU_STATUS_LFRCOENS_DEFAULT                      0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5822 #define CMU_STATUS_LFRCOENS_DEFAULT                       (_CMU_STATUS_LFRCOENS_DEFAULT << 6)        /**< Shifted mode DEFAULT for CMU_STATUS */
5823 #define CMU_STATUS_LFRCORDY                               (0x1UL << 7)                               /**< LFRCO Ready */
5824 #define _CMU_STATUS_LFRCORDY_SHIFT                        7                                          /**< Shift value for CMU_LFRCORDY */
5825 #define _CMU_STATUS_LFRCORDY_MASK                         0x80UL                                     /**< Bit mask for CMU_LFRCORDY */
5826 #define _CMU_STATUS_LFRCORDY_DEFAULT                      0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5827 #define CMU_STATUS_LFRCORDY_DEFAULT                       (_CMU_STATUS_LFRCORDY_DEFAULT << 7)        /**< Shifted mode DEFAULT for CMU_STATUS */
5828 #define CMU_STATUS_LFXOENS                                (0x1UL << 8)                               /**< LFXO Enable Status */
5829 #define _CMU_STATUS_LFXOENS_SHIFT                         8                                          /**< Shift value for CMU_LFXOENS */
5830 #define _CMU_STATUS_LFXOENS_MASK                          0x100UL                                    /**< Bit mask for CMU_LFXOENS */
5831 #define _CMU_STATUS_LFXOENS_DEFAULT                       0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5832 #define CMU_STATUS_LFXOENS_DEFAULT                        (_CMU_STATUS_LFXOENS_DEFAULT << 8)         /**< Shifted mode DEFAULT for CMU_STATUS */
5833 #define CMU_STATUS_LFXORDY                                (0x1UL << 9)                               /**< LFXO Ready */
5834 #define _CMU_STATUS_LFXORDY_SHIFT                         9                                          /**< Shift value for CMU_LFXORDY */
5835 #define _CMU_STATUS_LFXORDY_MASK                          0x200UL                                    /**< Bit mask for CMU_LFXORDY */
5836 #define _CMU_STATUS_LFXORDY_DEFAULT                       0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5837 #define CMU_STATUS_LFXORDY_DEFAULT                        (_CMU_STATUS_LFXORDY_DEFAULT << 9)         /**< Shifted mode DEFAULT for CMU_STATUS */
5838 #define CMU_STATUS_USHFRCOENS                             (0x1UL << 10)                              /**< USHFRCO Enable Status */
5839 #define _CMU_STATUS_USHFRCOENS_SHIFT                      10                                         /**< Shift value for CMU_USHFRCOENS */
5840 #define _CMU_STATUS_USHFRCOENS_MASK                       0x400UL                                    /**< Bit mask for CMU_USHFRCOENS */
5841 #define _CMU_STATUS_USHFRCOENS_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5842 #define CMU_STATUS_USHFRCOENS_DEFAULT                     (_CMU_STATUS_USHFRCOENS_DEFAULT << 10)     /**< Shifted mode DEFAULT for CMU_STATUS */
5843 #define CMU_STATUS_USHFRCORDY                             (0x1UL << 11)                              /**< USHFRCO Ready */
5844 #define _CMU_STATUS_USHFRCORDY_SHIFT                      11                                         /**< Shift value for CMU_USHFRCORDY */
5845 #define _CMU_STATUS_USHFRCORDY_MASK                       0x800UL                                    /**< Bit mask for CMU_USHFRCORDY */
5846 #define _CMU_STATUS_USHFRCORDY_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5847 #define CMU_STATUS_USHFRCORDY_DEFAULT                     (_CMU_STATUS_USHFRCORDY_DEFAULT << 11)     /**< Shifted mode DEFAULT for CMU_STATUS */
5848 #define CMU_STATUS_DPLLENS                                (0x1UL << 12)                              /**< DPLL Enable Status */
5849 #define _CMU_STATUS_DPLLENS_SHIFT                         12                                         /**< Shift value for CMU_DPLLENS */
5850 #define _CMU_STATUS_DPLLENS_MASK                          0x1000UL                                   /**< Bit mask for CMU_DPLLENS */
5851 #define _CMU_STATUS_DPLLENS_DEFAULT                       0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5852 #define CMU_STATUS_DPLLENS_DEFAULT                        (_CMU_STATUS_DPLLENS_DEFAULT << 12)        /**< Shifted mode DEFAULT for CMU_STATUS */
5853 #define CMU_STATUS_DPLLRDY                                (0x1UL << 13)                              /**< DPLL Ready */
5854 #define _CMU_STATUS_DPLLRDY_SHIFT                         13                                         /**< Shift value for CMU_DPLLRDY */
5855 #define _CMU_STATUS_DPLLRDY_MASK                          0x2000UL                                   /**< Bit mask for CMU_DPLLRDY */
5856 #define _CMU_STATUS_DPLLRDY_DEFAULT                       0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5857 #define CMU_STATUS_DPLLRDY_DEFAULT                        (_CMU_STATUS_DPLLRDY_DEFAULT << 13)        /**< Shifted mode DEFAULT for CMU_STATUS */
5858 #define CMU_STATUS_CALRDY                                 (0x1UL << 16)                              /**< Calibration Ready */
5859 #define _CMU_STATUS_CALRDY_SHIFT                          16                                         /**< Shift value for CMU_CALRDY */
5860 #define _CMU_STATUS_CALRDY_MASK                           0x10000UL                                  /**< Bit mask for CMU_CALRDY */
5861 #define _CMU_STATUS_CALRDY_DEFAULT                        0x00000001UL                               /**< Mode DEFAULT for CMU_STATUS */
5862 #define CMU_STATUS_CALRDY_DEFAULT                         (_CMU_STATUS_CALRDY_DEFAULT << 16)         /**< Shifted mode DEFAULT for CMU_STATUS */
5863 #define CMU_STATUS_PDMCLKENS                              (0x1UL << 19)                              /**< PDM Clock Enabled Status */
5864 #define _CMU_STATUS_PDMCLKENS_SHIFT                       19                                         /**< Shift value for CMU_PDMCLKENS */
5865 #define _CMU_STATUS_PDMCLKENS_MASK                        0x80000UL                                  /**< Bit mask for CMU_PDMCLKENS */
5866 #define _CMU_STATUS_PDMCLKENS_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5867 #define CMU_STATUS_PDMCLKENS_DEFAULT                      (_CMU_STATUS_PDMCLKENS_DEFAULT << 19)      /**< Shifted mode DEFAULT for CMU_STATUS */
5868 #define CMU_STATUS_HFXOPEAKDETRDY                         (0x1UL << 22)                              /**< HFXO Peak Detection Ready */
5869 #define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT                  22                                         /**< Shift value for CMU_HFXOPEAKDETRDY */
5870 #define _CMU_STATUS_HFXOPEAKDETRDY_MASK                   0x400000UL                                 /**< Bit mask for CMU_HFXOPEAKDETRDY */
5871 #define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT                0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5872 #define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT                 (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */
5873 #define CMU_STATUS_HFXOAMPLOW                             (0x1UL << 25)                              /**< HFXO Amplitude Tuning Value Too Low */
5874 #define _CMU_STATUS_HFXOAMPLOW_SHIFT                      25                                         /**< Shift value for CMU_HFXOAMPLOW */
5875 #define _CMU_STATUS_HFXOAMPLOW_MASK                       0x2000000UL                                /**< Bit mask for CMU_HFXOAMPLOW */
5876 #define _CMU_STATUS_HFXOAMPLOW_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5877 #define CMU_STATUS_HFXOAMPLOW_DEFAULT                     (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25)     /**< Shifted mode DEFAULT for CMU_STATUS */
5878 #define CMU_STATUS_LFXOPHASE                              (0x1UL << 27)                              /**< LFXO Clock Phase */
5879 #define _CMU_STATUS_LFXOPHASE_SHIFT                       27                                         /**< Shift value for CMU_LFXOPHASE */
5880 #define _CMU_STATUS_LFXOPHASE_MASK                        0x8000000UL                                /**< Bit mask for CMU_LFXOPHASE */
5881 #define _CMU_STATUS_LFXOPHASE_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5882 #define CMU_STATUS_LFXOPHASE_DEFAULT                      (_CMU_STATUS_LFXOPHASE_DEFAULT << 27)      /**< Shifted mode DEFAULT for CMU_STATUS */
5883 #define CMU_STATUS_LFRCOPHASE                             (0x1UL << 28)                              /**< LFRCO Clock Phase */
5884 #define _CMU_STATUS_LFRCOPHASE_SHIFT                      28                                         /**< Shift value for CMU_LFRCOPHASE */
5885 #define _CMU_STATUS_LFRCOPHASE_MASK                       0x10000000UL                               /**< Bit mask for CMU_LFRCOPHASE */
5886 #define _CMU_STATUS_LFRCOPHASE_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5887 #define CMU_STATUS_LFRCOPHASE_DEFAULT                     (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28)     /**< Shifted mode DEFAULT for CMU_STATUS */
5888 #define CMU_STATUS_ULFRCOPHASE                            (0x1UL << 29)                              /**< ULFRCO Clock Phase */
5889 #define _CMU_STATUS_ULFRCOPHASE_SHIFT                     29                                         /**< Shift value for CMU_ULFRCOPHASE */
5890 #define _CMU_STATUS_ULFRCOPHASE_MASK                      0x20000000UL                               /**< Bit mask for CMU_ULFRCOPHASE */
5891 #define _CMU_STATUS_ULFRCOPHASE_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_STATUS */
5892 #define CMU_STATUS_ULFRCOPHASE_DEFAULT                    (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29)    /**< Shifted mode DEFAULT for CMU_STATUS */
5893 
5894 /* Bit fields for CMU HFCLKSTATUS */
5895 #define _CMU_HFCLKSTATUS_RESETVALUE                       0x00000001UL                               /**< Default value for CMU_HFCLKSTATUS */
5896 #define _CMU_HFCLKSTATUS_MASK                             0x00000007UL                               /**< Mask for CMU_HFCLKSTATUS */
5897 #define _CMU_HFCLKSTATUS_SELECTED_SHIFT                   0                                          /**< Shift value for CMU_SELECTED */
5898 #define _CMU_HFCLKSTATUS_SELECTED_MASK                    0x7UL                                      /**< Bit mask for CMU_SELECTED */
5899 #define _CMU_HFCLKSTATUS_SELECTED_DEFAULT                 0x00000001UL                               /**< Mode DEFAULT for CMU_HFCLKSTATUS */
5900 #define _CMU_HFCLKSTATUS_SELECTED_HFRCO                   0x00000001UL                               /**< Mode HFRCO for CMU_HFCLKSTATUS */
5901 #define _CMU_HFCLKSTATUS_SELECTED_HFXO                    0x00000002UL                               /**< Mode HFXO for CMU_HFCLKSTATUS */
5902 #define _CMU_HFCLKSTATUS_SELECTED_LFRCO                   0x00000003UL                               /**< Mode LFRCO for CMU_HFCLKSTATUS */
5903 #define _CMU_HFCLKSTATUS_SELECTED_LFXO                    0x00000004UL                               /**< Mode LFXO for CMU_HFCLKSTATUS */
5904 #define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2               0x00000005UL                               /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */
5905 #define _CMU_HFCLKSTATUS_SELECTED_USHFRCO                 0x00000006UL                               /**< Mode USHFRCO for CMU_HFCLKSTATUS */
5906 #define _CMU_HFCLKSTATUS_SELECTED_CLKIN0                  0x00000007UL                               /**< Mode CLKIN0 for CMU_HFCLKSTATUS */
5907 #define CMU_HFCLKSTATUS_SELECTED_DEFAULT                  (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0)   /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */
5908 #define CMU_HFCLKSTATUS_SELECTED_HFRCO                    (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0)     /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */
5909 #define CMU_HFCLKSTATUS_SELECTED_HFXO                     (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0)      /**< Shifted mode HFXO for CMU_HFCLKSTATUS */
5910 #define CMU_HFCLKSTATUS_SELECTED_LFRCO                    (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0)     /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */
5911 #define CMU_HFCLKSTATUS_SELECTED_LFXO                     (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0)      /**< Shifted mode LFXO for CMU_HFCLKSTATUS */
5912 #define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2                (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */
5913 #define CMU_HFCLKSTATUS_SELECTED_USHFRCO                  (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0)   /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */
5914 #define CMU_HFCLKSTATUS_SELECTED_CLKIN0                   (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0)    /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */
5915 
5916 /* Bit fields for CMU HFXOTRIMSTATUS */
5917 #define _CMU_HFXOTRIMSTATUS_RESETVALUE                    0x00000000UL                                        /**< Default value for CMU_HFXOTRIMSTATUS */
5918 #define _CMU_HFXOTRIMSTATUS_MASK                          0xC7FF07FFUL                                        /**< Mask for CMU_HFXOTRIMSTATUS */
5919 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT            0                                                   /**< Shift value for CMU_IBTRIMXOCORE */
5920 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK             0x7FFUL                                             /**< Bit mask for CMU_IBTRIMXOCORE */
5921 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT          0x00000000UL                                        /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */
5922 #define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT           (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */
5923 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT         16                                                  /**< Shift value for CMU_IBTRIMXOCOREMON */
5924 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK          0x7FF0000UL                                         /**< Bit mask for CMU_IBTRIMXOCOREMON */
5925 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT       0x00000000UL                                        /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */
5926 #define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT        (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */
5927 #define CMU_HFXOTRIMSTATUS_VALID                          (0x1UL << 30)                                       /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */
5928 #define _CMU_HFXOTRIMSTATUS_VALID_SHIFT                   30                                                  /**< Shift value for CMU_VALID */
5929 #define _CMU_HFXOTRIMSTATUS_VALID_MASK                    0x40000000UL                                        /**< Bit mask for CMU_VALID */
5930 #define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT                 0x00000000UL                                        /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */
5931 #define CMU_HFXOTRIMSTATUS_VALID_DEFAULT                  (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30)           /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */
5932 #define CMU_HFXOTRIMSTATUS_MONVALID                       (0x1UL << 31)                                       /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */
5933 #define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT                31                                                  /**< Shift value for CMU_MONVALID */
5934 #define _CMU_HFXOTRIMSTATUS_MONVALID_MASK                 0x80000000UL                                        /**< Bit mask for CMU_MONVALID */
5935 #define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT              0x00000000UL                                        /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */
5936 #define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT               (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31)        /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */
5937 
5938 /* Bit fields for CMU IF */
5939 #define _CMU_IF_RESETVALUE                                0x00000001UL                             /**< Default value for CMU_IF */
5940 #define _CMU_IF_MASK                                      0xB803EBFFUL                             /**< Mask for CMU_IF */
5941 #define CMU_IF_HFRCORDY                                   (0x1UL << 0)                             /**< HFRCO Ready Interrupt Flag */
5942 #define _CMU_IF_HFRCORDY_SHIFT                            0                                        /**< Shift value for CMU_HFRCORDY */
5943 #define _CMU_IF_HFRCORDY_MASK                             0x1UL                                    /**< Bit mask for CMU_HFRCORDY */
5944 #define _CMU_IF_HFRCORDY_DEFAULT                          0x00000001UL                             /**< Mode DEFAULT for CMU_IF */
5945 #define CMU_IF_HFRCORDY_DEFAULT                           (_CMU_IF_HFRCORDY_DEFAULT << 0)          /**< Shifted mode DEFAULT for CMU_IF */
5946 #define CMU_IF_HFXORDY                                    (0x1UL << 1)                             /**< HFXO Ready Interrupt Flag */
5947 #define _CMU_IF_HFXORDY_SHIFT                             1                                        /**< Shift value for CMU_HFXORDY */
5948 #define _CMU_IF_HFXORDY_MASK                              0x2UL                                    /**< Bit mask for CMU_HFXORDY */
5949 #define _CMU_IF_HFXORDY_DEFAULT                           0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
5950 #define CMU_IF_HFXORDY_DEFAULT                            (_CMU_IF_HFXORDY_DEFAULT << 1)           /**< Shifted mode DEFAULT for CMU_IF */
5951 #define CMU_IF_LFRCORDY                                   (0x1UL << 2)                             /**< LFRCO Ready Interrupt Flag */
5952 #define _CMU_IF_LFRCORDY_SHIFT                            2                                        /**< Shift value for CMU_LFRCORDY */
5953 #define _CMU_IF_LFRCORDY_MASK                             0x4UL                                    /**< Bit mask for CMU_LFRCORDY */
5954 #define _CMU_IF_LFRCORDY_DEFAULT                          0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
5955 #define CMU_IF_LFRCORDY_DEFAULT                           (_CMU_IF_LFRCORDY_DEFAULT << 2)          /**< Shifted mode DEFAULT for CMU_IF */
5956 #define CMU_IF_LFXORDY                                    (0x1UL << 3)                             /**< LFXO Ready Interrupt Flag */
5957 #define _CMU_IF_LFXORDY_SHIFT                             3                                        /**< Shift value for CMU_LFXORDY */
5958 #define _CMU_IF_LFXORDY_MASK                              0x8UL                                    /**< Bit mask for CMU_LFXORDY */
5959 #define _CMU_IF_LFXORDY_DEFAULT                           0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
5960 #define CMU_IF_LFXORDY_DEFAULT                            (_CMU_IF_LFXORDY_DEFAULT << 3)           /**< Shifted mode DEFAULT for CMU_IF */
5961 #define CMU_IF_AUXHFRCORDY                                (0x1UL << 4)                             /**< AUXHFRCO Ready Interrupt Flag */
5962 #define _CMU_IF_AUXHFRCORDY_SHIFT                         4                                        /**< Shift value for CMU_AUXHFRCORDY */
5963 #define _CMU_IF_AUXHFRCORDY_MASK                          0x10UL                                   /**< Bit mask for CMU_AUXHFRCORDY */
5964 #define _CMU_IF_AUXHFRCORDY_DEFAULT                       0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
5965 #define CMU_IF_AUXHFRCORDY_DEFAULT                        (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)       /**< Shifted mode DEFAULT for CMU_IF */
5966 #define CMU_IF_CALRDY                                     (0x1UL << 5)                             /**< Calibration Ready Interrupt Flag */
5967 #define _CMU_IF_CALRDY_SHIFT                              5                                        /**< Shift value for CMU_CALRDY */
5968 #define _CMU_IF_CALRDY_MASK                               0x20UL                                   /**< Bit mask for CMU_CALRDY */
5969 #define _CMU_IF_CALRDY_DEFAULT                            0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
5970 #define CMU_IF_CALRDY_DEFAULT                             (_CMU_IF_CALRDY_DEFAULT << 5)            /**< Shifted mode DEFAULT for CMU_IF */
5971 #define CMU_IF_CALOF                                      (0x1UL << 6)                             /**< Calibration Overflow Interrupt Flag */
5972 #define _CMU_IF_CALOF_SHIFT                               6                                        /**< Shift value for CMU_CALOF */
5973 #define _CMU_IF_CALOF_MASK                                0x40UL                                   /**< Bit mask for CMU_CALOF */
5974 #define _CMU_IF_CALOF_DEFAULT                             0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
5975 #define CMU_IF_CALOF_DEFAULT                              (_CMU_IF_CALOF_DEFAULT << 6)             /**< Shifted mode DEFAULT for CMU_IF */
5976 #define CMU_IF_USHFRCORDY                                 (0x1UL << 7)                             /**< USHFRCO Ready Interrupt Flag */
5977 #define _CMU_IF_USHFRCORDY_SHIFT                          7                                        /**< Shift value for CMU_USHFRCORDY */
5978 #define _CMU_IF_USHFRCORDY_MASK                           0x80UL                                   /**< Bit mask for CMU_USHFRCORDY */
5979 #define _CMU_IF_USHFRCORDY_DEFAULT                        0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
5980 #define CMU_IF_USHFRCORDY_DEFAULT                         (_CMU_IF_USHFRCORDY_DEFAULT << 7)        /**< Shifted mode DEFAULT for CMU_IF */
5981 #define CMU_IF_HFXODISERR                                 (0x1UL << 8)                             /**< HFXO Disable Error Interrupt Flag */
5982 #define _CMU_IF_HFXODISERR_SHIFT                          8                                        /**< Shift value for CMU_HFXODISERR */
5983 #define _CMU_IF_HFXODISERR_MASK                           0x100UL                                  /**< Bit mask for CMU_HFXODISERR */
5984 #define _CMU_IF_HFXODISERR_DEFAULT                        0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
5985 #define CMU_IF_HFXODISERR_DEFAULT                         (_CMU_IF_HFXODISERR_DEFAULT << 8)        /**< Shifted mode DEFAULT for CMU_IF */
5986 #define CMU_IF_HFXOAUTOSW                                 (0x1UL << 9)                             /**< HFXO Automatic Switch Interrupt Flag */
5987 #define _CMU_IF_HFXOAUTOSW_SHIFT                          9                                        /**< Shift value for CMU_HFXOAUTOSW */
5988 #define _CMU_IF_HFXOAUTOSW_MASK                           0x200UL                                  /**< Bit mask for CMU_HFXOAUTOSW */
5989 #define _CMU_IF_HFXOAUTOSW_DEFAULT                        0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
5990 #define CMU_IF_HFXOAUTOSW_DEFAULT                         (_CMU_IF_HFXOAUTOSW_DEFAULT << 9)        /**< Shifted mode DEFAULT for CMU_IF */
5991 #define CMU_IF_HFXOPEAKDETRDY                             (0x1UL << 11)                            /**< HFXO Automatic Peak Detection Ready Interrupt Flag */
5992 #define _CMU_IF_HFXOPEAKDETRDY_SHIFT                      11                                       /**< Shift value for CMU_HFXOPEAKDETRDY */
5993 #define _CMU_IF_HFXOPEAKDETRDY_MASK                       0x800UL                                  /**< Bit mask for CMU_HFXOPEAKDETRDY */
5994 #define _CMU_IF_HFXOPEAKDETRDY_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
5995 #define CMU_IF_HFXOPEAKDETRDY_DEFAULT                     (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11)   /**< Shifted mode DEFAULT for CMU_IF */
5996 #define CMU_IF_HFRCODIS                                   (0x1UL << 13)                            /**< HFRCO Disable Interrupt Flag */
5997 #define _CMU_IF_HFRCODIS_SHIFT                            13                                       /**< Shift value for CMU_HFRCODIS */
5998 #define _CMU_IF_HFRCODIS_MASK                             0x2000UL                                 /**< Bit mask for CMU_HFRCODIS */
5999 #define _CMU_IF_HFRCODIS_DEFAULT                          0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
6000 #define CMU_IF_HFRCODIS_DEFAULT                           (_CMU_IF_HFRCODIS_DEFAULT << 13)         /**< Shifted mode DEFAULT for CMU_IF */
6001 #define CMU_IF_LFTIMEOUTERR                               (0x1UL << 14)                            /**< Low Frequency Timeout Error Interrupt Flag */
6002 #define _CMU_IF_LFTIMEOUTERR_SHIFT                        14                                       /**< Shift value for CMU_LFTIMEOUTERR */
6003 #define _CMU_IF_LFTIMEOUTERR_MASK                         0x4000UL                                 /**< Bit mask for CMU_LFTIMEOUTERR */
6004 #define _CMU_IF_LFTIMEOUTERR_DEFAULT                      0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
6005 #define CMU_IF_LFTIMEOUTERR_DEFAULT                       (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14)     /**< Shifted mode DEFAULT for CMU_IF */
6006 #define CMU_IF_DPLLRDY                                    (0x1UL << 15)                            /**< DPLL Lock Interrupt Flag */
6007 #define _CMU_IF_DPLLRDY_SHIFT                             15                                       /**< Shift value for CMU_DPLLRDY */
6008 #define _CMU_IF_DPLLRDY_MASK                              0x8000UL                                 /**< Bit mask for CMU_DPLLRDY */
6009 #define _CMU_IF_DPLLRDY_DEFAULT                           0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
6010 #define CMU_IF_DPLLRDY_DEFAULT                            (_CMU_IF_DPLLRDY_DEFAULT << 15)          /**< Shifted mode DEFAULT for CMU_IF */
6011 #define CMU_IF_DPLLLOCKFAILLOW                            (0x1UL << 16)                            /**< DPLL Lock Failure Low Interrupt Flag */
6012 #define _CMU_IF_DPLLLOCKFAILLOW_SHIFT                     16                                       /**< Shift value for CMU_DPLLLOCKFAILLOW */
6013 #define _CMU_IF_DPLLLOCKFAILLOW_MASK                      0x10000UL                                /**< Bit mask for CMU_DPLLLOCKFAILLOW */
6014 #define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT                   0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
6015 #define CMU_IF_DPLLLOCKFAILLOW_DEFAULT                    (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16)  /**< Shifted mode DEFAULT for CMU_IF */
6016 #define CMU_IF_DPLLLOCKFAILHIGH                           (0x1UL << 17)                            /**< DPLL Lock Failure Low Interrupt Flag */
6017 #define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT                    17                                       /**< Shift value for CMU_DPLLLOCKFAILHIGH */
6018 #define _CMU_IF_DPLLLOCKFAILHIGH_MASK                     0x20000UL                                /**< Bit mask for CMU_DPLLLOCKFAILHIGH */
6019 #define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
6020 #define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT                   (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */
6021 #define CMU_IF_LFXOEDGE                                   (0x1UL << 27)                            /**< LFXO Clock Edge Detected Interrupt Flag */
6022 #define _CMU_IF_LFXOEDGE_SHIFT                            27                                       /**< Shift value for CMU_LFXOEDGE */
6023 #define _CMU_IF_LFXOEDGE_MASK                             0x8000000UL                              /**< Bit mask for CMU_LFXOEDGE */
6024 #define _CMU_IF_LFXOEDGE_DEFAULT                          0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
6025 #define CMU_IF_LFXOEDGE_DEFAULT                           (_CMU_IF_LFXOEDGE_DEFAULT << 27)         /**< Shifted mode DEFAULT for CMU_IF */
6026 #define CMU_IF_LFRCOEDGE                                  (0x1UL << 28)                            /**< LFRCO Clock Edge Detected Interrupt Flag */
6027 #define _CMU_IF_LFRCOEDGE_SHIFT                           28                                       /**< Shift value for CMU_LFRCOEDGE */
6028 #define _CMU_IF_LFRCOEDGE_MASK                            0x10000000UL                             /**< Bit mask for CMU_LFRCOEDGE */
6029 #define _CMU_IF_LFRCOEDGE_DEFAULT                         0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
6030 #define CMU_IF_LFRCOEDGE_DEFAULT                          (_CMU_IF_LFRCOEDGE_DEFAULT << 28)        /**< Shifted mode DEFAULT for CMU_IF */
6031 #define CMU_IF_ULFRCOEDGE                                 (0x1UL << 29)                            /**< ULFRCO Clock Edge Detected Interrupt Flag */
6032 #define _CMU_IF_ULFRCOEDGE_SHIFT                          29                                       /**< Shift value for CMU_ULFRCOEDGE */
6033 #define _CMU_IF_ULFRCOEDGE_MASK                           0x20000000UL                             /**< Bit mask for CMU_ULFRCOEDGE */
6034 #define _CMU_IF_ULFRCOEDGE_DEFAULT                        0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
6035 #define CMU_IF_ULFRCOEDGE_DEFAULT                         (_CMU_IF_ULFRCOEDGE_DEFAULT << 29)       /**< Shifted mode DEFAULT for CMU_IF */
6036 #define CMU_IF_CMUERR                                     (0x1UL << 31)                            /**< CMU Error Interrupt Flag */
6037 #define _CMU_IF_CMUERR_SHIFT                              31                                       /**< Shift value for CMU_CMUERR */
6038 #define _CMU_IF_CMUERR_MASK                               0x80000000UL                             /**< Bit mask for CMU_CMUERR */
6039 #define _CMU_IF_CMUERR_DEFAULT                            0x00000000UL                             /**< Mode DEFAULT for CMU_IF */
6040 #define CMU_IF_CMUERR_DEFAULT                             (_CMU_IF_CMUERR_DEFAULT << 31)           /**< Shifted mode DEFAULT for CMU_IF */
6041 
6042 /* Bit fields for CMU IFS */
6043 #define _CMU_IFS_RESETVALUE                               0x00000000UL                              /**< Default value for CMU_IFS */
6044 #define _CMU_IFS_MASK                                     0xB803EBFFUL                              /**< Mask for CMU_IFS */
6045 #define CMU_IFS_HFRCORDY                                  (0x1UL << 0)                              /**< Set HFRCORDY Interrupt Flag */
6046 #define _CMU_IFS_HFRCORDY_SHIFT                           0                                         /**< Shift value for CMU_HFRCORDY */
6047 #define _CMU_IFS_HFRCORDY_MASK                            0x1UL                                     /**< Bit mask for CMU_HFRCORDY */
6048 #define _CMU_IFS_HFRCORDY_DEFAULT                         0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6049 #define CMU_IFS_HFRCORDY_DEFAULT                          (_CMU_IFS_HFRCORDY_DEFAULT << 0)          /**< Shifted mode DEFAULT for CMU_IFS */
6050 #define CMU_IFS_HFXORDY                                   (0x1UL << 1)                              /**< Set HFXORDY Interrupt Flag */
6051 #define _CMU_IFS_HFXORDY_SHIFT                            1                                         /**< Shift value for CMU_HFXORDY */
6052 #define _CMU_IFS_HFXORDY_MASK                             0x2UL                                     /**< Bit mask for CMU_HFXORDY */
6053 #define _CMU_IFS_HFXORDY_DEFAULT                          0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6054 #define CMU_IFS_HFXORDY_DEFAULT                           (_CMU_IFS_HFXORDY_DEFAULT << 1)           /**< Shifted mode DEFAULT for CMU_IFS */
6055 #define CMU_IFS_LFRCORDY                                  (0x1UL << 2)                              /**< Set LFRCORDY Interrupt Flag */
6056 #define _CMU_IFS_LFRCORDY_SHIFT                           2                                         /**< Shift value for CMU_LFRCORDY */
6057 #define _CMU_IFS_LFRCORDY_MASK                            0x4UL                                     /**< Bit mask for CMU_LFRCORDY */
6058 #define _CMU_IFS_LFRCORDY_DEFAULT                         0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6059 #define CMU_IFS_LFRCORDY_DEFAULT                          (_CMU_IFS_LFRCORDY_DEFAULT << 2)          /**< Shifted mode DEFAULT for CMU_IFS */
6060 #define CMU_IFS_LFXORDY                                   (0x1UL << 3)                              /**< Set LFXORDY Interrupt Flag */
6061 #define _CMU_IFS_LFXORDY_SHIFT                            3                                         /**< Shift value for CMU_LFXORDY */
6062 #define _CMU_IFS_LFXORDY_MASK                             0x8UL                                     /**< Bit mask for CMU_LFXORDY */
6063 #define _CMU_IFS_LFXORDY_DEFAULT                          0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6064 #define CMU_IFS_LFXORDY_DEFAULT                           (_CMU_IFS_LFXORDY_DEFAULT << 3)           /**< Shifted mode DEFAULT for CMU_IFS */
6065 #define CMU_IFS_AUXHFRCORDY                               (0x1UL << 4)                              /**< Set AUXHFRCORDY Interrupt Flag */
6066 #define _CMU_IFS_AUXHFRCORDY_SHIFT                        4                                         /**< Shift value for CMU_AUXHFRCORDY */
6067 #define _CMU_IFS_AUXHFRCORDY_MASK                         0x10UL                                    /**< Bit mask for CMU_AUXHFRCORDY */
6068 #define _CMU_IFS_AUXHFRCORDY_DEFAULT                      0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6069 #define CMU_IFS_AUXHFRCORDY_DEFAULT                       (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)       /**< Shifted mode DEFAULT for CMU_IFS */
6070 #define CMU_IFS_CALRDY                                    (0x1UL << 5)                              /**< Set CALRDY Interrupt Flag */
6071 #define _CMU_IFS_CALRDY_SHIFT                             5                                         /**< Shift value for CMU_CALRDY */
6072 #define _CMU_IFS_CALRDY_MASK                              0x20UL                                    /**< Bit mask for CMU_CALRDY */
6073 #define _CMU_IFS_CALRDY_DEFAULT                           0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6074 #define CMU_IFS_CALRDY_DEFAULT                            (_CMU_IFS_CALRDY_DEFAULT << 5)            /**< Shifted mode DEFAULT for CMU_IFS */
6075 #define CMU_IFS_CALOF                                     (0x1UL << 6)                              /**< Set CALOF Interrupt Flag */
6076 #define _CMU_IFS_CALOF_SHIFT                              6                                         /**< Shift value for CMU_CALOF */
6077 #define _CMU_IFS_CALOF_MASK                               0x40UL                                    /**< Bit mask for CMU_CALOF */
6078 #define _CMU_IFS_CALOF_DEFAULT                            0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6079 #define CMU_IFS_CALOF_DEFAULT                             (_CMU_IFS_CALOF_DEFAULT << 6)             /**< Shifted mode DEFAULT for CMU_IFS */
6080 #define CMU_IFS_USHFRCORDY                                (0x1UL << 7)                              /**< Set USHFRCORDY Interrupt Flag */
6081 #define _CMU_IFS_USHFRCORDY_SHIFT                         7                                         /**< Shift value for CMU_USHFRCORDY */
6082 #define _CMU_IFS_USHFRCORDY_MASK                          0x80UL                                    /**< Bit mask for CMU_USHFRCORDY */
6083 #define _CMU_IFS_USHFRCORDY_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6084 #define CMU_IFS_USHFRCORDY_DEFAULT                        (_CMU_IFS_USHFRCORDY_DEFAULT << 7)        /**< Shifted mode DEFAULT for CMU_IFS */
6085 #define CMU_IFS_HFXODISERR                                (0x1UL << 8)                              /**< Set HFXODISERR Interrupt Flag */
6086 #define _CMU_IFS_HFXODISERR_SHIFT                         8                                         /**< Shift value for CMU_HFXODISERR */
6087 #define _CMU_IFS_HFXODISERR_MASK                          0x100UL                                   /**< Bit mask for CMU_HFXODISERR */
6088 #define _CMU_IFS_HFXODISERR_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6089 #define CMU_IFS_HFXODISERR_DEFAULT                        (_CMU_IFS_HFXODISERR_DEFAULT << 8)        /**< Shifted mode DEFAULT for CMU_IFS */
6090 #define CMU_IFS_HFXOAUTOSW                                (0x1UL << 9)                              /**< Set HFXOAUTOSW Interrupt Flag */
6091 #define _CMU_IFS_HFXOAUTOSW_SHIFT                         9                                         /**< Shift value for CMU_HFXOAUTOSW */
6092 #define _CMU_IFS_HFXOAUTOSW_MASK                          0x200UL                                   /**< Bit mask for CMU_HFXOAUTOSW */
6093 #define _CMU_IFS_HFXOAUTOSW_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6094 #define CMU_IFS_HFXOAUTOSW_DEFAULT                        (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9)        /**< Shifted mode DEFAULT for CMU_IFS */
6095 #define CMU_IFS_HFXOPEAKDETRDY                            (0x1UL << 11)                             /**< Set HFXOPEAKDETRDY Interrupt Flag */
6096 #define _CMU_IFS_HFXOPEAKDETRDY_SHIFT                     11                                        /**< Shift value for CMU_HFXOPEAKDETRDY */
6097 #define _CMU_IFS_HFXOPEAKDETRDY_MASK                      0x800UL                                   /**< Bit mask for CMU_HFXOPEAKDETRDY */
6098 #define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6099 #define CMU_IFS_HFXOPEAKDETRDY_DEFAULT                    (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11)   /**< Shifted mode DEFAULT for CMU_IFS */
6100 #define CMU_IFS_HFRCODIS                                  (0x1UL << 13)                             /**< Set HFRCODIS Interrupt Flag */
6101 #define _CMU_IFS_HFRCODIS_SHIFT                           13                                        /**< Shift value for CMU_HFRCODIS */
6102 #define _CMU_IFS_HFRCODIS_MASK                            0x2000UL                                  /**< Bit mask for CMU_HFRCODIS */
6103 #define _CMU_IFS_HFRCODIS_DEFAULT                         0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6104 #define CMU_IFS_HFRCODIS_DEFAULT                          (_CMU_IFS_HFRCODIS_DEFAULT << 13)         /**< Shifted mode DEFAULT for CMU_IFS */
6105 #define CMU_IFS_LFTIMEOUTERR                              (0x1UL << 14)                             /**< Set LFTIMEOUTERR Interrupt Flag */
6106 #define _CMU_IFS_LFTIMEOUTERR_SHIFT                       14                                        /**< Shift value for CMU_LFTIMEOUTERR */
6107 #define _CMU_IFS_LFTIMEOUTERR_MASK                        0x4000UL                                  /**< Bit mask for CMU_LFTIMEOUTERR */
6108 #define _CMU_IFS_LFTIMEOUTERR_DEFAULT                     0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6109 #define CMU_IFS_LFTIMEOUTERR_DEFAULT                      (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14)     /**< Shifted mode DEFAULT for CMU_IFS */
6110 #define CMU_IFS_DPLLRDY                                   (0x1UL << 15)                             /**< Set DPLLRDY Interrupt Flag */
6111 #define _CMU_IFS_DPLLRDY_SHIFT                            15                                        /**< Shift value for CMU_DPLLRDY */
6112 #define _CMU_IFS_DPLLRDY_MASK                             0x8000UL                                  /**< Bit mask for CMU_DPLLRDY */
6113 #define _CMU_IFS_DPLLRDY_DEFAULT                          0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6114 #define CMU_IFS_DPLLRDY_DEFAULT                           (_CMU_IFS_DPLLRDY_DEFAULT << 15)          /**< Shifted mode DEFAULT for CMU_IFS */
6115 #define CMU_IFS_DPLLLOCKFAILLOW                           (0x1UL << 16)                             /**< Set DPLLLOCKFAILLOW Interrupt Flag */
6116 #define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT                    16                                        /**< Shift value for CMU_DPLLLOCKFAILLOW */
6117 #define _CMU_IFS_DPLLLOCKFAILLOW_MASK                     0x10000UL                                 /**< Bit mask for CMU_DPLLLOCKFAILLOW */
6118 #define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT                  0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6119 #define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT                   (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16)  /**< Shifted mode DEFAULT for CMU_IFS */
6120 #define CMU_IFS_DPLLLOCKFAILHIGH                          (0x1UL << 17)                             /**< Set DPLLLOCKFAILHIGH Interrupt Flag */
6121 #define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT                   17                                        /**< Shift value for CMU_DPLLLOCKFAILHIGH */
6122 #define _CMU_IFS_DPLLLOCKFAILHIGH_MASK                    0x20000UL                                 /**< Bit mask for CMU_DPLLLOCKFAILHIGH */
6123 #define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT                 0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6124 #define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT                  (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */
6125 #define CMU_IFS_LFXOEDGE                                  (0x1UL << 27)                             /**< Set LFXOEDGE Interrupt Flag */
6126 #define _CMU_IFS_LFXOEDGE_SHIFT                           27                                        /**< Shift value for CMU_LFXOEDGE */
6127 #define _CMU_IFS_LFXOEDGE_MASK                            0x8000000UL                               /**< Bit mask for CMU_LFXOEDGE */
6128 #define _CMU_IFS_LFXOEDGE_DEFAULT                         0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6129 #define CMU_IFS_LFXOEDGE_DEFAULT                          (_CMU_IFS_LFXOEDGE_DEFAULT << 27)         /**< Shifted mode DEFAULT for CMU_IFS */
6130 #define CMU_IFS_LFRCOEDGE                                 (0x1UL << 28)                             /**< Set LFRCOEDGE Interrupt Flag */
6131 #define _CMU_IFS_LFRCOEDGE_SHIFT                          28                                        /**< Shift value for CMU_LFRCOEDGE */
6132 #define _CMU_IFS_LFRCOEDGE_MASK                           0x10000000UL                              /**< Bit mask for CMU_LFRCOEDGE */
6133 #define _CMU_IFS_LFRCOEDGE_DEFAULT                        0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6134 #define CMU_IFS_LFRCOEDGE_DEFAULT                         (_CMU_IFS_LFRCOEDGE_DEFAULT << 28)        /**< Shifted mode DEFAULT for CMU_IFS */
6135 #define CMU_IFS_ULFRCOEDGE                                (0x1UL << 29)                             /**< Set ULFRCOEDGE Interrupt Flag */
6136 #define _CMU_IFS_ULFRCOEDGE_SHIFT                         29                                        /**< Shift value for CMU_ULFRCOEDGE */
6137 #define _CMU_IFS_ULFRCOEDGE_MASK                          0x20000000UL                              /**< Bit mask for CMU_ULFRCOEDGE */
6138 #define _CMU_IFS_ULFRCOEDGE_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6139 #define CMU_IFS_ULFRCOEDGE_DEFAULT                        (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29)       /**< Shifted mode DEFAULT for CMU_IFS */
6140 #define CMU_IFS_CMUERR                                    (0x1UL << 31)                             /**< Set CMUERR Interrupt Flag */
6141 #define _CMU_IFS_CMUERR_SHIFT                             31                                        /**< Shift value for CMU_CMUERR */
6142 #define _CMU_IFS_CMUERR_MASK                              0x80000000UL                              /**< Bit mask for CMU_CMUERR */
6143 #define _CMU_IFS_CMUERR_DEFAULT                           0x00000000UL                              /**< Mode DEFAULT for CMU_IFS */
6144 #define CMU_IFS_CMUERR_DEFAULT                            (_CMU_IFS_CMUERR_DEFAULT << 31)           /**< Shifted mode DEFAULT for CMU_IFS */
6145 
6146 /* Bit fields for CMU IFC */
6147 #define _CMU_IFC_RESETVALUE                               0x00000000UL                              /**< Default value for CMU_IFC */
6148 #define _CMU_IFC_MASK                                     0xB803EBFFUL                              /**< Mask for CMU_IFC */
6149 #define CMU_IFC_HFRCORDY                                  (0x1UL << 0)                              /**< Clear HFRCORDY Interrupt Flag */
6150 #define _CMU_IFC_HFRCORDY_SHIFT                           0                                         /**< Shift value for CMU_HFRCORDY */
6151 #define _CMU_IFC_HFRCORDY_MASK                            0x1UL                                     /**< Bit mask for CMU_HFRCORDY */
6152 #define _CMU_IFC_HFRCORDY_DEFAULT                         0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6153 #define CMU_IFC_HFRCORDY_DEFAULT                          (_CMU_IFC_HFRCORDY_DEFAULT << 0)          /**< Shifted mode DEFAULT for CMU_IFC */
6154 #define CMU_IFC_HFXORDY                                   (0x1UL << 1)                              /**< Clear HFXORDY Interrupt Flag */
6155 #define _CMU_IFC_HFXORDY_SHIFT                            1                                         /**< Shift value for CMU_HFXORDY */
6156 #define _CMU_IFC_HFXORDY_MASK                             0x2UL                                     /**< Bit mask for CMU_HFXORDY */
6157 #define _CMU_IFC_HFXORDY_DEFAULT                          0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6158 #define CMU_IFC_HFXORDY_DEFAULT                           (_CMU_IFC_HFXORDY_DEFAULT << 1)           /**< Shifted mode DEFAULT for CMU_IFC */
6159 #define CMU_IFC_LFRCORDY                                  (0x1UL << 2)                              /**< Clear LFRCORDY Interrupt Flag */
6160 #define _CMU_IFC_LFRCORDY_SHIFT                           2                                         /**< Shift value for CMU_LFRCORDY */
6161 #define _CMU_IFC_LFRCORDY_MASK                            0x4UL                                     /**< Bit mask for CMU_LFRCORDY */
6162 #define _CMU_IFC_LFRCORDY_DEFAULT                         0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6163 #define CMU_IFC_LFRCORDY_DEFAULT                          (_CMU_IFC_LFRCORDY_DEFAULT << 2)          /**< Shifted mode DEFAULT for CMU_IFC */
6164 #define CMU_IFC_LFXORDY                                   (0x1UL << 3)                              /**< Clear LFXORDY Interrupt Flag */
6165 #define _CMU_IFC_LFXORDY_SHIFT                            3                                         /**< Shift value for CMU_LFXORDY */
6166 #define _CMU_IFC_LFXORDY_MASK                             0x8UL                                     /**< Bit mask for CMU_LFXORDY */
6167 #define _CMU_IFC_LFXORDY_DEFAULT                          0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6168 #define CMU_IFC_LFXORDY_DEFAULT                           (_CMU_IFC_LFXORDY_DEFAULT << 3)           /**< Shifted mode DEFAULT for CMU_IFC */
6169 #define CMU_IFC_AUXHFRCORDY                               (0x1UL << 4)                              /**< Clear AUXHFRCORDY Interrupt Flag */
6170 #define _CMU_IFC_AUXHFRCORDY_SHIFT                        4                                         /**< Shift value for CMU_AUXHFRCORDY */
6171 #define _CMU_IFC_AUXHFRCORDY_MASK                         0x10UL                                    /**< Bit mask for CMU_AUXHFRCORDY */
6172 #define _CMU_IFC_AUXHFRCORDY_DEFAULT                      0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6173 #define CMU_IFC_AUXHFRCORDY_DEFAULT                       (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)       /**< Shifted mode DEFAULT for CMU_IFC */
6174 #define CMU_IFC_CALRDY                                    (0x1UL << 5)                              /**< Clear CALRDY Interrupt Flag */
6175 #define _CMU_IFC_CALRDY_SHIFT                             5                                         /**< Shift value for CMU_CALRDY */
6176 #define _CMU_IFC_CALRDY_MASK                              0x20UL                                    /**< Bit mask for CMU_CALRDY */
6177 #define _CMU_IFC_CALRDY_DEFAULT                           0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6178 #define CMU_IFC_CALRDY_DEFAULT                            (_CMU_IFC_CALRDY_DEFAULT << 5)            /**< Shifted mode DEFAULT for CMU_IFC */
6179 #define CMU_IFC_CALOF                                     (0x1UL << 6)                              /**< Clear CALOF Interrupt Flag */
6180 #define _CMU_IFC_CALOF_SHIFT                              6                                         /**< Shift value for CMU_CALOF */
6181 #define _CMU_IFC_CALOF_MASK                               0x40UL                                    /**< Bit mask for CMU_CALOF */
6182 #define _CMU_IFC_CALOF_DEFAULT                            0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6183 #define CMU_IFC_CALOF_DEFAULT                             (_CMU_IFC_CALOF_DEFAULT << 6)             /**< Shifted mode DEFAULT for CMU_IFC */
6184 #define CMU_IFC_USHFRCORDY                                (0x1UL << 7)                              /**< Clear USHFRCORDY Interrupt Flag */
6185 #define _CMU_IFC_USHFRCORDY_SHIFT                         7                                         /**< Shift value for CMU_USHFRCORDY */
6186 #define _CMU_IFC_USHFRCORDY_MASK                          0x80UL                                    /**< Bit mask for CMU_USHFRCORDY */
6187 #define _CMU_IFC_USHFRCORDY_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6188 #define CMU_IFC_USHFRCORDY_DEFAULT                        (_CMU_IFC_USHFRCORDY_DEFAULT << 7)        /**< Shifted mode DEFAULT for CMU_IFC */
6189 #define CMU_IFC_HFXODISERR                                (0x1UL << 8)                              /**< Clear HFXODISERR Interrupt Flag */
6190 #define _CMU_IFC_HFXODISERR_SHIFT                         8                                         /**< Shift value for CMU_HFXODISERR */
6191 #define _CMU_IFC_HFXODISERR_MASK                          0x100UL                                   /**< Bit mask for CMU_HFXODISERR */
6192 #define _CMU_IFC_HFXODISERR_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6193 #define CMU_IFC_HFXODISERR_DEFAULT                        (_CMU_IFC_HFXODISERR_DEFAULT << 8)        /**< Shifted mode DEFAULT for CMU_IFC */
6194 #define CMU_IFC_HFXOAUTOSW                                (0x1UL << 9)                              /**< Clear HFXOAUTOSW Interrupt Flag */
6195 #define _CMU_IFC_HFXOAUTOSW_SHIFT                         9                                         /**< Shift value for CMU_HFXOAUTOSW */
6196 #define _CMU_IFC_HFXOAUTOSW_MASK                          0x200UL                                   /**< Bit mask for CMU_HFXOAUTOSW */
6197 #define _CMU_IFC_HFXOAUTOSW_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6198 #define CMU_IFC_HFXOAUTOSW_DEFAULT                        (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9)        /**< Shifted mode DEFAULT for CMU_IFC */
6199 #define CMU_IFC_HFXOPEAKDETRDY                            (0x1UL << 11)                             /**< Clear HFXOPEAKDETRDY Interrupt Flag */
6200 #define _CMU_IFC_HFXOPEAKDETRDY_SHIFT                     11                                        /**< Shift value for CMU_HFXOPEAKDETRDY */
6201 #define _CMU_IFC_HFXOPEAKDETRDY_MASK                      0x800UL                                   /**< Bit mask for CMU_HFXOPEAKDETRDY */
6202 #define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6203 #define CMU_IFC_HFXOPEAKDETRDY_DEFAULT                    (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11)   /**< Shifted mode DEFAULT for CMU_IFC */
6204 #define CMU_IFC_HFRCODIS                                  (0x1UL << 13)                             /**< Clear HFRCODIS Interrupt Flag */
6205 #define _CMU_IFC_HFRCODIS_SHIFT                           13                                        /**< Shift value for CMU_HFRCODIS */
6206 #define _CMU_IFC_HFRCODIS_MASK                            0x2000UL                                  /**< Bit mask for CMU_HFRCODIS */
6207 #define _CMU_IFC_HFRCODIS_DEFAULT                         0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6208 #define CMU_IFC_HFRCODIS_DEFAULT                          (_CMU_IFC_HFRCODIS_DEFAULT << 13)         /**< Shifted mode DEFAULT for CMU_IFC */
6209 #define CMU_IFC_LFTIMEOUTERR                              (0x1UL << 14)                             /**< Clear LFTIMEOUTERR Interrupt Flag */
6210 #define _CMU_IFC_LFTIMEOUTERR_SHIFT                       14                                        /**< Shift value for CMU_LFTIMEOUTERR */
6211 #define _CMU_IFC_LFTIMEOUTERR_MASK                        0x4000UL                                  /**< Bit mask for CMU_LFTIMEOUTERR */
6212 #define _CMU_IFC_LFTIMEOUTERR_DEFAULT                     0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6213 #define CMU_IFC_LFTIMEOUTERR_DEFAULT                      (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14)     /**< Shifted mode DEFAULT for CMU_IFC */
6214 #define CMU_IFC_DPLLRDY                                   (0x1UL << 15)                             /**< Clear DPLLRDY Interrupt Flag */
6215 #define _CMU_IFC_DPLLRDY_SHIFT                            15                                        /**< Shift value for CMU_DPLLRDY */
6216 #define _CMU_IFC_DPLLRDY_MASK                             0x8000UL                                  /**< Bit mask for CMU_DPLLRDY */
6217 #define _CMU_IFC_DPLLRDY_DEFAULT                          0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6218 #define CMU_IFC_DPLLRDY_DEFAULT                           (_CMU_IFC_DPLLRDY_DEFAULT << 15)          /**< Shifted mode DEFAULT for CMU_IFC */
6219 #define CMU_IFC_DPLLLOCKFAILLOW                           (0x1UL << 16)                             /**< Clear DPLLLOCKFAILLOW Interrupt Flag */
6220 #define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT                    16                                        /**< Shift value for CMU_DPLLLOCKFAILLOW */
6221 #define _CMU_IFC_DPLLLOCKFAILLOW_MASK                     0x10000UL                                 /**< Bit mask for CMU_DPLLLOCKFAILLOW */
6222 #define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT                  0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6223 #define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT                   (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16)  /**< Shifted mode DEFAULT for CMU_IFC */
6224 #define CMU_IFC_DPLLLOCKFAILHIGH                          (0x1UL << 17)                             /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */
6225 #define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT                   17                                        /**< Shift value for CMU_DPLLLOCKFAILHIGH */
6226 #define _CMU_IFC_DPLLLOCKFAILHIGH_MASK                    0x20000UL                                 /**< Bit mask for CMU_DPLLLOCKFAILHIGH */
6227 #define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT                 0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6228 #define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT                  (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */
6229 #define CMU_IFC_LFXOEDGE                                  (0x1UL << 27)                             /**< Clear LFXOEDGE Interrupt Flag */
6230 #define _CMU_IFC_LFXOEDGE_SHIFT                           27                                        /**< Shift value for CMU_LFXOEDGE */
6231 #define _CMU_IFC_LFXOEDGE_MASK                            0x8000000UL                               /**< Bit mask for CMU_LFXOEDGE */
6232 #define _CMU_IFC_LFXOEDGE_DEFAULT                         0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6233 #define CMU_IFC_LFXOEDGE_DEFAULT                          (_CMU_IFC_LFXOEDGE_DEFAULT << 27)         /**< Shifted mode DEFAULT for CMU_IFC */
6234 #define CMU_IFC_LFRCOEDGE                                 (0x1UL << 28)                             /**< Clear LFRCOEDGE Interrupt Flag */
6235 #define _CMU_IFC_LFRCOEDGE_SHIFT                          28                                        /**< Shift value for CMU_LFRCOEDGE */
6236 #define _CMU_IFC_LFRCOEDGE_MASK                           0x10000000UL                              /**< Bit mask for CMU_LFRCOEDGE */
6237 #define _CMU_IFC_LFRCOEDGE_DEFAULT                        0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6238 #define CMU_IFC_LFRCOEDGE_DEFAULT                         (_CMU_IFC_LFRCOEDGE_DEFAULT << 28)        /**< Shifted mode DEFAULT for CMU_IFC */
6239 #define CMU_IFC_ULFRCOEDGE                                (0x1UL << 29)                             /**< Clear ULFRCOEDGE Interrupt Flag */
6240 #define _CMU_IFC_ULFRCOEDGE_SHIFT                         29                                        /**< Shift value for CMU_ULFRCOEDGE */
6241 #define _CMU_IFC_ULFRCOEDGE_MASK                          0x20000000UL                              /**< Bit mask for CMU_ULFRCOEDGE */
6242 #define _CMU_IFC_ULFRCOEDGE_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6243 #define CMU_IFC_ULFRCOEDGE_DEFAULT                        (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29)       /**< Shifted mode DEFAULT for CMU_IFC */
6244 #define CMU_IFC_CMUERR                                    (0x1UL << 31)                             /**< Clear CMUERR Interrupt Flag */
6245 #define _CMU_IFC_CMUERR_SHIFT                             31                                        /**< Shift value for CMU_CMUERR */
6246 #define _CMU_IFC_CMUERR_MASK                              0x80000000UL                              /**< Bit mask for CMU_CMUERR */
6247 #define _CMU_IFC_CMUERR_DEFAULT                           0x00000000UL                              /**< Mode DEFAULT for CMU_IFC */
6248 #define CMU_IFC_CMUERR_DEFAULT                            (_CMU_IFC_CMUERR_DEFAULT << 31)           /**< Shifted mode DEFAULT for CMU_IFC */
6249 
6250 /* Bit fields for CMU IEN */
6251 #define _CMU_IEN_RESETVALUE                               0x00000000UL                              /**< Default value for CMU_IEN */
6252 #define _CMU_IEN_MASK                                     0xB803EBFFUL                              /**< Mask for CMU_IEN */
6253 #define CMU_IEN_HFRCORDY                                  (0x1UL << 0)                              /**< HFRCORDY Interrupt Enable */
6254 #define _CMU_IEN_HFRCORDY_SHIFT                           0                                         /**< Shift value for CMU_HFRCORDY */
6255 #define _CMU_IEN_HFRCORDY_MASK                            0x1UL                                     /**< Bit mask for CMU_HFRCORDY */
6256 #define _CMU_IEN_HFRCORDY_DEFAULT                         0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6257 #define CMU_IEN_HFRCORDY_DEFAULT                          (_CMU_IEN_HFRCORDY_DEFAULT << 0)          /**< Shifted mode DEFAULT for CMU_IEN */
6258 #define CMU_IEN_HFXORDY                                   (0x1UL << 1)                              /**< HFXORDY Interrupt Enable */
6259 #define _CMU_IEN_HFXORDY_SHIFT                            1                                         /**< Shift value for CMU_HFXORDY */
6260 #define _CMU_IEN_HFXORDY_MASK                             0x2UL                                     /**< Bit mask for CMU_HFXORDY */
6261 #define _CMU_IEN_HFXORDY_DEFAULT                          0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6262 #define CMU_IEN_HFXORDY_DEFAULT                           (_CMU_IEN_HFXORDY_DEFAULT << 1)           /**< Shifted mode DEFAULT for CMU_IEN */
6263 #define CMU_IEN_LFRCORDY                                  (0x1UL << 2)                              /**< LFRCORDY Interrupt Enable */
6264 #define _CMU_IEN_LFRCORDY_SHIFT                           2                                         /**< Shift value for CMU_LFRCORDY */
6265 #define _CMU_IEN_LFRCORDY_MASK                            0x4UL                                     /**< Bit mask for CMU_LFRCORDY */
6266 #define _CMU_IEN_LFRCORDY_DEFAULT                         0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6267 #define CMU_IEN_LFRCORDY_DEFAULT                          (_CMU_IEN_LFRCORDY_DEFAULT << 2)          /**< Shifted mode DEFAULT for CMU_IEN */
6268 #define CMU_IEN_LFXORDY                                   (0x1UL << 3)                              /**< LFXORDY Interrupt Enable */
6269 #define _CMU_IEN_LFXORDY_SHIFT                            3                                         /**< Shift value for CMU_LFXORDY */
6270 #define _CMU_IEN_LFXORDY_MASK                             0x8UL                                     /**< Bit mask for CMU_LFXORDY */
6271 #define _CMU_IEN_LFXORDY_DEFAULT                          0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6272 #define CMU_IEN_LFXORDY_DEFAULT                           (_CMU_IEN_LFXORDY_DEFAULT << 3)           /**< Shifted mode DEFAULT for CMU_IEN */
6273 #define CMU_IEN_AUXHFRCORDY                               (0x1UL << 4)                              /**< AUXHFRCORDY Interrupt Enable */
6274 #define _CMU_IEN_AUXHFRCORDY_SHIFT                        4                                         /**< Shift value for CMU_AUXHFRCORDY */
6275 #define _CMU_IEN_AUXHFRCORDY_MASK                         0x10UL                                    /**< Bit mask for CMU_AUXHFRCORDY */
6276 #define _CMU_IEN_AUXHFRCORDY_DEFAULT                      0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6277 #define CMU_IEN_AUXHFRCORDY_DEFAULT                       (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)       /**< Shifted mode DEFAULT for CMU_IEN */
6278 #define CMU_IEN_CALRDY                                    (0x1UL << 5)                              /**< CALRDY Interrupt Enable */
6279 #define _CMU_IEN_CALRDY_SHIFT                             5                                         /**< Shift value for CMU_CALRDY */
6280 #define _CMU_IEN_CALRDY_MASK                              0x20UL                                    /**< Bit mask for CMU_CALRDY */
6281 #define _CMU_IEN_CALRDY_DEFAULT                           0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6282 #define CMU_IEN_CALRDY_DEFAULT                            (_CMU_IEN_CALRDY_DEFAULT << 5)            /**< Shifted mode DEFAULT for CMU_IEN */
6283 #define CMU_IEN_CALOF                                     (0x1UL << 6)                              /**< CALOF Interrupt Enable */
6284 #define _CMU_IEN_CALOF_SHIFT                              6                                         /**< Shift value for CMU_CALOF */
6285 #define _CMU_IEN_CALOF_MASK                               0x40UL                                    /**< Bit mask for CMU_CALOF */
6286 #define _CMU_IEN_CALOF_DEFAULT                            0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6287 #define CMU_IEN_CALOF_DEFAULT                             (_CMU_IEN_CALOF_DEFAULT << 6)             /**< Shifted mode DEFAULT for CMU_IEN */
6288 #define CMU_IEN_USHFRCORDY                                (0x1UL << 7)                              /**< USHFRCORDY Interrupt Enable */
6289 #define _CMU_IEN_USHFRCORDY_SHIFT                         7                                         /**< Shift value for CMU_USHFRCORDY */
6290 #define _CMU_IEN_USHFRCORDY_MASK                          0x80UL                                    /**< Bit mask for CMU_USHFRCORDY */
6291 #define _CMU_IEN_USHFRCORDY_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6292 #define CMU_IEN_USHFRCORDY_DEFAULT                        (_CMU_IEN_USHFRCORDY_DEFAULT << 7)        /**< Shifted mode DEFAULT for CMU_IEN */
6293 #define CMU_IEN_HFXODISERR                                (0x1UL << 8)                              /**< HFXODISERR Interrupt Enable */
6294 #define _CMU_IEN_HFXODISERR_SHIFT                         8                                         /**< Shift value for CMU_HFXODISERR */
6295 #define _CMU_IEN_HFXODISERR_MASK                          0x100UL                                   /**< Bit mask for CMU_HFXODISERR */
6296 #define _CMU_IEN_HFXODISERR_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6297 #define CMU_IEN_HFXODISERR_DEFAULT                        (_CMU_IEN_HFXODISERR_DEFAULT << 8)        /**< Shifted mode DEFAULT for CMU_IEN */
6298 #define CMU_IEN_HFXOAUTOSW                                (0x1UL << 9)                              /**< HFXOAUTOSW Interrupt Enable */
6299 #define _CMU_IEN_HFXOAUTOSW_SHIFT                         9                                         /**< Shift value for CMU_HFXOAUTOSW */
6300 #define _CMU_IEN_HFXOAUTOSW_MASK                          0x200UL                                   /**< Bit mask for CMU_HFXOAUTOSW */
6301 #define _CMU_IEN_HFXOAUTOSW_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6302 #define CMU_IEN_HFXOAUTOSW_DEFAULT                        (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9)        /**< Shifted mode DEFAULT for CMU_IEN */
6303 #define CMU_IEN_HFXOPEAKDETRDY                            (0x1UL << 11)                             /**< HFXOPEAKDETRDY Interrupt Enable */
6304 #define _CMU_IEN_HFXOPEAKDETRDY_SHIFT                     11                                        /**< Shift value for CMU_HFXOPEAKDETRDY */
6305 #define _CMU_IEN_HFXOPEAKDETRDY_MASK                      0x800UL                                   /**< Bit mask for CMU_HFXOPEAKDETRDY */
6306 #define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT                   0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6307 #define CMU_IEN_HFXOPEAKDETRDY_DEFAULT                    (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11)   /**< Shifted mode DEFAULT for CMU_IEN */
6308 #define CMU_IEN_HFRCODIS                                  (0x1UL << 13)                             /**< HFRCODIS Interrupt Enable */
6309 #define _CMU_IEN_HFRCODIS_SHIFT                           13                                        /**< Shift value for CMU_HFRCODIS */
6310 #define _CMU_IEN_HFRCODIS_MASK                            0x2000UL                                  /**< Bit mask for CMU_HFRCODIS */
6311 #define _CMU_IEN_HFRCODIS_DEFAULT                         0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6312 #define CMU_IEN_HFRCODIS_DEFAULT                          (_CMU_IEN_HFRCODIS_DEFAULT << 13)         /**< Shifted mode DEFAULT for CMU_IEN */
6313 #define CMU_IEN_LFTIMEOUTERR                              (0x1UL << 14)                             /**< LFTIMEOUTERR Interrupt Enable */
6314 #define _CMU_IEN_LFTIMEOUTERR_SHIFT                       14                                        /**< Shift value for CMU_LFTIMEOUTERR */
6315 #define _CMU_IEN_LFTIMEOUTERR_MASK                        0x4000UL                                  /**< Bit mask for CMU_LFTIMEOUTERR */
6316 #define _CMU_IEN_LFTIMEOUTERR_DEFAULT                     0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6317 #define CMU_IEN_LFTIMEOUTERR_DEFAULT                      (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14)     /**< Shifted mode DEFAULT for CMU_IEN */
6318 #define CMU_IEN_DPLLRDY                                   (0x1UL << 15)                             /**< DPLLRDY Interrupt Enable */
6319 #define _CMU_IEN_DPLLRDY_SHIFT                            15                                        /**< Shift value for CMU_DPLLRDY */
6320 #define _CMU_IEN_DPLLRDY_MASK                             0x8000UL                                  /**< Bit mask for CMU_DPLLRDY */
6321 #define _CMU_IEN_DPLLRDY_DEFAULT                          0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6322 #define CMU_IEN_DPLLRDY_DEFAULT                           (_CMU_IEN_DPLLRDY_DEFAULT << 15)          /**< Shifted mode DEFAULT for CMU_IEN */
6323 #define CMU_IEN_DPLLLOCKFAILLOW                           (0x1UL << 16)                             /**< DPLLLOCKFAILLOW Interrupt Enable */
6324 #define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT                    16                                        /**< Shift value for CMU_DPLLLOCKFAILLOW */
6325 #define _CMU_IEN_DPLLLOCKFAILLOW_MASK                     0x10000UL                                 /**< Bit mask for CMU_DPLLLOCKFAILLOW */
6326 #define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT                  0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6327 #define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT                   (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16)  /**< Shifted mode DEFAULT for CMU_IEN */
6328 #define CMU_IEN_DPLLLOCKFAILHIGH                          (0x1UL << 17)                             /**< DPLLLOCKFAILHIGH Interrupt Enable */
6329 #define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT                   17                                        /**< Shift value for CMU_DPLLLOCKFAILHIGH */
6330 #define _CMU_IEN_DPLLLOCKFAILHIGH_MASK                    0x20000UL                                 /**< Bit mask for CMU_DPLLLOCKFAILHIGH */
6331 #define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT                 0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6332 #define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT                  (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */
6333 #define CMU_IEN_LFXOEDGE                                  (0x1UL << 27)                             /**< LFXOEDGE Interrupt Enable */
6334 #define _CMU_IEN_LFXOEDGE_SHIFT                           27                                        /**< Shift value for CMU_LFXOEDGE */
6335 #define _CMU_IEN_LFXOEDGE_MASK                            0x8000000UL                               /**< Bit mask for CMU_LFXOEDGE */
6336 #define _CMU_IEN_LFXOEDGE_DEFAULT                         0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6337 #define CMU_IEN_LFXOEDGE_DEFAULT                          (_CMU_IEN_LFXOEDGE_DEFAULT << 27)         /**< Shifted mode DEFAULT for CMU_IEN */
6338 #define CMU_IEN_LFRCOEDGE                                 (0x1UL << 28)                             /**< LFRCOEDGE Interrupt Enable */
6339 #define _CMU_IEN_LFRCOEDGE_SHIFT                          28                                        /**< Shift value for CMU_LFRCOEDGE */
6340 #define _CMU_IEN_LFRCOEDGE_MASK                           0x10000000UL                              /**< Bit mask for CMU_LFRCOEDGE */
6341 #define _CMU_IEN_LFRCOEDGE_DEFAULT                        0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6342 #define CMU_IEN_LFRCOEDGE_DEFAULT                         (_CMU_IEN_LFRCOEDGE_DEFAULT << 28)        /**< Shifted mode DEFAULT for CMU_IEN */
6343 #define CMU_IEN_ULFRCOEDGE                                (0x1UL << 29)                             /**< ULFRCOEDGE Interrupt Enable */
6344 #define _CMU_IEN_ULFRCOEDGE_SHIFT                         29                                        /**< Shift value for CMU_ULFRCOEDGE */
6345 #define _CMU_IEN_ULFRCOEDGE_MASK                          0x20000000UL                              /**< Bit mask for CMU_ULFRCOEDGE */
6346 #define _CMU_IEN_ULFRCOEDGE_DEFAULT                       0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6347 #define CMU_IEN_ULFRCOEDGE_DEFAULT                        (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29)       /**< Shifted mode DEFAULT for CMU_IEN */
6348 #define CMU_IEN_CMUERR                                    (0x1UL << 31)                             /**< CMUERR Interrupt Enable */
6349 #define _CMU_IEN_CMUERR_SHIFT                             31                                        /**< Shift value for CMU_CMUERR */
6350 #define _CMU_IEN_CMUERR_MASK                              0x80000000UL                              /**< Bit mask for CMU_CMUERR */
6351 #define _CMU_IEN_CMUERR_DEFAULT                           0x00000000UL                              /**< Mode DEFAULT for CMU_IEN */
6352 #define CMU_IEN_CMUERR_DEFAULT                            (_CMU_IEN_CMUERR_DEFAULT << 31)           /**< Shifted mode DEFAULT for CMU_IEN */
6353 
6354 /* Bit fields for CMU HFBUSCLKEN0 */
6355 #define _CMU_HFBUSCLKEN0_RESETVALUE                       0x00000000UL                            /**< Default value for CMU_HFBUSCLKEN0 */
6356 #define _CMU_HFBUSCLKEN0_MASK                             0x000000F7UL                            /**< Mask for CMU_HFBUSCLKEN0 */
6357 #define CMU_HFBUSCLKEN0_LE                                (0x1UL << 0)                            /**< Low Energy Peripheral Interface Clock Enable */
6358 #define _CMU_HFBUSCLKEN0_LE_SHIFT                         0                                       /**< Shift value for CMU_LE */
6359 #define _CMU_HFBUSCLKEN0_LE_MASK                          0x1UL                                   /**< Bit mask for CMU_LE */
6360 #define _CMU_HFBUSCLKEN0_LE_DEFAULT                       0x00000000UL                            /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
6361 #define CMU_HFBUSCLKEN0_LE_DEFAULT                        (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0)      /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
6362 #define CMU_HFBUSCLKEN0_CRYPTO0                           (0x1UL << 1)                            /**< Advanced Encryption Standard Accelerator Clock Enable */
6363 #define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT                    1                                       /**< Shift value for CMU_CRYPTO0 */
6364 #define _CMU_HFBUSCLKEN0_CRYPTO0_MASK                     0x2UL                                   /**< Bit mask for CMU_CRYPTO0 */
6365 #define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT                  0x00000000UL                            /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
6366 #define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT                   (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
6367 #define CMU_HFBUSCLKEN0_EBI                               (0x1UL << 2)                            /**< External Bus Interface Clock Enable */
6368 #define _CMU_HFBUSCLKEN0_EBI_SHIFT                        2                                       /**< Shift value for CMU_EBI */
6369 #define _CMU_HFBUSCLKEN0_EBI_MASK                         0x4UL                                   /**< Bit mask for CMU_EBI */
6370 #define _CMU_HFBUSCLKEN0_EBI_DEFAULT                      0x00000000UL                            /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
6371 #define CMU_HFBUSCLKEN0_EBI_DEFAULT                       (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2)     /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
6372 #define CMU_HFBUSCLKEN0_GPIO                              (0x1UL << 4)                            /**< General purpose Input/Output Clock Enable */
6373 #define _CMU_HFBUSCLKEN0_GPIO_SHIFT                       4                                       /**< Shift value for CMU_GPIO */
6374 #define _CMU_HFBUSCLKEN0_GPIO_MASK                        0x10UL                                  /**< Bit mask for CMU_GPIO */
6375 #define _CMU_HFBUSCLKEN0_GPIO_DEFAULT                     0x00000000UL                            /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
6376 #define CMU_HFBUSCLKEN0_GPIO_DEFAULT                      (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 4)    /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
6377 #define CMU_HFBUSCLKEN0_PRS                               (0x1UL << 5)                            /**< Peripheral Reflex System Clock Enable */
6378 #define _CMU_HFBUSCLKEN0_PRS_SHIFT                        5                                       /**< Shift value for CMU_PRS */
6379 #define _CMU_HFBUSCLKEN0_PRS_MASK                         0x20UL                                  /**< Bit mask for CMU_PRS */
6380 #define _CMU_HFBUSCLKEN0_PRS_DEFAULT                      0x00000000UL                            /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
6381 #define CMU_HFBUSCLKEN0_PRS_DEFAULT                       (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 5)     /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
6382 #define CMU_HFBUSCLKEN0_LDMA                              (0x1UL << 6)                            /**< Linked Direct Memory Access Controller Clock Enable */
6383 #define _CMU_HFBUSCLKEN0_LDMA_SHIFT                       6                                       /**< Shift value for CMU_LDMA */
6384 #define _CMU_HFBUSCLKEN0_LDMA_MASK                        0x40UL                                  /**< Bit mask for CMU_LDMA */
6385 #define _CMU_HFBUSCLKEN0_LDMA_DEFAULT                     0x00000000UL                            /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
6386 #define CMU_HFBUSCLKEN0_LDMA_DEFAULT                      (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 6)    /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
6387 #define CMU_HFBUSCLKEN0_GPCRC                             (0x1UL << 7)                            /**< General Purpose CRC Clock Enable */
6388 #define _CMU_HFBUSCLKEN0_GPCRC_SHIFT                      7                                       /**< Shift value for CMU_GPCRC */
6389 #define _CMU_HFBUSCLKEN0_GPCRC_MASK                       0x80UL                                  /**< Bit mask for CMU_GPCRC */
6390 #define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT                    0x00000000UL                            /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */
6391 #define CMU_HFBUSCLKEN0_GPCRC_DEFAULT                     (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 7)   /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */
6392 
6393 /* Bit fields for CMU HFPERCLKEN0 */
6394 #define _CMU_HFPERCLKEN0_RESETVALUE                       0x00000000UL                               /**< Default value for CMU_HFPERCLKEN0 */
6395 #define _CMU_HFPERCLKEN0_MASK                             0x000FFFFFUL                               /**< Mask for CMU_HFPERCLKEN0 */
6396 #define CMU_HFPERCLKEN0_USART0                            (0x1UL << 0)                               /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
6397 #define _CMU_HFPERCLKEN0_USART0_SHIFT                     0                                          /**< Shift value for CMU_USART0 */
6398 #define _CMU_HFPERCLKEN0_USART0_MASK                      0x1UL                                      /**< Bit mask for CMU_USART0 */
6399 #define _CMU_HFPERCLKEN0_USART0_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6400 #define CMU_HFPERCLKEN0_USART0_DEFAULT                    (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6401 #define CMU_HFPERCLKEN0_USART1                            (0x1UL << 1)                               /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
6402 #define _CMU_HFPERCLKEN0_USART1_SHIFT                     1                                          /**< Shift value for CMU_USART1 */
6403 #define _CMU_HFPERCLKEN0_USART1_MASK                      0x2UL                                      /**< Bit mask for CMU_USART1 */
6404 #define _CMU_HFPERCLKEN0_USART1_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6405 #define CMU_HFPERCLKEN0_USART1_DEFAULT                    (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6406 #define CMU_HFPERCLKEN0_USART2                            (0x1UL << 2)                               /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */
6407 #define _CMU_HFPERCLKEN0_USART2_SHIFT                     2                                          /**< Shift value for CMU_USART2 */
6408 #define _CMU_HFPERCLKEN0_USART2_MASK                      0x4UL                                      /**< Bit mask for CMU_USART2 */
6409 #define _CMU_HFPERCLKEN0_USART2_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6410 #define CMU_HFPERCLKEN0_USART2_DEFAULT                    (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6411 #define CMU_HFPERCLKEN0_USART3                            (0x1UL << 3)                               /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */
6412 #define _CMU_HFPERCLKEN0_USART3_SHIFT                     3                                          /**< Shift value for CMU_USART3 */
6413 #define _CMU_HFPERCLKEN0_USART3_MASK                      0x8UL                                      /**< Bit mask for CMU_USART3 */
6414 #define _CMU_HFPERCLKEN0_USART3_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6415 #define CMU_HFPERCLKEN0_USART3_DEFAULT                    (_CMU_HFPERCLKEN0_USART3_DEFAULT << 3)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6416 #define CMU_HFPERCLKEN0_USART4                            (0x1UL << 4)                               /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */
6417 #define _CMU_HFPERCLKEN0_USART4_SHIFT                     4                                          /**< Shift value for CMU_USART4 */
6418 #define _CMU_HFPERCLKEN0_USART4_MASK                      0x10UL                                     /**< Bit mask for CMU_USART4 */
6419 #define _CMU_HFPERCLKEN0_USART4_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6420 #define CMU_HFPERCLKEN0_USART4_DEFAULT                    (_CMU_HFPERCLKEN0_USART4_DEFAULT << 4)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6421 #define CMU_HFPERCLKEN0_TIMER0                            (0x1UL << 5)                               /**< Timer 0 Clock Enable */
6422 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT                     5                                          /**< Shift value for CMU_TIMER0 */
6423 #define _CMU_HFPERCLKEN0_TIMER0_MASK                      0x20UL                                     /**< Bit mask for CMU_TIMER0 */
6424 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6425 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT                    (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6426 #define CMU_HFPERCLKEN0_TIMER1                            (0x1UL << 6)                               /**< Timer 1 Clock Enable */
6427 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT                     6                                          /**< Shift value for CMU_TIMER1 */
6428 #define _CMU_HFPERCLKEN0_TIMER1_MASK                      0x40UL                                     /**< Bit mask for CMU_TIMER1 */
6429 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6430 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT                    (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6431 #define CMU_HFPERCLKEN0_TIMER2                            (0x1UL << 7)                               /**< Timer 2 Clock Enable */
6432 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT                     7                                          /**< Shift value for CMU_TIMER2 */
6433 #define _CMU_HFPERCLKEN0_TIMER2_MASK                      0x80UL                                     /**< Bit mask for CMU_TIMER2 */
6434 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6435 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT                    (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6436 #define CMU_HFPERCLKEN0_TIMER3                            (0x1UL << 8)                               /**< Timer 3 Clock Enable */
6437 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT                     8                                          /**< Shift value for CMU_TIMER3 */
6438 #define _CMU_HFPERCLKEN0_TIMER3_MASK                      0x100UL                                    /**< Bit mask for CMU_TIMER3 */
6439 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6440 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT                    (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6441 #define CMU_HFPERCLKEN0_ACMP0                             (0x1UL << 9)                               /**< Analog Comparator 0 Clock Enable */
6442 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT                      9                                          /**< Shift value for CMU_ACMP0 */
6443 #define _CMU_HFPERCLKEN0_ACMP0_MASK                       0x200UL                                    /**< Bit mask for CMU_ACMP0 */
6444 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6445 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT                     (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9)      /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6446 #define CMU_HFPERCLKEN0_ACMP1                             (0x1UL << 10)                              /**< Analog Comparator 1 Clock Enable */
6447 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT                      10                                         /**< Shift value for CMU_ACMP1 */
6448 #define _CMU_HFPERCLKEN0_ACMP1_MASK                       0x400UL                                    /**< Bit mask for CMU_ACMP1 */
6449 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6450 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT                     (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6451 #define CMU_HFPERCLKEN0_ACMP2                             (0x1UL << 11)                              /**< Analog Comparator 2 Clock Enable */
6452 #define _CMU_HFPERCLKEN0_ACMP2_SHIFT                      11                                         /**< Shift value for CMU_ACMP2 */
6453 #define _CMU_HFPERCLKEN0_ACMP2_MASK                       0x800UL                                    /**< Bit mask for CMU_ACMP2 */
6454 #define _CMU_HFPERCLKEN0_ACMP2_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6455 #define CMU_HFPERCLKEN0_ACMP2_DEFAULT                     (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 11)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6456 #define CMU_HFPERCLKEN0_I2C0                              (0x1UL << 12)                              /**< I2C 0 Clock Enable */
6457 #define _CMU_HFPERCLKEN0_I2C0_SHIFT                       12                                         /**< Shift value for CMU_I2C0 */
6458 #define _CMU_HFPERCLKEN0_I2C0_MASK                        0x1000UL                                   /**< Bit mask for CMU_I2C0 */
6459 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6460 #define CMU_HFPERCLKEN0_I2C0_DEFAULT                      (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 12)      /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6461 #define CMU_HFPERCLKEN0_I2C1                              (0x1UL << 13)                              /**< I2C 1 Clock Enable */
6462 #define _CMU_HFPERCLKEN0_I2C1_SHIFT                       13                                         /**< Shift value for CMU_I2C1 */
6463 #define _CMU_HFPERCLKEN0_I2C1_MASK                        0x2000UL                                   /**< Bit mask for CMU_I2C1 */
6464 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6465 #define CMU_HFPERCLKEN0_I2C1_DEFAULT                      (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 13)      /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6466 #define CMU_HFPERCLKEN0_ADC0                              (0x1UL << 14)                              /**< Analog to Digital Converter 0 Clock Enable */
6467 #define _CMU_HFPERCLKEN0_ADC0_SHIFT                       14                                         /**< Shift value for CMU_ADC0 */
6468 #define _CMU_HFPERCLKEN0_ADC0_MASK                        0x4000UL                                   /**< Bit mask for CMU_ADC0 */
6469 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6470 #define CMU_HFPERCLKEN0_ADC0_DEFAULT                      (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 14)      /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6471 #define CMU_HFPERCLKEN0_ADC1                              (0x1UL << 15)                              /**< Analog to Digital Converter 0 Clock Enable */
6472 #define _CMU_HFPERCLKEN0_ADC1_SHIFT                       15                                         /**< Shift value for CMU_ADC1 */
6473 #define _CMU_HFPERCLKEN0_ADC1_MASK                        0x8000UL                                   /**< Bit mask for CMU_ADC1 */
6474 #define _CMU_HFPERCLKEN0_ADC1_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6475 #define CMU_HFPERCLKEN0_ADC1_DEFAULT                      (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 15)      /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6476 #define CMU_HFPERCLKEN0_PDM                               (0x1UL << 16)                              /**< PDM Interface  Clock Enable */
6477 #define _CMU_HFPERCLKEN0_PDM_SHIFT                        16                                         /**< Shift value for CMU_PDM */
6478 #define _CMU_HFPERCLKEN0_PDM_MASK                         0x10000UL                                  /**< Bit mask for CMU_PDM */
6479 #define _CMU_HFPERCLKEN0_PDM_DEFAULT                      0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6480 #define CMU_HFPERCLKEN0_PDM_DEFAULT                       (_CMU_HFPERCLKEN0_PDM_DEFAULT << 16)       /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6481 #define CMU_HFPERCLKEN0_CRYOTIMER                         (0x1UL << 17)                              /**< CRYOTIMER Clock Enable */
6482 #define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT                  17                                         /**< Shift value for CMU_CRYOTIMER */
6483 #define _CMU_HFPERCLKEN0_CRYOTIMER_MASK                   0x20000UL                                  /**< Bit mask for CMU_CRYOTIMER */
6484 #define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT                0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6485 #define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT                 (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6486 #define CMU_HFPERCLKEN0_IDAC0                             (0x1UL << 18)                              /**< Current Digital to Analog Converter 0 Clock Enable */
6487 #define _CMU_HFPERCLKEN0_IDAC0_SHIFT                      18                                         /**< Shift value for CMU_IDAC0 */
6488 #define _CMU_HFPERCLKEN0_IDAC0_MASK                       0x40000UL                                  /**< Bit mask for CMU_IDAC0 */
6489 #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6490 #define CMU_HFPERCLKEN0_IDAC0_DEFAULT                     (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 18)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6491 #define CMU_HFPERCLKEN0_TRNG0                             (0x1UL << 19)                              /**< True Random Number Generator 0 Clock Enable */
6492 #define _CMU_HFPERCLKEN0_TRNG0_SHIFT                      19                                         /**< Shift value for CMU_TRNG0 */
6493 #define _CMU_HFPERCLKEN0_TRNG0_MASK                       0x80000UL                                  /**< Bit mask for CMU_TRNG0 */
6494 #define _CMU_HFPERCLKEN0_TRNG0_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
6495 #define CMU_HFPERCLKEN0_TRNG0_DEFAULT                     (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 19)     /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
6496 
6497 /* Bit fields for CMU HFPERCLKEN1 */
6498 #define _CMU_HFPERCLKEN1_RESETVALUE                       0x00000000UL                            /**< Default value for CMU_HFPERCLKEN1 */
6499 #define _CMU_HFPERCLKEN1_MASK                             0x000000FFUL                            /**< Mask for CMU_HFPERCLKEN1 */
6500 #define CMU_HFPERCLKEN1_UART0                             (0x1UL << 0)                            /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */
6501 #define _CMU_HFPERCLKEN1_UART0_SHIFT                      0                                       /**< Shift value for CMU_UART0 */
6502 #define _CMU_HFPERCLKEN1_UART0_MASK                       0x1UL                                   /**< Bit mask for CMU_UART0 */
6503 #define _CMU_HFPERCLKEN1_UART0_DEFAULT                    0x00000000UL                            /**< Mode DEFAULT for CMU_HFPERCLKEN1 */
6504 #define CMU_HFPERCLKEN1_UART0_DEFAULT                     (_CMU_HFPERCLKEN1_UART0_DEFAULT << 0)   /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */
6505 #define CMU_HFPERCLKEN1_UART1                             (0x1UL << 1)                            /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */
6506 #define _CMU_HFPERCLKEN1_UART1_SHIFT                      1                                       /**< Shift value for CMU_UART1 */
6507 #define _CMU_HFPERCLKEN1_UART1_MASK                       0x2UL                                   /**< Bit mask for CMU_UART1 */
6508 #define _CMU_HFPERCLKEN1_UART1_DEFAULT                    0x00000000UL                            /**< Mode DEFAULT for CMU_HFPERCLKEN1 */
6509 #define CMU_HFPERCLKEN1_UART1_DEFAULT                     (_CMU_HFPERCLKEN1_UART1_DEFAULT << 1)   /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */
6510 #define CMU_HFPERCLKEN1_WTIMER0                           (0x1UL << 2)                            /**< Wide Timer 0 Clock Enable */
6511 #define _CMU_HFPERCLKEN1_WTIMER0_SHIFT                    2                                       /**< Shift value for CMU_WTIMER0 */
6512 #define _CMU_HFPERCLKEN1_WTIMER0_MASK                     0x4UL                                   /**< Bit mask for CMU_WTIMER0 */
6513 #define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT                  0x00000000UL                            /**< Mode DEFAULT for CMU_HFPERCLKEN1 */
6514 #define CMU_HFPERCLKEN1_WTIMER0_DEFAULT                   (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */
6515 #define CMU_HFPERCLKEN1_WTIMER1                           (0x1UL << 3)                            /**< Wide Timer 0 Clock Enable */
6516 #define _CMU_HFPERCLKEN1_WTIMER1_SHIFT                    3                                       /**< Shift value for CMU_WTIMER1 */
6517 #define _CMU_HFPERCLKEN1_WTIMER1_MASK                     0x8UL                                   /**< Bit mask for CMU_WTIMER1 */
6518 #define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT                  0x00000000UL                            /**< Mode DEFAULT for CMU_HFPERCLKEN1 */
6519 #define CMU_HFPERCLKEN1_WTIMER1_DEFAULT                   (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */
6520 #define CMU_HFPERCLKEN1_CAN0                              (0x1UL << 4)                            /**< CAN 0 Clock Enable */
6521 #define _CMU_HFPERCLKEN1_CAN0_SHIFT                       4                                       /**< Shift value for CMU_CAN0 */
6522 #define _CMU_HFPERCLKEN1_CAN0_MASK                        0x10UL                                  /**< Bit mask for CMU_CAN0 */
6523 #define _CMU_HFPERCLKEN1_CAN0_DEFAULT                     0x00000000UL                            /**< Mode DEFAULT for CMU_HFPERCLKEN1 */
6524 #define CMU_HFPERCLKEN1_CAN0_DEFAULT                      (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 4)    /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */
6525 #define CMU_HFPERCLKEN1_CAN1                              (0x1UL << 5)                            /**< CAN 1 Clock Enable */
6526 #define _CMU_HFPERCLKEN1_CAN1_SHIFT                       5                                       /**< Shift value for CMU_CAN1 */
6527 #define _CMU_HFPERCLKEN1_CAN1_MASK                        0x20UL                                  /**< Bit mask for CMU_CAN1 */
6528 #define _CMU_HFPERCLKEN1_CAN1_DEFAULT                     0x00000000UL                            /**< Mode DEFAULT for CMU_HFPERCLKEN1 */
6529 #define CMU_HFPERCLKEN1_CAN1_DEFAULT                      (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 5)    /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */
6530 #define CMU_HFPERCLKEN1_VDAC0                             (0x1UL << 6)                            /**< Digital to Analog Converter 0 Clock Enable */
6531 #define _CMU_HFPERCLKEN1_VDAC0_SHIFT                      6                                       /**< Shift value for CMU_VDAC0 */
6532 #define _CMU_HFPERCLKEN1_VDAC0_MASK                       0x40UL                                  /**< Bit mask for CMU_VDAC0 */
6533 #define _CMU_HFPERCLKEN1_VDAC0_DEFAULT                    0x00000000UL                            /**< Mode DEFAULT for CMU_HFPERCLKEN1 */
6534 #define CMU_HFPERCLKEN1_VDAC0_DEFAULT                     (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 6)   /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */
6535 #define CMU_HFPERCLKEN1_CSEN                              (0x1UL << 7)                            /**< Capacitive touch sense module Clock Enable */
6536 #define _CMU_HFPERCLKEN1_CSEN_SHIFT                       7                                       /**< Shift value for CMU_CSEN */
6537 #define _CMU_HFPERCLKEN1_CSEN_MASK                        0x80UL                                  /**< Bit mask for CMU_CSEN */
6538 #define _CMU_HFPERCLKEN1_CSEN_DEFAULT                     0x00000000UL                            /**< Mode DEFAULT for CMU_HFPERCLKEN1 */
6539 #define CMU_HFPERCLKEN1_CSEN_DEFAULT                      (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 7)    /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */
6540 
6541 /* Bit fields for CMU LFACLKEN0 */
6542 #define _CMU_LFACLKEN0_RESETVALUE                         0x00000000UL                           /**< Default value for CMU_LFACLKEN0 */
6543 #define _CMU_LFACLKEN0_MASK                               0x0000001FUL                           /**< Mask for CMU_LFACLKEN0 */
6544 #define CMU_LFACLKEN0_LETIMER0                            (0x1UL << 0)                           /**< Low Energy Timer 0 Clock Enable */
6545 #define _CMU_LFACLKEN0_LETIMER0_SHIFT                     0                                      /**< Shift value for CMU_LETIMER0 */
6546 #define _CMU_LFACLKEN0_LETIMER0_MASK                      0x1UL                                  /**< Bit mask for CMU_LETIMER0 */
6547 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT                   0x00000000UL                           /**< Mode DEFAULT for CMU_LFACLKEN0 */
6548 #define CMU_LFACLKEN0_LETIMER0_DEFAULT                    (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
6549 #define CMU_LFACLKEN0_LETIMER1                            (0x1UL << 1)                           /**< Low Energy Timer 1 Clock Enable */
6550 #define _CMU_LFACLKEN0_LETIMER1_SHIFT                     1                                      /**< Shift value for CMU_LETIMER1 */
6551 #define _CMU_LFACLKEN0_LETIMER1_MASK                      0x2UL                                  /**< Bit mask for CMU_LETIMER1 */
6552 #define _CMU_LFACLKEN0_LETIMER1_DEFAULT                   0x00000000UL                           /**< Mode DEFAULT for CMU_LFACLKEN0 */
6553 #define CMU_LFACLKEN0_LETIMER1_DEFAULT                    (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
6554 #define CMU_LFACLKEN0_LESENSE                             (0x1UL << 2)                           /**< Low Energy Sensor Interface Clock Enable */
6555 #define _CMU_LFACLKEN0_LESENSE_SHIFT                      2                                      /**< Shift value for CMU_LESENSE */
6556 #define _CMU_LFACLKEN0_LESENSE_MASK                       0x4UL                                  /**< Bit mask for CMU_LESENSE */
6557 #define _CMU_LFACLKEN0_LESENSE_DEFAULT                    0x00000000UL                           /**< Mode DEFAULT for CMU_LFACLKEN0 */
6558 #define CMU_LFACLKEN0_LESENSE_DEFAULT                     (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2)  /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
6559 #define CMU_LFACLKEN0_LCD                                 (0x1UL << 3)                           /**< Liquid Crystal Display Controller Clock Enable */
6560 #define _CMU_LFACLKEN0_LCD_SHIFT                          3                                      /**< Shift value for CMU_LCD */
6561 #define _CMU_LFACLKEN0_LCD_MASK                           0x8UL                                  /**< Bit mask for CMU_LCD */
6562 #define _CMU_LFACLKEN0_LCD_DEFAULT                        0x00000000UL                           /**< Mode DEFAULT for CMU_LFACLKEN0 */
6563 #define CMU_LFACLKEN0_LCD_DEFAULT                         (_CMU_LFACLKEN0_LCD_DEFAULT << 3)      /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
6564 #define CMU_LFACLKEN0_RTC                                 (0x1UL << 4)                           /**< Real-Time Counter Clock Enable */
6565 #define _CMU_LFACLKEN0_RTC_SHIFT                          4                                      /**< Shift value for CMU_RTC */
6566 #define _CMU_LFACLKEN0_RTC_MASK                           0x10UL                                 /**< Bit mask for CMU_RTC */
6567 #define _CMU_LFACLKEN0_RTC_DEFAULT                        0x00000000UL                           /**< Mode DEFAULT for CMU_LFACLKEN0 */
6568 #define CMU_LFACLKEN0_RTC_DEFAULT                         (_CMU_LFACLKEN0_RTC_DEFAULT << 4)      /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
6569 
6570 /* Bit fields for CMU LFBCLKEN0 */
6571 #define _CMU_LFBCLKEN0_RESETVALUE                         0x00000000UL                          /**< Default value for CMU_LFBCLKEN0 */
6572 #define _CMU_LFBCLKEN0_MASK                               0x0000000FUL                          /**< Mask for CMU_LFBCLKEN0 */
6573 #define CMU_LFBCLKEN0_LEUART0                             (0x1UL << 0)                          /**< Low Energy UART 0 Clock Enable */
6574 #define _CMU_LFBCLKEN0_LEUART0_SHIFT                      0                                     /**< Shift value for CMU_LEUART0 */
6575 #define _CMU_LFBCLKEN0_LEUART0_MASK                       0x1UL                                 /**< Bit mask for CMU_LEUART0 */
6576 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT                    0x00000000UL                          /**< Mode DEFAULT for CMU_LFBCLKEN0 */
6577 #define CMU_LFBCLKEN0_LEUART0_DEFAULT                     (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
6578 #define CMU_LFBCLKEN0_LEUART1                             (0x1UL << 1)                          /**< Low Energy UART 1 Clock Enable */
6579 #define _CMU_LFBCLKEN0_LEUART1_SHIFT                      1                                     /**< Shift value for CMU_LEUART1 */
6580 #define _CMU_LFBCLKEN0_LEUART1_MASK                       0x2UL                                 /**< Bit mask for CMU_LEUART1 */
6581 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT                    0x00000000UL                          /**< Mode DEFAULT for CMU_LFBCLKEN0 */
6582 #define CMU_LFBCLKEN0_LEUART1_DEFAULT                     (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
6583 #define CMU_LFBCLKEN0_SYSTICK                             (0x1UL << 2)                          /**<  Clock Enable */
6584 #define _CMU_LFBCLKEN0_SYSTICK_SHIFT                      2                                     /**< Shift value for CMU_SYSTICK */
6585 #define _CMU_LFBCLKEN0_SYSTICK_MASK                       0x4UL                                 /**< Bit mask for CMU_SYSTICK */
6586 #define _CMU_LFBCLKEN0_SYSTICK_DEFAULT                    0x00000000UL                          /**< Mode DEFAULT for CMU_LFBCLKEN0 */
6587 #define CMU_LFBCLKEN0_SYSTICK_DEFAULT                     (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
6588 #define CMU_LFBCLKEN0_CSEN                                (0x1UL << 3)                          /**< Capacitive touch sense module Clock Enable */
6589 #define _CMU_LFBCLKEN0_CSEN_SHIFT                         3                                     /**< Shift value for CMU_CSEN */
6590 #define _CMU_LFBCLKEN0_CSEN_MASK                          0x8UL                                 /**< Bit mask for CMU_CSEN */
6591 #define _CMU_LFBCLKEN0_CSEN_DEFAULT                       0x00000000UL                          /**< Mode DEFAULT for CMU_LFBCLKEN0 */
6592 #define CMU_LFBCLKEN0_CSEN_DEFAULT                        (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3)    /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
6593 
6594 /* Bit fields for CMU LFCCLKEN0 */
6595 #define _CMU_LFCCLKEN0_RESETVALUE                         0x00000000UL /**< Default value for CMU_LFCCLKEN0 */
6596 #define _CMU_LFCCLKEN0_MASK                               0x00000000UL /**< Mask for CMU_LFCCLKEN0 */
6597 
6598 /* Bit fields for CMU LFECLKEN0 */
6599 #define _CMU_LFECLKEN0_RESETVALUE                         0x00000000UL                       /**< Default value for CMU_LFECLKEN0 */
6600 #define _CMU_LFECLKEN0_MASK                               0x00000001UL                       /**< Mask for CMU_LFECLKEN0 */
6601 #define CMU_LFECLKEN0_RTCC                                (0x1UL << 0)                       /**< Real-Time Counter and Calendar Clock Enable */
6602 #define _CMU_LFECLKEN0_RTCC_SHIFT                         0                                  /**< Shift value for CMU_RTCC */
6603 #define _CMU_LFECLKEN0_RTCC_MASK                          0x1UL                              /**< Bit mask for CMU_RTCC */
6604 #define _CMU_LFECLKEN0_RTCC_DEFAULT                       0x00000000UL                       /**< Mode DEFAULT for CMU_LFECLKEN0 */
6605 #define CMU_LFECLKEN0_RTCC_DEFAULT                        (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */
6606 
6607 /* Bit fields for CMU HFPRESC */
6608 #define _CMU_HFPRESC_RESETVALUE                           0x00000000UL                              /**< Default value for CMU_HFPRESC */
6609 #define _CMU_HFPRESC_MASK                                 0x03001F00UL                              /**< Mask for CMU_HFPRESC */
6610 #define _CMU_HFPRESC_PRESC_SHIFT                          8                                         /**< Shift value for CMU_PRESC */
6611 #define _CMU_HFPRESC_PRESC_MASK                           0x1F00UL                                  /**< Bit mask for CMU_PRESC */
6612 #define _CMU_HFPRESC_PRESC_DEFAULT                        0x00000000UL                              /**< Mode DEFAULT for CMU_HFPRESC */
6613 #define _CMU_HFPRESC_PRESC_NODIVISION                     0x00000000UL                              /**< Mode NODIVISION for CMU_HFPRESC */
6614 #define CMU_HFPRESC_PRESC_DEFAULT                         (_CMU_HFPRESC_PRESC_DEFAULT << 8)         /**< Shifted mode DEFAULT for CMU_HFPRESC */
6615 #define CMU_HFPRESC_PRESC_NODIVISION                      (_CMU_HFPRESC_PRESC_NODIVISION << 8)      /**< Shifted mode NODIVISION for CMU_HFPRESC */
6616 #define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT                   24                                        /**< Shift value for CMU_HFCLKLEPRESC */
6617 #define _CMU_HFPRESC_HFCLKLEPRESC_MASK                    0x3000000UL                               /**< Bit mask for CMU_HFCLKLEPRESC */
6618 #define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT                 0x00000000UL                              /**< Mode DEFAULT for CMU_HFPRESC */
6619 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV2                    0x00000000UL                              /**< Mode DIV2 for CMU_HFPRESC */
6620 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV4                    0x00000001UL                              /**< Mode DIV4 for CMU_HFPRESC */
6621 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV8                    0x00000002UL                              /**< Mode DIV8 for CMU_HFPRESC */
6622 #define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT                  (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */
6623 #define CMU_HFPRESC_HFCLKLEPRESC_DIV2                     (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24)    /**< Shifted mode DIV2 for CMU_HFPRESC */
6624 #define CMU_HFPRESC_HFCLKLEPRESC_DIV4                     (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24)    /**< Shifted mode DIV4 for CMU_HFPRESC */
6625 #define CMU_HFPRESC_HFCLKLEPRESC_DIV8                     (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24)    /**< Shifted mode DIV8 for CMU_HFPRESC */
6626 
6627 /* Bit fields for CMU HFBUSPRESC */
6628 #define _CMU_HFBUSPRESC_RESETVALUE                        0x00000000UL                            /**< Default value for CMU_HFBUSPRESC */
6629 #define _CMU_HFBUSPRESC_MASK                              0x0001FF00UL                            /**< Mask for CMU_HFBUSPRESC */
6630 #define _CMU_HFBUSPRESC_PRESC_SHIFT                       8                                       /**< Shift value for CMU_PRESC */
6631 #define _CMU_HFBUSPRESC_PRESC_MASK                        0x1FF00UL                               /**< Bit mask for CMU_PRESC */
6632 #define _CMU_HFBUSPRESC_PRESC_DEFAULT                     0x00000000UL                            /**< Mode DEFAULT for CMU_HFBUSPRESC */
6633 #define _CMU_HFBUSPRESC_PRESC_NODIVISION                  0x00000000UL                            /**< Mode NODIVISION for CMU_HFBUSPRESC */
6634 #define CMU_HFBUSPRESC_PRESC_DEFAULT                      (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8)    /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */
6635 #define CMU_HFBUSPRESC_PRESC_NODIVISION                   (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */
6636 
6637 /* Bit fields for CMU HFCOREPRESC */
6638 #define _CMU_HFCOREPRESC_RESETVALUE                       0x00000000UL                             /**< Default value for CMU_HFCOREPRESC */
6639 #define _CMU_HFCOREPRESC_MASK                             0x0001FF00UL                             /**< Mask for CMU_HFCOREPRESC */
6640 #define _CMU_HFCOREPRESC_PRESC_SHIFT                      8                                        /**< Shift value for CMU_PRESC */
6641 #define _CMU_HFCOREPRESC_PRESC_MASK                       0x1FF00UL                                /**< Bit mask for CMU_PRESC */
6642 #define _CMU_HFCOREPRESC_PRESC_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CMU_HFCOREPRESC */
6643 #define _CMU_HFCOREPRESC_PRESC_NODIVISION                 0x00000000UL                             /**< Mode NODIVISION for CMU_HFCOREPRESC */
6644 #define CMU_HFCOREPRESC_PRESC_DEFAULT                     (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8)    /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */
6645 #define CMU_HFCOREPRESC_PRESC_NODIVISION                  (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */
6646 
6647 /* Bit fields for CMU HFPERPRESC */
6648 #define _CMU_HFPERPRESC_RESETVALUE                        0x00000000UL                            /**< Default value for CMU_HFPERPRESC */
6649 #define _CMU_HFPERPRESC_MASK                              0x0001FF00UL                            /**< Mask for CMU_HFPERPRESC */
6650 #define _CMU_HFPERPRESC_PRESC_SHIFT                       8                                       /**< Shift value for CMU_PRESC */
6651 #define _CMU_HFPERPRESC_PRESC_MASK                        0x1FF00UL                               /**< Bit mask for CMU_PRESC */
6652 #define _CMU_HFPERPRESC_PRESC_DEFAULT                     0x00000000UL                            /**< Mode DEFAULT for CMU_HFPERPRESC */
6653 #define _CMU_HFPERPRESC_PRESC_NODIVISION                  0x00000000UL                            /**< Mode NODIVISION for CMU_HFPERPRESC */
6654 #define CMU_HFPERPRESC_PRESC_DEFAULT                      (_CMU_HFPERPRESC_PRESC_DEFAULT << 8)    /**< Shifted mode DEFAULT for CMU_HFPERPRESC */
6655 #define CMU_HFPERPRESC_PRESC_NODIVISION                   (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */
6656 
6657 /* Bit fields for CMU HFEXPPRESC */
6658 #define _CMU_HFEXPPRESC_RESETVALUE                        0x00000000UL                            /**< Default value for CMU_HFEXPPRESC */
6659 #define _CMU_HFEXPPRESC_MASK                              0x00001F00UL                            /**< Mask for CMU_HFEXPPRESC */
6660 #define _CMU_HFEXPPRESC_PRESC_SHIFT                       8                                       /**< Shift value for CMU_PRESC */
6661 #define _CMU_HFEXPPRESC_PRESC_MASK                        0x1F00UL                                /**< Bit mask for CMU_PRESC */
6662 #define _CMU_HFEXPPRESC_PRESC_DEFAULT                     0x00000000UL                            /**< Mode DEFAULT for CMU_HFEXPPRESC */
6663 #define _CMU_HFEXPPRESC_PRESC_NODIVISION                  0x00000000UL                            /**< Mode NODIVISION for CMU_HFEXPPRESC */
6664 #define CMU_HFEXPPRESC_PRESC_DEFAULT                      (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8)    /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */
6665 #define CMU_HFEXPPRESC_PRESC_NODIVISION                   (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */
6666 
6667 /* Bit fields for CMU HFPERPRESCB */
6668 #define _CMU_HFPERPRESCB_RESETVALUE                       0x00000000UL                             /**< Default value for CMU_HFPERPRESCB */
6669 #define _CMU_HFPERPRESCB_MASK                             0x0001FF00UL                             /**< Mask for CMU_HFPERPRESCB */
6670 #define _CMU_HFPERPRESCB_PRESC_SHIFT                      8                                        /**< Shift value for CMU_PRESC */
6671 #define _CMU_HFPERPRESCB_PRESC_MASK                       0x1FF00UL                                /**< Bit mask for CMU_PRESC */
6672 #define _CMU_HFPERPRESCB_PRESC_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CMU_HFPERPRESCB */
6673 #define _CMU_HFPERPRESCB_PRESC_NODIVISION                 0x00000000UL                             /**< Mode NODIVISION for CMU_HFPERPRESCB */
6674 #define CMU_HFPERPRESCB_PRESC_DEFAULT                     (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8)    /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */
6675 #define CMU_HFPERPRESCB_PRESC_NODIVISION                  (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */
6676 
6677 /* Bit fields for CMU HFPERPRESCC */
6678 #define _CMU_HFPERPRESCC_RESETVALUE                       0x00000000UL                             /**< Default value for CMU_HFPERPRESCC */
6679 #define _CMU_HFPERPRESCC_MASK                             0x0001FF00UL                             /**< Mask for CMU_HFPERPRESCC */
6680 #define _CMU_HFPERPRESCC_PRESC_SHIFT                      8                                        /**< Shift value for CMU_PRESC */
6681 #define _CMU_HFPERPRESCC_PRESC_MASK                       0x1FF00UL                                /**< Bit mask for CMU_PRESC */
6682 #define _CMU_HFPERPRESCC_PRESC_DEFAULT                    0x00000000UL                             /**< Mode DEFAULT for CMU_HFPERPRESCC */
6683 #define _CMU_HFPERPRESCC_PRESC_NODIVISION                 0x00000000UL                             /**< Mode NODIVISION for CMU_HFPERPRESCC */
6684 #define CMU_HFPERPRESCC_PRESC_DEFAULT                     (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8)    /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */
6685 #define CMU_HFPERPRESCC_PRESC_NODIVISION                  (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */
6686 
6687 /* Bit fields for CMU LFAPRESC0 */
6688 #define _CMU_LFAPRESC0_RESETVALUE                         0x00000000UL                            /**< Default value for CMU_LFAPRESC0 */
6689 #define _CMU_LFAPRESC0_MASK                               0x000F73FFUL                            /**< Mask for CMU_LFAPRESC0 */
6690 #define _CMU_LFAPRESC0_LETIMER0_SHIFT                     0                                       /**< Shift value for CMU_LETIMER0 */
6691 #define _CMU_LFAPRESC0_LETIMER0_MASK                      0xFUL                                   /**< Bit mask for CMU_LETIMER0 */
6692 #define _CMU_LFAPRESC0_LETIMER0_DIV1                      0x00000000UL                            /**< Mode DIV1 for CMU_LFAPRESC0 */
6693 #define _CMU_LFAPRESC0_LETIMER0_DIV2                      0x00000001UL                            /**< Mode DIV2 for CMU_LFAPRESC0 */
6694 #define _CMU_LFAPRESC0_LETIMER0_DIV4                      0x00000002UL                            /**< Mode DIV4 for CMU_LFAPRESC0 */
6695 #define _CMU_LFAPRESC0_LETIMER0_DIV8                      0x00000003UL                            /**< Mode DIV8 for CMU_LFAPRESC0 */
6696 #define _CMU_LFAPRESC0_LETIMER0_DIV16                     0x00000004UL                            /**< Mode DIV16 for CMU_LFAPRESC0 */
6697 #define _CMU_LFAPRESC0_LETIMER0_DIV32                     0x00000005UL                            /**< Mode DIV32 for CMU_LFAPRESC0 */
6698 #define _CMU_LFAPRESC0_LETIMER0_DIV64                     0x00000006UL                            /**< Mode DIV64 for CMU_LFAPRESC0 */
6699 #define _CMU_LFAPRESC0_LETIMER0_DIV128                    0x00000007UL                            /**< Mode DIV128 for CMU_LFAPRESC0 */
6700 #define _CMU_LFAPRESC0_LETIMER0_DIV256                    0x00000008UL                            /**< Mode DIV256 for CMU_LFAPRESC0 */
6701 #define _CMU_LFAPRESC0_LETIMER0_DIV512                    0x00000009UL                            /**< Mode DIV512 for CMU_LFAPRESC0 */
6702 #define _CMU_LFAPRESC0_LETIMER0_DIV1024                   0x0000000AUL                            /**< Mode DIV1024 for CMU_LFAPRESC0 */
6703 #define _CMU_LFAPRESC0_LETIMER0_DIV2048                   0x0000000BUL                            /**< Mode DIV2048 for CMU_LFAPRESC0 */
6704 #define _CMU_LFAPRESC0_LETIMER0_DIV4096                   0x0000000CUL                            /**< Mode DIV4096 for CMU_LFAPRESC0 */
6705 #define _CMU_LFAPRESC0_LETIMER0_DIV8192                   0x0000000DUL                            /**< Mode DIV8192 for CMU_LFAPRESC0 */
6706 #define _CMU_LFAPRESC0_LETIMER0_DIV16384                  0x0000000EUL                            /**< Mode DIV16384 for CMU_LFAPRESC0 */
6707 #define _CMU_LFAPRESC0_LETIMER0_DIV32768                  0x0000000FUL                            /**< Mode DIV32768 for CMU_LFAPRESC0 */
6708 #define CMU_LFAPRESC0_LETIMER0_DIV1                       (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0)     /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
6709 #define CMU_LFAPRESC0_LETIMER0_DIV2                       (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0)     /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
6710 #define CMU_LFAPRESC0_LETIMER0_DIV4                       (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0)     /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
6711 #define CMU_LFAPRESC0_LETIMER0_DIV8                       (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0)     /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
6712 #define CMU_LFAPRESC0_LETIMER0_DIV16                      (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0)    /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
6713 #define CMU_LFAPRESC0_LETIMER0_DIV32                      (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0)    /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
6714 #define CMU_LFAPRESC0_LETIMER0_DIV64                      (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0)    /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
6715 #define CMU_LFAPRESC0_LETIMER0_DIV128                     (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0)   /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
6716 #define CMU_LFAPRESC0_LETIMER0_DIV256                     (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0)   /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
6717 #define CMU_LFAPRESC0_LETIMER0_DIV512                     (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0)   /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
6718 #define CMU_LFAPRESC0_LETIMER0_DIV1024                    (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0)  /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
6719 #define CMU_LFAPRESC0_LETIMER0_DIV2048                    (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0)  /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
6720 #define CMU_LFAPRESC0_LETIMER0_DIV4096                    (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0)  /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
6721 #define CMU_LFAPRESC0_LETIMER0_DIV8192                    (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0)  /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
6722 #define CMU_LFAPRESC0_LETIMER0_DIV16384                   (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
6723 #define CMU_LFAPRESC0_LETIMER0_DIV32768                   (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
6724 #define _CMU_LFAPRESC0_LETIMER1_SHIFT                     4                                       /**< Shift value for CMU_LETIMER1 */
6725 #define _CMU_LFAPRESC0_LETIMER1_MASK                      0xF0UL                                  /**< Bit mask for CMU_LETIMER1 */
6726 #define _CMU_LFAPRESC0_LETIMER1_DIV1                      0x00000000UL                            /**< Mode DIV1 for CMU_LFAPRESC0 */
6727 #define _CMU_LFAPRESC0_LETIMER1_DIV2                      0x00000001UL                            /**< Mode DIV2 for CMU_LFAPRESC0 */
6728 #define _CMU_LFAPRESC0_LETIMER1_DIV4                      0x00000002UL                            /**< Mode DIV4 for CMU_LFAPRESC0 */
6729 #define _CMU_LFAPRESC0_LETIMER1_DIV8                      0x00000003UL                            /**< Mode DIV8 for CMU_LFAPRESC0 */
6730 #define _CMU_LFAPRESC0_LETIMER1_DIV16                     0x00000004UL                            /**< Mode DIV16 for CMU_LFAPRESC0 */
6731 #define _CMU_LFAPRESC0_LETIMER1_DIV32                     0x00000005UL                            /**< Mode DIV32 for CMU_LFAPRESC0 */
6732 #define _CMU_LFAPRESC0_LETIMER1_DIV64                     0x00000006UL                            /**< Mode DIV64 for CMU_LFAPRESC0 */
6733 #define _CMU_LFAPRESC0_LETIMER1_DIV128                    0x00000007UL                            /**< Mode DIV128 for CMU_LFAPRESC0 */
6734 #define _CMU_LFAPRESC0_LETIMER1_DIV256                    0x00000008UL                            /**< Mode DIV256 for CMU_LFAPRESC0 */
6735 #define _CMU_LFAPRESC0_LETIMER1_DIV512                    0x00000009UL                            /**< Mode DIV512 for CMU_LFAPRESC0 */
6736 #define _CMU_LFAPRESC0_LETIMER1_DIV1024                   0x0000000AUL                            /**< Mode DIV1024 for CMU_LFAPRESC0 */
6737 #define _CMU_LFAPRESC0_LETIMER1_DIV2048                   0x0000000BUL                            /**< Mode DIV2048 for CMU_LFAPRESC0 */
6738 #define _CMU_LFAPRESC0_LETIMER1_DIV4096                   0x0000000CUL                            /**< Mode DIV4096 for CMU_LFAPRESC0 */
6739 #define _CMU_LFAPRESC0_LETIMER1_DIV8192                   0x0000000DUL                            /**< Mode DIV8192 for CMU_LFAPRESC0 */
6740 #define _CMU_LFAPRESC0_LETIMER1_DIV16384                  0x0000000EUL                            /**< Mode DIV16384 for CMU_LFAPRESC0 */
6741 #define _CMU_LFAPRESC0_LETIMER1_DIV32768                  0x0000000FUL                            /**< Mode DIV32768 for CMU_LFAPRESC0 */
6742 #define CMU_LFAPRESC0_LETIMER1_DIV1                       (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4)     /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
6743 #define CMU_LFAPRESC0_LETIMER1_DIV2                       (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4)     /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
6744 #define CMU_LFAPRESC0_LETIMER1_DIV4                       (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4)     /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
6745 #define CMU_LFAPRESC0_LETIMER1_DIV8                       (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4)     /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
6746 #define CMU_LFAPRESC0_LETIMER1_DIV16                      (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4)    /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
6747 #define CMU_LFAPRESC0_LETIMER1_DIV32                      (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4)    /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
6748 #define CMU_LFAPRESC0_LETIMER1_DIV64                      (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4)    /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
6749 #define CMU_LFAPRESC0_LETIMER1_DIV128                     (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4)   /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
6750 #define CMU_LFAPRESC0_LETIMER1_DIV256                     (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4)   /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
6751 #define CMU_LFAPRESC0_LETIMER1_DIV512                     (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4)   /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
6752 #define CMU_LFAPRESC0_LETIMER1_DIV1024                    (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4)  /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
6753 #define CMU_LFAPRESC0_LETIMER1_DIV2048                    (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4)  /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
6754 #define CMU_LFAPRESC0_LETIMER1_DIV4096                    (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4)  /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
6755 #define CMU_LFAPRESC0_LETIMER1_DIV8192                    (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4)  /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
6756 #define CMU_LFAPRESC0_LETIMER1_DIV16384                   (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
6757 #define CMU_LFAPRESC0_LETIMER1_DIV32768                   (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
6758 #define _CMU_LFAPRESC0_LESENSE_SHIFT                      8                                       /**< Shift value for CMU_LESENSE */
6759 #define _CMU_LFAPRESC0_LESENSE_MASK                       0x300UL                                 /**< Bit mask for CMU_LESENSE */
6760 #define _CMU_LFAPRESC0_LESENSE_DIV1                       0x00000000UL                            /**< Mode DIV1 for CMU_LFAPRESC0 */
6761 #define _CMU_LFAPRESC0_LESENSE_DIV2                       0x00000001UL                            /**< Mode DIV2 for CMU_LFAPRESC0 */
6762 #define _CMU_LFAPRESC0_LESENSE_DIV4                       0x00000002UL                            /**< Mode DIV4 for CMU_LFAPRESC0 */
6763 #define _CMU_LFAPRESC0_LESENSE_DIV8                       0x00000003UL                            /**< Mode DIV8 for CMU_LFAPRESC0 */
6764 #define CMU_LFAPRESC0_LESENSE_DIV1                        (_CMU_LFAPRESC0_LESENSE_DIV1 << 8)      /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
6765 #define CMU_LFAPRESC0_LESENSE_DIV2                        (_CMU_LFAPRESC0_LESENSE_DIV2 << 8)      /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
6766 #define CMU_LFAPRESC0_LESENSE_DIV4                        (_CMU_LFAPRESC0_LESENSE_DIV4 << 8)      /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
6767 #define CMU_LFAPRESC0_LESENSE_DIV8                        (_CMU_LFAPRESC0_LESENSE_DIV8 << 8)      /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
6768 #define _CMU_LFAPRESC0_LCD_SHIFT                          12                                      /**< Shift value for CMU_LCD */
6769 #define _CMU_LFAPRESC0_LCD_MASK                           0x7000UL                                /**< Bit mask for CMU_LCD */
6770 #define _CMU_LFAPRESC0_LCD_DIV1                           0x00000000UL                            /**< Mode DIV1 for CMU_LFAPRESC0 */
6771 #define _CMU_LFAPRESC0_LCD_DIV2                           0x00000001UL                            /**< Mode DIV2 for CMU_LFAPRESC0 */
6772 #define _CMU_LFAPRESC0_LCD_DIV4                           0x00000002UL                            /**< Mode DIV4 for CMU_LFAPRESC0 */
6773 #define _CMU_LFAPRESC0_LCD_DIV8                           0x00000003UL                            /**< Mode DIV8 for CMU_LFAPRESC0 */
6774 #define _CMU_LFAPRESC0_LCD_DIV16                          0x00000004UL                            /**< Mode DIV16 for CMU_LFAPRESC0 */
6775 #define _CMU_LFAPRESC0_LCD_DIV32                          0x00000005UL                            /**< Mode DIV32 for CMU_LFAPRESC0 */
6776 #define _CMU_LFAPRESC0_LCD_DIV64                          0x00000006UL                            /**< Mode DIV64 for CMU_LFAPRESC0 */
6777 #define _CMU_LFAPRESC0_LCD_DIV128                         0x00000007UL                            /**< Mode DIV128 for CMU_LFAPRESC0 */
6778 #define CMU_LFAPRESC0_LCD_DIV1                            (_CMU_LFAPRESC0_LCD_DIV1 << 12)         /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
6779 #define CMU_LFAPRESC0_LCD_DIV2                            (_CMU_LFAPRESC0_LCD_DIV2 << 12)         /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
6780 #define CMU_LFAPRESC0_LCD_DIV4                            (_CMU_LFAPRESC0_LCD_DIV4 << 12)         /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
6781 #define CMU_LFAPRESC0_LCD_DIV8                            (_CMU_LFAPRESC0_LCD_DIV8 << 12)         /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
6782 #define CMU_LFAPRESC0_LCD_DIV16                           (_CMU_LFAPRESC0_LCD_DIV16 << 12)        /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
6783 #define CMU_LFAPRESC0_LCD_DIV32                           (_CMU_LFAPRESC0_LCD_DIV32 << 12)        /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
6784 #define CMU_LFAPRESC0_LCD_DIV64                           (_CMU_LFAPRESC0_LCD_DIV64 << 12)        /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
6785 #define CMU_LFAPRESC0_LCD_DIV128                          (_CMU_LFAPRESC0_LCD_DIV128 << 12)       /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
6786 #define _CMU_LFAPRESC0_RTC_SHIFT                          16                                      /**< Shift value for CMU_RTC */
6787 #define _CMU_LFAPRESC0_RTC_MASK                           0xF0000UL                               /**< Bit mask for CMU_RTC */
6788 #define _CMU_LFAPRESC0_RTC_DIV1                           0x00000000UL                            /**< Mode DIV1 for CMU_LFAPRESC0 */
6789 #define _CMU_LFAPRESC0_RTC_DIV2                           0x00000001UL                            /**< Mode DIV2 for CMU_LFAPRESC0 */
6790 #define _CMU_LFAPRESC0_RTC_DIV4                           0x00000002UL                            /**< Mode DIV4 for CMU_LFAPRESC0 */
6791 #define _CMU_LFAPRESC0_RTC_DIV8                           0x00000003UL                            /**< Mode DIV8 for CMU_LFAPRESC0 */
6792 #define _CMU_LFAPRESC0_RTC_DIV16                          0x00000004UL                            /**< Mode DIV16 for CMU_LFAPRESC0 */
6793 #define _CMU_LFAPRESC0_RTC_DIV32                          0x00000005UL                            /**< Mode DIV32 for CMU_LFAPRESC0 */
6794 #define _CMU_LFAPRESC0_RTC_DIV64                          0x00000006UL                            /**< Mode DIV64 for CMU_LFAPRESC0 */
6795 #define _CMU_LFAPRESC0_RTC_DIV128                         0x00000007UL                            /**< Mode DIV128 for CMU_LFAPRESC0 */
6796 #define _CMU_LFAPRESC0_RTC_DIV256                         0x00000008UL                            /**< Mode DIV256 for CMU_LFAPRESC0 */
6797 #define _CMU_LFAPRESC0_RTC_DIV512                         0x00000009UL                            /**< Mode DIV512 for CMU_LFAPRESC0 */
6798 #define _CMU_LFAPRESC0_RTC_DIV1024                        0x0000000AUL                            /**< Mode DIV1024 for CMU_LFAPRESC0 */
6799 #define _CMU_LFAPRESC0_RTC_DIV2048                        0x0000000BUL                            /**< Mode DIV2048 for CMU_LFAPRESC0 */
6800 #define _CMU_LFAPRESC0_RTC_DIV4096                        0x0000000CUL                            /**< Mode DIV4096 for CMU_LFAPRESC0 */
6801 #define _CMU_LFAPRESC0_RTC_DIV8192                        0x0000000DUL                            /**< Mode DIV8192 for CMU_LFAPRESC0 */
6802 #define _CMU_LFAPRESC0_RTC_DIV16384                       0x0000000EUL                            /**< Mode DIV16384 for CMU_LFAPRESC0 */
6803 #define _CMU_LFAPRESC0_RTC_DIV32768                       0x0000000FUL                            /**< Mode DIV32768 for CMU_LFAPRESC0 */
6804 #define CMU_LFAPRESC0_RTC_DIV1                            (_CMU_LFAPRESC0_RTC_DIV1 << 16)         /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
6805 #define CMU_LFAPRESC0_RTC_DIV2                            (_CMU_LFAPRESC0_RTC_DIV2 << 16)         /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
6806 #define CMU_LFAPRESC0_RTC_DIV4                            (_CMU_LFAPRESC0_RTC_DIV4 << 16)         /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
6807 #define CMU_LFAPRESC0_RTC_DIV8                            (_CMU_LFAPRESC0_RTC_DIV8 << 16)         /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
6808 #define CMU_LFAPRESC0_RTC_DIV16                           (_CMU_LFAPRESC0_RTC_DIV16 << 16)        /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
6809 #define CMU_LFAPRESC0_RTC_DIV32                           (_CMU_LFAPRESC0_RTC_DIV32 << 16)        /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
6810 #define CMU_LFAPRESC0_RTC_DIV64                           (_CMU_LFAPRESC0_RTC_DIV64 << 16)        /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
6811 #define CMU_LFAPRESC0_RTC_DIV128                          (_CMU_LFAPRESC0_RTC_DIV128 << 16)       /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
6812 #define CMU_LFAPRESC0_RTC_DIV256                          (_CMU_LFAPRESC0_RTC_DIV256 << 16)       /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
6813 #define CMU_LFAPRESC0_RTC_DIV512                          (_CMU_LFAPRESC0_RTC_DIV512 << 16)       /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
6814 #define CMU_LFAPRESC0_RTC_DIV1024                         (_CMU_LFAPRESC0_RTC_DIV1024 << 16)      /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
6815 #define CMU_LFAPRESC0_RTC_DIV2048                         (_CMU_LFAPRESC0_RTC_DIV2048 << 16)      /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
6816 #define CMU_LFAPRESC0_RTC_DIV4096                         (_CMU_LFAPRESC0_RTC_DIV4096 << 16)      /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
6817 #define CMU_LFAPRESC0_RTC_DIV8192                         (_CMU_LFAPRESC0_RTC_DIV8192 << 16)      /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
6818 #define CMU_LFAPRESC0_RTC_DIV16384                        (_CMU_LFAPRESC0_RTC_DIV16384 << 16)     /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
6819 #define CMU_LFAPRESC0_RTC_DIV32768                        (_CMU_LFAPRESC0_RTC_DIV32768 << 16)     /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
6820 
6821 /* Bit fields for CMU LFBPRESC0 */
6822 #define _CMU_LFBPRESC0_RESETVALUE                         0x00000000UL                       /**< Default value for CMU_LFBPRESC0 */
6823 #define _CMU_LFBPRESC0_MASK                               0x00003F33UL                       /**< Mask for CMU_LFBPRESC0 */
6824 #define _CMU_LFBPRESC0_LEUART0_SHIFT                      0                                  /**< Shift value for CMU_LEUART0 */
6825 #define _CMU_LFBPRESC0_LEUART0_MASK                       0x3UL                              /**< Bit mask for CMU_LEUART0 */
6826 #define _CMU_LFBPRESC0_LEUART0_DIV1                       0x00000000UL                       /**< Mode DIV1 for CMU_LFBPRESC0 */
6827 #define _CMU_LFBPRESC0_LEUART0_DIV2                       0x00000001UL                       /**< Mode DIV2 for CMU_LFBPRESC0 */
6828 #define _CMU_LFBPRESC0_LEUART0_DIV4                       0x00000002UL                       /**< Mode DIV4 for CMU_LFBPRESC0 */
6829 #define _CMU_LFBPRESC0_LEUART0_DIV8                       0x00000003UL                       /**< Mode DIV8 for CMU_LFBPRESC0 */
6830 #define CMU_LFBPRESC0_LEUART0_DIV1                        (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
6831 #define CMU_LFBPRESC0_LEUART0_DIV2                        (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
6832 #define CMU_LFBPRESC0_LEUART0_DIV4                        (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
6833 #define CMU_LFBPRESC0_LEUART0_DIV8                        (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
6834 #define _CMU_LFBPRESC0_LEUART1_SHIFT                      4                                  /**< Shift value for CMU_LEUART1 */
6835 #define _CMU_LFBPRESC0_LEUART1_MASK                       0x30UL                             /**< Bit mask for CMU_LEUART1 */
6836 #define _CMU_LFBPRESC0_LEUART1_DIV1                       0x00000000UL                       /**< Mode DIV1 for CMU_LFBPRESC0 */
6837 #define _CMU_LFBPRESC0_LEUART1_DIV2                       0x00000001UL                       /**< Mode DIV2 for CMU_LFBPRESC0 */
6838 #define _CMU_LFBPRESC0_LEUART1_DIV4                       0x00000002UL                       /**< Mode DIV4 for CMU_LFBPRESC0 */
6839 #define _CMU_LFBPRESC0_LEUART1_DIV8                       0x00000003UL                       /**< Mode DIV8 for CMU_LFBPRESC0 */
6840 #define CMU_LFBPRESC0_LEUART1_DIV1                        (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
6841 #define CMU_LFBPRESC0_LEUART1_DIV2                        (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
6842 #define CMU_LFBPRESC0_LEUART1_DIV4                        (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
6843 #define CMU_LFBPRESC0_LEUART1_DIV8                        (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
6844 #define _CMU_LFBPRESC0_SYSTICK_SHIFT                      8                                  /**< Shift value for CMU_SYSTICK */
6845 #define _CMU_LFBPRESC0_SYSTICK_MASK                       0xF00UL                            /**< Bit mask for CMU_SYSTICK */
6846 #define _CMU_LFBPRESC0_SYSTICK_DIV1                       0x00000000UL                       /**< Mode DIV1 for CMU_LFBPRESC0 */
6847 #define CMU_LFBPRESC0_SYSTICK_DIV1                        (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
6848 #define _CMU_LFBPRESC0_CSEN_SHIFT                         12                                 /**< Shift value for CMU_CSEN */
6849 #define _CMU_LFBPRESC0_CSEN_MASK                          0x3000UL                           /**< Bit mask for CMU_CSEN */
6850 #define _CMU_LFBPRESC0_CSEN_DIV16                         0x00000000UL                       /**< Mode DIV16 for CMU_LFBPRESC0 */
6851 #define _CMU_LFBPRESC0_CSEN_DIV32                         0x00000001UL                       /**< Mode DIV32 for CMU_LFBPRESC0 */
6852 #define _CMU_LFBPRESC0_CSEN_DIV64                         0x00000002UL                       /**< Mode DIV64 for CMU_LFBPRESC0 */
6853 #define _CMU_LFBPRESC0_CSEN_DIV128                        0x00000003UL                       /**< Mode DIV128 for CMU_LFBPRESC0 */
6854 #define CMU_LFBPRESC0_CSEN_DIV16                          (_CMU_LFBPRESC0_CSEN_DIV16 << 12)  /**< Shifted mode DIV16 for CMU_LFBPRESC0 */
6855 #define CMU_LFBPRESC0_CSEN_DIV32                          (_CMU_LFBPRESC0_CSEN_DIV32 << 12)  /**< Shifted mode DIV32 for CMU_LFBPRESC0 */
6856 #define CMU_LFBPRESC0_CSEN_DIV64                          (_CMU_LFBPRESC0_CSEN_DIV64 << 12)  /**< Shifted mode DIV64 for CMU_LFBPRESC0 */
6857 #define CMU_LFBPRESC0_CSEN_DIV128                         (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */
6858 
6859 /* Bit fields for CMU LFEPRESC0 */
6860 #define _CMU_LFEPRESC0_RESETVALUE                         0x00000000UL                    /**< Default value for CMU_LFEPRESC0 */
6861 #define _CMU_LFEPRESC0_MASK                               0x00000003UL                    /**< Mask for CMU_LFEPRESC0 */
6862 #define _CMU_LFEPRESC0_RTCC_SHIFT                         0                               /**< Shift value for CMU_RTCC */
6863 #define _CMU_LFEPRESC0_RTCC_MASK                          0x3UL                           /**< Bit mask for CMU_RTCC */
6864 #define _CMU_LFEPRESC0_RTCC_DIV1                          0x00000000UL                    /**< Mode DIV1 for CMU_LFEPRESC0 */
6865 #define _CMU_LFEPRESC0_RTCC_DIV2                          0x00000001UL                    /**< Mode DIV2 for CMU_LFEPRESC0 */
6866 #define _CMU_LFEPRESC0_RTCC_DIV4                          0x00000002UL                    /**< Mode DIV4 for CMU_LFEPRESC0 */
6867 #define CMU_LFEPRESC0_RTCC_DIV1                           (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */
6868 #define CMU_LFEPRESC0_RTCC_DIV2                           (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */
6869 #define CMU_LFEPRESC0_RTCC_DIV4                           (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */
6870 
6871 /* Bit fields for CMU SYNCBUSY */
6872 #define _CMU_SYNCBUSY_RESETVALUE                          0x00000000UL                               /**< Default value for CMU_SYNCBUSY */
6873 #define _CMU_SYNCBUSY_MASK                                0x7F050155UL                               /**< Mask for CMU_SYNCBUSY */
6874 #define CMU_SYNCBUSY_LFACLKEN0                            (0x1UL << 0)                               /**< Low Frequency a Clock Enable 0 Busy */
6875 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT                     0                                          /**< Shift value for CMU_LFACLKEN0 */
6876 #define _CMU_SYNCBUSY_LFACLKEN0_MASK                      0x1UL                                      /**< Bit mask for CMU_LFACLKEN0 */
6877 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
6878 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT                    (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
6879 #define CMU_SYNCBUSY_LFAPRESC0                            (0x1UL << 2)                               /**< Low Frequency a Prescaler 0 Busy */
6880 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT                     2                                          /**< Shift value for CMU_LFAPRESC0 */
6881 #define _CMU_SYNCBUSY_LFAPRESC0_MASK                      0x4UL                                      /**< Bit mask for CMU_LFAPRESC0 */
6882 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
6883 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT                    (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)     /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
6884 #define CMU_SYNCBUSY_LFBCLKEN0                            (0x1UL << 4)                               /**< Low Frequency B Clock Enable 0 Busy */
6885 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT                     4                                          /**< Shift value for CMU_LFBCLKEN0 */
6886 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK                      0x10UL                                     /**< Bit mask for CMU_LFBCLKEN0 */
6887 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
6888 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT                    (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)     /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
6889 #define CMU_SYNCBUSY_LFBPRESC0                            (0x1UL << 6)                               /**< Low Frequency B Prescaler 0 Busy */
6890 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT                     6                                          /**< Shift value for CMU_LFBPRESC0 */
6891 #define _CMU_SYNCBUSY_LFBPRESC0_MASK                      0x40UL                                     /**< Bit mask for CMU_LFBPRESC0 */
6892 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
6893 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT                    (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)     /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
6894 #define CMU_SYNCBUSY_LFCCLKEN0                            (0x1UL << 8)                               /**< Low Frequency C Clock Enable 0 Busy */
6895 #define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT                     8                                          /**< Shift value for CMU_LFCCLKEN0 */
6896 #define _CMU_SYNCBUSY_LFCCLKEN0_MASK                      0x100UL                                    /**< Bit mask for CMU_LFCCLKEN0 */
6897 #define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
6898 #define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT                    (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8)     /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
6899 #define CMU_SYNCBUSY_LFECLKEN0                            (0x1UL << 16)                              /**< Low Frequency E Clock Enable 0 Busy */
6900 #define _CMU_SYNCBUSY_LFECLKEN0_SHIFT                     16                                         /**< Shift value for CMU_LFECLKEN0 */
6901 #define _CMU_SYNCBUSY_LFECLKEN0_MASK                      0x10000UL                                  /**< Bit mask for CMU_LFECLKEN0 */
6902 #define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
6903 #define CMU_SYNCBUSY_LFECLKEN0_DEFAULT                    (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16)    /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
6904 #define CMU_SYNCBUSY_LFEPRESC0                            (0x1UL << 18)                              /**< Low Frequency E Prescaler 0 Busy */
6905 #define _CMU_SYNCBUSY_LFEPRESC0_SHIFT                     18                                         /**< Shift value for CMU_LFEPRESC0 */
6906 #define _CMU_SYNCBUSY_LFEPRESC0_MASK                      0x40000UL                                  /**< Bit mask for CMU_LFEPRESC0 */
6907 #define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
6908 #define CMU_SYNCBUSY_LFEPRESC0_DEFAULT                    (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18)    /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
6909 #define CMU_SYNCBUSY_HFRCOBSY                             (0x1UL << 24)                              /**< HFRCO Busy */
6910 #define _CMU_SYNCBUSY_HFRCOBSY_SHIFT                      24                                         /**< Shift value for CMU_HFRCOBSY */
6911 #define _CMU_SYNCBUSY_HFRCOBSY_MASK                       0x1000000UL                                /**< Bit mask for CMU_HFRCOBSY */
6912 #define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
6913 #define CMU_SYNCBUSY_HFRCOBSY_DEFAULT                     (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24)     /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
6914 #define CMU_SYNCBUSY_AUXHFRCOBSY                          (0x1UL << 25)                              /**< AUXHFRCO Busy */
6915 #define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT                   25                                         /**< Shift value for CMU_AUXHFRCOBSY */
6916 #define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK                    0x2000000UL                                /**< Bit mask for CMU_AUXHFRCOBSY */
6917 #define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT                 0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
6918 #define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT                  (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25)  /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
6919 #define CMU_SYNCBUSY_LFRCOBSY                             (0x1UL << 26)                              /**< LFRCO Busy */
6920 #define _CMU_SYNCBUSY_LFRCOBSY_SHIFT                      26                                         /**< Shift value for CMU_LFRCOBSY */
6921 #define _CMU_SYNCBUSY_LFRCOBSY_MASK                       0x4000000UL                                /**< Bit mask for CMU_LFRCOBSY */
6922 #define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT                    0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
6923 #define CMU_SYNCBUSY_LFRCOBSY_DEFAULT                     (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26)     /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
6924 #define CMU_SYNCBUSY_LFRCOVREFBSY                         (0x1UL << 27)                              /**< LFRCO VREF Busy */
6925 #define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT                  27                                         /**< Shift value for CMU_LFRCOVREFBSY */
6926 #define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK                   0x8000000UL                                /**< Bit mask for CMU_LFRCOVREFBSY */
6927 #define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT                0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
6928 #define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT                 (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
6929 #define CMU_SYNCBUSY_HFXOBSY                              (0x1UL << 28)                              /**< HFXO Busy */
6930 #define _CMU_SYNCBUSY_HFXOBSY_SHIFT                       28                                         /**< Shift value for CMU_HFXOBSY */
6931 #define _CMU_SYNCBUSY_HFXOBSY_MASK                        0x10000000UL                               /**< Bit mask for CMU_HFXOBSY */
6932 #define _CMU_SYNCBUSY_HFXOBSY_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
6933 #define CMU_SYNCBUSY_HFXOBSY_DEFAULT                      (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28)      /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
6934 #define CMU_SYNCBUSY_LFXOBSY                              (0x1UL << 29)                              /**< LFXO Busy */
6935 #define _CMU_SYNCBUSY_LFXOBSY_SHIFT                       29                                         /**< Shift value for CMU_LFXOBSY */
6936 #define _CMU_SYNCBUSY_LFXOBSY_MASK                        0x20000000UL                               /**< Bit mask for CMU_LFXOBSY */
6937 #define _CMU_SYNCBUSY_LFXOBSY_DEFAULT                     0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
6938 #define CMU_SYNCBUSY_LFXOBSY_DEFAULT                      (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29)      /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
6939 #define CMU_SYNCBUSY_USHFRCOBSY                           (0x1UL << 30)                              /**< USHFRCO Busy */
6940 #define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT                    30                                         /**< Shift value for CMU_USHFRCOBSY */
6941 #define _CMU_SYNCBUSY_USHFRCOBSY_MASK                     0x40000000UL                               /**< Bit mask for CMU_USHFRCOBSY */
6942 #define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT                  0x00000000UL                               /**< Mode DEFAULT for CMU_SYNCBUSY */
6943 #define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT                   (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30)   /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
6944 
6945 /* Bit fields for CMU FREEZE */
6946 #define _CMU_FREEZE_RESETVALUE                            0x00000000UL                         /**< Default value for CMU_FREEZE */
6947 #define _CMU_FREEZE_MASK                                  0x00000001UL                         /**< Mask for CMU_FREEZE */
6948 #define CMU_FREEZE_REGFREEZE                              (0x1UL << 0)                         /**< Register Update Freeze */
6949 #define _CMU_FREEZE_REGFREEZE_SHIFT                       0                                    /**< Shift value for CMU_REGFREEZE */
6950 #define _CMU_FREEZE_REGFREEZE_MASK                        0x1UL                                /**< Bit mask for CMU_REGFREEZE */
6951 #define _CMU_FREEZE_REGFREEZE_DEFAULT                     0x00000000UL                         /**< Mode DEFAULT for CMU_FREEZE */
6952 #define _CMU_FREEZE_REGFREEZE_UPDATE                      0x00000000UL                         /**< Mode UPDATE for CMU_FREEZE */
6953 #define _CMU_FREEZE_REGFREEZE_FREEZE                      0x00000001UL                         /**< Mode FREEZE for CMU_FREEZE */
6954 #define CMU_FREEZE_REGFREEZE_DEFAULT                      (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
6955 #define CMU_FREEZE_REGFREEZE_UPDATE                       (_CMU_FREEZE_REGFREEZE_UPDATE << 0)  /**< Shifted mode UPDATE for CMU_FREEZE */
6956 #define CMU_FREEZE_REGFREEZE_FREEZE                       (_CMU_FREEZE_REGFREEZE_FREEZE << 0)  /**< Shifted mode FREEZE for CMU_FREEZE */
6957 
6958 /* Bit fields for CMU PCNTCTRL */
6959 #define _CMU_PCNTCTRL_RESETVALUE                          0x00000000UL                             /**< Default value for CMU_PCNTCTRL */
6960 #define _CMU_PCNTCTRL_MASK                                0x0000003FUL                             /**< Mask for CMU_PCNTCTRL */
6961 #define CMU_PCNTCTRL_PCNT0CLKEN                           (0x1UL << 0)                             /**< PCNT0 Clock Enable */
6962 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT                    0                                        /**< Shift value for CMU_PCNT0CLKEN */
6963 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK                     0x1UL                                    /**< Bit mask for CMU_PCNT0CLKEN */
6964 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
6965 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT                   (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
6966 #define CMU_PCNTCTRL_PCNT0CLKSEL                          (0x1UL << 1)                             /**< PCNT0 Clock Select */
6967 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT                   1                                        /**< Shift value for CMU_PCNT0CLKSEL */
6968 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK                    0x2UL                                    /**< Bit mask for CMU_PCNT0CLKSEL */
6969 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
6970 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK                  0x00000000UL                             /**< Mode LFACLK for CMU_PCNTCTRL */
6971 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0                 0x00000001UL                             /**< Mode PCNT0S0 for CMU_PCNTCTRL */
6972 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT                  (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
6973 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK                   (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)  /**< Shifted mode LFACLK for CMU_PCNTCTRL */
6974 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0                  (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
6975 #define CMU_PCNTCTRL_PCNT1CLKEN                           (0x1UL << 2)                             /**< PCNT1 Clock Enable */
6976 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT                    2                                        /**< Shift value for CMU_PCNT1CLKEN */
6977 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK                     0x4UL                                    /**< Bit mask for CMU_PCNT1CLKEN */
6978 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
6979 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT                   (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2)  /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
6980 #define CMU_PCNTCTRL_PCNT1CLKSEL                          (0x1UL << 3)                             /**< PCNT1 Clock Select */
6981 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT                   3                                        /**< Shift value for CMU_PCNT1CLKSEL */
6982 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK                    0x8UL                                    /**< Bit mask for CMU_PCNT1CLKSEL */
6983 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
6984 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK                  0x00000000UL                             /**< Mode LFACLK for CMU_PCNTCTRL */
6985 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0                 0x00000001UL                             /**< Mode PCNT1S0 for CMU_PCNTCTRL */
6986 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT                  (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
6987 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK                   (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3)  /**< Shifted mode LFACLK for CMU_PCNTCTRL */
6988 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0                  (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */
6989 #define CMU_PCNTCTRL_PCNT2CLKEN                           (0x1UL << 4)                             /**< PCNT2 Clock Enable */
6990 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT                    4                                        /**< Shift value for CMU_PCNT2CLKEN */
6991 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK                     0x10UL                                   /**< Bit mask for CMU_PCNT2CLKEN */
6992 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT                  0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
6993 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT                   (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4)  /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
6994 #define CMU_PCNTCTRL_PCNT2CLKSEL                          (0x1UL << 5)                             /**< PCNT2 Clock Select */
6995 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT                   5                                        /**< Shift value for CMU_PCNT2CLKSEL */
6996 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK                    0x20UL                                   /**< Bit mask for CMU_PCNT2CLKSEL */
6997 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT                 0x00000000UL                             /**< Mode DEFAULT for CMU_PCNTCTRL */
6998 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK                  0x00000000UL                             /**< Mode LFACLK for CMU_PCNTCTRL */
6999 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0                 0x00000001UL                             /**< Mode PCNT2S0 for CMU_PCNTCTRL */
7000 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT                  (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
7001 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK                   (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5)  /**< Shifted mode LFACLK for CMU_PCNTCTRL */
7002 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0                  (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */
7003 
7004 /* Bit fields for CMU ADCCTRL */
7005 #define _CMU_ADCCTRL_RESETVALUE                           0x00000000UL                               /**< Default value for CMU_ADCCTRL */
7006 #define _CMU_ADCCTRL_MASK                                 0x01330133UL                               /**< Mask for CMU_ADCCTRL */
7007 #define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT                     0                                          /**< Shift value for CMU_ADC0CLKDIV */
7008 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK                      0x3UL                                      /**< Bit mask for CMU_ADC0CLKDIV */
7009 #define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_ADCCTRL */
7010 #define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION                0x00000000UL                               /**< Mode NODIVISION for CMU_ADCCTRL */
7011 #define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT                    (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0)     /**< Shifted mode DEFAULT for CMU_ADCCTRL */
7012 #define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION                 (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0)  /**< Shifted mode NODIVISION for CMU_ADCCTRL */
7013 #define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT                     4                                          /**< Shift value for CMU_ADC0CLKSEL */
7014 #define _CMU_ADCCTRL_ADC0CLKSEL_MASK                      0x30UL                                     /**< Bit mask for CMU_ADC0CLKSEL */
7015 #define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_ADCCTRL */
7016 #define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED                  0x00000000UL                               /**< Mode DISABLED for CMU_ADCCTRL */
7017 #define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO                  0x00000001UL                               /**< Mode AUXHFRCO for CMU_ADCCTRL */
7018 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO                      0x00000002UL                               /**< Mode HFXO for CMU_ADCCTRL */
7019 #define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK                  0x00000003UL                               /**< Mode HFSRCCLK for CMU_ADCCTRL */
7020 #define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT                    (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4)     /**< Shifted mode DEFAULT for CMU_ADCCTRL */
7021 #define CMU_ADCCTRL_ADC0CLKSEL_DISABLED                   (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4)    /**< Shifted mode DISABLED for CMU_ADCCTRL */
7022 #define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO                   (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4)    /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */
7023 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO                       (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4)        /**< Shifted mode HFXO for CMU_ADCCTRL */
7024 #define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK                   (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4)    /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */
7025 #define CMU_ADCCTRL_ADC0CLKINV                            (0x1UL << 8)                               /**< Invert Clock Selected By ADC0CLKSEL */
7026 #define _CMU_ADCCTRL_ADC0CLKINV_SHIFT                     8                                          /**< Shift value for CMU_ADC0CLKINV */
7027 #define _CMU_ADCCTRL_ADC0CLKINV_MASK                      0x100UL                                    /**< Bit mask for CMU_ADC0CLKINV */
7028 #define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_ADCCTRL */
7029 #define CMU_ADCCTRL_ADC0CLKINV_DEFAULT                    (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8)     /**< Shifted mode DEFAULT for CMU_ADCCTRL */
7030 #define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT                     16                                         /**< Shift value for CMU_ADC1CLKDIV */
7031 #define _CMU_ADCCTRL_ADC1CLKDIV_MASK                      0x30000UL                                  /**< Bit mask for CMU_ADC1CLKDIV */
7032 #define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_ADCCTRL */
7033 #define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION                0x00000000UL                               /**< Mode NODIVISION for CMU_ADCCTRL */
7034 #define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT                    (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16)    /**< Shifted mode DEFAULT for CMU_ADCCTRL */
7035 #define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION                 (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */
7036 #define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT                     20                                         /**< Shift value for CMU_ADC1CLKSEL */
7037 #define _CMU_ADCCTRL_ADC1CLKSEL_MASK                      0x300000UL                                 /**< Bit mask for CMU_ADC1CLKSEL */
7038 #define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_ADCCTRL */
7039 #define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED                  0x00000000UL                               /**< Mode DISABLED for CMU_ADCCTRL */
7040 #define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO                  0x00000001UL                               /**< Mode AUXHFRCO for CMU_ADCCTRL */
7041 #define _CMU_ADCCTRL_ADC1CLKSEL_HFXO                      0x00000002UL                               /**< Mode HFXO for CMU_ADCCTRL */
7042 #define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK                  0x00000003UL                               /**< Mode HFSRCCLK for CMU_ADCCTRL */
7043 #define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT                    (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20)    /**< Shifted mode DEFAULT for CMU_ADCCTRL */
7044 #define CMU_ADCCTRL_ADC1CLKSEL_DISABLED                   (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20)   /**< Shifted mode DISABLED for CMU_ADCCTRL */
7045 #define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO                   (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20)   /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */
7046 #define CMU_ADCCTRL_ADC1CLKSEL_HFXO                       (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20)       /**< Shifted mode HFXO for CMU_ADCCTRL */
7047 #define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK                   (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20)   /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */
7048 #define CMU_ADCCTRL_ADC1CLKINV                            (0x1UL << 24)                              /**< Invert Clock Selected By ADC1CLKSEL */
7049 #define _CMU_ADCCTRL_ADC1CLKINV_SHIFT                     24                                         /**< Shift value for CMU_ADC1CLKINV */
7050 #define _CMU_ADCCTRL_ADC1CLKINV_MASK                      0x1000000UL                                /**< Bit mask for CMU_ADC1CLKINV */
7051 #define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT                   0x00000000UL                               /**< Mode DEFAULT for CMU_ADCCTRL */
7052 #define CMU_ADCCTRL_ADC1CLKINV_DEFAULT                    (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24)    /**< Shifted mode DEFAULT for CMU_ADCCTRL */
7053 
7054 /* Bit fields for CMU PDMCTRL */
7055 #define _CMU_PDMCTRL_RESETVALUE                           0x00000000UL                          /**< Default value for CMU_PDMCTRL */
7056 #define _CMU_PDMCTRL_MASK                                 0x00000083UL                          /**< Mask for CMU_PDMCTRL */
7057 #define _CMU_PDMCTRL_PDMCLKSEL_SHIFT                      0                                     /**< Shift value for CMU_PDMCLKSEL */
7058 #define _CMU_PDMCTRL_PDMCLKSEL_MASK                       0x3UL                                 /**< Bit mask for CMU_PDMCLKSEL */
7059 #define _CMU_PDMCTRL_PDMCLKSEL_DEFAULT                    0x00000000UL                          /**< Mode DEFAULT for CMU_PDMCTRL */
7060 #define _CMU_PDMCTRL_PDMCLKSEL_HFRCO                      0x00000000UL                          /**< Mode HFRCO for CMU_PDMCTRL */
7061 #define _CMU_PDMCTRL_PDMCLKSEL_HFXO                       0x00000001UL                          /**< Mode HFXO for CMU_PDMCTRL */
7062 #define _CMU_PDMCTRL_PDMCLKSEL_USHFRCO                    0x00000002UL                          /**< Mode USHFRCO for CMU_PDMCTRL */
7063 #define _CMU_PDMCTRL_PDMCLKSEL_CLKIN0                     0x00000003UL                          /**< Mode CLKIN0 for CMU_PDMCTRL */
7064 #define CMU_PDMCTRL_PDMCLKSEL_DEFAULT                     (_CMU_PDMCTRL_PDMCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PDMCTRL */
7065 #define CMU_PDMCTRL_PDMCLKSEL_HFRCO                       (_CMU_PDMCTRL_PDMCLKSEL_HFRCO << 0)   /**< Shifted mode HFRCO for CMU_PDMCTRL */
7066 #define CMU_PDMCTRL_PDMCLKSEL_HFXO                        (_CMU_PDMCTRL_PDMCLKSEL_HFXO << 0)    /**< Shifted mode HFXO for CMU_PDMCTRL */
7067 #define CMU_PDMCTRL_PDMCLKSEL_USHFRCO                     (_CMU_PDMCTRL_PDMCLKSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_PDMCTRL */
7068 #define CMU_PDMCTRL_PDMCLKSEL_CLKIN0                      (_CMU_PDMCTRL_PDMCLKSEL_CLKIN0 << 0)  /**< Shifted mode CLKIN0 for CMU_PDMCTRL */
7069 #define CMU_PDMCTRL_PDMCLKEN                              (0x1UL << 7)                          /**< PDM Core Clock Enable */
7070 #define _CMU_PDMCTRL_PDMCLKEN_SHIFT                       7                                     /**< Shift value for CMU_PDMCLKEN */
7071 #define _CMU_PDMCTRL_PDMCLKEN_MASK                        0x80UL                                /**< Bit mask for CMU_PDMCLKEN */
7072 #define _CMU_PDMCTRL_PDMCLKEN_DEFAULT                     0x00000000UL                          /**< Mode DEFAULT for CMU_PDMCTRL */
7073 #define CMU_PDMCTRL_PDMCLKEN_DEFAULT                      (_CMU_PDMCTRL_PDMCLKEN_DEFAULT << 7)  /**< Shifted mode DEFAULT for CMU_PDMCTRL */
7074 
7075 /* Bit fields for CMU ROUTEPEN */
7076 #define _CMU_ROUTEPEN_RESETVALUE                          0x00000000UL                            /**< Default value for CMU_ROUTEPEN */
7077 #define _CMU_ROUTEPEN_MASK                                0x10000007UL                            /**< Mask for CMU_ROUTEPEN */
7078 #define CMU_ROUTEPEN_CLKOUT0PEN                           (0x1UL << 0)                            /**< CLKOUT0 Pin Enable */
7079 #define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT                    0                                       /**< Shift value for CMU_CLKOUT0PEN */
7080 #define _CMU_ROUTEPEN_CLKOUT0PEN_MASK                     0x1UL                                   /**< Bit mask for CMU_CLKOUT0PEN */
7081 #define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT                  0x00000000UL                            /**< Mode DEFAULT for CMU_ROUTEPEN */
7082 #define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT                   (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */
7083 #define CMU_ROUTEPEN_CLKOUT1PEN                           (0x1UL << 1)                            /**< CLKOUT1 Pin Enable */
7084 #define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT                    1                                       /**< Shift value for CMU_CLKOUT1PEN */
7085 #define _CMU_ROUTEPEN_CLKOUT1PEN_MASK                     0x2UL                                   /**< Bit mask for CMU_CLKOUT1PEN */
7086 #define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT                  0x00000000UL                            /**< Mode DEFAULT for CMU_ROUTEPEN */
7087 #define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT                   (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */
7088 #define CMU_ROUTEPEN_CLKOUT2PEN                           (0x1UL << 2)                            /**< CLKOUT2 Pin Enable */
7089 #define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT                    2                                       /**< Shift value for CMU_CLKOUT2PEN */
7090 #define _CMU_ROUTEPEN_CLKOUT2PEN_MASK                     0x4UL                                   /**< Bit mask for CMU_CLKOUT2PEN */
7091 #define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT                  0x00000000UL                            /**< Mode DEFAULT for CMU_ROUTEPEN */
7092 #define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT                   (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */
7093 #define CMU_ROUTEPEN_CLKIN0PEN                            (0x1UL << 28)                           /**< CLKIN0 Pin Enable */
7094 #define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT                     28                                      /**< Shift value for CMU_CLKIN0PEN */
7095 #define _CMU_ROUTEPEN_CLKIN0PEN_MASK                      0x10000000UL                            /**< Bit mask for CMU_CLKIN0PEN */
7096 #define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT                   0x00000000UL                            /**< Mode DEFAULT for CMU_ROUTEPEN */
7097 #define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT                    (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */
7098 
7099 /* Bit fields for CMU ROUTELOC0 */
7100 #define _CMU_ROUTELOC0_RESETVALUE                         0x00000000UL                              /**< Default value for CMU_ROUTELOC0 */
7101 #define _CMU_ROUTELOC0_MASK                               0x00070707UL                              /**< Mask for CMU_ROUTELOC0 */
7102 #define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT                   0                                         /**< Shift value for CMU_CLKOUT0LOC */
7103 #define _CMU_ROUTELOC0_CLKOUT0LOC_MASK                    0x7UL                                     /**< Bit mask for CMU_CLKOUT0LOC */
7104 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0                    0x00000000UL                              /**< Mode LOC0 for CMU_ROUTELOC0 */
7105 #define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT                 0x00000000UL                              /**< Mode DEFAULT for CMU_ROUTELOC0 */
7106 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1                    0x00000001UL                              /**< Mode LOC1 for CMU_ROUTELOC0 */
7107 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2                    0x00000002UL                              /**< Mode LOC2 for CMU_ROUTELOC0 */
7108 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3                    0x00000003UL                              /**< Mode LOC3 for CMU_ROUTELOC0 */
7109 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4                    0x00000004UL                              /**< Mode LOC4 for CMU_ROUTELOC0 */
7110 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5                    0x00000005UL                              /**< Mode LOC5 for CMU_ROUTELOC0 */
7111 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC0                     (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0)     /**< Shifted mode LOC0 for CMU_ROUTELOC0 */
7112 #define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT                  (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */
7113 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC1                     (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0)     /**< Shifted mode LOC1 for CMU_ROUTELOC0 */
7114 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC2                     (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0)     /**< Shifted mode LOC2 for CMU_ROUTELOC0 */
7115 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC3                     (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0)     /**< Shifted mode LOC3 for CMU_ROUTELOC0 */
7116 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC4                     (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0)     /**< Shifted mode LOC4 for CMU_ROUTELOC0 */
7117 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC5                     (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0)     /**< Shifted mode LOC5 for CMU_ROUTELOC0 */
7118 #define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT                   8                                         /**< Shift value for CMU_CLKOUT1LOC */
7119 #define _CMU_ROUTELOC0_CLKOUT1LOC_MASK                    0x700UL                                   /**< Bit mask for CMU_CLKOUT1LOC */
7120 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0                    0x00000000UL                              /**< Mode LOC0 for CMU_ROUTELOC0 */
7121 #define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT                 0x00000000UL                              /**< Mode DEFAULT for CMU_ROUTELOC0 */
7122 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1                    0x00000001UL                              /**< Mode LOC1 for CMU_ROUTELOC0 */
7123 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2                    0x00000002UL                              /**< Mode LOC2 for CMU_ROUTELOC0 */
7124 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3                    0x00000003UL                              /**< Mode LOC3 for CMU_ROUTELOC0 */
7125 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4                    0x00000004UL                              /**< Mode LOC4 for CMU_ROUTELOC0 */
7126 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5                    0x00000005UL                              /**< Mode LOC5 for CMU_ROUTELOC0 */
7127 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC0                     (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8)     /**< Shifted mode LOC0 for CMU_ROUTELOC0 */
7128 #define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT                  (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8)  /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */
7129 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC1                     (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8)     /**< Shifted mode LOC1 for CMU_ROUTELOC0 */
7130 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC2                     (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8)     /**< Shifted mode LOC2 for CMU_ROUTELOC0 */
7131 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC3                     (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8)     /**< Shifted mode LOC3 for CMU_ROUTELOC0 */
7132 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC4                     (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8)     /**< Shifted mode LOC4 for CMU_ROUTELOC0 */
7133 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC5                     (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8)     /**< Shifted mode LOC5 for CMU_ROUTELOC0 */
7134 #define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT                   16                                        /**< Shift value for CMU_CLKOUT2LOC */
7135 #define _CMU_ROUTELOC0_CLKOUT2LOC_MASK                    0x70000UL                                 /**< Bit mask for CMU_CLKOUT2LOC */
7136 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0                    0x00000000UL                              /**< Mode LOC0 for CMU_ROUTELOC0 */
7137 #define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT                 0x00000000UL                              /**< Mode DEFAULT for CMU_ROUTELOC0 */
7138 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1                    0x00000001UL                              /**< Mode LOC1 for CMU_ROUTELOC0 */
7139 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2                    0x00000002UL                              /**< Mode LOC2 for CMU_ROUTELOC0 */
7140 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3                    0x00000003UL                              /**< Mode LOC3 for CMU_ROUTELOC0 */
7141 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4                    0x00000004UL                              /**< Mode LOC4 for CMU_ROUTELOC0 */
7142 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5                    0x00000005UL                              /**< Mode LOC5 for CMU_ROUTELOC0 */
7143 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC0                     (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16)    /**< Shifted mode LOC0 for CMU_ROUTELOC0 */
7144 #define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT                  (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */
7145 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC1                     (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16)    /**< Shifted mode LOC1 for CMU_ROUTELOC0 */
7146 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC2                     (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16)    /**< Shifted mode LOC2 for CMU_ROUTELOC0 */
7147 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC3                     (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16)    /**< Shifted mode LOC3 for CMU_ROUTELOC0 */
7148 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC4                     (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16)    /**< Shifted mode LOC4 for CMU_ROUTELOC0 */
7149 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC5                     (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16)    /**< Shifted mode LOC5 for CMU_ROUTELOC0 */
7150 
7151 /* Bit fields for CMU ROUTELOC1 */
7152 #define _CMU_ROUTELOC1_RESETVALUE                         0x00000000UL                            /**< Default value for CMU_ROUTELOC1 */
7153 #define _CMU_ROUTELOC1_MASK                               0x00000007UL                            /**< Mask for CMU_ROUTELOC1 */
7154 #define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT                    0                                       /**< Shift value for CMU_CLKIN0LOC */
7155 #define _CMU_ROUTELOC1_CLKIN0LOC_MASK                     0x7UL                                   /**< Bit mask for CMU_CLKIN0LOC */
7156 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC0                     0x00000000UL                            /**< Mode LOC0 for CMU_ROUTELOC1 */
7157 #define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT                  0x00000000UL                            /**< Mode DEFAULT for CMU_ROUTELOC1 */
7158 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC1                     0x00000001UL                            /**< Mode LOC1 for CMU_ROUTELOC1 */
7159 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC2                     0x00000002UL                            /**< Mode LOC2 for CMU_ROUTELOC1 */
7160 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC3                     0x00000003UL                            /**< Mode LOC3 for CMU_ROUTELOC1 */
7161 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC4                     0x00000004UL                            /**< Mode LOC4 for CMU_ROUTELOC1 */
7162 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC5                     0x00000005UL                            /**< Mode LOC5 for CMU_ROUTELOC1 */
7163 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC6                     0x00000006UL                            /**< Mode LOC6 for CMU_ROUTELOC1 */
7164 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC7                     0x00000007UL                            /**< Mode LOC7 for CMU_ROUTELOC1 */
7165 #define CMU_ROUTELOC1_CLKIN0LOC_LOC0                      (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0)    /**< Shifted mode LOC0 for CMU_ROUTELOC1 */
7166 #define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT                   (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */
7167 #define CMU_ROUTELOC1_CLKIN0LOC_LOC1                      (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0)    /**< Shifted mode LOC1 for CMU_ROUTELOC1 */
7168 #define CMU_ROUTELOC1_CLKIN0LOC_LOC2                      (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0)    /**< Shifted mode LOC2 for CMU_ROUTELOC1 */
7169 #define CMU_ROUTELOC1_CLKIN0LOC_LOC3                      (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0)    /**< Shifted mode LOC3 for CMU_ROUTELOC1 */
7170 #define CMU_ROUTELOC1_CLKIN0LOC_LOC4                      (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0)    /**< Shifted mode LOC4 for CMU_ROUTELOC1 */
7171 #define CMU_ROUTELOC1_CLKIN0LOC_LOC5                      (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0)    /**< Shifted mode LOC5 for CMU_ROUTELOC1 */
7172 #define CMU_ROUTELOC1_CLKIN0LOC_LOC6                      (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0)    /**< Shifted mode LOC6 for CMU_ROUTELOC1 */
7173 #define CMU_ROUTELOC1_CLKIN0LOC_LOC7                      (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0)    /**< Shifted mode LOC7 for CMU_ROUTELOC1 */
7174 
7175 /* Bit fields for CMU LOCK */
7176 #define _CMU_LOCK_RESETVALUE                              0x00000000UL                      /**< Default value for CMU_LOCK */
7177 #define _CMU_LOCK_MASK                                    0x0000FFFFUL                      /**< Mask for CMU_LOCK */
7178 #define _CMU_LOCK_LOCKKEY_SHIFT                           0                                 /**< Shift value for CMU_LOCKKEY */
7179 #define _CMU_LOCK_LOCKKEY_MASK                            0xFFFFUL                          /**< Bit mask for CMU_LOCKKEY */
7180 #define _CMU_LOCK_LOCKKEY_DEFAULT                         0x00000000UL                      /**< Mode DEFAULT for CMU_LOCK */
7181 #define _CMU_LOCK_LOCKKEY_UNLOCKED                        0x00000000UL                      /**< Mode UNLOCKED for CMU_LOCK */
7182 #define _CMU_LOCK_LOCKKEY_LOCK                            0x00000000UL                      /**< Mode LOCK for CMU_LOCK */
7183 #define _CMU_LOCK_LOCKKEY_LOCKED                          0x00000001UL                      /**< Mode LOCKED for CMU_LOCK */
7184 #define _CMU_LOCK_LOCKKEY_UNLOCK                          0x0000580EUL                      /**< Mode UNLOCK for CMU_LOCK */
7185 #define CMU_LOCK_LOCKKEY_DEFAULT                          (_CMU_LOCK_LOCKKEY_DEFAULT << 0)  /**< Shifted mode DEFAULT for CMU_LOCK */
7186 #define CMU_LOCK_LOCKKEY_UNLOCKED                         (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
7187 #define CMU_LOCK_LOCKKEY_LOCK                             (_CMU_LOCK_LOCKKEY_LOCK << 0)     /**< Shifted mode LOCK for CMU_LOCK */
7188 #define CMU_LOCK_LOCKKEY_LOCKED                           (_CMU_LOCK_LOCKKEY_LOCKED << 0)   /**< Shifted mode LOCKED for CMU_LOCK */
7189 #define CMU_LOCK_LOCKKEY_UNLOCK                           (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   /**< Shifted mode UNLOCK for CMU_LOCK */
7190 
7191 /* Bit fields for CMU HFRCOSS */
7192 #define _CMU_HFRCOSS_RESETVALUE                           0x00000000UL                      /**< Default value for CMU_HFRCOSS */
7193 #define _CMU_HFRCOSS_MASK                                 0x00001F07UL                      /**< Mask for CMU_HFRCOSS */
7194 #define _CMU_HFRCOSS_SSAMP_SHIFT                          0                                 /**< Shift value for CMU_SSAMP */
7195 #define _CMU_HFRCOSS_SSAMP_MASK                           0x7UL                             /**< Bit mask for CMU_SSAMP */
7196 #define _CMU_HFRCOSS_SSAMP_DEFAULT                        0x00000000UL                      /**< Mode DEFAULT for CMU_HFRCOSS */
7197 #define CMU_HFRCOSS_SSAMP_DEFAULT                         (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */
7198 #define _CMU_HFRCOSS_SSINV_SHIFT                          8                                 /**< Shift value for CMU_SSINV */
7199 #define _CMU_HFRCOSS_SSINV_MASK                           0x1F00UL                          /**< Bit mask for CMU_SSINV */
7200 #define _CMU_HFRCOSS_SSINV_DEFAULT                        0x00000000UL                      /**< Mode DEFAULT for CMU_HFRCOSS */
7201 #define CMU_HFRCOSS_SSINV_DEFAULT                         (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */
7202 
7203 /** @} */
7204 /** @} End of group EFM32GG12B310F1024GQ100_CMU */
7205 
7206 /***************************************************************************//**
7207  * @addtogroup EFM32GG12B310F1024GQ100_PRS
7208  * @{
7209  * @defgroup EFM32GG12B310F1024GQ100_PRS_BitFields  PRS Bit Fields
7210  * @{
7211  ******************************************************************************/
7212 
7213 /* Bit fields for PRS SWPULSE */
7214 #define _PRS_SWPULSE_RESETVALUE                    0x00000000UL                           /**< Default value for PRS_SWPULSE */
7215 #define _PRS_SWPULSE_MASK                          0x0000FFFFUL                           /**< Mask for PRS_SWPULSE */
7216 #define PRS_SWPULSE_CH0PULSE                       (0x1UL << 0)                           /**< Channel 0 Pulse Generation */
7217 #define _PRS_SWPULSE_CH0PULSE_SHIFT                0                                      /**< Shift value for PRS_CH0PULSE */
7218 #define _PRS_SWPULSE_CH0PULSE_MASK                 0x1UL                                  /**< Bit mask for PRS_CH0PULSE */
7219 #define _PRS_SWPULSE_CH0PULSE_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7220 #define PRS_SWPULSE_CH0PULSE_DEFAULT               (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
7221 #define PRS_SWPULSE_CH1PULSE                       (0x1UL << 1)                           /**< Channel 1 Pulse Generation */
7222 #define _PRS_SWPULSE_CH1PULSE_SHIFT                1                                      /**< Shift value for PRS_CH1PULSE */
7223 #define _PRS_SWPULSE_CH1PULSE_MASK                 0x2UL                                  /**< Bit mask for PRS_CH1PULSE */
7224 #define _PRS_SWPULSE_CH1PULSE_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7225 #define PRS_SWPULSE_CH1PULSE_DEFAULT               (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
7226 #define PRS_SWPULSE_CH2PULSE                       (0x1UL << 2)                           /**< Channel 2 Pulse Generation */
7227 #define _PRS_SWPULSE_CH2PULSE_SHIFT                2                                      /**< Shift value for PRS_CH2PULSE */
7228 #define _PRS_SWPULSE_CH2PULSE_MASK                 0x4UL                                  /**< Bit mask for PRS_CH2PULSE */
7229 #define _PRS_SWPULSE_CH2PULSE_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7230 #define PRS_SWPULSE_CH2PULSE_DEFAULT               (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
7231 #define PRS_SWPULSE_CH3PULSE                       (0x1UL << 3)                           /**< Channel 3 Pulse Generation */
7232 #define _PRS_SWPULSE_CH3PULSE_SHIFT                3                                      /**< Shift value for PRS_CH3PULSE */
7233 #define _PRS_SWPULSE_CH3PULSE_MASK                 0x8UL                                  /**< Bit mask for PRS_CH3PULSE */
7234 #define _PRS_SWPULSE_CH3PULSE_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7235 #define PRS_SWPULSE_CH3PULSE_DEFAULT               (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
7236 #define PRS_SWPULSE_CH4PULSE                       (0x1UL << 4)                           /**< Channel 4 Pulse Generation */
7237 #define _PRS_SWPULSE_CH4PULSE_SHIFT                4                                      /**< Shift value for PRS_CH4PULSE */
7238 #define _PRS_SWPULSE_CH4PULSE_MASK                 0x10UL                                 /**< Bit mask for PRS_CH4PULSE */
7239 #define _PRS_SWPULSE_CH4PULSE_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7240 #define PRS_SWPULSE_CH4PULSE_DEFAULT               (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
7241 #define PRS_SWPULSE_CH5PULSE                       (0x1UL << 5)                           /**< Channel 5 Pulse Generation */
7242 #define _PRS_SWPULSE_CH5PULSE_SHIFT                5                                      /**< Shift value for PRS_CH5PULSE */
7243 #define _PRS_SWPULSE_CH5PULSE_MASK                 0x20UL                                 /**< Bit mask for PRS_CH5PULSE */
7244 #define _PRS_SWPULSE_CH5PULSE_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7245 #define PRS_SWPULSE_CH5PULSE_DEFAULT               (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
7246 #define PRS_SWPULSE_CH6PULSE                       (0x1UL << 6)                           /**< Channel 6 Pulse Generation */
7247 #define _PRS_SWPULSE_CH6PULSE_SHIFT                6                                      /**< Shift value for PRS_CH6PULSE */
7248 #define _PRS_SWPULSE_CH6PULSE_MASK                 0x40UL                                 /**< Bit mask for PRS_CH6PULSE */
7249 #define _PRS_SWPULSE_CH6PULSE_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7250 #define PRS_SWPULSE_CH6PULSE_DEFAULT               (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
7251 #define PRS_SWPULSE_CH7PULSE                       (0x1UL << 7)                           /**< Channel 7 Pulse Generation */
7252 #define _PRS_SWPULSE_CH7PULSE_SHIFT                7                                      /**< Shift value for PRS_CH7PULSE */
7253 #define _PRS_SWPULSE_CH7PULSE_MASK                 0x80UL                                 /**< Bit mask for PRS_CH7PULSE */
7254 #define _PRS_SWPULSE_CH7PULSE_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7255 #define PRS_SWPULSE_CH7PULSE_DEFAULT               (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
7256 #define PRS_SWPULSE_CH8PULSE                       (0x1UL << 8)                           /**< Channel 8 Pulse Generation */
7257 #define _PRS_SWPULSE_CH8PULSE_SHIFT                8                                      /**< Shift value for PRS_CH8PULSE */
7258 #define _PRS_SWPULSE_CH8PULSE_MASK                 0x100UL                                /**< Bit mask for PRS_CH8PULSE */
7259 #define _PRS_SWPULSE_CH8PULSE_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7260 #define PRS_SWPULSE_CH8PULSE_DEFAULT               (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
7261 #define PRS_SWPULSE_CH9PULSE                       (0x1UL << 9)                           /**< Channel 9 Pulse Generation */
7262 #define _PRS_SWPULSE_CH9PULSE_SHIFT                9                                      /**< Shift value for PRS_CH9PULSE */
7263 #define _PRS_SWPULSE_CH9PULSE_MASK                 0x200UL                                /**< Bit mask for PRS_CH9PULSE */
7264 #define _PRS_SWPULSE_CH9PULSE_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7265 #define PRS_SWPULSE_CH9PULSE_DEFAULT               (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9)   /**< Shifted mode DEFAULT for PRS_SWPULSE */
7266 #define PRS_SWPULSE_CH10PULSE                      (0x1UL << 10)                          /**< Channel 10 Pulse Generation */
7267 #define _PRS_SWPULSE_CH10PULSE_SHIFT               10                                     /**< Shift value for PRS_CH10PULSE */
7268 #define _PRS_SWPULSE_CH10PULSE_MASK                0x400UL                                /**< Bit mask for PRS_CH10PULSE */
7269 #define _PRS_SWPULSE_CH10PULSE_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7270 #define PRS_SWPULSE_CH10PULSE_DEFAULT              (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */
7271 #define PRS_SWPULSE_CH11PULSE                      (0x1UL << 11)                          /**< Channel 11 Pulse Generation */
7272 #define _PRS_SWPULSE_CH11PULSE_SHIFT               11                                     /**< Shift value for PRS_CH11PULSE */
7273 #define _PRS_SWPULSE_CH11PULSE_MASK                0x800UL                                /**< Bit mask for PRS_CH11PULSE */
7274 #define _PRS_SWPULSE_CH11PULSE_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7275 #define PRS_SWPULSE_CH11PULSE_DEFAULT              (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */
7276 #define PRS_SWPULSE_CH12PULSE                      (0x1UL << 12)                          /**< Channel 12 Pulse Generation */
7277 #define _PRS_SWPULSE_CH12PULSE_SHIFT               12                                     /**< Shift value for PRS_CH12PULSE */
7278 #define _PRS_SWPULSE_CH12PULSE_MASK                0x1000UL                               /**< Bit mask for PRS_CH12PULSE */
7279 #define _PRS_SWPULSE_CH12PULSE_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7280 #define PRS_SWPULSE_CH12PULSE_DEFAULT              (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */
7281 #define PRS_SWPULSE_CH13PULSE                      (0x1UL << 13)                          /**< Channel 13 Pulse Generation */
7282 #define _PRS_SWPULSE_CH13PULSE_SHIFT               13                                     /**< Shift value for PRS_CH13PULSE */
7283 #define _PRS_SWPULSE_CH13PULSE_MASK                0x2000UL                               /**< Bit mask for PRS_CH13PULSE */
7284 #define _PRS_SWPULSE_CH13PULSE_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7285 #define PRS_SWPULSE_CH13PULSE_DEFAULT              (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */
7286 #define PRS_SWPULSE_CH14PULSE                      (0x1UL << 14)                          /**< Channel 14 Pulse Generation */
7287 #define _PRS_SWPULSE_CH14PULSE_SHIFT               14                                     /**< Shift value for PRS_CH14PULSE */
7288 #define _PRS_SWPULSE_CH14PULSE_MASK                0x4000UL                               /**< Bit mask for PRS_CH14PULSE */
7289 #define _PRS_SWPULSE_CH14PULSE_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7290 #define PRS_SWPULSE_CH14PULSE_DEFAULT              (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */
7291 #define PRS_SWPULSE_CH15PULSE                      (0x1UL << 15)                          /**< Channel 15 Pulse Generation */
7292 #define _PRS_SWPULSE_CH15PULSE_SHIFT               15                                     /**< Shift value for PRS_CH15PULSE */
7293 #define _PRS_SWPULSE_CH15PULSE_MASK                0x8000UL                               /**< Bit mask for PRS_CH15PULSE */
7294 #define _PRS_SWPULSE_CH15PULSE_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_SWPULSE */
7295 #define PRS_SWPULSE_CH15PULSE_DEFAULT              (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */
7296 
7297 /* Bit fields for PRS SWLEVEL */
7298 #define _PRS_SWLEVEL_RESETVALUE                    0x00000000UL                           /**< Default value for PRS_SWLEVEL */
7299 #define _PRS_SWLEVEL_MASK                          0x0000FFFFUL                           /**< Mask for PRS_SWLEVEL */
7300 #define PRS_SWLEVEL_CH0LEVEL                       (0x1UL << 0)                           /**< Channel 0 Software Level */
7301 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT                0                                      /**< Shift value for PRS_CH0LEVEL */
7302 #define _PRS_SWLEVEL_CH0LEVEL_MASK                 0x1UL                                  /**< Bit mask for PRS_CH0LEVEL */
7303 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7304 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT               (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7305 #define PRS_SWLEVEL_CH1LEVEL                       (0x1UL << 1)                           /**< Channel 1 Software Level */
7306 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT                1                                      /**< Shift value for PRS_CH1LEVEL */
7307 #define _PRS_SWLEVEL_CH1LEVEL_MASK                 0x2UL                                  /**< Bit mask for PRS_CH1LEVEL */
7308 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7309 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT               (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7310 #define PRS_SWLEVEL_CH2LEVEL                       (0x1UL << 2)                           /**< Channel 2 Software Level */
7311 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT                2                                      /**< Shift value for PRS_CH2LEVEL */
7312 #define _PRS_SWLEVEL_CH2LEVEL_MASK                 0x4UL                                  /**< Bit mask for PRS_CH2LEVEL */
7313 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7314 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT               (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7315 #define PRS_SWLEVEL_CH3LEVEL                       (0x1UL << 3)                           /**< Channel 3 Software Level */
7316 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT                3                                      /**< Shift value for PRS_CH3LEVEL */
7317 #define _PRS_SWLEVEL_CH3LEVEL_MASK                 0x8UL                                  /**< Bit mask for PRS_CH3LEVEL */
7318 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7319 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT               (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7320 #define PRS_SWLEVEL_CH4LEVEL                       (0x1UL << 4)                           /**< Channel 4 Software Level */
7321 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT                4                                      /**< Shift value for PRS_CH4LEVEL */
7322 #define _PRS_SWLEVEL_CH4LEVEL_MASK                 0x10UL                                 /**< Bit mask for PRS_CH4LEVEL */
7323 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7324 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT               (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7325 #define PRS_SWLEVEL_CH5LEVEL                       (0x1UL << 5)                           /**< Channel 5 Software Level */
7326 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT                5                                      /**< Shift value for PRS_CH5LEVEL */
7327 #define _PRS_SWLEVEL_CH5LEVEL_MASK                 0x20UL                                 /**< Bit mask for PRS_CH5LEVEL */
7328 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7329 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT               (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7330 #define PRS_SWLEVEL_CH6LEVEL                       (0x1UL << 6)                           /**< Channel 6 Software Level */
7331 #define _PRS_SWLEVEL_CH6LEVEL_SHIFT                6                                      /**< Shift value for PRS_CH6LEVEL */
7332 #define _PRS_SWLEVEL_CH6LEVEL_MASK                 0x40UL                                 /**< Bit mask for PRS_CH6LEVEL */
7333 #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7334 #define PRS_SWLEVEL_CH6LEVEL_DEFAULT               (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7335 #define PRS_SWLEVEL_CH7LEVEL                       (0x1UL << 7)                           /**< Channel 7 Software Level */
7336 #define _PRS_SWLEVEL_CH7LEVEL_SHIFT                7                                      /**< Shift value for PRS_CH7LEVEL */
7337 #define _PRS_SWLEVEL_CH7LEVEL_MASK                 0x80UL                                 /**< Bit mask for PRS_CH7LEVEL */
7338 #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7339 #define PRS_SWLEVEL_CH7LEVEL_DEFAULT               (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7340 #define PRS_SWLEVEL_CH8LEVEL                       (0x1UL << 8)                           /**< Channel 8 Software Level */
7341 #define _PRS_SWLEVEL_CH8LEVEL_SHIFT                8                                      /**< Shift value for PRS_CH8LEVEL */
7342 #define _PRS_SWLEVEL_CH8LEVEL_MASK                 0x100UL                                /**< Bit mask for PRS_CH8LEVEL */
7343 #define _PRS_SWLEVEL_CH8LEVEL_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7344 #define PRS_SWLEVEL_CH8LEVEL_DEFAULT               (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7345 #define PRS_SWLEVEL_CH9LEVEL                       (0x1UL << 9)                           /**< Channel 9 Software Level */
7346 #define _PRS_SWLEVEL_CH9LEVEL_SHIFT                9                                      /**< Shift value for PRS_CH9LEVEL */
7347 #define _PRS_SWLEVEL_CH9LEVEL_MASK                 0x200UL                                /**< Bit mask for PRS_CH9LEVEL */
7348 #define _PRS_SWLEVEL_CH9LEVEL_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7349 #define PRS_SWLEVEL_CH9LEVEL_DEFAULT               (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9)   /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7350 #define PRS_SWLEVEL_CH10LEVEL                      (0x1UL << 10)                          /**< Channel 10 Software Level */
7351 #define _PRS_SWLEVEL_CH10LEVEL_SHIFT               10                                     /**< Shift value for PRS_CH10LEVEL */
7352 #define _PRS_SWLEVEL_CH10LEVEL_MASK                0x400UL                                /**< Bit mask for PRS_CH10LEVEL */
7353 #define _PRS_SWLEVEL_CH10LEVEL_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7354 #define PRS_SWLEVEL_CH10LEVEL_DEFAULT              (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7355 #define PRS_SWLEVEL_CH11LEVEL                      (0x1UL << 11)                          /**< Channel 11 Software Level */
7356 #define _PRS_SWLEVEL_CH11LEVEL_SHIFT               11                                     /**< Shift value for PRS_CH11LEVEL */
7357 #define _PRS_SWLEVEL_CH11LEVEL_MASK                0x800UL                                /**< Bit mask for PRS_CH11LEVEL */
7358 #define _PRS_SWLEVEL_CH11LEVEL_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7359 #define PRS_SWLEVEL_CH11LEVEL_DEFAULT              (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7360 #define PRS_SWLEVEL_CH12LEVEL                      (0x1UL << 12)                          /**< Channel 12 Software Level */
7361 #define _PRS_SWLEVEL_CH12LEVEL_SHIFT               12                                     /**< Shift value for PRS_CH12LEVEL */
7362 #define _PRS_SWLEVEL_CH12LEVEL_MASK                0x1000UL                               /**< Bit mask for PRS_CH12LEVEL */
7363 #define _PRS_SWLEVEL_CH12LEVEL_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7364 #define PRS_SWLEVEL_CH12LEVEL_DEFAULT              (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7365 #define PRS_SWLEVEL_CH13LEVEL                      (0x1UL << 13)                          /**< Channel 13 Software Level */
7366 #define _PRS_SWLEVEL_CH13LEVEL_SHIFT               13                                     /**< Shift value for PRS_CH13LEVEL */
7367 #define _PRS_SWLEVEL_CH13LEVEL_MASK                0x2000UL                               /**< Bit mask for PRS_CH13LEVEL */
7368 #define _PRS_SWLEVEL_CH13LEVEL_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7369 #define PRS_SWLEVEL_CH13LEVEL_DEFAULT              (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7370 #define PRS_SWLEVEL_CH14LEVEL                      (0x1UL << 14)                          /**< Channel 14 Software Level */
7371 #define _PRS_SWLEVEL_CH14LEVEL_SHIFT               14                                     /**< Shift value for PRS_CH14LEVEL */
7372 #define _PRS_SWLEVEL_CH14LEVEL_MASK                0x4000UL                               /**< Bit mask for PRS_CH14LEVEL */
7373 #define _PRS_SWLEVEL_CH14LEVEL_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7374 #define PRS_SWLEVEL_CH14LEVEL_DEFAULT              (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7375 #define PRS_SWLEVEL_CH15LEVEL                      (0x1UL << 15)                          /**< Channel 15 Software Level */
7376 #define _PRS_SWLEVEL_CH15LEVEL_SHIFT               15                                     /**< Shift value for PRS_CH15LEVEL */
7377 #define _PRS_SWLEVEL_CH15LEVEL_MASK                0x8000UL                               /**< Bit mask for PRS_CH15LEVEL */
7378 #define _PRS_SWLEVEL_CH15LEVEL_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_SWLEVEL */
7379 #define PRS_SWLEVEL_CH15LEVEL_DEFAULT              (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
7380 
7381 /* Bit fields for PRS ROUTEPEN */
7382 #define _PRS_ROUTEPEN_RESETVALUE                   0x00000000UL                          /**< Default value for PRS_ROUTEPEN */
7383 #define _PRS_ROUTEPEN_MASK                         0x0000FFFFUL                          /**< Mask for PRS_ROUTEPEN */
7384 #define PRS_ROUTEPEN_CH0PEN                        (0x1UL << 0)                          /**< CH0 Pin Enable */
7385 #define _PRS_ROUTEPEN_CH0PEN_SHIFT                 0                                     /**< Shift value for PRS_CH0PEN */
7386 #define _PRS_ROUTEPEN_CH0PEN_MASK                  0x1UL                                 /**< Bit mask for PRS_CH0PEN */
7387 #define _PRS_ROUTEPEN_CH0PEN_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7388 #define PRS_ROUTEPEN_CH0PEN_DEFAULT                (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7389 #define PRS_ROUTEPEN_CH1PEN                        (0x1UL << 1)                          /**< CH1 Pin Enable */
7390 #define _PRS_ROUTEPEN_CH1PEN_SHIFT                 1                                     /**< Shift value for PRS_CH1PEN */
7391 #define _PRS_ROUTEPEN_CH1PEN_MASK                  0x2UL                                 /**< Bit mask for PRS_CH1PEN */
7392 #define _PRS_ROUTEPEN_CH1PEN_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7393 #define PRS_ROUTEPEN_CH1PEN_DEFAULT                (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7394 #define PRS_ROUTEPEN_CH2PEN                        (0x1UL << 2)                          /**< CH2 Pin Enable */
7395 #define _PRS_ROUTEPEN_CH2PEN_SHIFT                 2                                     /**< Shift value for PRS_CH2PEN */
7396 #define _PRS_ROUTEPEN_CH2PEN_MASK                  0x4UL                                 /**< Bit mask for PRS_CH2PEN */
7397 #define _PRS_ROUTEPEN_CH2PEN_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7398 #define PRS_ROUTEPEN_CH2PEN_DEFAULT                (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7399 #define PRS_ROUTEPEN_CH3PEN                        (0x1UL << 3)                          /**< CH3 Pin Enable */
7400 #define _PRS_ROUTEPEN_CH3PEN_SHIFT                 3                                     /**< Shift value for PRS_CH3PEN */
7401 #define _PRS_ROUTEPEN_CH3PEN_MASK                  0x8UL                                 /**< Bit mask for PRS_CH3PEN */
7402 #define _PRS_ROUTEPEN_CH3PEN_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7403 #define PRS_ROUTEPEN_CH3PEN_DEFAULT                (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7404 #define PRS_ROUTEPEN_CH4PEN                        (0x1UL << 4)                          /**< CH4 Pin Enable */
7405 #define _PRS_ROUTEPEN_CH4PEN_SHIFT                 4                                     /**< Shift value for PRS_CH4PEN */
7406 #define _PRS_ROUTEPEN_CH4PEN_MASK                  0x10UL                                /**< Bit mask for PRS_CH4PEN */
7407 #define _PRS_ROUTEPEN_CH4PEN_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7408 #define PRS_ROUTEPEN_CH4PEN_DEFAULT                (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7409 #define PRS_ROUTEPEN_CH5PEN                        (0x1UL << 5)                          /**< CH5 Pin Enable */
7410 #define _PRS_ROUTEPEN_CH5PEN_SHIFT                 5                                     /**< Shift value for PRS_CH5PEN */
7411 #define _PRS_ROUTEPEN_CH5PEN_MASK                  0x20UL                                /**< Bit mask for PRS_CH5PEN */
7412 #define _PRS_ROUTEPEN_CH5PEN_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7413 #define PRS_ROUTEPEN_CH5PEN_DEFAULT                (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7414 #define PRS_ROUTEPEN_CH6PEN                        (0x1UL << 6)                          /**< CH6 Pin Enable */
7415 #define _PRS_ROUTEPEN_CH6PEN_SHIFT                 6                                     /**< Shift value for PRS_CH6PEN */
7416 #define _PRS_ROUTEPEN_CH6PEN_MASK                  0x40UL                                /**< Bit mask for PRS_CH6PEN */
7417 #define _PRS_ROUTEPEN_CH6PEN_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7418 #define PRS_ROUTEPEN_CH6PEN_DEFAULT                (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7419 #define PRS_ROUTEPEN_CH7PEN                        (0x1UL << 7)                          /**< CH7 Pin Enable */
7420 #define _PRS_ROUTEPEN_CH7PEN_SHIFT                 7                                     /**< Shift value for PRS_CH7PEN */
7421 #define _PRS_ROUTEPEN_CH7PEN_MASK                  0x80UL                                /**< Bit mask for PRS_CH7PEN */
7422 #define _PRS_ROUTEPEN_CH7PEN_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7423 #define PRS_ROUTEPEN_CH7PEN_DEFAULT                (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7424 #define PRS_ROUTEPEN_CH8PEN                        (0x1UL << 8)                          /**< CH8 Pin Enable */
7425 #define _PRS_ROUTEPEN_CH8PEN_SHIFT                 8                                     /**< Shift value for PRS_CH8PEN */
7426 #define _PRS_ROUTEPEN_CH8PEN_MASK                  0x100UL                               /**< Bit mask for PRS_CH8PEN */
7427 #define _PRS_ROUTEPEN_CH8PEN_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7428 #define PRS_ROUTEPEN_CH8PEN_DEFAULT                (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7429 #define PRS_ROUTEPEN_CH9PEN                        (0x1UL << 9)                          /**< CH9 Pin Enable */
7430 #define _PRS_ROUTEPEN_CH9PEN_SHIFT                 9                                     /**< Shift value for PRS_CH9PEN */
7431 #define _PRS_ROUTEPEN_CH9PEN_MASK                  0x200UL                               /**< Bit mask for PRS_CH9PEN */
7432 #define _PRS_ROUTEPEN_CH9PEN_DEFAULT               0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7433 #define PRS_ROUTEPEN_CH9PEN_DEFAULT                (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9)   /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7434 #define PRS_ROUTEPEN_CH10PEN                       (0x1UL << 10)                         /**< CH10 Pin Enable */
7435 #define _PRS_ROUTEPEN_CH10PEN_SHIFT                10                                    /**< Shift value for PRS_CH10PEN */
7436 #define _PRS_ROUTEPEN_CH10PEN_MASK                 0x400UL                               /**< Bit mask for PRS_CH10PEN */
7437 #define _PRS_ROUTEPEN_CH10PEN_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7438 #define PRS_ROUTEPEN_CH10PEN_DEFAULT               (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7439 #define PRS_ROUTEPEN_CH11PEN                       (0x1UL << 11)                         /**< CH11 Pin Enable */
7440 #define _PRS_ROUTEPEN_CH11PEN_SHIFT                11                                    /**< Shift value for PRS_CH11PEN */
7441 #define _PRS_ROUTEPEN_CH11PEN_MASK                 0x800UL                               /**< Bit mask for PRS_CH11PEN */
7442 #define _PRS_ROUTEPEN_CH11PEN_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7443 #define PRS_ROUTEPEN_CH11PEN_DEFAULT               (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7444 #define PRS_ROUTEPEN_CH12PEN                       (0x1UL << 12)                         /**< CH12 Pin Enable */
7445 #define _PRS_ROUTEPEN_CH12PEN_SHIFT                12                                    /**< Shift value for PRS_CH12PEN */
7446 #define _PRS_ROUTEPEN_CH12PEN_MASK                 0x1000UL                              /**< Bit mask for PRS_CH12PEN */
7447 #define _PRS_ROUTEPEN_CH12PEN_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7448 #define PRS_ROUTEPEN_CH12PEN_DEFAULT               (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7449 #define PRS_ROUTEPEN_CH13PEN                       (0x1UL << 13)                         /**< CH13 Pin Enable */
7450 #define _PRS_ROUTEPEN_CH13PEN_SHIFT                13                                    /**< Shift value for PRS_CH13PEN */
7451 #define _PRS_ROUTEPEN_CH13PEN_MASK                 0x2000UL                              /**< Bit mask for PRS_CH13PEN */
7452 #define _PRS_ROUTEPEN_CH13PEN_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7453 #define PRS_ROUTEPEN_CH13PEN_DEFAULT               (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7454 #define PRS_ROUTEPEN_CH14PEN                       (0x1UL << 14)                         /**< CH14 Pin Enable */
7455 #define _PRS_ROUTEPEN_CH14PEN_SHIFT                14                                    /**< Shift value for PRS_CH14PEN */
7456 #define _PRS_ROUTEPEN_CH14PEN_MASK                 0x4000UL                              /**< Bit mask for PRS_CH14PEN */
7457 #define _PRS_ROUTEPEN_CH14PEN_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7458 #define PRS_ROUTEPEN_CH14PEN_DEFAULT               (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7459 #define PRS_ROUTEPEN_CH15PEN                       (0x1UL << 15)                         /**< CH15 Pin Enable */
7460 #define _PRS_ROUTEPEN_CH15PEN_SHIFT                15                                    /**< Shift value for PRS_CH15PEN */
7461 #define _PRS_ROUTEPEN_CH15PEN_MASK                 0x8000UL                              /**< Bit mask for PRS_CH15PEN */
7462 #define _PRS_ROUTEPEN_CH15PEN_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTEPEN */
7463 #define PRS_ROUTEPEN_CH15PEN_DEFAULT               (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */
7464 
7465 /* Bit fields for PRS ROUTELOC0 */
7466 #define _PRS_ROUTELOC0_RESETVALUE                  0x00000000UL                          /**< Default value for PRS_ROUTELOC0 */
7467 #define _PRS_ROUTELOC0_MASK                        0x03030303UL                          /**< Mask for PRS_ROUTELOC0 */
7468 #define _PRS_ROUTELOC0_CH0LOC_SHIFT                0                                     /**< Shift value for PRS_CH0LOC */
7469 #define _PRS_ROUTELOC0_CH0LOC_MASK                 0x3UL                                 /**< Bit mask for PRS_CH0LOC */
7470 #define _PRS_ROUTELOC0_CH0LOC_LOC0                 0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC0 */
7471 #define _PRS_ROUTELOC0_CH0LOC_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC0 */
7472 #define _PRS_ROUTELOC0_CH0LOC_LOC1                 0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC0 */
7473 #define _PRS_ROUTELOC0_CH0LOC_LOC2                 0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC0 */
7474 #define _PRS_ROUTELOC0_CH0LOC_LOC3                 0x00000003UL                          /**< Mode LOC3 for PRS_ROUTELOC0 */
7475 #define PRS_ROUTELOC0_CH0LOC_LOC0                  (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0)     /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
7476 #define PRS_ROUTELOC0_CH0LOC_DEFAULT               (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0)  /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
7477 #define PRS_ROUTELOC0_CH0LOC_LOC1                  (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0)     /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
7478 #define PRS_ROUTELOC0_CH0LOC_LOC2                  (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0)     /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
7479 #define PRS_ROUTELOC0_CH0LOC_LOC3                  (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0)     /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
7480 #define _PRS_ROUTELOC0_CH1LOC_SHIFT                8                                     /**< Shift value for PRS_CH1LOC */
7481 #define _PRS_ROUTELOC0_CH1LOC_MASK                 0x300UL                               /**< Bit mask for PRS_CH1LOC */
7482 #define _PRS_ROUTELOC0_CH1LOC_LOC0                 0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC0 */
7483 #define _PRS_ROUTELOC0_CH1LOC_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC0 */
7484 #define _PRS_ROUTELOC0_CH1LOC_LOC1                 0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC0 */
7485 #define _PRS_ROUTELOC0_CH1LOC_LOC2                 0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC0 */
7486 #define _PRS_ROUTELOC0_CH1LOC_LOC3                 0x00000003UL                          /**< Mode LOC3 for PRS_ROUTELOC0 */
7487 #define PRS_ROUTELOC0_CH1LOC_LOC0                  (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8)     /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
7488 #define PRS_ROUTELOC0_CH1LOC_DEFAULT               (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8)  /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
7489 #define PRS_ROUTELOC0_CH1LOC_LOC1                  (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8)     /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
7490 #define PRS_ROUTELOC0_CH1LOC_LOC2                  (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8)     /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
7491 #define PRS_ROUTELOC0_CH1LOC_LOC3                  (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8)     /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
7492 #define _PRS_ROUTELOC0_CH2LOC_SHIFT                16                                    /**< Shift value for PRS_CH2LOC */
7493 #define _PRS_ROUTELOC0_CH2LOC_MASK                 0x30000UL                             /**< Bit mask for PRS_CH2LOC */
7494 #define _PRS_ROUTELOC0_CH2LOC_LOC0                 0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC0 */
7495 #define _PRS_ROUTELOC0_CH2LOC_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC0 */
7496 #define _PRS_ROUTELOC0_CH2LOC_LOC1                 0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC0 */
7497 #define _PRS_ROUTELOC0_CH2LOC_LOC2                 0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC0 */
7498 #define _PRS_ROUTELOC0_CH2LOC_LOC3                 0x00000003UL                          /**< Mode LOC3 for PRS_ROUTELOC0 */
7499 #define PRS_ROUTELOC0_CH2LOC_LOC0                  (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16)    /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
7500 #define PRS_ROUTELOC0_CH2LOC_DEFAULT               (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
7501 #define PRS_ROUTELOC0_CH2LOC_LOC1                  (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16)    /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
7502 #define PRS_ROUTELOC0_CH2LOC_LOC2                  (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16)    /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
7503 #define PRS_ROUTELOC0_CH2LOC_LOC3                  (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16)    /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
7504 #define _PRS_ROUTELOC0_CH3LOC_SHIFT                24                                    /**< Shift value for PRS_CH3LOC */
7505 #define _PRS_ROUTELOC0_CH3LOC_MASK                 0x3000000UL                           /**< Bit mask for PRS_CH3LOC */
7506 #define _PRS_ROUTELOC0_CH3LOC_LOC0                 0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC0 */
7507 #define _PRS_ROUTELOC0_CH3LOC_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC0 */
7508 #define _PRS_ROUTELOC0_CH3LOC_LOC1                 0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC0 */
7509 #define _PRS_ROUTELOC0_CH3LOC_LOC2                 0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC0 */
7510 #define _PRS_ROUTELOC0_CH3LOC_LOC3                 0x00000003UL                          /**< Mode LOC3 for PRS_ROUTELOC0 */
7511 #define PRS_ROUTELOC0_CH3LOC_LOC0                  (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24)    /**< Shifted mode LOC0 for PRS_ROUTELOC0 */
7512 #define PRS_ROUTELOC0_CH3LOC_DEFAULT               (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */
7513 #define PRS_ROUTELOC0_CH3LOC_LOC1                  (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24)    /**< Shifted mode LOC1 for PRS_ROUTELOC0 */
7514 #define PRS_ROUTELOC0_CH3LOC_LOC2                  (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24)    /**< Shifted mode LOC2 for PRS_ROUTELOC0 */
7515 #define PRS_ROUTELOC0_CH3LOC_LOC3                  (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24)    /**< Shifted mode LOC3 for PRS_ROUTELOC0 */
7516 
7517 /* Bit fields for PRS ROUTELOC1 */
7518 #define _PRS_ROUTELOC1_RESETVALUE                  0x00000000UL                          /**< Default value for PRS_ROUTELOC1 */
7519 #define _PRS_ROUTELOC1_MASK                        0x03030303UL                          /**< Mask for PRS_ROUTELOC1 */
7520 #define _PRS_ROUTELOC1_CH4LOC_SHIFT                0                                     /**< Shift value for PRS_CH4LOC */
7521 #define _PRS_ROUTELOC1_CH4LOC_MASK                 0x3UL                                 /**< Bit mask for PRS_CH4LOC */
7522 #define _PRS_ROUTELOC1_CH4LOC_LOC0                 0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC1 */
7523 #define _PRS_ROUTELOC1_CH4LOC_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC1 */
7524 #define _PRS_ROUTELOC1_CH4LOC_LOC1                 0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC1 */
7525 #define _PRS_ROUTELOC1_CH4LOC_LOC2                 0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC1 */
7526 #define PRS_ROUTELOC1_CH4LOC_LOC0                  (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0)     /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
7527 #define PRS_ROUTELOC1_CH4LOC_DEFAULT               (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0)  /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
7528 #define PRS_ROUTELOC1_CH4LOC_LOC1                  (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0)     /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
7529 #define PRS_ROUTELOC1_CH4LOC_LOC2                  (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0)     /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
7530 #define _PRS_ROUTELOC1_CH5LOC_SHIFT                8                                     /**< Shift value for PRS_CH5LOC */
7531 #define _PRS_ROUTELOC1_CH5LOC_MASK                 0x300UL                               /**< Bit mask for PRS_CH5LOC */
7532 #define _PRS_ROUTELOC1_CH5LOC_LOC0                 0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC1 */
7533 #define _PRS_ROUTELOC1_CH5LOC_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC1 */
7534 #define _PRS_ROUTELOC1_CH5LOC_LOC1                 0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC1 */
7535 #define _PRS_ROUTELOC1_CH5LOC_LOC2                 0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC1 */
7536 #define PRS_ROUTELOC1_CH5LOC_LOC0                  (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8)     /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
7537 #define PRS_ROUTELOC1_CH5LOC_DEFAULT               (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8)  /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
7538 #define PRS_ROUTELOC1_CH5LOC_LOC1                  (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8)     /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
7539 #define PRS_ROUTELOC1_CH5LOC_LOC2                  (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8)     /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
7540 #define _PRS_ROUTELOC1_CH6LOC_SHIFT                16                                    /**< Shift value for PRS_CH6LOC */
7541 #define _PRS_ROUTELOC1_CH6LOC_MASK                 0x30000UL                             /**< Bit mask for PRS_CH6LOC */
7542 #define _PRS_ROUTELOC1_CH6LOC_LOC0                 0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC1 */
7543 #define _PRS_ROUTELOC1_CH6LOC_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC1 */
7544 #define _PRS_ROUTELOC1_CH6LOC_LOC1                 0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC1 */
7545 #define _PRS_ROUTELOC1_CH6LOC_LOC2                 0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC1 */
7546 #define PRS_ROUTELOC1_CH6LOC_LOC0                  (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16)    /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
7547 #define PRS_ROUTELOC1_CH6LOC_DEFAULT               (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
7548 #define PRS_ROUTELOC1_CH6LOC_LOC1                  (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16)    /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
7549 #define PRS_ROUTELOC1_CH6LOC_LOC2                  (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16)    /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
7550 #define _PRS_ROUTELOC1_CH7LOC_SHIFT                24                                    /**< Shift value for PRS_CH7LOC */
7551 #define _PRS_ROUTELOC1_CH7LOC_MASK                 0x3000000UL                           /**< Bit mask for PRS_CH7LOC */
7552 #define _PRS_ROUTELOC1_CH7LOC_LOC0                 0x00000000UL                          /**< Mode LOC0 for PRS_ROUTELOC1 */
7553 #define _PRS_ROUTELOC1_CH7LOC_DEFAULT              0x00000000UL                          /**< Mode DEFAULT for PRS_ROUTELOC1 */
7554 #define _PRS_ROUTELOC1_CH7LOC_LOC1                 0x00000001UL                          /**< Mode LOC1 for PRS_ROUTELOC1 */
7555 #define _PRS_ROUTELOC1_CH7LOC_LOC2                 0x00000002UL                          /**< Mode LOC2 for PRS_ROUTELOC1 */
7556 #define PRS_ROUTELOC1_CH7LOC_LOC0                  (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24)    /**< Shifted mode LOC0 for PRS_ROUTELOC1 */
7557 #define PRS_ROUTELOC1_CH7LOC_DEFAULT               (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */
7558 #define PRS_ROUTELOC1_CH7LOC_LOC1                  (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24)    /**< Shifted mode LOC1 for PRS_ROUTELOC1 */
7559 #define PRS_ROUTELOC1_CH7LOC_LOC2                  (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24)    /**< Shifted mode LOC2 for PRS_ROUTELOC1 */
7560 
7561 /* Bit fields for PRS ROUTELOC2 */
7562 #define _PRS_ROUTELOC2_RESETVALUE                  0x00000000UL                           /**< Default value for PRS_ROUTELOC2 */
7563 #define _PRS_ROUTELOC2_MASK                        0x03030303UL                           /**< Mask for PRS_ROUTELOC2 */
7564 #define _PRS_ROUTELOC2_CH8LOC_SHIFT                0                                      /**< Shift value for PRS_CH8LOC */
7565 #define _PRS_ROUTELOC2_CH8LOC_MASK                 0x3UL                                  /**< Bit mask for PRS_CH8LOC */
7566 #define _PRS_ROUTELOC2_CH8LOC_LOC0                 0x00000000UL                           /**< Mode LOC0 for PRS_ROUTELOC2 */
7567 #define _PRS_ROUTELOC2_CH8LOC_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_ROUTELOC2 */
7568 #define _PRS_ROUTELOC2_CH8LOC_LOC1                 0x00000001UL                           /**< Mode LOC1 for PRS_ROUTELOC2 */
7569 #define _PRS_ROUTELOC2_CH8LOC_LOC2                 0x00000002UL                           /**< Mode LOC2 for PRS_ROUTELOC2 */
7570 #define PRS_ROUTELOC2_CH8LOC_LOC0                  (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0)      /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
7571 #define PRS_ROUTELOC2_CH8LOC_DEFAULT               (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0)   /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
7572 #define PRS_ROUTELOC2_CH8LOC_LOC1                  (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0)      /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
7573 #define PRS_ROUTELOC2_CH8LOC_LOC2                  (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0)      /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
7574 #define _PRS_ROUTELOC2_CH9LOC_SHIFT                8                                      /**< Shift value for PRS_CH9LOC */
7575 #define _PRS_ROUTELOC2_CH9LOC_MASK                 0x300UL                                /**< Bit mask for PRS_CH9LOC */
7576 #define _PRS_ROUTELOC2_CH9LOC_LOC0                 0x00000000UL                           /**< Mode LOC0 for PRS_ROUTELOC2 */
7577 #define _PRS_ROUTELOC2_CH9LOC_DEFAULT              0x00000000UL                           /**< Mode DEFAULT for PRS_ROUTELOC2 */
7578 #define _PRS_ROUTELOC2_CH9LOC_LOC1                 0x00000001UL                           /**< Mode LOC1 for PRS_ROUTELOC2 */
7579 #define _PRS_ROUTELOC2_CH9LOC_LOC2                 0x00000002UL                           /**< Mode LOC2 for PRS_ROUTELOC2 */
7580 #define PRS_ROUTELOC2_CH9LOC_LOC0                  (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8)      /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
7581 #define PRS_ROUTELOC2_CH9LOC_DEFAULT               (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8)   /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
7582 #define PRS_ROUTELOC2_CH9LOC_LOC1                  (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8)      /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
7583 #define PRS_ROUTELOC2_CH9LOC_LOC2                  (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8)      /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
7584 #define _PRS_ROUTELOC2_CH10LOC_SHIFT               16                                     /**< Shift value for PRS_CH10LOC */
7585 #define _PRS_ROUTELOC2_CH10LOC_MASK                0x30000UL                              /**< Bit mask for PRS_CH10LOC */
7586 #define _PRS_ROUTELOC2_CH10LOC_LOC0                0x00000000UL                           /**< Mode LOC0 for PRS_ROUTELOC2 */
7587 #define _PRS_ROUTELOC2_CH10LOC_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_ROUTELOC2 */
7588 #define _PRS_ROUTELOC2_CH10LOC_LOC1                0x00000001UL                           /**< Mode LOC1 for PRS_ROUTELOC2 */
7589 #define _PRS_ROUTELOC2_CH10LOC_LOC2                0x00000002UL                           /**< Mode LOC2 for PRS_ROUTELOC2 */
7590 #define PRS_ROUTELOC2_CH10LOC_LOC0                 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16)    /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
7591 #define PRS_ROUTELOC2_CH10LOC_DEFAULT              (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
7592 #define PRS_ROUTELOC2_CH10LOC_LOC1                 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16)    /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
7593 #define PRS_ROUTELOC2_CH10LOC_LOC2                 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16)    /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
7594 #define _PRS_ROUTELOC2_CH11LOC_SHIFT               24                                     /**< Shift value for PRS_CH11LOC */
7595 #define _PRS_ROUTELOC2_CH11LOC_MASK                0x3000000UL                            /**< Bit mask for PRS_CH11LOC */
7596 #define _PRS_ROUTELOC2_CH11LOC_LOC0                0x00000000UL                           /**< Mode LOC0 for PRS_ROUTELOC2 */
7597 #define _PRS_ROUTELOC2_CH11LOC_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_ROUTELOC2 */
7598 #define _PRS_ROUTELOC2_CH11LOC_LOC1                0x00000001UL                           /**< Mode LOC1 for PRS_ROUTELOC2 */
7599 #define _PRS_ROUTELOC2_CH11LOC_LOC2                0x00000002UL                           /**< Mode LOC2 for PRS_ROUTELOC2 */
7600 #define PRS_ROUTELOC2_CH11LOC_LOC0                 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24)    /**< Shifted mode LOC0 for PRS_ROUTELOC2 */
7601 #define PRS_ROUTELOC2_CH11LOC_DEFAULT              (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */
7602 #define PRS_ROUTELOC2_CH11LOC_LOC1                 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24)    /**< Shifted mode LOC1 for PRS_ROUTELOC2 */
7603 #define PRS_ROUTELOC2_CH11LOC_LOC2                 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24)    /**< Shifted mode LOC2 for PRS_ROUTELOC2 */
7604 
7605 /* Bit fields for PRS ROUTELOC3 */
7606 #define _PRS_ROUTELOC3_RESETVALUE                  0x00000000UL                           /**< Default value for PRS_ROUTELOC3 */
7607 #define _PRS_ROUTELOC3_MASK                        0x03030303UL                           /**< Mask for PRS_ROUTELOC3 */
7608 #define _PRS_ROUTELOC3_CH12LOC_SHIFT               0                                      /**< Shift value for PRS_CH12LOC */
7609 #define _PRS_ROUTELOC3_CH12LOC_MASK                0x3UL                                  /**< Bit mask for PRS_CH12LOC */
7610 #define _PRS_ROUTELOC3_CH12LOC_LOC0                0x00000000UL                           /**< Mode LOC0 for PRS_ROUTELOC3 */
7611 #define _PRS_ROUTELOC3_CH12LOC_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_ROUTELOC3 */
7612 #define _PRS_ROUTELOC3_CH12LOC_LOC1                0x00000001UL                           /**< Mode LOC1 for PRS_ROUTELOC3 */
7613 #define _PRS_ROUTELOC3_CH12LOC_LOC2                0x00000002UL                           /**< Mode LOC2 for PRS_ROUTELOC3 */
7614 #define PRS_ROUTELOC3_CH12LOC_LOC0                 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0)     /**< Shifted mode LOC0 for PRS_ROUTELOC3 */
7615 #define PRS_ROUTELOC3_CH12LOC_DEFAULT              (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0)  /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */
7616 #define PRS_ROUTELOC3_CH12LOC_LOC1                 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0)     /**< Shifted mode LOC1 for PRS_ROUTELOC3 */
7617 #define PRS_ROUTELOC3_CH12LOC_LOC2                 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0)     /**< Shifted mode LOC2 for PRS_ROUTELOC3 */
7618 #define _PRS_ROUTELOC3_CH13LOC_SHIFT               8                                      /**< Shift value for PRS_CH13LOC */
7619 #define _PRS_ROUTELOC3_CH13LOC_MASK                0x300UL                                /**< Bit mask for PRS_CH13LOC */
7620 #define _PRS_ROUTELOC3_CH13LOC_LOC0                0x00000000UL                           /**< Mode LOC0 for PRS_ROUTELOC3 */
7621 #define _PRS_ROUTELOC3_CH13LOC_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_ROUTELOC3 */
7622 #define _PRS_ROUTELOC3_CH13LOC_LOC1                0x00000001UL                           /**< Mode LOC1 for PRS_ROUTELOC3 */
7623 #define _PRS_ROUTELOC3_CH13LOC_LOC2                0x00000002UL                           /**< Mode LOC2 for PRS_ROUTELOC3 */
7624 #define PRS_ROUTELOC3_CH13LOC_LOC0                 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8)     /**< Shifted mode LOC0 for PRS_ROUTELOC3 */
7625 #define PRS_ROUTELOC3_CH13LOC_DEFAULT              (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8)  /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */
7626 #define PRS_ROUTELOC3_CH13LOC_LOC1                 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8)     /**< Shifted mode LOC1 for PRS_ROUTELOC3 */
7627 #define PRS_ROUTELOC3_CH13LOC_LOC2                 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8)     /**< Shifted mode LOC2 for PRS_ROUTELOC3 */
7628 #define _PRS_ROUTELOC3_CH14LOC_SHIFT               16                                     /**< Shift value for PRS_CH14LOC */
7629 #define _PRS_ROUTELOC3_CH14LOC_MASK                0x30000UL                              /**< Bit mask for PRS_CH14LOC */
7630 #define _PRS_ROUTELOC3_CH14LOC_LOC0                0x00000000UL                           /**< Mode LOC0 for PRS_ROUTELOC3 */
7631 #define _PRS_ROUTELOC3_CH14LOC_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_ROUTELOC3 */
7632 #define _PRS_ROUTELOC3_CH14LOC_LOC1                0x00000001UL                           /**< Mode LOC1 for PRS_ROUTELOC3 */
7633 #define _PRS_ROUTELOC3_CH14LOC_LOC2                0x00000002UL                           /**< Mode LOC2 for PRS_ROUTELOC3 */
7634 #define PRS_ROUTELOC3_CH14LOC_LOC0                 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16)    /**< Shifted mode LOC0 for PRS_ROUTELOC3 */
7635 #define PRS_ROUTELOC3_CH14LOC_DEFAULT              (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */
7636 #define PRS_ROUTELOC3_CH14LOC_LOC1                 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16)    /**< Shifted mode LOC1 for PRS_ROUTELOC3 */
7637 #define PRS_ROUTELOC3_CH14LOC_LOC2                 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16)    /**< Shifted mode LOC2 for PRS_ROUTELOC3 */
7638 #define _PRS_ROUTELOC3_CH15LOC_SHIFT               24                                     /**< Shift value for PRS_CH15LOC */
7639 #define _PRS_ROUTELOC3_CH15LOC_MASK                0x3000000UL                            /**< Bit mask for PRS_CH15LOC */
7640 #define _PRS_ROUTELOC3_CH15LOC_LOC0                0x00000000UL                           /**< Mode LOC0 for PRS_ROUTELOC3 */
7641 #define _PRS_ROUTELOC3_CH15LOC_DEFAULT             0x00000000UL                           /**< Mode DEFAULT for PRS_ROUTELOC3 */
7642 #define _PRS_ROUTELOC3_CH15LOC_LOC1                0x00000001UL                           /**< Mode LOC1 for PRS_ROUTELOC3 */
7643 #define _PRS_ROUTELOC3_CH15LOC_LOC2                0x00000002UL                           /**< Mode LOC2 for PRS_ROUTELOC3 */
7644 #define PRS_ROUTELOC3_CH15LOC_LOC0                 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24)    /**< Shifted mode LOC0 for PRS_ROUTELOC3 */
7645 #define PRS_ROUTELOC3_CH15LOC_DEFAULT              (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */
7646 #define PRS_ROUTELOC3_CH15LOC_LOC1                 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24)    /**< Shifted mode LOC1 for PRS_ROUTELOC3 */
7647 #define PRS_ROUTELOC3_CH15LOC_LOC2                 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24)    /**< Shifted mode LOC2 for PRS_ROUTELOC3 */
7648 
7649 /* Bit fields for PRS CTRL */
7650 #define _PRS_CTRL_RESETVALUE                       0x00000000UL                         /**< Default value for PRS_CTRL */
7651 #define _PRS_CTRL_MASK                             0x0000001FUL                         /**< Mask for PRS_CTRL */
7652 #define PRS_CTRL_SEVONPRS                          (0x1UL << 0)                         /**< Set Event on PRS */
7653 #define _PRS_CTRL_SEVONPRS_SHIFT                   0                                    /**< Shift value for PRS_SEVONPRS */
7654 #define _PRS_CTRL_SEVONPRS_MASK                    0x1UL                                /**< Bit mask for PRS_SEVONPRS */
7655 #define _PRS_CTRL_SEVONPRS_DEFAULT                 0x00000000UL                         /**< Mode DEFAULT for PRS_CTRL */
7656 #define PRS_CTRL_SEVONPRS_DEFAULT                  (_PRS_CTRL_SEVONPRS_DEFAULT << 0)    /**< Shifted mode DEFAULT for PRS_CTRL */
7657 #define _PRS_CTRL_SEVONPRSSEL_SHIFT                1                                    /**< Shift value for PRS_SEVONPRSSEL */
7658 #define _PRS_CTRL_SEVONPRSSEL_MASK                 0x1EUL                               /**< Bit mask for PRS_SEVONPRSSEL */
7659 #define _PRS_CTRL_SEVONPRSSEL_DEFAULT              0x00000000UL                         /**< Mode DEFAULT for PRS_CTRL */
7660 #define _PRS_CTRL_SEVONPRSSEL_PRSCH0               0x00000000UL                         /**< Mode PRSCH0 for PRS_CTRL */
7661 #define _PRS_CTRL_SEVONPRSSEL_PRSCH1               0x00000001UL                         /**< Mode PRSCH1 for PRS_CTRL */
7662 #define _PRS_CTRL_SEVONPRSSEL_PRSCH2               0x00000002UL                         /**< Mode PRSCH2 for PRS_CTRL */
7663 #define _PRS_CTRL_SEVONPRSSEL_PRSCH3               0x00000003UL                         /**< Mode PRSCH3 for PRS_CTRL */
7664 #define _PRS_CTRL_SEVONPRSSEL_PRSCH4               0x00000004UL                         /**< Mode PRSCH4 for PRS_CTRL */
7665 #define _PRS_CTRL_SEVONPRSSEL_PRSCH5               0x00000005UL                         /**< Mode PRSCH5 for PRS_CTRL */
7666 #define _PRS_CTRL_SEVONPRSSEL_PRSCH6               0x00000006UL                         /**< Mode PRSCH6 for PRS_CTRL */
7667 #define _PRS_CTRL_SEVONPRSSEL_PRSCH7               0x00000007UL                         /**< Mode PRSCH7 for PRS_CTRL */
7668 #define _PRS_CTRL_SEVONPRSSEL_PRSCH8               0x00000008UL                         /**< Mode PRSCH8 for PRS_CTRL */
7669 #define _PRS_CTRL_SEVONPRSSEL_PRSCH9               0x00000009UL                         /**< Mode PRSCH9 for PRS_CTRL */
7670 #define _PRS_CTRL_SEVONPRSSEL_PRSCH10              0x0000000AUL                         /**< Mode PRSCH10 for PRS_CTRL */
7671 #define _PRS_CTRL_SEVONPRSSEL_PRSCH11              0x0000000BUL                         /**< Mode PRSCH11 for PRS_CTRL */
7672 #define _PRS_CTRL_SEVONPRSSEL_PRSCH12              0x0000000CUL                         /**< Mode PRSCH12 for PRS_CTRL */
7673 #define _PRS_CTRL_SEVONPRSSEL_PRSCH13              0x0000000DUL                         /**< Mode PRSCH13 for PRS_CTRL */
7674 #define _PRS_CTRL_SEVONPRSSEL_PRSCH14              0x0000000EUL                         /**< Mode PRSCH14 for PRS_CTRL */
7675 #define _PRS_CTRL_SEVONPRSSEL_PRSCH15              0x0000000FUL                         /**< Mode PRSCH15 for PRS_CTRL */
7676 #define PRS_CTRL_SEVONPRSSEL_DEFAULT               (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */
7677 #define PRS_CTRL_SEVONPRSSEL_PRSCH0                (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1)  /**< Shifted mode PRSCH0 for PRS_CTRL */
7678 #define PRS_CTRL_SEVONPRSSEL_PRSCH1                (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1)  /**< Shifted mode PRSCH1 for PRS_CTRL */
7679 #define PRS_CTRL_SEVONPRSSEL_PRSCH2                (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1)  /**< Shifted mode PRSCH2 for PRS_CTRL */
7680 #define PRS_CTRL_SEVONPRSSEL_PRSCH3                (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1)  /**< Shifted mode PRSCH3 for PRS_CTRL */
7681 #define PRS_CTRL_SEVONPRSSEL_PRSCH4                (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1)  /**< Shifted mode PRSCH4 for PRS_CTRL */
7682 #define PRS_CTRL_SEVONPRSSEL_PRSCH5                (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1)  /**< Shifted mode PRSCH5 for PRS_CTRL */
7683 #define PRS_CTRL_SEVONPRSSEL_PRSCH6                (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1)  /**< Shifted mode PRSCH6 for PRS_CTRL */
7684 #define PRS_CTRL_SEVONPRSSEL_PRSCH7                (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1)  /**< Shifted mode PRSCH7 for PRS_CTRL */
7685 #define PRS_CTRL_SEVONPRSSEL_PRSCH8                (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1)  /**< Shifted mode PRSCH8 for PRS_CTRL */
7686 #define PRS_CTRL_SEVONPRSSEL_PRSCH9                (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1)  /**< Shifted mode PRSCH9 for PRS_CTRL */
7687 #define PRS_CTRL_SEVONPRSSEL_PRSCH10               (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */
7688 #define PRS_CTRL_SEVONPRSSEL_PRSCH11               (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */
7689 #define PRS_CTRL_SEVONPRSSEL_PRSCH12               (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */
7690 #define PRS_CTRL_SEVONPRSSEL_PRSCH13               (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */
7691 #define PRS_CTRL_SEVONPRSSEL_PRSCH14               (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */
7692 #define PRS_CTRL_SEVONPRSSEL_PRSCH15               (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */
7693 
7694 /* Bit fields for PRS DMAREQ0 */
7695 #define _PRS_DMAREQ0_RESETVALUE                    0x00000000UL                       /**< Default value for PRS_DMAREQ0 */
7696 #define _PRS_DMAREQ0_MASK                          0x000003C0UL                       /**< Mask for PRS_DMAREQ0 */
7697 #define _PRS_DMAREQ0_PRSSEL_SHIFT                  6                                  /**< Shift value for PRS_PRSSEL */
7698 #define _PRS_DMAREQ0_PRSSEL_MASK                   0x3C0UL                            /**< Bit mask for PRS_PRSSEL */
7699 #define _PRS_DMAREQ0_PRSSEL_DEFAULT                0x00000000UL                       /**< Mode DEFAULT for PRS_DMAREQ0 */
7700 #define _PRS_DMAREQ0_PRSSEL_PRSCH0                 0x00000000UL                       /**< Mode PRSCH0 for PRS_DMAREQ0 */
7701 #define _PRS_DMAREQ0_PRSSEL_PRSCH1                 0x00000001UL                       /**< Mode PRSCH1 for PRS_DMAREQ0 */
7702 #define _PRS_DMAREQ0_PRSSEL_PRSCH2                 0x00000002UL                       /**< Mode PRSCH2 for PRS_DMAREQ0 */
7703 #define _PRS_DMAREQ0_PRSSEL_PRSCH3                 0x00000003UL                       /**< Mode PRSCH3 for PRS_DMAREQ0 */
7704 #define _PRS_DMAREQ0_PRSSEL_PRSCH4                 0x00000004UL                       /**< Mode PRSCH4 for PRS_DMAREQ0 */
7705 #define _PRS_DMAREQ0_PRSSEL_PRSCH5                 0x00000005UL                       /**< Mode PRSCH5 for PRS_DMAREQ0 */
7706 #define _PRS_DMAREQ0_PRSSEL_PRSCH6                 0x00000006UL                       /**< Mode PRSCH6 for PRS_DMAREQ0 */
7707 #define _PRS_DMAREQ0_PRSSEL_PRSCH7                 0x00000007UL                       /**< Mode PRSCH7 for PRS_DMAREQ0 */
7708 #define _PRS_DMAREQ0_PRSSEL_PRSCH8                 0x00000008UL                       /**< Mode PRSCH8 for PRS_DMAREQ0 */
7709 #define _PRS_DMAREQ0_PRSSEL_PRSCH9                 0x00000009UL                       /**< Mode PRSCH9 for PRS_DMAREQ0 */
7710 #define _PRS_DMAREQ0_PRSSEL_PRSCH10                0x0000000AUL                       /**< Mode PRSCH10 for PRS_DMAREQ0 */
7711 #define _PRS_DMAREQ0_PRSSEL_PRSCH11                0x0000000BUL                       /**< Mode PRSCH11 for PRS_DMAREQ0 */
7712 #define _PRS_DMAREQ0_PRSSEL_PRSCH12                0x0000000CUL                       /**< Mode PRSCH12 for PRS_DMAREQ0 */
7713 #define _PRS_DMAREQ0_PRSSEL_PRSCH13                0x0000000DUL                       /**< Mode PRSCH13 for PRS_DMAREQ0 */
7714 #define _PRS_DMAREQ0_PRSSEL_PRSCH14                0x0000000EUL                       /**< Mode PRSCH14 for PRS_DMAREQ0 */
7715 #define _PRS_DMAREQ0_PRSSEL_PRSCH15                0x0000000FUL                       /**< Mode PRSCH15 for PRS_DMAREQ0 */
7716 #define PRS_DMAREQ0_PRSSEL_DEFAULT                 (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */
7717 #define PRS_DMAREQ0_PRSSEL_PRSCH0                  (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6)  /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */
7718 #define PRS_DMAREQ0_PRSSEL_PRSCH1                  (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6)  /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */
7719 #define PRS_DMAREQ0_PRSSEL_PRSCH2                  (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6)  /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */
7720 #define PRS_DMAREQ0_PRSSEL_PRSCH3                  (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6)  /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */
7721 #define PRS_DMAREQ0_PRSSEL_PRSCH4                  (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6)  /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */
7722 #define PRS_DMAREQ0_PRSSEL_PRSCH5                  (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6)  /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */
7723 #define PRS_DMAREQ0_PRSSEL_PRSCH6                  (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6)  /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */
7724 #define PRS_DMAREQ0_PRSSEL_PRSCH7                  (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6)  /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */
7725 #define PRS_DMAREQ0_PRSSEL_PRSCH8                  (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6)  /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */
7726 #define PRS_DMAREQ0_PRSSEL_PRSCH9                  (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6)  /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */
7727 #define PRS_DMAREQ0_PRSSEL_PRSCH10                 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */
7728 #define PRS_DMAREQ0_PRSSEL_PRSCH11                 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */
7729 #define PRS_DMAREQ0_PRSSEL_PRSCH12                 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */
7730 #define PRS_DMAREQ0_PRSSEL_PRSCH13                 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */
7731 #define PRS_DMAREQ0_PRSSEL_PRSCH14                 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */
7732 #define PRS_DMAREQ0_PRSSEL_PRSCH15                 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */
7733 
7734 /* Bit fields for PRS DMAREQ1 */
7735 #define _PRS_DMAREQ1_RESETVALUE                    0x00000000UL                       /**< Default value for PRS_DMAREQ1 */
7736 #define _PRS_DMAREQ1_MASK                          0x000003C0UL                       /**< Mask for PRS_DMAREQ1 */
7737 #define _PRS_DMAREQ1_PRSSEL_SHIFT                  6                                  /**< Shift value for PRS_PRSSEL */
7738 #define _PRS_DMAREQ1_PRSSEL_MASK                   0x3C0UL                            /**< Bit mask for PRS_PRSSEL */
7739 #define _PRS_DMAREQ1_PRSSEL_DEFAULT                0x00000000UL                       /**< Mode DEFAULT for PRS_DMAREQ1 */
7740 #define _PRS_DMAREQ1_PRSSEL_PRSCH0                 0x00000000UL                       /**< Mode PRSCH0 for PRS_DMAREQ1 */
7741 #define _PRS_DMAREQ1_PRSSEL_PRSCH1                 0x00000001UL                       /**< Mode PRSCH1 for PRS_DMAREQ1 */
7742 #define _PRS_DMAREQ1_PRSSEL_PRSCH2                 0x00000002UL                       /**< Mode PRSCH2 for PRS_DMAREQ1 */
7743 #define _PRS_DMAREQ1_PRSSEL_PRSCH3                 0x00000003UL                       /**< Mode PRSCH3 for PRS_DMAREQ1 */
7744 #define _PRS_DMAREQ1_PRSSEL_PRSCH4                 0x00000004UL                       /**< Mode PRSCH4 for PRS_DMAREQ1 */
7745 #define _PRS_DMAREQ1_PRSSEL_PRSCH5                 0x00000005UL                       /**< Mode PRSCH5 for PRS_DMAREQ1 */
7746 #define _PRS_DMAREQ1_PRSSEL_PRSCH6                 0x00000006UL                       /**< Mode PRSCH6 for PRS_DMAREQ1 */
7747 #define _PRS_DMAREQ1_PRSSEL_PRSCH7                 0x00000007UL                       /**< Mode PRSCH7 for PRS_DMAREQ1 */
7748 #define _PRS_DMAREQ1_PRSSEL_PRSCH8                 0x00000008UL                       /**< Mode PRSCH8 for PRS_DMAREQ1 */
7749 #define _PRS_DMAREQ1_PRSSEL_PRSCH9                 0x00000009UL                       /**< Mode PRSCH9 for PRS_DMAREQ1 */
7750 #define _PRS_DMAREQ1_PRSSEL_PRSCH10                0x0000000AUL                       /**< Mode PRSCH10 for PRS_DMAREQ1 */
7751 #define _PRS_DMAREQ1_PRSSEL_PRSCH11                0x0000000BUL                       /**< Mode PRSCH11 for PRS_DMAREQ1 */
7752 #define _PRS_DMAREQ1_PRSSEL_PRSCH12                0x0000000CUL                       /**< Mode PRSCH12 for PRS_DMAREQ1 */
7753 #define _PRS_DMAREQ1_PRSSEL_PRSCH13                0x0000000DUL                       /**< Mode PRSCH13 for PRS_DMAREQ1 */
7754 #define _PRS_DMAREQ1_PRSSEL_PRSCH14                0x0000000EUL                       /**< Mode PRSCH14 for PRS_DMAREQ1 */
7755 #define _PRS_DMAREQ1_PRSSEL_PRSCH15                0x0000000FUL                       /**< Mode PRSCH15 for PRS_DMAREQ1 */
7756 #define PRS_DMAREQ1_PRSSEL_DEFAULT                 (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */
7757 #define PRS_DMAREQ1_PRSSEL_PRSCH0                  (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6)  /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */
7758 #define PRS_DMAREQ1_PRSSEL_PRSCH1                  (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6)  /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */
7759 #define PRS_DMAREQ1_PRSSEL_PRSCH2                  (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6)  /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */
7760 #define PRS_DMAREQ1_PRSSEL_PRSCH3                  (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6)  /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */
7761 #define PRS_DMAREQ1_PRSSEL_PRSCH4                  (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6)  /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */
7762 #define PRS_DMAREQ1_PRSSEL_PRSCH5                  (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6)  /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */
7763 #define PRS_DMAREQ1_PRSSEL_PRSCH6                  (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6)  /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */
7764 #define PRS_DMAREQ1_PRSSEL_PRSCH7                  (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6)  /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */
7765 #define PRS_DMAREQ1_PRSSEL_PRSCH8                  (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6)  /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */
7766 #define PRS_DMAREQ1_PRSSEL_PRSCH9                  (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6)  /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */
7767 #define PRS_DMAREQ1_PRSSEL_PRSCH10                 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */
7768 #define PRS_DMAREQ1_PRSSEL_PRSCH11                 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */
7769 #define PRS_DMAREQ1_PRSSEL_PRSCH12                 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */
7770 #define PRS_DMAREQ1_PRSSEL_PRSCH13                 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */
7771 #define PRS_DMAREQ1_PRSSEL_PRSCH14                 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */
7772 #define PRS_DMAREQ1_PRSSEL_PRSCH15                 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */
7773 
7774 /* Bit fields for PRS PEEK */
7775 #define _PRS_PEEK_RESETVALUE                       0x00000000UL                      /**< Default value for PRS_PEEK */
7776 #define _PRS_PEEK_MASK                             0x0000FFFFUL                      /**< Mask for PRS_PEEK */
7777 #define PRS_PEEK_CH0VAL                            (0x1UL << 0)                      /**< Channel 0 Current Value */
7778 #define _PRS_PEEK_CH0VAL_SHIFT                     0                                 /**< Shift value for PRS_CH0VAL */
7779 #define _PRS_PEEK_CH0VAL_MASK                      0x1UL                             /**< Bit mask for PRS_CH0VAL */
7780 #define _PRS_PEEK_CH0VAL_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7781 #define PRS_PEEK_CH0VAL_DEFAULT                    (_PRS_PEEK_CH0VAL_DEFAULT << 0)   /**< Shifted mode DEFAULT for PRS_PEEK */
7782 #define PRS_PEEK_CH1VAL                            (0x1UL << 1)                      /**< Channel 1 Current Value */
7783 #define _PRS_PEEK_CH1VAL_SHIFT                     1                                 /**< Shift value for PRS_CH1VAL */
7784 #define _PRS_PEEK_CH1VAL_MASK                      0x2UL                             /**< Bit mask for PRS_CH1VAL */
7785 #define _PRS_PEEK_CH1VAL_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7786 #define PRS_PEEK_CH1VAL_DEFAULT                    (_PRS_PEEK_CH1VAL_DEFAULT << 1)   /**< Shifted mode DEFAULT for PRS_PEEK */
7787 #define PRS_PEEK_CH2VAL                            (0x1UL << 2)                      /**< Channel 2 Current Value */
7788 #define _PRS_PEEK_CH2VAL_SHIFT                     2                                 /**< Shift value for PRS_CH2VAL */
7789 #define _PRS_PEEK_CH2VAL_MASK                      0x4UL                             /**< Bit mask for PRS_CH2VAL */
7790 #define _PRS_PEEK_CH2VAL_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7791 #define PRS_PEEK_CH2VAL_DEFAULT                    (_PRS_PEEK_CH2VAL_DEFAULT << 2)   /**< Shifted mode DEFAULT for PRS_PEEK */
7792 #define PRS_PEEK_CH3VAL                            (0x1UL << 3)                      /**< Channel 3 Current Value */
7793 #define _PRS_PEEK_CH3VAL_SHIFT                     3                                 /**< Shift value for PRS_CH3VAL */
7794 #define _PRS_PEEK_CH3VAL_MASK                      0x8UL                             /**< Bit mask for PRS_CH3VAL */
7795 #define _PRS_PEEK_CH3VAL_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7796 #define PRS_PEEK_CH3VAL_DEFAULT                    (_PRS_PEEK_CH3VAL_DEFAULT << 3)   /**< Shifted mode DEFAULT for PRS_PEEK */
7797 #define PRS_PEEK_CH4VAL                            (0x1UL << 4)                      /**< Channel 4 Current Value */
7798 #define _PRS_PEEK_CH4VAL_SHIFT                     4                                 /**< Shift value for PRS_CH4VAL */
7799 #define _PRS_PEEK_CH4VAL_MASK                      0x10UL                            /**< Bit mask for PRS_CH4VAL */
7800 #define _PRS_PEEK_CH4VAL_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7801 #define PRS_PEEK_CH4VAL_DEFAULT                    (_PRS_PEEK_CH4VAL_DEFAULT << 4)   /**< Shifted mode DEFAULT for PRS_PEEK */
7802 #define PRS_PEEK_CH5VAL                            (0x1UL << 5)                      /**< Channel 5 Current Value */
7803 #define _PRS_PEEK_CH5VAL_SHIFT                     5                                 /**< Shift value for PRS_CH5VAL */
7804 #define _PRS_PEEK_CH5VAL_MASK                      0x20UL                            /**< Bit mask for PRS_CH5VAL */
7805 #define _PRS_PEEK_CH5VAL_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7806 #define PRS_PEEK_CH5VAL_DEFAULT                    (_PRS_PEEK_CH5VAL_DEFAULT << 5)   /**< Shifted mode DEFAULT for PRS_PEEK */
7807 #define PRS_PEEK_CH6VAL                            (0x1UL << 6)                      /**< Channel 6 Current Value */
7808 #define _PRS_PEEK_CH6VAL_SHIFT                     6                                 /**< Shift value for PRS_CH6VAL */
7809 #define _PRS_PEEK_CH6VAL_MASK                      0x40UL                            /**< Bit mask for PRS_CH6VAL */
7810 #define _PRS_PEEK_CH6VAL_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7811 #define PRS_PEEK_CH6VAL_DEFAULT                    (_PRS_PEEK_CH6VAL_DEFAULT << 6)   /**< Shifted mode DEFAULT for PRS_PEEK */
7812 #define PRS_PEEK_CH7VAL                            (0x1UL << 7)                      /**< Channel 7 Current Value */
7813 #define _PRS_PEEK_CH7VAL_SHIFT                     7                                 /**< Shift value for PRS_CH7VAL */
7814 #define _PRS_PEEK_CH7VAL_MASK                      0x80UL                            /**< Bit mask for PRS_CH7VAL */
7815 #define _PRS_PEEK_CH7VAL_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7816 #define PRS_PEEK_CH7VAL_DEFAULT                    (_PRS_PEEK_CH7VAL_DEFAULT << 7)   /**< Shifted mode DEFAULT for PRS_PEEK */
7817 #define PRS_PEEK_CH8VAL                            (0x1UL << 8)                      /**< Channel 8 Current Value */
7818 #define _PRS_PEEK_CH8VAL_SHIFT                     8                                 /**< Shift value for PRS_CH8VAL */
7819 #define _PRS_PEEK_CH8VAL_MASK                      0x100UL                           /**< Bit mask for PRS_CH8VAL */
7820 #define _PRS_PEEK_CH8VAL_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7821 #define PRS_PEEK_CH8VAL_DEFAULT                    (_PRS_PEEK_CH8VAL_DEFAULT << 8)   /**< Shifted mode DEFAULT for PRS_PEEK */
7822 #define PRS_PEEK_CH9VAL                            (0x1UL << 9)                      /**< Channel 9 Current Value */
7823 #define _PRS_PEEK_CH9VAL_SHIFT                     9                                 /**< Shift value for PRS_CH9VAL */
7824 #define _PRS_PEEK_CH9VAL_MASK                      0x200UL                           /**< Bit mask for PRS_CH9VAL */
7825 #define _PRS_PEEK_CH9VAL_DEFAULT                   0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7826 #define PRS_PEEK_CH9VAL_DEFAULT                    (_PRS_PEEK_CH9VAL_DEFAULT << 9)   /**< Shifted mode DEFAULT for PRS_PEEK */
7827 #define PRS_PEEK_CH10VAL                           (0x1UL << 10)                     /**< Channel 10 Current Value */
7828 #define _PRS_PEEK_CH10VAL_SHIFT                    10                                /**< Shift value for PRS_CH10VAL */
7829 #define _PRS_PEEK_CH10VAL_MASK                     0x400UL                           /**< Bit mask for PRS_CH10VAL */
7830 #define _PRS_PEEK_CH10VAL_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7831 #define PRS_PEEK_CH10VAL_DEFAULT                   (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */
7832 #define PRS_PEEK_CH11VAL                           (0x1UL << 11)                     /**< Channel 11 Current Value */
7833 #define _PRS_PEEK_CH11VAL_SHIFT                    11                                /**< Shift value for PRS_CH11VAL */
7834 #define _PRS_PEEK_CH11VAL_MASK                     0x800UL                           /**< Bit mask for PRS_CH11VAL */
7835 #define _PRS_PEEK_CH11VAL_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7836 #define PRS_PEEK_CH11VAL_DEFAULT                   (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */
7837 #define PRS_PEEK_CH12VAL                           (0x1UL << 12)                     /**< Channel 12 Current Value */
7838 #define _PRS_PEEK_CH12VAL_SHIFT                    12                                /**< Shift value for PRS_CH12VAL */
7839 #define _PRS_PEEK_CH12VAL_MASK                     0x1000UL                          /**< Bit mask for PRS_CH12VAL */
7840 #define _PRS_PEEK_CH12VAL_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7841 #define PRS_PEEK_CH12VAL_DEFAULT                   (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */
7842 #define PRS_PEEK_CH13VAL                           (0x1UL << 13)                     /**< Channel 13 Current Value */
7843 #define _PRS_PEEK_CH13VAL_SHIFT                    13                                /**< Shift value for PRS_CH13VAL */
7844 #define _PRS_PEEK_CH13VAL_MASK                     0x2000UL                          /**< Bit mask for PRS_CH13VAL */
7845 #define _PRS_PEEK_CH13VAL_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7846 #define PRS_PEEK_CH13VAL_DEFAULT                   (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */
7847 #define PRS_PEEK_CH14VAL                           (0x1UL << 14)                     /**< Channel 14 Current Value */
7848 #define _PRS_PEEK_CH14VAL_SHIFT                    14                                /**< Shift value for PRS_CH14VAL */
7849 #define _PRS_PEEK_CH14VAL_MASK                     0x4000UL                          /**< Bit mask for PRS_CH14VAL */
7850 #define _PRS_PEEK_CH14VAL_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7851 #define PRS_PEEK_CH14VAL_DEFAULT                   (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */
7852 #define PRS_PEEK_CH15VAL                           (0x1UL << 15)                     /**< Channel 15 Current Value */
7853 #define _PRS_PEEK_CH15VAL_SHIFT                    15                                /**< Shift value for PRS_CH15VAL */
7854 #define _PRS_PEEK_CH15VAL_MASK                     0x8000UL                          /**< Bit mask for PRS_CH15VAL */
7855 #define _PRS_PEEK_CH15VAL_DEFAULT                  0x00000000UL                      /**< Mode DEFAULT for PRS_PEEK */
7856 #define PRS_PEEK_CH15VAL_DEFAULT                   (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */
7857 
7858 /* Bit fields for PRS CH_CTRL */
7859 #define _PRS_CH_CTRL_RESETVALUE                    0x00000000UL                                   /**< Default value for PRS_CH_CTRL */
7860 #define _PRS_CH_CTRL_MASK                          0x5E307F07UL                                   /**< Mask for PRS_CH_CTRL */
7861 #define _PRS_CH_CTRL_SIGSEL_SHIFT                  0                                              /**< Shift value for PRS_SIGSEL */
7862 #define _PRS_CH_CTRL_SIGSEL_MASK                   0x7UL                                          /**< Bit mask for PRS_SIGSEL */
7863 #define _PRS_CH_CTRL_SIGSEL_PRSCH0                 0x00000000UL                                   /**< Mode PRSCH0 for PRS_CH_CTRL */
7864 #define _PRS_CH_CTRL_SIGSEL_PRSCH8                 0x00000000UL                                   /**< Mode PRSCH8 for PRS_CH_CTRL */
7865 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT               0x00000000UL                                   /**< Mode ACMP0OUT for PRS_CH_CTRL */
7866 #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT               0x00000000UL                                   /**< Mode ACMP1OUT for PRS_CH_CTRL */
7867 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE             0x00000000UL                                   /**< Mode ADC0SINGLE for PRS_CH_CTRL */
7868 #define _PRS_CH_CTRL_SIGSEL_RTCOF                  0x00000000UL                                   /**< Mode RTCOF for PRS_CH_CTRL */
7869 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0               0x00000000UL                                   /**< Mode GPIOPIN0 for PRS_CH_CTRL */
7870 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8               0x00000000UL                                   /**< Mode GPIOPIN8 for PRS_CH_CTRL */
7871 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0            0x00000000UL                                   /**< Mode LETIMER0CH0 for PRS_CH_CTRL */
7872 #define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0            0x00000000UL                                   /**< Mode LETIMER1CH0 for PRS_CH_CTRL */
7873 #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC               0x00000000UL                                   /**< Mode PCNT0TCC for PRS_CH_CTRL */
7874 #define _PRS_CH_CTRL_SIGSEL_PCNT1TCC               0x00000000UL                                   /**< Mode PCNT1TCC for PRS_CH_CTRL */
7875 #define _PRS_CH_CTRL_SIGSEL_PCNT2TCC               0x00000000UL                                   /**< Mode PCNT2TCC for PRS_CH_CTRL */
7876 #define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD        0x00000000UL                                   /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */
7877 #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0             0x00000000UL                                   /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */
7878 #define _PRS_CH_CTRL_SIGSEL_VDAC0CH0               0x00000000UL                                   /**< Mode VDAC0CH0 for PRS_CH_CTRL */
7879 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0        0x00000000UL                                   /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */
7880 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8        0x00000000UL                                   /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */
7881 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0            0x00000000UL                                   /**< Mode LESENSEDEC0 for PRS_CH_CTRL */
7882 #define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT         0x00000000UL                                   /**< Mode LESENSEMEASACT for PRS_CH_CTRL */
7883 #define _PRS_CH_CTRL_SIGSEL_ACMP2OUT               0x00000000UL                                   /**< Mode ACMP2OUT for PRS_CH_CTRL */
7884 #define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE             0x00000000UL                                   /**< Mode ADC1SINGLE for PRS_CH_CTRL */
7885 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX             0x00000000UL                                   /**< Mode USART0IRTX for PRS_CH_CTRL */
7886 #define _PRS_CH_CTRL_SIGSEL_USART2IRTX             0x00000000UL                                   /**< Mode USART2IRTX for PRS_CH_CTRL */
7887 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF               0x00000000UL                                   /**< Mode TIMER0UF for PRS_CH_CTRL */
7888 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF               0x00000000UL                                   /**< Mode TIMER1UF for PRS_CH_CTRL */
7889 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF               0x00000000UL                                   /**< Mode TIMER2UF for PRS_CH_CTRL */
7890 #define _PRS_CH_CTRL_SIGSEL_CM4TXEV                0x00000000UL                                   /**< Mode CM4TXEV for PRS_CH_CTRL */
7891 #define _PRS_CH_CTRL_SIGSEL_TIMER3UF               0x00000000UL                                   /**< Mode TIMER3UF for PRS_CH_CTRL */
7892 #define _PRS_CH_CTRL_SIGSEL_WTIMER0UF              0x00000000UL                                   /**< Mode WTIMER0UF for PRS_CH_CTRL */
7893 #define _PRS_CH_CTRL_SIGSEL_WTIMER1UF              0x00000000UL                                   /**< Mode WTIMER1UF for PRS_CH_CTRL */
7894 #define _PRS_CH_CTRL_SIGSEL_PDMDSRPULSE            0x00000000UL                                   /**< Mode PDMDSRPULSE for PRS_CH_CTRL */
7895 #define _PRS_CH_CTRL_SIGSEL_PRSCH1                 0x00000001UL                                   /**< Mode PRSCH1 for PRS_CH_CTRL */
7896 #define _PRS_CH_CTRL_SIGSEL_PRSCH9                 0x00000001UL                                   /**< Mode PRSCH9 for PRS_CH_CTRL */
7897 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN               0x00000001UL                                   /**< Mode ADC0SCAN for PRS_CH_CTRL */
7898 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0               0x00000001UL                                   /**< Mode RTCCOMP0 for PRS_CH_CTRL */
7899 #define _PRS_CH_CTRL_SIGSEL_RTCCCCV0               0x00000001UL                                   /**< Mode RTCCCCV0 for PRS_CH_CTRL */
7900 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1               0x00000001UL                                   /**< Mode GPIOPIN1 for PRS_CH_CTRL */
7901 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9               0x00000001UL                                   /**< Mode GPIOPIN9 for PRS_CH_CTRL */
7902 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1            0x00000001UL                                   /**< Mode LETIMER0CH1 for PRS_CH_CTRL */
7903 #define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1            0x00000001UL                                   /**< Mode LETIMER1CH1 for PRS_CH_CTRL */
7904 #define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF              0x00000001UL                                   /**< Mode PCNT0UFOF for PRS_CH_CTRL */
7905 #define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF              0x00000001UL                                   /**< Mode PCNT1UFOF for PRS_CH_CTRL */
7906 #define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF              0x00000001UL                                   /**< Mode PCNT2UFOF for PRS_CH_CTRL */
7907 #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1             0x00000001UL                                   /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */
7908 #define _PRS_CH_CTRL_SIGSEL_VDAC0CH1               0x00000001UL                                   /**< Mode VDAC0CH1 for PRS_CH_CTRL */
7909 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1        0x00000001UL                                   /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */
7910 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9        0x00000001UL                                   /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */
7911 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1            0x00000001UL                                   /**< Mode LESENSEDEC1 for PRS_CH_CTRL */
7912 #define _PRS_CH_CTRL_SIGSEL_ADC1SCAN               0x00000001UL                                   /**< Mode ADC1SCAN for PRS_CH_CTRL */
7913 #define _PRS_CH_CTRL_SIGSEL_USART0TXC              0x00000001UL                                   /**< Mode USART0TXC for PRS_CH_CTRL */
7914 #define _PRS_CH_CTRL_SIGSEL_USART1TXC              0x00000001UL                                   /**< Mode USART1TXC for PRS_CH_CTRL */
7915 #define _PRS_CH_CTRL_SIGSEL_USART2TXC              0x00000001UL                                   /**< Mode USART2TXC for PRS_CH_CTRL */
7916 #define _PRS_CH_CTRL_SIGSEL_USART3TXC              0x00000001UL                                   /**< Mode USART3TXC for PRS_CH_CTRL */
7917 #define _PRS_CH_CTRL_SIGSEL_USART4TXC              0x00000001UL                                   /**< Mode USART4TXC for PRS_CH_CTRL */
7918 #define _PRS_CH_CTRL_SIGSEL_UART0TXC               0x00000001UL                                   /**< Mode UART0TXC for PRS_CH_CTRL */
7919 #define _PRS_CH_CTRL_SIGSEL_UART1TXC               0x00000001UL                                   /**< Mode UART1TXC for PRS_CH_CTRL */
7920 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF               0x00000001UL                                   /**< Mode TIMER0OF for PRS_CH_CTRL */
7921 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF               0x00000001UL                                   /**< Mode TIMER1OF for PRS_CH_CTRL */
7922 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF               0x00000001UL                                   /**< Mode TIMER2OF for PRS_CH_CTRL */
7923 #define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF      0x00000001UL                                   /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */
7924 #define _PRS_CH_CTRL_SIGSEL_TIMER3OF               0x00000001UL                                   /**< Mode TIMER3OF for PRS_CH_CTRL */
7925 #define _PRS_CH_CTRL_SIGSEL_WTIMER0OF              0x00000001UL                                   /**< Mode WTIMER0OF for PRS_CH_CTRL */
7926 #define _PRS_CH_CTRL_SIGSEL_WTIMER1OF              0x00000001UL                                   /**< Mode WTIMER1OF for PRS_CH_CTRL */
7927 #define _PRS_CH_CTRL_SIGSEL_PRSCH2                 0x00000002UL                                   /**< Mode PRSCH2 for PRS_CH_CTRL */
7928 #define _PRS_CH_CTRL_SIGSEL_PRSCH10                0x00000002UL                                   /**< Mode PRSCH10 for PRS_CH_CTRL */
7929 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1               0x00000002UL                                   /**< Mode RTCCOMP1 for PRS_CH_CTRL */
7930 #define _PRS_CH_CTRL_SIGSEL_RTCCCCV1               0x00000002UL                                   /**< Mode RTCCCCV1 for PRS_CH_CTRL */
7931 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2               0x00000002UL                                   /**< Mode GPIOPIN2 for PRS_CH_CTRL */
7932 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10              0x00000002UL                                   /**< Mode GPIOPIN10 for PRS_CH_CTRL */
7933 #define _PRS_CH_CTRL_SIGSEL_PCNT0DIR               0x00000002UL                                   /**< Mode PCNT0DIR for PRS_CH_CTRL */
7934 #define _PRS_CH_CTRL_SIGSEL_PCNT1DIR               0x00000002UL                                   /**< Mode PCNT1DIR for PRS_CH_CTRL */
7935 #define _PRS_CH_CTRL_SIGSEL_PCNT2DIR               0x00000002UL                                   /**< Mode PCNT2DIR for PRS_CH_CTRL */
7936 #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0              0x00000002UL                                   /**< Mode VDAC0OPA0 for PRS_CH_CTRL */
7937 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2        0x00000002UL                                   /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */
7938 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10       0x00000002UL                                   /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */
7939 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2            0x00000002UL                                   /**< Mode LESENSEDEC2 for PRS_CH_CTRL */
7940 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV          0x00000002UL                                   /**< Mode USART0RXDATAV for PRS_CH_CTRL */
7941 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV          0x00000002UL                                   /**< Mode USART1RXDATAV for PRS_CH_CTRL */
7942 #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV          0x00000002UL                                   /**< Mode USART2RXDATAV for PRS_CH_CTRL */
7943 #define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV          0x00000002UL                                   /**< Mode USART3RXDATAV for PRS_CH_CTRL */
7944 #define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV          0x00000002UL                                   /**< Mode USART4RXDATAV for PRS_CH_CTRL */
7945 #define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV           0x00000002UL                                   /**< Mode UART0RXDATAV for PRS_CH_CTRL */
7946 #define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV           0x00000002UL                                   /**< Mode UART1RXDATAV for PRS_CH_CTRL */
7947 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0              0x00000002UL                                   /**< Mode TIMER0CC0 for PRS_CH_CTRL */
7948 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0              0x00000002UL                                   /**< Mode TIMER1CC0 for PRS_CH_CTRL */
7949 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0              0x00000002UL                                   /**< Mode TIMER2CC0 for PRS_CH_CTRL */
7950 #define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF    0x00000002UL                                   /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */
7951 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC0              0x00000002UL                                   /**< Mode TIMER3CC0 for PRS_CH_CTRL */
7952 #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0             0x00000002UL                                   /**< Mode WTIMER0CC0 for PRS_CH_CTRL */
7953 #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0             0x00000002UL                                   /**< Mode WTIMER1CC0 for PRS_CH_CTRL */
7954 #define _PRS_CH_CTRL_SIGSEL_PRSCH3                 0x00000003UL                                   /**< Mode PRSCH3 for PRS_CH_CTRL */
7955 #define _PRS_CH_CTRL_SIGSEL_PRSCH11                0x00000003UL                                   /**< Mode PRSCH11 for PRS_CH_CTRL */
7956 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP2               0x00000003UL                                   /**< Mode RTCCOMP2 for PRS_CH_CTRL */
7957 #define _PRS_CH_CTRL_SIGSEL_RTCCCCV2               0x00000003UL                                   /**< Mode RTCCCCV2 for PRS_CH_CTRL */
7958 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3               0x00000003UL                                   /**< Mode GPIOPIN3 for PRS_CH_CTRL */
7959 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11              0x00000003UL                                   /**< Mode GPIOPIN11 for PRS_CH_CTRL */
7960 #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1              0x00000003UL                                   /**< Mode VDAC0OPA1 for PRS_CH_CTRL */
7961 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3        0x00000003UL                                   /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */
7962 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11       0x00000003UL                                   /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */
7963 #define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP          0x00000003UL                                   /**< Mode LESENSEDECCMP for PRS_CH_CTRL */
7964 #define _PRS_CH_CTRL_SIGSEL_USART0RTS              0x00000003UL                                   /**< Mode USART0RTS for PRS_CH_CTRL */
7965 #define _PRS_CH_CTRL_SIGSEL_USART1RTS              0x00000003UL                                   /**< Mode USART1RTS for PRS_CH_CTRL */
7966 #define _PRS_CH_CTRL_SIGSEL_USART2RTS              0x00000003UL                                   /**< Mode USART2RTS for PRS_CH_CTRL */
7967 #define _PRS_CH_CTRL_SIGSEL_USART3RTS              0x00000003UL                                   /**< Mode USART3RTS for PRS_CH_CTRL */
7968 #define _PRS_CH_CTRL_SIGSEL_USART4RTS              0x00000003UL                                   /**< Mode USART4RTS for PRS_CH_CTRL */
7969 #define _PRS_CH_CTRL_SIGSEL_UART0RTS               0x00000003UL                                   /**< Mode UART0RTS for PRS_CH_CTRL */
7970 #define _PRS_CH_CTRL_SIGSEL_UART1RTS               0x00000003UL                                   /**< Mode UART1RTS for PRS_CH_CTRL */
7971 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1              0x00000003UL                                   /**< Mode TIMER0CC1 for PRS_CH_CTRL */
7972 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1              0x00000003UL                                   /**< Mode TIMER1CC1 for PRS_CH_CTRL */
7973 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1              0x00000003UL                                   /**< Mode TIMER2CC1 for PRS_CH_CTRL */
7974 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC1              0x00000003UL                                   /**< Mode TIMER3CC1 for PRS_CH_CTRL */
7975 #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1             0x00000003UL                                   /**< Mode WTIMER0CC1 for PRS_CH_CTRL */
7976 #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1             0x00000003UL                                   /**< Mode WTIMER1CC1 for PRS_CH_CTRL */
7977 #define _PRS_CH_CTRL_SIGSEL_PRSCH4                 0x00000004UL                                   /**< Mode PRSCH4 for PRS_CH_CTRL */
7978 #define _PRS_CH_CTRL_SIGSEL_PRSCH12                0x00000004UL                                   /**< Mode PRSCH12 for PRS_CH_CTRL */
7979 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP3               0x00000004UL                                   /**< Mode RTCCOMP3 for PRS_CH_CTRL */
7980 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4               0x00000004UL                                   /**< Mode GPIOPIN4 for PRS_CH_CTRL */
7981 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12              0x00000004UL                                   /**< Mode GPIOPIN12 for PRS_CH_CTRL */
7982 #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2              0x00000004UL                                   /**< Mode VDAC0OPA2 for PRS_CH_CTRL */
7983 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4        0x00000004UL                                   /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */
7984 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12       0x00000004UL                                   /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */
7985 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2              0x00000004UL                                   /**< Mode TIMER0CC2 for PRS_CH_CTRL */
7986 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2              0x00000004UL                                   /**< Mode TIMER1CC2 for PRS_CH_CTRL */
7987 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2              0x00000004UL                                   /**< Mode TIMER2CC2 for PRS_CH_CTRL */
7988 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC2              0x00000004UL                                   /**< Mode TIMER3CC2 for PRS_CH_CTRL */
7989 #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2             0x00000004UL                                   /**< Mode WTIMER0CC2 for PRS_CH_CTRL */
7990 #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2             0x00000004UL                                   /**< Mode WTIMER1CC2 for PRS_CH_CTRL */
7991 #define _PRS_CH_CTRL_SIGSEL_PRSCH5                 0x00000005UL                                   /**< Mode PRSCH5 for PRS_CH_CTRL */
7992 #define _PRS_CH_CTRL_SIGSEL_PRSCH13                0x00000005UL                                   /**< Mode PRSCH13 for PRS_CH_CTRL */
7993 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP4               0x00000005UL                                   /**< Mode RTCCOMP4 for PRS_CH_CTRL */
7994 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5               0x00000005UL                                   /**< Mode GPIOPIN5 for PRS_CH_CTRL */
7995 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13              0x00000005UL                                   /**< Mode GPIOPIN13 for PRS_CH_CTRL */
7996 #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3              0x00000005UL                                   /**< Mode VDAC0OPA3 for PRS_CH_CTRL */
7997 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5        0x00000005UL                                   /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */
7998 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13       0x00000005UL                                   /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */
7999 #define _PRS_CH_CTRL_SIGSEL_USART0TX               0x00000005UL                                   /**< Mode USART0TX for PRS_CH_CTRL */
8000 #define _PRS_CH_CTRL_SIGSEL_USART1TX               0x00000005UL                                   /**< Mode USART1TX for PRS_CH_CTRL */
8001 #define _PRS_CH_CTRL_SIGSEL_USART2TX               0x00000005UL                                   /**< Mode USART2TX for PRS_CH_CTRL */
8002 #define _PRS_CH_CTRL_SIGSEL_USART3TX               0x00000005UL                                   /**< Mode USART3TX for PRS_CH_CTRL */
8003 #define _PRS_CH_CTRL_SIGSEL_USART4TX               0x00000005UL                                   /**< Mode USART4TX for PRS_CH_CTRL */
8004 #define _PRS_CH_CTRL_SIGSEL_UART0TX                0x00000005UL                                   /**< Mode UART0TX for PRS_CH_CTRL */
8005 #define _PRS_CH_CTRL_SIGSEL_UART1TX                0x00000005UL                                   /**< Mode UART1TX for PRS_CH_CTRL */
8006 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC3              0x00000005UL                                   /**< Mode TIMER1CC3 for PRS_CH_CTRL */
8007 #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3             0x00000005UL                                   /**< Mode WTIMER1CC3 for PRS_CH_CTRL */
8008 #define _PRS_CH_CTRL_SIGSEL_PRSCH6                 0x00000006UL                                   /**< Mode PRSCH6 for PRS_CH_CTRL */
8009 #define _PRS_CH_CTRL_SIGSEL_PRSCH14                0x00000006UL                                   /**< Mode PRSCH14 for PRS_CH_CTRL */
8010 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP5               0x00000006UL                                   /**< Mode RTCCOMP5 for PRS_CH_CTRL */
8011 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6               0x00000006UL                                   /**< Mode GPIOPIN6 for PRS_CH_CTRL */
8012 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14              0x00000006UL                                   /**< Mode GPIOPIN14 for PRS_CH_CTRL */
8013 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6        0x00000006UL                                   /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */
8014 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14       0x00000006UL                                   /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */
8015 #define _PRS_CH_CTRL_SIGSEL_USART0CS               0x00000006UL                                   /**< Mode USART0CS for PRS_CH_CTRL */
8016 #define _PRS_CH_CTRL_SIGSEL_USART1CS               0x00000006UL                                   /**< Mode USART1CS for PRS_CH_CTRL */
8017 #define _PRS_CH_CTRL_SIGSEL_USART2CS               0x00000006UL                                   /**< Mode USART2CS for PRS_CH_CTRL */
8018 #define _PRS_CH_CTRL_SIGSEL_USART3CS               0x00000006UL                                   /**< Mode USART3CS for PRS_CH_CTRL */
8019 #define _PRS_CH_CTRL_SIGSEL_USART4CS               0x00000006UL                                   /**< Mode USART4CS for PRS_CH_CTRL */
8020 #define _PRS_CH_CTRL_SIGSEL_UART0CS                0x00000006UL                                   /**< Mode UART0CS for PRS_CH_CTRL */
8021 #define _PRS_CH_CTRL_SIGSEL_UART1CS                0x00000006UL                                   /**< Mode UART1CS for PRS_CH_CTRL */
8022 #define _PRS_CH_CTRL_SIGSEL_PRSCH7                 0x00000007UL                                   /**< Mode PRSCH7 for PRS_CH_CTRL */
8023 #define _PRS_CH_CTRL_SIGSEL_PRSCH15                0x00000007UL                                   /**< Mode PRSCH15 for PRS_CH_CTRL */
8024 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7               0x00000007UL                                   /**< Mode GPIOPIN7 for PRS_CH_CTRL */
8025 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15              0x00000007UL                                   /**< Mode GPIOPIN15 for PRS_CH_CTRL */
8026 #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2             0x00000007UL                                   /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */
8027 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7        0x00000007UL                                   /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */
8028 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15       0x00000007UL                                   /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */
8029 #define PRS_CH_CTRL_SIGSEL_PRSCH0                  (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0)              /**< Shifted mode PRSCH0 for PRS_CH_CTRL */
8030 #define PRS_CH_CTRL_SIGSEL_PRSCH8                  (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0)              /**< Shifted mode PRSCH8 for PRS_CH_CTRL */
8031 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT                (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0)            /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */
8032 #define PRS_CH_CTRL_SIGSEL_ACMP1OUT                (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0)            /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */
8033 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE              (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0)          /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */
8034 #define PRS_CH_CTRL_SIGSEL_RTCOF                   (_PRS_CH_CTRL_SIGSEL_RTCOF << 0)               /**< Shifted mode RTCOF for PRS_CH_CTRL */
8035 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0                (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0)            /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */
8036 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8                (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0)            /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */
8037 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0             (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0)         /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */
8038 #define PRS_CH_CTRL_SIGSEL_LETIMER1CH0             (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0)         /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */
8039 #define PRS_CH_CTRL_SIGSEL_PCNT0TCC                (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0)            /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */
8040 #define PRS_CH_CTRL_SIGSEL_PCNT1TCC                (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0)            /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */
8041 #define PRS_CH_CTRL_SIGSEL_PCNT2TCC                (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0)            /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */
8042 #define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD         (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0)     /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */
8043 #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0              (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0)          /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */
8044 #define PRS_CH_CTRL_SIGSEL_VDAC0CH0                (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0)            /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */
8045 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0         (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0)     /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */
8046 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8         (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0)     /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */
8047 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0             (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0)         /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */
8048 #define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT          (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0)      /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */
8049 #define PRS_CH_CTRL_SIGSEL_ACMP2OUT                (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0)            /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */
8050 #define PRS_CH_CTRL_SIGSEL_ADC1SINGLE              (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0)          /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */
8051 #define PRS_CH_CTRL_SIGSEL_USART0IRTX              (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0)          /**< Shifted mode USART0IRTX for PRS_CH_CTRL */
8052 #define PRS_CH_CTRL_SIGSEL_USART2IRTX              (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0)          /**< Shifted mode USART2IRTX for PRS_CH_CTRL */
8053 #define PRS_CH_CTRL_SIGSEL_TIMER0UF                (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0)            /**< Shifted mode TIMER0UF for PRS_CH_CTRL */
8054 #define PRS_CH_CTRL_SIGSEL_TIMER1UF                (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0)            /**< Shifted mode TIMER1UF for PRS_CH_CTRL */
8055 #define PRS_CH_CTRL_SIGSEL_TIMER2UF                (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0)            /**< Shifted mode TIMER2UF for PRS_CH_CTRL */
8056 #define PRS_CH_CTRL_SIGSEL_CM4TXEV                 (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0)             /**< Shifted mode CM4TXEV for PRS_CH_CTRL */
8057 #define PRS_CH_CTRL_SIGSEL_TIMER3UF                (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0)            /**< Shifted mode TIMER3UF for PRS_CH_CTRL */
8058 #define PRS_CH_CTRL_SIGSEL_WTIMER0UF               (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0)           /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */
8059 #define PRS_CH_CTRL_SIGSEL_WTIMER1UF               (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0)           /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */
8060 #define PRS_CH_CTRL_SIGSEL_PDMDSRPULSE             (_PRS_CH_CTRL_SIGSEL_PDMDSRPULSE << 0)         /**< Shifted mode PDMDSRPULSE for PRS_CH_CTRL */
8061 #define PRS_CH_CTRL_SIGSEL_PRSCH1                  (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0)              /**< Shifted mode PRSCH1 for PRS_CH_CTRL */
8062 #define PRS_CH_CTRL_SIGSEL_PRSCH9                  (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0)              /**< Shifted mode PRSCH9 for PRS_CH_CTRL */
8063 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN                (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0)            /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */
8064 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0                (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0)            /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */
8065 #define PRS_CH_CTRL_SIGSEL_RTCCCCV0                (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0)            /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */
8066 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1                (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0)            /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */
8067 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9                (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0)            /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */
8068 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1             (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0)         /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */
8069 #define PRS_CH_CTRL_SIGSEL_LETIMER1CH1             (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0)         /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */
8070 #define PRS_CH_CTRL_SIGSEL_PCNT0UFOF               (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0)           /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */
8071 #define PRS_CH_CTRL_SIGSEL_PCNT1UFOF               (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0)           /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */
8072 #define PRS_CH_CTRL_SIGSEL_PCNT2UFOF               (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0)           /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */
8073 #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1              (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0)          /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */
8074 #define PRS_CH_CTRL_SIGSEL_VDAC0CH1                (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0)            /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */
8075 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1         (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0)     /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */
8076 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9         (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0)     /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */
8077 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1             (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0)         /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */
8078 #define PRS_CH_CTRL_SIGSEL_ADC1SCAN                (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0)            /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */
8079 #define PRS_CH_CTRL_SIGSEL_USART0TXC               (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0)           /**< Shifted mode USART0TXC for PRS_CH_CTRL */
8080 #define PRS_CH_CTRL_SIGSEL_USART1TXC               (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0)           /**< Shifted mode USART1TXC for PRS_CH_CTRL */
8081 #define PRS_CH_CTRL_SIGSEL_USART2TXC               (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0)           /**< Shifted mode USART2TXC for PRS_CH_CTRL */
8082 #define PRS_CH_CTRL_SIGSEL_USART3TXC               (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0)           /**< Shifted mode USART3TXC for PRS_CH_CTRL */
8083 #define PRS_CH_CTRL_SIGSEL_USART4TXC               (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0)           /**< Shifted mode USART4TXC for PRS_CH_CTRL */
8084 #define PRS_CH_CTRL_SIGSEL_UART0TXC                (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0)            /**< Shifted mode UART0TXC for PRS_CH_CTRL */
8085 #define PRS_CH_CTRL_SIGSEL_UART1TXC                (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0)            /**< Shifted mode UART1TXC for PRS_CH_CTRL */
8086 #define PRS_CH_CTRL_SIGSEL_TIMER0OF                (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0)            /**< Shifted mode TIMER0OF for PRS_CH_CTRL */
8087 #define PRS_CH_CTRL_SIGSEL_TIMER1OF                (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0)            /**< Shifted mode TIMER1OF for PRS_CH_CTRL */
8088 #define PRS_CH_CTRL_SIGSEL_TIMER2OF                (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0)            /**< Shifted mode TIMER2OF for PRS_CH_CTRL */
8089 #define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF       (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0)   /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */
8090 #define PRS_CH_CTRL_SIGSEL_TIMER3OF                (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0)            /**< Shifted mode TIMER3OF for PRS_CH_CTRL */
8091 #define PRS_CH_CTRL_SIGSEL_WTIMER0OF               (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0)           /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */
8092 #define PRS_CH_CTRL_SIGSEL_WTIMER1OF               (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0)           /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */
8093 #define PRS_CH_CTRL_SIGSEL_PRSCH2                  (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0)              /**< Shifted mode PRSCH2 for PRS_CH_CTRL */
8094 #define PRS_CH_CTRL_SIGSEL_PRSCH10                 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0)             /**< Shifted mode PRSCH10 for PRS_CH_CTRL */
8095 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1                (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0)            /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */
8096 #define PRS_CH_CTRL_SIGSEL_RTCCCCV1                (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0)            /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */
8097 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2                (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0)            /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */
8098 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10               (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0)           /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */
8099 #define PRS_CH_CTRL_SIGSEL_PCNT0DIR                (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0)            /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */
8100 #define PRS_CH_CTRL_SIGSEL_PCNT1DIR                (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0)            /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */
8101 #define PRS_CH_CTRL_SIGSEL_PCNT2DIR                (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0)            /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */
8102 #define PRS_CH_CTRL_SIGSEL_VDAC0OPA0               (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0)           /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */
8103 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2         (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0)     /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */
8104 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10        (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0)    /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */
8105 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2             (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0)         /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */
8106 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV           (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0)       /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */
8107 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV           (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0)       /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */
8108 #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV           (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0)       /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */
8109 #define PRS_CH_CTRL_SIGSEL_USART3RXDATAV           (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0)       /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */
8110 #define PRS_CH_CTRL_SIGSEL_USART4RXDATAV           (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0)       /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */
8111 #define PRS_CH_CTRL_SIGSEL_UART0RXDATAV            (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0)        /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */
8112 #define PRS_CH_CTRL_SIGSEL_UART1RXDATAV            (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0)        /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */
8113 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0               (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0)           /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */
8114 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0               (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0)           /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */
8115 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0               (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0)           /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */
8116 #define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF     (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */
8117 #define PRS_CH_CTRL_SIGSEL_TIMER3CC0               (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0)           /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */
8118 #define PRS_CH_CTRL_SIGSEL_WTIMER0CC0              (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0)          /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */
8119 #define PRS_CH_CTRL_SIGSEL_WTIMER1CC0              (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0)          /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */
8120 #define PRS_CH_CTRL_SIGSEL_PRSCH3                  (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0)              /**< Shifted mode PRSCH3 for PRS_CH_CTRL */
8121 #define PRS_CH_CTRL_SIGSEL_PRSCH11                 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0)             /**< Shifted mode PRSCH11 for PRS_CH_CTRL */
8122 #define PRS_CH_CTRL_SIGSEL_RTCCOMP2                (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0)            /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */
8123 #define PRS_CH_CTRL_SIGSEL_RTCCCCV2                (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0)            /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */
8124 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3                (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0)            /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */
8125 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11               (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0)           /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */
8126 #define PRS_CH_CTRL_SIGSEL_VDAC0OPA1               (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0)           /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */
8127 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3         (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0)     /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */
8128 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11        (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0)    /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */
8129 #define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP           (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0)       /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */
8130 #define PRS_CH_CTRL_SIGSEL_USART0RTS               (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0)           /**< Shifted mode USART0RTS for PRS_CH_CTRL */
8131 #define PRS_CH_CTRL_SIGSEL_USART1RTS               (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0)           /**< Shifted mode USART1RTS for PRS_CH_CTRL */
8132 #define PRS_CH_CTRL_SIGSEL_USART2RTS               (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0)           /**< Shifted mode USART2RTS for PRS_CH_CTRL */
8133 #define PRS_CH_CTRL_SIGSEL_USART3RTS               (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0)           /**< Shifted mode USART3RTS for PRS_CH_CTRL */
8134 #define PRS_CH_CTRL_SIGSEL_USART4RTS               (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0)           /**< Shifted mode USART4RTS for PRS_CH_CTRL */
8135 #define PRS_CH_CTRL_SIGSEL_UART0RTS                (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0)            /**< Shifted mode UART0RTS for PRS_CH_CTRL */
8136 #define PRS_CH_CTRL_SIGSEL_UART1RTS                (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0)            /**< Shifted mode UART1RTS for PRS_CH_CTRL */
8137 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1               (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0)           /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */
8138 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1               (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0)           /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */
8139 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1               (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0)           /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */
8140 #define PRS_CH_CTRL_SIGSEL_TIMER3CC1               (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0)           /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */
8141 #define PRS_CH_CTRL_SIGSEL_WTIMER0CC1              (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0)          /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */
8142 #define PRS_CH_CTRL_SIGSEL_WTIMER1CC1              (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0)          /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */
8143 #define PRS_CH_CTRL_SIGSEL_PRSCH4                  (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0)              /**< Shifted mode PRSCH4 for PRS_CH_CTRL */
8144 #define PRS_CH_CTRL_SIGSEL_PRSCH12                 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0)             /**< Shifted mode PRSCH12 for PRS_CH_CTRL */
8145 #define PRS_CH_CTRL_SIGSEL_RTCCOMP3                (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0)            /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */
8146 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4                (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0)            /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */
8147 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12               (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0)           /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */
8148 #define PRS_CH_CTRL_SIGSEL_VDAC0OPA2               (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0)           /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */
8149 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4         (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0)     /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */
8150 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12        (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0)    /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */
8151 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2               (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0)           /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */
8152 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2               (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0)           /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */
8153 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2               (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0)           /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */
8154 #define PRS_CH_CTRL_SIGSEL_TIMER3CC2               (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0)           /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */
8155 #define PRS_CH_CTRL_SIGSEL_WTIMER0CC2              (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0)          /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */
8156 #define PRS_CH_CTRL_SIGSEL_WTIMER1CC2              (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0)          /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */
8157 #define PRS_CH_CTRL_SIGSEL_PRSCH5                  (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0)              /**< Shifted mode PRSCH5 for PRS_CH_CTRL */
8158 #define PRS_CH_CTRL_SIGSEL_PRSCH13                 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0)             /**< Shifted mode PRSCH13 for PRS_CH_CTRL */
8159 #define PRS_CH_CTRL_SIGSEL_RTCCOMP4                (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0)            /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */
8160 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5                (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0)            /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */
8161 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13               (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0)           /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */
8162 #define PRS_CH_CTRL_SIGSEL_VDAC0OPA3               (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0)           /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */
8163 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5         (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0)     /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */
8164 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13        (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0)    /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */
8165 #define PRS_CH_CTRL_SIGSEL_USART0TX                (_PRS_CH_CTRL_SIGSEL_USART0TX << 0)            /**< Shifted mode USART0TX for PRS_CH_CTRL */
8166 #define PRS_CH_CTRL_SIGSEL_USART1TX                (_PRS_CH_CTRL_SIGSEL_USART1TX << 0)            /**< Shifted mode USART1TX for PRS_CH_CTRL */
8167 #define PRS_CH_CTRL_SIGSEL_USART2TX                (_PRS_CH_CTRL_SIGSEL_USART2TX << 0)            /**< Shifted mode USART2TX for PRS_CH_CTRL */
8168 #define PRS_CH_CTRL_SIGSEL_USART3TX                (_PRS_CH_CTRL_SIGSEL_USART3TX << 0)            /**< Shifted mode USART3TX for PRS_CH_CTRL */
8169 #define PRS_CH_CTRL_SIGSEL_USART4TX                (_PRS_CH_CTRL_SIGSEL_USART4TX << 0)            /**< Shifted mode USART4TX for PRS_CH_CTRL */
8170 #define PRS_CH_CTRL_SIGSEL_UART0TX                 (_PRS_CH_CTRL_SIGSEL_UART0TX << 0)             /**< Shifted mode UART0TX for PRS_CH_CTRL */
8171 #define PRS_CH_CTRL_SIGSEL_UART1TX                 (_PRS_CH_CTRL_SIGSEL_UART1TX << 0)             /**< Shifted mode UART1TX for PRS_CH_CTRL */
8172 #define PRS_CH_CTRL_SIGSEL_TIMER1CC3               (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0)           /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */
8173 #define PRS_CH_CTRL_SIGSEL_WTIMER1CC3              (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0)          /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */
8174 #define PRS_CH_CTRL_SIGSEL_PRSCH6                  (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0)              /**< Shifted mode PRSCH6 for PRS_CH_CTRL */
8175 #define PRS_CH_CTRL_SIGSEL_PRSCH14                 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0)             /**< Shifted mode PRSCH14 for PRS_CH_CTRL */
8176 #define PRS_CH_CTRL_SIGSEL_RTCCOMP5                (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0)            /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */
8177 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6                (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0)            /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */
8178 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14               (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0)           /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */
8179 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6         (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0)     /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */
8180 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14        (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0)    /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */
8181 #define PRS_CH_CTRL_SIGSEL_USART0CS                (_PRS_CH_CTRL_SIGSEL_USART0CS << 0)            /**< Shifted mode USART0CS for PRS_CH_CTRL */
8182 #define PRS_CH_CTRL_SIGSEL_USART1CS                (_PRS_CH_CTRL_SIGSEL_USART1CS << 0)            /**< Shifted mode USART1CS for PRS_CH_CTRL */
8183 #define PRS_CH_CTRL_SIGSEL_USART2CS                (_PRS_CH_CTRL_SIGSEL_USART2CS << 0)            /**< Shifted mode USART2CS for PRS_CH_CTRL */
8184 #define PRS_CH_CTRL_SIGSEL_USART3CS                (_PRS_CH_CTRL_SIGSEL_USART3CS << 0)            /**< Shifted mode USART3CS for PRS_CH_CTRL */
8185 #define PRS_CH_CTRL_SIGSEL_USART4CS                (_PRS_CH_CTRL_SIGSEL_USART4CS << 0)            /**< Shifted mode USART4CS for PRS_CH_CTRL */
8186 #define PRS_CH_CTRL_SIGSEL_UART0CS                 (_PRS_CH_CTRL_SIGSEL_UART0CS << 0)             /**< Shifted mode UART0CS for PRS_CH_CTRL */
8187 #define PRS_CH_CTRL_SIGSEL_UART1CS                 (_PRS_CH_CTRL_SIGSEL_UART1CS << 0)             /**< Shifted mode UART1CS for PRS_CH_CTRL */
8188 #define PRS_CH_CTRL_SIGSEL_PRSCH7                  (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0)              /**< Shifted mode PRSCH7 for PRS_CH_CTRL */
8189 #define PRS_CH_CTRL_SIGSEL_PRSCH15                 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0)             /**< Shifted mode PRSCH15 for PRS_CH_CTRL */
8190 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7                (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0)            /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */
8191 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15               (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0)           /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */
8192 #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2              (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0)          /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */
8193 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7         (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0)     /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */
8194 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15        (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0)    /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */
8195 #define _PRS_CH_CTRL_SOURCESEL_SHIFT               8                                              /**< Shift value for PRS_SOURCESEL */
8196 #define _PRS_CH_CTRL_SOURCESEL_MASK                0x7F00UL                                       /**< Bit mask for PRS_SOURCESEL */
8197 #define _PRS_CH_CTRL_SOURCESEL_NONE                0x00000000UL                                   /**< Mode NONE for PRS_CH_CTRL */
8198 #define _PRS_CH_CTRL_SOURCESEL_PRSL                0x00000001UL                                   /**< Mode PRSL for PRS_CH_CTRL */
8199 #define _PRS_CH_CTRL_SOURCESEL_PRS                 0x00000002UL                                   /**< Mode PRS for PRS_CH_CTRL */
8200 #define _PRS_CH_CTRL_SOURCESEL_ACMP0               0x00000004UL                                   /**< Mode ACMP0 for PRS_CH_CTRL */
8201 #define _PRS_CH_CTRL_SOURCESEL_ACMP1               0x00000005UL                                   /**< Mode ACMP1 for PRS_CH_CTRL */
8202 #define _PRS_CH_CTRL_SOURCESEL_ADC0                0x00000006UL                                   /**< Mode ADC0 for PRS_CH_CTRL */
8203 #define _PRS_CH_CTRL_SOURCESEL_RTC                 0x00000007UL                                   /**< Mode RTC for PRS_CH_CTRL */
8204 #define _PRS_CH_CTRL_SOURCESEL_RTCC                0x00000008UL                                   /**< Mode RTCC for PRS_CH_CTRL */
8205 #define _PRS_CH_CTRL_SOURCESEL_GPIOL               0x00000009UL                                   /**< Mode GPIOL for PRS_CH_CTRL */
8206 #define _PRS_CH_CTRL_SOURCESEL_GPIOH               0x0000000AUL                                   /**< Mode GPIOH for PRS_CH_CTRL */
8207 #define _PRS_CH_CTRL_SOURCESEL_LETIMER0            0x0000000BUL                                   /**< Mode LETIMER0 for PRS_CH_CTRL */
8208 #define _PRS_CH_CTRL_SOURCESEL_LETIMER1            0x0000000CUL                                   /**< Mode LETIMER1 for PRS_CH_CTRL */
8209 #define _PRS_CH_CTRL_SOURCESEL_PCNT0               0x0000000DUL                                   /**< Mode PCNT0 for PRS_CH_CTRL */
8210 #define _PRS_CH_CTRL_SOURCESEL_PCNT1               0x0000000EUL                                   /**< Mode PCNT1 for PRS_CH_CTRL */
8211 #define _PRS_CH_CTRL_SOURCESEL_PCNT2               0x0000000FUL                                   /**< Mode PCNT2 for PRS_CH_CTRL */
8212 #define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER           0x00000010UL                                   /**< Mode CRYOTIMER for PRS_CH_CTRL */
8213 #define _PRS_CH_CTRL_SOURCESEL_CMU                 0x00000011UL                                   /**< Mode CMU for PRS_CH_CTRL */
8214 #define _PRS_CH_CTRL_SOURCESEL_VDAC0               0x00000017UL                                   /**< Mode VDAC0 for PRS_CH_CTRL */
8215 #define _PRS_CH_CTRL_SOURCESEL_LESENSEL            0x00000018UL                                   /**< Mode LESENSEL for PRS_CH_CTRL */
8216 #define _PRS_CH_CTRL_SOURCESEL_LESENSEH            0x00000019UL                                   /**< Mode LESENSEH for PRS_CH_CTRL */
8217 #define _PRS_CH_CTRL_SOURCESEL_LESENSED            0x0000001AUL                                   /**< Mode LESENSED for PRS_CH_CTRL */
8218 #define _PRS_CH_CTRL_SOURCESEL_LESENSE             0x0000001BUL                                   /**< Mode LESENSE for PRS_CH_CTRL */
8219 #define _PRS_CH_CTRL_SOURCESEL_ACMP2               0x0000001CUL                                   /**< Mode ACMP2 for PRS_CH_CTRL */
8220 #define _PRS_CH_CTRL_SOURCESEL_ADC1                0x0000001DUL                                   /**< Mode ADC1 for PRS_CH_CTRL */
8221 #define _PRS_CH_CTRL_SOURCESEL_USART0              0x00000030UL                                   /**< Mode USART0 for PRS_CH_CTRL */
8222 #define _PRS_CH_CTRL_SOURCESEL_USART1              0x00000031UL                                   /**< Mode USART1 for PRS_CH_CTRL */
8223 #define _PRS_CH_CTRL_SOURCESEL_USART2              0x00000032UL                                   /**< Mode USART2 for PRS_CH_CTRL */
8224 #define _PRS_CH_CTRL_SOURCESEL_USART3              0x00000033UL                                   /**< Mode USART3 for PRS_CH_CTRL */
8225 #define _PRS_CH_CTRL_SOURCESEL_USART4              0x00000034UL                                   /**< Mode USART4 for PRS_CH_CTRL */
8226 #define _PRS_CH_CTRL_SOURCESEL_UART0               0x00000036UL                                   /**< Mode UART0 for PRS_CH_CTRL */
8227 #define _PRS_CH_CTRL_SOURCESEL_UART1               0x00000037UL                                   /**< Mode UART1 for PRS_CH_CTRL */
8228 #define _PRS_CH_CTRL_SOURCESEL_TIMER0              0x0000003CUL                                   /**< Mode TIMER0 for PRS_CH_CTRL */
8229 #define _PRS_CH_CTRL_SOURCESEL_TIMER1              0x0000003DUL                                   /**< Mode TIMER1 for PRS_CH_CTRL */
8230 #define _PRS_CH_CTRL_SOURCESEL_TIMER2              0x0000003EUL                                   /**< Mode TIMER2 for PRS_CH_CTRL */
8231 #define _PRS_CH_CTRL_SOURCESEL_CM4                 0x00000043UL                                   /**< Mode CM4 for PRS_CH_CTRL */
8232 #define _PRS_CH_CTRL_SOURCESEL_TIMER3              0x00000050UL                                   /**< Mode TIMER3 for PRS_CH_CTRL */
8233 #define _PRS_CH_CTRL_SOURCESEL_WTIMER0             0x00000052UL                                   /**< Mode WTIMER0 for PRS_CH_CTRL */
8234 #define _PRS_CH_CTRL_SOURCESEL_WTIMER1             0x00000053UL                                   /**< Mode WTIMER1 for PRS_CH_CTRL */
8235 #define _PRS_CH_CTRL_SOURCESEL_PDM                 0x00000079UL                                   /**< Mode PDM for PRS_CH_CTRL */
8236 #define PRS_CH_CTRL_SOURCESEL_NONE                 (_PRS_CH_CTRL_SOURCESEL_NONE << 8)             /**< Shifted mode NONE for PRS_CH_CTRL */
8237 #define PRS_CH_CTRL_SOURCESEL_PRSL                 (_PRS_CH_CTRL_SOURCESEL_PRSL << 8)             /**< Shifted mode PRSL for PRS_CH_CTRL */
8238 #define PRS_CH_CTRL_SOURCESEL_PRS                  (_PRS_CH_CTRL_SOURCESEL_PRS << 8)              /**< Shifted mode PRS for PRS_CH_CTRL */
8239 #define PRS_CH_CTRL_SOURCESEL_ACMP0                (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8)            /**< Shifted mode ACMP0 for PRS_CH_CTRL */
8240 #define PRS_CH_CTRL_SOURCESEL_ACMP1                (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8)            /**< Shifted mode ACMP1 for PRS_CH_CTRL */
8241 #define PRS_CH_CTRL_SOURCESEL_ADC0                 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8)             /**< Shifted mode ADC0 for PRS_CH_CTRL */
8242 #define PRS_CH_CTRL_SOURCESEL_RTC                  (_PRS_CH_CTRL_SOURCESEL_RTC << 8)              /**< Shifted mode RTC for PRS_CH_CTRL */
8243 #define PRS_CH_CTRL_SOURCESEL_RTCC                 (_PRS_CH_CTRL_SOURCESEL_RTCC << 8)             /**< Shifted mode RTCC for PRS_CH_CTRL */
8244 #define PRS_CH_CTRL_SOURCESEL_GPIOL                (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8)            /**< Shifted mode GPIOL for PRS_CH_CTRL */
8245 #define PRS_CH_CTRL_SOURCESEL_GPIOH                (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8)            /**< Shifted mode GPIOH for PRS_CH_CTRL */
8246 #define PRS_CH_CTRL_SOURCESEL_LETIMER0             (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8)         /**< Shifted mode LETIMER0 for PRS_CH_CTRL */
8247 #define PRS_CH_CTRL_SOURCESEL_LETIMER1             (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8)         /**< Shifted mode LETIMER1 for PRS_CH_CTRL */
8248 #define PRS_CH_CTRL_SOURCESEL_PCNT0                (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8)            /**< Shifted mode PCNT0 for PRS_CH_CTRL */
8249 #define PRS_CH_CTRL_SOURCESEL_PCNT1                (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8)            /**< Shifted mode PCNT1 for PRS_CH_CTRL */
8250 #define PRS_CH_CTRL_SOURCESEL_PCNT2                (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8)            /**< Shifted mode PCNT2 for PRS_CH_CTRL */
8251 #define PRS_CH_CTRL_SOURCESEL_CRYOTIMER            (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8)        /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */
8252 #define PRS_CH_CTRL_SOURCESEL_CMU                  (_PRS_CH_CTRL_SOURCESEL_CMU << 8)              /**< Shifted mode CMU for PRS_CH_CTRL */
8253 #define PRS_CH_CTRL_SOURCESEL_VDAC0                (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8)            /**< Shifted mode VDAC0 for PRS_CH_CTRL */
8254 #define PRS_CH_CTRL_SOURCESEL_LESENSEL             (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8)         /**< Shifted mode LESENSEL for PRS_CH_CTRL */
8255 #define PRS_CH_CTRL_SOURCESEL_LESENSEH             (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8)         /**< Shifted mode LESENSEH for PRS_CH_CTRL */
8256 #define PRS_CH_CTRL_SOURCESEL_LESENSED             (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8)         /**< Shifted mode LESENSED for PRS_CH_CTRL */
8257 #define PRS_CH_CTRL_SOURCESEL_LESENSE              (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8)          /**< Shifted mode LESENSE for PRS_CH_CTRL */
8258 #define PRS_CH_CTRL_SOURCESEL_ACMP2                (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8)            /**< Shifted mode ACMP2 for PRS_CH_CTRL */
8259 #define PRS_CH_CTRL_SOURCESEL_ADC1                 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8)             /**< Shifted mode ADC1 for PRS_CH_CTRL */
8260 #define PRS_CH_CTRL_SOURCESEL_USART0               (_PRS_CH_CTRL_SOURCESEL_USART0 << 8)           /**< Shifted mode USART0 for PRS_CH_CTRL */
8261 #define PRS_CH_CTRL_SOURCESEL_USART1               (_PRS_CH_CTRL_SOURCESEL_USART1 << 8)           /**< Shifted mode USART1 for PRS_CH_CTRL */
8262 #define PRS_CH_CTRL_SOURCESEL_USART2               (_PRS_CH_CTRL_SOURCESEL_USART2 << 8)           /**< Shifted mode USART2 for PRS_CH_CTRL */
8263 #define PRS_CH_CTRL_SOURCESEL_USART3               (_PRS_CH_CTRL_SOURCESEL_USART3 << 8)           /**< Shifted mode USART3 for PRS_CH_CTRL */
8264 #define PRS_CH_CTRL_SOURCESEL_USART4               (_PRS_CH_CTRL_SOURCESEL_USART4 << 8)           /**< Shifted mode USART4 for PRS_CH_CTRL */
8265 #define PRS_CH_CTRL_SOURCESEL_UART0                (_PRS_CH_CTRL_SOURCESEL_UART0 << 8)            /**< Shifted mode UART0 for PRS_CH_CTRL */
8266 #define PRS_CH_CTRL_SOURCESEL_UART1                (_PRS_CH_CTRL_SOURCESEL_UART1 << 8)            /**< Shifted mode UART1 for PRS_CH_CTRL */
8267 #define PRS_CH_CTRL_SOURCESEL_TIMER0               (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8)           /**< Shifted mode TIMER0 for PRS_CH_CTRL */
8268 #define PRS_CH_CTRL_SOURCESEL_TIMER1               (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8)           /**< Shifted mode TIMER1 for PRS_CH_CTRL */
8269 #define PRS_CH_CTRL_SOURCESEL_TIMER2               (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8)           /**< Shifted mode TIMER2 for PRS_CH_CTRL */
8270 #define PRS_CH_CTRL_SOURCESEL_CM4                  (_PRS_CH_CTRL_SOURCESEL_CM4 << 8)              /**< Shifted mode CM4 for PRS_CH_CTRL */
8271 #define PRS_CH_CTRL_SOURCESEL_TIMER3               (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8)           /**< Shifted mode TIMER3 for PRS_CH_CTRL */
8272 #define PRS_CH_CTRL_SOURCESEL_WTIMER0              (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8)          /**< Shifted mode WTIMER0 for PRS_CH_CTRL */
8273 #define PRS_CH_CTRL_SOURCESEL_WTIMER1              (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8)          /**< Shifted mode WTIMER1 for PRS_CH_CTRL */
8274 #define PRS_CH_CTRL_SOURCESEL_PDM                  (_PRS_CH_CTRL_SOURCESEL_PDM << 8)              /**< Shifted mode PDM for PRS_CH_CTRL */
8275 #define _PRS_CH_CTRL_EDSEL_SHIFT                   20                                             /**< Shift value for PRS_EDSEL */
8276 #define _PRS_CH_CTRL_EDSEL_MASK                    0x300000UL                                     /**< Bit mask for PRS_EDSEL */
8277 #define _PRS_CH_CTRL_EDSEL_DEFAULT                 0x00000000UL                                   /**< Mode DEFAULT for PRS_CH_CTRL */
8278 #define _PRS_CH_CTRL_EDSEL_OFF                     0x00000000UL                                   /**< Mode OFF for PRS_CH_CTRL */
8279 #define _PRS_CH_CTRL_EDSEL_POSEDGE                 0x00000001UL                                   /**< Mode POSEDGE for PRS_CH_CTRL */
8280 #define _PRS_CH_CTRL_EDSEL_NEGEDGE                 0x00000002UL                                   /**< Mode NEGEDGE for PRS_CH_CTRL */
8281 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES               0x00000003UL                                   /**< Mode BOTHEDGES for PRS_CH_CTRL */
8282 #define PRS_CH_CTRL_EDSEL_DEFAULT                  (_PRS_CH_CTRL_EDSEL_DEFAULT << 20)             /**< Shifted mode DEFAULT for PRS_CH_CTRL */
8283 #define PRS_CH_CTRL_EDSEL_OFF                      (_PRS_CH_CTRL_EDSEL_OFF << 20)                 /**< Shifted mode OFF for PRS_CH_CTRL */
8284 #define PRS_CH_CTRL_EDSEL_POSEDGE                  (_PRS_CH_CTRL_EDSEL_POSEDGE << 20)             /**< Shifted mode POSEDGE for PRS_CH_CTRL */
8285 #define PRS_CH_CTRL_EDSEL_NEGEDGE                  (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20)             /**< Shifted mode NEGEDGE for PRS_CH_CTRL */
8286 #define PRS_CH_CTRL_EDSEL_BOTHEDGES                (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20)           /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */
8287 #define PRS_CH_CTRL_STRETCH                        (0x1UL << 25)                                  /**< Stretch Channel Output */
8288 #define _PRS_CH_CTRL_STRETCH_SHIFT                 25                                             /**< Shift value for PRS_STRETCH */
8289 #define _PRS_CH_CTRL_STRETCH_MASK                  0x2000000UL                                    /**< Bit mask for PRS_STRETCH */
8290 #define _PRS_CH_CTRL_STRETCH_DEFAULT               0x00000000UL                                   /**< Mode DEFAULT for PRS_CH_CTRL */
8291 #define PRS_CH_CTRL_STRETCH_DEFAULT                (_PRS_CH_CTRL_STRETCH_DEFAULT << 25)           /**< Shifted mode DEFAULT for PRS_CH_CTRL */
8292 #define PRS_CH_CTRL_INV                            (0x1UL << 26)                                  /**< Invert Channel */
8293 #define _PRS_CH_CTRL_INV_SHIFT                     26                                             /**< Shift value for PRS_INV */
8294 #define _PRS_CH_CTRL_INV_MASK                      0x4000000UL                                    /**< Bit mask for PRS_INV */
8295 #define _PRS_CH_CTRL_INV_DEFAULT                   0x00000000UL                                   /**< Mode DEFAULT for PRS_CH_CTRL */
8296 #define PRS_CH_CTRL_INV_DEFAULT                    (_PRS_CH_CTRL_INV_DEFAULT << 26)               /**< Shifted mode DEFAULT for PRS_CH_CTRL */
8297 #define PRS_CH_CTRL_ORPREV                         (0x1UL << 27)                                  /**< Or Previous */
8298 #define _PRS_CH_CTRL_ORPREV_SHIFT                  27                                             /**< Shift value for PRS_ORPREV */
8299 #define _PRS_CH_CTRL_ORPREV_MASK                   0x8000000UL                                    /**< Bit mask for PRS_ORPREV */
8300 #define _PRS_CH_CTRL_ORPREV_DEFAULT                0x00000000UL                                   /**< Mode DEFAULT for PRS_CH_CTRL */
8301 #define PRS_CH_CTRL_ORPREV_DEFAULT                 (_PRS_CH_CTRL_ORPREV_DEFAULT << 27)            /**< Shifted mode DEFAULT for PRS_CH_CTRL */
8302 #define PRS_CH_CTRL_ANDNEXT                        (0x1UL << 28)                                  /**< And Next */
8303 #define _PRS_CH_CTRL_ANDNEXT_SHIFT                 28                                             /**< Shift value for PRS_ANDNEXT */
8304 #define _PRS_CH_CTRL_ANDNEXT_MASK                  0x10000000UL                                   /**< Bit mask for PRS_ANDNEXT */
8305 #define _PRS_CH_CTRL_ANDNEXT_DEFAULT               0x00000000UL                                   /**< Mode DEFAULT for PRS_CH_CTRL */
8306 #define PRS_CH_CTRL_ANDNEXT_DEFAULT                (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28)           /**< Shifted mode DEFAULT for PRS_CH_CTRL */
8307 #define PRS_CH_CTRL_ASYNC                          (0x1UL << 30)                                  /**< Asynchronous Reflex */
8308 #define _PRS_CH_CTRL_ASYNC_SHIFT                   30                                             /**< Shift value for PRS_ASYNC */
8309 #define _PRS_CH_CTRL_ASYNC_MASK                    0x40000000UL                                   /**< Bit mask for PRS_ASYNC */
8310 #define _PRS_CH_CTRL_ASYNC_DEFAULT                 0x00000000UL                                   /**< Mode DEFAULT for PRS_CH_CTRL */
8311 #define PRS_CH_CTRL_ASYNC_DEFAULT                  (_PRS_CH_CTRL_ASYNC_DEFAULT << 30)             /**< Shifted mode DEFAULT for PRS_CH_CTRL */
8312 
8313 /** @} */
8314 /** @} End of group EFM32GG12B310F1024GQ100_PRS */
8315 
8316 /***************************************************************************//**
8317  * @addtogroup EFM32GG12B310F1024GQ100_SMU
8318  * @{
8319  * @defgroup EFM32GG12B310F1024GQ100_SMU_BitFields  SMU Bit Fields
8320  * @{
8321  ******************************************************************************/
8322 
8323 /* Bit fields for SMU IF */
8324 #define _SMU_IF_RESETVALUE                 0x00000000UL                   /**< Default value for SMU_IF */
8325 #define _SMU_IF_MASK                       0x00000001UL                   /**< Mask for SMU_IF */
8326 #define SMU_IF_PPUPRIV                     (0x1UL << 0)                   /**< PPU Privilege Interrupt Flag */
8327 #define _SMU_IF_PPUPRIV_SHIFT              0                              /**< Shift value for SMU_PPUPRIV */
8328 #define _SMU_IF_PPUPRIV_MASK               0x1UL                          /**< Bit mask for SMU_PPUPRIV */
8329 #define _SMU_IF_PPUPRIV_DEFAULT            0x00000000UL                   /**< Mode DEFAULT for SMU_IF */
8330 #define SMU_IF_PPUPRIV_DEFAULT             (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */
8331 
8332 /* Bit fields for SMU IFS */
8333 #define _SMU_IFS_RESETVALUE                0x00000000UL                    /**< Default value for SMU_IFS */
8334 #define _SMU_IFS_MASK                      0x00000001UL                    /**< Mask for SMU_IFS */
8335 #define SMU_IFS_PPUPRIV                    (0x1UL << 0)                    /**< Set PPUPRIV Interrupt Flag */
8336 #define _SMU_IFS_PPUPRIV_SHIFT             0                               /**< Shift value for SMU_PPUPRIV */
8337 #define _SMU_IFS_PPUPRIV_MASK              0x1UL                           /**< Bit mask for SMU_PPUPRIV */
8338 #define _SMU_IFS_PPUPRIV_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for SMU_IFS */
8339 #define SMU_IFS_PPUPRIV_DEFAULT            (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */
8340 
8341 /* Bit fields for SMU IFC */
8342 #define _SMU_IFC_RESETVALUE                0x00000000UL                    /**< Default value for SMU_IFC */
8343 #define _SMU_IFC_MASK                      0x00000001UL                    /**< Mask for SMU_IFC */
8344 #define SMU_IFC_PPUPRIV                    (0x1UL << 0)                    /**< Clear PPUPRIV Interrupt Flag */
8345 #define _SMU_IFC_PPUPRIV_SHIFT             0                               /**< Shift value for SMU_PPUPRIV */
8346 #define _SMU_IFC_PPUPRIV_MASK              0x1UL                           /**< Bit mask for SMU_PPUPRIV */
8347 #define _SMU_IFC_PPUPRIV_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for SMU_IFC */
8348 #define SMU_IFC_PPUPRIV_DEFAULT            (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */
8349 
8350 /* Bit fields for SMU IEN */
8351 #define _SMU_IEN_RESETVALUE                0x00000000UL                    /**< Default value for SMU_IEN */
8352 #define _SMU_IEN_MASK                      0x00000001UL                    /**< Mask for SMU_IEN */
8353 #define SMU_IEN_PPUPRIV                    (0x1UL << 0)                    /**< PPUPRIV Interrupt Enable */
8354 #define _SMU_IEN_PPUPRIV_SHIFT             0                               /**< Shift value for SMU_PPUPRIV */
8355 #define _SMU_IEN_PPUPRIV_MASK              0x1UL                           /**< Bit mask for SMU_PPUPRIV */
8356 #define _SMU_IEN_PPUPRIV_DEFAULT           0x00000000UL                    /**< Mode DEFAULT for SMU_IEN */
8357 #define SMU_IEN_PPUPRIV_DEFAULT            (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */
8358 
8359 /* Bit fields for SMU PPUCTRL */
8360 #define _SMU_PPUCTRL_RESETVALUE            0x00000000UL                       /**< Default value for SMU_PPUCTRL */
8361 #define _SMU_PPUCTRL_MASK                  0x00000001UL                       /**< Mask for SMU_PPUCTRL */
8362 #define SMU_PPUCTRL_ENABLE                 (0x1UL << 0)                       /**<  */
8363 #define _SMU_PPUCTRL_ENABLE_SHIFT          0                                  /**< Shift value for SMU_ENABLE */
8364 #define _SMU_PPUCTRL_ENABLE_MASK           0x1UL                              /**< Bit mask for SMU_ENABLE */
8365 #define _SMU_PPUCTRL_ENABLE_DEFAULT        0x00000000UL                       /**< Mode DEFAULT for SMU_PPUCTRL */
8366 #define SMU_PPUCTRL_ENABLE_DEFAULT         (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */
8367 
8368 /* Bit fields for SMU PPUPATD0 */
8369 #define _SMU_PPUPATD0_RESETVALUE           0x00000000UL                           /**< Default value for SMU_PPUPATD0 */
8370 #define _SMU_PPUPATD0_MASK                 0x1FFFFFFFUL                           /**< Mask for SMU_PPUPATD0 */
8371 #define SMU_PPUPATD0_ACMP0                 (0x1UL << 0)                           /**< Analog Comparator 0 access control bit */
8372 #define _SMU_PPUPATD0_ACMP0_SHIFT          0                                      /**< Shift value for SMU_ACMP0 */
8373 #define _SMU_PPUPATD0_ACMP0_MASK           0x1UL                                  /**< Bit mask for SMU_ACMP0 */
8374 #define _SMU_PPUPATD0_ACMP0_DEFAULT        0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8375 #define SMU_PPUPATD0_ACMP0_DEFAULT         (_SMU_PPUPATD0_ACMP0_DEFAULT << 0)     /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8376 #define SMU_PPUPATD0_ACMP1                 (0x1UL << 1)                           /**< Analog Comparator 1 access control bit */
8377 #define _SMU_PPUPATD0_ACMP1_SHIFT          1                                      /**< Shift value for SMU_ACMP1 */
8378 #define _SMU_PPUPATD0_ACMP1_MASK           0x2UL                                  /**< Bit mask for SMU_ACMP1 */
8379 #define _SMU_PPUPATD0_ACMP1_DEFAULT        0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8380 #define SMU_PPUPATD0_ACMP1_DEFAULT         (_SMU_PPUPATD0_ACMP1_DEFAULT << 1)     /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8381 #define SMU_PPUPATD0_ACMP2                 (0x1UL << 2)                           /**< Analog Comparator 2 access control bit */
8382 #define _SMU_PPUPATD0_ACMP2_SHIFT          2                                      /**< Shift value for SMU_ACMP2 */
8383 #define _SMU_PPUPATD0_ACMP2_MASK           0x4UL                                  /**< Bit mask for SMU_ACMP2 */
8384 #define _SMU_PPUPATD0_ACMP2_DEFAULT        0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8385 #define SMU_PPUPATD0_ACMP2_DEFAULT         (_SMU_PPUPATD0_ACMP2_DEFAULT << 2)     /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8386 #define SMU_PPUPATD0_ADC0                  (0x1UL << 3)                           /**< Analog to Digital Converter 0 access control bit */
8387 #define _SMU_PPUPATD0_ADC0_SHIFT           3                                      /**< Shift value for SMU_ADC0 */
8388 #define _SMU_PPUPATD0_ADC0_MASK            0x8UL                                  /**< Bit mask for SMU_ADC0 */
8389 #define _SMU_PPUPATD0_ADC0_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8390 #define SMU_PPUPATD0_ADC0_DEFAULT          (_SMU_PPUPATD0_ADC0_DEFAULT << 3)      /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8391 #define SMU_PPUPATD0_ADC1                  (0x1UL << 4)                           /**< Analog to Digital Converter 0 access control bit */
8392 #define _SMU_PPUPATD0_ADC1_SHIFT           4                                      /**< Shift value for SMU_ADC1 */
8393 #define _SMU_PPUPATD0_ADC1_MASK            0x10UL                                 /**< Bit mask for SMU_ADC1 */
8394 #define _SMU_PPUPATD0_ADC1_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8395 #define SMU_PPUPATD0_ADC1_DEFAULT          (_SMU_PPUPATD0_ADC1_DEFAULT << 4)      /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8396 #define SMU_PPUPATD0_CAN0                  (0x1UL << 5)                           /**< CAN 0 access control bit */
8397 #define _SMU_PPUPATD0_CAN0_SHIFT           5                                      /**< Shift value for SMU_CAN0 */
8398 #define _SMU_PPUPATD0_CAN0_MASK            0x20UL                                 /**< Bit mask for SMU_CAN0 */
8399 #define _SMU_PPUPATD0_CAN0_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8400 #define SMU_PPUPATD0_CAN0_DEFAULT          (_SMU_PPUPATD0_CAN0_DEFAULT << 5)      /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8401 #define SMU_PPUPATD0_CAN1                  (0x1UL << 6)                           /**< CAN 1 access control bit */
8402 #define _SMU_PPUPATD0_CAN1_SHIFT           6                                      /**< Shift value for SMU_CAN1 */
8403 #define _SMU_PPUPATD0_CAN1_MASK            0x40UL                                 /**< Bit mask for SMU_CAN1 */
8404 #define _SMU_PPUPATD0_CAN1_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8405 #define SMU_PPUPATD0_CAN1_DEFAULT          (_SMU_PPUPATD0_CAN1_DEFAULT << 6)      /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8406 #define SMU_PPUPATD0_CMU                   (0x1UL << 7)                           /**< Clock Management Unit access control bit */
8407 #define _SMU_PPUPATD0_CMU_SHIFT            7                                      /**< Shift value for SMU_CMU */
8408 #define _SMU_PPUPATD0_CMU_MASK             0x80UL                                 /**< Bit mask for SMU_CMU */
8409 #define _SMU_PPUPATD0_CMU_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8410 #define SMU_PPUPATD0_CMU_DEFAULT           (_SMU_PPUPATD0_CMU_DEFAULT << 7)       /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8411 #define SMU_PPUPATD0_CRYOTIMER             (0x1UL << 8)                           /**< CRYOTIMER access control bit */
8412 #define _SMU_PPUPATD0_CRYOTIMER_SHIFT      8                                      /**< Shift value for SMU_CRYOTIMER */
8413 #define _SMU_PPUPATD0_CRYOTIMER_MASK       0x100UL                                /**< Bit mask for SMU_CRYOTIMER */
8414 #define _SMU_PPUPATD0_CRYOTIMER_DEFAULT    0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8415 #define SMU_PPUPATD0_CRYOTIMER_DEFAULT     (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8416 #define SMU_PPUPATD0_CRYPTO0               (0x1UL << 9)                           /**< Advanced Encryption Standard Accelerator access control bit */
8417 #define _SMU_PPUPATD0_CRYPTO0_SHIFT        9                                      /**< Shift value for SMU_CRYPTO0 */
8418 #define _SMU_PPUPATD0_CRYPTO0_MASK         0x200UL                                /**< Bit mask for SMU_CRYPTO0 */
8419 #define _SMU_PPUPATD0_CRYPTO0_DEFAULT      0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8420 #define SMU_PPUPATD0_CRYPTO0_DEFAULT       (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 9)   /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8421 #define SMU_PPUPATD0_CSEN                  (0x1UL << 10)                          /**< Capacitive touch sense module access control bit */
8422 #define _SMU_PPUPATD0_CSEN_SHIFT           10                                     /**< Shift value for SMU_CSEN */
8423 #define _SMU_PPUPATD0_CSEN_MASK            0x400UL                                /**< Bit mask for SMU_CSEN */
8424 #define _SMU_PPUPATD0_CSEN_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8425 #define SMU_PPUPATD0_CSEN_DEFAULT          (_SMU_PPUPATD0_CSEN_DEFAULT << 10)     /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8426 #define SMU_PPUPATD0_VDAC0                 (0x1UL << 11)                          /**< Digital to Analog Converter 0 access control bit */
8427 #define _SMU_PPUPATD0_VDAC0_SHIFT          11                                     /**< Shift value for SMU_VDAC0 */
8428 #define _SMU_PPUPATD0_VDAC0_MASK           0x800UL                                /**< Bit mask for SMU_VDAC0 */
8429 #define _SMU_PPUPATD0_VDAC0_DEFAULT        0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8430 #define SMU_PPUPATD0_VDAC0_DEFAULT         (_SMU_PPUPATD0_VDAC0_DEFAULT << 11)    /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8431 #define SMU_PPUPATD0_PRS                   (0x1UL << 12)                          /**< Peripheral Reflex System access control bit */
8432 #define _SMU_PPUPATD0_PRS_SHIFT            12                                     /**< Shift value for SMU_PRS */
8433 #define _SMU_PPUPATD0_PRS_MASK             0x1000UL                               /**< Bit mask for SMU_PRS */
8434 #define _SMU_PPUPATD0_PRS_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8435 #define SMU_PPUPATD0_PRS_DEFAULT           (_SMU_PPUPATD0_PRS_DEFAULT << 12)      /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8436 #define SMU_PPUPATD0_EBI                   (0x1UL << 13)                          /**< External Bus Interface access control bit */
8437 #define _SMU_PPUPATD0_EBI_SHIFT            13                                     /**< Shift value for SMU_EBI */
8438 #define _SMU_PPUPATD0_EBI_MASK             0x2000UL                               /**< Bit mask for SMU_EBI */
8439 #define _SMU_PPUPATD0_EBI_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8440 #define SMU_PPUPATD0_EBI_DEFAULT           (_SMU_PPUPATD0_EBI_DEFAULT << 13)      /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8441 #define SMU_PPUPATD0_EMU                   (0x1UL << 14)                          /**< Energy Management Unit access control bit */
8442 #define _SMU_PPUPATD0_EMU_SHIFT            14                                     /**< Shift value for SMU_EMU */
8443 #define _SMU_PPUPATD0_EMU_MASK             0x4000UL                               /**< Bit mask for SMU_EMU */
8444 #define _SMU_PPUPATD0_EMU_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8445 #define SMU_PPUPATD0_EMU_DEFAULT           (_SMU_PPUPATD0_EMU_DEFAULT << 14)      /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8446 #define SMU_PPUPATD0_FPUEH                 (0x1UL << 15)                          /**< FPU Exception Handler access control bit */
8447 #define _SMU_PPUPATD0_FPUEH_SHIFT          15                                     /**< Shift value for SMU_FPUEH */
8448 #define _SMU_PPUPATD0_FPUEH_MASK           0x8000UL                               /**< Bit mask for SMU_FPUEH */
8449 #define _SMU_PPUPATD0_FPUEH_DEFAULT        0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8450 #define SMU_PPUPATD0_FPUEH_DEFAULT         (_SMU_PPUPATD0_FPUEH_DEFAULT << 15)    /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8451 #define SMU_PPUPATD0_GPCRC                 (0x1UL << 16)                          /**< General Purpose CRC access control bit */
8452 #define _SMU_PPUPATD0_GPCRC_SHIFT          16                                     /**< Shift value for SMU_GPCRC */
8453 #define _SMU_PPUPATD0_GPCRC_MASK           0x10000UL                              /**< Bit mask for SMU_GPCRC */
8454 #define _SMU_PPUPATD0_GPCRC_DEFAULT        0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8455 #define SMU_PPUPATD0_GPCRC_DEFAULT         (_SMU_PPUPATD0_GPCRC_DEFAULT << 16)    /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8456 #define SMU_PPUPATD0_GPIO                  (0x1UL << 17)                          /**< General purpose Input/Output access control bit */
8457 #define _SMU_PPUPATD0_GPIO_SHIFT           17                                     /**< Shift value for SMU_GPIO */
8458 #define _SMU_PPUPATD0_GPIO_MASK            0x20000UL                              /**< Bit mask for SMU_GPIO */
8459 #define _SMU_PPUPATD0_GPIO_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8460 #define SMU_PPUPATD0_GPIO_DEFAULT          (_SMU_PPUPATD0_GPIO_DEFAULT << 17)     /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8461 #define SMU_PPUPATD0_I2C0                  (0x1UL << 18)                          /**< I2C 0 access control bit */
8462 #define _SMU_PPUPATD0_I2C0_SHIFT           18                                     /**< Shift value for SMU_I2C0 */
8463 #define _SMU_PPUPATD0_I2C0_MASK            0x40000UL                              /**< Bit mask for SMU_I2C0 */
8464 #define _SMU_PPUPATD0_I2C0_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8465 #define SMU_PPUPATD0_I2C0_DEFAULT          (_SMU_PPUPATD0_I2C0_DEFAULT << 18)     /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8466 #define SMU_PPUPATD0_I2C1                  (0x1UL << 19)                          /**< I2C 1 access control bit */
8467 #define _SMU_PPUPATD0_I2C1_SHIFT           19                                     /**< Shift value for SMU_I2C1 */
8468 #define _SMU_PPUPATD0_I2C1_MASK            0x80000UL                              /**< Bit mask for SMU_I2C1 */
8469 #define _SMU_PPUPATD0_I2C1_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8470 #define SMU_PPUPATD0_I2C1_DEFAULT          (_SMU_PPUPATD0_I2C1_DEFAULT << 19)     /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8471 #define SMU_PPUPATD0_IDAC0                 (0x1UL << 20)                          /**< Current Digital to Analog Converter 0 access control bit */
8472 #define _SMU_PPUPATD0_IDAC0_SHIFT          20                                     /**< Shift value for SMU_IDAC0 */
8473 #define _SMU_PPUPATD0_IDAC0_MASK           0x100000UL                             /**< Bit mask for SMU_IDAC0 */
8474 #define _SMU_PPUPATD0_IDAC0_DEFAULT        0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8475 #define SMU_PPUPATD0_IDAC0_DEFAULT         (_SMU_PPUPATD0_IDAC0_DEFAULT << 20)    /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8476 #define SMU_PPUPATD0_MSC                   (0x1UL << 21)                          /**< Memory System Controller access control bit */
8477 #define _SMU_PPUPATD0_MSC_SHIFT            21                                     /**< Shift value for SMU_MSC */
8478 #define _SMU_PPUPATD0_MSC_MASK             0x200000UL                             /**< Bit mask for SMU_MSC */
8479 #define _SMU_PPUPATD0_MSC_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8480 #define SMU_PPUPATD0_MSC_DEFAULT           (_SMU_PPUPATD0_MSC_DEFAULT << 21)      /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8481 #define SMU_PPUPATD0_LCD                   (0x1UL << 22)                          /**< Liquid Crystal Display Controller access control bit */
8482 #define _SMU_PPUPATD0_LCD_SHIFT            22                                     /**< Shift value for SMU_LCD */
8483 #define _SMU_PPUPATD0_LCD_MASK             0x400000UL                             /**< Bit mask for SMU_LCD */
8484 #define _SMU_PPUPATD0_LCD_DEFAULT          0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8485 #define SMU_PPUPATD0_LCD_DEFAULT           (_SMU_PPUPATD0_LCD_DEFAULT << 22)      /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8486 #define SMU_PPUPATD0_LDMA                  (0x1UL << 23)                          /**< Linked Direct Memory Access Controller access control bit */
8487 #define _SMU_PPUPATD0_LDMA_SHIFT           23                                     /**< Shift value for SMU_LDMA */
8488 #define _SMU_PPUPATD0_LDMA_MASK            0x800000UL                             /**< Bit mask for SMU_LDMA */
8489 #define _SMU_PPUPATD0_LDMA_DEFAULT         0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8490 #define SMU_PPUPATD0_LDMA_DEFAULT          (_SMU_PPUPATD0_LDMA_DEFAULT << 23)     /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8491 #define SMU_PPUPATD0_LESENSE               (0x1UL << 24)                          /**< Low Energy Sensor Interface access control bit */
8492 #define _SMU_PPUPATD0_LESENSE_SHIFT        24                                     /**< Shift value for SMU_LESENSE */
8493 #define _SMU_PPUPATD0_LESENSE_MASK         0x1000000UL                            /**< Bit mask for SMU_LESENSE */
8494 #define _SMU_PPUPATD0_LESENSE_DEFAULT      0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8495 #define SMU_PPUPATD0_LESENSE_DEFAULT       (_SMU_PPUPATD0_LESENSE_DEFAULT << 24)  /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8496 #define SMU_PPUPATD0_LETIMER0              (0x1UL << 25)                          /**< Low Energy Timer 0 access control bit */
8497 #define _SMU_PPUPATD0_LETIMER0_SHIFT       25                                     /**< Shift value for SMU_LETIMER0 */
8498 #define _SMU_PPUPATD0_LETIMER0_MASK        0x2000000UL                            /**< Bit mask for SMU_LETIMER0 */
8499 #define _SMU_PPUPATD0_LETIMER0_DEFAULT     0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8500 #define SMU_PPUPATD0_LETIMER0_DEFAULT      (_SMU_PPUPATD0_LETIMER0_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8501 #define SMU_PPUPATD0_LETIMER1              (0x1UL << 26)                          /**< Low Energy Timer 1 access control bit */
8502 #define _SMU_PPUPATD0_LETIMER1_SHIFT       26                                     /**< Shift value for SMU_LETIMER1 */
8503 #define _SMU_PPUPATD0_LETIMER1_MASK        0x4000000UL                            /**< Bit mask for SMU_LETIMER1 */
8504 #define _SMU_PPUPATD0_LETIMER1_DEFAULT     0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8505 #define SMU_PPUPATD0_LETIMER1_DEFAULT      (_SMU_PPUPATD0_LETIMER1_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8506 #define SMU_PPUPATD0_LEUART0               (0x1UL << 27)                          /**< Low Energy UART 0 access control bit */
8507 #define _SMU_PPUPATD0_LEUART0_SHIFT        27                                     /**< Shift value for SMU_LEUART0 */
8508 #define _SMU_PPUPATD0_LEUART0_MASK         0x8000000UL                            /**< Bit mask for SMU_LEUART0 */
8509 #define _SMU_PPUPATD0_LEUART0_DEFAULT      0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8510 #define SMU_PPUPATD0_LEUART0_DEFAULT       (_SMU_PPUPATD0_LEUART0_DEFAULT << 27)  /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8511 #define SMU_PPUPATD0_LEUART1               (0x1UL << 28)                          /**< Low Energy UART 1 access control bit */
8512 #define _SMU_PPUPATD0_LEUART1_SHIFT        28                                     /**< Shift value for SMU_LEUART1 */
8513 #define _SMU_PPUPATD0_LEUART1_MASK         0x10000000UL                           /**< Bit mask for SMU_LEUART1 */
8514 #define _SMU_PPUPATD0_LEUART1_DEFAULT      0x00000000UL                           /**< Mode DEFAULT for SMU_PPUPATD0 */
8515 #define SMU_PPUPATD0_LEUART1_DEFAULT       (_SMU_PPUPATD0_LEUART1_DEFAULT << 28)  /**< Shifted mode DEFAULT for SMU_PPUPATD0 */
8516 
8517 /* Bit fields for SMU PPUPATD1 */
8518 #define _SMU_PPUPATD1_RESETVALUE           0x00000000UL                          /**< Default value for SMU_PPUPATD1 */
8519 #define _SMU_PPUPATD1_MASK                 0x07BFFEEFUL                          /**< Mask for SMU_PPUPATD1 */
8520 #define SMU_PPUPATD1_PCNT0                 (0x1UL << 0)                          /**< Pulse Counter 0 access control bit */
8521 #define _SMU_PPUPATD1_PCNT0_SHIFT          0                                     /**< Shift value for SMU_PCNT0 */
8522 #define _SMU_PPUPATD1_PCNT0_MASK           0x1UL                                 /**< Bit mask for SMU_PCNT0 */
8523 #define _SMU_PPUPATD1_PCNT0_DEFAULT        0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8524 #define SMU_PPUPATD1_PCNT0_DEFAULT         (_SMU_PPUPATD1_PCNT0_DEFAULT << 0)    /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8525 #define SMU_PPUPATD1_PCNT1                 (0x1UL << 1)                          /**< Pulse Counter 1 access control bit */
8526 #define _SMU_PPUPATD1_PCNT1_SHIFT          1                                     /**< Shift value for SMU_PCNT1 */
8527 #define _SMU_PPUPATD1_PCNT1_MASK           0x2UL                                 /**< Bit mask for SMU_PCNT1 */
8528 #define _SMU_PPUPATD1_PCNT1_DEFAULT        0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8529 #define SMU_PPUPATD1_PCNT1_DEFAULT         (_SMU_PPUPATD1_PCNT1_DEFAULT << 1)    /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8530 #define SMU_PPUPATD1_PCNT2                 (0x1UL << 2)                          /**< Pulse Counter 2 access control bit */
8531 #define _SMU_PPUPATD1_PCNT2_SHIFT          2                                     /**< Shift value for SMU_PCNT2 */
8532 #define _SMU_PPUPATD1_PCNT2_MASK           0x4UL                                 /**< Bit mask for SMU_PCNT2 */
8533 #define _SMU_PPUPATD1_PCNT2_DEFAULT        0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8534 #define SMU_PPUPATD1_PCNT2_DEFAULT         (_SMU_PPUPATD1_PCNT2_DEFAULT << 2)    /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8535 #define SMU_PPUPATD1_PDM                   (0x1UL << 3)                          /**< PDM Interface  access control bit */
8536 #define _SMU_PPUPATD1_PDM_SHIFT            3                                     /**< Shift value for SMU_PDM */
8537 #define _SMU_PPUPATD1_PDM_MASK             0x8UL                                 /**< Bit mask for SMU_PDM */
8538 #define _SMU_PPUPATD1_PDM_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8539 #define SMU_PPUPATD1_PDM_DEFAULT           (_SMU_PPUPATD1_PDM_DEFAULT << 3)      /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8540 #define SMU_PPUPATD1_RMU                   (0x1UL << 5)                          /**< Reset Management Unit access control bit */
8541 #define _SMU_PPUPATD1_RMU_SHIFT            5                                     /**< Shift value for SMU_RMU */
8542 #define _SMU_PPUPATD1_RMU_MASK             0x20UL                                /**< Bit mask for SMU_RMU */
8543 #define _SMU_PPUPATD1_RMU_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8544 #define SMU_PPUPATD1_RMU_DEFAULT           (_SMU_PPUPATD1_RMU_DEFAULT << 5)      /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8545 #define SMU_PPUPATD1_RTC                   (0x1UL << 6)                          /**< Real-Time Counter access control bit */
8546 #define _SMU_PPUPATD1_RTC_SHIFT            6                                     /**< Shift value for SMU_RTC */
8547 #define _SMU_PPUPATD1_RTC_MASK             0x40UL                                /**< Bit mask for SMU_RTC */
8548 #define _SMU_PPUPATD1_RTC_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8549 #define SMU_PPUPATD1_RTC_DEFAULT           (_SMU_PPUPATD1_RTC_DEFAULT << 6)      /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8550 #define SMU_PPUPATD1_RTCC                  (0x1UL << 7)                          /**< Real-Time Counter and Calendar access control bit */
8551 #define _SMU_PPUPATD1_RTCC_SHIFT           7                                     /**< Shift value for SMU_RTCC */
8552 #define _SMU_PPUPATD1_RTCC_MASK            0x80UL                                /**< Bit mask for SMU_RTCC */
8553 #define _SMU_PPUPATD1_RTCC_DEFAULT         0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8554 #define SMU_PPUPATD1_RTCC_DEFAULT          (_SMU_PPUPATD1_RTCC_DEFAULT << 7)     /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8555 #define SMU_PPUPATD1_SMU                   (0x1UL << 9)                          /**< Security Management Unit access control bit */
8556 #define _SMU_PPUPATD1_SMU_SHIFT            9                                     /**< Shift value for SMU_SMU */
8557 #define _SMU_PPUPATD1_SMU_MASK             0x200UL                               /**< Bit mask for SMU_SMU */
8558 #define _SMU_PPUPATD1_SMU_DEFAULT          0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8559 #define SMU_PPUPATD1_SMU_DEFAULT           (_SMU_PPUPATD1_SMU_DEFAULT << 9)      /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8560 #define SMU_PPUPATD1_TIMER0                (0x1UL << 10)                         /**< Timer 0 access control bit */
8561 #define _SMU_PPUPATD1_TIMER0_SHIFT         10                                    /**< Shift value for SMU_TIMER0 */
8562 #define _SMU_PPUPATD1_TIMER0_MASK          0x400UL                               /**< Bit mask for SMU_TIMER0 */
8563 #define _SMU_PPUPATD1_TIMER0_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8564 #define SMU_PPUPATD1_TIMER0_DEFAULT        (_SMU_PPUPATD1_TIMER0_DEFAULT << 10)  /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8565 #define SMU_PPUPATD1_TIMER1                (0x1UL << 11)                         /**< Timer 1 access control bit */
8566 #define _SMU_PPUPATD1_TIMER1_SHIFT         11                                    /**< Shift value for SMU_TIMER1 */
8567 #define _SMU_PPUPATD1_TIMER1_MASK          0x800UL                               /**< Bit mask for SMU_TIMER1 */
8568 #define _SMU_PPUPATD1_TIMER1_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8569 #define SMU_PPUPATD1_TIMER1_DEFAULT        (_SMU_PPUPATD1_TIMER1_DEFAULT << 11)  /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8570 #define SMU_PPUPATD1_TIMER2                (0x1UL << 12)                         /**< Timer 2 access control bit */
8571 #define _SMU_PPUPATD1_TIMER2_SHIFT         12                                    /**< Shift value for SMU_TIMER2 */
8572 #define _SMU_PPUPATD1_TIMER2_MASK          0x1000UL                              /**< Bit mask for SMU_TIMER2 */
8573 #define _SMU_PPUPATD1_TIMER2_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8574 #define SMU_PPUPATD1_TIMER2_DEFAULT        (_SMU_PPUPATD1_TIMER2_DEFAULT << 12)  /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8575 #define SMU_PPUPATD1_TIMER3                (0x1UL << 13)                         /**< Timer 3 access control bit */
8576 #define _SMU_PPUPATD1_TIMER3_SHIFT         13                                    /**< Shift value for SMU_TIMER3 */
8577 #define _SMU_PPUPATD1_TIMER3_MASK          0x2000UL                              /**< Bit mask for SMU_TIMER3 */
8578 #define _SMU_PPUPATD1_TIMER3_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8579 #define SMU_PPUPATD1_TIMER3_DEFAULT        (_SMU_PPUPATD1_TIMER3_DEFAULT << 13)  /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8580 #define SMU_PPUPATD1_TRNG0                 (0x1UL << 14)                         /**< True Random Number Generator 0 access control bit */
8581 #define _SMU_PPUPATD1_TRNG0_SHIFT          14                                    /**< Shift value for SMU_TRNG0 */
8582 #define _SMU_PPUPATD1_TRNG0_MASK           0x4000UL                              /**< Bit mask for SMU_TRNG0 */
8583 #define _SMU_PPUPATD1_TRNG0_DEFAULT        0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8584 #define SMU_PPUPATD1_TRNG0_DEFAULT         (_SMU_PPUPATD1_TRNG0_DEFAULT << 14)   /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8585 #define SMU_PPUPATD1_UART0                 (0x1UL << 15)                         /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */
8586 #define _SMU_PPUPATD1_UART0_SHIFT          15                                    /**< Shift value for SMU_UART0 */
8587 #define _SMU_PPUPATD1_UART0_MASK           0x8000UL                              /**< Bit mask for SMU_UART0 */
8588 #define _SMU_PPUPATD1_UART0_DEFAULT        0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8589 #define SMU_PPUPATD1_UART0_DEFAULT         (_SMU_PPUPATD1_UART0_DEFAULT << 15)   /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8590 #define SMU_PPUPATD1_UART1                 (0x1UL << 16)                         /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */
8591 #define _SMU_PPUPATD1_UART1_SHIFT          16                                    /**< Shift value for SMU_UART1 */
8592 #define _SMU_PPUPATD1_UART1_MASK           0x10000UL                             /**< Bit mask for SMU_UART1 */
8593 #define _SMU_PPUPATD1_UART1_DEFAULT        0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8594 #define SMU_PPUPATD1_UART1_DEFAULT         (_SMU_PPUPATD1_UART1_DEFAULT << 16)   /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8595 #define SMU_PPUPATD1_USART0                (0x1UL << 17)                         /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */
8596 #define _SMU_PPUPATD1_USART0_SHIFT         17                                    /**< Shift value for SMU_USART0 */
8597 #define _SMU_PPUPATD1_USART0_MASK          0x20000UL                             /**< Bit mask for SMU_USART0 */
8598 #define _SMU_PPUPATD1_USART0_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8599 #define SMU_PPUPATD1_USART0_DEFAULT        (_SMU_PPUPATD1_USART0_DEFAULT << 17)  /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8600 #define SMU_PPUPATD1_USART1                (0x1UL << 18)                         /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */
8601 #define _SMU_PPUPATD1_USART1_SHIFT         18                                    /**< Shift value for SMU_USART1 */
8602 #define _SMU_PPUPATD1_USART1_MASK          0x40000UL                             /**< Bit mask for SMU_USART1 */
8603 #define _SMU_PPUPATD1_USART1_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8604 #define SMU_PPUPATD1_USART1_DEFAULT        (_SMU_PPUPATD1_USART1_DEFAULT << 18)  /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8605 #define SMU_PPUPATD1_USART2                (0x1UL << 19)                         /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */
8606 #define _SMU_PPUPATD1_USART2_SHIFT         19                                    /**< Shift value for SMU_USART2 */
8607 #define _SMU_PPUPATD1_USART2_MASK          0x80000UL                             /**< Bit mask for SMU_USART2 */
8608 #define _SMU_PPUPATD1_USART2_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8609 #define SMU_PPUPATD1_USART2_DEFAULT        (_SMU_PPUPATD1_USART2_DEFAULT << 19)  /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8610 #define SMU_PPUPATD1_USART3                (0x1UL << 20)                         /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */
8611 #define _SMU_PPUPATD1_USART3_SHIFT         20                                    /**< Shift value for SMU_USART3 */
8612 #define _SMU_PPUPATD1_USART3_MASK          0x100000UL                            /**< Bit mask for SMU_USART3 */
8613 #define _SMU_PPUPATD1_USART3_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8614 #define SMU_PPUPATD1_USART3_DEFAULT        (_SMU_PPUPATD1_USART3_DEFAULT << 20)  /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8615 #define SMU_PPUPATD1_USART4                (0x1UL << 21)                         /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */
8616 #define _SMU_PPUPATD1_USART4_SHIFT         21                                    /**< Shift value for SMU_USART4 */
8617 #define _SMU_PPUPATD1_USART4_MASK          0x200000UL                            /**< Bit mask for SMU_USART4 */
8618 #define _SMU_PPUPATD1_USART4_DEFAULT       0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8619 #define SMU_PPUPATD1_USART4_DEFAULT        (_SMU_PPUPATD1_USART4_DEFAULT << 21)  /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8620 #define SMU_PPUPATD1_WDOG0                 (0x1UL << 23)                         /**< Watchdog access control bit */
8621 #define _SMU_PPUPATD1_WDOG0_SHIFT          23                                    /**< Shift value for SMU_WDOG0 */
8622 #define _SMU_PPUPATD1_WDOG0_MASK           0x800000UL                            /**< Bit mask for SMU_WDOG0 */
8623 #define _SMU_PPUPATD1_WDOG0_DEFAULT        0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8624 #define SMU_PPUPATD1_WDOG0_DEFAULT         (_SMU_PPUPATD1_WDOG0_DEFAULT << 23)   /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8625 #define SMU_PPUPATD1_WDOG1                 (0x1UL << 24)                         /**< Watchdog access control bit */
8626 #define _SMU_PPUPATD1_WDOG1_SHIFT          24                                    /**< Shift value for SMU_WDOG1 */
8627 #define _SMU_PPUPATD1_WDOG1_MASK           0x1000000UL                           /**< Bit mask for SMU_WDOG1 */
8628 #define _SMU_PPUPATD1_WDOG1_DEFAULT        0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8629 #define SMU_PPUPATD1_WDOG1_DEFAULT         (_SMU_PPUPATD1_WDOG1_DEFAULT << 24)   /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8630 #define SMU_PPUPATD1_WTIMER0               (0x1UL << 25)                         /**< Wide Timer 0 access control bit */
8631 #define _SMU_PPUPATD1_WTIMER0_SHIFT        25                                    /**< Shift value for SMU_WTIMER0 */
8632 #define _SMU_PPUPATD1_WTIMER0_MASK         0x2000000UL                           /**< Bit mask for SMU_WTIMER0 */
8633 #define _SMU_PPUPATD1_WTIMER0_DEFAULT      0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8634 #define SMU_PPUPATD1_WTIMER0_DEFAULT       (_SMU_PPUPATD1_WTIMER0_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8635 #define SMU_PPUPATD1_WTIMER1               (0x1UL << 26)                         /**< Wide Timer 0 access control bit */
8636 #define _SMU_PPUPATD1_WTIMER1_SHIFT        26                                    /**< Shift value for SMU_WTIMER1 */
8637 #define _SMU_PPUPATD1_WTIMER1_MASK         0x4000000UL                           /**< Bit mask for SMU_WTIMER1 */
8638 #define _SMU_PPUPATD1_WTIMER1_DEFAULT      0x00000000UL                          /**< Mode DEFAULT for SMU_PPUPATD1 */
8639 #define SMU_PPUPATD1_WTIMER1_DEFAULT       (_SMU_PPUPATD1_WTIMER1_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */
8640 
8641 /* Bit fields for SMU PPUPATD2 */
8642 #define _SMU_PPUPATD2_RESETVALUE           0x00000000UL /**< Default value for SMU_PPUPATD2 */
8643 #define _SMU_PPUPATD2_MASK                 0x00000000UL /**< Mask for SMU_PPUPATD2 */
8644 
8645 /* Bit fields for SMU PPUFS */
8646 #define _SMU_PPUFS_RESETVALUE              0x00000000UL                         /**< Default value for SMU_PPUFS */
8647 #define _SMU_PPUFS_MASK                    0x0000007FUL                         /**< Mask for SMU_PPUFS */
8648 #define _SMU_PPUFS_PERIPHID_SHIFT          0                                    /**< Shift value for SMU_PERIPHID */
8649 #define _SMU_PPUFS_PERIPHID_MASK           0x7FUL                               /**< Bit mask for SMU_PERIPHID */
8650 #define _SMU_PPUFS_PERIPHID_DEFAULT        0x00000000UL                         /**< Mode DEFAULT for SMU_PPUFS */
8651 #define _SMU_PPUFS_PERIPHID_ACMP0          0x00000000UL                         /**< Mode ACMP0 for SMU_PPUFS */
8652 #define _SMU_PPUFS_PERIPHID_ACMP1          0x00000001UL                         /**< Mode ACMP1 for SMU_PPUFS */
8653 #define _SMU_PPUFS_PERIPHID_ACMP2          0x00000002UL                         /**< Mode ACMP2 for SMU_PPUFS */
8654 #define _SMU_PPUFS_PERIPHID_ADC0           0x00000003UL                         /**< Mode ADC0 for SMU_PPUFS */
8655 #define _SMU_PPUFS_PERIPHID_ADC1           0x00000004UL                         /**< Mode ADC1 for SMU_PPUFS */
8656 #define _SMU_PPUFS_PERIPHID_CAN0           0x00000005UL                         /**< Mode CAN0 for SMU_PPUFS */
8657 #define _SMU_PPUFS_PERIPHID_CAN1           0x00000006UL                         /**< Mode CAN1 for SMU_PPUFS */
8658 #define _SMU_PPUFS_PERIPHID_CMU            0x00000007UL                         /**< Mode CMU for SMU_PPUFS */
8659 #define _SMU_PPUFS_PERIPHID_CRYOTIMER      0x00000008UL                         /**< Mode CRYOTIMER for SMU_PPUFS */
8660 #define _SMU_PPUFS_PERIPHID_CRYPTO0        0x00000009UL                         /**< Mode CRYPTO0 for SMU_PPUFS */
8661 #define _SMU_PPUFS_PERIPHID_CSEN           0x0000000AUL                         /**< Mode CSEN for SMU_PPUFS */
8662 #define _SMU_PPUFS_PERIPHID_VDAC0          0x0000000BUL                         /**< Mode VDAC0 for SMU_PPUFS */
8663 #define _SMU_PPUFS_PERIPHID_PRS            0x0000000CUL                         /**< Mode PRS for SMU_PPUFS */
8664 #define _SMU_PPUFS_PERIPHID_EBI            0x0000000DUL                         /**< Mode EBI for SMU_PPUFS */
8665 #define _SMU_PPUFS_PERIPHID_EMU            0x0000000EUL                         /**< Mode EMU for SMU_PPUFS */
8666 #define _SMU_PPUFS_PERIPHID_FPUEH          0x0000000FUL                         /**< Mode FPUEH for SMU_PPUFS */
8667 #define _SMU_PPUFS_PERIPHID_GPCRC          0x00000010UL                         /**< Mode GPCRC for SMU_PPUFS */
8668 #define _SMU_PPUFS_PERIPHID_GPIO           0x00000011UL                         /**< Mode GPIO for SMU_PPUFS */
8669 #define _SMU_PPUFS_PERIPHID_I2C0           0x00000012UL                         /**< Mode I2C0 for SMU_PPUFS */
8670 #define _SMU_PPUFS_PERIPHID_I2C1           0x00000013UL                         /**< Mode I2C1 for SMU_PPUFS */
8671 #define _SMU_PPUFS_PERIPHID_IDAC0          0x00000014UL                         /**< Mode IDAC0 for SMU_PPUFS */
8672 #define _SMU_PPUFS_PERIPHID_MSC            0x00000015UL                         /**< Mode MSC for SMU_PPUFS */
8673 #define _SMU_PPUFS_PERIPHID_LCD            0x00000016UL                         /**< Mode LCD for SMU_PPUFS */
8674 #define _SMU_PPUFS_PERIPHID_LDMA           0x00000017UL                         /**< Mode LDMA for SMU_PPUFS */
8675 #define _SMU_PPUFS_PERIPHID_LESENSE        0x00000018UL                         /**< Mode LESENSE for SMU_PPUFS */
8676 #define _SMU_PPUFS_PERIPHID_LETIMER0       0x00000019UL                         /**< Mode LETIMER0 for SMU_PPUFS */
8677 #define _SMU_PPUFS_PERIPHID_LETIMER1       0x0000001AUL                         /**< Mode LETIMER1 for SMU_PPUFS */
8678 #define _SMU_PPUFS_PERIPHID_LEUART0        0x0000001BUL                         /**< Mode LEUART0 for SMU_PPUFS */
8679 #define _SMU_PPUFS_PERIPHID_LEUART1        0x0000001CUL                         /**< Mode LEUART1 for SMU_PPUFS */
8680 #define _SMU_PPUFS_PERIPHID_PCNT0          0x00000020UL                         /**< Mode PCNT0 for SMU_PPUFS */
8681 #define _SMU_PPUFS_PERIPHID_PCNT1          0x00000021UL                         /**< Mode PCNT1 for SMU_PPUFS */
8682 #define _SMU_PPUFS_PERIPHID_PCNT2          0x00000022UL                         /**< Mode PCNT2 for SMU_PPUFS */
8683 #define _SMU_PPUFS_PERIPHID_PDM            0x00000023UL                         /**< Mode PDM for SMU_PPUFS */
8684 #define _SMU_PPUFS_PERIPHID_RMU            0x00000025UL                         /**< Mode RMU for SMU_PPUFS */
8685 #define _SMU_PPUFS_PERIPHID_RTC            0x00000026UL                         /**< Mode RTC for SMU_PPUFS */
8686 #define _SMU_PPUFS_PERIPHID_RTCC           0x00000027UL                         /**< Mode RTCC for SMU_PPUFS */
8687 #define _SMU_PPUFS_PERIPHID_SMU            0x00000029UL                         /**< Mode SMU for SMU_PPUFS */
8688 #define _SMU_PPUFS_PERIPHID_TIMER0         0x0000002AUL                         /**< Mode TIMER0 for SMU_PPUFS */
8689 #define _SMU_PPUFS_PERIPHID_TIMER1         0x0000002BUL                         /**< Mode TIMER1 for SMU_PPUFS */
8690 #define _SMU_PPUFS_PERIPHID_TIMER2         0x0000002CUL                         /**< Mode TIMER2 for SMU_PPUFS */
8691 #define _SMU_PPUFS_PERIPHID_TIMER3         0x0000002DUL                         /**< Mode TIMER3 for SMU_PPUFS */
8692 #define _SMU_PPUFS_PERIPHID_TRNG0          0x0000002EUL                         /**< Mode TRNG0 for SMU_PPUFS */
8693 #define _SMU_PPUFS_PERIPHID_UART0          0x0000002FUL                         /**< Mode UART0 for SMU_PPUFS */
8694 #define _SMU_PPUFS_PERIPHID_UART1          0x00000030UL                         /**< Mode UART1 for SMU_PPUFS */
8695 #define _SMU_PPUFS_PERIPHID_USART0         0x00000031UL                         /**< Mode USART0 for SMU_PPUFS */
8696 #define _SMU_PPUFS_PERIPHID_USART1         0x00000032UL                         /**< Mode USART1 for SMU_PPUFS */
8697 #define _SMU_PPUFS_PERIPHID_USART2         0x00000033UL                         /**< Mode USART2 for SMU_PPUFS */
8698 #define _SMU_PPUFS_PERIPHID_USART3         0x00000034UL                         /**< Mode USART3 for SMU_PPUFS */
8699 #define _SMU_PPUFS_PERIPHID_USART4         0x00000035UL                         /**< Mode USART4 for SMU_PPUFS */
8700 #define _SMU_PPUFS_PERIPHID_WDOG0          0x00000037UL                         /**< Mode WDOG0 for SMU_PPUFS */
8701 #define _SMU_PPUFS_PERIPHID_WDOG1          0x00000038UL                         /**< Mode WDOG1 for SMU_PPUFS */
8702 #define _SMU_PPUFS_PERIPHID_WTIMER0        0x00000039UL                         /**< Mode WTIMER0 for SMU_PPUFS */
8703 #define _SMU_PPUFS_PERIPHID_WTIMER1        0x0000003AUL                         /**< Mode WTIMER1 for SMU_PPUFS */
8704 #define SMU_PPUFS_PERIPHID_DEFAULT         (_SMU_PPUFS_PERIPHID_DEFAULT << 0)   /**< Shifted mode DEFAULT for SMU_PPUFS */
8705 #define SMU_PPUFS_PERIPHID_ACMP0           (_SMU_PPUFS_PERIPHID_ACMP0 << 0)     /**< Shifted mode ACMP0 for SMU_PPUFS */
8706 #define SMU_PPUFS_PERIPHID_ACMP1           (_SMU_PPUFS_PERIPHID_ACMP1 << 0)     /**< Shifted mode ACMP1 for SMU_PPUFS */
8707 #define SMU_PPUFS_PERIPHID_ACMP2           (_SMU_PPUFS_PERIPHID_ACMP2 << 0)     /**< Shifted mode ACMP2 for SMU_PPUFS */
8708 #define SMU_PPUFS_PERIPHID_ADC0            (_SMU_PPUFS_PERIPHID_ADC0 << 0)      /**< Shifted mode ADC0 for SMU_PPUFS */
8709 #define SMU_PPUFS_PERIPHID_ADC1            (_SMU_PPUFS_PERIPHID_ADC1 << 0)      /**< Shifted mode ADC1 for SMU_PPUFS */
8710 #define SMU_PPUFS_PERIPHID_CAN0            (_SMU_PPUFS_PERIPHID_CAN0 << 0)      /**< Shifted mode CAN0 for SMU_PPUFS */
8711 #define SMU_PPUFS_PERIPHID_CAN1            (_SMU_PPUFS_PERIPHID_CAN1 << 0)      /**< Shifted mode CAN1 for SMU_PPUFS */
8712 #define SMU_PPUFS_PERIPHID_CMU             (_SMU_PPUFS_PERIPHID_CMU << 0)       /**< Shifted mode CMU for SMU_PPUFS */
8713 #define SMU_PPUFS_PERIPHID_CRYOTIMER       (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */
8714 #define SMU_PPUFS_PERIPHID_CRYPTO0         (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0)   /**< Shifted mode CRYPTO0 for SMU_PPUFS */
8715 #define SMU_PPUFS_PERIPHID_CSEN            (_SMU_PPUFS_PERIPHID_CSEN << 0)      /**< Shifted mode CSEN for SMU_PPUFS */
8716 #define SMU_PPUFS_PERIPHID_VDAC0           (_SMU_PPUFS_PERIPHID_VDAC0 << 0)     /**< Shifted mode VDAC0 for SMU_PPUFS */
8717 #define SMU_PPUFS_PERIPHID_PRS             (_SMU_PPUFS_PERIPHID_PRS << 0)       /**< Shifted mode PRS for SMU_PPUFS */
8718 #define SMU_PPUFS_PERIPHID_EBI             (_SMU_PPUFS_PERIPHID_EBI << 0)       /**< Shifted mode EBI for SMU_PPUFS */
8719 #define SMU_PPUFS_PERIPHID_EMU             (_SMU_PPUFS_PERIPHID_EMU << 0)       /**< Shifted mode EMU for SMU_PPUFS */
8720 #define SMU_PPUFS_PERIPHID_FPUEH           (_SMU_PPUFS_PERIPHID_FPUEH << 0)     /**< Shifted mode FPUEH for SMU_PPUFS */
8721 #define SMU_PPUFS_PERIPHID_GPCRC           (_SMU_PPUFS_PERIPHID_GPCRC << 0)     /**< Shifted mode GPCRC for SMU_PPUFS */
8722 #define SMU_PPUFS_PERIPHID_GPIO            (_SMU_PPUFS_PERIPHID_GPIO << 0)      /**< Shifted mode GPIO for SMU_PPUFS */
8723 #define SMU_PPUFS_PERIPHID_I2C0            (_SMU_PPUFS_PERIPHID_I2C0 << 0)      /**< Shifted mode I2C0 for SMU_PPUFS */
8724 #define SMU_PPUFS_PERIPHID_I2C1            (_SMU_PPUFS_PERIPHID_I2C1 << 0)      /**< Shifted mode I2C1 for SMU_PPUFS */
8725 #define SMU_PPUFS_PERIPHID_IDAC0           (_SMU_PPUFS_PERIPHID_IDAC0 << 0)     /**< Shifted mode IDAC0 for SMU_PPUFS */
8726 #define SMU_PPUFS_PERIPHID_MSC             (_SMU_PPUFS_PERIPHID_MSC << 0)       /**< Shifted mode MSC for SMU_PPUFS */
8727 #define SMU_PPUFS_PERIPHID_LCD             (_SMU_PPUFS_PERIPHID_LCD << 0)       /**< Shifted mode LCD for SMU_PPUFS */
8728 #define SMU_PPUFS_PERIPHID_LDMA            (_SMU_PPUFS_PERIPHID_LDMA << 0)      /**< Shifted mode LDMA for SMU_PPUFS */
8729 #define SMU_PPUFS_PERIPHID_LESENSE         (_SMU_PPUFS_PERIPHID_LESENSE << 0)   /**< Shifted mode LESENSE for SMU_PPUFS */
8730 #define SMU_PPUFS_PERIPHID_LETIMER0        (_SMU_PPUFS_PERIPHID_LETIMER0 << 0)  /**< Shifted mode LETIMER0 for SMU_PPUFS */
8731 #define SMU_PPUFS_PERIPHID_LETIMER1        (_SMU_PPUFS_PERIPHID_LETIMER1 << 0)  /**< Shifted mode LETIMER1 for SMU_PPUFS */
8732 #define SMU_PPUFS_PERIPHID_LEUART0         (_SMU_PPUFS_PERIPHID_LEUART0 << 0)   /**< Shifted mode LEUART0 for SMU_PPUFS */
8733 #define SMU_PPUFS_PERIPHID_LEUART1         (_SMU_PPUFS_PERIPHID_LEUART1 << 0)   /**< Shifted mode LEUART1 for SMU_PPUFS */
8734 #define SMU_PPUFS_PERIPHID_PCNT0           (_SMU_PPUFS_PERIPHID_PCNT0 << 0)     /**< Shifted mode PCNT0 for SMU_PPUFS */
8735 #define SMU_PPUFS_PERIPHID_PCNT1           (_SMU_PPUFS_PERIPHID_PCNT1 << 0)     /**< Shifted mode PCNT1 for SMU_PPUFS */
8736 #define SMU_PPUFS_PERIPHID_PCNT2           (_SMU_PPUFS_PERIPHID_PCNT2 << 0)     /**< Shifted mode PCNT2 for SMU_PPUFS */
8737 #define SMU_PPUFS_PERIPHID_PDM             (_SMU_PPUFS_PERIPHID_PDM << 0)       /**< Shifted mode PDM for SMU_PPUFS */
8738 #define SMU_PPUFS_PERIPHID_RMU             (_SMU_PPUFS_PERIPHID_RMU << 0)       /**< Shifted mode RMU for SMU_PPUFS */
8739 #define SMU_PPUFS_PERIPHID_RTC             (_SMU_PPUFS_PERIPHID_RTC << 0)       /**< Shifted mode RTC for SMU_PPUFS */
8740 #define SMU_PPUFS_PERIPHID_RTCC            (_SMU_PPUFS_PERIPHID_RTCC << 0)      /**< Shifted mode RTCC for SMU_PPUFS */
8741 #define SMU_PPUFS_PERIPHID_SMU             (_SMU_PPUFS_PERIPHID_SMU << 0)       /**< Shifted mode SMU for SMU_PPUFS */
8742 #define SMU_PPUFS_PERIPHID_TIMER0          (_SMU_PPUFS_PERIPHID_TIMER0 << 0)    /**< Shifted mode TIMER0 for SMU_PPUFS */
8743 #define SMU_PPUFS_PERIPHID_TIMER1          (_SMU_PPUFS_PERIPHID_TIMER1 << 0)    /**< Shifted mode TIMER1 for SMU_PPUFS */
8744 #define SMU_PPUFS_PERIPHID_TIMER2          (_SMU_PPUFS_PERIPHID_TIMER2 << 0)    /**< Shifted mode TIMER2 for SMU_PPUFS */
8745 #define SMU_PPUFS_PERIPHID_TIMER3          (_SMU_PPUFS_PERIPHID_TIMER3 << 0)    /**< Shifted mode TIMER3 for SMU_PPUFS */
8746 #define SMU_PPUFS_PERIPHID_TRNG0           (_SMU_PPUFS_PERIPHID_TRNG0 << 0)     /**< Shifted mode TRNG0 for SMU_PPUFS */
8747 #define SMU_PPUFS_PERIPHID_UART0           (_SMU_PPUFS_PERIPHID_UART0 << 0)     /**< Shifted mode UART0 for SMU_PPUFS */
8748 #define SMU_PPUFS_PERIPHID_UART1           (_SMU_PPUFS_PERIPHID_UART1 << 0)     /**< Shifted mode UART1 for SMU_PPUFS */
8749 #define SMU_PPUFS_PERIPHID_USART0          (_SMU_PPUFS_PERIPHID_USART0 << 0)    /**< Shifted mode USART0 for SMU_PPUFS */
8750 #define SMU_PPUFS_PERIPHID_USART1          (_SMU_PPUFS_PERIPHID_USART1 << 0)    /**< Shifted mode USART1 for SMU_PPUFS */
8751 #define SMU_PPUFS_PERIPHID_USART2          (_SMU_PPUFS_PERIPHID_USART2 << 0)    /**< Shifted mode USART2 for SMU_PPUFS */
8752 #define SMU_PPUFS_PERIPHID_USART3          (_SMU_PPUFS_PERIPHID_USART3 << 0)    /**< Shifted mode USART3 for SMU_PPUFS */
8753 #define SMU_PPUFS_PERIPHID_USART4          (_SMU_PPUFS_PERIPHID_USART4 << 0)    /**< Shifted mode USART4 for SMU_PPUFS */
8754 #define SMU_PPUFS_PERIPHID_WDOG0           (_SMU_PPUFS_PERIPHID_WDOG0 << 0)     /**< Shifted mode WDOG0 for SMU_PPUFS */
8755 #define SMU_PPUFS_PERIPHID_WDOG1           (_SMU_PPUFS_PERIPHID_WDOG1 << 0)     /**< Shifted mode WDOG1 for SMU_PPUFS */
8756 #define SMU_PPUFS_PERIPHID_WTIMER0         (_SMU_PPUFS_PERIPHID_WTIMER0 << 0)   /**< Shifted mode WTIMER0 for SMU_PPUFS */
8757 #define SMU_PPUFS_PERIPHID_WTIMER1         (_SMU_PPUFS_PERIPHID_WTIMER1 << 0)   /**< Shifted mode WTIMER1 for SMU_PPUFS */
8758 
8759 /** @} */
8760 /** @} End of group EFM32GG12B310F1024GQ100_SMU */
8761 
8762 /***************************************************************************//**
8763  * @defgroup EFM32GG12B310F1024GQ100_UNLOCK Unlock Codes
8764  * @{
8765  ******************************************************************************/
8766 #define MSC_UNLOCK_CODE      0x1B71 /**< MSC unlock code */
8767 #define EMU_UNLOCK_CODE      0xADE8 /**< EMU unlock code */
8768 #define RMU_UNLOCK_CODE      0xE084 /**< RMU unlock code */
8769 #define CMU_UNLOCK_CODE      0x580E /**< CMU unlock code */
8770 #define GPIO_UNLOCK_CODE     0xA534 /**< GPIO unlock code */
8771 #define TIMER_UNLOCK_CODE    0xCE80 /**< TIMER unlock code */
8772 #define RTCC_UNLOCK_CODE     0xAEE8 /**< RTCC unlock code */
8773 
8774 /** @} End of group EFM32GG12B310F1024GQ100_UNLOCK */
8775 
8776 /** @} End of group EFM32GG12B310F1024GQ100_BitFields */
8777 
8778 /***************************************************************************//**
8779  * @addtogroup EFM32GG12B310F1024GQ100_Alternate_Function Alternate Function
8780  * @{
8781  * @defgroup EFM32GG12B310F1024GQ100_AF_Ports Alternate Function Ports
8782  * @{
8783  ******************************************************************************/
8784 
8785 #define AF_CMU_CLK0_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? -1 : (i) == 4 ? 5 : (i) == 5 ? 0 :  -1)                                /**< Port number for AF_CMU_CLK0 location number i */
8786 #define AF_CMU_CLK1_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? -1 : (i) == 4 ? 5 : (i) == 5 ? 1 :  -1)                                /**< Port number for AF_CMU_CLK1 location number i */
8787 #define AF_CMU_CLK2_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? -1 : (i) == 4 ? 0 : (i) == 5 ? 3 :  -1)                                /**< Port number for AF_CMU_CLK2 location number i */
8788 #define AF_CMU_CLKI0_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_CMU_CLKI0 location number i */
8789 #define AF_CMU_DIGEXTCLK_PORT(i)     ((i) == 0 ? 1 :  -1)                                                                                                            /**< Port number for AF_CMU_DIGEXTCLK location number i */
8790 #define AF_CMU_IOPOVR_PORT(i)        ((i) == 0 ? 1 :  -1)                                                                                                            /**< Port number for AF_CMU_IOPOVR location number i */
8791 #define AF_CMU_IONOVR_PORT(i)        ((i) == 0 ? 1 :  -1)                                                                                                            /**< Port number for AF_CMU_IONOVR location number i */
8792 #define AF_LESENSE_CH0_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH0 location number i */
8793 #define AF_LESENSE_CH1_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH1 location number i */
8794 #define AF_LESENSE_CH2_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH2 location number i */
8795 #define AF_LESENSE_CH3_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH3 location number i */
8796 #define AF_LESENSE_CH4_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH4 location number i */
8797 #define AF_LESENSE_CH5_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH5 location number i */
8798 #define AF_LESENSE_CH6_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH6 location number i */
8799 #define AF_LESENSE_CH7_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH7 location number i */
8800 #define AF_LESENSE_CH8_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH8 location number i */
8801 #define AF_LESENSE_CH9_PORT(i)       ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH9 location number i */
8802 #define AF_LESENSE_CH10_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH10 location number i */
8803 #define AF_LESENSE_CH11_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH11 location number i */
8804 #define AF_LESENSE_CH12_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH12 location number i */
8805 #define AF_LESENSE_CH13_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH13 location number i */
8806 #define AF_LESENSE_CH14_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH14 location number i */
8807 #define AF_LESENSE_CH15_PORT(i)      ((i) == 0 ? 2 :  -1)                                                                                                            /**< Port number for AF_LESENSE_CH15 location number i */
8808 #define AF_LESENSE_ALTEX0_PORT(i)    ((i) == 0 ? 3 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX0 location number i */
8809 #define AF_LESENSE_ALTEX1_PORT(i)    ((i) == 0 ? 3 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX1 location number i */
8810 #define AF_LESENSE_ALTEX2_PORT(i)    ((i) == 0 ? 0 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX2 location number i */
8811 #define AF_LESENSE_ALTEX3_PORT(i)    ((i) == 0 ? 0 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX3 location number i */
8812 #define AF_LESENSE_ALTEX4_PORT(i)    ((i) == 0 ? 0 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX4 location number i */
8813 #define AF_LESENSE_ALTEX5_PORT(i)    ((i) == 0 ? 4 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX5 location number i */
8814 #define AF_LESENSE_ALTEX6_PORT(i)    ((i) == 0 ? 4 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX6 location number i */
8815 #define AF_LESENSE_ALTEX7_PORT(i)    ((i) == 0 ? 4 :  -1)                                                                                                            /**< Port number for AF_LESENSE_ALTEX7 location number i */
8816 #define AF_EBI_AD00_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD00 location number i */
8817 #define AF_EBI_AD01_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD01 location number i */
8818 #define AF_EBI_AD02_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD02 location number i */
8819 #define AF_EBI_AD03_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD03 location number i */
8820 #define AF_EBI_AD04_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD04 location number i */
8821 #define AF_EBI_AD05_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD05 location number i */
8822 #define AF_EBI_AD06_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 1 :  -1)                                                                                             /**< Port number for AF_EBI_AD06 location number i */
8823 #define AF_EBI_AD07_PORT(i)          ((i) == 0 ? 4 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD07 location number i */
8824 #define AF_EBI_AD08_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD08 location number i */
8825 #define AF_EBI_AD09_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD09 location number i */
8826 #define AF_EBI_AD10_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD10 location number i */
8827 #define AF_EBI_AD11_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD11 location number i */
8828 #define AF_EBI_AD12_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                             /**< Port number for AF_EBI_AD12 location number i */
8829 #define AF_EBI_AD13_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_EBI_AD13 location number i */
8830 #define AF_EBI_AD14_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_EBI_AD14 location number i */
8831 #define AF_EBI_AD15_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 0 :  -1)                                                                                             /**< Port number for AF_EBI_AD15 location number i */
8832 #define AF_EBI_CS0_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_EBI_CS0 location number i */
8833 #define AF_EBI_CS1_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_EBI_CS1 location number i */
8834 #define AF_EBI_CS2_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_EBI_CS2 location number i */
8835 #define AF_EBI_CS3_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_EBI_CS3 location number i */
8836 #define AF_EBI_ARDY_PORT(i)          ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_ARDY location number i */
8837 #define AF_EBI_ALE_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_EBI_ALE location number i */
8838 #define AF_EBI_WEn_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_WEn location number i */
8839 #define AF_EBI_REn_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_REn location number i */
8840 #define AF_EBI_BL0_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_BL0 location number i */
8841 #define AF_EBI_BL1_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_BL1 location number i */
8842 #define AF_EBI_NANDWEn_PORT(i)       ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_NANDWEn location number i */
8843 #define AF_EBI_NANDREn_PORT(i)       ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_EBI_NANDREn location number i */
8844 #define AF_EBI_A00_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                              /**< Port number for AF_EBI_A00 location number i */
8845 #define AF_EBI_A01_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A01 location number i */
8846 #define AF_EBI_A02_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A02 location number i */
8847 #define AF_EBI_A03_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A03 location number i */
8848 #define AF_EBI_A04_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A04 location number i */
8849 #define AF_EBI_A05_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A05 location number i */
8850 #define AF_EBI_A06_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A06 location number i */
8851 #define AF_EBI_A07_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A07 location number i */
8852 #define AF_EBI_A08_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_A08 location number i */
8853 #define AF_EBI_A09_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                              /**< Port number for AF_EBI_A09 location number i */
8854 #define AF_EBI_A10_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                              /**< Port number for AF_EBI_A10 location number i */
8855 #define AF_EBI_A11_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                              /**< Port number for AF_EBI_A11 location number i */
8856 #define AF_EBI_A12_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                              /**< Port number for AF_EBI_A12 location number i */
8857 #define AF_EBI_A13_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A13 location number i */
8858 #define AF_EBI_A14_PORT(i)           ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A14 location number i */
8859 #define AF_EBI_A15_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A15 location number i */
8860 #define AF_EBI_A16_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A16 location number i */
8861 #define AF_EBI_A17_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A17 location number i */
8862 #define AF_EBI_A18_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A18 location number i */
8863 #define AF_EBI_A19_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A19 location number i */
8864 #define AF_EBI_A20_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Port number for AF_EBI_A20 location number i */
8865 #define AF_EBI_A21_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                              /**< Port number for AF_EBI_A21 location number i */
8866 #define AF_EBI_A22_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                              /**< Port number for AF_EBI_A22 location number i */
8867 #define AF_EBI_A23_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                              /**< Port number for AF_EBI_A23 location number i */
8868 #define AF_EBI_A24_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                              /**< Port number for AF_EBI_A24 location number i */
8869 #define AF_EBI_A25_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                              /**< Port number for AF_EBI_A25 location number i */
8870 #define AF_EBI_A26_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                              /**< Port number for AF_EBI_A26 location number i */
8871 #define AF_EBI_A27_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                              /**< Port number for AF_EBI_A27 location number i */
8872 #define AF_EBI_CSTFT_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_CSTFT location number i */
8873 #define AF_EBI_DCLK_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_DCLK location number i */
8874 #define AF_EBI_DTEN_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_DTEN location number i */
8875 #define AF_EBI_VSNC_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_VSNC location number i */
8876 #define AF_EBI_HSNC_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                              /**< Port number for AF_EBI_HSNC location number i */
8877 #define AF_PDM_CLK_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 1 : (i) == 4 ? 3 :  -1)                                                /**< Port number for AF_PDM_CLK location number i */
8878 #define AF_PDM_DAT0_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 1 : (i) == 4 ? 3 :  -1)                                                /**< Port number for AF_PDM_DAT0 location number i */
8879 #define AF_PDM_DAT1_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 1 : (i) == 4 ? 3 :  -1)                                                /**< Port number for AF_PDM_DAT1 location number i */
8880 #define AF_PDM_DAT2_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 5 : (i) == 3 ? 1 : (i) == 4 ? 3 :  -1)                                                /**< Port number for AF_PDM_DAT2 location number i */
8881 #define AF_PDM_DAT3_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 3 :  -1)                                                /**< Port number for AF_PDM_DAT3 location number i */
8882 #define AF_PRS_CH0_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 :  -1)                                                               /**< Port number for AF_PRS_CH0 location number i */
8883 #define AF_PRS_CH1_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 :  -1)                                                               /**< Port number for AF_PRS_CH1 location number i */
8884 #define AF_PRS_CH2_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 :  -1)                                                               /**< Port number for AF_PRS_CH2 location number i */
8885 #define AF_PRS_CH3_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 :  -1)                                                               /**< Port number for AF_PRS_CH3 location number i */
8886 #define AF_PRS_CH4_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 :  -1)                                                                              /**< Port number for AF_PRS_CH4 location number i */
8887 #define AF_PRS_CH5_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_PRS_CH5 location number i */
8888 #define AF_PRS_CH6_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_PRS_CH6 location number i */
8889 #define AF_PRS_CH7_PORT(i)           ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_PRS_CH7 location number i */
8890 #define AF_PRS_CH8_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_PRS_CH8 location number i */
8891 #define AF_PRS_CH9_PORT(i)           ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 :  -1)                                                                              /**< Port number for AF_PRS_CH9 location number i */
8892 #define AF_PRS_CH10_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_PRS_CH10 location number i */
8893 #define AF_PRS_CH11_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_PRS_CH11 location number i */
8894 #define AF_PRS_CH12_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_PRS_CH12 location number i */
8895 #define AF_PRS_CH13_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_PRS_CH13 location number i */
8896 #define AF_PRS_CH14_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_PRS_CH14 location number i */
8897 #define AF_PRS_CH15_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 :  -1)                                                                              /**< Port number for AF_PRS_CH15 location number i */
8898 #define AF_CAN0_RX_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? -1 : (i) == 5 ? 3 : (i) == 6 ? 4 :  -1)                 /**< Port number for AF_CAN0_RX location number i */
8899 #define AF_CAN0_TX_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? -1 : (i) == 5 ? 3 : (i) == 6 ? 4 :  -1)                 /**< Port number for AF_CAN0_TX location number i */
8900 #define AF_CAN1_RX_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 :  -1)                                 /**< Port number for AF_CAN1_RX location number i */
8901 #define AF_CAN1_TX_PORT(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 :  -1)                                 /**< Port number for AF_CAN1_TX location number i */
8902 #define AF_TIMER0_CC0_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 :  -1)   /**< Port number for AF_TIMER0_CC0 location number i */
8903 #define AF_TIMER0_CC1_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 :  -1)   /**< Port number for AF_TIMER0_CC1 location number i */
8904 #define AF_TIMER0_CC2_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 :  -1)   /**< Port number for AF_TIMER0_CC2 location number i */
8905 #define AF_TIMER0_CC3_PORT(i)        (-1)                                                                                                                            /**< Port number for AF_TIMER0_CC3 location number i */
8906 #define AF_TIMER0_CDTI0_PORT(i)      ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 :  -1)                                                /**< Port number for AF_TIMER0_CDTI0 location number i */
8907 #define AF_TIMER0_CDTI1_PORT(i)      ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 :  -1)                                                /**< Port number for AF_TIMER0_CDTI1 location number i */
8908 #define AF_TIMER0_CDTI2_PORT(i)      ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 :  -1)                                                /**< Port number for AF_TIMER0_CDTI2 location number i */
8909 #define AF_TIMER0_CDTI3_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER0_CDTI3 location number i */
8910 #define AF_TIMER1_CC0_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 :  -1)                  /**< Port number for AF_TIMER1_CC0 location number i */
8911 #define AF_TIMER1_CC1_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 :  -1)                  /**< Port number for AF_TIMER1_CC1 location number i */
8912 #define AF_TIMER1_CC2_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_TIMER1_CC2 location number i */
8913 #define AF_TIMER1_CC3_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 :  -1)                  /**< Port number for AF_TIMER1_CC3 location number i */
8914 #define AF_TIMER1_CDTI0_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER1_CDTI0 location number i */
8915 #define AF_TIMER1_CDTI1_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER1_CDTI1 location number i */
8916 #define AF_TIMER1_CDTI2_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER1_CDTI2 location number i */
8917 #define AF_TIMER1_CDTI3_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER1_CDTI3 location number i */
8918 #define AF_TIMER2_CC0_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_TIMER2_CC0 location number i */
8919 #define AF_TIMER2_CC1_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_TIMER2_CC1 location number i */
8920 #define AF_TIMER2_CC2_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_TIMER2_CC2 location number i */
8921 #define AF_TIMER2_CC3_PORT(i)        (-1)                                                                                                                            /**< Port number for AF_TIMER2_CC3 location number i */
8922 #define AF_TIMER2_CDTI0_PORT(i)      ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_TIMER2_CDTI0 location number i */
8923 #define AF_TIMER2_CDTI1_PORT(i)      ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_TIMER2_CDTI1 location number i */
8924 #define AF_TIMER2_CDTI2_PORT(i)      ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_TIMER2_CDTI2 location number i */
8925 #define AF_TIMER2_CDTI3_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER2_CDTI3 location number i */
8926 #define AF_TIMER3_CC0_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 :  -1)   /**< Port number for AF_TIMER3_CC0 location number i */
8927 #define AF_TIMER3_CC1_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_TIMER3_CC1 location number i */
8928 #define AF_TIMER3_CC2_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_TIMER3_CC2 location number i */
8929 #define AF_TIMER3_CC3_PORT(i)        (-1)                                                                                                                            /**< Port number for AF_TIMER3_CC3 location number i */
8930 #define AF_TIMER3_CDTI0_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER3_CDTI0 location number i */
8931 #define AF_TIMER3_CDTI1_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER3_CDTI1 location number i */
8932 #define AF_TIMER3_CDTI2_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER3_CDTI2 location number i */
8933 #define AF_TIMER3_CDTI3_PORT(i)      (-1)                                                                                                                            /**< Port number for AF_TIMER3_CDTI3 location number i */
8934 #define AF_WTIMER0_CC0_PORT(i)       ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 :  -1) /**< Port number for AF_WTIMER0_CC0 location number i */
8935 #define AF_WTIMER0_CC1_PORT(i)       ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 :  -1) /**< Port number for AF_WTIMER0_CC1 location number i */
8936 #define AF_WTIMER0_CC2_PORT(i)       ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 :  -1) /**< Port number for AF_WTIMER0_CC2 location number i */
8937 #define AF_WTIMER0_CC3_PORT(i)       (-1)                                                                                                                            /**< Port number for AF_WTIMER0_CC3 location number i */
8938 #define AF_WTIMER0_CDTI0_PORT(i)     ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? -1 : (i) == 4 ? 3 :  -1)                                               /**< Port number for AF_WTIMER0_CDTI0 location number i */
8939 #define AF_WTIMER0_CDTI1_PORT(i)     ((i) == 0 ? 4 : (i) == 1 ? -1 : (i) == 2 ? 0 : (i) == 3 ? -1 : (i) == 4 ? 3 :  -1)                                              /**< Port number for AF_WTIMER0_CDTI1 location number i */
8940 #define AF_WTIMER0_CDTI2_PORT(i)     ((i) == 0 ? 4 : (i) == 1 ? -1 : (i) == 2 ? 0 : (i) == 3 ? -1 : (i) == 4 ? 3 :  -1)                                              /**< Port number for AF_WTIMER0_CDTI2 location number i */
8941 #define AF_WTIMER0_CDTI3_PORT(i)     (-1)                                                                                                                            /**< Port number for AF_WTIMER0_CDTI3 location number i */
8942 #define AF_WTIMER1_CC0_PORT(i)       ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 :  -1)                                 /**< Port number for AF_WTIMER1_CC0 location number i */
8943 #define AF_WTIMER1_CC1_PORT(i)       ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_WTIMER1_CC1 location number i */
8944 #define AF_WTIMER1_CC2_PORT(i)       ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_WTIMER1_CC2 location number i */
8945 #define AF_WTIMER1_CC3_PORT(i)       ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_WTIMER1_CC3 location number i */
8946 #define AF_WTIMER1_CDTI0_PORT(i)     (-1)                                                                                                                            /**< Port number for AF_WTIMER1_CDTI0 location number i */
8947 #define AF_WTIMER1_CDTI1_PORT(i)     (-1)                                                                                                                            /**< Port number for AF_WTIMER1_CDTI1 location number i */
8948 #define AF_WTIMER1_CDTI2_PORT(i)     (-1)                                                                                                                            /**< Port number for AF_WTIMER1_CDTI2 location number i */
8949 #define AF_WTIMER1_CDTI3_PORT(i)     (-1)                                                                                                                            /**< Port number for AF_WTIMER1_CDTI3 location number i */
8950 #define AF_USART0_TX_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_USART0_TX location number i */
8951 #define AF_USART0_RX_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_USART0_RX location number i */
8952 #define AF_USART0_CLK_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 :  -1)                                 /**< Port number for AF_USART0_CLK location number i */
8953 #define AF_USART0_CS_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 :  -1)                                 /**< Port number for AF_USART0_CS location number i */
8954 #define AF_USART0_CTS_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 :  -1)                                 /**< Port number for AF_USART0_CTS location number i */
8955 #define AF_USART0_RTS_PORT(i)        ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 :  -1)                                 /**< Port number for AF_USART0_RTS location number i */
8956 #define AF_USART1_TX_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 :  -1)                  /**< Port number for AF_USART1_TX location number i */
8957 #define AF_USART1_RX_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 :  -1)                  /**< Port number for AF_USART1_RX location number i */
8958 #define AF_USART1_CLK_PORT(i)        ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 :  -1)                  /**< Port number for AF_USART1_CLK location number i */
8959 #define AF_USART1_CS_PORT(i)         ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 :  -1)                  /**< Port number for AF_USART1_CS location number i */
8960 #define AF_USART1_CTS_PORT(i)        ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 :  -1)                                 /**< Port number for AF_USART1_CTS location number i */
8961 #define AF_USART1_RTS_PORT(i)        ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 :  -1)                                 /**< Port number for AF_USART1_RTS location number i */
8962 #define AF_USART2_TX_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_USART2_TX location number i */
8963 #define AF_USART2_RX_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_USART2_RX location number i */
8964 #define AF_USART2_CLK_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_USART2_CLK location number i */
8965 #define AF_USART2_CS_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 :  -1)                                 /**< Port number for AF_USART2_CS location number i */
8966 #define AF_USART2_CTS_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 :  -1)                                 /**< Port number for AF_USART2_CTS location number i */
8967 #define AF_USART2_RTS_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 :  -1)                                 /**< Port number for AF_USART2_RTS location number i */
8968 #define AF_USART3_TX_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 :  -1)                                                                              /**< Port number for AF_USART3_TX location number i */
8969 #define AF_USART3_RX_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 :  -1)                                                                              /**< Port number for AF_USART3_RX location number i */
8970 #define AF_USART3_CLK_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_USART3_CLK location number i */
8971 #define AF_USART3_CS_PORT(i)         ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 :  -1)                                                               /**< Port number for AF_USART3_CS location number i */
8972 #define AF_USART3_CTS_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 :  -1)                                                                              /**< Port number for AF_USART3_CTS location number i */
8973 #define AF_USART3_RTS_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 :  -1)                                                               /**< Port number for AF_USART3_RTS location number i */
8974 #define AF_USART4_TX_PORT(i)         ((i) == 0 ? 1 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_TX location number i */
8975 #define AF_USART4_RX_PORT(i)         ((i) == 0 ? 1 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_RX location number i */
8976 #define AF_USART4_CLK_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_CLK location number i */
8977 #define AF_USART4_CS_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_CS location number i */
8978 #define AF_USART4_CTS_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_CTS location number i */
8979 #define AF_USART4_RTS_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 3 :  -1)                                                                                             /**< Port number for AF_USART4_RTS location number i */
8980 #define AF_UART0_TX_PORT(i)          ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 :  -1)                  /**< Port number for AF_UART0_TX location number i */
8981 #define AF_UART0_RX_PORT(i)          ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 :  -1)                  /**< Port number for AF_UART0_RX location number i */
8982 #define AF_UART0_CLK_PORT(i)         (-1)                                                                                                                            /**< Port number for AF_UART0_CLK location number i */
8983 #define AF_UART0_CS_PORT(i)          (-1)                                                                                                                            /**< Port number for AF_UART0_CS location number i */
8984 #define AF_UART0_CTS_PORT(i)         ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 :  -1)                                 /**< Port number for AF_UART0_CTS location number i */
8985 #define AF_UART0_RTS_PORT(i)         ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 :  -1)                                 /**< Port number for AF_UART0_RTS location number i */
8986 #define AF_UART1_TX_PORT(i)          ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_UART1_TX location number i */
8987 #define AF_UART1_RX_PORT(i)          ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_UART1_RX location number i */
8988 #define AF_UART1_CLK_PORT(i)         (-1)                                                                                                                            /**< Port number for AF_UART1_CLK location number i */
8989 #define AF_UART1_CS_PORT(i)          (-1)                                                                                                                            /**< Port number for AF_UART1_CS location number i */
8990 #define AF_UART1_CTS_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 :  -1)                                                /**< Port number for AF_UART1_CTS location number i */
8991 #define AF_UART1_RTS_PORT(i)         ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 :  -1)                                                /**< Port number for AF_UART1_RTS location number i */
8992 #define AF_LEUART0_TX_PORT(i)        ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_LEUART0_TX location number i */
8993 #define AF_LEUART0_RX_PORT(i)        ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 :  -1)                                 /**< Port number for AF_LEUART0_RX location number i */
8994 #define AF_LEUART1_TX_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 :  -1)                                                /**< Port number for AF_LEUART1_TX location number i */
8995 #define AF_LEUART1_RX_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 :  -1)                                                /**< Port number for AF_LEUART1_RX location number i */
8996 #define AF_LETIMER0_OUT0_PORT(i)     ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_LETIMER0_OUT0 location number i */
8997 #define AF_LETIMER0_OUT1_PORT(i)     ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_LETIMER0_OUT1 location number i */
8998 #define AF_LETIMER1_OUT0_PORT(i)     ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 :  -1)                                 /**< Port number for AF_LETIMER1_OUT0 location number i */
8999 #define AF_LETIMER1_OUT1_PORT(i)     ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 :  -1)                                 /**< Port number for AF_LETIMER1_OUT1 location number i */
9000 #define AF_PCNT0_S0IN_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_PCNT0_S0IN location number i */
9001 #define AF_PCNT0_S1IN_PORT(i)        ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_PCNT0_S1IN location number i */
9002 #define AF_PCNT1_S0IN_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 :  -1)                  /**< Port number for AF_PCNT1_S0IN location number i */
9003 #define AF_PCNT1_S1IN_PORT(i)        ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 :  -1)                  /**< Port number for AF_PCNT1_S1IN location number i */
9004 #define AF_PCNT2_S0IN_PORT(i)        ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 :  -1)                                                /**< Port number for AF_PCNT2_S0IN location number i */
9005 #define AF_PCNT2_S1IN_PORT(i)        ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 :  -1)                                                /**< Port number for AF_PCNT2_S1IN location number i */
9006 #define AF_I2C0_SDA_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 :  -1)   /**< Port number for AF_I2C0_SDA location number i */
9007 #define AF_I2C0_SCL_PORT(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 :  -1)   /**< Port number for AF_I2C0_SCL location number i */
9008 #define AF_I2C1_SDA_PORT(i)          ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 :  -1)                                                /**< Port number for AF_I2C1_SDA location number i */
9009 #define AF_I2C1_SCL_PORT(i)          ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 :  -1)                                                /**< Port number for AF_I2C1_SCL location number i */
9010 #define AF_ACMP0_OUT_PORT(i)         ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 :  -1)   /**< Port number for AF_ACMP0_OUT location number i */
9011 #define AF_ACMP1_OUT_PORT(i)         ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 :  -1)   /**< Port number for AF_ACMP1_OUT location number i */
9012 #define AF_ACMP2_OUT_PORT(i)         ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 :  -1)                                                                              /**< Port number for AF_ACMP2_OUT location number i */
9013 #define AF_DBG_TDI_PORT(i)           ((i) == 0 ? 5 :  -1)                                                                                                            /**< Port number for AF_DBG_TDI location number i */
9014 #define AF_DBG_TDO_PORT(i)           ((i) == 0 ? 5 :  -1)                                                                                                            /**< Port number for AF_DBG_TDO location number i */
9015 #define AF_DBG_SWV_PORT(i)           ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 :  -1)                                                               /**< Port number for AF_DBG_SWV location number i */
9016 #define AF_DBG_SWDIOTMS_PORT(i)      ((i) == 0 ? 5 :  -1)                                                                                                            /**< Port number for AF_DBG_SWDIOTMS location number i */
9017 #define AF_DBG_SWCLKTCK_PORT(i)      ((i) == 0 ? 5 :  -1)                                                                                                            /**< Port number for AF_DBG_SWCLKTCK location number i */
9018 #define AF_ETM_TCLK_PORT(i)          ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_ETM_TCLK location number i */
9019 #define AF_ETM_TD0_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_ETM_TD0 location number i */
9020 #define AF_ETM_TD1_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_ETM_TD1 location number i */
9021 #define AF_ETM_TD2_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_ETM_TD2 location number i */
9022 #define AF_ETM_TD3_PORT(i)           ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                /**< Port number for AF_ETM_TD3 location number i */
9023 
9024 /** @} */
9025 /** @} End of group EFM32GG12B310F1024GQ100_AF_Ports */
9026 
9027 /***************************************************************************//**
9028  * @addtogroup EFM32GG12B310F1024GQ100_Alternate_Function Alternate Function
9029  * @{
9030  * @defgroup EFM32GG12B310F1024GQ100_AF_Pins Alternate Function Pins
9031  * @{
9032  ******************************************************************************/
9033 
9034 #define AF_CMU_CLK0_PIN(i)          ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? -1 : (i) == 4 ? 2 : (i) == 5 ? 12 :  -1)                                /**< Pin number for AF_CMU_CLK0 location number i */
9035 #define AF_CMU_CLK1_PIN(i)          ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? -1 : (i) == 4 ? 3 : (i) == 5 ? 11 :  -1)                                /**< Pin number for AF_CMU_CLK1 location number i */
9036 #define AF_CMU_CLK2_PIN(i)          ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? -1 : (i) == 4 ? 3 : (i) == 5 ? 10 :  -1)                                 /**< Pin number for AF_CMU_CLK2 location number i */
9037 #define AF_CMU_CLKI0_PIN(i)         ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 :  -1) /**< Pin number for AF_CMU_CLKI0 location number i */
9038 #define AF_CMU_DIGEXTCLK_PIN(i)     ((i) == 0 ? 14 :  -1)                                                                                                             /**< Pin number for AF_CMU_DIGEXTCLK location number i */
9039 #define AF_CMU_IOPOVR_PIN(i)        ((i) == 0 ? 13 :  -1)                                                                                                             /**< Pin number for AF_CMU_IOPOVR location number i */
9040 #define AF_CMU_IONOVR_PIN(i)        ((i) == 0 ? 14 :  -1)                                                                                                             /**< Pin number for AF_CMU_IONOVR location number i */
9041 #define AF_LESENSE_CH0_PIN(i)       ((i) == 0 ? 0 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH0 location number i */
9042 #define AF_LESENSE_CH1_PIN(i)       ((i) == 0 ? 1 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH1 location number i */
9043 #define AF_LESENSE_CH2_PIN(i)       ((i) == 0 ? 2 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH2 location number i */
9044 #define AF_LESENSE_CH3_PIN(i)       ((i) == 0 ? 3 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH3 location number i */
9045 #define AF_LESENSE_CH4_PIN(i)       ((i) == 0 ? 4 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH4 location number i */
9046 #define AF_LESENSE_CH5_PIN(i)       ((i) == 0 ? 5 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH5 location number i */
9047 #define AF_LESENSE_CH6_PIN(i)       ((i) == 0 ? 6 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH6 location number i */
9048 #define AF_LESENSE_CH7_PIN(i)       ((i) == 0 ? 7 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH7 location number i */
9049 #define AF_LESENSE_CH8_PIN(i)       ((i) == 0 ? 8 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH8 location number i */
9050 #define AF_LESENSE_CH9_PIN(i)       ((i) == 0 ? 9 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_CH9 location number i */
9051 #define AF_LESENSE_CH10_PIN(i)      ((i) == 0 ? 10 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH10 location number i */
9052 #define AF_LESENSE_CH11_PIN(i)      ((i) == 0 ? 11 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH11 location number i */
9053 #define AF_LESENSE_CH12_PIN(i)      ((i) == 0 ? 12 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH12 location number i */
9054 #define AF_LESENSE_CH13_PIN(i)      ((i) == 0 ? 13 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH13 location number i */
9055 #define AF_LESENSE_CH14_PIN(i)      ((i) == 0 ? 14 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH14 location number i */
9056 #define AF_LESENSE_CH15_PIN(i)      ((i) == 0 ? 15 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_CH15 location number i */
9057 #define AF_LESENSE_ALTEX0_PIN(i)    ((i) == 0 ? 6 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_ALTEX0 location number i */
9058 #define AF_LESENSE_ALTEX1_PIN(i)    ((i) == 0 ? 7 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_ALTEX1 location number i */
9059 #define AF_LESENSE_ALTEX2_PIN(i)    ((i) == 0 ? 3 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_ALTEX2 location number i */
9060 #define AF_LESENSE_ALTEX3_PIN(i)    ((i) == 0 ? 4 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_ALTEX3 location number i */
9061 #define AF_LESENSE_ALTEX4_PIN(i)    ((i) == 0 ? 5 :  -1)                                                                                                              /**< Pin number for AF_LESENSE_ALTEX4 location number i */
9062 #define AF_LESENSE_ALTEX5_PIN(i)    ((i) == 0 ? 11 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_ALTEX5 location number i */
9063 #define AF_LESENSE_ALTEX6_PIN(i)    ((i) == 0 ? 12 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_ALTEX6 location number i */
9064 #define AF_LESENSE_ALTEX7_PIN(i)    ((i) == 0 ? 13 :  -1)                                                                                                             /**< Pin number for AF_LESENSE_ALTEX7 location number i */
9065 #define AF_EBI_AD00_PIN(i)          ((i) == 0 ? 8 : (i) == 1 ? 0 :  -1)                                                                                               /**< Pin number for AF_EBI_AD00 location number i */
9066 #define AF_EBI_AD01_PIN(i)          ((i) == 0 ? 9 : (i) == 1 ? 1 :  -1)                                                                                               /**< Pin number for AF_EBI_AD01 location number i */
9067 #define AF_EBI_AD02_PIN(i)          ((i) == 0 ? 10 : (i) == 1 ? 2 :  -1)                                                                                              /**< Pin number for AF_EBI_AD02 location number i */
9068 #define AF_EBI_AD03_PIN(i)          ((i) == 0 ? 11 : (i) == 1 ? 3 :  -1)                                                                                              /**< Pin number for AF_EBI_AD03 location number i */
9069 #define AF_EBI_AD04_PIN(i)          ((i) == 0 ? 12 : (i) == 1 ? 4 :  -1)                                                                                              /**< Pin number for AF_EBI_AD04 location number i */
9070 #define AF_EBI_AD05_PIN(i)          ((i) == 0 ? 13 : (i) == 1 ? 5 :  -1)                                                                                              /**< Pin number for AF_EBI_AD05 location number i */
9071 #define AF_EBI_AD06_PIN(i)          ((i) == 0 ? 14 : (i) == 1 ? 6 :  -1)                                                                                              /**< Pin number for AF_EBI_AD06 location number i */
9072 #define AF_EBI_AD07_PIN(i)          ((i) == 0 ? 15 : (i) == 1 ? 0 :  -1)                                                                                              /**< Pin number for AF_EBI_AD07 location number i */
9073 #define AF_EBI_AD08_PIN(i)          ((i) == 0 ? 15 : (i) == 1 ? 1 :  -1)                                                                                              /**< Pin number for AF_EBI_AD08 location number i */
9074 #define AF_EBI_AD09_PIN(i)          ((i) == 0 ? 0 : (i) == 1 ? 2 :  -1)                                                                                               /**< Pin number for AF_EBI_AD09 location number i */
9075 #define AF_EBI_AD10_PIN(i)          ((i) == 0 ? 1 : (i) == 1 ? 3 :  -1)                                                                                               /**< Pin number for AF_EBI_AD10 location number i */
9076 #define AF_EBI_AD11_PIN(i)          ((i) == 0 ? 2 : (i) == 1 ? 4 :  -1)                                                                                               /**< Pin number for AF_EBI_AD11 location number i */
9077 #define AF_EBI_AD12_PIN(i)          ((i) == 0 ? 3 : (i) == 1 ? 5 :  -1)                                                                                               /**< Pin number for AF_EBI_AD12 location number i */
9078 #define AF_EBI_AD13_PIN(i)          ((i) == 0 ? 4 : (i) == 1 ? 7 :  -1)                                                                                               /**< Pin number for AF_EBI_AD13 location number i */
9079 #define AF_EBI_AD14_PIN(i)          ((i) == 0 ? 5 : (i) == 1 ? 8 :  -1)                                                                                               /**< Pin number for AF_EBI_AD14 location number i */
9080 #define AF_EBI_AD15_PIN(i)          ((i) == 0 ? 6 : (i) == 1 ? 9 :  -1)                                                                                               /**< Pin number for AF_EBI_AD15 location number i */
9081 #define AF_EBI_CS0_PIN(i)           ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 :  -1)                                                 /**< Pin number for AF_EBI_CS0 location number i */
9082 #define AF_EBI_CS1_PIN(i)           ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 :  -1)                                                /**< Pin number for AF_EBI_CS1 location number i */
9083 #define AF_EBI_CS2_PIN(i)           ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 :  -1)                                               /**< Pin number for AF_EBI_CS2 location number i */
9084 #define AF_EBI_CS3_PIN(i)           ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 :  -1)                                               /**< Pin number for AF_EBI_CS3 location number i */
9085 #define AF_EBI_ARDY_PIN(i)          ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 :  -1)                               /**< Pin number for AF_EBI_ARDY location number i */
9086 #define AF_EBI_ALE_PIN(i)           ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 :  -1)                                 /**< Pin number for AF_EBI_ALE location number i */
9087 #define AF_EBI_WEn_PIN(i)           ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 :  -1)                                  /**< Pin number for AF_EBI_WEn location number i */
9088 #define AF_EBI_REn_PIN(i)           ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 :  -1)                                 /**< Pin number for AF_EBI_REn location number i */
9089 #define AF_EBI_BL0_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 :  -1)                                  /**< Pin number for AF_EBI_BL0 location number i */
9090 #define AF_EBI_BL1_PIN(i)           ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 :  -1)                                  /**< Pin number for AF_EBI_BL1 location number i */
9091 #define AF_EBI_NANDWEn_PIN(i)       ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 :  -1)                               /**< Pin number for AF_EBI_NANDWEn location number i */
9092 #define AF_EBI_NANDREn_PIN(i)       ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 :  -1)                                /**< Pin number for AF_EBI_NANDREn location number i */
9093 #define AF_EBI_A00_PIN(i)           ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? -1 : (i) == 3 ? 5 :  -1)                                                               /**< Pin number for AF_EBI_A00 location number i */
9094 #define AF_EBI_A01_PIN(i)           ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? -1 : (i) == 3 ? 7 :  -1)                                                              /**< Pin number for AF_EBI_A01 location number i */
9095 #define AF_EBI_A02_PIN(i)           ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? -1 : (i) == 3 ? 8 :  -1)                                                              /**< Pin number for AF_EBI_A02 location number i */
9096 #define AF_EBI_A03_PIN(i)           ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? -1 : (i) == 3 ? 9 :  -1)                                                               /**< Pin number for AF_EBI_A03 location number i */
9097 #define AF_EBI_A04_PIN(i)           ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? -1 : (i) == 3 ? 10 :  -1)                                                              /**< Pin number for AF_EBI_A04 location number i */
9098 #define AF_EBI_A05_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 11 :  -1)                                                               /**< Pin number for AF_EBI_A05 location number i */
9099 #define AF_EBI_A06_PIN(i)           ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 12 :  -1)                                                               /**< Pin number for AF_EBI_A06 location number i */
9100 #define AF_EBI_A07_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 13 :  -1)                                                               /**< Pin number for AF_EBI_A07 location number i */
9101 #define AF_EBI_A08_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 14 :  -1)                                                               /**< Pin number for AF_EBI_A08 location number i */
9102 #define AF_EBI_A09_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 9 :  -1)                                                                /**< Pin number for AF_EBI_A09 location number i */
9103 #define AF_EBI_A10_PIN(i)           ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? -1 : (i) == 3 ? 10 :  -1)                                                               /**< Pin number for AF_EBI_A10 location number i */
9104 #define AF_EBI_A11_PIN(i)           ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? -1 : (i) == 3 ? 11 :  -1)                                                               /**< Pin number for AF_EBI_A11 location number i */
9105 #define AF_EBI_A12_PIN(i)           ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? -1 : (i) == 3 ? 12 :  -1)                                                               /**< Pin number for AF_EBI_A12 location number i */
9106 #define AF_EBI_A13_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                                /**< Pin number for AF_EBI_A13 location number i */
9107 #define AF_EBI_A14_PIN(i)           ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                                /**< Pin number for AF_EBI_A14 location number i */
9108 #define AF_EBI_A15_PIN(i)           ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                                /**< Pin number for AF_EBI_A15 location number i */
9109 #define AF_EBI_A16_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                                /**< Pin number for AF_EBI_A16 location number i */
9110 #define AF_EBI_A17_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                                /**< Pin number for AF_EBI_A17 location number i */
9111 #define AF_EBI_A18_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? -1 : (i) == 3 ? 5 :  -1)                                                                /**< Pin number for AF_EBI_A18 location number i */
9112 #define AF_EBI_A19_PIN(i)           ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? -1 : (i) == 3 ? 6 :  -1)                                                                /**< Pin number for AF_EBI_A19 location number i */
9113 #define AF_EBI_A20_PIN(i)           ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? -1 : (i) == 3 ? 7 :  -1)                                                                /**< Pin number for AF_EBI_A20 location number i */
9114 #define AF_EBI_A21_PIN(i)           ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? -1 : (i) == 3 ? 7 :  -1)                                                                /**< Pin number for AF_EBI_A21 location number i */
9115 #define AF_EBI_A22_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                               /**< Pin number for AF_EBI_A22 location number i */
9116 #define AF_EBI_A23_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? -1 : (i) == 3 ? 5 :  -1)                                                               /**< Pin number for AF_EBI_A23 location number i */
9117 #define AF_EBI_A24_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? -1 : (i) == 3 ? 6 :  -1)                                                                /**< Pin number for AF_EBI_A24 location number i */
9118 #define AF_EBI_A25_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? -1 : (i) == 3 ? 7 :  -1)                                                                /**< Pin number for AF_EBI_A25 location number i */
9119 #define AF_EBI_A26_PIN(i)           ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? -1 : (i) == 3 ? 8 :  -1)                                                                /**< Pin number for AF_EBI_A26 location number i */
9120 #define AF_EBI_A27_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? -1 : (i) == 3 ? 9 :  -1)                                                                /**< Pin number for AF_EBI_A27 location number i */
9121 #define AF_EBI_CSTFT_PIN(i)         ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? -1 : (i) == 3 ? 0 :  -1)                                                                /**< Pin number for AF_EBI_CSTFT location number i */
9122 #define AF_EBI_DCLK_PIN(i)          ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? -1 : (i) == 3 ? 1 :  -1)                                                                /**< Pin number for AF_EBI_DCLK location number i */
9123 #define AF_EBI_DTEN_PIN(i)          ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? -1 : (i) == 3 ? 2 :  -1)                                                                /**< Pin number for AF_EBI_DTEN location number i */
9124 #define AF_EBI_VSNC_PIN(i)          ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? -1 : (i) == 3 ? 3 :  -1)                                                              /**< Pin number for AF_EBI_VSNC location number i */
9125 #define AF_EBI_HSNC_PIN(i)          ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? -1 : (i) == 3 ? 4 :  -1)                                                              /**< Pin number for AF_EBI_HSNC location number i */
9126 #define AF_PDM_CLK_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 0 :  -1)                                                 /**< Pin number for AF_PDM_CLK location number i */
9127 #define AF_PDM_DAT0_PIN(i)          ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 11 : (i) == 4 ? 1 :  -1)                                                 /**< Pin number for AF_PDM_DAT0 location number i */
9128 #define AF_PDM_DAT1_PIN(i)          ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 8 : (i) == 3 ? 10 : (i) == 4 ? 2 :  -1)                                                /**< Pin number for AF_PDM_DAT1 location number i */
9129 #define AF_PDM_DAT2_PIN(i)          ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 9 : (i) == 3 ? 9 : (i) == 4 ? 3 :  -1)                                                 /**< Pin number for AF_PDM_DAT2 location number i */
9130 #define AF_PDM_DAT3_PIN(i)          ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 13 : (i) == 4 ? 4 :  -1)                                                /**< Pin number for AF_PDM_DAT3 location number i */
9131 #define AF_PRS_CH0_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 :  -1)                                                                /**< Pin number for AF_PRS_CH0 location number i */
9132 #define AF_PRS_CH1_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 :  -1)                                                               /**< Pin number for AF_PRS_CH1 location number i */
9133 #define AF_PRS_CH2_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 :  -1)                                                               /**< Pin number for AF_PRS_CH2 location number i */
9134 #define AF_PRS_CH3_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 :  -1)                                                                /**< Pin number for AF_PRS_CH3 location number i */
9135 #define AF_PRS_CH4_PIN(i)           ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 :  -1)                                                                                /**< Pin number for AF_PRS_CH4 location number i */
9136 #define AF_PRS_CH5_PIN(i)           ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 :  -1)                                                                                /**< Pin number for AF_PRS_CH5 location number i */
9137 #define AF_PRS_CH6_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 :  -1)                                                                               /**< Pin number for AF_PRS_CH6 location number i */
9138 #define AF_PRS_CH7_PIN(i)           ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 :  -1)                                                                               /**< Pin number for AF_PRS_CH7 location number i */
9139 #define AF_PRS_CH8_PIN(i)           ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 :  -1)                                                                                /**< Pin number for AF_PRS_CH8 location number i */
9140 #define AF_PRS_CH9_PIN(i)           ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 :  -1)                                                                               /**< Pin number for AF_PRS_CH9 location number i */
9141 #define AF_PRS_CH10_PIN(i)          ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 :  -1)                                                                               /**< Pin number for AF_PRS_CH10 location number i */
9142 #define AF_PRS_CH11_PIN(i)          ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 :  -1)                                                                               /**< Pin number for AF_PRS_CH11 location number i */
9143 #define AF_PRS_CH12_PIN(i)          ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 :  -1)                                                                               /**< Pin number for AF_PRS_CH12 location number i */
9144 #define AF_PRS_CH13_PIN(i)          ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 :  -1)                                                                              /**< Pin number for AF_PRS_CH13 location number i */
9145 #define AF_PRS_CH14_PIN(i)          ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 :  -1)                                                                              /**< Pin number for AF_PRS_CH14 location number i */
9146 #define AF_PRS_CH15_PIN(i)          ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 :  -1)                                                                               /**< Pin number for AF_PRS_CH15 location number i */
9147 #define AF_CAN0_RX_PIN(i)           ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? -1 : (i) == 5 ? 14 : (i) == 6 ? 0 :  -1)                  /**< Pin number for AF_CAN0_RX location number i */
9148 #define AF_CAN0_TX_PIN(i)           ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? -1 : (i) == 5 ? 15 : (i) == 6 ? 1 :  -1)                 /**< Pin number for AF_CAN0_TX location number i */
9149 #define AF_CAN1_RX_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 :  -1)                                 /**< Pin number for AF_CAN1_RX location number i */
9150 #define AF_CAN1_TX_PIN(i)           ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 :  -1)                                /**< Pin number for AF_CAN1_TX location number i */
9151 #define AF_TIMER0_CC0_PIN(i)        ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 :  -1)     /**< Pin number for AF_TIMER0_CC0 location number i */
9152 #define AF_TIMER0_CC1_PIN(i)        ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 :  -1)     /**< Pin number for AF_TIMER0_CC1 location number i */
9153 #define AF_TIMER0_CC2_PIN(i)        ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 :  -1)   /**< Pin number for AF_TIMER0_CC2 location number i */
9154 #define AF_TIMER0_CC3_PIN(i)        (-1)                                                                                                                              /**< Pin number for AF_TIMER0_CC3 location number i */
9155 #define AF_TIMER0_CDTI0_PIN(i)      ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 :  -1)                                                 /**< Pin number for AF_TIMER0_CDTI0 location number i */
9156 #define AF_TIMER0_CDTI1_PIN(i)      ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 :  -1)                                                 /**< Pin number for AF_TIMER0_CDTI1 location number i */
9157 #define AF_TIMER0_CDTI2_PIN(i)      ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 :  -1)                                                /**< Pin number for AF_TIMER0_CDTI2 location number i */
9158 #define AF_TIMER0_CDTI3_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER0_CDTI3 location number i */
9159 #define AF_TIMER1_CC0_PIN(i)        ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 :  -1)                 /**< Pin number for AF_TIMER1_CC0 location number i */
9160 #define AF_TIMER1_CC1_PIN(i)        ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 :  -1)                 /**< Pin number for AF_TIMER1_CC1 location number i */
9161 #define AF_TIMER1_CC2_PIN(i)        ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 :  -1)                               /**< Pin number for AF_TIMER1_CC2 location number i */
9162 #define AF_TIMER1_CC3_PIN(i)        ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 :  -1)               /**< Pin number for AF_TIMER1_CC3 location number i */
9163 #define AF_TIMER1_CDTI0_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER1_CDTI0 location number i */
9164 #define AF_TIMER1_CDTI1_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER1_CDTI1 location number i */
9165 #define AF_TIMER1_CDTI2_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER1_CDTI2 location number i */
9166 #define AF_TIMER1_CDTI3_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER1_CDTI3 location number i */
9167 #define AF_TIMER2_CC0_PIN(i)        ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 :  -1)                                  /**< Pin number for AF_TIMER2_CC0 location number i */
9168 #define AF_TIMER2_CC1_PIN(i)        ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 :  -1)                                 /**< Pin number for AF_TIMER2_CC1 location number i */
9169 #define AF_TIMER2_CC2_PIN(i)        ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 :  -1)                               /**< Pin number for AF_TIMER2_CC2 location number i */
9170 #define AF_TIMER2_CC3_PIN(i)        (-1)                                                                                                                              /**< Pin number for AF_TIMER2_CC3 location number i */
9171 #define AF_TIMER2_CDTI0_PIN(i)      ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 :  -1)                                                                               /**< Pin number for AF_TIMER2_CDTI0 location number i */
9172 #define AF_TIMER2_CDTI1_PIN(i)      ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 :  -1)                                                                              /**< Pin number for AF_TIMER2_CDTI1 location number i */
9173 #define AF_TIMER2_CDTI2_PIN(i)      ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 :  -1)                                                                              /**< Pin number for AF_TIMER2_CDTI2 location number i */
9174 #define AF_TIMER2_CDTI3_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER2_CDTI3 location number i */
9175 #define AF_TIMER3_CC0_PIN(i)        ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 :  -1)   /**< Pin number for AF_TIMER3_CC0 location number i */
9176 #define AF_TIMER3_CC1_PIN(i)        ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 :  -1)  /**< Pin number for AF_TIMER3_CC1 location number i */
9177 #define AF_TIMER3_CC2_PIN(i)        ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 :  -1)   /**< Pin number for AF_TIMER3_CC2 location number i */
9178 #define AF_TIMER3_CC3_PIN(i)        (-1)                                                                                                                              /**< Pin number for AF_TIMER3_CC3 location number i */
9179 #define AF_TIMER3_CDTI0_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER3_CDTI0 location number i */
9180 #define AF_TIMER3_CDTI1_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER3_CDTI1 location number i */
9181 #define AF_TIMER3_CDTI2_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER3_CDTI2 location number i */
9182 #define AF_TIMER3_CDTI3_PIN(i)      (-1)                                                                                                                              /**< Pin number for AF_TIMER3_CDTI3 location number i */
9183 #define AF_WTIMER0_CC0_PIN(i)       ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 :  -1)  /**< Pin number for AF_WTIMER0_CC0 location number i */
9184 #define AF_WTIMER0_CC1_PIN(i)       ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 :  -1)  /**< Pin number for AF_WTIMER0_CC1 location number i */
9185 #define AF_WTIMER0_CC2_PIN(i)       ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? -1 : (i) == 3 ? -1 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 :  -1)  /**< Pin number for AF_WTIMER0_CC2 location number i */
9186 #define AF_WTIMER0_CC3_PIN(i)       (-1)                                                                                                                              /**< Pin number for AF_WTIMER0_CC3 location number i */
9187 #define AF_WTIMER0_CDTI0_PIN(i)     ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? -1 : (i) == 4 ? 4 :  -1)                                              /**< Pin number for AF_WTIMER0_CDTI0 location number i */
9188 #define AF_WTIMER0_CDTI1_PIN(i)     ((i) == 0 ? 11 : (i) == 1 ? -1 : (i) == 2 ? 13 : (i) == 3 ? -1 : (i) == 4 ? 5 :  -1)                                              /**< Pin number for AF_WTIMER0_CDTI1 location number i */
9189 #define AF_WTIMER0_CDTI2_PIN(i)     ((i) == 0 ? 12 : (i) == 1 ? -1 : (i) == 2 ? 14 : (i) == 3 ? -1 : (i) == 4 ? 6 :  -1)                                              /**< Pin number for AF_WTIMER0_CDTI2 location number i */
9190 #define AF_WTIMER0_CDTI3_PIN(i)     (-1)                                                                                                                              /**< Pin number for AF_WTIMER0_CDTI3 location number i */
9191 #define AF_WTIMER1_CC0_PIN(i)       ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 :  -1)                                  /**< Pin number for AF_WTIMER1_CC0 location number i */
9192 #define AF_WTIMER1_CC1_PIN(i)       ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                 /**< Pin number for AF_WTIMER1_CC1 location number i */
9193 #define AF_WTIMER1_CC2_PIN(i)       ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 :  -1)                                                  /**< Pin number for AF_WTIMER1_CC2 location number i */
9194 #define AF_WTIMER1_CC3_PIN(i)       ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 :  -1)                                                  /**< Pin number for AF_WTIMER1_CC3 location number i */
9195 #define AF_WTIMER1_CDTI0_PIN(i)     (-1)                                                                                                                              /**< Pin number for AF_WTIMER1_CDTI0 location number i */
9196 #define AF_WTIMER1_CDTI1_PIN(i)     (-1)                                                                                                                              /**< Pin number for AF_WTIMER1_CDTI1 location number i */
9197 #define AF_WTIMER1_CDTI2_PIN(i)     (-1)                                                                                                                              /**< Pin number for AF_WTIMER1_CDTI2 location number i */
9198 #define AF_WTIMER1_CDTI3_PIN(i)     (-1)                                                                                                                              /**< Pin number for AF_WTIMER1_CDTI3 location number i */
9199 #define AF_USART0_TX_PIN(i)         ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 :  -1)                                /**< Pin number for AF_USART0_TX location number i */
9200 #define AF_USART0_RX_PIN(i)         ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 :  -1)                                /**< Pin number for AF_USART0_RX location number i */
9201 #define AF_USART0_CLK_PIN(i)        ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 :  -1)                               /**< Pin number for AF_USART0_CLK location number i */
9202 #define AF_USART0_CS_PIN(i)         ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 :  -1)                               /**< Pin number for AF_USART0_CS location number i */
9203 #define AF_USART0_CTS_PIN(i)        ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 :  -1)                                /**< Pin number for AF_USART0_CTS location number i */
9204 #define AF_USART0_RTS_PIN(i)        ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 :  -1)                                 /**< Pin number for AF_USART0_RTS location number i */
9205 #define AF_USART1_TX_PIN(i)         ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 :  -1)                   /**< Pin number for AF_USART1_TX location number i */
9206 #define AF_USART1_RX_PIN(i)         ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 :  -1)                    /**< Pin number for AF_USART1_RX location number i */
9207 #define AF_USART1_CLK_PIN(i)        ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 :  -1)                  /**< Pin number for AF_USART1_CLK location number i */
9208 #define AF_USART1_CS_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 :  -1)                   /**< Pin number for AF_USART1_CS location number i */
9209 #define AF_USART1_CTS_PIN(i)        ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 :  -1)                                 /**< Pin number for AF_USART1_CTS location number i */
9210 #define AF_USART1_RTS_PIN(i)        ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 :  -1)                                /**< Pin number for AF_USART1_RTS location number i */
9211 #define AF_USART2_TX_PIN(i)         ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 :  -1)                                  /**< Pin number for AF_USART2_TX location number i */
9212 #define AF_USART2_RX_PIN(i)         ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 :  -1)                                  /**< Pin number for AF_USART2_RX location number i */
9213 #define AF_USART2_CLK_PIN(i)        ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 :  -1)                                  /**< Pin number for AF_USART2_CLK location number i */
9214 #define AF_USART2_CS_PIN(i)         ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 :  -1)                                 /**< Pin number for AF_USART2_CS location number i */
9215 #define AF_USART2_CTS_PIN(i)        ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 :  -1)                               /**< Pin number for AF_USART2_CTS location number i */
9216 #define AF_USART2_RTS_PIN(i)        ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 :  -1)                               /**< Pin number for AF_USART2_RTS location number i */
9217 #define AF_USART3_TX_PIN(i)         ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 :  -1)                                                                                /**< Pin number for AF_USART3_TX location number i */
9218 #define AF_USART3_RX_PIN(i)         ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 :  -1)                                                                                /**< Pin number for AF_USART3_RX location number i */
9219 #define AF_USART3_CLK_PIN(i)        ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 :  -1)                                                                                /**< Pin number for AF_USART3_CLK location number i */
9220 #define AF_USART3_CS_PIN(i)         ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 :  -1)                                                                /**< Pin number for AF_USART3_CS location number i */
9221 #define AF_USART3_CTS_PIN(i)        ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 :  -1)                                                                                /**< Pin number for AF_USART3_CTS location number i */
9222 #define AF_USART3_RTS_PIN(i)        ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 :  -1)                                                               /**< Pin number for AF_USART3_RTS location number i */
9223 #define AF_USART4_TX_PIN(i)         ((i) == 0 ? 7 : (i) == 1 ? 9 :  -1)                                                                                               /**< Pin number for AF_USART4_TX location number i */
9224 #define AF_USART4_RX_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 10 :  -1)                                                                                              /**< Pin number for AF_USART4_RX location number i */
9225 #define AF_USART4_CLK_PIN(i)        ((i) == 0 ? 4 : (i) == 1 ? 11 :  -1)                                                                                              /**< Pin number for AF_USART4_CLK location number i */
9226 #define AF_USART4_CS_PIN(i)         ((i) == 0 ? 5 : (i) == 1 ? 12 :  -1)                                                                                              /**< Pin number for AF_USART4_CS location number i */
9227 #define AF_USART4_CTS_PIN(i)        ((i) == 0 ? 7 : (i) == 1 ? 13 :  -1)                                                                                              /**< Pin number for AF_USART4_CTS location number i */
9228 #define AF_USART4_RTS_PIN(i)        ((i) == 0 ? 8 : (i) == 1 ? 14 :  -1)                                                                                              /**< Pin number for AF_USART4_RTS location number i */
9229 #define AF_UART0_TX_PIN(i)          ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 :  -1)                   /**< Pin number for AF_UART0_TX location number i */
9230 #define AF_UART0_RX_PIN(i)          ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 :  -1)                   /**< Pin number for AF_UART0_RX location number i */
9231 #define AF_UART0_CLK_PIN(i)         (-1)                                                                                                                              /**< Pin number for AF_UART0_CLK location number i */
9232 #define AF_UART0_CS_PIN(i)          (-1)                                                                                                                              /**< Pin number for AF_UART0_CS location number i */
9233 #define AF_UART0_CTS_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 :  -1)                                  /**< Pin number for AF_UART0_CTS location number i */
9234 #define AF_UART0_RTS_PIN(i)         ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 :  -1)                                  /**< Pin number for AF_UART0_RTS location number i */
9235 #define AF_UART1_TX_PIN(i)          ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 :  -1)                                               /**< Pin number for AF_UART1_TX location number i */
9236 #define AF_UART1_RX_PIN(i)          ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 :  -1)                                              /**< Pin number for AF_UART1_RX location number i */
9237 #define AF_UART1_CLK_PIN(i)         (-1)                                                                                                                              /**< Pin number for AF_UART1_CLK location number i */
9238 #define AF_UART1_CS_PIN(i)          (-1)                                                                                                                              /**< Pin number for AF_UART1_CS location number i */
9239 #define AF_UART1_CTS_PIN(i)         ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 :  -1)                                                /**< Pin number for AF_UART1_CTS location number i */
9240 #define AF_UART1_RTS_PIN(i)         ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 :  -1)                                                /**< Pin number for AF_UART1_RTS location number i */
9241 #define AF_LEUART0_TX_PIN(i)        ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 :  -1)                                /**< Pin number for AF_LEUART0_TX location number i */
9242 #define AF_LEUART0_RX_PIN(i)        ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 :  -1)                                /**< Pin number for AF_LEUART0_RX location number i */
9243 #define AF_LEUART1_TX_PIN(i)        ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 :  -1)                                                  /**< Pin number for AF_LEUART1_TX location number i */
9244 #define AF_LEUART1_RX_PIN(i)        ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 :  -1)                                                  /**< Pin number for AF_LEUART1_RX location number i */
9245 #define AF_LETIMER0_OUT0_PIN(i)     ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 :  -1)  /**< Pin number for AF_LETIMER0_OUT0 location number i */
9246 #define AF_LETIMER0_OUT1_PIN(i)     ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 :  -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */
9247 #define AF_LETIMER1_OUT0_PIN(i)     ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 :  -1)                                 /**< Pin number for AF_LETIMER1_OUT0 location number i */
9248 #define AF_LETIMER1_OUT1_PIN(i)     ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 :  -1)                                 /**< Pin number for AF_LETIMER1_OUT1 location number i */
9249 #define AF_PCNT0_S0IN_PIN(i)        ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 :  -1)   /**< Pin number for AF_PCNT0_S0IN location number i */
9250 #define AF_PCNT0_S1IN_PIN(i)        ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 :  -1)   /**< Pin number for AF_PCNT0_S1IN location number i */
9251 #define AF_PCNT1_S0IN_PIN(i)        ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 :  -1)                 /**< Pin number for AF_PCNT1_S0IN location number i */
9252 #define AF_PCNT1_S1IN_PIN(i)        ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 :  -1)                  /**< Pin number for AF_PCNT1_S1IN location number i */
9253 #define AF_PCNT2_S0IN_PIN(i)        ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 :  -1)                                               /**< Pin number for AF_PCNT2_S0IN location number i */
9254 #define AF_PCNT2_S1IN_PIN(i)        ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 :  -1)                                               /**< Pin number for AF_PCNT2_S1IN location number i */
9255 #define AF_I2C0_SDA_PIN(i)          ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 :  -1)   /**< Pin number for AF_I2C0_SDA location number i */
9256 #define AF_I2C0_SCL_PIN(i)          ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 :  -1)   /**< Pin number for AF_I2C0_SCL location number i */
9257 #define AF_I2C1_SDA_PIN(i)          ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 :  -1)                                                /**< Pin number for AF_I2C1_SDA location number i */
9258 #define AF_I2C1_SCL_PIN(i)          ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 :  -1)                                                 /**< Pin number for AF_I2C1_SCL location number i */
9259 #define AF_ACMP0_OUT_PIN(i)         ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 :  -1)   /**< Pin number for AF_ACMP0_OUT location number i */
9260 #define AF_ACMP1_OUT_PIN(i)         ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 :  -1)  /**< Pin number for AF_ACMP1_OUT location number i */
9261 #define AF_ACMP2_OUT_PIN(i)         ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 :  -1)                                                                                /**< Pin number for AF_ACMP2_OUT location number i */
9262 #define AF_DBG_TDI_PIN(i)           ((i) == 0 ? 5 :  -1)                                                                                                              /**< Pin number for AF_DBG_TDI location number i */
9263 #define AF_DBG_TDO_PIN(i)           ((i) == 0 ? 2 :  -1)                                                                                                              /**< Pin number for AF_DBG_TDO location number i */
9264 #define AF_DBG_SWV_PIN(i)           ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 :  -1)                                                                /**< Pin number for AF_DBG_SWV location number i */
9265 #define AF_DBG_SWDIOTMS_PIN(i)      ((i) == 0 ? 1 :  -1)                                                                                                              /**< Pin number for AF_DBG_SWDIOTMS location number i */
9266 #define AF_DBG_SWCLKTCK_PIN(i)      ((i) == 0 ? 0 :  -1)                                                                                                              /**< Pin number for AF_DBG_SWCLKTCK location number i */
9267 #define AF_ETM_TCLK_PIN(i)          ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 :  -1)                                                 /**< Pin number for AF_ETM_TCLK location number i */
9268 #define AF_ETM_TD0_PIN(i)           ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 :  -1)                                                 /**< Pin number for AF_ETM_TD0 location number i */
9269 #define AF_ETM_TD1_PIN(i)           ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 :  -1)                                                /**< Pin number for AF_ETM_TD1 location number i */
9270 #define AF_ETM_TD2_PIN(i)           ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 :  -1)                                                /**< Pin number for AF_ETM_TD2 location number i */
9271 #define AF_ETM_TD3_PIN(i)           ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 :  -1)                                                 /**< Pin number for AF_ETM_TD3 location number i */
9272 
9273 /** @} */
9274 /** @} End of group EFM32GG12B310F1024GQ100_AF_Pins */
9275 
9276 /** @} End of group EFM32GG12B310F1024GQ100 */
9277 
9278 /** @} End of group Parts */
9279 
9280 #ifdef __cplusplus
9281 }
9282 #endif
9283 
9284 #endif /* EFM32GG12B310F1024GQ100_H */
9285