1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG21 ICACHE register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG21_ICACHE_H 31 #define EFR32MG21_ICACHE_H 32 #define ICACHE_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG21_ICACHE ICACHE 40 * @{ 41 * @brief EFR32MG21 ICACHE Register Declaration. 42 *****************************************************************************/ 43 44 /** ICACHE Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP Version */ 47 __IOM uint32_t CTRL; /**< Control Register */ 48 __IM uint32_t PCHITS; /**< Performance Counter Hits */ 49 __IM uint32_t PCMISSES; /**< Performance Counter Misses */ 50 __IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */ 51 __IM uint32_t STATUS; /**< Status Register */ 52 __IOM uint32_t CMD; /**< Command Register */ 53 __IOM uint32_t LPMODE; /**< Low Power Mode */ 54 __IOM uint32_t IF; /**< Interrupt Flag */ 55 __IOM uint32_t IEN; /**< Interrupt Enable */ 56 uint32_t RESERVED0[1014U]; /**< Reserved for future use */ 57 __IM uint32_t IPVERSION_SET; /**< IP Version */ 58 __IOM uint32_t CTRL_SET; /**< Control Register */ 59 __IM uint32_t PCHITS_SET; /**< Performance Counter Hits */ 60 __IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */ 61 __IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */ 62 __IM uint32_t STATUS_SET; /**< Status Register */ 63 __IOM uint32_t CMD_SET; /**< Command Register */ 64 __IOM uint32_t LPMODE_SET; /**< Low Power Mode */ 65 __IOM uint32_t IF_SET; /**< Interrupt Flag */ 66 __IOM uint32_t IEN_SET; /**< Interrupt Enable */ 67 uint32_t RESERVED1[1014U]; /**< Reserved for future use */ 68 __IM uint32_t IPVERSION_CLR; /**< IP Version */ 69 __IOM uint32_t CTRL_CLR; /**< Control Register */ 70 __IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */ 71 __IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */ 72 __IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */ 73 __IM uint32_t STATUS_CLR; /**< Status Register */ 74 __IOM uint32_t CMD_CLR; /**< Command Register */ 75 __IOM uint32_t LPMODE_CLR; /**< Low Power Mode */ 76 __IOM uint32_t IF_CLR; /**< Interrupt Flag */ 77 __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ 78 uint32_t RESERVED2[1014U]; /**< Reserved for future use */ 79 __IM uint32_t IPVERSION_TGL; /**< IP Version */ 80 __IOM uint32_t CTRL_TGL; /**< Control Register */ 81 __IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */ 82 __IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */ 83 __IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */ 84 __IM uint32_t STATUS_TGL; /**< Status Register */ 85 __IOM uint32_t CMD_TGL; /**< Command Register */ 86 __IOM uint32_t LPMODE_TGL; /**< Low Power Mode */ 87 __IOM uint32_t IF_TGL; /**< Interrupt Flag */ 88 __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ 89 } ICACHE_TypeDef; 90 /** @} End of group EFR32MG21_ICACHE */ 91 92 /**************************************************************************//** 93 * @addtogroup EFR32MG21_ICACHE 94 * @{ 95 * @defgroup EFR32MG21_ICACHE_BitFields ICACHE Bit Fields 96 * @{ 97 *****************************************************************************/ 98 99 /* Bit fields for ICACHE IPVERSION */ 100 #define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */ 101 #define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */ 102 #define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */ 103 #define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */ 104 #define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */ 105 #define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */ 106 107 /* Bit fields for ICACHE CTRL */ 108 #define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */ 109 #define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */ 110 #define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */ 111 #define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */ 112 #define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */ 113 #define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ 114 #define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */ 115 #define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */ 116 #define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */ 117 #define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */ 118 #define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ 119 #define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */ 120 #define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */ 121 #define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */ 122 #define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */ 123 #define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ 124 #define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */ 125 126 /* Bit fields for ICACHE PCHITS */ 127 #define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */ 128 #define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */ 129 #define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */ 130 #define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */ 131 #define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */ 132 #define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */ 133 134 /* Bit fields for ICACHE PCMISSES */ 135 #define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */ 136 #define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */ 137 #define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */ 138 #define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */ 139 #define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */ 140 #define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */ 141 142 /* Bit fields for ICACHE PCAHITS */ 143 #define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */ 144 #define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */ 145 #define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */ 146 #define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */ 147 #define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */ 148 #define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */ 149 150 /* Bit fields for ICACHE STATUS */ 151 #define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */ 152 #define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */ 153 #define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */ 154 #define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */ 155 #define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */ 156 #define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */ 157 #define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */ 158 159 /* Bit fields for ICACHE CMD */ 160 #define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */ 161 #define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */ 162 #define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */ 163 #define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */ 164 #define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */ 165 #define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ 166 #define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */ 167 #define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ 168 #define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */ 169 #define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */ 170 #define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ 171 #define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */ 172 #define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ 173 #define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */ 174 #define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */ 175 #define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ 176 #define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */ 177 178 /* Bit fields for ICACHE LPMODE */ 179 #define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */ 180 #define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */ 181 #define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */ 182 #define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */ 183 #define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */ 184 #define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */ 185 #define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */ 186 #define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */ 187 #define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ 188 #define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */ 189 #define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */ 190 #define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */ 191 #define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */ 192 #define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */ 193 #define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */ 194 #define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ 195 196 /* Bit fields for ICACHE IF */ 197 #define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */ 198 #define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */ 199 #define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */ 200 #define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ 201 #define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ 202 #define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ 203 #define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */ 204 #define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */ 205 #define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ 206 #define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ 207 #define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ 208 #define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */ 209 #define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */ 210 #define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ 211 #define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ 212 #define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ 213 #define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */ 214 #define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */ 215 #define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ 216 #define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ 217 #define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ 218 #define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */ 219 220 /* Bit fields for ICACHE IEN */ 221 #define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */ 222 #define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */ 223 #define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */ 224 #define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ 225 #define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ 226 #define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ 227 #define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */ 228 #define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */ 229 #define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ 230 #define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ 231 #define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ 232 #define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */ 233 #define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */ 234 #define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ 235 #define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ 236 #define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ 237 #define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */ 238 #define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */ 239 #define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ 240 #define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ 241 #define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ 242 #define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */ 243 244 /** @} End of group EFR32MG21_ICACHE_BitFields */ 245 /** @} End of group EFR32MG21_ICACHE */ 246 /** @} End of group Parts */ 247 248 #endif /* EFR32MG21_ICACHE_H */ 249
