1 /***************************************************************************//**
2  * @file
3  * @brief EFR32FG1P_LDMA_CH register and bit field definitions
4  *******************************************************************************
5  * # License
6  * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b>
7  *******************************************************************************
8  *
9  * SPDX-License-Identifier: Zlib
10  *
11  * The licensor of this software is Silicon Laboratories Inc.
12  *
13  * This software is provided 'as-is', without any express or implied
14  * warranty. In no event will the authors be held liable for any damages
15  * arising from the use of this software.
16  *
17  * Permission is granted to anyone to use this software for any purpose,
18  * including commercial applications, and to alter it and redistribute it
19  * freely, subject to the following restrictions:
20  *
21  * 1. The origin of this software must not be misrepresented; you must not
22  *    claim that you wrote the original software. If you use this software
23  *    in a product, an acknowledgment in the product documentation would be
24  *    appreciated but is not required.
25  * 2. Altered source versions must be plainly marked as such, and must not be
26  *    misrepresented as being the original software.
27  * 3. This notice may not be removed or altered from any source distribution.
28  *
29  ******************************************************************************/
30 
31 #if defined(__ICCARM__)
32 #pragma system_include       /* Treat file as system include file. */
33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
34 #pragma clang system_header  /* Treat file as system include file. */
35 #endif
36 
37 /***************************************************************************//**
38  * @addtogroup Parts
39  * @{
40  ******************************************************************************/
41 /***************************************************************************//**
42  * @brief LDMA_CH LDMA CH Register
43  * @ingroup EFR32FG1P_LDMA
44  ******************************************************************************/
45 typedef struct {
46   __IOM uint32_t REQSEL;        /**< Channel Peripheral Request Select Register  */
47   __IOM uint32_t CFG;           /**< Channel Configuration Register  */
48   __IOM uint32_t LOOP;          /**< Channel Loop Counter Register  */
49   __IOM uint32_t CTRL;          /**< Channel Descriptor Control Word Register  */
50   __IOM uint32_t SRC;           /**< Channel Descriptor Source Data Address Register  */
51   __IOM uint32_t DST;           /**< Channel Descriptor Destination Data Address Register  */
52   __IOM uint32_t LINK;          /**< Channel Descriptor Link Structure Address Register  */
53   uint32_t       RESERVED0[5U]; /**< Reserved future */
54 } LDMA_CH_TypeDef;
55 
56 /** @} End of group Parts */
57