1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG22 MSC register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG22_MSC_H 31 #define EFR32BG22_MSC_H 32 #define MSC_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG22_MSC MSC 40 * @{ 41 * @brief EFR32BG22 MSC Register Declaration. 42 *****************************************************************************/ 43 44 /** MSC Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP version ID */ 47 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 48 __IOM uint32_t READCTRL; /**< Read Control Register */ 49 __IOM uint32_t WRITECTRL; /**< Write Control Register */ 50 __IOM uint32_t WRITECMD; /**< Write Command Register */ 51 __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ 52 __IOM uint32_t WDATA; /**< Write Data Register */ 53 __IM uint32_t STATUS; /**< Status Register */ 54 __IOM uint32_t IF; /**< Interrupt Flag Register */ 55 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 56 uint32_t RESERVED1[3U]; /**< Reserved for future use */ 57 __IM uint32_t USERDATASIZE; /**< User Data Region Size Register */ 58 __IOM uint32_t CMD; /**< Command Register */ 59 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 60 __IOM uint32_t MISCLOCKWORD; /**< Mass erase and User data page lock word */ 61 uint32_t RESERVED2[3U]; /**< Reserved for future use */ 62 __IOM uint32_t PWRCTRL; /**< Power control register */ 63 uint32_t RESERVED3[51U]; /**< Reserved for future use */ 64 __IOM uint32_t PAGELOCK0; /**< Main space page 0-31 lock word */ 65 __IOM uint32_t PAGELOCK1; /**< Main space page 32-63 lock word */ 66 uint32_t RESERVED4[2U]; /**< Reserved for future use */ 67 uint32_t RESERVED5[4U]; /**< Reserved for future use */ 68 uint32_t RESERVED6[4U]; /**< Reserved for future use */ 69 uint32_t RESERVED7[4U]; /**< Reserved for future use */ 70 uint32_t RESERVED8[4U]; /**< Reserved for future use */ 71 uint32_t RESERVED9[12U]; /**< Reserved for future use */ 72 uint32_t RESERVED10[1U]; /**< Reserved for future use */ 73 uint32_t RESERVED11[11U]; /**< Reserved for future use */ 74 uint32_t RESERVED12[1U]; /**< Reserved for future use */ 75 uint32_t RESERVED13[907U]; /**< Reserved for future use */ 76 __IM uint32_t IPVERSION_SET; /**< IP version ID */ 77 uint32_t RESERVED14[1U]; /**< Reserved for future use */ 78 __IOM uint32_t READCTRL_SET; /**< Read Control Register */ 79 __IOM uint32_t WRITECTRL_SET; /**< Write Control Register */ 80 __IOM uint32_t WRITECMD_SET; /**< Write Command Register */ 81 __IOM uint32_t ADDRB_SET; /**< Page Erase/Write Address Buffer */ 82 __IOM uint32_t WDATA_SET; /**< Write Data Register */ 83 __IM uint32_t STATUS_SET; /**< Status Register */ 84 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 85 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 86 uint32_t RESERVED15[3U]; /**< Reserved for future use */ 87 __IM uint32_t USERDATASIZE_SET; /**< User Data Region Size Register */ 88 __IOM uint32_t CMD_SET; /**< Command Register */ 89 __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ 90 __IOM uint32_t MISCLOCKWORD_SET; /**< Mass erase and User data page lock word */ 91 uint32_t RESERVED16[3U]; /**< Reserved for future use */ 92 __IOM uint32_t PWRCTRL_SET; /**< Power control register */ 93 uint32_t RESERVED17[51U]; /**< Reserved for future use */ 94 __IOM uint32_t PAGELOCK0_SET; /**< Main space page 0-31 lock word */ 95 __IOM uint32_t PAGELOCK1_SET; /**< Main space page 32-63 lock word */ 96 uint32_t RESERVED18[2U]; /**< Reserved for future use */ 97 uint32_t RESERVED19[4U]; /**< Reserved for future use */ 98 uint32_t RESERVED20[4U]; /**< Reserved for future use */ 99 uint32_t RESERVED21[4U]; /**< Reserved for future use */ 100 uint32_t RESERVED22[4U]; /**< Reserved for future use */ 101 uint32_t RESERVED23[12U]; /**< Reserved for future use */ 102 uint32_t RESERVED24[1U]; /**< Reserved for future use */ 103 uint32_t RESERVED25[11U]; /**< Reserved for future use */ 104 uint32_t RESERVED26[1U]; /**< Reserved for future use */ 105 uint32_t RESERVED27[907U]; /**< Reserved for future use */ 106 __IM uint32_t IPVERSION_CLR; /**< IP version ID */ 107 uint32_t RESERVED28[1U]; /**< Reserved for future use */ 108 __IOM uint32_t READCTRL_CLR; /**< Read Control Register */ 109 __IOM uint32_t WRITECTRL_CLR; /**< Write Control Register */ 110 __IOM uint32_t WRITECMD_CLR; /**< Write Command Register */ 111 __IOM uint32_t ADDRB_CLR; /**< Page Erase/Write Address Buffer */ 112 __IOM uint32_t WDATA_CLR; /**< Write Data Register */ 113 __IM uint32_t STATUS_CLR; /**< Status Register */ 114 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 115 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 116 uint32_t RESERVED29[3U]; /**< Reserved for future use */ 117 __IM uint32_t USERDATASIZE_CLR; /**< User Data Region Size Register */ 118 __IOM uint32_t CMD_CLR; /**< Command Register */ 119 __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ 120 __IOM uint32_t MISCLOCKWORD_CLR; /**< Mass erase and User data page lock word */ 121 uint32_t RESERVED30[3U]; /**< Reserved for future use */ 122 __IOM uint32_t PWRCTRL_CLR; /**< Power control register */ 123 uint32_t RESERVED31[51U]; /**< Reserved for future use */ 124 __IOM uint32_t PAGELOCK0_CLR; /**< Main space page 0-31 lock word */ 125 __IOM uint32_t PAGELOCK1_CLR; /**< Main space page 32-63 lock word */ 126 uint32_t RESERVED32[2U]; /**< Reserved for future use */ 127 uint32_t RESERVED33[4U]; /**< Reserved for future use */ 128 uint32_t RESERVED34[4U]; /**< Reserved for future use */ 129 uint32_t RESERVED35[4U]; /**< Reserved for future use */ 130 uint32_t RESERVED36[4U]; /**< Reserved for future use */ 131 uint32_t RESERVED37[12U]; /**< Reserved for future use */ 132 uint32_t RESERVED38[1U]; /**< Reserved for future use */ 133 uint32_t RESERVED39[11U]; /**< Reserved for future use */ 134 uint32_t RESERVED40[1U]; /**< Reserved for future use */ 135 uint32_t RESERVED41[907U]; /**< Reserved for future use */ 136 __IM uint32_t IPVERSION_TGL; /**< IP version ID */ 137 uint32_t RESERVED42[1U]; /**< Reserved for future use */ 138 __IOM uint32_t READCTRL_TGL; /**< Read Control Register */ 139 __IOM uint32_t WRITECTRL_TGL; /**< Write Control Register */ 140 __IOM uint32_t WRITECMD_TGL; /**< Write Command Register */ 141 __IOM uint32_t ADDRB_TGL; /**< Page Erase/Write Address Buffer */ 142 __IOM uint32_t WDATA_TGL; /**< Write Data Register */ 143 __IM uint32_t STATUS_TGL; /**< Status Register */ 144 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 145 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 146 uint32_t RESERVED43[3U]; /**< Reserved for future use */ 147 __IM uint32_t USERDATASIZE_TGL; /**< User Data Region Size Register */ 148 __IOM uint32_t CMD_TGL; /**< Command Register */ 149 __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ 150 __IOM uint32_t MISCLOCKWORD_TGL; /**< Mass erase and User data page lock word */ 151 uint32_t RESERVED44[3U]; /**< Reserved for future use */ 152 __IOM uint32_t PWRCTRL_TGL; /**< Power control register */ 153 uint32_t RESERVED45[51U]; /**< Reserved for future use */ 154 __IOM uint32_t PAGELOCK0_TGL; /**< Main space page 0-31 lock word */ 155 __IOM uint32_t PAGELOCK1_TGL; /**< Main space page 32-63 lock word */ 156 uint32_t RESERVED46[2U]; /**< Reserved for future use */ 157 uint32_t RESERVED47[4U]; /**< Reserved for future use */ 158 uint32_t RESERVED48[4U]; /**< Reserved for future use */ 159 uint32_t RESERVED49[4U]; /**< Reserved for future use */ 160 uint32_t RESERVED50[4U]; /**< Reserved for future use */ 161 uint32_t RESERVED51[12U]; /**< Reserved for future use */ 162 uint32_t RESERVED52[1U]; /**< Reserved for future use */ 163 uint32_t RESERVED53[11U]; /**< Reserved for future use */ 164 uint32_t RESERVED54[1U]; /**< Reserved for future use */ 165 } MSC_TypeDef; 166 /** @} End of group EFR32BG22_MSC */ 167 168 /**************************************************************************//** 169 * @addtogroup EFR32BG22_MSC 170 * @{ 171 * @defgroup EFR32BG22_MSC_BitFields MSC Bit Fields 172 * @{ 173 *****************************************************************************/ 174 175 /* Bit fields for MSC IPVERSION */ 176 #define _MSC_IPVERSION_RESETVALUE 0x00000008UL /**< Default value for MSC_IPVERSION */ 177 #define _MSC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MSC_IPVERSION */ 178 #define _MSC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MSC_IPVERSION */ 179 #define _MSC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_IPVERSION */ 180 #define _MSC_IPVERSION_IPVERSION_DEFAULT 0x00000008UL /**< Mode DEFAULT for MSC_IPVERSION */ 181 #define MSC_IPVERSION_IPVERSION_DEFAULT (_MSC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IPVERSION */ 182 183 /* Bit fields for MSC READCTRL */ 184 #define _MSC_READCTRL_RESETVALUE 0x00200000UL /**< Default value for MSC_READCTRL */ 185 #define _MSC_READCTRL_MASK 0x00301002UL /**< Mask for MSC_READCTRL */ 186 #define MSC_READCTRL_DOUTBUFEN (0x1UL << 12) /**< Flash dout pipeline buffer enable */ 187 #define _MSC_READCTRL_DOUTBUFEN_SHIFT 12 /**< Shift value for MSC_DOUTBUFEN */ 188 #define _MSC_READCTRL_DOUTBUFEN_MASK 0x1000UL /**< Bit mask for MSC_DOUTBUFEN */ 189 #define _MSC_READCTRL_DOUTBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 190 #define MSC_READCTRL_DOUTBUFEN_DEFAULT (_MSC_READCTRL_DOUTBUFEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_READCTRL */ 191 #define _MSC_READCTRL_MODE_SHIFT 20 /**< Shift value for MSC_MODE */ 192 #define _MSC_READCTRL_MODE_MASK 0x300000UL /**< Bit mask for MSC_MODE */ 193 #define _MSC_READCTRL_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_READCTRL */ 194 #define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ 195 #define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ 196 #define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ 197 #define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ 198 #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_READCTRL */ 199 #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 20) /**< Shifted mode WS0 for MSC_READCTRL */ 200 #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 20) /**< Shifted mode WS1 for MSC_READCTRL */ 201 #define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 20) /**< Shifted mode WS2 for MSC_READCTRL */ 202 #define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 20) /**< Shifted mode WS3 for MSC_READCTRL */ 203 204 /* Bit fields for MSC WRITECTRL */ 205 #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ 206 #define _MSC_WRITECTRL_MASK 0x0000000BUL /**< Mask for MSC_WRITECTRL */ 207 #define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ 208 #define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ 209 #define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ 210 #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ 211 #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ 212 #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ 213 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ 214 #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ 215 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ 216 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ 217 #define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Write */ 218 #define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */ 219 #define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */ 220 #define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ 221 #define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ 222 223 /* Bit fields for MSC WRITECMD */ 224 #define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ 225 #define _MSC_WRITECMD_MASK 0x00001126UL /**< Mask for MSC_WRITECMD */ 226 #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ 227 #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ 228 #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ 229 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 230 #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 231 #define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ 232 #define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ 233 #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ 234 #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 235 #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 236 #define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ 237 #define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ 238 #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ 239 #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 240 #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 241 #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ 242 #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ 243 #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ 244 #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 245 #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 246 #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ 247 #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ 248 #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ 249 #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 250 #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 251 252 /* Bit fields for MSC ADDRB */ 253 #define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ 254 #define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ 255 #define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ 256 #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ 257 #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ 258 #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ 259 260 /* Bit fields for MSC WDATA */ 261 #define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ 262 #define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ 263 #define _MSC_WDATA_DATAW_SHIFT 0 /**< Shift value for MSC_DATAW */ 264 #define _MSC_WDATA_DATAW_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_DATAW */ 265 #define _MSC_WDATA_DATAW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ 266 #define MSC_WDATA_DATAW_DEFAULT (_MSC_WDATA_DATAW_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ 267 268 /* Bit fields for MSC STATUS */ 269 #define _MSC_STATUS_RESETVALUE 0x08000008UL /**< Default value for MSC_STATUS */ 270 #define _MSC_STATUS_MASK 0xF901007FUL /**< Mask for MSC_STATUS */ 271 #define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ 272 #define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ 273 #define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ 274 #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 275 #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ 276 #define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ 277 #define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ 278 #define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ 279 #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 280 #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ 281 #define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ 282 #define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ 283 #define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ 284 #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 285 #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ 286 #define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ 287 #define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ 288 #define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ 289 #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ 290 #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ 291 #define MSC_STATUS_ERASEABORTED (0x1UL << 4) /**< Erase Operation Aborted */ 292 #define _MSC_STATUS_ERASEABORTED_SHIFT 4 /**< Shift value for MSC_ERASEABORTED */ 293 #define _MSC_STATUS_ERASEABORTED_MASK 0x10UL /**< Bit mask for MSC_ERASEABORTED */ 294 #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 295 #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ 296 #define MSC_STATUS_PENDING (0x1UL << 5) /**< Write Command In Queue */ 297 #define _MSC_STATUS_PENDING_SHIFT 5 /**< Shift value for MSC_PENDING */ 298 #define _MSC_STATUS_PENDING_MASK 0x20UL /**< Bit mask for MSC_PENDING */ 299 #define _MSC_STATUS_PENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 300 #define MSC_STATUS_PENDING_DEFAULT (_MSC_STATUS_PENDING_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ 301 #define MSC_STATUS_TIMEOUT (0x1UL << 6) /**< Write Command Timeout */ 302 #define _MSC_STATUS_TIMEOUT_SHIFT 6 /**< Shift value for MSC_TIMEOUT */ 303 #define _MSC_STATUS_TIMEOUT_MASK 0x40UL /**< Bit mask for MSC_TIMEOUT */ 304 #define _MSC_STATUS_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 305 #define MSC_STATUS_TIMEOUT_DEFAULT (_MSC_STATUS_TIMEOUT_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ 306 #define MSC_STATUS_REGLOCK (0x1UL << 16) /**< Register Lock Status */ 307 #define _MSC_STATUS_REGLOCK_SHIFT 16 /**< Shift value for MSC_REGLOCK */ 308 #define _MSC_STATUS_REGLOCK_MASK 0x10000UL /**< Bit mask for MSC_REGLOCK */ 309 #define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 310 #define _MSC_STATUS_REGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_STATUS */ 311 #define _MSC_STATUS_REGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_STATUS */ 312 #define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_STATUS */ 313 #define MSC_STATUS_REGLOCK_UNLOCKED (_MSC_STATUS_REGLOCK_UNLOCKED << 16) /**< Shifted mode UNLOCKED for MSC_STATUS */ 314 #define MSC_STATUS_REGLOCK_LOCKED (_MSC_STATUS_REGLOCK_LOCKED << 16) /**< Shifted mode LOCKED for MSC_STATUS */ 315 #define MSC_STATUS_PWRON (0x1UL << 24) /**< Flash Power On Status */ 316 #define _MSC_STATUS_PWRON_SHIFT 24 /**< Shift value for MSC_PWRON */ 317 #define _MSC_STATUS_PWRON_MASK 0x1000000UL /**< Bit mask for MSC_PWRON */ 318 #define _MSC_STATUS_PWRON_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 319 #define MSC_STATUS_PWRON_DEFAULT (_MSC_STATUS_PWRON_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ 320 #define MSC_STATUS_WREADY (0x1UL << 27) /**< Flash Write Ready */ 321 #define _MSC_STATUS_WREADY_SHIFT 27 /**< Shift value for MSC_WREADY */ 322 #define _MSC_STATUS_WREADY_MASK 0x8000000UL /**< Bit mask for MSC_WREADY */ 323 #define _MSC_STATUS_WREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ 324 #define MSC_STATUS_WREADY_DEFAULT (_MSC_STATUS_WREADY_DEFAULT << 27) /**< Shifted mode DEFAULT for MSC_STATUS */ 325 #define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ 326 #define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ 327 #define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 328 #define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ 329 330 /* Bit fields for MSC IF */ 331 #define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ 332 #define _MSC_IF_MASK 0x00000307UL /**< Mask for MSC_IF */ 333 #define MSC_IF_ERASE (0x1UL << 0) /**< Host Erase Done Interrupt Read Flag */ 334 #define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ 335 #define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ 336 #define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 337 #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ 338 #define MSC_IF_WRITE (0x1UL << 1) /**< Host Write Done Interrupt Read Flag */ 339 #define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ 340 #define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ 341 #define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 342 #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ 343 #define MSC_IF_WDATAOV (0x1UL << 2) /**< Host write buffer overflow */ 344 #define _MSC_IF_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ 345 #define _MSC_IF_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ 346 #define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 347 #define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ 348 #define MSC_IF_PWRUPF (0x1UL << 8) /**< Flash Power Up Sequence Complete Flag */ 349 #define _MSC_IF_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ 350 #define _MSC_IF_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ 351 #define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 352 #define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ 353 #define MSC_IF_PWROFF (0x1UL << 9) /**< Flash Power Off Sequence Complete Flag */ 354 #define _MSC_IF_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ 355 #define _MSC_IF_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ 356 #define _MSC_IF_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 357 #define MSC_IF_PWROFF_DEFAULT (_MSC_IF_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IF */ 358 359 /* Bit fields for MSC IEN */ 360 #define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ 361 #define _MSC_IEN_MASK 0x00000307UL /**< Mask for MSC_IEN */ 362 #define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt enable */ 363 #define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ 364 #define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ 365 #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 366 #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ 367 #define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt enable */ 368 #define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ 369 #define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ 370 #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 371 #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ 372 #define MSC_IEN_WDATAOV (0x1UL << 2) /**< write data buffer overflow irq enable */ 373 #define _MSC_IEN_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ 374 #define _MSC_IEN_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ 375 #define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 376 #define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ 377 #define MSC_IEN_PWRUPF (0x1UL << 8) /**< Flash Power Up Seq done irq enable */ 378 #define _MSC_IEN_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ 379 #define _MSC_IEN_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ 380 #define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 381 #define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ 382 #define MSC_IEN_PWROFF (0x1UL << 9) /**< Flash Power Off Seq done irq enable */ 383 #define _MSC_IEN_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ 384 #define _MSC_IEN_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ 385 #define _MSC_IEN_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 386 #define MSC_IEN_PWROFF_DEFAULT (_MSC_IEN_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IEN */ 387 388 /* Bit fields for MSC USERDATASIZE */ 389 #define _MSC_USERDATASIZE_RESETVALUE 0x00000004UL /**< Default value for MSC_USERDATASIZE */ 390 #define _MSC_USERDATASIZE_MASK 0x0000003FUL /**< Mask for MSC_USERDATASIZE */ 391 #define _MSC_USERDATASIZE_USERDATASIZE_SHIFT 0 /**< Shift value for MSC_USERDATASIZE */ 392 #define _MSC_USERDATASIZE_USERDATASIZE_MASK 0x3FUL /**< Bit mask for MSC_USERDATASIZE */ 393 #define _MSC_USERDATASIZE_USERDATASIZE_DEFAULT 0x00000004UL /**< Mode DEFAULT for MSC_USERDATASIZE */ 394 #define MSC_USERDATASIZE_USERDATASIZE_DEFAULT (_MSC_USERDATASIZE_USERDATASIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_USERDATASIZE */ 395 396 /* Bit fields for MSC CMD */ 397 #define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ 398 #define _MSC_CMD_MASK 0x00000011UL /**< Mask for MSC_CMD */ 399 #define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ 400 #define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ 401 #define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ 402 #define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ 403 #define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ 404 #define MSC_CMD_PWROFF (0x1UL << 4) /**< Flash power off/sleep command */ 405 #define _MSC_CMD_PWROFF_SHIFT 4 /**< Shift value for MSC_PWROFF */ 406 #define _MSC_CMD_PWROFF_MASK 0x10UL /**< Bit mask for MSC_PWROFF */ 407 #define _MSC_CMD_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ 408 #define MSC_CMD_PWROFF_DEFAULT (_MSC_CMD_PWROFF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CMD */ 409 410 /* Bit fields for MSC LOCK */ 411 #define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ 412 #define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ 413 #define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ 414 #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ 415 #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ 416 #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ 417 #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ 418 #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ 419 #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ 420 #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ 421 422 /* Bit fields for MSC MISCLOCKWORD */ 423 #define _MSC_MISCLOCKWORD_RESETVALUE 0x00000011UL /**< Default value for MSC_MISCLOCKWORD */ 424 #define _MSC_MISCLOCKWORD_MASK 0x00000011UL /**< Mask for MSC_MISCLOCKWORD */ 425 #define MSC_MISCLOCKWORD_MELOCKBIT (0x1UL << 0) /**< Mass Erase Lock */ 426 #define _MSC_MISCLOCKWORD_MELOCKBIT_SHIFT 0 /**< Shift value for MSC_MELOCKBIT */ 427 #define _MSC_MISCLOCKWORD_MELOCKBIT_MASK 0x1UL /**< Bit mask for MSC_MELOCKBIT */ 428 #define _MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ 429 #define MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ 430 #define MSC_MISCLOCKWORD_UDLOCKBIT (0x1UL << 4) /**< User Data Lock */ 431 #define _MSC_MISCLOCKWORD_UDLOCKBIT_SHIFT 4 /**< Shift value for MSC_UDLOCKBIT */ 432 #define _MSC_MISCLOCKWORD_UDLOCKBIT_MASK 0x10UL /**< Bit mask for MSC_UDLOCKBIT */ 433 #define _MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ 434 #define MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ 435 436 /* Bit fields for MSC PWRCTRL */ 437 #define _MSC_PWRCTRL_RESETVALUE 0x00100002UL /**< Default value for MSC_PWRCTRL */ 438 #define _MSC_PWRCTRL_MASK 0x00FF0013UL /**< Mask for MSC_PWRCTRL */ 439 #define MSC_PWRCTRL_PWROFFONEM1ENTRY (0x1UL << 0) /**< Power down Flash macro when enter EM1 */ 440 #define _MSC_PWRCTRL_PWROFFONEM1ENTRY_SHIFT 0 /**< Shift value for MSC_PWROFFONEM1ENTRY */ 441 #define _MSC_PWRCTRL_PWROFFONEM1ENTRY_MASK 0x1UL /**< Bit mask for MSC_PWROFFONEM1ENTRY */ 442 #define _MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ 443 #define MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ 444 #define MSC_PWRCTRL_PWROFFONEM1PENTRY (0x1UL << 1) /**< Power down Flash macro when enter EM1P */ 445 #define _MSC_PWRCTRL_PWROFFONEM1PENTRY_SHIFT 1 /**< Shift value for MSC_PWROFFONEM1PENTRY */ 446 #define _MSC_PWRCTRL_PWROFFONEM1PENTRY_MASK 0x2UL /**< Bit mask for MSC_PWROFFONEM1PENTRY */ 447 #define _MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_PWRCTRL */ 448 #define MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ 449 #define MSC_PWRCTRL_PWROFFENTRYAGAIN (0x1UL << 4) /**< POWER down flash again in EM1/EM1p */ 450 #define _MSC_PWRCTRL_PWROFFENTRYAGAIN_SHIFT 4 /**< Shift value for MSC_PWROFFENTRYAGAIN */ 451 #define _MSC_PWRCTRL_PWROFFENTRYAGAIN_MASK 0x10UL /**< Bit mask for MSC_PWROFFENTRYAGAIN */ 452 #define _MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ 453 #define MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT (_MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ 454 #define _MSC_PWRCTRL_PWROFFDLY_SHIFT 16 /**< Shift value for MSC_PWROFFDLY */ 455 #define _MSC_PWRCTRL_PWROFFDLY_MASK 0xFF0000UL /**< Bit mask for MSC_PWROFFDLY */ 456 #define _MSC_PWRCTRL_PWROFFDLY_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_PWRCTRL */ 457 #define MSC_PWRCTRL_PWROFFDLY_DEFAULT (_MSC_PWRCTRL_PWROFFDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ 458 459 /* Bit fields for MSC PAGELOCK0 */ 460 #define _MSC_PAGELOCK0_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK0 */ 461 #define _MSC_PAGELOCK0_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK0 */ 462 #define _MSC_PAGELOCK0_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ 463 #define _MSC_PAGELOCK0_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ 464 #define _MSC_PAGELOCK0_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK0 */ 465 #define MSC_PAGELOCK0_LOCKBIT_DEFAULT (_MSC_PAGELOCK0_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK0 */ 466 467 /* Bit fields for MSC PAGELOCK1 */ 468 #define _MSC_PAGELOCK1_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK1 */ 469 #define _MSC_PAGELOCK1_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK1 */ 470 #define _MSC_PAGELOCK1_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ 471 #define _MSC_PAGELOCK1_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ 472 #define _MSC_PAGELOCK1_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK1 */ 473 #define MSC_PAGELOCK1_LOCKBIT_DEFAULT (_MSC_PAGELOCK1_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK1 */ 474 475 /** @} End of group EFR32BG22_MSC_BitFields */ 476 /** @} End of group EFR32BG22_MSC */ 477 /** @} End of group Parts */ 478 479 #endif /* EFR32BG22_MSC_H */ 480
