1 /***************************************************************************//**
2  * @file
3  * @brief CMSIS Cortex-M4 System Layer for EFM32WG devices.
4  *******************************************************************************
5  * # License
6  * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
7  *******************************************************************************
8  *
9  * SPDX-License-Identifier: Zlib
10  *
11  * The licensor of this software is Silicon Laboratories Inc.
12  *
13  * This software is provided 'as-is', without any express or implied
14  * warranty. In no event will the authors be held liable for any damages
15  * arising from the use of this software.
16  *
17  * Permission is granted to anyone to use this software for any purpose,
18  * including commercial applications, and to alter it and redistribute it
19  * freely, subject to the following restrictions:
20  *
21  * 1. The origin of this software must not be misrepresented; you must not
22  *    claim that you wrote the original software. If you use this software
23  *    in a product, an acknowledgment in the product documentation would be
24  *    appreciated but is not required.
25  * 2. Altered source versions must be plainly marked as such, and must not be
26  *    misrepresented as being the original software.
27  * 3. This notice may not be removed or altered from any source distribution.
28  *
29  ******************************************************************************/
30 
31 #ifndef SYSTEM_EFM32WG_H
32 #define SYSTEM_EFM32WG_H
33 
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 
38 #include <stdint.h>
39 
40 /***************************************************************************//**
41  * @addtogroup Parts
42  * @{
43  ******************************************************************************/
44 /***************************************************************************//**
45  * @addtogroup EFM32WG EFM32WG
46  * @{
47  ******************************************************************************/
48 
49 /*******************************************************************************
50  ******************************   TYPEDEFS   ***********************************
51  ******************************************************************************/
52 
53 /* Interrupt vectortable entry */
54 typedef union {
55   void (*pFunc)(void);
56   void *topOfStack;
57 } tVectorEntry;
58 
59 /*******************************************************************************
60  **************************   GLOBAL VARIABLES   *******************************
61  ******************************************************************************/
62 
63 extern uint32_t SystemCoreClock;    /**< System Clock Frequency (Core Clock) */
64 
65 #if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
66 #if defined(__ICCARM__)    /* IAR requires the __vector_table symbol */
67 #define __Vectors    __vector_table
68 #endif
69 extern const tVectorEntry __Vectors[];
70 #endif
71 
72 /*******************************************************************************
73  *****************************   PROTOTYPES   **********************************
74  ******************************************************************************/
75 
76 /* Interrupt routines - prototypes */
77 void Reset_Handler(void);           /**< Reset Handler */
78 void NMI_Handler(void);             /**< NMI Handler */
79 void HardFault_Handler(void);       /**< Hard Fault Handler */
80 void MemManage_Handler(void);       /**< MPU Fault Handler */
81 void BusFault_Handler(void);        /**< Bus Fault Handler */
82 void UsageFault_Handler(void);      /**< Usage Fault Handler */
83 void SVC_Handler(void);             /**< SVCall Handler */
84 void DebugMon_Handler(void);        /**< Debug Monitor Handler */
85 void PendSV_Handler(void);          /**< PendSV Handler */
86 void SysTick_Handler(void);         /**< SysTick Handler */
87 
88 void DMA_IRQHandler(void);          /**< DMA IRQ Handler */
89 void GPIO_EVEN_IRQHandler(void);    /**< GPIO EVEN IRQ Handler */
90 void TIMER0_IRQHandler(void);       /**< TIMER0 IRQ Handler */
91 void USART0_RX_IRQHandler(void);    /**< USART0 RX IRQ Handler */
92 void USART0_TX_IRQHandler(void);    /**< USART0 TX IRQ Handler */
93 void USB_IRQHandler(void);          /**< USB IRQ Handler */
94 void ACMP0_IRQHandler(void);        /**< ACMP0 IRQ Handler */
95 void ADC0_IRQHandler(void);         /**< ADC0 IRQ Handler */
96 void DAC0_IRQHandler(void);         /**< DAC0 IRQ Handler */
97 void I2C0_IRQHandler(void);         /**< I2C0 IRQ Handler */
98 void I2C1_IRQHandler(void);         /**< I2C1 IRQ Handler */
99 void GPIO_ODD_IRQHandler(void);     /**< GPIO ODD IRQ Handler */
100 void TIMER1_IRQHandler(void);       /**< TIMER1 IRQ Handler */
101 void TIMER2_IRQHandler(void);       /**< TIMER2 IRQ Handler */
102 void TIMER3_IRQHandler(void);       /**< TIMER3 IRQ Handler */
103 void USART1_RX_IRQHandler(void);    /**< USART1 RX IRQ Handler */
104 void USART1_TX_IRQHandler(void);    /**< USART1 TX IRQ Handler */
105 void LESENSE_IRQHandler(void);      /**< LESENSE IRQ Handler */
106 void USART2_RX_IRQHandler(void);    /**< USART2 RX IRQ Handler */
107 void USART2_TX_IRQHandler(void);    /**< USART2 TX IRQ Handler */
108 void UART0_RX_IRQHandler(void);     /**< UART0 RX IRQ Handler */
109 void UART0_TX_IRQHandler(void);     /**< UART0 TX IRQ Handler */
110 void UART1_RX_IRQHandler(void);     /**< UART1 RX IRQ Handler */
111 void UART1_TX_IRQHandler(void);     /**< UART1 TX IRQ Handler */
112 void LEUART0_IRQHandler(void);      /**< LEUART0 IRQ Handler */
113 void LEUART1_IRQHandler(void);      /**< LEUART1 IRQ Handler */
114 void LETIMER0_IRQHandler(void);     /**< LETIMER0 IRQ Handler */
115 void PCNT0_IRQHandler(void);        /**< PCNT0 IRQ Handler */
116 void PCNT1_IRQHandler(void);        /**< PCNT1 IRQ Handler */
117 void PCNT2_IRQHandler(void);        /**< PCNT2 IRQ Handler */
118 void RTC_IRQHandler(void);          /**< RTC IRQ Handler */
119 void BURTC_IRQHandler(void);        /**< BURTC IRQ Handler */
120 void CMU_IRQHandler(void);          /**< CMU IRQ Handler */
121 void VCMP_IRQHandler(void);         /**< VCMP IRQ Handler */
122 void LCD_IRQHandler(void);          /**< LCD IRQ Handler */
123 void MSC_IRQHandler(void);          /**< MSC IRQ Handler */
124 void AES_IRQHandler(void);          /**< AES IRQ Handler */
125 void EBI_IRQHandler(void);          /**< EBI IRQ Handler */
126 void EMU_IRQHandler(void);          /**< EMU IRQ Handler */
127 void FPUEH_IRQHandler(void);        /**< FPUEH IRQ Handler */
128 
129 uint32_t SystemCoreClockGet(void);
130 uint32_t SystemMaxCoreClockGet(void);
131 
132 /***************************************************************************//**
133  * @brief
134  *   Update CMSIS SystemCoreClock variable.
135  *
136  * @details
137  *   CMSIS defines a global variable SystemCoreClock that shall hold the
138  *   core frequency in Hz. If the core frequency is dynamically changed, the
139  *   variable must be kept updated in order to be CMSIS compliant.
140  *
141  *   Notice that if only changing core clock frequency through the EFM32 CMU
142  *   API, this variable will be kept updated. This function is only provided
143  *   for CMSIS compliance and if a user modifies the the core clock outside
144  *   the CMU API.
145  ******************************************************************************/
SystemCoreClockUpdate(void)146 static __INLINE void SystemCoreClockUpdate(void)
147 {
148   (void)SystemCoreClockGet();
149 }
150 
151 void SystemInit(void);
152 uint32_t SystemHFClockGet(void);
153 uint32_t SystemHFXOClockGet(void);
154 void SystemHFXOClockSet(uint32_t freq);
155 uint32_t SystemLFRCOClockGet(void);
156 uint32_t SystemULFRCOClockGet(void);
157 uint32_t SystemLFXOClockGet(void);
158 void SystemLFXOClockSet(uint32_t freq);
159 
160 /** @} End of group EFM32WG */
161 /** @} End of group Parts */
162 
163 #ifdef __cplusplus
164 }
165 #endif
166 
167 #endif /* SYSTEM_EFM32WG_H */
168