1 /***************************************************************************//** 2 * @file 3 * @brief EFM32WG_LCD register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32WG_LCD 43 * @{ 44 * @brief EFM32WG_LCD Register Declaration 45 ******************************************************************************/ 46 typedef struct { 47 __IOM uint32_t CTRL; /**< Control Register */ 48 __IOM uint32_t DISPCTRL; /**< Display Control Register */ 49 __IOM uint32_t SEGEN; /**< Segment Enable Register */ 50 __IOM uint32_t BACTRL; /**< Blink and Animation Control Register */ 51 __IM uint32_t STATUS; /**< Status Register */ 52 __IOM uint32_t AREGA; /**< Animation Register A */ 53 __IOM uint32_t AREGB; /**< Animation Register B */ 54 __IM uint32_t IF; /**< Interrupt Flag Register */ 55 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 56 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 57 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 58 59 uint32_t RESERVED0[5U]; /**< Reserved for future use **/ 60 __IOM uint32_t SEGD0L; /**< Segment Data Low Register 0 */ 61 __IOM uint32_t SEGD1L; /**< Segment Data Low Register 1 */ 62 __IOM uint32_t SEGD2L; /**< Segment Data Low Register 2 */ 63 __IOM uint32_t SEGD3L; /**< Segment Data Low Register 3 */ 64 __IOM uint32_t SEGD0H; /**< Segment Data High Register 0 */ 65 __IOM uint32_t SEGD1H; /**< Segment Data High Register 1 */ 66 __IOM uint32_t SEGD2H; /**< Segment Data High Register 2 */ 67 __IOM uint32_t SEGD3H; /**< Segment Data High Register 3 */ 68 69 __IOM uint32_t FREEZE; /**< Freeze Register */ 70 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 71 72 uint32_t RESERVED1[19U]; /**< Reserved for future use **/ 73 __IOM uint32_t SEGD4H; /**< Segment Data High Register 4 */ 74 __IOM uint32_t SEGD5H; /**< Segment Data High Register 5 */ 75 __IOM uint32_t SEGD6H; /**< Segment Data High Register 6 */ 76 __IOM uint32_t SEGD7H; /**< Segment Data High Register 7 */ 77 uint32_t RESERVED2[2U]; /**< Reserved for future use **/ 78 __IOM uint32_t SEGD4L; /**< Segment Data Low Register 4 */ 79 __IOM uint32_t SEGD5L; /**< Segment Data Low Register 5 */ 80 __IOM uint32_t SEGD6L; /**< Segment Data Low Register 6 */ 81 __IOM uint32_t SEGD7L; /**< Segment Data Low Register 7 */ 82 } LCD_TypeDef; /**< LCD Register Declaration *//** @} */ 83 84 /***************************************************************************//** 85 * @defgroup EFM32WG_LCD_BitFields 86 * @{ 87 ******************************************************************************/ 88 89 /* Bit fields for LCD CTRL */ 90 #define _LCD_CTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_CTRL */ 91 #define _LCD_CTRL_MASK 0x00800007UL /**< Mask for LCD_CTRL */ 92 #define LCD_CTRL_EN (0x1UL << 0) /**< LCD Enable */ 93 #define _LCD_CTRL_EN_SHIFT 0 /**< Shift value for LCD_EN */ 94 #define _LCD_CTRL_EN_MASK 0x1UL /**< Bit mask for LCD_EN */ 95 #define _LCD_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ 96 #define LCD_CTRL_EN_DEFAULT (_LCD_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CTRL */ 97 #define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */ 98 #define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */ 99 #define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ 100 #define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */ 101 #define _LCD_CTRL_UDCTRL_FCEVENT 0x00000001UL /**< Mode FCEVENT for LCD_CTRL */ 102 #define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL /**< Mode FRAMESTART for LCD_CTRL */ 103 #define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */ 104 #define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */ 105 #define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */ 106 #define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */ 107 #define LCD_CTRL_DSC (0x1UL << 23) /**< Direct Segment Control */ 108 #define _LCD_CTRL_DSC_SHIFT 23 /**< Shift value for LCD_DSC */ 109 #define _LCD_CTRL_DSC_MASK 0x800000UL /**< Bit mask for LCD_DSC */ 110 #define _LCD_CTRL_DSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ 111 #define LCD_CTRL_DSC_DEFAULT (_LCD_CTRL_DSC_DEFAULT << 23) /**< Shifted mode DEFAULT for LCD_CTRL */ 112 113 /* Bit fields for LCD DISPCTRL */ 114 #define _LCD_DISPCTRL_RESETVALUE 0x000C1F00UL /**< Default value for LCD_DISPCTRL */ 115 #define _LCD_DISPCTRL_MASK 0x005D9F1FUL /**< Mask for LCD_DISPCTRL */ 116 #define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */ 117 #define _LCD_DISPCTRL_MUX_MASK 0x3UL /**< Bit mask for LCD_MUX */ 118 #define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ 119 #define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ 120 #define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */ 121 #define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */ 122 #define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */ 123 #define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ 124 #define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */ 125 #define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */ 126 #define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */ 127 #define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */ 128 #define _LCD_DISPCTRL_BIAS_SHIFT 2 /**< Shift value for LCD_BIAS */ 129 #define _LCD_DISPCTRL_BIAS_MASK 0xCUL /**< Bit mask for LCD_BIAS */ 130 #define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ 131 #define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ 132 #define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */ 133 #define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */ 134 #define _LCD_DISPCTRL_BIAS_ONEFOURTH 0x00000003UL /**< Mode ONEFOURTH for LCD_DISPCTRL */ 135 #define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ 136 #define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 2) /**< Shifted mode STATIC for LCD_DISPCTRL */ 137 #define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 2) /**< Shifted mode ONEHALF for LCD_DISPCTRL */ 138 #define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 2) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */ 139 #define LCD_DISPCTRL_BIAS_ONEFOURTH (_LCD_DISPCTRL_BIAS_ONEFOURTH << 2) /**< Shifted mode ONEFOURTH for LCD_DISPCTRL */ 140 #define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */ 141 #define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */ 142 #define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */ 143 #define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ 144 #define _LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL /**< Mode LOWPOWER for LCD_DISPCTRL */ 145 #define _LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL /**< Mode NORMAL for LCD_DISPCTRL */ 146 #define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ 147 #define LCD_DISPCTRL_WAVE_LOWPOWER (_LCD_DISPCTRL_WAVE_LOWPOWER << 4) /**< Shifted mode LOWPOWER for LCD_DISPCTRL */ 148 #define LCD_DISPCTRL_WAVE_NORMAL (_LCD_DISPCTRL_WAVE_NORMAL << 4) /**< Shifted mode NORMAL for LCD_DISPCTRL */ 149 #define _LCD_DISPCTRL_CONLEV_SHIFT 8 /**< Shift value for LCD_CONLEV */ 150 #define _LCD_DISPCTRL_CONLEV_MASK 0x1F00UL /**< Bit mask for LCD_CONLEV */ 151 #define _LCD_DISPCTRL_CONLEV_MIN 0x00000000UL /**< Mode MIN for LCD_DISPCTRL */ 152 #define _LCD_DISPCTRL_CONLEV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LCD_DISPCTRL */ 153 #define _LCD_DISPCTRL_CONLEV_MAX 0x0000001FUL /**< Mode MAX for LCD_DISPCTRL */ 154 #define LCD_DISPCTRL_CONLEV_MIN (_LCD_DISPCTRL_CONLEV_MIN << 8) /**< Shifted mode MIN for LCD_DISPCTRL */ 155 #define LCD_DISPCTRL_CONLEV_DEFAULT (_LCD_DISPCTRL_CONLEV_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ 156 #define LCD_DISPCTRL_CONLEV_MAX (_LCD_DISPCTRL_CONLEV_MAX << 8) /**< Shifted mode MAX for LCD_DISPCTRL */ 157 #define LCD_DISPCTRL_CONCONF (0x1UL << 15) /**< Contrast Configuration */ 158 #define _LCD_DISPCTRL_CONCONF_SHIFT 15 /**< Shift value for LCD_CONCONF */ 159 #define _LCD_DISPCTRL_CONCONF_MASK 0x8000UL /**< Bit mask for LCD_CONCONF */ 160 #define _LCD_DISPCTRL_CONCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ 161 #define _LCD_DISPCTRL_CONCONF_VLCD 0x00000000UL /**< Mode VLCD for LCD_DISPCTRL */ 162 #define _LCD_DISPCTRL_CONCONF_GND 0x00000001UL /**< Mode GND for LCD_DISPCTRL */ 163 #define LCD_DISPCTRL_CONCONF_DEFAULT (_LCD_DISPCTRL_CONCONF_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ 164 #define LCD_DISPCTRL_CONCONF_VLCD (_LCD_DISPCTRL_CONCONF_VLCD << 15) /**< Shifted mode VLCD for LCD_DISPCTRL */ 165 #define LCD_DISPCTRL_CONCONF_GND (_LCD_DISPCTRL_CONCONF_GND << 15) /**< Shifted mode GND for LCD_DISPCTRL */ 166 #define LCD_DISPCTRL_VLCDSEL (0x1UL << 16) /**< VLCD Selection */ 167 #define _LCD_DISPCTRL_VLCDSEL_SHIFT 16 /**< Shift value for LCD_VLCDSEL */ 168 #define _LCD_DISPCTRL_VLCDSEL_MASK 0x10000UL /**< Bit mask for LCD_VLCDSEL */ 169 #define _LCD_DISPCTRL_VLCDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ 170 #define _LCD_DISPCTRL_VLCDSEL_VDD 0x00000000UL /**< Mode VDD for LCD_DISPCTRL */ 171 #define _LCD_DISPCTRL_VLCDSEL_VEXTBOOST 0x00000001UL /**< Mode VEXTBOOST for LCD_DISPCTRL */ 172 #define LCD_DISPCTRL_VLCDSEL_DEFAULT (_LCD_DISPCTRL_VLCDSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ 173 #define LCD_DISPCTRL_VLCDSEL_VDD (_LCD_DISPCTRL_VLCDSEL_VDD << 16) /**< Shifted mode VDD for LCD_DISPCTRL */ 174 #define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (_LCD_DISPCTRL_VLCDSEL_VEXTBOOST << 16) /**< Shifted mode VEXTBOOST for LCD_DISPCTRL */ 175 #define _LCD_DISPCTRL_VBLEV_SHIFT 18 /**< Shift value for LCD_VBLEV */ 176 #define _LCD_DISPCTRL_VBLEV_MASK 0x1C0000UL /**< Bit mask for LCD_VBLEV */ 177 #define _LCD_DISPCTRL_VBLEV_LEVEL0 0x00000000UL /**< Mode LEVEL0 for LCD_DISPCTRL */ 178 #define _LCD_DISPCTRL_VBLEV_LEVEL1 0x00000001UL /**< Mode LEVEL1 for LCD_DISPCTRL */ 179 #define _LCD_DISPCTRL_VBLEV_LEVEL2 0x00000002UL /**< Mode LEVEL2 for LCD_DISPCTRL */ 180 #define _LCD_DISPCTRL_VBLEV_DEFAULT 0x00000003UL /**< Mode DEFAULT for LCD_DISPCTRL */ 181 #define _LCD_DISPCTRL_VBLEV_LEVEL3 0x00000003UL /**< Mode LEVEL3 for LCD_DISPCTRL */ 182 #define _LCD_DISPCTRL_VBLEV_LEVEL4 0x00000004UL /**< Mode LEVEL4 for LCD_DISPCTRL */ 183 #define _LCD_DISPCTRL_VBLEV_LEVEL5 0x00000005UL /**< Mode LEVEL5 for LCD_DISPCTRL */ 184 #define _LCD_DISPCTRL_VBLEV_LEVEL6 0x00000006UL /**< Mode LEVEL6 for LCD_DISPCTRL */ 185 #define _LCD_DISPCTRL_VBLEV_LEVEL7 0x00000007UL /**< Mode LEVEL7 for LCD_DISPCTRL */ 186 #define LCD_DISPCTRL_VBLEV_LEVEL0 (_LCD_DISPCTRL_VBLEV_LEVEL0 << 18) /**< Shifted mode LEVEL0 for LCD_DISPCTRL */ 187 #define LCD_DISPCTRL_VBLEV_LEVEL1 (_LCD_DISPCTRL_VBLEV_LEVEL1 << 18) /**< Shifted mode LEVEL1 for LCD_DISPCTRL */ 188 #define LCD_DISPCTRL_VBLEV_LEVEL2 (_LCD_DISPCTRL_VBLEV_LEVEL2 << 18) /**< Shifted mode LEVEL2 for LCD_DISPCTRL */ 189 #define LCD_DISPCTRL_VBLEV_DEFAULT (_LCD_DISPCTRL_VBLEV_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ 190 #define LCD_DISPCTRL_VBLEV_LEVEL3 (_LCD_DISPCTRL_VBLEV_LEVEL3 << 18) /**< Shifted mode LEVEL3 for LCD_DISPCTRL */ 191 #define LCD_DISPCTRL_VBLEV_LEVEL4 (_LCD_DISPCTRL_VBLEV_LEVEL4 << 18) /**< Shifted mode LEVEL4 for LCD_DISPCTRL */ 192 #define LCD_DISPCTRL_VBLEV_LEVEL5 (_LCD_DISPCTRL_VBLEV_LEVEL5 << 18) /**< Shifted mode LEVEL5 for LCD_DISPCTRL */ 193 #define LCD_DISPCTRL_VBLEV_LEVEL6 (_LCD_DISPCTRL_VBLEV_LEVEL6 << 18) /**< Shifted mode LEVEL6 for LCD_DISPCTRL */ 194 #define LCD_DISPCTRL_VBLEV_LEVEL7 (_LCD_DISPCTRL_VBLEV_LEVEL7 << 18) /**< Shifted mode LEVEL7 for LCD_DISPCTRL */ 195 #define LCD_DISPCTRL_MUXE (0x1UL << 22) /**< Extended Mux Configuration */ 196 #define _LCD_DISPCTRL_MUXE_SHIFT 22 /**< Shift value for LCD_MUXE */ 197 #define _LCD_DISPCTRL_MUXE_MASK 0x400000UL /**< Bit mask for LCD_MUXE */ 198 #define _LCD_DISPCTRL_MUXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ 199 #define _LCD_DISPCTRL_MUXE_MUX 0x00000000UL /**< Mode MUX for LCD_DISPCTRL */ 200 #define _LCD_DISPCTRL_MUXE_MUXE 0x00000001UL /**< Mode MUXE for LCD_DISPCTRL */ 201 #define LCD_DISPCTRL_MUXE_DEFAULT (_LCD_DISPCTRL_MUXE_DEFAULT << 22) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ 202 #define LCD_DISPCTRL_MUXE_MUX (_LCD_DISPCTRL_MUXE_MUX << 22) /**< Shifted mode MUX for LCD_DISPCTRL */ 203 #define LCD_DISPCTRL_MUXE_MUXE (_LCD_DISPCTRL_MUXE_MUXE << 22) /**< Shifted mode MUXE for LCD_DISPCTRL */ 204 205 /* Bit fields for LCD SEGEN */ 206 #define _LCD_SEGEN_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN */ 207 #define _LCD_SEGEN_MASK 0x000003FFUL /**< Mask for LCD_SEGEN */ 208 #define _LCD_SEGEN_SEGEN_SHIFT 0 /**< Shift value for LCD_SEGEN */ 209 #define _LCD_SEGEN_SEGEN_MASK 0x3FFUL /**< Bit mask for LCD_SEGEN */ 210 #define _LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN */ 211 #define LCD_SEGEN_SEGEN_DEFAULT (_LCD_SEGEN_SEGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGEN */ 212 213 /* Bit fields for LCD BACTRL */ 214 #define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */ 215 #define _LCD_BACTRL_MASK 0x10FF01FFUL /**< Mask for LCD_BACTRL */ 216 #define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */ 217 #define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */ 218 #define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */ 219 #define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 220 #define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */ 221 #define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */ 222 #define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */ 223 #define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */ 224 #define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 225 #define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */ 226 #define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */ 227 #define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */ 228 #define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */ 229 #define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 230 #define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */ 231 #define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */ 232 #define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */ 233 #define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 234 #define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ 235 #define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ 236 #define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ 237 #define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */ 238 #define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */ 239 #define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ 240 #define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ 241 #define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */ 242 #define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */ 243 #define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 244 #define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ 245 #define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ 246 #define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ 247 #define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */ 248 #define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */ 249 #define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ 250 #define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ 251 #define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */ 252 #define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */ 253 #define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */ 254 #define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 255 #define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */ 256 #define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */ 257 #define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */ 258 #define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */ 259 #define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */ 260 #define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */ 261 #define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */ 262 #define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */ 263 #define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 264 #define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */ 265 #define _LCD_BACTRL_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */ 266 #define _LCD_BACTRL_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */ 267 #define _LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 268 #define _LCD_BACTRL_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACTRL */ 269 #define _LCD_BACTRL_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACTRL */ 270 #define _LCD_BACTRL_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACTRL */ 271 #define _LCD_BACTRL_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACTRL */ 272 #define LCD_BACTRL_FCPRESC_DEFAULT (_LCD_BACTRL_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACTRL */ 273 #define LCD_BACTRL_FCPRESC_DIV1 (_LCD_BACTRL_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACTRL */ 274 #define LCD_BACTRL_FCPRESC_DIV2 (_LCD_BACTRL_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACTRL */ 275 #define LCD_BACTRL_FCPRESC_DIV4 (_LCD_BACTRL_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACTRL */ 276 #define LCD_BACTRL_FCPRESC_DIV8 (_LCD_BACTRL_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACTRL */ 277 #define _LCD_BACTRL_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */ 278 #define _LCD_BACTRL_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */ 279 #define _LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 280 #define LCD_BACTRL_FCTOP_DEFAULT (_LCD_BACTRL_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACTRL */ 281 #define LCD_BACTRL_ALOC (0x1UL << 28) /**< Animation Location */ 282 #define _LCD_BACTRL_ALOC_SHIFT 28 /**< Shift value for LCD_ALOC */ 283 #define _LCD_BACTRL_ALOC_MASK 0x10000000UL /**< Bit mask for LCD_ALOC */ 284 #define _LCD_BACTRL_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ 285 #define _LCD_BACTRL_ALOC_SEG0TO7 0x00000000UL /**< Mode SEG0TO7 for LCD_BACTRL */ 286 #define _LCD_BACTRL_ALOC_SEG8TO15 0x00000001UL /**< Mode SEG8TO15 for LCD_BACTRL */ 287 #define LCD_BACTRL_ALOC_DEFAULT (_LCD_BACTRL_ALOC_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_BACTRL */ 288 #define LCD_BACTRL_ALOC_SEG0TO7 (_LCD_BACTRL_ALOC_SEG0TO7 << 28) /**< Shifted mode SEG0TO7 for LCD_BACTRL */ 289 #define LCD_BACTRL_ALOC_SEG8TO15 (_LCD_BACTRL_ALOC_SEG8TO15 << 28) /**< Shifted mode SEG8TO15 for LCD_BACTRL */ 290 291 /* Bit fields for LCD STATUS */ 292 #define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */ 293 #define _LCD_STATUS_MASK 0x0000010FUL /**< Mask for LCD_STATUS */ 294 #define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */ 295 #define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */ 296 #define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ 297 #define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */ 298 #define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */ 299 #define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */ 300 #define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */ 301 #define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ 302 #define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */ 303 304 /* Bit fields for LCD AREGA */ 305 #define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */ 306 #define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */ 307 #define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */ 308 #define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */ 309 #define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */ 310 #define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */ 311 312 /* Bit fields for LCD AREGB */ 313 #define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */ 314 #define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */ 315 #define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */ 316 #define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */ 317 #define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */ 318 #define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */ 319 320 /* Bit fields for LCD IF */ 321 #define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */ 322 #define _LCD_IF_MASK 0x00000001UL /**< Mask for LCD_IF */ 323 #define LCD_IF_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag */ 324 #define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */ 325 #define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ 326 #define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ 327 #define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */ 328 329 /* Bit fields for LCD IFS */ 330 #define _LCD_IFS_RESETVALUE 0x00000000UL /**< Default value for LCD_IFS */ 331 #define _LCD_IFS_MASK 0x00000001UL /**< Mask for LCD_IFS */ 332 #define LCD_IFS_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Set */ 333 #define _LCD_IFS_FC_SHIFT 0 /**< Shift value for LCD_FC */ 334 #define _LCD_IFS_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ 335 #define _LCD_IFS_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFS */ 336 #define LCD_IFS_FC_DEFAULT (_LCD_IFS_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFS */ 337 338 /* Bit fields for LCD IFC */ 339 #define _LCD_IFC_RESETVALUE 0x00000000UL /**< Default value for LCD_IFC */ 340 #define _LCD_IFC_MASK 0x00000001UL /**< Mask for LCD_IFC */ 341 #define LCD_IFC_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Clear */ 342 #define _LCD_IFC_FC_SHIFT 0 /**< Shift value for LCD_FC */ 343 #define _LCD_IFC_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ 344 #define _LCD_IFC_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFC */ 345 #define LCD_IFC_FC_DEFAULT (_LCD_IFC_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFC */ 346 347 /* Bit fields for LCD IEN */ 348 #define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */ 349 #define _LCD_IEN_MASK 0x00000001UL /**< Mask for LCD_IEN */ 350 #define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter Interrupt Enable */ 351 #define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */ 352 #define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ 353 #define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ 354 #define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */ 355 356 /* Bit fields for LCD SEGD0L */ 357 #define _LCD_SEGD0L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0L */ 358 #define _LCD_SEGD0L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD0L */ 359 #define _LCD_SEGD0L_SEGD0L_SHIFT 0 /**< Shift value for LCD_SEGD0L */ 360 #define _LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD0L */ 361 #define _LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0L */ 362 #define LCD_SEGD0L_SEGD0L_DEFAULT (_LCD_SEGD0L_SEGD0L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0L */ 363 364 /* Bit fields for LCD SEGD1L */ 365 #define _LCD_SEGD1L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1L */ 366 #define _LCD_SEGD1L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD1L */ 367 #define _LCD_SEGD1L_SEGD1L_SHIFT 0 /**< Shift value for LCD_SEGD1L */ 368 #define _LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD1L */ 369 #define _LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1L */ 370 #define LCD_SEGD1L_SEGD1L_DEFAULT (_LCD_SEGD1L_SEGD1L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1L */ 371 372 /* Bit fields for LCD SEGD2L */ 373 #define _LCD_SEGD2L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2L */ 374 #define _LCD_SEGD2L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD2L */ 375 #define _LCD_SEGD2L_SEGD2L_SHIFT 0 /**< Shift value for LCD_SEGD2L */ 376 #define _LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD2L */ 377 #define _LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2L */ 378 #define LCD_SEGD2L_SEGD2L_DEFAULT (_LCD_SEGD2L_SEGD2L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2L */ 379 380 /* Bit fields for LCD SEGD3L */ 381 #define _LCD_SEGD3L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3L */ 382 #define _LCD_SEGD3L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD3L */ 383 #define _LCD_SEGD3L_SEGD3L_SHIFT 0 /**< Shift value for LCD_SEGD3L */ 384 #define _LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD3L */ 385 #define _LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3L */ 386 #define LCD_SEGD3L_SEGD3L_DEFAULT (_LCD_SEGD3L_SEGD3L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3L */ 387 388 /* Bit fields for LCD SEGD0H */ 389 #define _LCD_SEGD0H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0H */ 390 #define _LCD_SEGD0H_MASK 0x000000FFUL /**< Mask for LCD_SEGD0H */ 391 #define _LCD_SEGD0H_SEGD0H_SHIFT 0 /**< Shift value for LCD_SEGD0H */ 392 #define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL /**< Bit mask for LCD_SEGD0H */ 393 #define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0H */ 394 #define LCD_SEGD0H_SEGD0H_DEFAULT (_LCD_SEGD0H_SEGD0H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0H */ 395 396 /* Bit fields for LCD SEGD1H */ 397 #define _LCD_SEGD1H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1H */ 398 #define _LCD_SEGD1H_MASK 0x000000FFUL /**< Mask for LCD_SEGD1H */ 399 #define _LCD_SEGD1H_SEGD1H_SHIFT 0 /**< Shift value for LCD_SEGD1H */ 400 #define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL /**< Bit mask for LCD_SEGD1H */ 401 #define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1H */ 402 #define LCD_SEGD1H_SEGD1H_DEFAULT (_LCD_SEGD1H_SEGD1H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1H */ 403 404 /* Bit fields for LCD SEGD2H */ 405 #define _LCD_SEGD2H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2H */ 406 #define _LCD_SEGD2H_MASK 0x000000FFUL /**< Mask for LCD_SEGD2H */ 407 #define _LCD_SEGD2H_SEGD2H_SHIFT 0 /**< Shift value for LCD_SEGD2H */ 408 #define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL /**< Bit mask for LCD_SEGD2H */ 409 #define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2H */ 410 #define LCD_SEGD2H_SEGD2H_DEFAULT (_LCD_SEGD2H_SEGD2H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2H */ 411 412 /* Bit fields for LCD SEGD3H */ 413 #define _LCD_SEGD3H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3H */ 414 #define _LCD_SEGD3H_MASK 0x000000FFUL /**< Mask for LCD_SEGD3H */ 415 #define _LCD_SEGD3H_SEGD3H_SHIFT 0 /**< Shift value for LCD_SEGD3H */ 416 #define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL /**< Bit mask for LCD_SEGD3H */ 417 #define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3H */ 418 #define LCD_SEGD3H_SEGD3H_DEFAULT (_LCD_SEGD3H_SEGD3H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3H */ 419 420 /* Bit fields for LCD FREEZE */ 421 #define _LCD_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LCD_FREEZE */ 422 #define _LCD_FREEZE_MASK 0x00000001UL /**< Mask for LCD_FREEZE */ 423 #define LCD_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ 424 #define _LCD_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LCD_REGFREEZE */ 425 #define _LCD_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LCD_REGFREEZE */ 426 #define _LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */ 427 #define _LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LCD_FREEZE */ 428 #define _LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LCD_FREEZE */ 429 #define LCD_FREEZE_REGFREEZE_DEFAULT (_LCD_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FREEZE */ 430 #define LCD_FREEZE_REGFREEZE_UPDATE (_LCD_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LCD_FREEZE */ 431 #define LCD_FREEZE_REGFREEZE_FREEZE (_LCD_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LCD_FREEZE */ 432 433 /* Bit fields for LCD SYNCBUSY */ 434 #define _LCD_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LCD_SYNCBUSY */ 435 #define _LCD_SYNCBUSY_MASK 0x000FFFFFUL /**< Mask for LCD_SYNCBUSY */ 436 #define LCD_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ 437 #define _LCD_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LCD_CTRL */ 438 #define _LCD_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LCD_CTRL */ 439 #define _LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 440 #define LCD_SYNCBUSY_CTRL_DEFAULT (_LCD_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 441 #define LCD_SYNCBUSY_BACTRL (0x1UL << 1) /**< BACTRL Register Busy */ 442 #define _LCD_SYNCBUSY_BACTRL_SHIFT 1 /**< Shift value for LCD_BACTRL */ 443 #define _LCD_SYNCBUSY_BACTRL_MASK 0x2UL /**< Bit mask for LCD_BACTRL */ 444 #define _LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 445 #define LCD_SYNCBUSY_BACTRL_DEFAULT (_LCD_SYNCBUSY_BACTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 446 #define LCD_SYNCBUSY_AREGA (0x1UL << 2) /**< AREGA Register Busy */ 447 #define _LCD_SYNCBUSY_AREGA_SHIFT 2 /**< Shift value for LCD_AREGA */ 448 #define _LCD_SYNCBUSY_AREGA_MASK 0x4UL /**< Bit mask for LCD_AREGA */ 449 #define _LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 450 #define LCD_SYNCBUSY_AREGA_DEFAULT (_LCD_SYNCBUSY_AREGA_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 451 #define LCD_SYNCBUSY_AREGB (0x1UL << 3) /**< AREGB Register Busy */ 452 #define _LCD_SYNCBUSY_AREGB_SHIFT 3 /**< Shift value for LCD_AREGB */ 453 #define _LCD_SYNCBUSY_AREGB_MASK 0x8UL /**< Bit mask for LCD_AREGB */ 454 #define _LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 455 #define LCD_SYNCBUSY_AREGB_DEFAULT (_LCD_SYNCBUSY_AREGB_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 456 #define LCD_SYNCBUSY_SEGD0L (0x1UL << 4) /**< SEGD0L Register Busy */ 457 #define _LCD_SYNCBUSY_SEGD0L_SHIFT 4 /**< Shift value for LCD_SEGD0L */ 458 #define _LCD_SYNCBUSY_SEGD0L_MASK 0x10UL /**< Bit mask for LCD_SEGD0L */ 459 #define _LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 460 #define LCD_SYNCBUSY_SEGD0L_DEFAULT (_LCD_SYNCBUSY_SEGD0L_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 461 #define LCD_SYNCBUSY_SEGD1L (0x1UL << 5) /**< SEGD1L Register Busy */ 462 #define _LCD_SYNCBUSY_SEGD1L_SHIFT 5 /**< Shift value for LCD_SEGD1L */ 463 #define _LCD_SYNCBUSY_SEGD1L_MASK 0x20UL /**< Bit mask for LCD_SEGD1L */ 464 #define _LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 465 #define LCD_SYNCBUSY_SEGD1L_DEFAULT (_LCD_SYNCBUSY_SEGD1L_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 466 #define LCD_SYNCBUSY_SEGD2L (0x1UL << 6) /**< SEGD2L Register Busy */ 467 #define _LCD_SYNCBUSY_SEGD2L_SHIFT 6 /**< Shift value for LCD_SEGD2L */ 468 #define _LCD_SYNCBUSY_SEGD2L_MASK 0x40UL /**< Bit mask for LCD_SEGD2L */ 469 #define _LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 470 #define LCD_SYNCBUSY_SEGD2L_DEFAULT (_LCD_SYNCBUSY_SEGD2L_DEFAULT << 6) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 471 #define LCD_SYNCBUSY_SEGD3L (0x1UL << 7) /**< SEGD3L Register Busy */ 472 #define _LCD_SYNCBUSY_SEGD3L_SHIFT 7 /**< Shift value for LCD_SEGD3L */ 473 #define _LCD_SYNCBUSY_SEGD3L_MASK 0x80UL /**< Bit mask for LCD_SEGD3L */ 474 #define _LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 475 #define LCD_SYNCBUSY_SEGD3L_DEFAULT (_LCD_SYNCBUSY_SEGD3L_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 476 #define LCD_SYNCBUSY_SEGD0H (0x1UL << 8) /**< SEGD0H Register Busy */ 477 #define _LCD_SYNCBUSY_SEGD0H_SHIFT 8 /**< Shift value for LCD_SEGD0H */ 478 #define _LCD_SYNCBUSY_SEGD0H_MASK 0x100UL /**< Bit mask for LCD_SEGD0H */ 479 #define _LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 480 #define LCD_SYNCBUSY_SEGD0H_DEFAULT (_LCD_SYNCBUSY_SEGD0H_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 481 #define LCD_SYNCBUSY_SEGD1H (0x1UL << 9) /**< SEGD1H Register Busy */ 482 #define _LCD_SYNCBUSY_SEGD1H_SHIFT 9 /**< Shift value for LCD_SEGD1H */ 483 #define _LCD_SYNCBUSY_SEGD1H_MASK 0x200UL /**< Bit mask for LCD_SEGD1H */ 484 #define _LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 485 #define LCD_SYNCBUSY_SEGD1H_DEFAULT (_LCD_SYNCBUSY_SEGD1H_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 486 #define LCD_SYNCBUSY_SEGD2H (0x1UL << 10) /**< SEGD2H Register Busy */ 487 #define _LCD_SYNCBUSY_SEGD2H_SHIFT 10 /**< Shift value for LCD_SEGD2H */ 488 #define _LCD_SYNCBUSY_SEGD2H_MASK 0x400UL /**< Bit mask for LCD_SEGD2H */ 489 #define _LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 490 #define LCD_SYNCBUSY_SEGD2H_DEFAULT (_LCD_SYNCBUSY_SEGD2H_DEFAULT << 10) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 491 #define LCD_SYNCBUSY_SEGD3H (0x1UL << 11) /**< SEGD3H Register Busy */ 492 #define _LCD_SYNCBUSY_SEGD3H_SHIFT 11 /**< Shift value for LCD_SEGD3H */ 493 #define _LCD_SYNCBUSY_SEGD3H_MASK 0x800UL /**< Bit mask for LCD_SEGD3H */ 494 #define _LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 495 #define LCD_SYNCBUSY_SEGD3H_DEFAULT (_LCD_SYNCBUSY_SEGD3H_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 496 #define LCD_SYNCBUSY_SEGD4H (0x1UL << 12) /**< SEGD4H Register Busy */ 497 #define _LCD_SYNCBUSY_SEGD4H_SHIFT 12 /**< Shift value for LCD_SEGD4H */ 498 #define _LCD_SYNCBUSY_SEGD4H_MASK 0x1000UL /**< Bit mask for LCD_SEGD4H */ 499 #define _LCD_SYNCBUSY_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 500 #define LCD_SYNCBUSY_SEGD4H_DEFAULT (_LCD_SYNCBUSY_SEGD4H_DEFAULT << 12) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 501 #define LCD_SYNCBUSY_SEGD5H (0x1UL << 13) /**< SEGD5H Register Busy */ 502 #define _LCD_SYNCBUSY_SEGD5H_SHIFT 13 /**< Shift value for LCD_SEGD5H */ 503 #define _LCD_SYNCBUSY_SEGD5H_MASK 0x2000UL /**< Bit mask for LCD_SEGD5H */ 504 #define _LCD_SYNCBUSY_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 505 #define LCD_SYNCBUSY_SEGD5H_DEFAULT (_LCD_SYNCBUSY_SEGD5H_DEFAULT << 13) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 506 #define LCD_SYNCBUSY_SEGD6H (0x1UL << 14) /**< SEGD6H Register Busy */ 507 #define _LCD_SYNCBUSY_SEGD6H_SHIFT 14 /**< Shift value for LCD_SEGD6H */ 508 #define _LCD_SYNCBUSY_SEGD6H_MASK 0x4000UL /**< Bit mask for LCD_SEGD6H */ 509 #define _LCD_SYNCBUSY_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 510 #define LCD_SYNCBUSY_SEGD6H_DEFAULT (_LCD_SYNCBUSY_SEGD6H_DEFAULT << 14) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 511 #define LCD_SYNCBUSY_SEGD7H (0x1UL << 15) /**< SEGD7H Register Busy */ 512 #define _LCD_SYNCBUSY_SEGD7H_SHIFT 15 /**< Shift value for LCD_SEGD7H */ 513 #define _LCD_SYNCBUSY_SEGD7H_MASK 0x8000UL /**< Bit mask for LCD_SEGD7H */ 514 #define _LCD_SYNCBUSY_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 515 #define LCD_SYNCBUSY_SEGD7H_DEFAULT (_LCD_SYNCBUSY_SEGD7H_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 516 #define LCD_SYNCBUSY_SEGD4L (0x1UL << 16) /**< SEGD4L Register Busy */ 517 #define _LCD_SYNCBUSY_SEGD4L_SHIFT 16 /**< Shift value for LCD_SEGD4L */ 518 #define _LCD_SYNCBUSY_SEGD4L_MASK 0x10000UL /**< Bit mask for LCD_SEGD4L */ 519 #define _LCD_SYNCBUSY_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 520 #define LCD_SYNCBUSY_SEGD4L_DEFAULT (_LCD_SYNCBUSY_SEGD4L_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 521 #define LCD_SYNCBUSY_SEGD5L (0x1UL << 17) /**< SEGD5L Register Busy */ 522 #define _LCD_SYNCBUSY_SEGD5L_SHIFT 17 /**< Shift value for LCD_SEGD5L */ 523 #define _LCD_SYNCBUSY_SEGD5L_MASK 0x20000UL /**< Bit mask for LCD_SEGD5L */ 524 #define _LCD_SYNCBUSY_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 525 #define LCD_SYNCBUSY_SEGD5L_DEFAULT (_LCD_SYNCBUSY_SEGD5L_DEFAULT << 17) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 526 #define LCD_SYNCBUSY_SEGD6L (0x1UL << 18) /**< SEGD6L Register Busy */ 527 #define _LCD_SYNCBUSY_SEGD6L_SHIFT 18 /**< Shift value for LCD_SEGD6L */ 528 #define _LCD_SYNCBUSY_SEGD6L_MASK 0x40000UL /**< Bit mask for LCD_SEGD6L */ 529 #define _LCD_SYNCBUSY_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 530 #define LCD_SYNCBUSY_SEGD6L_DEFAULT (_LCD_SYNCBUSY_SEGD6L_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 531 #define LCD_SYNCBUSY_SEGD7L (0x1UL << 19) /**< SEGD7L Register Busy */ 532 #define _LCD_SYNCBUSY_SEGD7L_SHIFT 19 /**< Shift value for LCD_SEGD7L */ 533 #define _LCD_SYNCBUSY_SEGD7L_MASK 0x80000UL /**< Bit mask for LCD_SEGD7L */ 534 #define _LCD_SYNCBUSY_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ 535 #define LCD_SYNCBUSY_SEGD7L_DEFAULT (_LCD_SYNCBUSY_SEGD7L_DEFAULT << 19) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ 536 537 /* Bit fields for LCD SEGD4H */ 538 #define _LCD_SEGD4H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4H */ 539 #define _LCD_SEGD4H_MASK 0x000000FFUL /**< Mask for LCD_SEGD4H */ 540 #define _LCD_SEGD4H_SEGD4H_SHIFT 0 /**< Shift value for LCD_SEGD4H */ 541 #define _LCD_SEGD4H_SEGD4H_MASK 0xFFUL /**< Bit mask for LCD_SEGD4H */ 542 #define _LCD_SEGD4H_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4H */ 543 #define LCD_SEGD4H_SEGD4H_DEFAULT (_LCD_SEGD4H_SEGD4H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4H */ 544 545 /* Bit fields for LCD SEGD5H */ 546 #define _LCD_SEGD5H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5H */ 547 #define _LCD_SEGD5H_MASK 0x000000FFUL /**< Mask for LCD_SEGD5H */ 548 #define _LCD_SEGD5H_SEGD5H_SHIFT 0 /**< Shift value for LCD_SEGD5H */ 549 #define _LCD_SEGD5H_SEGD5H_MASK 0xFFUL /**< Bit mask for LCD_SEGD5H */ 550 #define _LCD_SEGD5H_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5H */ 551 #define LCD_SEGD5H_SEGD5H_DEFAULT (_LCD_SEGD5H_SEGD5H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5H */ 552 553 /* Bit fields for LCD SEGD6H */ 554 #define _LCD_SEGD6H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6H */ 555 #define _LCD_SEGD6H_MASK 0x000000FFUL /**< Mask for LCD_SEGD6H */ 556 #define _LCD_SEGD6H_SEGD6H_SHIFT 0 /**< Shift value for LCD_SEGD6H */ 557 #define _LCD_SEGD6H_SEGD6H_MASK 0xFFUL /**< Bit mask for LCD_SEGD6H */ 558 #define _LCD_SEGD6H_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6H */ 559 #define LCD_SEGD6H_SEGD6H_DEFAULT (_LCD_SEGD6H_SEGD6H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6H */ 560 561 /* Bit fields for LCD SEGD7H */ 562 #define _LCD_SEGD7H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7H */ 563 #define _LCD_SEGD7H_MASK 0x000000FFUL /**< Mask for LCD_SEGD7H */ 564 #define _LCD_SEGD7H_SEGD7H_SHIFT 0 /**< Shift value for LCD_SEGD7H */ 565 #define _LCD_SEGD7H_SEGD7H_MASK 0xFFUL /**< Bit mask for LCD_SEGD7H */ 566 #define _LCD_SEGD7H_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7H */ 567 #define LCD_SEGD7H_SEGD7H_DEFAULT (_LCD_SEGD7H_SEGD7H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7H */ 568 569 /* Bit fields for LCD SEGD4L */ 570 #define _LCD_SEGD4L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4L */ 571 #define _LCD_SEGD4L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD4L */ 572 #define _LCD_SEGD4L_SEGD4L_SHIFT 0 /**< Shift value for LCD_SEGD4L */ 573 #define _LCD_SEGD4L_SEGD4L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD4L */ 574 #define _LCD_SEGD4L_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4L */ 575 #define LCD_SEGD4L_SEGD4L_DEFAULT (_LCD_SEGD4L_SEGD4L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4L */ 576 577 /* Bit fields for LCD SEGD5L */ 578 #define _LCD_SEGD5L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5L */ 579 #define _LCD_SEGD5L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD5L */ 580 #define _LCD_SEGD5L_SEGD5L_SHIFT 0 /**< Shift value for LCD_SEGD5L */ 581 #define _LCD_SEGD5L_SEGD5L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD5L */ 582 #define _LCD_SEGD5L_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5L */ 583 #define LCD_SEGD5L_SEGD5L_DEFAULT (_LCD_SEGD5L_SEGD5L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5L */ 584 585 /* Bit fields for LCD SEGD6L */ 586 #define _LCD_SEGD6L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6L */ 587 #define _LCD_SEGD6L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD6L */ 588 #define _LCD_SEGD6L_SEGD6L_SHIFT 0 /**< Shift value for LCD_SEGD6L */ 589 #define _LCD_SEGD6L_SEGD6L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD6L */ 590 #define _LCD_SEGD6L_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6L */ 591 #define LCD_SEGD6L_SEGD6L_DEFAULT (_LCD_SEGD6L_SEGD6L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6L */ 592 593 /* Bit fields for LCD SEGD7L */ 594 #define _LCD_SEGD7L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7L */ 595 #define _LCD_SEGD7L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD7L */ 596 #define _LCD_SEGD7L_SEGD7L_SHIFT 0 /**< Shift value for LCD_SEGD7L */ 597 #define _LCD_SEGD7L_SEGD7L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD7L */ 598 #define _LCD_SEGD7L_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7L */ 599 #define LCD_SEGD7L_SEGD7L_DEFAULT (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7L */ 600 601 /** @} End of group EFM32WG_LCD */ 602 /** @} End of group Parts */ 603
