1 /***************************************************************************//** 2 * @file 3 * @brief EFM32HG_MSC register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32HG_MSC 43 * @{ 44 * @brief EFM32HG_MSC Register Declaration 45 ******************************************************************************/ 46 typedef struct { 47 __IOM uint32_t CTRL; /**< Memory System Control Register */ 48 __IOM uint32_t READCTRL; /**< Read Control Register */ 49 __IOM uint32_t WRITECTRL; /**< Write Control Register */ 50 __IOM uint32_t WRITECMD; /**< Write Command Register */ 51 __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ 52 53 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 54 __IOM uint32_t WDATA; /**< Write Data Register */ 55 __IM uint32_t STATUS; /**< Status Register */ 56 57 uint32_t RESERVED1[3U]; /**< Reserved for future use **/ 58 __IM uint32_t IF; /**< Interrupt Flag Register */ 59 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 60 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 61 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 62 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 63 __IOM uint32_t CMD; /**< Command Register */ 64 __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ 65 __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ 66 uint32_t RESERVED2[1U]; /**< Reserved for future use **/ 67 __IOM uint32_t TIMEBASE; /**< Flash Write and Erase Timebase */ 68 __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ 69 __IOM uint32_t IRQLATENCY; /**< Irq Latency Register */ 70 } MSC_TypeDef; /**< MSC Register Declaration *//** @} */ 71 72 /***************************************************************************//** 73 * @defgroup EFM32HG_MSC_BitFields 74 * @{ 75 ******************************************************************************/ 76 77 /* Bit fields for MSC CTRL */ 78 #define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */ 79 #define _MSC_CTRL_MASK 0x00000001UL /**< Mask for MSC_CTRL */ 80 #define MSC_CTRL_BUSFAULT (0x1UL << 0) /**< Bus Fault Response Enable */ 81 #define _MSC_CTRL_BUSFAULT_SHIFT 0 /**< Shift value for MSC_BUSFAULT */ 82 #define _MSC_CTRL_BUSFAULT_MASK 0x1UL /**< Bit mask for MSC_BUSFAULT */ 83 #define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL /**< Mode GENERATE for MSC_CTRL */ 84 #define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ 85 #define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL /**< Mode IGNORE for MSC_CTRL */ 86 #define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0) /**< Shifted mode GENERATE for MSC_CTRL */ 87 #define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ 88 #define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0) /**< Shifted mode IGNORE for MSC_CTRL */ 89 90 /* Bit fields for MSC READCTRL */ 91 #define _MSC_READCTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_READCTRL */ 92 #define _MSC_READCTRL_MASK 0x0000009FUL /**< Mask for MSC_READCTRL */ 93 #define _MSC_READCTRL_MODE_SHIFT 0 /**< Shift value for MSC_MODE */ 94 #define _MSC_READCTRL_MODE_MASK 0x7UL /**< Bit mask for MSC_MODE */ 95 #define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ 96 #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ 97 #define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ 98 #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0) /**< Shifted mode WS0 for MSC_READCTRL */ 99 #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_READCTRL */ 100 #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0) /**< Shifted mode WS1 for MSC_READCTRL */ 101 #define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ 102 #define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ 103 #define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ 104 #define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 105 #define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ 106 #define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ 107 #define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ 108 #define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ 109 #define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 110 #define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ 111 #define MSC_READCTRL_RAMCEN (0x1UL << 7) /**< RAM Cache Enable */ 112 #define _MSC_READCTRL_RAMCEN_SHIFT 7 /**< Shift value for MSC_RAMCEN */ 113 #define _MSC_READCTRL_RAMCEN_MASK 0x80UL /**< Bit mask for MSC_RAMCEN */ 114 #define _MSC_READCTRL_RAMCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 115 #define MSC_READCTRL_RAMCEN_DEFAULT (_MSC_READCTRL_RAMCEN_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_READCTRL */ 116 117 /* Bit fields for MSC WRITECTRL */ 118 #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ 119 #define _MSC_WRITECTRL_MASK 0x00000003UL /**< Mask for MSC_WRITECTRL */ 120 #define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ 121 #define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ 122 #define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ 123 #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ 124 #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ 125 #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ 126 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ 127 #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ 128 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ 129 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ 130 131 /* Bit fields for MSC WRITECMD */ 132 #define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ 133 #define _MSC_WRITECMD_MASK 0x0000113FUL /**< Mask for MSC_WRITECMD */ 134 #define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */ 135 #define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ 136 #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ 137 #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 138 #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 139 #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ 140 #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ 141 #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ 142 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 143 #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 144 #define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ 145 #define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ 146 #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ 147 #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 148 #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 149 #define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ 150 #define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ 151 #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ 152 #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 153 #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 154 #define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ 155 #define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ 156 #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ 157 #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 158 #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 159 #define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ 160 #define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ 161 #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ 162 #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 163 #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 164 #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ 165 #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ 166 #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ 167 #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 168 #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 169 #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ 170 #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ 171 #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ 172 #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 173 #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 174 175 /* Bit fields for MSC ADDRB */ 176 #define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ 177 #define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ 178 #define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ 179 #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ 180 #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ 181 #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ 182 183 /* Bit fields for MSC WDATA */ 184 #define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ 185 #define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ 186 #define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ 187 #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ 188 #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ 189 #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ 190 191 /* Bit fields for MSC STATUS */ 192 #define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ 193 #define _MSC_STATUS_MASK 0x0000007FUL /**< Mask for MSC_STATUS */ 194 #define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ 195 #define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ 196 #define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ 197 #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 198 #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ 199 #define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ 200 #define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ 201 #define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ 202 #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 203 #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ 204 #define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ 205 #define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ 206 #define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ 207 #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 208 #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ 209 #define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ 210 #define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ 211 #define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ 212 #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ 213 #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ 214 #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ 215 #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ 216 #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ 217 #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 218 #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ 219 #define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ 220 #define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ 221 #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ 222 #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 223 #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ 224 #define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ 225 #define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ 226 #define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ 227 #define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 228 #define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ 229 230 /* Bit fields for MSC IF */ 231 #define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ 232 #define _MSC_IF_MASK 0x0000000FUL /**< Mask for MSC_IF */ 233 #define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ 234 #define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ 235 #define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ 236 #define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 237 #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ 238 #define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ 239 #define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ 240 #define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ 241 #define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 242 #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ 243 #define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ 244 #define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ 245 #define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ 246 #define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 247 #define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ 248 #define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ 249 #define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ 250 #define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ 251 #define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 252 #define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ 253 254 /* Bit fields for MSC IFS */ 255 #define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ 256 #define _MSC_IFS_MASK 0x0000000FUL /**< Mask for MSC_IFS */ 257 #define MSC_IFS_ERASE (0x1UL << 0) /**< Erase Done Interrupt Set */ 258 #define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ 259 #define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ 260 #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 261 #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ 262 #define MSC_IFS_WRITE (0x1UL << 1) /**< Write Done Interrupt Set */ 263 #define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ 264 #define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ 265 #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 266 #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ 267 #define MSC_IFS_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Set */ 268 #define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ 269 #define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ 270 #define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 271 #define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ 272 #define MSC_IFS_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Set */ 273 #define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ 274 #define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ 275 #define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 276 #define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ 277 278 /* Bit fields for MSC IFC */ 279 #define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ 280 #define _MSC_IFC_MASK 0x0000000FUL /**< Mask for MSC_IFC */ 281 #define MSC_IFC_ERASE (0x1UL << 0) /**< Erase Done Interrupt Clear */ 282 #define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ 283 #define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ 284 #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 285 #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ 286 #define MSC_IFC_WRITE (0x1UL << 1) /**< Write Done Interrupt Clear */ 287 #define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ 288 #define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ 289 #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 290 #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ 291 #define MSC_IFC_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Clear */ 292 #define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ 293 #define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ 294 #define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 295 #define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ 296 #define MSC_IFC_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Clear */ 297 #define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ 298 #define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ 299 #define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 300 #define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ 301 302 /* Bit fields for MSC IEN */ 303 #define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ 304 #define _MSC_IEN_MASK 0x0000000FUL /**< Mask for MSC_IEN */ 305 #define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt Enable */ 306 #define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ 307 #define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ 308 #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 309 #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ 310 #define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt Enable */ 311 #define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ 312 #define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ 313 #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 314 #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ 315 #define MSC_IEN_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Enable */ 316 #define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ 317 #define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ 318 #define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 319 #define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ 320 #define MSC_IEN_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Enable */ 321 #define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ 322 #define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ 323 #define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 324 #define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ 325 326 /* Bit fields for MSC LOCK */ 327 #define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ 328 #define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ 329 #define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ 330 #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ 331 #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ 332 #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ 333 #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ 334 #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ 335 #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ 336 #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ 337 #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ 338 #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ 339 #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ 340 #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ 341 342 /* Bit fields for MSC CMD */ 343 #define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ 344 #define _MSC_CMD_MASK 0x00000007UL /**< Mask for MSC_CMD */ 345 #define MSC_CMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ 346 #define _MSC_CMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ 347 #define _MSC_CMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ 348 #define _MSC_CMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ 349 #define MSC_CMD_INVCACHE_DEFAULT (_MSC_CMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ 350 #define MSC_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ 351 #define _MSC_CMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ 352 #define _MSC_CMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ 353 #define _MSC_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ 354 #define MSC_CMD_STARTPC_DEFAULT (_MSC_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ 355 #define MSC_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ 356 #define _MSC_CMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ 357 #define _MSC_CMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ 358 #define _MSC_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ 359 #define MSC_CMD_STOPPC_DEFAULT (_MSC_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CMD */ 360 361 /* Bit fields for MSC CACHEHITS */ 362 #define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ 363 #define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ 364 #define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ 365 #define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ 366 #define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ 367 #define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ 368 369 /* Bit fields for MSC CACHEMISSES */ 370 #define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ 371 #define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ 372 #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ 373 #define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ 374 #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ 375 #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ 376 377 /* Bit fields for MSC TIMEBASE */ 378 #define _MSC_TIMEBASE_RESETVALUE 0x00000010UL /**< Default value for MSC_TIMEBASE */ 379 #define _MSC_TIMEBASE_MASK 0x0001003FUL /**< Mask for MSC_TIMEBASE */ 380 #define _MSC_TIMEBASE_BASE_SHIFT 0 /**< Shift value for MSC_BASE */ 381 #define _MSC_TIMEBASE_BASE_MASK 0x3FUL /**< Bit mask for MSC_BASE */ 382 #define _MSC_TIMEBASE_BASE_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_TIMEBASE */ 383 #define MSC_TIMEBASE_BASE_DEFAULT (_MSC_TIMEBASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_TIMEBASE */ 384 #define MSC_TIMEBASE_PERIOD (0x1UL << 16) /**< Sets the timebase period */ 385 #define _MSC_TIMEBASE_PERIOD_SHIFT 16 /**< Shift value for MSC_PERIOD */ 386 #define _MSC_TIMEBASE_PERIOD_MASK 0x10000UL /**< Bit mask for MSC_PERIOD */ 387 #define _MSC_TIMEBASE_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_TIMEBASE */ 388 #define _MSC_TIMEBASE_PERIOD_1US 0x00000000UL /**< Mode 1US for MSC_TIMEBASE */ 389 #define _MSC_TIMEBASE_PERIOD_5US 0x00000001UL /**< Mode 5US for MSC_TIMEBASE */ 390 #define MSC_TIMEBASE_PERIOD_DEFAULT (_MSC_TIMEBASE_PERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_TIMEBASE */ 391 #define MSC_TIMEBASE_PERIOD_1US (_MSC_TIMEBASE_PERIOD_1US << 16) /**< Shifted mode 1US for MSC_TIMEBASE */ 392 #define MSC_TIMEBASE_PERIOD_5US (_MSC_TIMEBASE_PERIOD_5US << 16) /**< Shifted mode 5US for MSC_TIMEBASE */ 393 394 /* Bit fields for MSC MASSLOCK */ 395 #define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ 396 #define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ 397 #define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ 398 #define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ 399 #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ 400 #define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ 401 #define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ 402 #define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ 403 #define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ 404 #define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ 405 #define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ 406 #define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ 407 #define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ 408 #define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ 409 410 /* Bit fields for MSC IRQLATENCY */ 411 #define _MSC_IRQLATENCY_RESETVALUE 0x00000000UL /**< Default value for MSC_IRQLATENCY */ 412 #define _MSC_IRQLATENCY_MASK 0x000000FFUL /**< Mask for MSC_IRQLATENCY */ 413 #define _MSC_IRQLATENCY_IRQLATENCY_SHIFT 0 /**< Shift value for MSC_IRQLATENCY */ 414 #define _MSC_IRQLATENCY_IRQLATENCY_MASK 0xFFUL /**< Bit mask for MSC_IRQLATENCY */ 415 #define _MSC_IRQLATENCY_IRQLATENCY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IRQLATENCY */ 416 #define MSC_IRQLATENCY_IRQLATENCY_DEFAULT (_MSC_IRQLATENCY_IRQLATENCY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IRQLATENCY */ 417 418 /** @} End of group EFM32HG_MSC */ 419 /** @} End of group Parts */ 420
