1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG11B_LEUART register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG11B_LEUART LEUART 43 * @{ 44 * @brief EFM32GG11B_LEUART Register Declaration 45 ******************************************************************************/ 46 /** LEUART Register Declaration */ 47 typedef struct { 48 __IOM uint32_t CTRL; /**< Control Register */ 49 __IOM uint32_t CMD; /**< Command Register */ 50 __IM uint32_t STATUS; /**< Status Register */ 51 __IOM uint32_t CLKDIV; /**< Clock Control Register */ 52 __IOM uint32_t STARTFRAME; /**< Start Frame Register */ 53 __IOM uint32_t SIGFRAME; /**< Signal Frame Register */ 54 __IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */ 55 __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ 56 __IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */ 57 __IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */ 58 __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ 59 __IM uint32_t IF; /**< Interrupt Flag Register */ 60 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 61 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 62 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 63 __IOM uint32_t PULSECTRL; /**< Pulse Control Register */ 64 65 __IOM uint32_t FREEZE; /**< Freeze Register */ 66 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 67 68 uint32_t RESERVED0[3U]; /**< Reserved for future use **/ 69 __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ 70 __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ 71 uint32_t RESERVED1[2U]; /**< Reserved for future use **/ 72 __IOM uint32_t INPUT; /**< LEUART Input Register */ 73 } LEUART_TypeDef; /** @} */ 74 75 /***************************************************************************//** 76 * @addtogroup EFM32GG11B_LEUART 77 * @{ 78 * @defgroup EFM32GG11B_LEUART_BitFields LEUART Bit Fields 79 * @{ 80 ******************************************************************************/ 81 82 /* Bit fields for LEUART CTRL */ 83 #define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */ 84 #define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */ 85 #define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */ 86 #define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */ 87 #define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */ 88 #define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ 89 #define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */ 90 #define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */ 91 #define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */ 92 #define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */ 93 #define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ 94 #define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */ 95 #define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */ 96 #define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */ 97 #define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */ 98 #define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */ 99 #define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */ 100 #define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */ 101 #define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ 102 #define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ 103 #define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */ 104 #define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */ 105 #define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */ 106 #define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */ 107 #define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */ 108 #define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */ 109 #define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */ 110 #define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */ 111 #define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */ 112 #define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ 113 #define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */ 114 #define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */ 115 #define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */ 116 #define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */ 117 #define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */ 118 #define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input and Output */ 119 #define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */ 120 #define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */ 121 #define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ 122 #define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */ 123 #define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA on Error */ 124 #define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */ 125 #define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */ 126 #define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ 127 #define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */ 128 #define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */ 129 #define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */ 130 #define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */ 131 #define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ 132 #define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */ 133 #define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */ 134 #define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */ 135 #define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */ 136 #define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ 137 #define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */ 138 #define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */ 139 #define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */ 140 #define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */ 141 #define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ 142 #define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */ 143 #define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */ 144 #define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */ 145 #define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */ 146 #define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ 147 #define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */ 148 #define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */ 149 #define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */ 150 #define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */ 151 #define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ 152 #define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */ 153 #define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */ 154 #define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */ 155 #define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */ 156 #define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ 157 #define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */ 158 #define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */ 159 #define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */ 160 #define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */ 161 #define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ 162 #define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */ 163 #define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */ 164 #define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */ 165 #define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */ 166 #define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */ 167 #define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */ 168 #define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */ 169 #define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */ 170 #define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */ 171 #define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */ 172 #define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */ 173 #define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */ 174 #define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */ 175 176 /* Bit fields for LEUART CMD */ 177 #define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */ 178 #define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */ 179 #define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ 180 #define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */ 181 #define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */ 182 #define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ 183 #define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */ 184 #define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ 185 #define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */ 186 #define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */ 187 #define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ 188 #define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */ 189 #define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ 190 #define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */ 191 #define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */ 192 #define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ 193 #define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */ 194 #define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ 195 #define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */ 196 #define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */ 197 #define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ 198 #define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */ 199 #define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ 200 #define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */ 201 #define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */ 202 #define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ 203 #define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */ 204 #define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ 205 #define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */ 206 #define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */ 207 #define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ 208 #define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */ 209 #define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ 210 #define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */ 211 #define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */ 212 #define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ 213 #define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */ 214 #define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */ 215 #define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */ 216 #define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */ 217 #define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */ 218 #define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */ 219 220 /* Bit fields for LEUART STATUS */ 221 #define _LEUART_STATUS_RESETVALUE 0x00000050UL /**< Default value for LEUART_STATUS */ 222 #define _LEUART_STATUS_MASK 0x0000007FUL /**< Mask for LEUART_STATUS */ 223 #define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ 224 #define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */ 225 #define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */ 226 #define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ 227 #define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */ 228 #define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ 229 #define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */ 230 #define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */ 231 #define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ 232 #define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */ 233 #define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */ 234 #define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */ 235 #define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */ 236 #define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ 237 #define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */ 238 #define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */ 239 #define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */ 240 #define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */ 241 #define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ 242 #define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */ 243 #define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */ 244 #define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */ 245 #define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */ 246 #define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ 247 #define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */ 248 #define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */ 249 #define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */ 250 #define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */ 251 #define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */ 252 #define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */ 253 #define LEUART_STATUS_TXIDLE (0x1UL << 6) /**< TX Idle */ 254 #define _LEUART_STATUS_TXIDLE_SHIFT 6 /**< Shift value for LEUART_TXIDLE */ 255 #define _LEUART_STATUS_TXIDLE_MASK 0x40UL /**< Bit mask for LEUART_TXIDLE */ 256 #define _LEUART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */ 257 #define LEUART_STATUS_TXIDLE_DEFAULT (_LEUART_STATUS_TXIDLE_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_STATUS */ 258 259 /* Bit fields for LEUART CLKDIV */ 260 #define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */ 261 #define _LEUART_CLKDIV_MASK 0x0001FFF8UL /**< Mask for LEUART_CLKDIV */ 262 #define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */ 263 #define _LEUART_CLKDIV_DIV_MASK 0x1FFF8UL /**< Bit mask for LEUART_DIV */ 264 #define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */ 265 #define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */ 266 267 /* Bit fields for LEUART STARTFRAME */ 268 #define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */ 269 #define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */ 270 #define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */ 271 #define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */ 272 #define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */ 273 #define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */ 274 275 /* Bit fields for LEUART SIGFRAME */ 276 #define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */ 277 #define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */ 278 #define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */ 279 #define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */ 280 #define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */ 281 #define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */ 282 283 /* Bit fields for LEUART RXDATAX */ 284 #define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */ 285 #define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */ 286 #define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ 287 #define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */ 288 #define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ 289 #define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ 290 #define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */ 291 #define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */ 292 #define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */ 293 #define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ 294 #define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ 295 #define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */ 296 #define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */ 297 #define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */ 298 #define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */ 299 #define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */ 300 301 /* Bit fields for LEUART RXDATA */ 302 #define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */ 303 #define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */ 304 #define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */ 305 #define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */ 306 #define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */ 307 #define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */ 308 309 /* Bit fields for LEUART RXDATAXP */ 310 #define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */ 311 #define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */ 312 #define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */ 313 #define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */ 314 #define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ 315 #define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ 316 #define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */ 317 #define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */ 318 #define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */ 319 #define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ 320 #define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ 321 #define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */ 322 #define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */ 323 #define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */ 324 #define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */ 325 #define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */ 326 327 /* Bit fields for LEUART TXDATAX */ 328 #define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */ 329 #define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */ 330 #define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ 331 #define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */ 332 #define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ 333 #define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ 334 #define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */ 335 #define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */ 336 #define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */ 337 #define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ 338 #define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ 339 #define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */ 340 #define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */ 341 #define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */ 342 #define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ 343 #define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ 344 #define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ 345 #define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */ 346 #define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */ 347 #define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */ 348 #define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */ 349 350 /* Bit fields for LEUART TXDATA */ 351 #define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */ 352 #define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */ 353 #define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */ 354 #define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */ 355 #define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */ 356 #define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */ 357 358 /* Bit fields for LEUART IF */ 359 #define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */ 360 #define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */ 361 #define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ 362 #define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ 363 #define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ 364 #define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ 365 #define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */ 366 #define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ 367 #define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ 368 #define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ 369 #define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */ 370 #define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */ 371 #define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ 372 #define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ 373 #define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ 374 #define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ 375 #define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */ 376 #define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */ 377 #define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ 378 #define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ 379 #define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ 380 #define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */ 381 #define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */ 382 #define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ 383 #define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ 384 #define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ 385 #define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */ 386 #define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */ 387 #define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ 388 #define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ 389 #define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ 390 #define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */ 391 #define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */ 392 #define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ 393 #define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ 394 #define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ 395 #define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */ 396 #define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */ 397 #define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ 398 #define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ 399 #define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ 400 #define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */ 401 #define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */ 402 #define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ 403 #define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ 404 #define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ 405 #define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */ 406 #define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */ 407 #define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ 408 #define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ 409 #define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ 410 #define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */ 411 #define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */ 412 #define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ 413 #define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ 414 #define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */ 415 #define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */ 416 417 /* Bit fields for LEUART IFS */ 418 #define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */ 419 #define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */ 420 #define LEUART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ 421 #define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ 422 #define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ 423 #define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ 424 #define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */ 425 #define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RXOF Interrupt Flag */ 426 #define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ 427 #define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ 428 #define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ 429 #define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */ 430 #define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RXUF Interrupt Flag */ 431 #define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ 432 #define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ 433 #define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ 434 #define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */ 435 #define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TXOF Interrupt Flag */ 436 #define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ 437 #define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ 438 #define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ 439 #define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */ 440 #define LEUART_IFS_PERR (0x1UL << 6) /**< Set PERR Interrupt Flag */ 441 #define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ 442 #define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ 443 #define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ 444 #define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */ 445 #define LEUART_IFS_FERR (0x1UL << 7) /**< Set FERR Interrupt Flag */ 446 #define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ 447 #define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ 448 #define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ 449 #define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */ 450 #define LEUART_IFS_MPAF (0x1UL << 8) /**< Set MPAF Interrupt Flag */ 451 #define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ 452 #define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ 453 #define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ 454 #define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */ 455 #define LEUART_IFS_STARTF (0x1UL << 9) /**< Set STARTF Interrupt Flag */ 456 #define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ 457 #define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ 458 #define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ 459 #define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */ 460 #define LEUART_IFS_SIGF (0x1UL << 10) /**< Set SIGF Interrupt Flag */ 461 #define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ 462 #define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ 463 #define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */ 464 #define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */ 465 466 /* Bit fields for LEUART IFC */ 467 #define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */ 468 #define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */ 469 #define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ 470 #define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ 471 #define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ 472 #define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ 473 #define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */ 474 #define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RXOF Interrupt Flag */ 475 #define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ 476 #define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ 477 #define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ 478 #define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */ 479 #define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RXUF Interrupt Flag */ 480 #define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ 481 #define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ 482 #define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ 483 #define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */ 484 #define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TXOF Interrupt Flag */ 485 #define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ 486 #define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ 487 #define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ 488 #define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */ 489 #define LEUART_IFC_PERR (0x1UL << 6) /**< Clear PERR Interrupt Flag */ 490 #define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ 491 #define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ 492 #define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ 493 #define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */ 494 #define LEUART_IFC_FERR (0x1UL << 7) /**< Clear FERR Interrupt Flag */ 495 #define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ 496 #define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ 497 #define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ 498 #define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */ 499 #define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear MPAF Interrupt Flag */ 500 #define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ 501 #define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ 502 #define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ 503 #define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */ 504 #define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear STARTF Interrupt Flag */ 505 #define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ 506 #define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ 507 #define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ 508 #define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */ 509 #define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear SIGF Interrupt Flag */ 510 #define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ 511 #define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ 512 #define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */ 513 #define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */ 514 515 /* Bit fields for LEUART IEN */ 516 #define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */ 517 #define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */ 518 #define LEUART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ 519 #define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */ 520 #define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */ 521 #define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ 522 #define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */ 523 #define LEUART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ 524 #define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */ 525 #define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */ 526 #define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ 527 #define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */ 528 #define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ 529 #define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */ 530 #define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */ 531 #define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ 532 #define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */ 533 #define LEUART_IEN_RXOF (0x1UL << 3) /**< RXOF Interrupt Enable */ 534 #define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */ 535 #define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */ 536 #define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ 537 #define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */ 538 #define LEUART_IEN_RXUF (0x1UL << 4) /**< RXUF Interrupt Enable */ 539 #define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */ 540 #define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */ 541 #define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ 542 #define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */ 543 #define LEUART_IEN_TXOF (0x1UL << 5) /**< TXOF Interrupt Enable */ 544 #define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */ 545 #define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */ 546 #define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ 547 #define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */ 548 #define LEUART_IEN_PERR (0x1UL << 6) /**< PERR Interrupt Enable */ 549 #define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */ 550 #define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */ 551 #define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ 552 #define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */ 553 #define LEUART_IEN_FERR (0x1UL << 7) /**< FERR Interrupt Enable */ 554 #define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */ 555 #define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */ 556 #define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ 557 #define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */ 558 #define LEUART_IEN_MPAF (0x1UL << 8) /**< MPAF Interrupt Enable */ 559 #define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */ 560 #define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */ 561 #define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ 562 #define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */ 563 #define LEUART_IEN_STARTF (0x1UL << 9) /**< STARTF Interrupt Enable */ 564 #define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */ 565 #define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */ 566 #define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ 567 #define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */ 568 #define LEUART_IEN_SIGF (0x1UL << 10) /**< SIGF Interrupt Enable */ 569 #define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */ 570 #define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */ 571 #define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */ 572 #define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */ 573 574 /* Bit fields for LEUART PULSECTRL */ 575 #define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */ 576 #define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */ 577 #define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */ 578 #define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */ 579 #define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ 580 #define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ 581 #define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */ 582 #define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */ 583 #define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */ 584 #define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ 585 #define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ 586 #define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */ 587 #define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */ 588 #define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */ 589 #define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */ 590 #define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */ 591 592 /* Bit fields for LEUART FREEZE */ 593 #define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */ 594 #define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */ 595 #define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ 596 #define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */ 597 #define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */ 598 #define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */ 599 #define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */ 600 #define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */ 601 #define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */ 602 #define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */ 603 #define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */ 604 605 /* Bit fields for LEUART SYNCBUSY */ 606 #define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */ 607 #define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */ 608 #define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ 609 #define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */ 610 #define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */ 611 #define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ 612 #define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ 613 #define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ 614 #define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */ 615 #define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */ 616 #define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ 617 #define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ 618 #define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */ 619 #define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */ 620 #define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */ 621 #define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ 622 #define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ 623 #define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */ 624 #define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */ 625 #define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */ 626 #define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ 627 #define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ 628 #define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */ 629 #define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */ 630 #define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */ 631 #define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ 632 #define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ 633 #define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */ 634 #define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */ 635 #define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */ 636 #define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ 637 #define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ 638 #define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */ 639 #define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */ 640 #define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */ 641 #define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ 642 #define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ 643 #define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */ 644 #define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */ 645 #define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */ 646 #define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */ 647 #define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */ 648 649 /* Bit fields for LEUART ROUTEPEN */ 650 #define _LEUART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTEPEN */ 651 #define _LEUART_ROUTEPEN_MASK 0x00000003UL /**< Mask for LEUART_ROUTEPEN */ 652 #define LEUART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ 653 #define _LEUART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */ 654 #define _LEUART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */ 655 #define _LEUART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ 656 #define LEUART_ROUTEPEN_RXPEN_DEFAULT (_LEUART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ 657 #define LEUART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ 658 #define _LEUART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */ 659 #define _LEUART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */ 660 #define _LEUART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */ 661 #define LEUART_ROUTEPEN_TXPEN_DEFAULT (_LEUART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */ 662 663 /* Bit fields for LEUART ROUTELOC0 */ 664 #define _LEUART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTELOC0 */ 665 #define _LEUART_ROUTELOC0_MASK 0x00000707UL /**< Mask for LEUART_ROUTELOC0 */ 666 #define _LEUART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for LEUART_RXLOC */ 667 #define _LEUART_ROUTELOC0_RXLOC_MASK 0x7UL /**< Bit mask for LEUART_RXLOC */ 668 #define _LEUART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ 669 #define _LEUART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ 670 #define _LEUART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ 671 #define _LEUART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ 672 #define _LEUART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ 673 #define _LEUART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ 674 #define _LEUART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ 675 #define LEUART_ROUTELOC0_RXLOC_LOC0 (_LEUART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ 676 #define LEUART_ROUTELOC0_RXLOC_DEFAULT (_LEUART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ 677 #define LEUART_ROUTELOC0_RXLOC_LOC1 (_LEUART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ 678 #define LEUART_ROUTELOC0_RXLOC_LOC2 (_LEUART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ 679 #define LEUART_ROUTELOC0_RXLOC_LOC3 (_LEUART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ 680 #define LEUART_ROUTELOC0_RXLOC_LOC4 (_LEUART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ 681 #define LEUART_ROUTELOC0_RXLOC_LOC5 (_LEUART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ 682 #define _LEUART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for LEUART_TXLOC */ 683 #define _LEUART_ROUTELOC0_TXLOC_MASK 0x700UL /**< Bit mask for LEUART_TXLOC */ 684 #define _LEUART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */ 685 #define _LEUART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */ 686 #define _LEUART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */ 687 #define _LEUART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */ 688 #define _LEUART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */ 689 #define _LEUART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */ 690 #define _LEUART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */ 691 #define LEUART_ROUTELOC0_TXLOC_LOC0 (_LEUART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */ 692 #define LEUART_ROUTELOC0_TXLOC_DEFAULT (_LEUART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */ 693 #define LEUART_ROUTELOC0_TXLOC_LOC1 (_LEUART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */ 694 #define LEUART_ROUTELOC0_TXLOC_LOC2 (_LEUART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */ 695 #define LEUART_ROUTELOC0_TXLOC_LOC3 (_LEUART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */ 696 #define LEUART_ROUTELOC0_TXLOC_LOC4 (_LEUART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */ 697 #define LEUART_ROUTELOC0_TXLOC_LOC5 (_LEUART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */ 698 699 /* Bit fields for LEUART INPUT */ 700 #define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */ 701 #define _LEUART_INPUT_MASK 0x0000003FUL /**< Mask for LEUART_INPUT */ 702 #define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */ 703 #define _LEUART_INPUT_RXPRSSEL_MASK 0x1FUL /**< Bit mask for LEUART_RXPRSSEL */ 704 #define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ 705 #define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */ 706 #define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */ 707 #define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */ 708 #define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */ 709 #define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */ 710 #define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */ 711 #define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */ 712 #define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */ 713 #define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */ 714 #define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */ 715 #define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */ 716 #define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */ 717 #define _LEUART_INPUT_RXPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for LEUART_INPUT */ 718 #define _LEUART_INPUT_RXPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for LEUART_INPUT */ 719 #define _LEUART_INPUT_RXPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for LEUART_INPUT */ 720 #define _LEUART_INPUT_RXPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for LEUART_INPUT */ 721 #define _LEUART_INPUT_RXPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for LEUART_INPUT */ 722 #define _LEUART_INPUT_RXPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for LEUART_INPUT */ 723 #define _LEUART_INPUT_RXPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for LEUART_INPUT */ 724 #define _LEUART_INPUT_RXPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for LEUART_INPUT */ 725 #define _LEUART_INPUT_RXPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for LEUART_INPUT */ 726 #define _LEUART_INPUT_RXPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for LEUART_INPUT */ 727 #define _LEUART_INPUT_RXPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for LEUART_INPUT */ 728 #define _LEUART_INPUT_RXPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for LEUART_INPUT */ 729 #define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */ 730 #define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */ 731 #define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */ 732 #define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */ 733 #define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */ 734 #define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */ 735 #define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */ 736 #define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */ 737 #define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */ 738 #define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */ 739 #define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */ 740 #define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */ 741 #define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */ 742 #define LEUART_INPUT_RXPRSSEL_PRSCH12 (_LEUART_INPUT_RXPRSSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for LEUART_INPUT */ 743 #define LEUART_INPUT_RXPRSSEL_PRSCH13 (_LEUART_INPUT_RXPRSSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for LEUART_INPUT */ 744 #define LEUART_INPUT_RXPRSSEL_PRSCH14 (_LEUART_INPUT_RXPRSSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for LEUART_INPUT */ 745 #define LEUART_INPUT_RXPRSSEL_PRSCH15 (_LEUART_INPUT_RXPRSSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for LEUART_INPUT */ 746 #define LEUART_INPUT_RXPRSSEL_PRSCH16 (_LEUART_INPUT_RXPRSSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for LEUART_INPUT */ 747 #define LEUART_INPUT_RXPRSSEL_PRSCH17 (_LEUART_INPUT_RXPRSSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for LEUART_INPUT */ 748 #define LEUART_INPUT_RXPRSSEL_PRSCH18 (_LEUART_INPUT_RXPRSSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for LEUART_INPUT */ 749 #define LEUART_INPUT_RXPRSSEL_PRSCH19 (_LEUART_INPUT_RXPRSSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for LEUART_INPUT */ 750 #define LEUART_INPUT_RXPRSSEL_PRSCH20 (_LEUART_INPUT_RXPRSSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for LEUART_INPUT */ 751 #define LEUART_INPUT_RXPRSSEL_PRSCH21 (_LEUART_INPUT_RXPRSSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for LEUART_INPUT */ 752 #define LEUART_INPUT_RXPRSSEL_PRSCH22 (_LEUART_INPUT_RXPRSSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for LEUART_INPUT */ 753 #define LEUART_INPUT_RXPRSSEL_PRSCH23 (_LEUART_INPUT_RXPRSSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for LEUART_INPUT */ 754 #define LEUART_INPUT_RXPRS (0x1UL << 5) /**< PRS RX Enable */ 755 #define _LEUART_INPUT_RXPRS_SHIFT 5 /**< Shift value for LEUART_RXPRS */ 756 #define _LEUART_INPUT_RXPRS_MASK 0x20UL /**< Bit mask for LEUART_RXPRS */ 757 #define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */ 758 #define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_INPUT */ 759 760 /** @} */ 761 /** @} End of group EFM32GG11B_LEUART */ 762 /** @} End of group Parts */ 763
