1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG11B_LDMA register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG11B_LDMA LDMA 43 * @{ 44 * @brief EFM32GG11B_LDMA Register Declaration 45 ******************************************************************************/ 46 /** LDMA Register Declaration */ 47 typedef struct { 48 __IOM uint32_t CTRL; /**< DMA Control Register */ 49 __IM uint32_t STATUS; /**< DMA Status Register */ 50 __IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */ 51 uint32_t RESERVED0[5U]; /**< Reserved for future use **/ 52 __IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */ 53 __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ 54 __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */ 55 __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ 56 __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */ 57 __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ 58 __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ 59 __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ 60 __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ 61 uint32_t RESERVED1[7U]; /**< Reserved for future use **/ 62 __IM uint32_t IF; /**< Interrupt Flag Register */ 63 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 64 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 65 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 66 67 uint32_t RESERVED2[4U]; /**< Reserved registers */ 68 LDMA_CH_TypeDef CH[24U]; /**< DMA Channel Registers */ 69 } LDMA_TypeDef; /** @} */ 70 71 /***************************************************************************//** 72 * @addtogroup EFM32GG11B_LDMA 73 * @{ 74 * @defgroup EFM32GG11B_LDMA_BitFields LDMA Bit Fields 75 * @{ 76 ******************************************************************************/ 77 78 /* Bit fields for LDMA CTRL */ 79 #define _LDMA_CTRL_RESETVALUE 0x17000000UL /**< Default value for LDMA_CTRL */ 80 #define _LDMA_CTRL_MASK 0x1F00FFFFUL /**< Mask for LDMA_CTRL */ 81 #define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */ 82 #define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */ 83 #define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ 84 #define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */ 85 #define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */ 86 #define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */ 87 #define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ 88 #define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */ 89 #define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ 90 #define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */ 91 #define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000017UL /**< Mode DEFAULT for LDMA_CTRL */ 92 #define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ 93 94 /* Bit fields for LDMA STATUS */ 95 #define _LDMA_STATUS_RESETVALUE 0x18100000UL /**< Default value for LDMA_STATUS */ 96 #define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */ 97 #define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ 98 #define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ 99 #define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ 100 #define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ 101 #define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ 102 #define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ 103 #define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ 104 #define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ 105 #define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ 106 #define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ 107 #define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ 108 #define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */ 109 #define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ 110 #define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ 111 #define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ 112 #define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */ 113 #define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ 114 #define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ 115 #define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ 116 #define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ 117 #define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ 118 #define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ 119 #define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ 120 #define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ 121 #define _LDMA_STATUS_CHNUM_DEFAULT 0x00000018UL /**< Mode DEFAULT for LDMA_STATUS */ 122 #define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ 123 124 /* Bit fields for LDMA SYNC */ 125 #define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */ 126 #define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */ 127 #define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ 128 #define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ 129 #define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */ 130 #define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */ 131 132 /* Bit fields for LDMA CHEN */ 133 #define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ 134 #define _LDMA_CHEN_MASK 0x00FFFFFFUL /**< Mask for LDMA_CHEN */ 135 #define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ 136 #define _LDMA_CHEN_CHEN_MASK 0xFFFFFFUL /**< Bit mask for LDMA_CHEN */ 137 #define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ 138 #define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ 139 140 /* Bit fields for LDMA CHBUSY */ 141 #define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ 142 #define _LDMA_CHBUSY_MASK 0x00FFFFFFUL /**< Mask for LDMA_CHBUSY */ 143 #define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ 144 #define _LDMA_CHBUSY_BUSY_MASK 0xFFFFFFUL /**< Bit mask for LDMA_BUSY */ 145 #define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ 146 #define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ 147 148 /* Bit fields for LDMA CHDONE */ 149 #define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ 150 #define _LDMA_CHDONE_MASK 0x00FFFFFFUL /**< Mask for LDMA_CHDONE */ 151 #define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ 152 #define _LDMA_CHDONE_CHDONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_CHDONE */ 153 #define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ 154 #define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ 155 156 /* Bit fields for LDMA DBGHALT */ 157 #define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ 158 #define _LDMA_DBGHALT_MASK 0x00FFFFFFUL /**< Mask for LDMA_DBGHALT */ 159 #define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ 160 #define _LDMA_DBGHALT_DBGHALT_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DBGHALT */ 161 #define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ 162 #define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ 163 164 /* Bit fields for LDMA SWREQ */ 165 #define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ 166 #define _LDMA_SWREQ_MASK 0x00FFFFFFUL /**< Mask for LDMA_SWREQ */ 167 #define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ 168 #define _LDMA_SWREQ_SWREQ_MASK 0xFFFFFFUL /**< Bit mask for LDMA_SWREQ */ 169 #define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ 170 #define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ 171 172 /* Bit fields for LDMA REQDIS */ 173 #define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ 174 #define _LDMA_REQDIS_MASK 0x00FFFFFFUL /**< Mask for LDMA_REQDIS */ 175 #define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ 176 #define _LDMA_REQDIS_REQDIS_MASK 0xFFFFFFUL /**< Bit mask for LDMA_REQDIS */ 177 #define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ 178 #define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ 179 180 /* Bit fields for LDMA REQPEND */ 181 #define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ 182 #define _LDMA_REQPEND_MASK 0x00FFFFFFUL /**< Mask for LDMA_REQPEND */ 183 #define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ 184 #define _LDMA_REQPEND_REQPEND_MASK 0xFFFFFFUL /**< Bit mask for LDMA_REQPEND */ 185 #define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ 186 #define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ 187 188 /* Bit fields for LDMA LINKLOAD */ 189 #define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ 190 #define _LDMA_LINKLOAD_MASK 0x00FFFFFFUL /**< Mask for LDMA_LINKLOAD */ 191 #define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ 192 #define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFFFFFUL /**< Bit mask for LDMA_LINKLOAD */ 193 #define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ 194 #define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ 195 196 /* Bit fields for LDMA REQCLEAR */ 197 #define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ 198 #define _LDMA_REQCLEAR_MASK 0x00FFFFFFUL /**< Mask for LDMA_REQCLEAR */ 199 #define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ 200 #define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFFFFFUL /**< Bit mask for LDMA_REQCLEAR */ 201 #define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ 202 #define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ 203 204 /* Bit fields for LDMA IF */ 205 #define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ 206 #define _LDMA_IF_MASK 0x80FFFFFFUL /**< Mask for LDMA_IF */ 207 #define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ 208 #define _LDMA_IF_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */ 209 #define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ 210 #define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ 211 #define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */ 212 #define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ 213 #define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ 214 #define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ 215 #define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ 216 217 /* Bit fields for LDMA IFS */ 218 #define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */ 219 #define _LDMA_IFS_MASK 0x80FFFFFFUL /**< Mask for LDMA_IFS */ 220 #define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ 221 #define _LDMA_IFS_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */ 222 #define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ 223 #define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */ 224 #define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */ 225 #define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ 226 #define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ 227 #define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */ 228 #define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */ 229 230 /* Bit fields for LDMA IFC */ 231 #define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */ 232 #define _LDMA_IFC_MASK 0x80FFFFFFUL /**< Mask for LDMA_IFC */ 233 #define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ 234 #define _LDMA_IFC_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */ 235 #define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ 236 #define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */ 237 #define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */ 238 #define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ 239 #define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ 240 #define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */ 241 #define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */ 242 243 /* Bit fields for LDMA IEN */ 244 #define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ 245 #define _LDMA_IEN_MASK 0x80FFFFFFUL /**< Mask for LDMA_IEN */ 246 #define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */ 247 #define _LDMA_IEN_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */ 248 #define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ 249 #define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ 250 #define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */ 251 #define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ 252 #define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ 253 #define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ 254 #define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ 255 256 /* Bit fields for LDMA CH_REQSEL */ 257 #define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */ 258 #define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */ 259 #define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */ 260 #define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */ 261 #define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */ 262 #define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */ 263 #define _LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for LDMA_CH_REQSEL */ 264 #define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for LDMA_CH_REQSEL */ 265 #define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */ 266 #define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */ 267 #define _LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for LDMA_CH_REQSEL */ 268 #define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV 0x00000000UL /**< Mode USART3RXDATAV for LDMA_CH_REQSEL */ 269 #define _LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV 0x00000000UL /**< Mode USART4RXDATAV for LDMA_CH_REQSEL */ 270 #define _LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV 0x00000000UL /**< Mode USART5RXDATAV for LDMA_CH_REQSEL */ 271 #define _LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV 0x00000000UL /**< Mode UART0RXDATAV for LDMA_CH_REQSEL */ 272 #define _LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV 0x00000000UL /**< Mode UART1RXDATAV for LDMA_CH_REQSEL */ 273 #define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */ 274 #define _LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for LDMA_CH_REQSEL */ 275 #define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */ 276 #define _LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for LDMA_CH_REQSEL */ 277 #define _LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV 0x00000000UL /**< Mode I2C2RXDATAV for LDMA_CH_REQSEL */ 278 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */ 279 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */ 280 #define _LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for LDMA_CH_REQSEL */ 281 #define _LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for LDMA_CH_REQSEL */ 282 #define _LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000000UL /**< Mode TIMER4UFOF for LDMA_CH_REQSEL */ 283 #define _LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF 0x00000000UL /**< Mode TIMER5UFOF for LDMA_CH_REQSEL */ 284 #define _LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF 0x00000000UL /**< Mode TIMER6UFOF for LDMA_CH_REQSEL */ 285 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF 0x00000000UL /**< Mode WTIMER0UFOF for LDMA_CH_REQSEL */ 286 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF 0x00000000UL /**< Mode WTIMER1UFOF for LDMA_CH_REQSEL */ 287 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF 0x00000000UL /**< Mode WTIMER2UFOF for LDMA_CH_REQSEL */ 288 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF 0x00000000UL /**< Mode WTIMER3UFOF for LDMA_CH_REQSEL */ 289 #define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */ 290 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR 0x00000000UL /**< Mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */ 291 #define _LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY 0x00000000UL /**< Mode EBIPXL0EMPTY for LDMA_CH_REQSEL */ 292 #define _LDMA_CH_REQSEL_SIGSEL_CSENDATA 0x00000000UL /**< Mode CSENDATA for LDMA_CH_REQSEL */ 293 #define _LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for LDMA_CH_REQSEL */ 294 #define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */ 295 #define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */ 296 #define _LDMA_CH_REQSEL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for LDMA_CH_REQSEL */ 297 #define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for LDMA_CH_REQSEL */ 298 #define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */ 299 #define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */ 300 #define _LDMA_CH_REQSEL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for LDMA_CH_REQSEL */ 301 #define _LDMA_CH_REQSEL_SIGSEL_USART3TXBL 0x00000001UL /**< Mode USART3TXBL for LDMA_CH_REQSEL */ 302 #define _LDMA_CH_REQSEL_SIGSEL_USART4TXBL 0x00000001UL /**< Mode USART4TXBL for LDMA_CH_REQSEL */ 303 #define _LDMA_CH_REQSEL_SIGSEL_USART5TXBL 0x00000001UL /**< Mode USART5TXBL for LDMA_CH_REQSEL */ 304 #define _LDMA_CH_REQSEL_SIGSEL_UART0TXBL 0x00000001UL /**< Mode UART0TXBL for LDMA_CH_REQSEL */ 305 #define _LDMA_CH_REQSEL_SIGSEL_UART1TXBL 0x00000001UL /**< Mode UART1TXBL for LDMA_CH_REQSEL */ 306 #define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */ 307 #define _LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for LDMA_CH_REQSEL */ 308 #define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */ 309 #define _LDMA_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for LDMA_CH_REQSEL */ 310 #define _LDMA_CH_REQSEL_SIGSEL_I2C2TXBL 0x00000001UL /**< Mode I2C2TXBL for LDMA_CH_REQSEL */ 311 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */ 312 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */ 313 #define _LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for LDMA_CH_REQSEL */ 314 #define _LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for LDMA_CH_REQSEL */ 315 #define _LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000001UL /**< Mode TIMER4CC0 for LDMA_CH_REQSEL */ 316 #define _LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 0x00000001UL /**< Mode TIMER5CC0 for LDMA_CH_REQSEL */ 317 #define _LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 0x00000001UL /**< Mode TIMER6CC0 for LDMA_CH_REQSEL */ 318 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 0x00000001UL /**< Mode WTIMER0CC0 for LDMA_CH_REQSEL */ 319 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 0x00000001UL /**< Mode WTIMER1CC0 for LDMA_CH_REQSEL */ 320 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 0x00000001UL /**< Mode WTIMER2CC0 for LDMA_CH_REQSEL */ 321 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 0x00000001UL /**< Mode WTIMER3CC0 for LDMA_CH_REQSEL */ 322 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR 0x00000001UL /**< Mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */ 323 #define _LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY 0x00000001UL /**< Mode EBIPXL1EMPTY for LDMA_CH_REQSEL */ 324 #define _LDMA_CH_REQSEL_SIGSEL_CSENBSLN 0x00000001UL /**< Mode CSENBSLN for LDMA_CH_REQSEL */ 325 #define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */ 326 #define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */ 327 #define _LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for LDMA_CH_REQSEL */ 328 #define _LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY 0x00000002UL /**< Mode USART3TXEMPTY for LDMA_CH_REQSEL */ 329 #define _LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY 0x00000002UL /**< Mode USART4TXEMPTY for LDMA_CH_REQSEL */ 330 #define _LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY 0x00000002UL /**< Mode USART5TXEMPTY for LDMA_CH_REQSEL */ 331 #define _LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY 0x00000002UL /**< Mode UART0TXEMPTY for LDMA_CH_REQSEL */ 332 #define _LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY 0x00000002UL /**< Mode UART1TXEMPTY for LDMA_CH_REQSEL */ 333 #define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ 334 #define _LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for LDMA_CH_REQSEL */ 335 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */ 336 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */ 337 #define _LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for LDMA_CH_REQSEL */ 338 #define _LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for LDMA_CH_REQSEL */ 339 #define _LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000002UL /**< Mode TIMER4CC1 for LDMA_CH_REQSEL */ 340 #define _LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 0x00000002UL /**< Mode TIMER5CC1 for LDMA_CH_REQSEL */ 341 #define _LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 0x00000002UL /**< Mode TIMER6CC1 for LDMA_CH_REQSEL */ 342 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 0x00000002UL /**< Mode WTIMER0CC1 for LDMA_CH_REQSEL */ 343 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 0x00000002UL /**< Mode WTIMER1CC1 for LDMA_CH_REQSEL */ 344 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 0x00000002UL /**< Mode WTIMER2CC1 for LDMA_CH_REQSEL */ 345 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 0x00000002UL /**< Mode WTIMER3CC1 for LDMA_CH_REQSEL */ 346 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD 0x00000002UL /**< Mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */ 347 #define _LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL 0x00000002UL /**< Mode EBIPXLFULL for LDMA_CH_REQSEL */ 348 #define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ 349 #define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT 0x00000003UL /**< Mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */ 350 #define _LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT 0x00000003UL /**< Mode USART4RXDATAVRIGHT for LDMA_CH_REQSEL */ 351 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */ 352 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */ 353 #define _LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for LDMA_CH_REQSEL */ 354 #define _LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for LDMA_CH_REQSEL */ 355 #define _LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000003UL /**< Mode TIMER4CC2 for LDMA_CH_REQSEL */ 356 #define _LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 0x00000003UL /**< Mode TIMER5CC2 for LDMA_CH_REQSEL */ 357 #define _LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 0x00000003UL /**< Mode TIMER6CC2 for LDMA_CH_REQSEL */ 358 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 0x00000003UL /**< Mode WTIMER0CC2 for LDMA_CH_REQSEL */ 359 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 0x00000003UL /**< Mode WTIMER1CC2 for LDMA_CH_REQSEL */ 360 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 0x00000003UL /**< Mode WTIMER2CC2 for LDMA_CH_REQSEL */ 361 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 0x00000003UL /**< Mode WTIMER3CC2 for LDMA_CH_REQSEL */ 362 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR 0x00000003UL /**< Mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */ 363 #define _LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY 0x00000003UL /**< Mode EBIDDEMPTY for LDMA_CH_REQSEL */ 364 #define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ 365 #define _LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT 0x00000004UL /**< Mode USART3TXBLRIGHT for LDMA_CH_REQSEL */ 366 #define _LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT 0x00000004UL /**< Mode USART4TXBLRIGHT for LDMA_CH_REQSEL */ 367 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */ 368 #define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 0x00000004UL /**< Mode WTIMER1CC3 for LDMA_CH_REQSEL */ 369 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD 0x00000004UL /**< Mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */ 370 #define _LDMA_CH_REQSEL_SIGSEL_EBIVSYNC 0x00000004UL /**< Mode EBIVSYNC for LDMA_CH_REQSEL */ 371 #define _LDMA_CH_REQSEL_SIGSEL_EBIHSYNC 0x00000005UL /**< Mode EBIHSYNC for LDMA_CH_REQSEL */ 372 #define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */ 373 #define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */ 374 #define LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for LDMA_CH_REQSEL */ 375 #define LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for LDMA_CH_REQSEL */ 376 #define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */ 377 #define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */ 378 #define LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for LDMA_CH_REQSEL */ 379 #define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for LDMA_CH_REQSEL */ 380 #define LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for LDMA_CH_REQSEL */ 381 #define LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for LDMA_CH_REQSEL */ 382 #define LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for LDMA_CH_REQSEL */ 383 #define LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for LDMA_CH_REQSEL */ 384 #define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */ 385 #define LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for LDMA_CH_REQSEL */ 386 #define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */ 387 #define LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for LDMA_CH_REQSEL */ 388 #define LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV << 0) /**< Shifted mode I2C2RXDATAV for LDMA_CH_REQSEL */ 389 #define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */ 390 #define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */ 391 #define LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for LDMA_CH_REQSEL */ 392 #define LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for LDMA_CH_REQSEL */ 393 #define LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /**< Shifted mode TIMER4UFOF for LDMA_CH_REQSEL */ 394 #define LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF << 0) /**< Shifted mode TIMER5UFOF for LDMA_CH_REQSEL */ 395 #define LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF << 0) /**< Shifted mode TIMER6UFOF for LDMA_CH_REQSEL */ 396 #define LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF << 0) /**< Shifted mode WTIMER0UFOF for LDMA_CH_REQSEL */ 397 #define LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF << 0) /**< Shifted mode WTIMER1UFOF for LDMA_CH_REQSEL */ 398 #define LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF << 0) /**< Shifted mode WTIMER2UFOF for LDMA_CH_REQSEL */ 399 #define LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF << 0) /**< Shifted mode WTIMER3UFOF for LDMA_CH_REQSEL */ 400 #define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */ 401 #define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR << 0) /**< Shifted mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */ 402 #define LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY (_LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY << 0) /**< Shifted mode EBIPXL0EMPTY for LDMA_CH_REQSEL */ 403 #define LDMA_CH_REQSEL_SIGSEL_CSENDATA (_LDMA_CH_REQSEL_SIGSEL_CSENDATA << 0) /**< Shifted mode CSENDATA for LDMA_CH_REQSEL */ 404 #define LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV (_LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for LDMA_CH_REQSEL */ 405 #define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */ 406 #define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */ 407 #define LDMA_CH_REQSEL_SIGSEL_ADC1SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for LDMA_CH_REQSEL */ 408 #define LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for LDMA_CH_REQSEL */ 409 #define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */ 410 #define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */ 411 #define LDMA_CH_REQSEL_SIGSEL_USART2TXBL (_LDMA_CH_REQSEL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for LDMA_CH_REQSEL */ 412 #define LDMA_CH_REQSEL_SIGSEL_USART3TXBL (_LDMA_CH_REQSEL_SIGSEL_USART3TXBL << 0) /**< Shifted mode USART3TXBL for LDMA_CH_REQSEL */ 413 #define LDMA_CH_REQSEL_SIGSEL_USART4TXBL (_LDMA_CH_REQSEL_SIGSEL_USART4TXBL << 0) /**< Shifted mode USART4TXBL for LDMA_CH_REQSEL */ 414 #define LDMA_CH_REQSEL_SIGSEL_USART5TXBL (_LDMA_CH_REQSEL_SIGSEL_USART5TXBL << 0) /**< Shifted mode USART5TXBL for LDMA_CH_REQSEL */ 415 #define LDMA_CH_REQSEL_SIGSEL_UART0TXBL (_LDMA_CH_REQSEL_SIGSEL_UART0TXBL << 0) /**< Shifted mode UART0TXBL for LDMA_CH_REQSEL */ 416 #define LDMA_CH_REQSEL_SIGSEL_UART1TXBL (_LDMA_CH_REQSEL_SIGSEL_UART1TXBL << 0) /**< Shifted mode UART1TXBL for LDMA_CH_REQSEL */ 417 #define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */ 418 #define LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for LDMA_CH_REQSEL */ 419 #define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */ 420 #define LDMA_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for LDMA_CH_REQSEL */ 421 #define LDMA_CH_REQSEL_SIGSEL_I2C2TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C2TXBL << 0) /**< Shifted mode I2C2TXBL for LDMA_CH_REQSEL */ 422 #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */ 423 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */ 424 #define LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for LDMA_CH_REQSEL */ 425 #define LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for LDMA_CH_REQSEL */ 426 #define LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for LDMA_CH_REQSEL */ 427 #define LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for LDMA_CH_REQSEL */ 428 #define LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for LDMA_CH_REQSEL */ 429 #define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for LDMA_CH_REQSEL */ 430 #define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for LDMA_CH_REQSEL */ 431 #define LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for LDMA_CH_REQSEL */ 432 #define LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for LDMA_CH_REQSEL */ 433 #define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR << 0) /**< Shifted mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */ 434 #define LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY (_LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY << 0) /**< Shifted mode EBIPXL1EMPTY for LDMA_CH_REQSEL */ 435 #define LDMA_CH_REQSEL_SIGSEL_CSENBSLN (_LDMA_CH_REQSEL_SIGSEL_CSENBSLN << 0) /**< Shifted mode CSENBSLN for LDMA_CH_REQSEL */ 436 #define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */ 437 #define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */ 438 #define LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for LDMA_CH_REQSEL */ 439 #define LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY << 0) /**< Shifted mode USART3TXEMPTY for LDMA_CH_REQSEL */ 440 #define LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY << 0) /**< Shifted mode USART4TXEMPTY for LDMA_CH_REQSEL */ 441 #define LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY << 0) /**< Shifted mode USART5TXEMPTY for LDMA_CH_REQSEL */ 442 #define LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY << 0) /**< Shifted mode UART0TXEMPTY for LDMA_CH_REQSEL */ 443 #define LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY << 0) /**< Shifted mode UART1TXEMPTY for LDMA_CH_REQSEL */ 444 #define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */ 445 #define LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for LDMA_CH_REQSEL */ 446 #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */ 447 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */ 448 #define LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for LDMA_CH_REQSEL */ 449 #define LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for LDMA_CH_REQSEL */ 450 #define LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for LDMA_CH_REQSEL */ 451 #define LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for LDMA_CH_REQSEL */ 452 #define LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for LDMA_CH_REQSEL */ 453 #define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for LDMA_CH_REQSEL */ 454 #define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for LDMA_CH_REQSEL */ 455 #define LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for LDMA_CH_REQSEL */ 456 #define LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for LDMA_CH_REQSEL */ 457 #define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD << 0) /**< Shifted mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */ 458 #define LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL (_LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL << 0) /**< Shifted mode EBIPXLFULL for LDMA_CH_REQSEL */ 459 #define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */ 460 #define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT << 0) /**< Shifted mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */ 461 #define LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT << 0) /**< Shifted mode USART4RXDATAVRIGHT for LDMA_CH_REQSEL */ 462 #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */ 463 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */ 464 #define LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for LDMA_CH_REQSEL */ 465 #define LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for LDMA_CH_REQSEL */ 466 #define LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for LDMA_CH_REQSEL */ 467 #define LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for LDMA_CH_REQSEL */ 468 #define LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for LDMA_CH_REQSEL */ 469 #define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for LDMA_CH_REQSEL */ 470 #define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for LDMA_CH_REQSEL */ 471 #define LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for LDMA_CH_REQSEL */ 472 #define LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for LDMA_CH_REQSEL */ 473 #define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR << 0) /**< Shifted mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */ 474 #define LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY (_LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY << 0) /**< Shifted mode EBIDDEMPTY for LDMA_CH_REQSEL */ 475 #define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */ 476 #define LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT << 0) /**< Shifted mode USART3TXBLRIGHT for LDMA_CH_REQSEL */ 477 #define LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT << 0) /**< Shifted mode USART4TXBLRIGHT for LDMA_CH_REQSEL */ 478 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */ 479 #define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for LDMA_CH_REQSEL */ 480 #define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD << 0) /**< Shifted mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */ 481 #define LDMA_CH_REQSEL_SIGSEL_EBIVSYNC (_LDMA_CH_REQSEL_SIGSEL_EBIVSYNC << 0) /**< Shifted mode EBIVSYNC for LDMA_CH_REQSEL */ 482 #define LDMA_CH_REQSEL_SIGSEL_EBIHSYNC (_LDMA_CH_REQSEL_SIGSEL_EBIHSYNC << 0) /**< Shifted mode EBIHSYNC for LDMA_CH_REQSEL */ 483 #define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */ 484 #define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */ 485 #define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */ 486 #define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */ 487 #define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */ 488 #define _LDMA_CH_REQSEL_SOURCESEL_ADC1 0x00000009UL /**< Mode ADC1 for LDMA_CH_REQSEL */ 489 #define _LDMA_CH_REQSEL_SOURCESEL_VDAC0 0x0000000AUL /**< Mode VDAC0 for LDMA_CH_REQSEL */ 490 #define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */ 491 #define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */ 492 #define _LDMA_CH_REQSEL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for LDMA_CH_REQSEL */ 493 #define _LDMA_CH_REQSEL_SOURCESEL_USART3 0x0000000FUL /**< Mode USART3 for LDMA_CH_REQSEL */ 494 #define _LDMA_CH_REQSEL_SOURCESEL_USART4 0x00000010UL /**< Mode USART4 for LDMA_CH_REQSEL */ 495 #define _LDMA_CH_REQSEL_SOURCESEL_USART5 0x00000011UL /**< Mode USART5 for LDMA_CH_REQSEL */ 496 #define _LDMA_CH_REQSEL_SOURCESEL_UART0 0x00000012UL /**< Mode UART0 for LDMA_CH_REQSEL */ 497 #define _LDMA_CH_REQSEL_SOURCESEL_UART1 0x00000013UL /**< Mode UART1 for LDMA_CH_REQSEL */ 498 #define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000014UL /**< Mode LEUART0 for LDMA_CH_REQSEL */ 499 #define _LDMA_CH_REQSEL_SOURCESEL_LEUART1 0x00000015UL /**< Mode LEUART1 for LDMA_CH_REQSEL */ 500 #define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000016UL /**< Mode I2C0 for LDMA_CH_REQSEL */ 501 #define _LDMA_CH_REQSEL_SOURCESEL_I2C1 0x00000017UL /**< Mode I2C1 for LDMA_CH_REQSEL */ 502 #define _LDMA_CH_REQSEL_SOURCESEL_I2C2 0x00000018UL /**< Mode I2C2 for LDMA_CH_REQSEL */ 503 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000019UL /**< Mode TIMER0 for LDMA_CH_REQSEL */ 504 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x0000001AUL /**< Mode TIMER1 for LDMA_CH_REQSEL */ 505 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER2 0x0000001BUL /**< Mode TIMER2 for LDMA_CH_REQSEL */ 506 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER3 0x0000001CUL /**< Mode TIMER3 for LDMA_CH_REQSEL */ 507 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER4 0x0000001DUL /**< Mode TIMER4 for LDMA_CH_REQSEL */ 508 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER5 0x0000001EUL /**< Mode TIMER5 for LDMA_CH_REQSEL */ 509 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER6 0x0000001FUL /**< Mode TIMER6 for LDMA_CH_REQSEL */ 510 #define _LDMA_CH_REQSEL_SOURCESEL_WTIMER0 0x00000020UL /**< Mode WTIMER0 for LDMA_CH_REQSEL */ 511 #define _LDMA_CH_REQSEL_SOURCESEL_WTIMER1 0x00000021UL /**< Mode WTIMER1 for LDMA_CH_REQSEL */ 512 #define _LDMA_CH_REQSEL_SOURCESEL_WTIMER2 0x00000022UL /**< Mode WTIMER2 for LDMA_CH_REQSEL */ 513 #define _LDMA_CH_REQSEL_SOURCESEL_WTIMER3 0x00000023UL /**< Mode WTIMER3 for LDMA_CH_REQSEL */ 514 #define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */ 515 #define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 0x00000031UL /**< Mode CRYPTO0 for LDMA_CH_REQSEL */ 516 #define _LDMA_CH_REQSEL_SOURCESEL_EBI 0x00000032UL /**< Mode EBI for LDMA_CH_REQSEL */ 517 #define _LDMA_CH_REQSEL_SOURCESEL_CSEN 0x0000003DUL /**< Mode CSEN for LDMA_CH_REQSEL */ 518 #define _LDMA_CH_REQSEL_SOURCESEL_LESENSE 0x0000003EUL /**< Mode LESENSE for LDMA_CH_REQSEL */ 519 #define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */ 520 #define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */ 521 #define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */ 522 #define LDMA_CH_REQSEL_SOURCESEL_ADC1 (_LDMA_CH_REQSEL_SOURCESEL_ADC1 << 16) /**< Shifted mode ADC1 for LDMA_CH_REQSEL */ 523 #define LDMA_CH_REQSEL_SOURCESEL_VDAC0 (_LDMA_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted mode VDAC0 for LDMA_CH_REQSEL */ 524 #define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */ 525 #define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */ 526 #define LDMA_CH_REQSEL_SOURCESEL_USART2 (_LDMA_CH_REQSEL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for LDMA_CH_REQSEL */ 527 #define LDMA_CH_REQSEL_SOURCESEL_USART3 (_LDMA_CH_REQSEL_SOURCESEL_USART3 << 16) /**< Shifted mode USART3 for LDMA_CH_REQSEL */ 528 #define LDMA_CH_REQSEL_SOURCESEL_USART4 (_LDMA_CH_REQSEL_SOURCESEL_USART4 << 16) /**< Shifted mode USART4 for LDMA_CH_REQSEL */ 529 #define LDMA_CH_REQSEL_SOURCESEL_USART5 (_LDMA_CH_REQSEL_SOURCESEL_USART5 << 16) /**< Shifted mode USART5 for LDMA_CH_REQSEL */ 530 #define LDMA_CH_REQSEL_SOURCESEL_UART0 (_LDMA_CH_REQSEL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for LDMA_CH_REQSEL */ 531 #define LDMA_CH_REQSEL_SOURCESEL_UART1 (_LDMA_CH_REQSEL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for LDMA_CH_REQSEL */ 532 #define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */ 533 #define LDMA_CH_REQSEL_SOURCESEL_LEUART1 (_LDMA_CH_REQSEL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for LDMA_CH_REQSEL */ 534 #define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */ 535 #define LDMA_CH_REQSEL_SOURCESEL_I2C1 (_LDMA_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for LDMA_CH_REQSEL */ 536 #define LDMA_CH_REQSEL_SOURCESEL_I2C2 (_LDMA_CH_REQSEL_SOURCESEL_I2C2 << 16) /**< Shifted mode I2C2 for LDMA_CH_REQSEL */ 537 #define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */ 538 #define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */ 539 #define LDMA_CH_REQSEL_SOURCESEL_TIMER2 (_LDMA_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for LDMA_CH_REQSEL */ 540 #define LDMA_CH_REQSEL_SOURCESEL_TIMER3 (_LDMA_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for LDMA_CH_REQSEL */ 541 #define LDMA_CH_REQSEL_SOURCESEL_TIMER4 (_LDMA_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted mode TIMER4 for LDMA_CH_REQSEL */ 542 #define LDMA_CH_REQSEL_SOURCESEL_TIMER5 (_LDMA_CH_REQSEL_SOURCESEL_TIMER5 << 16) /**< Shifted mode TIMER5 for LDMA_CH_REQSEL */ 543 #define LDMA_CH_REQSEL_SOURCESEL_TIMER6 (_LDMA_CH_REQSEL_SOURCESEL_TIMER6 << 16) /**< Shifted mode TIMER6 for LDMA_CH_REQSEL */ 544 #define LDMA_CH_REQSEL_SOURCESEL_WTIMER0 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER0 << 16) /**< Shifted mode WTIMER0 for LDMA_CH_REQSEL */ 545 #define LDMA_CH_REQSEL_SOURCESEL_WTIMER1 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER1 << 16) /**< Shifted mode WTIMER1 for LDMA_CH_REQSEL */ 546 #define LDMA_CH_REQSEL_SOURCESEL_WTIMER2 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER2 << 16) /**< Shifted mode WTIMER2 for LDMA_CH_REQSEL */ 547 #define LDMA_CH_REQSEL_SOURCESEL_WTIMER3 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER3 << 16) /**< Shifted mode WTIMER3 for LDMA_CH_REQSEL */ 548 #define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */ 549 #define LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 << 16) /**< Shifted mode CRYPTO0 for LDMA_CH_REQSEL */ 550 #define LDMA_CH_REQSEL_SOURCESEL_EBI (_LDMA_CH_REQSEL_SOURCESEL_EBI << 16) /**< Shifted mode EBI for LDMA_CH_REQSEL */ 551 #define LDMA_CH_REQSEL_SOURCESEL_CSEN (_LDMA_CH_REQSEL_SOURCESEL_CSEN << 16) /**< Shifted mode CSEN for LDMA_CH_REQSEL */ 552 #define LDMA_CH_REQSEL_SOURCESEL_LESENSE (_LDMA_CH_REQSEL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for LDMA_CH_REQSEL */ 553 554 /* Bit fields for LDMA CH_CFG */ 555 #define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ 556 #define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ 557 #define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ 558 #define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ 559 #define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ 560 #define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ 561 #define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ 562 #define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ 563 #define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ 564 #define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ 565 #define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ 566 #define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ 567 #define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ 568 #define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ 569 #define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ 570 #define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ 571 #define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ 572 #define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ 573 #define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ 574 #define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ 575 #define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ 576 #define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ 577 #define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ 578 #define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ 579 #define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ 580 #define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ 581 #define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ 582 #define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ 583 #define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ 584 #define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ 585 #define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ 586 #define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ 587 588 /* Bit fields for LDMA CH_LOOP */ 589 #define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ 590 #define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ 591 #define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ 592 #define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ 593 #define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ 594 #define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ 595 596 /* Bit fields for LDMA CH_CTRL */ 597 #define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ 598 #define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ 599 #define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ 600 #define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ 601 #define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 602 #define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ 603 #define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ 604 #define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ 605 #define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 606 #define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ 607 #define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ 608 #define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ 609 #define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ 610 #define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ 611 #define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ 612 #define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 613 #define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 614 #define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ 615 #define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ 616 #define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 617 #define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 618 #define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ 619 #define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ 620 #define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ 621 #define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 622 #define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 623 #define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ 624 #define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ 625 #define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 626 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ 627 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ 628 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ 629 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ 630 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ 631 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ 632 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ 633 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ 634 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ 635 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ 636 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ 637 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ 638 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ 639 #define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ 640 #define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 641 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ 642 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ 643 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ 644 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ 645 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ 646 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ 647 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ 648 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ 649 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ 650 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ 651 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ 652 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ 653 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ 654 #define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ 655 #define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */ 656 #define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */ 657 #define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */ 658 #define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 659 #define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 660 #define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ 661 #define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ 662 #define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ 663 #define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 664 #define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ 665 #define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ 666 #define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 667 #define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ 668 #define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ 669 #define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ 670 #define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ 671 #define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ 672 #define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 673 #define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 674 #define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ 675 #define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ 676 #define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ 677 #define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 678 #define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 679 #define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ 680 #define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ 681 #define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 682 #define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ 683 #define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ 684 #define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ 685 #define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ 686 #define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 687 #define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ 688 #define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ 689 #define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ 690 #define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ 691 #define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ 692 #define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ 693 #define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 694 #define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ 695 #define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ 696 #define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ 697 #define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 698 #define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ 699 #define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ 700 #define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ 701 #define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ 702 #define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ 703 #define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 704 #define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ 705 #define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ 706 #define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ 707 #define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ 708 #define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 709 #define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ 710 #define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ 711 #define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ 712 #define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ 713 #define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ 714 #define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ 715 #define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ 716 #define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 717 #define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ 718 #define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ 719 #define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 720 #define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ 721 #define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ 722 #define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ 723 #define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ 724 #define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ 725 #define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ 726 #define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ 727 #define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ 728 #define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ 729 #define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ 730 #define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ 731 732 /* Bit fields for LDMA CH_SRC */ 733 #define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ 734 #define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ 735 #define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ 736 #define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ 737 #define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ 738 #define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ 739 740 /* Bit fields for LDMA CH_DST */ 741 #define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ 742 #define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ 743 #define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ 744 #define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ 745 #define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ 746 #define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ 747 748 /* Bit fields for LDMA CH_LINK */ 749 #define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ 750 #define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ 751 #define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ 752 #define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ 753 #define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ 754 #define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ 755 #define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ 756 #define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ 757 #define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ 758 #define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ 759 #define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ 760 #define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ 761 #define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ 762 #define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ 763 #define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ 764 #define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ 765 #define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ 766 #define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ 767 #define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ 768 #define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ 769 770 /** @} */ 771 /** @} End of group EFM32GG11B_LDMA */ 772 /** @} End of group Parts */ 773
