1 /***************************************************************************//** 2 * @file 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File 4 * for EFM32GG11B520F2048GQ100 5 ******************************************************************************* 6 * # License 7 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 8 ******************************************************************************* 9 * 10 * SPDX-License-Identifier: Zlib 11 * 12 * The licensor of this software is Silicon Laboratories Inc. 13 * 14 * This software is provided 'as-is', without any express or implied 15 * warranty. In no event will the authors be held liable for any damages 16 * arising from the use of this software. 17 * 18 * Permission is granted to anyone to use this software for any purpose, 19 * including commercial applications, and to alter it and redistribute it 20 * freely, subject to the following restrictions: 21 * 22 * 1. The origin of this software must not be misrepresented; you must not 23 * claim that you wrote the original software. If you use this software 24 * in a product, an acknowledgment in the product documentation would be 25 * appreciated but is not required. 26 * 2. Altered source versions must be plainly marked as such, and must not be 27 * misrepresented as being the original software. 28 * 3. This notice may not be removed or altered from any source distribution. 29 * 30 ******************************************************************************/ 31 32 #if defined(__ICCARM__) 33 #pragma system_include /* Treat file as system include file. */ 34 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 35 #pragma clang system_header /* Treat file as system include file. */ 36 #endif 37 38 #ifndef EFM32GG11B520F2048GQ100_H 39 #define EFM32GG11B520F2048GQ100_H 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /***************************************************************************//** 46 * @addtogroup Parts 47 * @{ 48 ******************************************************************************/ 49 50 /***************************************************************************//** 51 * @defgroup EFM32GG11B520F2048GQ100 EFM32GG11B520F2048GQ100 52 * @{ 53 ******************************************************************************/ 54 55 /** Interrupt Number Definition */ 56 typedef enum IRQn{ 57 /****** Cortex-M4 Processor Exceptions Numbers *******************************************/ 58 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 59 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ 60 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ 61 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ 62 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ 63 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ 64 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ 65 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ 66 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ 67 68 /****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ 69 70 EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ 71 WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ 72 LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ 73 GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ 74 SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ 75 TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ 76 USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ 77 USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ 78 ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ 79 ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ 80 IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ 81 I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ 82 I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ 83 GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ 84 TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ 85 TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ 86 TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ 87 USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ 88 USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ 89 USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ 90 USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ 91 UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ 92 UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ 93 UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ 94 UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ 95 LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ 96 LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ 97 LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ 98 PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ 99 PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ 100 PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ 101 RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ 102 CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ 103 MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ 104 CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ 105 CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ 106 FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ 107 USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ 108 USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ 109 USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ 110 USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ 111 WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ 112 WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ 113 WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ 114 WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ 115 I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ 116 VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ 117 TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ 118 TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ 119 TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ 120 USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ 121 USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ 122 CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ 123 LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ 124 EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ 125 ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ 126 ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ 127 LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ 128 CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ 129 CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ 130 RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ 131 WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ 132 LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ 133 TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ 134 } IRQn_Type; 135 136 /***************************************************************************//** 137 * @defgroup EFM32GG11B520F2048GQ100_Core Core 138 * @{ 139 * @brief Processor and Core Peripheral Section 140 ******************************************************************************/ 141 #define __MPU_PRESENT 1U /**< Presence of MPU */ 142 #define __FPU_PRESENT 1U /**< Presence of FPU */ 143 #define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ 144 #define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ 145 #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ 146 147 /** @} End of group EFM32GG11B520F2048GQ100_Core */ 148 149 /***************************************************************************//** 150 * @defgroup EFM32GG11B520F2048GQ100_Part Part 151 * @{ 152 ******************************************************************************/ 153 154 /** Part family */ 155 156 #define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ 157 #define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ 158 #define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ 159 #define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ 160 #define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ 161 #define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ 162 #define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ 163 #define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ 164 #define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ 165 #define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ 166 #define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ 167 #define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ 168 169 /* If part number is not defined as compiler option, define it */ 170 #if !defined(EFM32GG11B520F2048GQ100) 171 #define EFM32GG11B520F2048GQ100 1 /**< GIANT Gecko Part */ 172 #endif 173 174 /** Configure part number */ 175 #define PART_NUMBER "EFM32GG11B520F2048GQ100" /**< Part Number */ 176 177 /** Memory Base addresses and limits */ 178 #define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ 179 #define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ 180 #define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ 181 #define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ 182 #define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ 183 #define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ 184 #define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ 185 #define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ 186 #define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ 187 #define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ 188 #define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ 189 #define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ 190 #define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ 191 #define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ 192 #define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ 193 #define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ 194 #define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ 195 #define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ 196 #define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ 197 #define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ 198 #define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ 199 #define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ 200 #define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ 201 #define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ 202 #define USB_MEM_BASE (0x40100000UL) /**< USB base address */ 203 #define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ 204 #define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ 205 #define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ 206 #define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ 207 #define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ 208 #define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ 209 #define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ 210 #define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ 211 #define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ 212 #define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ 213 #define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ 214 #define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ 215 #define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ 216 #define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ 217 #define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ 218 #define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ 219 #define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ 220 #define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ 221 #define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ 222 #define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ 223 #define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ 224 #define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ 225 #define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ 226 #define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ 227 #define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ 228 #define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ 229 #define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ 230 #define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ 231 #define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ 232 #define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ 233 #define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ 234 #define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ 235 #define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ 236 #define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ 237 #define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ 238 #define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ 239 #define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ 240 #define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ 241 #define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ 242 #define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ 243 #define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ 244 #define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ 245 #define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ 246 #define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ 247 #define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ 248 #define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ 249 #define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ 250 #define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ 251 #define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ 252 #define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ 253 #define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ 254 #define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ 255 #define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ 256 #define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ 257 #define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ 258 #define PER_MEM_BASE (0x40000000UL) /**< PER base address */ 259 #define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ 260 #define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ 261 #define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ 262 #define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ 263 #define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ 264 #define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ 265 #define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ 266 #define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ 267 #define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ 268 #define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ 269 #define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ 270 271 /** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ 272 #define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ 273 #define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ 274 #define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ 275 #define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ 276 277 /** Bit banding area */ 278 #define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ 279 #define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ 280 281 /** Flash and SRAM limits for EFM32GG11B520F2048GQ100 */ 282 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ 283 #define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ 284 #define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ 285 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ 286 #define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ 287 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ 288 #define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ 289 #define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ 290 #define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ 291 292 /** AF channels connect the different on-chip peripherals with the af-mux */ 293 #define AFCHAN_MAX 355U 294 /** AF channel maximum location number */ 295 #define AFCHANLOC_MAX 8U 296 /** Analog AF channels */ 297 #define AFACHAN_MAX 184U 298 299 /* Part number capabilities */ 300 301 #define CRYPTO_PRESENT /**< CRYPTO is available in this part */ 302 #define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ 303 #define CAN_PRESENT /**< CAN is available in this part */ 304 #define CAN_COUNT 2 /**< 2 CANs available */ 305 #define TIMER_PRESENT /**< TIMER is available in this part */ 306 #define TIMER_COUNT 7 /**< 7 TIMERs available */ 307 #define WTIMER_PRESENT /**< WTIMER is available in this part */ 308 #define WTIMER_COUNT 4 /**< 4 WTIMERs available */ 309 #define USART_PRESENT /**< USART is available in this part */ 310 #define USART_COUNT 6 /**< 6 USARTs available */ 311 #define UART_PRESENT /**< UART is available in this part */ 312 #define UART_COUNT 2 /**< 2 UARTs available */ 313 #define LEUART_PRESENT /**< LEUART is available in this part */ 314 #define LEUART_COUNT 2 /**< 2 LEUARTs available */ 315 #define LETIMER_PRESENT /**< LETIMER is available in this part */ 316 #define LETIMER_COUNT 2 /**< 2 LETIMERs available */ 317 #define PCNT_PRESENT /**< PCNT is available in this part */ 318 #define PCNT_COUNT 3 /**< 3 PCNTs available */ 319 #define I2C_PRESENT /**< I2C is available in this part */ 320 #define I2C_COUNT 3 /**< 3 I2Cs available */ 321 #define ADC_PRESENT /**< ADC is available in this part */ 322 #define ADC_COUNT 2 /**< 2 ADCs available */ 323 #define ACMP_PRESENT /**< ACMP is available in this part */ 324 #define ACMP_COUNT 4 /**< 4 ACMPs available */ 325 #define VDAC_PRESENT /**< VDAC is available in this part */ 326 #define VDAC_COUNT 1 /**< 1 VDACs available */ 327 #define IDAC_PRESENT /**< IDAC is available in this part */ 328 #define IDAC_COUNT 1 /**< 1 IDACs available */ 329 #define WDOG_PRESENT /**< WDOG is available in this part */ 330 #define WDOG_COUNT 2 /**< 2 WDOGs available */ 331 #define TRNG_PRESENT /**< TRNG is available in this part */ 332 #define TRNG_COUNT 1 /**< 1 TRNGs available */ 333 #define MSC_PRESENT /**< MSC is available in this part */ 334 #define MSC_COUNT 1 /**< 1 MSC available */ 335 #define EMU_PRESENT /**< EMU is available in this part */ 336 #define EMU_COUNT 1 /**< 1 EMU available */ 337 #define RMU_PRESENT /**< RMU is available in this part */ 338 #define RMU_COUNT 1 /**< 1 RMU available */ 339 #define CMU_PRESENT /**< CMU is available in this part */ 340 #define CMU_COUNT 1 /**< 1 CMU available */ 341 #define LESENSE_PRESENT /**< LESENSE is available in this part */ 342 #define LESENSE_COUNT 1 /**< 1 LESENSE available */ 343 #define EBI_PRESENT /**< EBI is available in this part */ 344 #define EBI_COUNT 1 /**< 1 EBI available */ 345 #define GPIO_PRESENT /**< GPIO is available in this part */ 346 #define GPIO_COUNT 1 /**< 1 GPIO available */ 347 #define PRS_PRESENT /**< PRS is available in this part */ 348 #define PRS_COUNT 1 /**< 1 PRS available */ 349 #define LDMA_PRESENT /**< LDMA is available in this part */ 350 #define LDMA_COUNT 1 /**< 1 LDMA available */ 351 #define FPUEH_PRESENT /**< FPUEH is available in this part */ 352 #define FPUEH_COUNT 1 /**< 1 FPUEH available */ 353 #define GPCRC_PRESENT /**< GPCRC is available in this part */ 354 #define GPCRC_COUNT 1 /**< 1 GPCRC available */ 355 #define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ 356 #define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ 357 #define BU_PRESENT /**< BU is available in this part */ 358 #define BU_COUNT 1 /**< 1 BU available */ 359 #define CSEN_PRESENT /**< CSEN is available in this part */ 360 #define CSEN_COUNT 1 /**< 1 CSEN available */ 361 #define LCD_PRESENT /**< LCD is available in this part */ 362 #define LCD_COUNT 1 /**< 1 LCD available */ 363 #define RTC_PRESENT /**< RTC is available in this part */ 364 #define RTC_COUNT 1 /**< 1 RTC available */ 365 #define RTCC_PRESENT /**< RTCC is available in this part */ 366 #define RTCC_COUNT 1 /**< 1 RTCC available */ 367 #define ETM_PRESENT /**< ETM is available in this part */ 368 #define ETM_COUNT 1 /**< 1 ETM available */ 369 #define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ 370 #define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ 371 #define SMU_PRESENT /**< SMU is available in this part */ 372 #define SMU_COUNT 1 /**< 1 SMU available */ 373 #define DCDC_PRESENT /**< DCDC is available in this part */ 374 #define DCDC_COUNT 1 /**< 1 DCDC available */ 375 376 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 377 #include "system_efm32gg11b.h" /* System Header File */ 378 379 /** @} End of group EFM32GG11B520F2048GQ100_Part */ 380 381 /***************************************************************************//** 382 * @defgroup EFM32GG11B520F2048GQ100_Peripheral_TypeDefs Peripheral TypeDefs 383 * @{ 384 * @brief Device Specific Peripheral Register Structures 385 ******************************************************************************/ 386 387 /***************************************************************************//** 388 * @defgroup EFM32GG11B520F2048GQ100_MSC MSC 389 * @{ 390 * @brief EFM32GG11B520F2048GQ100_MSC Register Declaration 391 ******************************************************************************/ 392 /** MSC Register Declaration */ 393 typedef struct { 394 __IOM uint32_t CTRL; /**< Memory System Control Register */ 395 __IOM uint32_t READCTRL; /**< Read Control Register */ 396 __IOM uint32_t WRITECTRL; /**< Write Control Register */ 397 __IOM uint32_t WRITECMD; /**< Write Command Register */ 398 __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ 399 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 400 __IOM uint32_t WDATA; /**< Write Data Register */ 401 __IM uint32_t STATUS; /**< Status Register */ 402 403 uint32_t RESERVED1[4U]; /**< Reserved for future use **/ 404 __IM uint32_t IF; /**< Interrupt Flag Register */ 405 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 406 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 407 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 408 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 409 __IOM uint32_t CACHECMD; /**< Flash Cache Command Register */ 410 __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ 411 __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ 412 413 uint32_t RESERVED2[1U]; /**< Reserved for future use **/ 414 __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */ 415 416 uint32_t RESERVED3[1U]; /**< Reserved for future use **/ 417 __IOM uint32_t STARTUP; /**< Startup Control */ 418 419 uint32_t RESERVED4[4U]; /**< Reserved for future use **/ 420 __IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */ 421 __IOM uint32_t CMD; /**< Command Register */ 422 423 uint32_t RESERVED5[6U]; /**< Reserved for future use **/ 424 __IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */ 425 __IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */ 426 __IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */ 427 428 uint32_t RESERVED6[25U]; /**< Reserved for future use **/ 429 __IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */ 430 __IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */ 431 __IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */ 432 __IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */ 433 } MSC_TypeDef; /** @} */ 434 435 /***************************************************************************//** 436 * @defgroup EFM32GG11B520F2048GQ100_EMU EMU 437 * @{ 438 * @brief EFM32GG11B520F2048GQ100_EMU Register Declaration 439 ******************************************************************************/ 440 /** EMU Register Declaration */ 441 typedef struct { 442 __IOM uint32_t CTRL; /**< Control Register */ 443 __IM uint32_t STATUS; /**< Status Register */ 444 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 445 __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ 446 __IOM uint32_t CMD; /**< Command Register */ 447 448 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 449 __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ 450 __IOM uint32_t TEMPLIMITS; /**< Temperature Limits for Interrupt Generation */ 451 __IM uint32_t TEMP; /**< Value of Last Temperature Measurement */ 452 __IM uint32_t IF; /**< Interrupt Flag Register */ 453 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 454 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 455 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 456 __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ 457 458 uint32_t RESERVED1[1U]; /**< Reserved for future use **/ 459 __IOM uint32_t PWRCTRL; /**< Power Control Register */ 460 __IOM uint32_t DCDCCTRL; /**< DCDC Control */ 461 462 uint32_t RESERVED2[2U]; /**< Reserved for future use **/ 463 __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ 464 __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ 465 __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ 466 __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ 467 __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ 468 469 uint32_t RESERVED3[1U]; /**< Reserved for future use **/ 470 __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ 471 472 uint32_t RESERVED4[1U]; /**< Reserved for future use **/ 473 __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ 474 __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ 475 476 uint32_t RESERVED5[1U]; /**< Reserved for future use **/ 477 __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ 478 479 uint32_t RESERVED6[5U]; /**< Reserved for future use **/ 480 __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ 481 __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ 482 __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ 483 __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ 484 __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */ 485 __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */ 486 487 uint32_t RESERVED7[3U]; /**< Reserved for future use **/ 488 __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ 489 __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ 490 __IOM uint32_t BUCTRL; /**< Backup Power Configuration Register */ 491 uint32_t RESERVED8[2U]; /**< Reserved for future use **/ 492 __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */ 493 __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */ 494 __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */ 495 496 uint32_t RESERVED9[2U]; /**< Reserved for future use **/ 497 __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */ 498 499 uint32_t RESERVED10[3U]; /**< Reserved for future use **/ 500 __IOM uint32_t DCDCLPEM01CFG; /**< Configuration Bits for Low Power Mode to Be Applied During EM01, This Field is Only Relevant If LP Mode is Used in EM01 */ 501 __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */ 502 503 uint32_t RESERVED11[1U]; /**< Reserved for future use **/ 504 __IM uint32_t R5VSYNC; /**< 5V Read Status Register */ 505 506 uint32_t RESERVED12[1U]; /**< Reserved for future use **/ 507 __IOM uint32_t EM23PERNORETAINCMD; /**< Clears Corresponding Bits in EM23PERNORETAINSTATUS Unlocking Access to Peripheral */ 508 __IM uint32_t EM23PERNORETAINSTATUS; /**< Status Indicating If Peripherals Were Powered Down in EM23, Subsequently Locking Access to It */ 509 __IOM uint32_t EM23PERNORETAINCTRL; /**< When Set Corresponding Peripherals May Get Powered Down in EM23 */ 510 } EMU_TypeDef; /** @} */ 511 512 #include "efm32gg11b_rmu.h" 513 514 /***************************************************************************//** 515 * @defgroup EFM32GG11B520F2048GQ100_CMU CMU 516 * @{ 517 * @brief EFM32GG11B520F2048GQ100_CMU Register Declaration 518 ******************************************************************************/ 519 /** CMU Register Declaration */ 520 typedef struct { 521 __IOM uint32_t CTRL; /**< CMU Control Register */ 522 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 523 __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ 524 525 uint32_t RESERVED1[1U]; /**< Reserved for future use **/ 526 __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ 527 528 uint32_t RESERVED2[1U]; /**< Reserved for future use **/ 529 __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ 530 531 uint32_t RESERVED3[1U]; /**< Reserved for future use **/ 532 __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ 533 __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ 534 __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ 535 __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ 536 __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ 537 __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ 538 __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ 539 540 uint32_t RESERVED4[1U]; /**< Reserved for future use **/ 541 __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ 542 __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ 543 uint32_t RESERVED5[2U]; /**< Reserved for future use **/ 544 __IOM uint32_t CALCTRL; /**< Calibration Control Register */ 545 __IOM uint32_t CALCNT; /**< Calibration Counter Register */ 546 uint32_t RESERVED6[2U]; /**< Reserved for future use **/ 547 __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ 548 __IOM uint32_t CMD; /**< Command Register */ 549 uint32_t RESERVED7[2U]; /**< Reserved for future use **/ 550 __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ 551 __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ 552 uint32_t RESERVED8[2U]; /**< Reserved for future use **/ 553 __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ 554 __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ 555 __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ 556 __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ 557 __IM uint32_t STATUS; /**< Status Register */ 558 __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ 559 uint32_t RESERVED9[1U]; /**< Reserved for future use **/ 560 __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ 561 __IM uint32_t IF; /**< Interrupt Flag Register */ 562 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 563 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 564 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 565 __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ 566 567 uint32_t RESERVED10[3U]; /**< Reserved for future use **/ 568 __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ 569 __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ 570 571 uint32_t RESERVED11[6U]; /**< Reserved for future use **/ 572 __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ 573 uint32_t RESERVED12[1U]; /**< Reserved for future use **/ 574 __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ 575 __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ 576 __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ 577 uint32_t RESERVED13[3U]; /**< Reserved for future use **/ 578 __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ 579 __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ 580 __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ 581 __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ 582 583 uint32_t RESERVED14[1U]; /**< Reserved for future use **/ 584 __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ 585 __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ 586 __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ 587 __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ 588 uint32_t RESERVED15[1U]; /**< Reserved for future use **/ 589 __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ 590 uint32_t RESERVED16[1U]; /**< Reserved for future use **/ 591 __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ 592 593 uint32_t RESERVED17[3U]; /**< Reserved for future use **/ 594 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 595 __IOM uint32_t FREEZE; /**< Freeze Register */ 596 uint32_t RESERVED18[2U]; /**< Reserved for future use **/ 597 __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ 598 599 uint32_t RESERVED19[2U]; /**< Reserved for future use **/ 600 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ 601 602 uint32_t RESERVED20[4U]; /**< Reserved for future use **/ 603 __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ 604 __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ 605 __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ 606 uint32_t RESERVED21[1U]; /**< Reserved for future use **/ 607 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 608 __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ 609 } CMU_TypeDef; /** @} */ 610 611 #include "efm32gg11b_crypto.h" 612 #include "efm32gg11b_lesense_st.h" 613 #include "efm32gg11b_lesense_buf.h" 614 #include "efm32gg11b_lesense_ch.h" 615 #include "efm32gg11b_lesense.h" 616 #include "efm32gg11b_ebi.h" 617 #include "efm32gg11b_gpio_p.h" 618 #include "efm32gg11b_gpio.h" 619 #include "efm32gg11b_prs_ch.h" 620 621 /***************************************************************************//** 622 * @defgroup EFM32GG11B520F2048GQ100_PRS PRS 623 * @{ 624 * @brief EFM32GG11B520F2048GQ100_PRS Register Declaration 625 ******************************************************************************/ 626 /** PRS Register Declaration */ 627 typedef struct { 628 __IOM uint32_t SWPULSE; /**< Software Pulse Register */ 629 __IOM uint32_t SWLEVEL; /**< Software Level Register */ 630 __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ 631 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 632 __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ 633 __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ 634 __IOM uint32_t ROUTELOC2; /**< I/O Routing Location Register */ 635 __IOM uint32_t ROUTELOC3; /**< I/O Routing Location Register */ 636 __IOM uint32_t ROUTELOC4; /**< I/O Routing Location Register */ 637 __IOM uint32_t ROUTELOC5; /**< I/O Routing Location Register */ 638 uint32_t RESERVED1[2U]; /**< Reserved for future use **/ 639 __IOM uint32_t CTRL; /**< Control Register */ 640 __IOM uint32_t DMAREQ0; /**< DMA Request 0 Register */ 641 __IOM uint32_t DMAREQ1; /**< DMA Request 1 Register */ 642 uint32_t RESERVED2[1U]; /**< Reserved for future use **/ 643 __IM uint32_t PEEK; /**< PRS Channel Values */ 644 645 uint32_t RESERVED3[3U]; /**< Reserved registers */ 646 PRS_CH_TypeDef CH[24U]; /**< Channel registers */ 647 } PRS_TypeDef; /** @} */ 648 649 #include "efm32gg11b_ldma_ch.h" 650 #include "efm32gg11b_ldma.h" 651 #include "efm32gg11b_fpueh.h" 652 #include "efm32gg11b_gpcrc.h" 653 #include "efm32gg11b_can_mir.h" 654 #include "efm32gg11b_can.h" 655 #include "efm32gg11b_timer_cc.h" 656 #include "efm32gg11b_timer.h" 657 #include "efm32gg11b_usart.h" 658 #include "efm32gg11b_leuart.h" 659 #include "efm32gg11b_letimer.h" 660 #include "efm32gg11b_cryotimer.h" 661 #include "efm32gg11b_pcnt.h" 662 #include "efm32gg11b_i2c.h" 663 #include "efm32gg11b_adc.h" 664 #include "efm32gg11b_acmp.h" 665 #include "efm32gg11b_vdac_opa.h" 666 #include "efm32gg11b_vdac.h" 667 #include "efm32gg11b_idac.h" 668 #include "efm32gg11b_csen.h" 669 #include "efm32gg11b_lcd.h" 670 #include "efm32gg11b_rtc_comp.h" 671 #include "efm32gg11b_rtc.h" 672 #include "efm32gg11b_rtcc_cc.h" 673 #include "efm32gg11b_rtcc_ret.h" 674 #include "efm32gg11b_rtcc.h" 675 #include "efm32gg11b_wdog_pch.h" 676 #include "efm32gg11b_wdog.h" 677 #include "efm32gg11b_etm.h" 678 679 /***************************************************************************//** 680 * @defgroup EFM32GG11B520F2048GQ100_SMU SMU 681 * @{ 682 * @brief EFM32GG11B520F2048GQ100_SMU Register Declaration 683 ******************************************************************************/ 684 /** SMU Register Declaration */ 685 typedef struct { 686 uint32_t RESERVED0[3U]; /**< Reserved for future use **/ 687 __IM uint32_t IF; /**< Interrupt Flag Register */ 688 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 689 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 690 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 691 692 uint32_t RESERVED1[9U]; /**< Reserved for future use **/ 693 __IOM uint32_t PPUCTRL; /**< PPU Control Register */ 694 uint32_t RESERVED2[3U]; /**< Reserved for future use **/ 695 __IOM uint32_t PPUPATD0; /**< PPU Privilege Access Type Descriptor 0 */ 696 __IOM uint32_t PPUPATD1; /**< PPU Privilege Access Type Descriptor 1 */ 697 __IOM uint32_t PPUPATD2; /**< PPU Privilege Access Type Descriptor 2 */ 698 699 uint32_t RESERVED3[13U]; /**< Reserved for future use **/ 700 __IM uint32_t PPUFS; /**< PPU Fault Status */ 701 } SMU_TypeDef; /** @} */ 702 703 #include "efm32gg11b_trng.h" 704 #include "efm32gg11b_dma_descriptor.h" 705 #include "efm32gg11b_devinfo.h" 706 #include "efm32gg11b_romtable.h" 707 708 /** @} End of group EFM32GG11B520F2048GQ100_Peripheral_TypeDefs */ 709 710 /***************************************************************************//** 711 * @defgroup EFM32GG11B520F2048GQ100_Peripheral_Base Peripheral Memory Map 712 * @{ 713 ******************************************************************************/ 714 715 #define MSC_BASE (0x40000000UL) /**< MSC base address */ 716 #define EMU_BASE (0x400E3000UL) /**< EMU base address */ 717 #define RMU_BASE (0x400E5000UL) /**< RMU base address */ 718 #define CMU_BASE (0x400E4000UL) /**< CMU base address */ 719 #define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ 720 #define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ 721 #define EBI_BASE (0x4000B000UL) /**< EBI base address */ 722 #define GPIO_BASE (0x40088000UL) /**< GPIO base address */ 723 #define PRS_BASE (0x400E6000UL) /**< PRS base address */ 724 #define LDMA_BASE (0x40002000UL) /**< LDMA base address */ 725 #define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ 726 #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ 727 #define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ 728 #define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ 729 #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ 730 #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ 731 #define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ 732 #define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ 733 #define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ 734 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ 735 #define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ 736 #define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ 737 #define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ 738 #define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ 739 #define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ 740 #define USART0_BASE (0x40010000UL) /**< USART0 base address */ 741 #define USART1_BASE (0x40010400UL) /**< USART1 base address */ 742 #define USART2_BASE (0x40010800UL) /**< USART2 base address */ 743 #define USART3_BASE (0x40010C00UL) /**< USART3 base address */ 744 #define USART4_BASE (0x40011000UL) /**< USART4 base address */ 745 #define USART5_BASE (0x40011400UL) /**< USART5 base address */ 746 #define UART0_BASE (0x40014000UL) /**< UART0 base address */ 747 #define UART1_BASE (0x40014400UL) /**< UART1 base address */ 748 #define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ 749 #define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ 750 #define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ 751 #define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ 752 #define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ 753 #define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ 754 #define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ 755 #define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ 756 #define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ 757 #define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ 758 #define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ 759 #define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ 760 #define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ 761 #define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ 762 #define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ 763 #define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ 764 #define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ 765 #define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ 766 #define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ 767 #define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ 768 #define LCD_BASE (0x40054000UL) /**< LCD base address */ 769 #define RTC_BASE (0x40060000UL) /**< RTC base address */ 770 #define RTCC_BASE (0x40062000UL) /**< RTCC base address */ 771 #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ 772 #define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ 773 #define ETM_BASE (0xE0041000UL) /**< ETM base address */ 774 #define SMU_BASE (0x40020000UL) /**< SMU base address */ 775 #define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ 776 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ 777 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ 778 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ 779 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ 780 781 /** @} End of group EFM32GG11B520F2048GQ100_Peripheral_Base */ 782 783 /***************************************************************************//** 784 * @defgroup EFM32GG11B520F2048GQ100_Peripheral_Declaration Peripheral Declarations 785 * @{ 786 ******************************************************************************/ 787 788 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ 789 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ 790 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ 791 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ 792 #define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ 793 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ 794 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ 795 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ 796 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ 797 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ 798 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ 799 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ 800 #define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ 801 #define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ 802 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ 803 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ 804 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ 805 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ 806 #define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ 807 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ 808 #define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ 809 #define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ 810 #define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ 811 #define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ 812 #define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ 813 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ 814 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ 815 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ 816 #define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ 817 #define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ 818 #define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ 819 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ 820 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ 821 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ 822 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ 823 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ 824 #define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ 825 #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ 826 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ 827 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ 828 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ 829 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ 830 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ 831 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ 832 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ 833 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ 834 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ 835 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ 836 #define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ 837 #define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ 838 #define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ 839 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ 840 #define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ 841 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ 842 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ 843 #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ 844 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ 845 #define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ 846 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ 847 #define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ 848 #define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ 849 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ 850 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ 851 852 /** @} End of group EFM32GG11B520F2048GQ100_Peripheral_Declaration */ 853 854 /***************************************************************************//** 855 * @defgroup EFM32GG11B520F2048GQ100_Peripheral_Offsets Peripheral Offsets 856 * @{ 857 ******************************************************************************/ 858 859 #define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ 860 #define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ 861 #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ 862 #define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ 863 #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ 864 #define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ 865 #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ 866 #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ 867 #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ 868 #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ 869 #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ 870 #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ 871 #define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ 872 #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ 873 #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ 874 #define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ 875 876 /** @} End of group EFM32GG11B520F2048GQ100_Peripheral_Offsets */ 877 878 /***************************************************************************//** 879 * @defgroup EFM32GG11B520F2048GQ100_BitFields Bit Fields 880 * @{ 881 ******************************************************************************/ 882 883 /***************************************************************************//** 884 * @addtogroup EFM32GG11B520F2048GQ100_PRS 885 * @{ 886 * @addtogroup EFM32GG11B520F2048GQ100_PRS_Signals PRS Signals 887 * @{ 888 * @brief PRS Signal names 889 ******************************************************************************/ 890 #define PRS_PRS_CH0 ((1 << 8) + 0) /**< PRS PRS channel 0 */ 891 #define PRS_PRS_CH1 ((1 << 8) + 1) /**< PRS PRS channel 1 */ 892 #define PRS_PRS_CH2 ((1 << 8) + 2) /**< PRS PRS channel 2 */ 893 #define PRS_PRS_CH3 ((1 << 8) + 3) /**< PRS PRS channel 3 */ 894 #define PRS_PRS_CH4 ((1 << 8) + 4) /**< PRS PRS channel 4 */ 895 #define PRS_PRS_CH5 ((1 << 8) + 5) /**< PRS PRS channel 5 */ 896 #define PRS_PRS_CH6 ((1 << 8) + 6) /**< PRS PRS channel 6 */ 897 #define PRS_PRS_CH7 ((1 << 8) + 7) /**< PRS PRS channel 7 */ 898 #define PRS_PRS_CH8 ((2 << 8) + 0) /**< PRS PRS channel 8 */ 899 #define PRS_PRS_CH9 ((2 << 8) + 1) /**< PRS PRS channel 9 */ 900 #define PRS_PRS_CH10 ((2 << 8) + 2) /**< PRS PRS channel 10 */ 901 #define PRS_PRS_CH11 ((2 << 8) + 3) /**< PRS PRS channel 11 */ 902 #define PRS_PRS_CH12 ((2 << 8) + 4) /**< PRS PRS channel 12 */ 903 #define PRS_PRS_CH13 ((2 << 8) + 5) /**< PRS PRS channel 13 */ 904 #define PRS_PRS_CH14 ((2 << 8) + 6) /**< PRS PRS channel 14 */ 905 #define PRS_PRS_CH15 ((2 << 8) + 7) /**< PRS PRS channel 15 */ 906 #define PRS_PRS_CH16 ((3 << 8) + 0) /**< PRS PRS channel 16 */ 907 #define PRS_PRS_CH17 ((3 << 8) + 1) /**< PRS PRS channel 17 */ 908 #define PRS_PRS_CH18 ((3 << 8) + 2) /**< PRS PRS channel 18 */ 909 #define PRS_PRS_CH19 ((3 << 8) + 3) /**< PRS PRS channel 19 */ 910 #define PRS_PRS_CH20 ((3 << 8) + 4) /**< PRS PRS channel 20 */ 911 #define PRS_PRS_CH21 ((3 << 8) + 5) /**< PRS PRS channel 21 */ 912 #define PRS_PRS_CH22 ((3 << 8) + 6) /**< PRS PRS channel 22 */ 913 #define PRS_PRS_CH23 ((3 << 8) + 7) /**< PRS PRS channel 23 */ 914 #define PRS_ACMP0_OUT ((4 << 8) + 0) /**< PRS Analog comparator output */ 915 #define PRS_ACMP1_OUT ((5 << 8) + 0) /**< PRS Analog comparator output */ 916 #define PRS_ADC0_SINGLE ((6 << 8) + 0) /**< PRS ADC single conversion done */ 917 #define PRS_ADC0_SCAN ((6 << 8) + 1) /**< PRS ADC scan conversion done */ 918 #define PRS_RTC_OF ((7 << 8) + 0) /**< PRS RTC Overflow */ 919 #define PRS_RTC_COMP0 ((7 << 8) + 1) /**< PRS RTC Compare 0 */ 920 #define PRS_RTC_COMP1 ((7 << 8) + 2) /**< PRS RTC Compare 1 */ 921 #define PRS_RTC_COMP2 ((7 << 8) + 3) /**< PRS RTC Compare 2 */ 922 #define PRS_RTC_COMP3 ((7 << 8) + 4) /**< PRS RTC Compare 3 */ 923 #define PRS_RTC_COMP4 ((7 << 8) + 5) /**< PRS RTC Compare 4 */ 924 #define PRS_RTC_COMP5 ((7 << 8) + 6) /**< PRS RTC Compare 5 */ 925 #define PRS_RTCC_CCV0 ((8 << 8) + 1) /**< PRS RTCC Compare 0 */ 926 #define PRS_RTCC_CCV1 ((8 << 8) + 2) /**< PRS RTCC Compare 1 */ 927 #define PRS_RTCC_CCV2 ((8 << 8) + 3) /**< PRS RTCC Compare 2 */ 928 #define PRS_GPIO_PIN0 ((9 << 8) + 0) /**< PRS GPIO pin 0 */ 929 #define PRS_GPIO_PIN1 ((9 << 8) + 1) /**< PRS GPIO pin 1 */ 930 #define PRS_GPIO_PIN2 ((9 << 8) + 2) /**< PRS GPIO pin 2 */ 931 #define PRS_GPIO_PIN3 ((9 << 8) + 3) /**< PRS GPIO pin 3 */ 932 #define PRS_GPIO_PIN4 ((9 << 8) + 4) /**< PRS GPIO pin 4 */ 933 #define PRS_GPIO_PIN5 ((9 << 8) + 5) /**< PRS GPIO pin 5 */ 934 #define PRS_GPIO_PIN6 ((9 << 8) + 6) /**< PRS GPIO pin 6 */ 935 #define PRS_GPIO_PIN7 ((9 << 8) + 7) /**< PRS GPIO pin 7 */ 936 #define PRS_GPIO_PIN8 ((10 << 8) + 0) /**< PRS GPIO pin 8 */ 937 #define PRS_GPIO_PIN9 ((10 << 8) + 1) /**< PRS GPIO pin 9 */ 938 #define PRS_GPIO_PIN10 ((10 << 8) + 2) /**< PRS GPIO pin 10 */ 939 #define PRS_GPIO_PIN11 ((10 << 8) + 3) /**< PRS GPIO pin 11 */ 940 #define PRS_GPIO_PIN12 ((10 << 8) + 4) /**< PRS GPIO pin 12 */ 941 #define PRS_GPIO_PIN13 ((10 << 8) + 5) /**< PRS GPIO pin 13 */ 942 #define PRS_GPIO_PIN14 ((10 << 8) + 6) /**< PRS GPIO pin 14 */ 943 #define PRS_GPIO_PIN15 ((10 << 8) + 7) /**< PRS GPIO pin 15 */ 944 #define PRS_LETIMER0_CH0 ((11 << 8) + 0) /**< PRS LETIMER CH0 Out */ 945 #define PRS_LETIMER0_CH1 ((11 << 8) + 1) /**< PRS LETIMER CH1 Out */ 946 #define PRS_LETIMER1_CH0 ((12 << 8) + 0) /**< PRS LETIMER CH0 Out */ 947 #define PRS_LETIMER1_CH1 ((12 << 8) + 1) /**< PRS LETIMER CH1 Out */ 948 #define PRS_PCNT0_TCC ((13 << 8) + 0) /**< PRS Triggered compare match */ 949 #define PRS_PCNT0_UFOF ((13 << 8) + 1) /**< PRS Counter overflow or underflow */ 950 #define PRS_PCNT0_DIR ((13 << 8) + 2) /**< PRS Counter direction */ 951 #define PRS_PCNT1_TCC ((14 << 8) + 0) /**< PRS Triggered compare match */ 952 #define PRS_PCNT1_UFOF ((14 << 8) + 1) /**< PRS Counter overflow or underflow */ 953 #define PRS_PCNT1_DIR ((14 << 8) + 2) /**< PRS Counter direction */ 954 #define PRS_PCNT2_TCC ((15 << 8) + 0) /**< PRS Triggered compare match */ 955 #define PRS_PCNT2_UFOF ((15 << 8) + 1) /**< PRS Counter overflow or underflow */ 956 #define PRS_PCNT2_DIR ((15 << 8) + 2) /**< PRS Counter direction */ 957 #define PRS_CRYOTIMER_PERIOD ((16 << 8) + 0) /**< PRS CRYOTIMER Output */ 958 #define PRS_CMU_CLKOUT0 ((17 << 8) + 0) /**< PRS Clock Output 0 */ 959 #define PRS_CMU_CLKOUT1 ((17 << 8) + 1) /**< PRS Clock Output 1 */ 960 #define PRS_CMU_CLKOUT2 ((17 << 8) + 7) /**< PRS Clock Output 2 */ 961 #define PRS_VDAC0_CH0 ((23 << 8) + 0) /**< PRS DAC ch0 conversion done */ 962 #define PRS_VDAC0_CH1 ((23 << 8) + 1) /**< PRS DAC ch1 conversion done */ 963 #define PRS_VDAC0_OPA0 ((23 << 8) + 2) /**< PRS OPA0 warmed up. output is valid. */ 964 #define PRS_VDAC0_OPA1 ((23 << 8) + 3) /**< PRS OPA1 warmed up. output is valid. */ 965 #define PRS_VDAC0_OPA2 ((23 << 8) + 4) /**< PRS OPA2 warmed up. output is valid. */ 966 #define PRS_VDAC0_OPA3 ((23 << 8) + 5) /**< PRS OPA3 warmed up. output is valid. */ 967 #define PRS_LESENSE_SCANRES0 ((24 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ 968 #define PRS_LESENSE_SCANRES1 ((24 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ 969 #define PRS_LESENSE_SCANRES2 ((24 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ 970 #define PRS_LESENSE_SCANRES3 ((24 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ 971 #define PRS_LESENSE_SCANRES4 ((24 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ 972 #define PRS_LESENSE_SCANRES5 ((24 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ 973 #define PRS_LESENSE_SCANRES6 ((24 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ 974 #define PRS_LESENSE_SCANRES7 ((24 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ 975 #define PRS_LESENSE_SCANRES8 ((25 << 8) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ 976 #define PRS_LESENSE_SCANRES9 ((25 << 8) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ 977 #define PRS_LESENSE_SCANRES10 ((25 << 8) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ 978 #define PRS_LESENSE_SCANRES11 ((25 << 8) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ 979 #define PRS_LESENSE_SCANRES12 ((25 << 8) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ 980 #define PRS_LESENSE_SCANRES13 ((25 << 8) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ 981 #define PRS_LESENSE_SCANRES14 ((25 << 8) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ 982 #define PRS_LESENSE_SCANRES15 ((25 << 8) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ 983 #define PRS_LESENSE_DEC0 ((26 << 8) + 0) /**< PRS LESENSE Decoder PRS out 0 */ 984 #define PRS_LESENSE_DEC1 ((26 << 8) + 1) /**< PRS LESENSE Decoder PRS out 1 */ 985 #define PRS_LESENSE_DEC2 ((26 << 8) + 2) /**< PRS LESENSE Decoder PRS out 2 */ 986 #define PRS_LESENSE_DECCMP ((26 << 8) + 3) /**< PRS LESENSE Decoder PRS compare value match channel */ 987 #define PRS_LESENSE_MEASACT ((27 << 8) + 0) /**< PRS LESENSE Measurement active */ 988 #define PRS_ACMP2_OUT ((28 << 8) + 0) /**< PRS Analog comparator output */ 989 #define PRS_ACMP3_OUT ((29 << 8) + 0) /**< PRS Analog comparator output */ 990 #define PRS_ADC1_SINGLE ((30 << 8) + 0) /**< PRS ADC single conversion done */ 991 #define PRS_ADC1_SCAN ((30 << 8) + 1) /**< PRS ADC scan conversion done */ 992 #define PRS_USART0_IRTX ((48 << 8) + 0) /**< PRS */ 993 #define PRS_USART0_TXC ((48 << 8) + 1) /**< PRS */ 994 #define PRS_USART0_RXDATAV ((48 << 8) + 2) /**< PRS */ 995 #define PRS_USART0_RTS ((48 << 8) + 3) /**< PRS */ 996 #define PRS_USART0_TX ((48 << 8) + 5) /**< PRS */ 997 #define PRS_USART0_CS ((48 << 8) + 6) /**< PRS */ 998 #define PRS_USART1_TXC ((49 << 8) + 1) /**< PRS */ 999 #define PRS_USART1_RXDATAV ((49 << 8) + 2) /**< PRS */ 1000 #define PRS_USART1_RTS ((49 << 8) + 3) /**< PRS */ 1001 #define PRS_USART1_TX ((49 << 8) + 5) /**< PRS */ 1002 #define PRS_USART1_CS ((49 << 8) + 6) /**< PRS */ 1003 #define PRS_USART2_IRTX ((50 << 8) + 0) /**< PRS USART 2 IRDA out */ 1004 #define PRS_USART2_TXC ((50 << 8) + 1) /**< PRS */ 1005 #define PRS_USART2_RXDATAV ((50 << 8) + 2) /**< PRS */ 1006 #define PRS_USART2_RTS ((50 << 8) + 3) /**< PRS */ 1007 #define PRS_USART2_TX ((50 << 8) + 5) /**< PRS */ 1008 #define PRS_USART2_CS ((50 << 8) + 6) /**< PRS */ 1009 #define PRS_USART3_TXC ((51 << 8) + 1) /**< PRS */ 1010 #define PRS_USART3_RXDATAV ((51 << 8) + 2) /**< PRS */ 1011 #define PRS_USART3_RTS ((51 << 8) + 3) /**< PRS */ 1012 #define PRS_USART3_TX ((51 << 8) + 5) /**< PRS */ 1013 #define PRS_USART3_CS ((51 << 8) + 6) /**< PRS */ 1014 #define PRS_USART4_TXC ((52 << 8) + 1) /**< PRS */ 1015 #define PRS_USART4_RXDATAV ((52 << 8) + 2) /**< PRS */ 1016 #define PRS_USART4_RTS ((52 << 8) + 3) /**< PRS */ 1017 #define PRS_USART4_TX ((52 << 8) + 5) /**< PRS */ 1018 #define PRS_USART4_CS ((52 << 8) + 6) /**< PRS */ 1019 #define PRS_USART5_TXC ((53 << 8) + 1) /**< PRS */ 1020 #define PRS_USART5_RXDATAV ((53 << 8) + 2) /**< PRS */ 1021 #define PRS_USART5_RTS ((53 << 8) + 3) /**< PRS */ 1022 #define PRS_USART5_TX ((53 << 8) + 5) /**< PRS */ 1023 #define PRS_USART5_CS ((53 << 8) + 6) /**< PRS */ 1024 #define PRS_UART0_TXC ((54 << 8) + 1) /**< PRS */ 1025 #define PRS_UART0_RXDATAV ((54 << 8) + 2) /**< PRS */ 1026 #define PRS_UART0_RTS ((54 << 8) + 3) /**< PRS */ 1027 #define PRS_UART0_TX ((54 << 8) + 5) /**< PRS */ 1028 #define PRS_UART0_CS ((54 << 8) + 6) /**< PRS */ 1029 #define PRS_UART1_TXC ((55 << 8) + 1) /**< PRS */ 1030 #define PRS_UART1_RXDATAV ((55 << 8) + 2) /**< PRS */ 1031 #define PRS_UART1_RTS ((55 << 8) + 3) /**< PRS */ 1032 #define PRS_UART1_TX ((55 << 8) + 5) /**< PRS */ 1033 #define PRS_UART1_CS ((55 << 8) + 6) /**< PRS */ 1034 #define PRS_TIMER0_UF ((60 << 8) + 0) /**< PRS */ 1035 #define PRS_TIMER0_OF ((60 << 8) + 1) /**< PRS */ 1036 #define PRS_TIMER0_CC0 ((60 << 8) + 2) /**< PRS */ 1037 #define PRS_TIMER0_CC1 ((60 << 8) + 3) /**< PRS */ 1038 #define PRS_TIMER0_CC2 ((60 << 8) + 4) /**< PRS */ 1039 #define PRS_TIMER1_UF ((61 << 8) + 0) /**< PRS */ 1040 #define PRS_TIMER1_OF ((61 << 8) + 1) /**< PRS */ 1041 #define PRS_TIMER1_CC0 ((61 << 8) + 2) /**< PRS */ 1042 #define PRS_TIMER1_CC1 ((61 << 8) + 3) /**< PRS */ 1043 #define PRS_TIMER1_CC2 ((61 << 8) + 4) /**< PRS */ 1044 #define PRS_TIMER1_CC3 ((61 << 8) + 5) /**< PRS */ 1045 #define PRS_TIMER2_UF ((62 << 8) + 0) /**< PRS */ 1046 #define PRS_TIMER2_OF ((62 << 8) + 1) /**< PRS */ 1047 #define PRS_TIMER2_CC0 ((62 << 8) + 2) /**< PRS */ 1048 #define PRS_TIMER2_CC1 ((62 << 8) + 3) /**< PRS */ 1049 #define PRS_TIMER2_CC2 ((62 << 8) + 4) /**< PRS */ 1050 #define PRS_CM4_TXEV ((67 << 8) + 0) /**< PRS */ 1051 #define PRS_CM4_ICACHEPCHITSOF ((67 << 8) + 1) /**< PRS */ 1052 #define PRS_CM4_ICACHEPCMISSESOF ((67 << 8) + 2) /**< PRS */ 1053 #define PRS_TIMER3_UF ((80 << 8) + 0) /**< PRS */ 1054 #define PRS_TIMER3_OF ((80 << 8) + 1) /**< PRS */ 1055 #define PRS_TIMER3_CC0 ((80 << 8) + 2) /**< PRS */ 1056 #define PRS_TIMER3_CC1 ((80 << 8) + 3) /**< PRS */ 1057 #define PRS_TIMER3_CC2 ((80 << 8) + 4) /**< PRS */ 1058 #define PRS_WTIMER0_UF ((82 << 8) + 0) /**< PRS */ 1059 #define PRS_WTIMER0_OF ((82 << 8) + 1) /**< PRS */ 1060 #define PRS_WTIMER0_CC0 ((82 << 8) + 2) /**< PRS */ 1061 #define PRS_WTIMER0_CC1 ((82 << 8) + 3) /**< PRS */ 1062 #define PRS_WTIMER0_CC2 ((82 << 8) + 4) /**< PRS */ 1063 #define PRS_WTIMER1_UF ((83 << 8) + 0) /**< PRS */ 1064 #define PRS_WTIMER1_OF ((83 << 8) + 1) /**< PRS */ 1065 #define PRS_WTIMER1_CC0 ((83 << 8) + 2) /**< PRS */ 1066 #define PRS_WTIMER1_CC1 ((83 << 8) + 3) /**< PRS */ 1067 #define PRS_WTIMER1_CC2 ((83 << 8) + 4) /**< PRS */ 1068 #define PRS_WTIMER1_CC3 ((83 << 8) + 5) /**< PRS */ 1069 #define PRS_WTIMER2_UF ((84 << 8) + 0) /**< PRS */ 1070 #define PRS_WTIMER2_OF ((84 << 8) + 1) /**< PRS */ 1071 #define PRS_WTIMER2_CC0 ((84 << 8) + 2) /**< PRS */ 1072 #define PRS_WTIMER2_CC1 ((84 << 8) + 3) /**< PRS */ 1073 #define PRS_WTIMER2_CC2 ((84 << 8) + 4) /**< PRS */ 1074 #define PRS_WTIMER3_UF ((85 << 8) + 0) /**< PRS */ 1075 #define PRS_WTIMER3_OF ((85 << 8) + 1) /**< PRS */ 1076 #define PRS_WTIMER3_CC0 ((85 << 8) + 2) /**< PRS */ 1077 #define PRS_WTIMER3_CC1 ((85 << 8) + 3) /**< PRS */ 1078 #define PRS_WTIMER3_CC2 ((85 << 8) + 4) /**< PRS */ 1079 #define PRS_TIMER4_UF ((98 << 8) + 0) /**< PRS */ 1080 #define PRS_TIMER4_OF ((98 << 8) + 1) /**< PRS */ 1081 #define PRS_TIMER4_CC0 ((98 << 8) + 2) /**< PRS */ 1082 #define PRS_TIMER4_CC1 ((98 << 8) + 3) /**< PRS */ 1083 #define PRS_TIMER4_CC2 ((98 << 8) + 4) /**< PRS */ 1084 #define PRS_TIMER5_UF ((99 << 8) + 0) /**< PRS */ 1085 #define PRS_TIMER5_OF ((99 << 8) + 1) /**< PRS */ 1086 #define PRS_TIMER5_CC0 ((99 << 8) + 2) /**< PRS */ 1087 #define PRS_TIMER5_CC1 ((99 << 8) + 3) /**< PRS */ 1088 #define PRS_TIMER5_CC2 ((99 << 8) + 4) /**< PRS */ 1089 #define PRS_TIMER6_UF ((100 << 8) + 0) /**< PRS */ 1090 #define PRS_TIMER6_OF ((100 << 8) + 1) /**< PRS */ 1091 #define PRS_TIMER6_CC0 ((100 << 8) + 2) /**< PRS */ 1092 #define PRS_TIMER6_CC1 ((100 << 8) + 3) /**< PRS */ 1093 #define PRS_TIMER6_CC2 ((100 << 8) + 4) /**< PRS */ 1094 1095 /** @} */ 1096 /** @} End of group EFM32GG11B520F2048GQ100_PRS */ 1097 1098 #include "efm32gg11b_dmareq.h" 1099 1100 /***************************************************************************//** 1101 * @addtogroup EFM32GG11B520F2048GQ100_WTIMER 1102 * @{ 1103 * @defgroup EFM32GG11B520F2048GQ100_WTIMER_BitFields WTIMER Bit Fields 1104 * @{ 1105 ******************************************************************************/ 1106 1107 /* Bit fields for WTIMER CTRL */ 1108 #define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ 1109 #define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ 1110 #define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ 1111 #define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ 1112 #define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 1113 #define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ 1114 #define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ 1115 #define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ 1116 #define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ 1117 #define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 1118 #define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ 1119 #define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ 1120 #define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ 1121 #define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ 1122 #define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ 1123 #define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ 1124 #define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ 1125 #define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 1126 #define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 1127 #define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ 1128 #define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ 1129 #define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ 1130 #define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 1131 #define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 1132 #define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ 1133 #define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ 1134 #define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ 1135 #define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 1136 #define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ 1137 #define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ 1138 #define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 1139 #define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ 1140 #define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ 1141 #define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ 1142 #define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ 1143 #define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ 1144 #define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 1145 #define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 1146 #define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ 1147 #define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ 1148 #define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ 1149 #define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 1150 #define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 1151 #define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ 1152 #define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ 1153 #define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 1154 #define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ 1155 #define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ 1156 #define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ 1157 #define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ 1158 #define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 1159 #define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ 1160 #define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ 1161 #define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ 1162 #define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ 1163 #define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ 1164 #define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ 1165 #define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 1166 #define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ 1167 #define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ 1168 #define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ 1169 #define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ 1170 #define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 1171 #define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ 1172 #define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ 1173 #define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ 1174 #define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ 1175 #define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ 1176 #define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ 1177 #define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ 1178 #define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 1179 #define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 1180 #define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ 1181 #define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ 1182 #define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ 1183 #define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 1184 #define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 1185 #define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ 1186 #define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ 1187 #define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 1188 #define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ 1189 #define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ 1190 #define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ 1191 #define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 1192 #define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ 1193 #define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ 1194 #define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ 1195 #define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ 1196 #define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ 1197 #define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 1198 #define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ 1199 #define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ 1200 #define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ 1201 #define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ 1202 #define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ 1203 #define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ 1204 #define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ 1205 #define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ 1206 #define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ 1207 #define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ 1208 #define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ 1209 #define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 1210 #define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ 1211 #define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ 1212 #define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ 1213 #define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ 1214 #define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ 1215 #define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ 1216 #define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ 1217 #define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ 1218 #define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ 1219 #define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ 1220 #define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ 1221 #define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ 1222 #define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ 1223 #define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ 1224 #define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 1225 #define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 1226 #define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ 1227 #define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ 1228 #define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ 1229 #define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 1230 #define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 1231 1232 /* Bit fields for WTIMER CMD */ 1233 #define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ 1234 #define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ 1235 #define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ 1236 #define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ 1237 #define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ 1238 #define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ 1239 #define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ 1240 #define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ 1241 #define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ 1242 #define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ 1243 #define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ 1244 #define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ 1245 1246 /* Bit fields for WTIMER STATUS */ 1247 #define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ 1248 #define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ 1249 #define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ 1250 #define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ 1251 #define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ 1252 #define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 1253 #define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 1254 #define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ 1255 #define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ 1256 #define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ 1257 #define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 1258 #define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ 1259 #define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ 1260 #define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 1261 #define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ 1262 #define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ 1263 #define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ 1264 #define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ 1265 #define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ 1266 #define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 1267 #define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 1268 #define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ 1269 #define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ 1270 #define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ 1271 #define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 1272 #define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 1273 #define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ 1274 #define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ 1275 #define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ 1276 #define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 1277 #define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 1278 #define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ 1279 #define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ 1280 #define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ 1281 #define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 1282 #define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 1283 #define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ 1284 #define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ 1285 #define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ 1286 #define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 1287 #define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 1288 #define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ 1289 #define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ 1290 #define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ 1291 #define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 1292 #define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 1293 #define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ 1294 #define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ 1295 #define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ 1296 #define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 1297 #define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 1298 #define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ 1299 #define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ 1300 #define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ 1301 #define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 1302 #define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 1303 #define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ 1304 #define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ 1305 #define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ 1306 #define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 1307 #define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 1308 #define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ 1309 #define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ 1310 #define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ 1311 #define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 1312 #define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ 1313 #define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ 1314 #define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 1315 #define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ 1316 #define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ 1317 #define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ 1318 #define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ 1319 #define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ 1320 #define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 1321 #define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ 1322 #define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ 1323 #define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 1324 #define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ 1325 #define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ 1326 #define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ 1327 #define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ 1328 #define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ 1329 #define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 1330 #define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ 1331 #define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ 1332 #define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 1333 #define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ 1334 #define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ 1335 #define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ 1336 #define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ 1337 #define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ 1338 #define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 1339 #define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ 1340 #define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ 1341 #define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 1342 #define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ 1343 #define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ 1344 1345 /* Bit fields for WTIMER IF */ 1346 #define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ 1347 #define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ 1348 #define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ 1349 #define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ 1350 #define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ 1351 #define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 1352 #define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ 1353 #define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ 1354 #define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ 1355 #define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ 1356 #define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 1357 #define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ 1358 #define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ 1359 #define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ 1360 #define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ 1361 #define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 1362 #define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ 1363 #define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ 1364 #define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ 1365 #define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ 1366 #define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 1367 #define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ 1368 #define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ 1369 #define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ 1370 #define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ 1371 #define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 1372 #define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ 1373 #define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ 1374 #define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ 1375 #define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ 1376 #define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 1377 #define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ 1378 #define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ 1379 #define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ 1380 #define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ 1381 #define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 1382 #define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ 1383 #define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ 1384 #define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ 1385 #define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ 1386 #define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 1387 #define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ 1388 #define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ 1389 #define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ 1390 #define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ 1391 #define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 1392 #define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ 1393 #define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ 1394 #define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ 1395 #define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ 1396 #define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 1397 #define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ 1398 #define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ 1399 #define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ 1400 #define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ 1401 #define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 1402 #define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ 1403 1404 /* Bit fields for WTIMER IFS */ 1405 #define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ 1406 #define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ 1407 #define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ 1408 #define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ 1409 #define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ 1410 #define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 1411 #define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ 1412 #define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ 1413 #define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ 1414 #define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ 1415 #define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 1416 #define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ 1417 #define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ 1418 #define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ 1419 #define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ 1420 #define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 1421 #define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ 1422 #define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ 1423 #define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ 1424 #define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ 1425 #define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 1426 #define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ 1427 #define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ 1428 #define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ 1429 #define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ 1430 #define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 1431 #define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ 1432 #define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ 1433 #define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ 1434 #define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ 1435 #define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 1436 #define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ 1437 #define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ 1438 #define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ 1439 #define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ 1440 #define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 1441 #define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ 1442 #define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ 1443 #define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ 1444 #define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ 1445 #define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 1446 #define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ 1447 #define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ 1448 #define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ 1449 #define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ 1450 #define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 1451 #define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ 1452 #define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ 1453 #define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ 1454 #define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ 1455 #define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 1456 #define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ 1457 #define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ 1458 #define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ 1459 #define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ 1460 #define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 1461 #define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ 1462 1463 /* Bit fields for WTIMER IFC */ 1464 #define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ 1465 #define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ 1466 #define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ 1467 #define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ 1468 #define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ 1469 #define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1470 #define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1471 #define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ 1472 #define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ 1473 #define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ 1474 #define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1475 #define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1476 #define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ 1477 #define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ 1478 #define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ 1479 #define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1480 #define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1481 #define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ 1482 #define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ 1483 #define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ 1484 #define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1485 #define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1486 #define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ 1487 #define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ 1488 #define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ 1489 #define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1490 #define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1491 #define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ 1492 #define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ 1493 #define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ 1494 #define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1495 #define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1496 #define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ 1497 #define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ 1498 #define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ 1499 #define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1500 #define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1501 #define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ 1502 #define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ 1503 #define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ 1504 #define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1505 #define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1506 #define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ 1507 #define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ 1508 #define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ 1509 #define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1510 #define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1511 #define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ 1512 #define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ 1513 #define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ 1514 #define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1515 #define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1516 #define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ 1517 #define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ 1518 #define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ 1519 #define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1520 #define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1521 1522 /* Bit fields for WTIMER IEN */ 1523 #define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ 1524 #define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ 1525 #define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ 1526 #define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ 1527 #define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ 1528 #define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1529 #define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1530 #define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ 1531 #define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ 1532 #define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ 1533 #define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1534 #define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1535 #define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ 1536 #define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ 1537 #define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ 1538 #define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1539 #define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1540 #define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ 1541 #define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ 1542 #define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ 1543 #define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1544 #define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1545 #define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ 1546 #define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ 1547 #define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ 1548 #define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1549 #define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1550 #define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ 1551 #define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ 1552 #define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ 1553 #define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1554 #define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1555 #define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ 1556 #define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ 1557 #define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ 1558 #define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1559 #define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1560 #define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ 1561 #define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ 1562 #define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ 1563 #define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1564 #define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1565 #define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ 1566 #define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ 1567 #define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ 1568 #define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1569 #define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1570 #define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ 1571 #define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ 1572 #define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ 1573 #define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1574 #define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1575 #define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ 1576 #define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ 1577 #define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ 1578 #define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1579 #define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1580 1581 /* Bit fields for WTIMER TOP */ 1582 #define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ 1583 #define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ 1584 #define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ 1585 #define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ 1586 #define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ 1587 #define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ 1588 1589 /* Bit fields for WTIMER TOPB */ 1590 #define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ 1591 #define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ 1592 #define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ 1593 #define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ 1594 #define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ 1595 #define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ 1596 1597 /* Bit fields for WTIMER CNT */ 1598 #define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ 1599 #define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ 1600 #define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ 1601 #define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ 1602 #define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ 1603 #define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ 1604 1605 /* Bit fields for WTIMER LOCK */ 1606 #define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ 1607 #define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ 1608 #define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ 1609 #define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ 1610 #define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ 1611 #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ 1612 #define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ 1613 #define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ 1614 #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ 1615 #define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ 1616 #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ 1617 #define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ 1618 #define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ 1619 #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ 1620 1621 /* Bit fields for WTIMER ROUTEPEN */ 1622 #define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ 1623 #define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ 1624 #define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ 1625 #define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ 1626 #define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ 1627 #define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1628 #define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1629 #define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ 1630 #define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ 1631 #define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ 1632 #define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1633 #define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1634 #define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ 1635 #define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ 1636 #define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ 1637 #define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1638 #define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1639 #define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ 1640 #define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ 1641 #define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ 1642 #define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1643 #define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1644 #define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ 1645 #define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ 1646 #define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ 1647 #define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1648 #define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1649 #define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ 1650 #define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ 1651 #define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ 1652 #define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1653 #define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1654 #define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ 1655 #define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ 1656 #define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ 1657 #define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1658 #define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1659 1660 /* Bit fields for WTIMER ROUTELOC0 */ 1661 #define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ 1662 #define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ 1663 #define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ 1664 #define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ 1665 #define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ 1666 #define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ 1667 #define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ 1668 #define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ 1669 #define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ 1670 #define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ 1671 #define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ 1672 #define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ 1673 #define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ 1674 #define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ 1675 #define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ 1676 #define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ 1677 #define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ 1678 #define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ 1679 #define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ 1680 #define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ 1681 #define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ 1682 #define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ 1683 #define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ 1684 #define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ 1685 #define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ 1686 #define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ 1687 #define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ 1688 #define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ 1689 #define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ 1690 #define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ 1691 #define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ 1692 #define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ 1693 #define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ 1694 #define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ 1695 #define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ 1696 #define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ 1697 #define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ 1698 #define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ 1699 #define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ 1700 #define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ 1701 #define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ 1702 #define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ 1703 #define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ 1704 #define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ 1705 #define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ 1706 #define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ 1707 #define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ 1708 #define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ 1709 #define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ 1710 #define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ 1711 #define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ 1712 #define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ 1713 #define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ 1714 #define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ 1715 #define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ 1716 #define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ 1717 #define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ 1718 #define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ 1719 #define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ 1720 #define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ 1721 #define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ 1722 #define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ 1723 #define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ 1724 #define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ 1725 #define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ 1726 #define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ 1727 #define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ 1728 #define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ 1729 #define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ 1730 #define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ 1731 #define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ 1732 #define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ 1733 #define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ 1734 #define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ 1735 #define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ 1736 #define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ 1737 #define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ 1738 #define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ 1739 #define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ 1740 #define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ 1741 #define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ 1742 #define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ 1743 1744 /* Bit fields for WTIMER ROUTELOC2 */ 1745 #define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ 1746 #define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ 1747 #define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ 1748 #define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ 1749 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ 1750 #define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ 1751 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ 1752 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ 1753 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ 1754 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ 1755 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ 1756 #define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ 1757 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ 1758 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ 1759 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ 1760 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ 1761 #define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ 1762 #define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ 1763 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ 1764 #define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ 1765 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ 1766 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ 1767 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ 1768 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ 1769 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ 1770 #define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ 1771 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ 1772 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ 1773 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ 1774 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ 1775 #define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ 1776 #define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ 1777 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ 1778 #define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ 1779 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ 1780 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ 1781 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ 1782 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ 1783 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ 1784 #define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ 1785 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ 1786 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ 1787 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ 1788 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ 1789 1790 /* Bit fields for WTIMER CC_CTRL */ 1791 #define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ 1792 #define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ 1793 #define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ 1794 #define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ 1795 #define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1796 #define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ 1797 #define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ 1798 #define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ 1799 #define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ 1800 #define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1801 #define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ 1802 #define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ 1803 #define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ 1804 #define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ 1805 #define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ 1806 #define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ 1807 #define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ 1808 #define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1809 #define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1810 #define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ 1811 #define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ 1812 #define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ 1813 #define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1814 #define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1815 #define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ 1816 #define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ 1817 #define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1818 #define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ 1819 #define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ 1820 #define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ 1821 #define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ 1822 #define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1823 #define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ 1824 #define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ 1825 #define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ 1826 #define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ 1827 #define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ 1828 #define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ 1829 #define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1830 #define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ 1831 #define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ 1832 #define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ 1833 #define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ 1834 #define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1835 #define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ 1836 #define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ 1837 #define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ 1838 #define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ 1839 #define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ 1840 #define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ 1841 #define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1842 #define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ 1843 #define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ 1844 #define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ 1845 #define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ 1846 #define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1847 #define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ 1848 #define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ 1849 #define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ 1850 #define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ 1851 #define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ 1852 #define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ 1853 #define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1854 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ 1855 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ 1856 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ 1857 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ 1858 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ 1859 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ 1860 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ 1861 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ 1862 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ 1863 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ 1864 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ 1865 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ 1866 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ 1867 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ 1868 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ 1869 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ 1870 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ 1871 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ 1872 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ 1873 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ 1874 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ 1875 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ 1876 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ 1877 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ 1878 #define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1879 #define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ 1880 #define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ 1881 #define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ 1882 #define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ 1883 #define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ 1884 #define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ 1885 #define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ 1886 #define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ 1887 #define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ 1888 #define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ 1889 #define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ 1890 #define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ 1891 #define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ 1892 #define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ 1893 #define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ 1894 #define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ 1895 #define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ 1896 #define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ 1897 #define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ 1898 #define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ 1899 #define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ 1900 #define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ 1901 #define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ 1902 #define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ 1903 #define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ 1904 #define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ 1905 #define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1906 #define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ 1907 #define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ 1908 #define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ 1909 #define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ 1910 #define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1911 #define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ 1912 #define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ 1913 #define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ 1914 #define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ 1915 #define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ 1916 #define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ 1917 #define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1918 #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ 1919 #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ 1920 #define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ 1921 #define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ 1922 #define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1923 #define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ 1924 #define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ 1925 #define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ 1926 #define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ 1927 #define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ 1928 #define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ 1929 #define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ 1930 #define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1931 #define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ 1932 #define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ 1933 #define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1934 #define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ 1935 #define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ 1936 #define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ 1937 #define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ 1938 #define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ 1939 #define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1940 #define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ 1941 #define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ 1942 #define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1943 #define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ 1944 #define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ 1945 #define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ 1946 #define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ 1947 #define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ 1948 #define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1949 #define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ 1950 #define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ 1951 #define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1952 #define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ 1953 #define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ 1954 1955 /* Bit fields for WTIMER CC_CCV */ 1956 #define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ 1957 #define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ 1958 #define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ 1959 #define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ 1960 #define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ 1961 #define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ 1962 1963 /* Bit fields for WTIMER CC_CCVP */ 1964 #define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ 1965 #define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ 1966 #define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ 1967 #define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ 1968 #define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ 1969 #define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ 1970 1971 /* Bit fields for WTIMER CC_CCVB */ 1972 #define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ 1973 #define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ 1974 #define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ 1975 #define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ 1976 #define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ 1977 #define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ 1978 1979 /* Bit fields for WTIMER DTCTRL */ 1980 #define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ 1981 #define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ 1982 #define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ 1983 #define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ 1984 #define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ 1985 #define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1986 #define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1987 #define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ 1988 #define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ 1989 #define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ 1990 #define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1991 #define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ 1992 #define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ 1993 #define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1994 #define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ 1995 #define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ 1996 #define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ 1997 #define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ 1998 #define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ 1999 #define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 2000 #define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 2001 #define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ 2002 #define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ 2003 #define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ 2004 #define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 2005 #define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 2006 #define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ 2007 #define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ 2008 #define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 2009 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ 2010 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ 2011 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ 2012 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ 2013 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ 2014 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ 2015 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ 2016 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ 2017 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ 2018 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ 2019 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ 2020 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ 2021 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ 2022 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ 2023 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ 2024 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ 2025 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ 2026 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ 2027 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ 2028 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ 2029 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ 2030 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ 2031 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ 2032 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ 2033 #define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 2034 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ 2035 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ 2036 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ 2037 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ 2038 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ 2039 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ 2040 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ 2041 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ 2042 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ 2043 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ 2044 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ 2045 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ 2046 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ 2047 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ 2048 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ 2049 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ 2050 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ 2051 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ 2052 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ 2053 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ 2054 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ 2055 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ 2056 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ 2057 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ 2058 #define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ 2059 #define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ 2060 #define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ 2061 #define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 2062 #define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 2063 #define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ 2064 #define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ 2065 #define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ 2066 #define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 2067 #define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 2068 #define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ 2069 #define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ 2070 #define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ 2071 #define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 2072 #define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 2073 2074 /* Bit fields for WTIMER DTTIME */ 2075 #define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ 2076 #define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ 2077 #define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ 2078 #define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ 2079 #define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ 2080 #define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ 2081 #define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ 2082 #define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ 2083 #define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ 2084 #define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ 2085 #define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ 2086 #define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ 2087 #define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ 2088 #define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ 2089 #define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ 2090 #define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ 2091 #define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ 2092 #define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ 2093 #define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ 2094 #define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ 2095 #define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ 2096 #define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ 2097 #define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ 2098 #define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ 2099 #define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ 2100 #define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ 2101 #define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ 2102 #define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ 2103 #define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ 2104 #define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ 2105 #define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ 2106 #define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ 2107 #define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ 2108 #define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ 2109 #define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ 2110 #define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ 2111 2112 /* Bit fields for WTIMER DTFC */ 2113 #define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ 2114 #define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ 2115 #define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ 2116 #define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ 2117 #define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 2118 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ 2119 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ 2120 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ 2121 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ 2122 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ 2123 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ 2124 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ 2125 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ 2126 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ 2127 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ 2128 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ 2129 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ 2130 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ 2131 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ 2132 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ 2133 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ 2134 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ 2135 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ 2136 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ 2137 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ 2138 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ 2139 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ 2140 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ 2141 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ 2142 #define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 2143 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ 2144 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ 2145 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ 2146 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ 2147 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ 2148 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ 2149 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ 2150 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ 2151 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ 2152 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ 2153 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ 2154 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ 2155 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ 2156 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ 2157 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ 2158 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ 2159 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ 2160 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ 2161 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ 2162 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ 2163 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ 2164 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ 2165 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ 2166 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ 2167 #define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ 2168 #define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ 2169 #define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 2170 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ 2171 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ 2172 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ 2173 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ 2174 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ 2175 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ 2176 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ 2177 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ 2178 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ 2179 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ 2180 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ 2181 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ 2182 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ 2183 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ 2184 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ 2185 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ 2186 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ 2187 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ 2188 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ 2189 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ 2190 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ 2191 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ 2192 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ 2193 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ 2194 #define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 2195 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ 2196 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ 2197 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ 2198 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ 2199 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ 2200 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ 2201 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ 2202 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ 2203 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ 2204 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ 2205 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ 2206 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ 2207 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ 2208 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ 2209 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ 2210 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ 2211 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ 2212 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ 2213 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ 2214 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ 2215 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ 2216 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ 2217 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ 2218 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ 2219 #define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ 2220 #define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ 2221 #define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 2222 #define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ 2223 #define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ 2224 #define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ 2225 #define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ 2226 #define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 2227 #define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ 2228 #define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ 2229 #define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ 2230 #define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ 2231 #define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ 2232 #define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ 2233 #define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ 2234 #define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 2235 #define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 2236 #define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ 2237 #define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ 2238 #define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ 2239 #define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 2240 #define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 2241 #define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ 2242 #define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ 2243 #define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ 2244 #define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 2245 #define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 2246 #define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ 2247 #define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ 2248 #define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ 2249 #define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 2250 #define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 2251 2252 /* Bit fields for WTIMER DTOGEN */ 2253 #define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ 2254 #define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ 2255 #define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ 2256 #define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ 2257 #define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ 2258 #define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 2259 #define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 2260 #define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ 2261 #define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ 2262 #define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ 2263 #define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 2264 #define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 2265 #define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ 2266 #define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ 2267 #define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ 2268 #define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 2269 #define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 2270 #define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ 2271 #define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ 2272 #define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ 2273 #define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 2274 #define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 2275 #define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ 2276 #define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ 2277 #define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ 2278 #define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 2279 #define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 2280 #define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ 2281 #define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ 2282 #define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ 2283 #define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 2284 #define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 2285 2286 /* Bit fields for WTIMER DTFAULT */ 2287 #define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ 2288 #define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ 2289 #define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ 2290 #define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ 2291 #define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ 2292 #define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ 2293 #define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ 2294 #define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ 2295 #define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ 2296 #define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ 2297 #define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ 2298 #define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ 2299 #define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ 2300 #define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ 2301 #define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ 2302 #define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ 2303 #define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ 2304 #define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ 2305 #define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ 2306 #define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ 2307 #define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ 2308 #define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ 2309 2310 /* Bit fields for WTIMER DTFAULTC */ 2311 #define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ 2312 #define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ 2313 #define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ 2314 #define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ 2315 #define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ 2316 #define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ 2317 #define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ 2318 #define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ 2319 #define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ 2320 #define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ 2321 #define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ 2322 #define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ 2323 #define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ 2324 #define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ 2325 #define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ 2326 #define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ 2327 #define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ 2328 #define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ 2329 #define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ 2330 #define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ 2331 #define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ 2332 #define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ 2333 2334 /* Bit fields for WTIMER DTLOCK */ 2335 #define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ 2336 #define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ 2337 #define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ 2338 #define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ 2339 #define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ 2340 #define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ 2341 #define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ 2342 #define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ 2343 #define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ 2344 #define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ 2345 #define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ 2346 #define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ 2347 #define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ 2348 #define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ 2349 2350 /** @} */ 2351 /** @} End of group EFM32GG11B520F2048GQ100_WTIMER */ 2352 2353 #include "efm32gg11b_uart.h" 2354 2355 /***************************************************************************//** 2356 * @addtogroup EFM32GG11B520F2048GQ100_MSC 2357 * @{ 2358 * @defgroup EFM32GG11B520F2048GQ100_MSC_BitFields MSC Bit Fields 2359 * @{ 2360 ******************************************************************************/ 2361 2362 /* Bit fields for MSC CTRL */ 2363 #define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */ 2364 #define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */ 2365 #define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ 2366 #define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */ 2367 #define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */ 2368 #define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ 2369 #define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ 2370 #define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */ 2371 #define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */ 2372 #define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */ 2373 #define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ 2374 #define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */ 2375 #define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */ 2376 #define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */ 2377 #define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */ 2378 #define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ 2379 #define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */ 2380 #define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */ 2381 #define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */ 2382 #define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */ 2383 #define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ 2384 #define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */ 2385 #define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */ 2386 #define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */ 2387 #define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */ 2388 #define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ 2389 #define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */ 2390 #define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */ 2391 #define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */ 2392 #define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */ 2393 #define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ 2394 #define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */ 2395 #define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */ 2396 #define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */ 2397 #define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */ 2398 #define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ 2399 #define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */ 2400 #define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */ 2401 #define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */ 2402 #define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */ 2403 #define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */ 2404 #define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */ 2405 #define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */ 2406 #define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */ 2407 #define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */ 2408 #define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */ 2409 2410 /* Bit fields for MSC READCTRL */ 2411 #define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */ 2412 #define _MSC_READCTRL_MASK 0x13000378UL /**< Mask for MSC_READCTRL */ 2413 #define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ 2414 #define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ 2415 #define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ 2416 #define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 2417 #define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ 2418 #define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ 2419 #define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ 2420 #define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ 2421 #define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 2422 #define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ 2423 #define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ 2424 #define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ 2425 #define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ 2426 #define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 2427 #define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ 2428 #define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ 2429 #define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ 2430 #define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ 2431 #define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 2432 #define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ 2433 #define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */ 2434 #define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */ 2435 #define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */ 2436 #define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ 2437 #define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */ 2438 #define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */ 2439 #define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */ 2440 #define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */ 2441 #define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 2442 #define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */ 2443 #define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */ 2444 #define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */ 2445 #define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ 2446 #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ 2447 #define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ 2448 #define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ 2449 #define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ 2450 #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */ 2451 #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */ 2452 #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */ 2453 #define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */ 2454 #define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */ 2455 #define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */ 2456 #define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */ 2457 #define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */ 2458 #define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ 2459 #define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */ 2460 2461 /* Bit fields for MSC WRITECTRL */ 2462 #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ 2463 #define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */ 2464 #define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ 2465 #define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ 2466 #define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ 2467 #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ 2468 #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ 2469 #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ 2470 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ 2471 #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ 2472 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ 2473 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ 2474 #define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */ 2475 #define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */ 2476 #define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */ 2477 #define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ 2478 #define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ 2479 2480 /* Bit fields for MSC WRITECMD */ 2481 #define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ 2482 #define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */ 2483 #define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */ 2484 #define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ 2485 #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ 2486 #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 2487 #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 2488 #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ 2489 #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ 2490 #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ 2491 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 2492 #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 2493 #define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ 2494 #define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ 2495 #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ 2496 #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 2497 #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 2498 #define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ 2499 #define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ 2500 #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ 2501 #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 2502 #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 2503 #define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ 2504 #define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ 2505 #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ 2506 #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 2507 #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 2508 #define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */ 2509 #define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ 2510 #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ 2511 #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 2512 #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 2513 #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */ 2514 #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ 2515 #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ 2516 #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 2517 #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 2518 #define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */ 2519 #define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */ 2520 #define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */ 2521 #define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 2522 #define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 2523 #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */ 2524 #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ 2525 #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ 2526 #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ 2527 #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ 2528 2529 /* Bit fields for MSC ADDRB */ 2530 #define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ 2531 #define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ 2532 #define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ 2533 #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ 2534 #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ 2535 #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ 2536 2537 /* Bit fields for MSC WDATA */ 2538 #define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ 2539 #define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ 2540 #define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ 2541 #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ 2542 #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ 2543 #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ 2544 2545 /* Bit fields for MSC STATUS */ 2546 #define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ 2547 #define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */ 2548 #define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ 2549 #define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ 2550 #define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ 2551 #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 2552 #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ 2553 #define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ 2554 #define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ 2555 #define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ 2556 #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 2557 #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ 2558 #define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ 2559 #define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ 2560 #define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ 2561 #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 2562 #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ 2563 #define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ 2564 #define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ 2565 #define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ 2566 #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ 2567 #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ 2568 #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ 2569 #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ 2570 #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ 2571 #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 2572 #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ 2573 #define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ 2574 #define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ 2575 #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ 2576 #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 2577 #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ 2578 #define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ 2579 #define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ 2580 #define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ 2581 #define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 2582 #define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ 2583 #define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */ 2584 #define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */ 2585 #define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */ 2586 #define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 2587 #define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ 2588 #define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */ 2589 #define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */ 2590 #define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 2591 #define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ 2592 #define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ 2593 #define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ 2594 #define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ 2595 #define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ 2596 2597 /* Bit fields for MSC IF */ 2598 #define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ 2599 #define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */ 2600 #define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ 2601 #define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ 2602 #define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ 2603 #define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 2604 #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ 2605 #define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ 2606 #define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ 2607 #define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ 2608 #define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 2609 #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ 2610 #define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ 2611 #define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ 2612 #define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ 2613 #define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 2614 #define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ 2615 #define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ 2616 #define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ 2617 #define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ 2618 #define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 2619 #define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ 2620 #define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */ 2621 #define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ 2622 #define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ 2623 #define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 2624 #define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */ 2625 #define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */ 2626 #define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ 2627 #define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ 2628 #define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 2629 #define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */ 2630 #define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */ 2631 #define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ 2632 #define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ 2633 #define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 2634 #define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */ 2635 #define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */ 2636 #define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ 2637 #define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ 2638 #define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 2639 #define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ 2640 #define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */ 2641 #define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ 2642 #define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ 2643 #define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 2644 #define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */ 2645 #define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */ 2646 #define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ 2647 #define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ 2648 #define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 2649 #define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */ 2650 #define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */ 2651 #define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ 2652 #define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ 2653 #define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 2654 #define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */ 2655 #define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */ 2656 #define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ 2657 #define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ 2658 #define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ 2659 #define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */ 2660 2661 /* Bit fields for MSC IFS */ 2662 #define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ 2663 #define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */ 2664 #define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */ 2665 #define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ 2666 #define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ 2667 #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 2668 #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ 2669 #define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */ 2670 #define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ 2671 #define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ 2672 #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 2673 #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ 2674 #define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */ 2675 #define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ 2676 #define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ 2677 #define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 2678 #define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ 2679 #define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */ 2680 #define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ 2681 #define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ 2682 #define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 2683 #define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ 2684 #define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */ 2685 #define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ 2686 #define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ 2687 #define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 2688 #define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */ 2689 #define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */ 2690 #define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ 2691 #define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ 2692 #define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 2693 #define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */ 2694 #define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */ 2695 #define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ 2696 #define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ 2697 #define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 2698 #define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */ 2699 #define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */ 2700 #define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ 2701 #define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ 2702 #define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 2703 #define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */ 2704 #define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */ 2705 #define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ 2706 #define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ 2707 #define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 2708 #define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */ 2709 #define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */ 2710 #define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ 2711 #define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ 2712 #define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 2713 #define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */ 2714 #define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */ 2715 #define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ 2716 #define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ 2717 #define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 2718 #define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */ 2719 #define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */ 2720 #define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ 2721 #define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ 2722 #define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ 2723 #define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */ 2724 2725 /* Bit fields for MSC IFC */ 2726 #define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ 2727 #define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */ 2728 #define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */ 2729 #define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ 2730 #define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ 2731 #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 2732 #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ 2733 #define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */ 2734 #define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ 2735 #define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ 2736 #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 2737 #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ 2738 #define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */ 2739 #define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ 2740 #define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ 2741 #define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 2742 #define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ 2743 #define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */ 2744 #define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ 2745 #define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ 2746 #define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 2747 #define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ 2748 #define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */ 2749 #define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ 2750 #define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ 2751 #define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 2752 #define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */ 2753 #define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */ 2754 #define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ 2755 #define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ 2756 #define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 2757 #define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */ 2758 #define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */ 2759 #define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ 2760 #define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ 2761 #define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 2762 #define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */ 2763 #define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */ 2764 #define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ 2765 #define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ 2766 #define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 2767 #define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */ 2768 #define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */ 2769 #define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ 2770 #define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ 2771 #define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 2772 #define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */ 2773 #define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */ 2774 #define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ 2775 #define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ 2776 #define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 2777 #define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */ 2778 #define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */ 2779 #define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ 2780 #define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ 2781 #define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 2782 #define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */ 2783 #define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */ 2784 #define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ 2785 #define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ 2786 #define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ 2787 #define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */ 2788 2789 /* Bit fields for MSC IEN */ 2790 #define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ 2791 #define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */ 2792 #define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */ 2793 #define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ 2794 #define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ 2795 #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 2796 #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ 2797 #define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */ 2798 #define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ 2799 #define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ 2800 #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 2801 #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ 2802 #define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */ 2803 #define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ 2804 #define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ 2805 #define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 2806 #define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ 2807 #define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */ 2808 #define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ 2809 #define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ 2810 #define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 2811 #define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ 2812 #define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */ 2813 #define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */ 2814 #define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */ 2815 #define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 2816 #define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */ 2817 #define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */ 2818 #define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */ 2819 #define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */ 2820 #define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 2821 #define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */ 2822 #define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */ 2823 #define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */ 2824 #define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */ 2825 #define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 2826 #define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */ 2827 #define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */ 2828 #define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */ 2829 #define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */ 2830 #define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 2831 #define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ 2832 #define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */ 2833 #define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */ 2834 #define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */ 2835 #define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 2836 #define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */ 2837 #define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */ 2838 #define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */ 2839 #define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */ 2840 #define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 2841 #define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */ 2842 #define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */ 2843 #define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */ 2844 #define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */ 2845 #define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 2846 #define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */ 2847 #define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */ 2848 #define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */ 2849 #define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */ 2850 #define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ 2851 #define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */ 2852 2853 /* Bit fields for MSC LOCK */ 2854 #define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ 2855 #define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ 2856 #define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ 2857 #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ 2858 #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ 2859 #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ 2860 #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ 2861 #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ 2862 #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ 2863 #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ 2864 #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ 2865 #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ 2866 #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ 2867 #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ 2868 2869 /* Bit fields for MSC CACHECMD */ 2870 #define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */ 2871 #define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */ 2872 #define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ 2873 #define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ 2874 #define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ 2875 #define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ 2876 #define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */ 2877 #define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ 2878 #define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ 2879 #define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ 2880 #define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ 2881 #define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */ 2882 #define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ 2883 #define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ 2884 #define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ 2885 #define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */ 2886 #define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */ 2887 2888 /* Bit fields for MSC CACHEHITS */ 2889 #define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ 2890 #define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ 2891 #define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ 2892 #define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ 2893 #define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ 2894 #define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ 2895 2896 /* Bit fields for MSC CACHEMISSES */ 2897 #define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ 2898 #define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ 2899 #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ 2900 #define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ 2901 #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ 2902 #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ 2903 2904 /* Bit fields for MSC MASSLOCK */ 2905 #define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ 2906 #define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ 2907 #define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ 2908 #define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ 2909 #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ 2910 #define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ 2911 #define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ 2912 #define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ 2913 #define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ 2914 #define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ 2915 #define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ 2916 #define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ 2917 #define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ 2918 #define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ 2919 2920 /* Bit fields for MSC STARTUP */ 2921 #define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */ 2922 #define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */ 2923 #define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */ 2924 #define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */ 2925 #define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */ 2926 #define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */ 2927 #define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */ 2928 #define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */ 2929 #define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ 2930 #define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */ 2931 #define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */ 2932 #define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */ 2933 #define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */ 2934 #define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ 2935 #define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */ 2936 #define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */ 2937 #define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */ 2938 #define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */ 2939 #define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ 2940 #define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */ 2941 #define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */ 2942 #define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */ 2943 #define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */ 2944 #define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */ 2945 #define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */ 2946 #define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */ 2947 #define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */ 2948 #define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */ 2949 #define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */ 2950 2951 /* Bit fields for MSC BANKSWITCHLOCK */ 2952 #define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */ 2953 #define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */ 2954 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */ 2955 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */ 2956 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */ 2957 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */ 2958 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */ 2959 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */ 2960 #define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */ 2961 #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */ 2962 #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */ 2963 #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */ 2964 #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */ 2965 #define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */ 2966 2967 /* Bit fields for MSC CMD */ 2968 #define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ 2969 #define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */ 2970 #define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ 2971 #define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ 2972 #define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ 2973 #define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ 2974 #define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ 2975 #define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */ 2976 #define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */ 2977 #define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */ 2978 #define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ 2979 #define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ 2980 2981 /* Bit fields for MSC BOOTLOADERCTRL */ 2982 #define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */ 2983 #define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */ 2984 #define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */ 2985 #define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */ 2986 #define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */ 2987 #define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ 2988 #define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ 2989 #define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */ 2990 #define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */ 2991 #define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */ 2992 #define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */ 2993 #define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */ 2994 2995 /* Bit fields for MSC AAPUNLOCKCMD */ 2996 #define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */ 2997 #define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */ 2998 #define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */ 2999 #define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */ 3000 #define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */ 3001 #define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */ 3002 #define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */ 3003 3004 /* Bit fields for MSC CACHECONFIG0 */ 3005 #define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */ 3006 #define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */ 3007 #define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */ 3008 #define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */ 3009 #define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */ 3010 #define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */ 3011 #define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */ 3012 #define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */ 3013 #define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */ 3014 #define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */ 3015 #define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */ 3016 #define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */ 3017 3018 /* Bit fields for MSC RAMCTRL */ 3019 #define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */ 3020 #define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */ 3021 #define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ 3022 #define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */ 3023 #define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */ 3024 #define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ 3025 #define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ 3026 #define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */ 3027 #define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */ 3028 #define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */ 3029 #define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ 3030 #define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ 3031 #define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */ 3032 #define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */ 3033 #define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */ 3034 #define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ 3035 #define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ 3036 #define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */ 3037 #define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */ 3038 #define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */ 3039 #define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ 3040 #define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ 3041 #define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */ 3042 #define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */ 3043 #define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */ 3044 #define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ 3045 #define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ 3046 #define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */ 3047 #define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */ 3048 #define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */ 3049 #define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ 3050 #define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ 3051 #define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */ 3052 #define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */ 3053 #define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */ 3054 #define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */ 3055 #define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */ 3056 3057 /* Bit fields for MSC ECCCTRL */ 3058 #define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */ 3059 #define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */ 3060 #define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ 3061 #define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */ 3062 #define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */ 3063 #define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ 3064 #define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ 3065 #define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ 3066 #define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */ 3067 #define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */ 3068 #define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ 3069 #define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ 3070 #define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */ 3071 #define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */ 3072 #define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */ 3073 #define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ 3074 #define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ 3075 #define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */ 3076 #define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */ 3077 #define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */ 3078 #define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */ 3079 #define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */ 3080 3081 /* Bit fields for MSC RAMECCADDR */ 3082 #define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */ 3083 #define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */ 3084 #define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */ 3085 #define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */ 3086 #define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */ 3087 #define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */ 3088 3089 /* Bit fields for MSC RAM1ECCADDR */ 3090 #define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */ 3091 #define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */ 3092 #define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */ 3093 #define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */ 3094 #define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */ 3095 #define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */ 3096 3097 /** @} */ 3098 /** @} End of group EFM32GG11B520F2048GQ100_MSC */ 3099 3100 /***************************************************************************//** 3101 * @addtogroup EFM32GG11B520F2048GQ100_EMU 3102 * @{ 3103 * @defgroup EFM32GG11B520F2048GQ100_EMU_BitFields EMU Bit Fields 3104 * @{ 3105 ******************************************************************************/ 3106 3107 /* Bit fields for EMU CTRL */ 3108 #define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ 3109 #define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ 3110 #define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ 3111 #define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ 3112 #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ 3113 #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 3114 #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ 3115 #define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ 3116 #define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ 3117 #define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ 3118 #define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 3119 #define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ 3120 #define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ 3121 #define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ 3122 #define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ 3123 #define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 3124 #define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ 3125 #define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically Configures Flash and Frequency to Wakeup From EM2 or EM3 at Low Voltage */ 3126 #define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ 3127 #define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ 3128 #define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 3129 #define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ 3130 #define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ 3131 #define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ 3132 #define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 3133 #define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ 3134 #define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ 3135 #define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ 3136 #define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ 3137 #define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ 3138 #define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ 3139 #define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ 3140 #define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ 3141 #define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ 3142 #define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ 3143 #define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ 3144 #define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ 3145 #define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ 3146 #define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ 3147 #define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ 3148 #define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ 3149 #define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ 3150 3151 /* Bit fields for EMU STATUS */ 3152 #define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ 3153 #define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */ 3154 #define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON Ready */ 3155 #define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ 3156 #define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ 3157 #define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 3158 #define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ 3159 #define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel */ 3160 #define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ 3161 #define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ 3162 #define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 3163 #define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ 3164 #define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel */ 3165 #define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ 3166 #define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ 3167 #define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 3168 #define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ 3169 #define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel */ 3170 #define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ 3171 #define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ 3172 #define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 3173 #define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ 3174 #define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel */ 3175 #define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ 3176 #define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ 3177 #define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 3178 #define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ 3179 #define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel */ 3180 #define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */ 3181 #define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */ 3182 #define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 3183 #define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ 3184 #define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel */ 3185 #define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */ 3186 #define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */ 3187 #define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 3188 #define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */ 3189 #define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready */ 3190 #define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */ 3191 #define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */ 3192 #define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 3193 #define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ 3194 #define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ 3195 #define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ 3196 #define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 3197 #define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ 3198 #define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ 3199 #define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ 3200 #define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ 3201 #define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ 3202 #define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ 3203 #define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ 3204 #define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is Busy Scaling Voltage */ 3205 #define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ 3206 #define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ 3207 #define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 3208 #define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ 3209 #define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ 3210 #define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ 3211 #define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ 3212 #define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 3213 #define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ 3214 #define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ 3215 #define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ 3216 #define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ 3217 #define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ 3218 #define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ 3219 #define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ 3220 #define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ 3221 #define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ 3222 #define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ 3223 3224 /* Bit fields for EMU LOCK */ 3225 #define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ 3226 #define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ 3227 #define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ 3228 #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ 3229 #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ 3230 #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ 3231 #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ 3232 #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ 3233 #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ 3234 #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ 3235 #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ 3236 #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ 3237 #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ 3238 #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ 3239 3240 /* Bit fields for EMU RAM0CTRL */ 3241 #define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ 3242 #define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */ 3243 #define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ 3244 #define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */ 3245 #define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ 3246 #define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ 3247 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */ 3248 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */ 3249 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */ 3250 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */ 3251 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */ 3252 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */ 3253 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */ 3254 #define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ 3255 #define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ 3256 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */ 3257 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */ 3258 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */ 3259 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */ 3260 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */ 3261 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */ 3262 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */ 3263 3264 /* Bit fields for EMU CMD */ 3265 #define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ 3266 #define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ 3267 #define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ 3268 #define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ 3269 #define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ 3270 #define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ 3271 #define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ 3272 #define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 0 */ 3273 #define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ 3274 #define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ 3275 #define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ 3276 #define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ 3277 #define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to Scale to Voltage Scale Level 2 */ 3278 #define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ 3279 #define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ 3280 #define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ 3281 #define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ 3282 3283 /* Bit fields for EMU EM4CTRL */ 3284 #define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ 3285 #define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ 3286 #define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ 3287 #define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ 3288 #define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ 3289 #define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 3290 #define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ 3291 #define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ 3292 #define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 3293 #define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ 3294 #define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ 3295 #define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain During EM4 */ 3296 #define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ 3297 #define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ 3298 #define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 3299 #define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 3300 #define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain During EM4 */ 3301 #define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ 3302 #define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ 3303 #define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 3304 #define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 3305 #define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain During EM4S */ 3306 #define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ 3307 #define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ 3308 #define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 3309 #define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 3310 #define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ 3311 #define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ 3312 #define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 3313 #define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ 3314 #define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ 3315 #define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ 3316 #define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 3317 #define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ 3318 #define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ 3319 #define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ 3320 #define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ 3321 #define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ 3322 #define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ 3323 #define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ 3324 3325 /* Bit fields for EMU TEMPLIMITS */ 3326 #define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ 3327 #define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ 3328 #define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ 3329 #define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ 3330 #define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ 3331 #define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ 3332 #define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ 3333 #define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ 3334 #define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ 3335 #define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ 3336 #define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup Due to Low/high Temperature */ 3337 #define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ 3338 #define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ 3339 #define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ 3340 #define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ 3341 3342 /* Bit fields for EMU TEMP */ 3343 #define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ 3344 #define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ 3345 #define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ 3346 #define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ 3347 #define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ 3348 #define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ 3349 3350 /* Bit fields for EMU IF */ 3351 #define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ 3352 #define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */ 3353 #define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ 3354 #define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ 3355 #define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ 3356 #define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3357 #define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ 3358 #define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ 3359 #define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ 3360 #define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ 3361 #define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3362 #define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ 3363 #define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ 3364 #define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ 3365 #define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ 3366 #define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3367 #define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ 3368 #define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ 3369 #define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ 3370 #define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ 3371 #define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3372 #define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ 3373 #define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ 3374 #define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ 3375 #define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ 3376 #define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3377 #define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ 3378 #define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ 3379 #define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ 3380 #define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ 3381 #define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3382 #define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ 3383 #define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ 3384 #define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ 3385 #define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ 3386 #define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3387 #define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ 3388 #define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ 3389 #define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ 3390 #define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ 3391 #define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3392 #define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ 3393 #define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */ 3394 #define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ 3395 #define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ 3396 #define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3397 #define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */ 3398 #define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */ 3399 #define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ 3400 #define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ 3401 #define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3402 #define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */ 3403 #define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V Regulator is Ready to Use */ 3404 #define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ 3405 #define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ 3406 #define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3407 #define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */ 3408 #define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */ 3409 #define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ 3410 #define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ 3411 #define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3412 #define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */ 3413 #define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */ 3414 #define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ 3415 #define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ 3416 #define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3417 #define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */ 3418 #define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET Current Limit Hit */ 3419 #define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ 3420 #define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ 3421 #define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3422 #define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ 3423 #define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET Current Limit Hit */ 3424 #define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ 3425 #define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ 3426 #define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3427 #define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ 3428 #define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP Mode is Running */ 3429 #define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ 3430 #define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ 3431 #define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3432 #define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ 3433 #define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN Mode is Running */ 3434 #define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ 3435 #define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ 3436 #define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3437 #define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ 3438 #define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in Bypass */ 3439 #define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ 3440 #define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ 3441 #define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3442 #define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ 3443 #define EMU_IF_BURDY (0x1UL << 22) /**< Backup Functionality Ready Interrupt Flag */ 3444 #define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ 3445 #define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ 3446 #define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3447 #define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */ 3448 #define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V Regulator Voltage Update Done */ 3449 #define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ 3450 #define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ 3451 #define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3452 #define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */ 3453 #define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ From EM2 and EM3 */ 3454 #define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ 3455 #define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ 3456 #define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3457 #define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ 3458 #define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ 3459 #define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ 3460 #define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ 3461 #define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3462 #define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ 3463 #define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ 3464 #define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 3465 #define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 3466 #define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3467 #define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ 3468 #define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ 3469 #define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 3470 #define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 3471 #define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3472 #define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ 3473 #define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ 3474 #define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 3475 #define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 3476 #define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ 3477 #define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ 3478 3479 /* Bit fields for EMU IFS */ 3480 #define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ 3481 #define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */ 3482 #define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ 3483 #define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ 3484 #define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ 3485 #define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3486 #define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ 3487 #define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ 3488 #define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ 3489 #define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ 3490 #define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3491 #define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ 3492 #define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ 3493 #define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ 3494 #define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ 3495 #define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3496 #define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ 3497 #define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ 3498 #define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ 3499 #define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ 3500 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3501 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ 3502 #define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ 3503 #define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ 3504 #define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ 3505 #define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3506 #define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ 3507 #define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ 3508 #define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ 3509 #define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ 3510 #define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3511 #define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ 3512 #define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ 3513 #define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ 3514 #define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ 3515 #define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3516 #define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ 3517 #define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ 3518 #define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ 3519 #define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ 3520 #define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3521 #define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ 3522 #define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */ 3523 #define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ 3524 #define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ 3525 #define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3526 #define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */ 3527 #define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */ 3528 #define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ 3529 #define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ 3530 #define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3531 #define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */ 3532 #define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */ 3533 #define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ 3534 #define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ 3535 #define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3536 #define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */ 3537 #define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */ 3538 #define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ 3539 #define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ 3540 #define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3541 #define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */ 3542 #define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */ 3543 #define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ 3544 #define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ 3545 #define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3546 #define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */ 3547 #define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ 3548 #define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ 3549 #define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ 3550 #define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3551 #define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ 3552 #define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ 3553 #define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ 3554 #define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ 3555 #define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3556 #define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ 3557 #define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ 3558 #define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ 3559 #define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ 3560 #define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3561 #define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ 3562 #define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ 3563 #define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ 3564 #define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ 3565 #define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3566 #define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ 3567 #define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ 3568 #define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ 3569 #define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ 3570 #define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3571 #define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ 3572 #define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */ 3573 #define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ 3574 #define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ 3575 #define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3576 #define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */ 3577 #define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */ 3578 #define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ 3579 #define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ 3580 #define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3581 #define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */ 3582 #define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ 3583 #define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ 3584 #define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ 3585 #define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3586 #define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ 3587 #define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ 3588 #define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ 3589 #define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ 3590 #define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3591 #define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ 3592 #define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ 3593 #define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 3594 #define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 3595 #define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3596 #define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ 3597 #define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ 3598 #define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 3599 #define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 3600 #define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3601 #define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ 3602 #define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ 3603 #define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 3604 #define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 3605 #define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ 3606 #define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ 3607 3608 /* Bit fields for EMU IFC */ 3609 #define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ 3610 #define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */ 3611 #define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ 3612 #define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ 3613 #define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ 3614 #define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3615 #define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ 3616 #define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ 3617 #define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ 3618 #define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ 3619 #define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3620 #define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ 3621 #define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ 3622 #define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ 3623 #define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ 3624 #define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3625 #define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ 3626 #define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ 3627 #define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ 3628 #define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ 3629 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3630 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ 3631 #define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ 3632 #define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ 3633 #define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ 3634 #define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3635 #define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ 3636 #define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ 3637 #define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ 3638 #define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ 3639 #define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3640 #define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ 3641 #define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ 3642 #define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ 3643 #define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ 3644 #define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3645 #define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ 3646 #define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ 3647 #define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ 3648 #define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ 3649 #define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3650 #define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ 3651 #define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */ 3652 #define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ 3653 #define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ 3654 #define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3655 #define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */ 3656 #define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */ 3657 #define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ 3658 #define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ 3659 #define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3660 #define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */ 3661 #define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */ 3662 #define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ 3663 #define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ 3664 #define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3665 #define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */ 3666 #define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */ 3667 #define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ 3668 #define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ 3669 #define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3670 #define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */ 3671 #define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */ 3672 #define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ 3673 #define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ 3674 #define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3675 #define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */ 3676 #define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ 3677 #define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ 3678 #define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ 3679 #define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3680 #define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ 3681 #define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ 3682 #define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ 3683 #define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ 3684 #define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3685 #define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ 3686 #define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ 3687 #define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ 3688 #define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ 3689 #define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3690 #define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ 3691 #define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ 3692 #define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ 3693 #define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ 3694 #define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3695 #define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ 3696 #define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ 3697 #define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ 3698 #define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ 3699 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3700 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ 3701 #define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */ 3702 #define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ 3703 #define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ 3704 #define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3705 #define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */ 3706 #define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */ 3707 #define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ 3708 #define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ 3709 #define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3710 #define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */ 3711 #define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ 3712 #define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ 3713 #define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ 3714 #define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3715 #define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ 3716 #define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ 3717 #define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ 3718 #define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ 3719 #define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3720 #define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ 3721 #define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ 3722 #define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 3723 #define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 3724 #define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3725 #define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ 3726 #define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ 3727 #define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 3728 #define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 3729 #define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3730 #define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ 3731 #define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ 3732 #define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 3733 #define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 3734 #define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ 3735 #define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ 3736 3737 /* Bit fields for EMU IEN */ 3738 #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ 3739 #define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */ 3740 #define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ 3741 #define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ 3742 #define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ 3743 #define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3744 #define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ 3745 #define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ 3746 #define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ 3747 #define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ 3748 #define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3749 #define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ 3750 #define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ 3751 #define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ 3752 #define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ 3753 #define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3754 #define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ 3755 #define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ 3756 #define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ 3757 #define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ 3758 #define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3759 #define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ 3760 #define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ 3761 #define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ 3762 #define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ 3763 #define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3764 #define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ 3765 #define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ 3766 #define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ 3767 #define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ 3768 #define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3769 #define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ 3770 #define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ 3771 #define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ 3772 #define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ 3773 #define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3774 #define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ 3775 #define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ 3776 #define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ 3777 #define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ 3778 #define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3779 #define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ 3780 #define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */ 3781 #define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */ 3782 #define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */ 3783 #define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3784 #define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */ 3785 #define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */ 3786 #define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */ 3787 #define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */ 3788 #define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3789 #define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */ 3790 #define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */ 3791 #define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */ 3792 #define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */ 3793 #define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3794 #define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */ 3795 #define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */ 3796 #define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */ 3797 #define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */ 3798 #define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3799 #define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */ 3800 #define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */ 3801 #define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */ 3802 #define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */ 3803 #define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3804 #define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */ 3805 #define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ 3806 #define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ 3807 #define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ 3808 #define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3809 #define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ 3810 #define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ 3811 #define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ 3812 #define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ 3813 #define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3814 #define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ 3815 #define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ 3816 #define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ 3817 #define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ 3818 #define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3819 #define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ 3820 #define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ 3821 #define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ 3822 #define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ 3823 #define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3824 #define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ 3825 #define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ 3826 #define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ 3827 #define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ 3828 #define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3829 #define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ 3830 #define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */ 3831 #define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */ 3832 #define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */ 3833 #define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3834 #define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */ 3835 #define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */ 3836 #define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */ 3837 #define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */ 3838 #define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3839 #define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */ 3840 #define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ 3841 #define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ 3842 #define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ 3843 #define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3844 #define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ 3845 #define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ 3846 #define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ 3847 #define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ 3848 #define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3849 #define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ 3850 #define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ 3851 #define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ 3852 #define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ 3853 #define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3854 #define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ 3855 #define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ 3856 #define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ 3857 #define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ 3858 #define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3859 #define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ 3860 #define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ 3861 #define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ 3862 #define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ 3863 #define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ 3864 #define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ 3865 3866 /* Bit fields for EMU PWRLOCK */ 3867 #define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ 3868 #define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ 3869 #define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ 3870 #define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ 3871 #define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ 3872 #define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ 3873 #define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ 3874 #define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ 3875 #define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ 3876 #define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ 3877 #define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ 3878 #define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ 3879 #define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ 3880 #define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ 3881 3882 /* Bit fields for EMU PWRCTRL */ 3883 #define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ 3884 #define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */ 3885 #define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ 3886 #define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ 3887 #define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ 3888 #define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ 3889 #define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ 3890 #define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ 3891 #define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ 3892 #define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ 3893 #define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ 3894 #define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This Field Selects the Input Supply Pin for the Digital LDO */ 3895 #define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ 3896 #define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ 3897 #define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ 3898 #define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ 3899 #define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ 3900 #define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ 3901 #define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ 3902 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ 3903 #define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows Immediate Switching of ANASW and REGPWRSEL Bitfields */ 3904 #define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */ 3905 #define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */ 3906 #define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ 3907 #define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ 3908 3909 /* Bit fields for EMU DCDCCTRL */ 3910 #define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ 3911 #define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ 3912 #define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ 3913 #define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ 3914 #define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ 3915 #define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ 3916 #define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ 3917 #define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ 3918 #define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ 3919 #define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ 3920 #define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ 3921 #define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ 3922 #define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ 3923 #define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ 3924 #define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ 3925 #define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ 3926 #define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ 3927 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ 3928 #define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ 3929 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ 3930 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ 3931 #define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ 3932 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ 3933 #define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ 3934 #define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ 3935 #define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ 3936 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ 3937 #define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ 3938 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ 3939 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ 3940 #define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ 3941 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ 3942 3943 /* Bit fields for EMU DCDCMISCCTRL */ 3944 #define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ 3945 #define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ 3946 #define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC Into CCM Mode in Low Noise Operation */ 3947 #define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ 3948 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ 3949 #define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 3950 #define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 3951 #define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP Mode Hysteresis in the State Machine Control */ 3952 #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ 3953 #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ 3954 #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 3955 #define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 3956 #define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator Threshold on the High Side */ 3957 #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ 3958 #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ 3959 #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 3960 #define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 3961 #define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC Into CCM Mode Immediately, Based on LNFORCECCM */ 3962 #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ 3963 #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ 3964 #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 3965 #define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 3966 #define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ 3967 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ 3968 #define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 3969 #define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 3970 #define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ 3971 #define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ 3972 #define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 3973 #define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 3974 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ 3975 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ 3976 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 3977 #define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 3978 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ 3979 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ 3980 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 3981 #define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 3982 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ 3983 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ 3984 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 3985 #define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 3986 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ 3987 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ 3988 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ 3989 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ 3990 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ 3991 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ 3992 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ 3993 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ 3994 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ 3995 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ 3996 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ 3997 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ 3998 3999 /* Bit fields for EMU DCDCZDETCTRL */ 4000 #define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ 4001 #define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ 4002 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ 4003 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ 4004 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ 4005 #define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ 4006 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ 4007 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ 4008 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ 4009 #define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ 4010 4011 /* Bit fields for EMU DCDCCLIMCTRL */ 4012 #define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ 4013 #define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ 4014 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ 4015 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ 4016 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ 4017 #define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ 4018 #define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ 4019 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ 4020 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ 4021 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ 4022 #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ 4023 4024 /* Bit fields for EMU DCDCLNCOMPCTRL */ 4025 #define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ 4026 #define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ 4027 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ 4028 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ 4029 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 4030 #define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 4031 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ 4032 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ 4033 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 4034 #define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 4035 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ 4036 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ 4037 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 4038 #define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 4039 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ 4040 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ 4041 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 4042 #define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 4043 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ 4044 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ 4045 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 4046 #define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 4047 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ 4048 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ 4049 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 4050 #define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ 4051 4052 /* Bit fields for EMU DCDCLNVCTRL */ 4053 #define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ 4054 #define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ 4055 #define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ 4056 #define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ 4057 #define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ 4058 #define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ 4059 #define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ 4060 #define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ 4061 #define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ 4062 #define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ 4063 #define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ 4064 #define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ 4065 #define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ 4066 #define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ 4067 #define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ 4068 4069 /* Bit fields for EMU DCDCLPVCTRL */ 4070 #define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ 4071 #define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ 4072 #define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low Power Feedback Attenuation */ 4073 #define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ 4074 #define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ 4075 #define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ 4076 #define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ 4077 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ 4078 #define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ 4079 #define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ 4080 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ 4081 #define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ 4082 #define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ 4083 #define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ 4084 #define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ 4085 4086 /* Bit fields for EMU DCDCLPCTRL */ 4087 #define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ 4088 #define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ 4089 #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ 4090 #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ 4091 #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ 4092 #define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ 4093 #define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP Mode Duty Cycling Enable */ 4094 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ 4095 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ 4096 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ 4097 #define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ 4098 #define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ 4099 #define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ 4100 #define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ 4101 #define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ 4102 4103 /* Bit fields for EMU DCDCLNFREQCTRL */ 4104 #define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ 4105 #define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ 4106 #define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ 4107 #define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ 4108 #define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ 4109 #define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ 4110 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ 4111 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ 4112 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ 4113 #define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ 4114 4115 /* Bit fields for EMU DCDCSYNC */ 4116 #define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ 4117 #define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ 4118 #define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy */ 4119 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ 4120 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ 4121 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ 4122 #define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ 4123 4124 /* Bit fields for EMU VMONAVDDCTRL */ 4125 #define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ 4126 #define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ 4127 #define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ 4128 #define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ 4129 #define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ 4130 #define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ 4131 #define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ 4132 #define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ 4133 #define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ 4134 #define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ 4135 #define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ 4136 #define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ 4137 #define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ 4138 #define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ 4139 #define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ 4140 #define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ 4141 #define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ 4142 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ 4143 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ 4144 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ 4145 #define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ 4146 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ 4147 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ 4148 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ 4149 #define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ 4150 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ 4151 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ 4152 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ 4153 #define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ 4154 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ 4155 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ 4156 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ 4157 #define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ 4158 4159 /* Bit fields for EMU VMONALTAVDDCTRL */ 4160 #define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ 4161 #define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ 4162 #define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ 4163 #define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ 4164 #define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ 4165 #define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ 4166 #define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ 4167 #define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ 4168 #define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ 4169 #define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ 4170 #define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ 4171 #define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ 4172 #define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ 4173 #define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ 4174 #define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ 4175 #define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ 4176 #define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ 4177 #define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ 4178 #define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ 4179 #define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ 4180 #define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ 4181 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ 4182 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ 4183 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ 4184 #define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ 4185 4186 /* Bit fields for EMU VMONDVDDCTRL */ 4187 #define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ 4188 #define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ 4189 #define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ 4190 #define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ 4191 #define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ 4192 #define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ 4193 #define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ 4194 #define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ 4195 #define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ 4196 #define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ 4197 #define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ 4198 #define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ 4199 #define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ 4200 #define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ 4201 #define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ 4202 #define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ 4203 #define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ 4204 #define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ 4205 #define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ 4206 #define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ 4207 #define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ 4208 #define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ 4209 #define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ 4210 #define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ 4211 #define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ 4212 4213 /* Bit fields for EMU VMONIO0CTRL */ 4214 #define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ 4215 #define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ 4216 #define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ 4217 #define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ 4218 #define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ 4219 #define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ 4220 #define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ 4221 #define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ 4222 #define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ 4223 #define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ 4224 #define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ 4225 #define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ 4226 #define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ 4227 #define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ 4228 #define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ 4229 #define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ 4230 #define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ 4231 #define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention Disable */ 4232 #define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ 4233 #define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ 4234 #define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ 4235 #define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ 4236 #define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ 4237 #define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ 4238 #define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ 4239 #define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ 4240 #define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ 4241 #define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ 4242 #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ 4243 #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ 4244 4245 /* Bit fields for EMU VMONIO1CTRL */ 4246 #define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */ 4247 #define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */ 4248 #define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */ 4249 #define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ 4250 #define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ 4251 #define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ 4252 #define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ 4253 #define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ 4254 #define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ 4255 #define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ 4256 #define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ 4257 #define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ 4258 #define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ 4259 #define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ 4260 #define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ 4261 #define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ 4262 #define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ 4263 #define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention Disable */ 4264 #define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ 4265 #define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ 4266 #define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ 4267 #define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ 4268 #define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ 4269 #define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ 4270 #define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ 4271 #define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ 4272 #define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ 4273 #define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ 4274 #define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */ 4275 #define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */ 4276 4277 /* Bit fields for EMU VMONBUVDDCTRL */ 4278 #define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */ 4279 #define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */ 4280 #define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */ 4281 #define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ 4282 #define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ 4283 #define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ 4284 #define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ 4285 #define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ 4286 #define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ 4287 #define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ 4288 #define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ 4289 #define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ 4290 #define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ 4291 #define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ 4292 #define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ 4293 #define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ 4294 #define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ 4295 #define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ 4296 #define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ 4297 #define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ 4298 #define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ 4299 #define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ 4300 #define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ 4301 #define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */ 4302 #define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */ 4303 4304 /* Bit fields for EMU RAM1CTRL */ 4305 #define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ 4306 #define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */ 4307 #define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ 4308 #define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */ 4309 #define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ 4310 #define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ 4311 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */ 4312 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */ 4313 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */ 4314 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */ 4315 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */ 4316 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */ 4317 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */ 4318 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */ 4319 #define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ 4320 #define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ 4321 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */ 4322 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */ 4323 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */ 4324 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */ 4325 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */ 4326 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */ 4327 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */ 4328 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */ 4329 4330 /* Bit fields for EMU RAM2CTRL */ 4331 #define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ 4332 #define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */ 4333 #define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ 4334 #define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ 4335 #define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ 4336 #define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ 4337 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */ 4338 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */ 4339 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */ 4340 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */ 4341 #define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ 4342 #define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ 4343 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */ 4344 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */ 4345 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */ 4346 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */ 4347 4348 /* Bit fields for EMU BUCTRL */ 4349 #define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ 4350 #define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */ 4351 #define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable Backup Mode */ 4352 #define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ 4353 #define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ 4354 #define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 4355 #define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 4356 #define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable Backup Mode Status Export */ 4357 #define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ 4358 #define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ 4359 #define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 4360 #define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 4361 #define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN Probing */ 4362 #define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */ 4363 #define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */ 4364 #define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 4365 #define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 4366 #define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */ 4367 #define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */ 4368 #define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 4369 #define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */ 4370 #define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */ 4371 #define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */ 4372 #define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */ 4373 #define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 4374 #define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */ 4375 #define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */ 4376 #define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */ 4377 #define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */ 4378 #define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */ 4379 #define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */ 4380 #define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 4381 #define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */ 4382 #define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */ 4383 #define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */ 4384 #define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */ 4385 #define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 4386 #define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */ 4387 #define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */ 4388 #define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */ 4389 #define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */ 4390 #define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */ 4391 #define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */ 4392 #define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 4393 #define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ 4394 #define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ 4395 #define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ 4396 #define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ 4397 #define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 4398 #define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */ 4399 #define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */ 4400 #define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */ 4401 #define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */ 4402 #define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */ 4403 #define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */ 4404 #define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 4405 #define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */ 4406 #define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */ 4407 #define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */ 4408 #define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */ 4409 #define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 4410 #define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */ 4411 #define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */ 4412 #define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */ 4413 #define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */ 4414 #define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU Comparator */ 4415 #define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */ 4416 #define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */ 4417 #define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ 4418 #define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */ 4419 4420 /* Bit fields for EMU R5VCTRL */ 4421 #define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */ 4422 #define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */ 4423 #define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */ 4424 #define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */ 4425 #define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */ 4426 #define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ 4427 #define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ 4428 #define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup Due to VBUS Detection */ 4429 #define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */ 4430 #define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */ 4431 #define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ 4432 #define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ 4433 #define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the Regulator Current Monitor for Selected Current Path to Either VREGI or VBUS */ 4434 #define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */ 4435 #define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */ 4436 #define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ 4437 #define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ 4438 #define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */ 4439 #define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */ 4440 #define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */ 4441 #define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */ 4442 #define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */ 4443 #define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */ 4444 #define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */ 4445 #define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */ 4446 #define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */ 4447 #define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */ 4448 4449 /* Bit fields for EMU R5VADCCTRL */ 4450 #define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */ 4451 #define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */ 4452 #define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V Subsystem ADC MUX */ 4453 #define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */ 4454 #define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */ 4455 #define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ 4456 #define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ 4457 #define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */ 4458 #define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */ 4459 #define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */ 4460 #define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */ 4461 #define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */ 4462 #define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */ 4463 #define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */ 4464 #define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */ 4465 #define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */ 4466 #define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */ 4467 #define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */ 4468 #define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */ 4469 #define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */ 4470 #define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */ 4471 4472 /* Bit fields for EMU R5VOUTLEVEL */ 4473 #define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */ 4474 #define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */ 4475 #define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */ 4476 #define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */ 4477 #define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */ 4478 #define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */ 4479 4480 /* Bit fields for EMU R5VDETCTRL */ 4481 #define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */ 4482 #define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */ 4483 #define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */ 4484 #define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */ 4485 #define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */ 4486 #define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ 4487 #define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ 4488 #define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */ 4489 #define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */ 4490 #define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */ 4491 #define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ 4492 #define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ 4493 #define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */ 4494 #define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */ 4495 #define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */ 4496 #define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */ 4497 #define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */ 4498 4499 /* Bit fields for EMU DCDCLPEM01CFG */ 4500 #define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ 4501 #define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ 4502 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ 4503 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ 4504 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ 4505 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ 4506 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ 4507 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ 4508 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ 4509 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ 4510 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ 4511 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ 4512 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ 4513 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ 4514 #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ 4515 #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ 4516 #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ 4517 #define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ 4518 4519 /* Bit fields for EMU R5VSTATUS */ 4520 #define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */ 4521 #define _EMU_R5VSTATUS_MASK 0x0000003DUL /**< Mask for EMU_R5VSTATUS */ 4522 #define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI Detected */ 4523 #define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */ 4524 #define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */ 4525 #define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ 4526 #define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ 4527 #define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO Detected */ 4528 #define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */ 4529 #define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */ 4530 #define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ 4531 #define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ 4532 #define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the Supply Comparator Between VBUS and VREGI */ 4533 #define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */ 4534 #define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */ 4535 #define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ 4536 #define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ 4537 #define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator Dropout Detection */ 4538 #define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */ 4539 #define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */ 4540 #define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */ 4541 #define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ 4542 #define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates If the Regulator is Going Through a Cold Start */ 4543 #define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */ 4544 #define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */ 4545 #define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */ 4546 #define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */ 4547 4548 /* Bit fields for EMU R5VSYNC */ 4549 #define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */ 4550 #define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */ 4551 #define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy */ 4552 #define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */ 4553 #define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */ 4554 #define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */ 4555 #define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */ 4556 4557 /* Bit fields for EMU EM23PERNORETAINCMD */ 4558 #define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ 4559 #define _EMU_EM23PERNORETAINCMD_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ 4560 #define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears Status Bit of ACMP0 and Unlocks Access to It */ 4561 #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ 4562 #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ 4563 #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4564 #define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4565 #define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears Status Bit of ACMP1 and Unlocks Access to It */ 4566 #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ 4567 #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ 4568 #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4569 #define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4570 #define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears Status Bit of PCNT0 and Unlocks Access to It */ 4571 #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ 4572 #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ 4573 #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4574 #define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4575 #define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears Status Bit of PCNT1 and Unlocks Access to It */ 4576 #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ 4577 #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ 4578 #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4579 #define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4580 #define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears Status Bit of PCNT2 and Unlocks Access to It */ 4581 #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ 4582 #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ 4583 #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4584 #define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4585 #define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears Status Bit of I2C0 and Unlocks Access to It */ 4586 #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ 4587 #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ 4588 #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4589 #define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4590 #define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears Status Bit of I2C1 and Unlocks Access to It */ 4591 #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ 4592 #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ 4593 #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4594 #define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4595 #define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears Status Bit of DAC0 and Unlocks Access to It */ 4596 #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ 4597 #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ 4598 #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4599 #define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4600 #define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears Status Bit of IDAC0 and Unlocks Access to It */ 4601 #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ 4602 #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ 4603 #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4604 #define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4605 #define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears Status Bit of ADC0 and Unlocks Access to It */ 4606 #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ 4607 #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ 4608 #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4609 #define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4610 #define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears Status Bit of LETIMER0 and Unlocks Access to It */ 4611 #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ 4612 #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ 4613 #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4614 #define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4615 #define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears Status Bit of WDOG0 and Unlocks Access to It */ 4616 #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ 4617 #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ 4618 #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4619 #define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4620 #define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears Status Bit of WDOG1 and Unlocks Access to It */ 4621 #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ 4622 #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ 4623 #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4624 #define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4625 #define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears Status Bit of LESENSE0 and Unlocks Access to It */ 4626 #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ 4627 #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ 4628 #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4629 #define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4630 #define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears Status Bit of CSEN and Unlocks Access to It */ 4631 #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ 4632 #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ 4633 #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4634 #define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4635 #define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears Status Bit of LEUART0 and Unlocks Access to It */ 4636 #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ 4637 #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ 4638 #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4639 #define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4640 #define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears Status Bit of LEUART1 and Unlocks Access to It */ 4641 #define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */ 4642 #define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */ 4643 #define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4644 #define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4645 #define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears Status Bit of LCD and Unlocks Access to It */ 4646 #define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */ 4647 #define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */ 4648 #define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4649 #define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4650 #define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears Status Bit of LETIMER1 and Unlocks Access to It */ 4651 #define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */ 4652 #define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */ 4653 #define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4654 #define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4655 #define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears Status Bit of I2C2 and Unlocks Access to It */ 4656 #define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */ 4657 #define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */ 4658 #define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4659 #define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4660 #define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears Status Bit of ADC1 and Unlocks Access to It */ 4661 #define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */ 4662 #define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */ 4663 #define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4664 #define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4665 #define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears Status Bit of ACMP2 and Unlocks Access to It */ 4666 #define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */ 4667 #define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */ 4668 #define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4669 #define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4670 #define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears Status Bit of ACMP3 and Unlocks Access to It */ 4671 #define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */ 4672 #define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */ 4673 #define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4674 #define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4675 #define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears Status Bit of RTC and Unlocks Access to It */ 4676 #define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */ 4677 #define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */ 4678 #define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4679 #define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ 4680 4681 /* Bit fields for EMU EM23PERNORETAINSTATUS */ 4682 #define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ 4683 #define _EMU_EM23PERNORETAINSTATUS_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ 4684 #define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates If ACMP0 Powered Down During EM23 */ 4685 #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ 4686 #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ 4687 #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4688 #define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4689 #define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates If ACMP1 Powered Down During EM23 */ 4690 #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ 4691 #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ 4692 #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4693 #define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4694 #define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates If PCNT0 Powered Down During EM23 */ 4695 #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ 4696 #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ 4697 #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4698 #define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4699 #define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates If PCNT1 Powered Down During EM23 */ 4700 #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ 4701 #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ 4702 #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4703 #define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4704 #define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates If PCNT2 Powered Down During EM23 */ 4705 #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ 4706 #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ 4707 #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4708 #define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4709 #define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates If I2C0 Powered Down During EM23 */ 4710 #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ 4711 #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ 4712 #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4713 #define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4714 #define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates If I2C1 Powered Down During EM23 */ 4715 #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ 4716 #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ 4717 #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4718 #define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4719 #define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates If DAC0 Powered Down During EM23 */ 4720 #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ 4721 #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ 4722 #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4723 #define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4724 #define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates If IDAC0 Powered Down During EM23 */ 4725 #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ 4726 #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ 4727 #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4728 #define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4729 #define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates If ADC0 Powered Down During EM23 */ 4730 #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ 4731 #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ 4732 #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4733 #define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4734 #define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates If LETIMER0 Powered Down During EM23 */ 4735 #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ 4736 #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ 4737 #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4738 #define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4739 #define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates If WDOG0 Powered Down During EM23 */ 4740 #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ 4741 #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ 4742 #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4743 #define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4744 #define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates If WDOG1 Powered Down During EM23 */ 4745 #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ 4746 #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ 4747 #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4748 #define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4749 #define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates If LESENSE0 Powered Down During EM23 */ 4750 #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ 4751 #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ 4752 #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4753 #define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4754 #define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates If CSEN Powered Down During EM23 */ 4755 #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ 4756 #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ 4757 #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4758 #define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4759 #define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates If LEUART0 Powered Down During EM23 */ 4760 #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ 4761 #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ 4762 #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4763 #define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4764 #define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates If LEUART1 Powered Down During EM23 */ 4765 #define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */ 4766 #define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */ 4767 #define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4768 #define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4769 #define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates If LCD Powered Down During EM23 */ 4770 #define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */ 4771 #define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */ 4772 #define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4773 #define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4774 #define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates If LETIMER1 Powered Down During EM23 */ 4775 #define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */ 4776 #define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */ 4777 #define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4778 #define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4779 #define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates If I2C2 Powered Down During EM23 */ 4780 #define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */ 4781 #define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */ 4782 #define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4783 #define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4784 #define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates If ADC1 Powered Down During EM23 */ 4785 #define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */ 4786 #define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */ 4787 #define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4788 #define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4789 #define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates If ACMP2 Powered Down During EM23 */ 4790 #define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */ 4791 #define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */ 4792 #define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4793 #define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4794 #define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates If ACMP3 Powered Down During EM23 */ 4795 #define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */ 4796 #define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */ 4797 #define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4798 #define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4799 #define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates If RTC Powered Down During EM23 */ 4800 #define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */ 4801 #define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */ 4802 #define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4803 #define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ 4804 4805 /* Bit fields for EMU EM23PERNORETAINCTRL */ 4806 #define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ 4807 #define _EMU_EM23PERNORETAINCTRL_MASK 0x00FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ 4808 #define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow Power Down of ACMP0 During EM23 */ 4809 #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ 4810 #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ 4811 #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4812 #define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4813 #define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow Power Down of ACMP1 During EM23 */ 4814 #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ 4815 #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ 4816 #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4817 #define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4818 #define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow Power Down of PCNT0 During EM23 */ 4819 #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ 4820 #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ 4821 #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4822 #define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4823 #define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow Power Down of PCNT1 During EM23 */ 4824 #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ 4825 #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ 4826 #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4827 #define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4828 #define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow Power Down of PCNT2 During EM23 */ 4829 #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ 4830 #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ 4831 #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4832 #define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4833 #define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow Power Down of I2C0 During EM23 */ 4834 #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ 4835 #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ 4836 #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4837 #define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4838 #define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow Power Down of I2C1 During EM23 */ 4839 #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ 4840 #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ 4841 #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4842 #define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4843 #define EMU_EM23PERNORETAINCTRL_VDAC0DIS (0x1UL << 7) /**< Allow Power Down of DAC0 During EM23 */ 4844 #define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_SHIFT 7 /**< Shift value for EMU_VDAC0DIS */ 4845 #define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK 0x80UL /**< Bit mask for EMU_VDAC0DIS */ 4846 #define _EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4847 #define EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_VDAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4848 #define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow Power Down of IDAC0 During EM23 */ 4849 #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ 4850 #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ 4851 #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4852 #define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4853 #define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow Power Down of ADC0 During EM23 */ 4854 #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ 4855 #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ 4856 #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4857 #define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4858 #define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow Power Down of LETIMER0 During EM23 */ 4859 #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ 4860 #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ 4861 #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4862 #define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4863 #define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow Power Down of WDOG0 During EM23 */ 4864 #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ 4865 #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ 4866 #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4867 #define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4868 #define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow Power Down of WDOG1 During EM23 */ 4869 #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ 4870 #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ 4871 #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4872 #define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4873 #define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow Power Down of LESENSE0 During EM23 */ 4874 #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ 4875 #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ 4876 #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4877 #define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4878 #define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow Power Down of CSEN During EM23 */ 4879 #define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ 4880 #define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ 4881 #define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4882 #define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4883 #define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow Power Down of LEUART0 During EM23 */ 4884 #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ 4885 #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ 4886 #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4887 #define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4888 #define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow Power Down of LEUART1 During EM23 */ 4889 #define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */ 4890 #define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */ 4891 #define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4892 #define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4893 #define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow Power Down of LCD During EM23 */ 4894 #define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */ 4895 #define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */ 4896 #define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4897 #define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4898 #define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow Power Down of LETIMER1 During EM23 */ 4899 #define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */ 4900 #define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */ 4901 #define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4902 #define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4903 #define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow Power Down of I2C2 During EM23 */ 4904 #define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */ 4905 #define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */ 4906 #define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4907 #define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4908 #define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow Power Down of ADC1 During EM23 */ 4909 #define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */ 4910 #define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */ 4911 #define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4912 #define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4913 #define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow Power Down of ACMP2 During EM23 */ 4914 #define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */ 4915 #define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */ 4916 #define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4917 #define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4918 #define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow Power Down of ACMP3 During EM23 */ 4919 #define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */ 4920 #define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */ 4921 #define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4922 #define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4923 #define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow Power Down of RTC During EM23 */ 4924 #define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */ 4925 #define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */ 4926 #define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4927 #define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ 4928 4929 /** @} */ 4930 /** @} End of group EFM32GG11B520F2048GQ100_EMU */ 4931 4932 /***************************************************************************//** 4933 * @addtogroup EFM32GG11B520F2048GQ100_CMU 4934 * @{ 4935 * @defgroup EFM32GG11B520F2048GQ100_CMU_BitFields CMU Bit Fields 4936 * @{ 4937 ******************************************************************************/ 4938 4939 /* Bit fields for CMU CTRL */ 4940 #define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ 4941 #define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ 4942 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ 4943 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ 4944 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 4945 #define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ 4946 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ 4947 #define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ 4948 #define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ 4949 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ 4950 #define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ 4951 #define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ 4952 #define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ 4953 #define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ 4954 #define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ 4955 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ 4956 #define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ 4957 #define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ 4958 #define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ 4959 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ 4960 #define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ 4961 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ 4962 #define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ 4963 #define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ 4964 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ 4965 #define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ 4966 #define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ 4967 #define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ 4968 #define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ 4969 #define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ 4970 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ 4971 #define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ 4972 #define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ 4973 #define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ 4974 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ 4975 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ 4976 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 4977 #define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ 4978 #define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ 4979 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ 4980 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ 4981 #define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ 4982 #define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ 4983 #define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ 4984 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ 4985 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ 4986 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ 4987 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ 4988 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ 4989 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ 4990 #define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ 4991 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ 4992 #define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ 4993 #define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ 4994 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ 4995 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ 4996 #define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ 4997 #define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ 4998 #define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ 4999 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ 5000 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ 5001 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ 5002 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ 5003 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ 5004 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ 5005 #define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ 5006 #define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ 5007 #define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ 5008 #define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 5009 #define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ 5010 #define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ 5011 #define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ 5012 #define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ 5013 #define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ 5014 #define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ 5015 #define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ 5016 #define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ 5017 #define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ 5018 #define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ 5019 #define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ 5020 #define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ 5021 #define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ 5022 #define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ 5023 #define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ 5024 #define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ 5025 #define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ 5026 #define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ 5027 #define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ 5028 #define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ 5029 #define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ 5030 #define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ 5031 #define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ 5032 #define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ 5033 #define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ 5034 #define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ 5035 #define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ 5036 #define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ 5037 #define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ 5038 #define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ 5039 #define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ 5040 #define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ 5041 #define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ 5042 #define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ 5043 #define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ 5044 #define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ 5045 #define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 5046 #define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ 5047 #define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ 5048 #define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ 5049 #define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ 5050 #define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ 5051 #define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ 5052 5053 /* Bit fields for CMU USHFRCOCTRL */ 5054 #define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ 5055 #define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ 5056 #define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 5057 #define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 5058 #define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 5059 #define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 5060 #define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ 5061 #define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ 5062 #define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 5063 #define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 5064 #define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ 5065 #define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ 5066 #define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 5067 #define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 5068 #define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ 5069 #define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ 5070 #define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 5071 #define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 5072 #define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ 5073 #define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ 5074 #define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ 5075 #define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 5076 #define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 5077 #define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ 5078 #define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ 5079 #define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 5080 #define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ 5081 #define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ 5082 #define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ 5083 #define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 5084 #define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ 5085 #define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ 5086 #define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ 5087 #define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ 5088 #define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ 5089 #define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ 5090 #define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 5091 #define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 5092 #define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ 5093 #define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ 5094 #define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 5095 #define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 5096 5097 /* Bit fields for CMU HFRCOCTRL */ 5098 #define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ 5099 #define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ 5100 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 5101 #define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 5102 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 5103 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 5104 #define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ 5105 #define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ 5106 #define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 5107 #define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 5108 #define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ 5109 #define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ 5110 #define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 5111 #define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 5112 #define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ 5113 #define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ 5114 #define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 5115 #define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 5116 #define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ 5117 #define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ 5118 #define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ 5119 #define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 5120 #define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 5121 #define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ 5122 #define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ 5123 #define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 5124 #define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ 5125 #define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ 5126 #define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ 5127 #define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 5128 #define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ 5129 #define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ 5130 #define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ 5131 #define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ 5132 #define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ 5133 #define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ 5134 #define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 5135 #define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 5136 #define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ 5137 #define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ 5138 #define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 5139 #define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 5140 5141 /* Bit fields for CMU AUXHFRCOCTRL */ 5142 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ 5143 #define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ 5144 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 5145 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 5146 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 5147 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 5148 #define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ 5149 #define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ 5150 #define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 5151 #define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 5152 #define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ 5153 #define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ 5154 #define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 5155 #define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 5156 #define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ 5157 #define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ 5158 #define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 5159 #define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 5160 #define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ 5161 #define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ 5162 #define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ 5163 #define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 5164 #define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 5165 #define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ 5166 #define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ 5167 #define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 5168 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ 5169 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ 5170 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ 5171 #define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 5172 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ 5173 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ 5174 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ 5175 #define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ 5176 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ 5177 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ 5178 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 5179 #define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 5180 #define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ 5181 #define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ 5182 #define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 5183 #define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 5184 5185 /* Bit fields for CMU LFRCOCTRL */ 5186 #define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL /**< Default value for CMU_LFRCOCTRL */ 5187 #define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ 5188 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 5189 #define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ 5190 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 5191 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 5192 #define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ 5193 #define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ 5194 #define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ 5195 #define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 5196 #define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 5197 #define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ 5198 #define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ 5199 #define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ 5200 #define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 5201 #define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 5202 #define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ 5203 #define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ 5204 #define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ 5205 #define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 5206 #define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 5207 #define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ 5208 #define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ 5209 #define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 5210 #define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ 5211 #define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ 5212 #define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ 5213 #define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ 5214 #define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 5215 #define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ 5216 #define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ 5217 #define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ 5218 #define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ 5219 #define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ 5220 #define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ 5221 #define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ 5222 #define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 5223 #define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ 5224 #define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ 5225 #define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ 5226 #define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 5227 #define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ 5228 #define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ 5229 #define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ 5230 #define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ 5231 #define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 5232 #define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 5233 5234 /* Bit fields for CMU HFXOCTRL */ 5235 #define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ 5236 #define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ 5237 #define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ 5238 #define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ 5239 #define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 5240 #define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ 5241 #define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ 5242 #define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ 5243 #define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ 5244 #define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 5245 #define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ 5246 #define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ 5247 #define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ 5248 #define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ 5249 #define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ 5250 #define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ 5251 #define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ 5252 #define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 5253 #define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 5254 #define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ 5255 #define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ 5256 #define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 5257 #define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ 5258 #define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ 5259 #define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ 5260 #define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ 5261 #define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 5262 #define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ 5263 #define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ 5264 #define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ 5265 #define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ 5266 #define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ 5267 #define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ 5268 #define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 5269 #define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ 5270 #define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ 5271 #define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ 5272 #define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ 5273 #define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ 5274 #define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ 5275 #define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ 5276 #define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ 5277 #define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 5278 #define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ 5279 #define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ 5280 #define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ 5281 #define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ 5282 #define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ 5283 #define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ 5284 #define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ 5285 #define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ 5286 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ 5287 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ 5288 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ 5289 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 5290 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 5291 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ 5292 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ 5293 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ 5294 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 5295 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 5296 5297 /* Bit fields for CMU HFXOCTRL1 */ 5298 #define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ 5299 #define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ 5300 #define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ 5301 #define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ 5302 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ 5303 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ 5304 #define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ 5305 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ 5306 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ 5307 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ 5308 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ 5309 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ 5310 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ 5311 #define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ 5312 #define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ 5313 #define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ 5314 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ 5315 #define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ 5316 #define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ 5317 #define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ 5318 #define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ 5319 #define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ 5320 5321 /* Bit fields for CMU HFXOSTARTUPCTRL */ 5322 #define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ 5323 #define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ 5324 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ 5325 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ 5326 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 5327 #define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 5328 #define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ 5329 #define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ 5330 #define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 5331 #define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 5332 5333 /* Bit fields for CMU HFXOSTEADYSTATECTRL */ 5334 #define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ 5335 #define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ 5336 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ 5337 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ 5338 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 5339 #define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 5340 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ 5341 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ 5342 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 5343 #define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 5344 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ 5345 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ 5346 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ 5347 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 5348 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 5349 #define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ 5350 #define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ 5351 #define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ 5352 #define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 5353 #define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 5354 5355 /* Bit fields for CMU HFXOTIMEOUTCTRL */ 5356 #define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ 5357 #define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ 5358 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ 5359 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ 5360 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 5361 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 5362 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 5363 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 5364 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ 5365 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ 5366 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 5367 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5368 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5369 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5370 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5371 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5372 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5373 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5374 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 5375 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5376 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 5377 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 5378 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 5379 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 5380 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ 5381 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ 5382 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 5383 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5384 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5385 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5386 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5387 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5388 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5389 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5390 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 5391 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5392 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ 5393 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ 5394 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 5395 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 5396 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 5397 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 5398 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ 5399 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ 5400 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 5401 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5402 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 5403 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5404 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5405 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5406 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5407 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5408 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5409 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5410 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 5411 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 5412 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 5413 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 5414 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ 5415 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ 5416 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 5417 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5418 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 5419 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5420 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5421 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5422 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5423 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5424 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5425 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5426 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ 5427 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ 5428 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 5429 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 5430 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 5431 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 5432 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ 5433 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ 5434 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 5435 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5436 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5437 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5438 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5439 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5440 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5441 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 5442 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5443 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5444 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 5445 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 5446 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 5447 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 5448 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ 5449 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ 5450 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 5451 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5452 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5453 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5454 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5455 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5456 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5457 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 5458 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5459 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ 5460 5461 /* Bit fields for CMU LFXOCTRL */ 5462 #define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ 5463 #define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ 5464 #define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 5465 #define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 5466 #define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 5467 #define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 5468 #define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ 5469 #define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ 5470 #define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 5471 #define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ 5472 #define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ 5473 #define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ 5474 #define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 5475 #define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ 5476 #define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ 5477 #define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ 5478 #define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ 5479 #define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ 5480 #define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 5481 #define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 5482 #define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ 5483 #define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ 5484 #define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ 5485 #define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 5486 #define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 5487 #define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ 5488 #define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ 5489 #define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ 5490 #define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 5491 #define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 5492 #define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ 5493 #define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ 5494 #define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 5495 #define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 5496 #define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ 5497 #define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ 5498 #define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ 5499 #define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 5500 #define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 5501 #define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ 5502 #define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ 5503 #define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ 5504 #define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ 5505 #define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ 5506 #define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ 5507 #define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ 5508 #define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ 5509 #define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ 5510 #define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 5511 #define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ 5512 #define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ 5513 #define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ 5514 #define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ 5515 #define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ 5516 #define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ 5517 #define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ 5518 #define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ 5519 #define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 5520 #define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ 5521 5522 /* Bit fields for CMU DPLLCTRL */ 5523 #define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ 5524 #define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ 5525 #define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ 5526 #define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ 5527 #define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ 5528 #define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 5529 #define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ 5530 #define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ 5531 #define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 5532 #define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ 5533 #define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ 5534 #define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ 5535 #define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ 5536 #define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ 5537 #define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 5538 #define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ 5539 #define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ 5540 #define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 5541 #define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ 5542 #define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ 5543 #define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ 5544 #define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ 5545 #define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ 5546 #define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 5547 #define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 5548 #define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ 5549 #define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ 5550 #define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 5551 #define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ 5552 #define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ 5553 #define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ 5554 #define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ 5555 #define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 5556 #define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ 5557 #define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ 5558 #define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ 5559 #define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ 5560 #define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ 5561 #define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ 5562 #define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ 5563 #define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 5564 #define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 5565 5566 /* Bit fields for CMU DPLLCTRL1 */ 5567 #define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ 5568 #define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ 5569 #define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ 5570 #define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ 5571 #define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ 5572 #define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ 5573 #define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ 5574 #define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ 5575 #define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ 5576 #define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ 5577 5578 /* Bit fields for CMU CALCTRL */ 5579 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ 5580 #define _CMU_CALCTRL_MASK 0x1F1F01F7UL /**< Mask for CMU_CALCTRL */ 5581 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ 5582 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ 5583 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 5584 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ 5585 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ 5586 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ 5587 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ 5588 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ 5589 #define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ 5590 #define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ 5591 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 5592 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ 5593 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ 5594 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ 5595 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ 5596 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ 5597 #define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ 5598 #define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ 5599 #define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ 5600 #define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ 5601 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 5602 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ 5603 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ 5604 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ 5605 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ 5606 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ 5607 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ 5608 #define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ 5609 #define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ 5610 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 5611 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ 5612 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ 5613 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ 5614 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ 5615 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ 5616 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ 5617 #define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ 5618 #define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ 5619 #define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ 5620 #define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ 5621 #define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ 5622 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 5623 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 5624 #define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ 5625 #define _CMU_CALCTRL_PRSUPSEL_MASK 0x1F0000UL /**< Bit mask for CMU_PRSUPSEL */ 5626 #define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 5627 #define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ 5628 #define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ 5629 #define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ 5630 #define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ 5631 #define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ 5632 #define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ 5633 #define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ 5634 #define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ 5635 #define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ 5636 #define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ 5637 #define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ 5638 #define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ 5639 #define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ 5640 #define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ 5641 #define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ 5642 #define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ 5643 #define _CMU_CALCTRL_PRSUPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ 5644 #define _CMU_CALCTRL_PRSUPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ 5645 #define _CMU_CALCTRL_PRSUPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ 5646 #define _CMU_CALCTRL_PRSUPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ 5647 #define _CMU_CALCTRL_PRSUPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ 5648 #define _CMU_CALCTRL_PRSUPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ 5649 #define _CMU_CALCTRL_PRSUPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ 5650 #define _CMU_CALCTRL_PRSUPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ 5651 #define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 5652 #define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ 5653 #define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ 5654 #define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ 5655 #define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ 5656 #define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ 5657 #define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ 5658 #define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ 5659 #define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ 5660 #define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ 5661 #define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ 5662 #define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ 5663 #define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ 5664 #define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ 5665 #define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ 5666 #define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ 5667 #define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ 5668 #define CMU_CALCTRL_PRSUPSEL_PRSCH16 (_CMU_CALCTRL_PRSUPSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ 5669 #define CMU_CALCTRL_PRSUPSEL_PRSCH17 (_CMU_CALCTRL_PRSUPSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ 5670 #define CMU_CALCTRL_PRSUPSEL_PRSCH18 (_CMU_CALCTRL_PRSUPSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ 5671 #define CMU_CALCTRL_PRSUPSEL_PRSCH19 (_CMU_CALCTRL_PRSUPSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ 5672 #define CMU_CALCTRL_PRSUPSEL_PRSCH20 (_CMU_CALCTRL_PRSUPSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ 5673 #define CMU_CALCTRL_PRSUPSEL_PRSCH21 (_CMU_CALCTRL_PRSUPSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ 5674 #define CMU_CALCTRL_PRSUPSEL_PRSCH22 (_CMU_CALCTRL_PRSUPSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ 5675 #define CMU_CALCTRL_PRSUPSEL_PRSCH23 (_CMU_CALCTRL_PRSUPSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ 5676 #define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ 5677 #define _CMU_CALCTRL_PRSDOWNSEL_MASK 0x1F000000UL /**< Bit mask for CMU_PRSDOWNSEL */ 5678 #define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 5679 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ 5680 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ 5681 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ 5682 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ 5683 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ 5684 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ 5685 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ 5686 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ 5687 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ 5688 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ 5689 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ 5690 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ 5691 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ 5692 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ 5693 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ 5694 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ 5695 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for CMU_CALCTRL */ 5696 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for CMU_CALCTRL */ 5697 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for CMU_CALCTRL */ 5698 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for CMU_CALCTRL */ 5699 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for CMU_CALCTRL */ 5700 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for CMU_CALCTRL */ 5701 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for CMU_CALCTRL */ 5702 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for CMU_CALCTRL */ 5703 #define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 5704 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ 5705 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ 5706 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ 5707 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ 5708 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ 5709 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ 5710 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ 5711 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ 5712 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ 5713 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ 5714 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ 5715 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ 5716 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ 5717 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ 5718 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ 5719 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ 5720 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH16 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH16 << 24) /**< Shifted mode PRSCH16 for CMU_CALCTRL */ 5721 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH17 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH17 << 24) /**< Shifted mode PRSCH17 for CMU_CALCTRL */ 5722 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH18 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH18 << 24) /**< Shifted mode PRSCH18 for CMU_CALCTRL */ 5723 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH19 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH19 << 24) /**< Shifted mode PRSCH19 for CMU_CALCTRL */ 5724 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH20 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH20 << 24) /**< Shifted mode PRSCH20 for CMU_CALCTRL */ 5725 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH21 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH21 << 24) /**< Shifted mode PRSCH21 for CMU_CALCTRL */ 5726 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH22 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH22 << 24) /**< Shifted mode PRSCH22 for CMU_CALCTRL */ 5727 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH23 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH23 << 24) /**< Shifted mode PRSCH23 for CMU_CALCTRL */ 5728 5729 /* Bit fields for CMU CALCNT */ 5730 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ 5731 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ 5732 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ 5733 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ 5734 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ 5735 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ 5736 5737 /* Bit fields for CMU OSCENCMD */ 5738 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ 5739 #define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ 5740 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ 5741 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ 5742 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ 5743 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 5744 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 5745 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ 5746 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ 5747 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ 5748 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 5749 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 5750 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ 5751 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ 5752 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ 5753 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 5754 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 5755 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ 5756 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ 5757 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ 5758 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 5759 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 5760 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ 5761 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ 5762 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ 5763 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 5764 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 5765 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ 5766 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ 5767 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ 5768 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 5769 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 5770 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ 5771 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ 5772 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ 5773 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 5774 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 5775 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ 5776 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ 5777 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ 5778 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 5779 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 5780 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ 5781 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ 5782 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ 5783 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 5784 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 5785 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ 5786 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ 5787 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ 5788 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 5789 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 5790 #define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ 5791 #define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ 5792 #define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ 5793 #define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 5794 #define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 5795 #define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ 5796 #define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ 5797 #define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ 5798 #define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 5799 #define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 5800 #define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ 5801 #define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ 5802 #define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ 5803 #define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 5804 #define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 5805 #define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ 5806 #define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ 5807 #define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ 5808 #define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 5809 #define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 5810 5811 /* Bit fields for CMU CMD */ 5812 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ 5813 #define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ 5814 #define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ 5815 #define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ 5816 #define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ 5817 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 5818 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ 5819 #define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ 5820 #define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ 5821 #define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ 5822 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 5823 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ 5824 #define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ 5825 #define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ 5826 #define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ 5827 #define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 5828 #define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ 5829 5830 /* Bit fields for CMU DBGCLKSEL */ 5831 #define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ 5832 #define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ 5833 #define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ 5834 #define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ 5835 #define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ 5836 #define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ 5837 #define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ 5838 #define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ 5839 #define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ 5840 #define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ 5841 #define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ 5842 #define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ 5843 5844 /* Bit fields for CMU HFCLKSEL */ 5845 #define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ 5846 #define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ 5847 #define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ 5848 #define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ 5849 #define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ 5850 #define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ 5851 #define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ 5852 #define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ 5853 #define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ 5854 #define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ 5855 #define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ 5856 #define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ 5857 #define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ 5858 #define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ 5859 #define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ 5860 #define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ 5861 #define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ 5862 #define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ 5863 #define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ 5864 #define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ 5865 5866 /* Bit fields for CMU LFACLKSEL */ 5867 #define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ 5868 #define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ 5869 #define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ 5870 #define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ 5871 #define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ 5872 #define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ 5873 #define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ 5874 #define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ 5875 #define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ 5876 #define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ 5877 #define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ 5878 #define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ 5879 #define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ 5880 #define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ 5881 5882 /* Bit fields for CMU LFBCLKSEL */ 5883 #define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ 5884 #define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ 5885 #define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ 5886 #define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ 5887 #define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ 5888 #define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ 5889 #define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ 5890 #define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ 5891 #define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ 5892 #define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ 5893 #define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ 5894 #define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ 5895 #define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ 5896 #define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ 5897 #define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ 5898 #define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ 5899 5900 /* Bit fields for CMU LFECLKSEL */ 5901 #define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ 5902 #define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ 5903 #define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ 5904 #define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ 5905 #define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ 5906 #define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ 5907 #define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ 5908 #define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ 5909 #define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ 5910 #define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ 5911 #define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ 5912 #define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ 5913 #define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ 5914 #define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ 5915 5916 /* Bit fields for CMU LFCCLKSEL */ 5917 #define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ 5918 #define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ 5919 #define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ 5920 #define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ 5921 #define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ 5922 #define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ 5923 #define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ 5924 #define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ 5925 #define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ 5926 #define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ 5927 #define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ 5928 #define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ 5929 #define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ 5930 #define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ 5931 5932 /* Bit fields for CMU STATUS */ 5933 #define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ 5934 #define _CMU_STATUS_MASK 0x3A413FFFUL /**< Mask for CMU_STATUS */ 5935 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ 5936 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ 5937 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ 5938 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 5939 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ 5940 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ 5941 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ 5942 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ 5943 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 5944 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ 5945 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ 5946 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ 5947 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ 5948 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 5949 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ 5950 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ 5951 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ 5952 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ 5953 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 5954 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ 5955 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ 5956 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ 5957 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ 5958 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 5959 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ 5960 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ 5961 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ 5962 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ 5963 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 5964 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ 5965 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ 5966 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ 5967 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ 5968 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 5969 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ 5970 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ 5971 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ 5972 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ 5973 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 5974 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ 5975 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ 5976 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ 5977 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ 5978 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 5979 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ 5980 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ 5981 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ 5982 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ 5983 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 5984 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ 5985 #define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ 5986 #define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ 5987 #define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ 5988 #define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 5989 #define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ 5990 #define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ 5991 #define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ 5992 #define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ 5993 #define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 5994 #define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ 5995 #define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ 5996 #define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ 5997 #define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ 5998 #define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 5999 #define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ 6000 #define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ 6001 #define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ 6002 #define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ 6003 #define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 6004 #define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ 6005 #define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ 6006 #define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ 6007 #define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ 6008 #define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 6009 #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ 6010 #define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ 6011 #define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ 6012 #define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 6013 #define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 6014 #define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ 6015 #define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ 6016 #define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ 6017 #define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ 6018 #define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 6019 #define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ 6020 #define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ 6021 #define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ 6022 #define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ 6023 #define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 6024 #define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ 6025 #define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ 6026 #define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ 6027 #define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ 6028 #define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 6029 #define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ 6030 #define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ 6031 #define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ 6032 #define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ 6033 #define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 6034 #define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ 6035 6036 /* Bit fields for CMU HFCLKSTATUS */ 6037 #define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ 6038 #define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ 6039 #define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ 6040 #define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ 6041 #define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ 6042 #define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ 6043 #define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ 6044 #define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ 6045 #define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ 6046 #define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ 6047 #define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ 6048 #define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ 6049 #define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ 6050 #define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ 6051 #define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ 6052 #define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ 6053 #define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ 6054 #define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ 6055 #define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ 6056 #define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ 6057 6058 /* Bit fields for CMU HFXOTRIMSTATUS */ 6059 #define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ 6060 #define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ 6061 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ 6062 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ 6063 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ 6064 #define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ 6065 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ 6066 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ 6067 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ 6068 #define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ 6069 #define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ 6070 #define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ 6071 #define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ 6072 #define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ 6073 #define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ 6074 #define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ 6075 #define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ 6076 #define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ 6077 #define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ 6078 #define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ 6079 6080 /* Bit fields for CMU IF */ 6081 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ 6082 #define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ 6083 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ 6084 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 6085 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 6086 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ 6087 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ 6088 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ 6089 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 6090 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 6091 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6092 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ 6093 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ 6094 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 6095 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 6096 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6097 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ 6098 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ 6099 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 6100 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 6101 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6102 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ 6103 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ 6104 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 6105 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 6106 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6107 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ 6108 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ 6109 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 6110 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 6111 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6112 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ 6113 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ 6114 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 6115 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 6116 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6117 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ 6118 #define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ 6119 #define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ 6120 #define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ 6121 #define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6122 #define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ 6123 #define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ 6124 #define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 6125 #define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 6126 #define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6127 #define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ 6128 #define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ 6129 #define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 6130 #define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 6131 #define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6132 #define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ 6133 #define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ 6134 #define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 6135 #define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 6136 #define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6137 #define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ 6138 #define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ 6139 #define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 6140 #define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 6141 #define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6142 #define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ 6143 #define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ 6144 #define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 6145 #define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 6146 #define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6147 #define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ 6148 #define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ 6149 #define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 6150 #define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 6151 #define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6152 #define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ 6153 #define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ 6154 #define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 6155 #define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 6156 #define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6157 #define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ 6158 #define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ 6159 #define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 6160 #define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 6161 #define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6162 #define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ 6163 #define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ 6164 #define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 6165 #define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 6166 #define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6167 #define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ 6168 #define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ 6169 #define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 6170 #define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 6171 #define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6172 #define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ 6173 #define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ 6174 #define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 6175 #define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 6176 #define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6177 #define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ 6178 #define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ 6179 #define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 6180 #define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 6181 #define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 6182 #define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ 6183 6184 /* Bit fields for CMU IFS */ 6185 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ 6186 #define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ 6187 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ 6188 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 6189 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 6190 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6191 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ 6192 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ 6193 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 6194 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 6195 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6196 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ 6197 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ 6198 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 6199 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 6200 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6201 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ 6202 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ 6203 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 6204 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 6205 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6206 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ 6207 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ 6208 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 6209 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 6210 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6211 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ 6212 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ 6213 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 6214 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 6215 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6216 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ 6217 #define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ 6218 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 6219 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 6220 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6221 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ 6222 #define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ 6223 #define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ 6224 #define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ 6225 #define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6226 #define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ 6227 #define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ 6228 #define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 6229 #define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 6230 #define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6231 #define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ 6232 #define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ 6233 #define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 6234 #define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 6235 #define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6236 #define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ 6237 #define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ 6238 #define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 6239 #define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 6240 #define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6241 #define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ 6242 #define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ 6243 #define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 6244 #define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 6245 #define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6246 #define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ 6247 #define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ 6248 #define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 6249 #define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 6250 #define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6251 #define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ 6252 #define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ 6253 #define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 6254 #define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 6255 #define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6256 #define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ 6257 #define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ 6258 #define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 6259 #define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 6260 #define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6261 #define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ 6262 #define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ 6263 #define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 6264 #define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 6265 #define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6266 #define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ 6267 #define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ 6268 #define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 6269 #define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 6270 #define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6271 #define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ 6272 #define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ 6273 #define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 6274 #define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 6275 #define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6276 #define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ 6277 #define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ 6278 #define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 6279 #define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 6280 #define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6281 #define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ 6282 #define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ 6283 #define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 6284 #define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 6285 #define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 6286 #define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ 6287 6288 /* Bit fields for CMU IFC */ 6289 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ 6290 #define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ 6291 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ 6292 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 6293 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 6294 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6295 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ 6296 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ 6297 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 6298 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 6299 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6300 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ 6301 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ 6302 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 6303 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 6304 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6305 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ 6306 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ 6307 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 6308 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 6309 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6310 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ 6311 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ 6312 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 6313 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 6314 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6315 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ 6316 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ 6317 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 6318 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 6319 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6320 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ 6321 #define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ 6322 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 6323 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 6324 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6325 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ 6326 #define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ 6327 #define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ 6328 #define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ 6329 #define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6330 #define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ 6331 #define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ 6332 #define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 6333 #define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 6334 #define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6335 #define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ 6336 #define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ 6337 #define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 6338 #define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 6339 #define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6340 #define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ 6341 #define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ 6342 #define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 6343 #define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 6344 #define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6345 #define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ 6346 #define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ 6347 #define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 6348 #define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 6349 #define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6350 #define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ 6351 #define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ 6352 #define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 6353 #define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 6354 #define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6355 #define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ 6356 #define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ 6357 #define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 6358 #define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 6359 #define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6360 #define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ 6361 #define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ 6362 #define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 6363 #define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 6364 #define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6365 #define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ 6366 #define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ 6367 #define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 6368 #define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 6369 #define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6370 #define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ 6371 #define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ 6372 #define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 6373 #define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 6374 #define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6375 #define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ 6376 #define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ 6377 #define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 6378 #define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 6379 #define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6380 #define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ 6381 #define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ 6382 #define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 6383 #define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 6384 #define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6385 #define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ 6386 #define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ 6387 #define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 6388 #define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 6389 #define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 6390 #define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ 6391 6392 /* Bit fields for CMU IEN */ 6393 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ 6394 #define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ 6395 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ 6396 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 6397 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 6398 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6399 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ 6400 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ 6401 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 6402 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 6403 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6404 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ 6405 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ 6406 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 6407 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 6408 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6409 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ 6410 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ 6411 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 6412 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 6413 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6414 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ 6415 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ 6416 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 6417 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 6418 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6419 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ 6420 #define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ 6421 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 6422 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 6423 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6424 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ 6425 #define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ 6426 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 6427 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 6428 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6429 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ 6430 #define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ 6431 #define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ 6432 #define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ 6433 #define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6434 #define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ 6435 #define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ 6436 #define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 6437 #define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 6438 #define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6439 #define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ 6440 #define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ 6441 #define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 6442 #define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 6443 #define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6444 #define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ 6445 #define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ 6446 #define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 6447 #define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 6448 #define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6449 #define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ 6450 #define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ 6451 #define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 6452 #define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 6453 #define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6454 #define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ 6455 #define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ 6456 #define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 6457 #define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 6458 #define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6459 #define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ 6460 #define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ 6461 #define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 6462 #define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 6463 #define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6464 #define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ 6465 #define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ 6466 #define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 6467 #define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 6468 #define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6469 #define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ 6470 #define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ 6471 #define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 6472 #define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 6473 #define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6474 #define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ 6475 #define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ 6476 #define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 6477 #define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 6478 #define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6479 #define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ 6480 #define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ 6481 #define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 6482 #define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 6483 #define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6484 #define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ 6485 #define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ 6486 #define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 6487 #define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 6488 #define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6489 #define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ 6490 #define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ 6491 #define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 6492 #define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 6493 #define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 6494 #define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ 6495 6496 /* Bit fields for CMU HFBUSCLKEN0 */ 6497 #define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ 6498 #define _CMU_HFBUSCLKEN0_MASK 0x000001E7UL /**< Mask for CMU_HFBUSCLKEN0 */ 6499 #define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ 6500 #define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ 6501 #define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ 6502 #define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 6503 #define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 6504 #define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ 6505 #define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ 6506 #define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ 6507 #define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 6508 #define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 6509 #define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ 6510 #define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ 6511 #define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ 6512 #define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 6513 #define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 6514 #define CMU_HFBUSCLKEN0_GPIO (0x1UL << 5) /**< General purpose Input/Output Clock Enable */ 6515 #define _CMU_HFBUSCLKEN0_GPIO_SHIFT 5 /**< Shift value for CMU_GPIO */ 6516 #define _CMU_HFBUSCLKEN0_GPIO_MASK 0x20UL /**< Bit mask for CMU_GPIO */ 6517 #define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 6518 #define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 6519 #define CMU_HFBUSCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ 6520 #define _CMU_HFBUSCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ 6521 #define _CMU_HFBUSCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ 6522 #define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 6523 #define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 6524 #define CMU_HFBUSCLKEN0_LDMA (0x1UL << 7) /**< Linked Direct Memory Access Controller Clock Enable */ 6525 #define _CMU_HFBUSCLKEN0_LDMA_SHIFT 7 /**< Shift value for CMU_LDMA */ 6526 #define _CMU_HFBUSCLKEN0_LDMA_MASK 0x80UL /**< Bit mask for CMU_LDMA */ 6527 #define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 6528 #define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 6529 #define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 8) /**< General Purpose CRC Clock Enable */ 6530 #define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 8 /**< Shift value for CMU_GPCRC */ 6531 #define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x100UL /**< Bit mask for CMU_GPCRC */ 6532 #define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 6533 #define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 6534 6535 /* Bit fields for CMU HFPERCLKEN0 */ 6536 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ 6537 #define _CMU_HFPERCLKEN0_MASK 0x01FFFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ 6538 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ 6539 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ 6540 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ 6541 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6542 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6543 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ 6544 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ 6545 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ 6546 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6547 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6548 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ 6549 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ 6550 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ 6551 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6552 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6553 #define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 3) /**< Timer 3 Clock Enable */ 6554 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT 3 /**< Shift value for CMU_TIMER3 */ 6555 #define _CMU_HFPERCLKEN0_TIMER3_MASK 0x8UL /**< Bit mask for CMU_TIMER3 */ 6556 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6557 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6558 #define CMU_HFPERCLKEN0_TIMER4 (0x1UL << 4) /**< Timer 4 Clock Enable */ 6559 #define _CMU_HFPERCLKEN0_TIMER4_SHIFT 4 /**< Shift value for CMU_TIMER4 */ 6560 #define _CMU_HFPERCLKEN0_TIMER4_MASK 0x10UL /**< Bit mask for CMU_TIMER4 */ 6561 #define _CMU_HFPERCLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6562 #define CMU_HFPERCLKEN0_TIMER4_DEFAULT (_CMU_HFPERCLKEN0_TIMER4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6563 #define CMU_HFPERCLKEN0_TIMER5 (0x1UL << 5) /**< Timer 5 Clock Enable */ 6564 #define _CMU_HFPERCLKEN0_TIMER5_SHIFT 5 /**< Shift value for CMU_TIMER5 */ 6565 #define _CMU_HFPERCLKEN0_TIMER5_MASK 0x20UL /**< Bit mask for CMU_TIMER5 */ 6566 #define _CMU_HFPERCLKEN0_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6567 #define CMU_HFPERCLKEN0_TIMER5_DEFAULT (_CMU_HFPERCLKEN0_TIMER5_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6568 #define CMU_HFPERCLKEN0_TIMER6 (0x1UL << 6) /**< Timer 6 Clock Enable */ 6569 #define _CMU_HFPERCLKEN0_TIMER6_SHIFT 6 /**< Shift value for CMU_TIMER6 */ 6570 #define _CMU_HFPERCLKEN0_TIMER6_MASK 0x40UL /**< Bit mask for CMU_TIMER6 */ 6571 #define _CMU_HFPERCLKEN0_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6572 #define CMU_HFPERCLKEN0_TIMER6_DEFAULT (_CMU_HFPERCLKEN0_TIMER6_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6573 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 7) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ 6574 #define _CMU_HFPERCLKEN0_USART0_SHIFT 7 /**< Shift value for CMU_USART0 */ 6575 #define _CMU_HFPERCLKEN0_USART0_MASK 0x80UL /**< Bit mask for CMU_USART0 */ 6576 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6577 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6578 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 8) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ 6579 #define _CMU_HFPERCLKEN0_USART1_SHIFT 8 /**< Shift value for CMU_USART1 */ 6580 #define _CMU_HFPERCLKEN0_USART1_MASK 0x100UL /**< Bit mask for CMU_USART1 */ 6581 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6582 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6583 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 9) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ 6584 #define _CMU_HFPERCLKEN0_USART2_SHIFT 9 /**< Shift value for CMU_USART2 */ 6585 #define _CMU_HFPERCLKEN0_USART2_MASK 0x200UL /**< Bit mask for CMU_USART2 */ 6586 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6587 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6588 #define CMU_HFPERCLKEN0_USART3 (0x1UL << 10) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ 6589 #define _CMU_HFPERCLKEN0_USART3_SHIFT 10 /**< Shift value for CMU_USART3 */ 6590 #define _CMU_HFPERCLKEN0_USART3_MASK 0x400UL /**< Bit mask for CMU_USART3 */ 6591 #define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6592 #define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6593 #define CMU_HFPERCLKEN0_USART4 (0x1UL << 11) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ 6594 #define _CMU_HFPERCLKEN0_USART4_SHIFT 11 /**< Shift value for CMU_USART4 */ 6595 #define _CMU_HFPERCLKEN0_USART4_MASK 0x800UL /**< Bit mask for CMU_USART4 */ 6596 #define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6597 #define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6598 #define CMU_HFPERCLKEN0_USART5 (0x1UL << 12) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable */ 6599 #define _CMU_HFPERCLKEN0_USART5_SHIFT 12 /**< Shift value for CMU_USART5 */ 6600 #define _CMU_HFPERCLKEN0_USART5_MASK 0x1000UL /**< Bit mask for CMU_USART5 */ 6601 #define _CMU_HFPERCLKEN0_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6602 #define CMU_HFPERCLKEN0_USART5_DEFAULT (_CMU_HFPERCLKEN0_USART5_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6603 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 13) /**< Analog Comparator 0 Clock Enable */ 6604 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 13 /**< Shift value for CMU_ACMP0 */ 6605 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x2000UL /**< Bit mask for CMU_ACMP0 */ 6606 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6607 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6608 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 14) /**< Analog Comparator 1 Clock Enable */ 6609 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 14 /**< Shift value for CMU_ACMP1 */ 6610 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x4000UL /**< Bit mask for CMU_ACMP1 */ 6611 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6612 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6613 #define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 15) /**< Analog Comparator 1 Clock Enable */ 6614 #define _CMU_HFPERCLKEN0_ACMP2_SHIFT 15 /**< Shift value for CMU_ACMP2 */ 6615 #define _CMU_HFPERCLKEN0_ACMP2_MASK 0x8000UL /**< Bit mask for CMU_ACMP2 */ 6616 #define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6617 #define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6618 #define CMU_HFPERCLKEN0_ACMP3 (0x1UL << 16) /**< Analog Comparator 3 Clock Enable */ 6619 #define _CMU_HFPERCLKEN0_ACMP3_SHIFT 16 /**< Shift value for CMU_ACMP3 */ 6620 #define _CMU_HFPERCLKEN0_ACMP3_MASK 0x10000UL /**< Bit mask for CMU_ACMP3 */ 6621 #define _CMU_HFPERCLKEN0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6622 #define CMU_HFPERCLKEN0_ACMP3_DEFAULT (_CMU_HFPERCLKEN0_ACMP3_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6623 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 17) /**< I2C 0 Clock Enable */ 6624 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 17 /**< Shift value for CMU_I2C0 */ 6625 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x20000UL /**< Bit mask for CMU_I2C0 */ 6626 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6627 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6628 #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 18) /**< I2C 1 Clock Enable */ 6629 #define _CMU_HFPERCLKEN0_I2C1_SHIFT 18 /**< Shift value for CMU_I2C1 */ 6630 #define _CMU_HFPERCLKEN0_I2C1_MASK 0x40000UL /**< Bit mask for CMU_I2C1 */ 6631 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6632 #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6633 #define CMU_HFPERCLKEN0_I2C2 (0x1UL << 19) /**< I2C 2 Clock Enable */ 6634 #define _CMU_HFPERCLKEN0_I2C2_SHIFT 19 /**< Shift value for CMU_I2C2 */ 6635 #define _CMU_HFPERCLKEN0_I2C2_MASK 0x80000UL /**< Bit mask for CMU_I2C2 */ 6636 #define _CMU_HFPERCLKEN0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6637 #define CMU_HFPERCLKEN0_I2C2_DEFAULT (_CMU_HFPERCLKEN0_I2C2_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6638 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 20) /**< Analog to Digital Converter 0 Clock Enable */ 6639 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 20 /**< Shift value for CMU_ADC0 */ 6640 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x100000UL /**< Bit mask for CMU_ADC0 */ 6641 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6642 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6643 #define CMU_HFPERCLKEN0_ADC1 (0x1UL << 21) /**< Analog to Digital Converter 0 Clock Enable */ 6644 #define _CMU_HFPERCLKEN0_ADC1_SHIFT 21 /**< Shift value for CMU_ADC1 */ 6645 #define _CMU_HFPERCLKEN0_ADC1_MASK 0x200000UL /**< Bit mask for CMU_ADC1 */ 6646 #define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6647 #define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6648 #define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 22) /**< CRYOTIMER Clock Enable */ 6649 #define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 22 /**< Shift value for CMU_CRYOTIMER */ 6650 #define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400000UL /**< Bit mask for CMU_CRYOTIMER */ 6651 #define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6652 #define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6653 #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 Clock Enable */ 6654 #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 23 /**< Shift value for CMU_IDAC0 */ 6655 #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x800000UL /**< Bit mask for CMU_IDAC0 */ 6656 #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6657 #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6658 #define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 24) /**< True Random Number Generator 0 Clock Enable */ 6659 #define _CMU_HFPERCLKEN0_TRNG0_SHIFT 24 /**< Shift value for CMU_TRNG0 */ 6660 #define _CMU_HFPERCLKEN0_TRNG0_MASK 0x1000000UL /**< Bit mask for CMU_TRNG0 */ 6661 #define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 6662 #define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 6663 6664 /* Bit fields for CMU HFPERCLKEN1 */ 6665 #define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ 6666 #define _CMU_HFPERCLKEN1_MASK 0x000003FFUL /**< Mask for CMU_HFPERCLKEN1 */ 6667 #define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 0) /**< Wide Timer 0 Clock Enable */ 6668 #define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 0 /**< Shift value for CMU_WTIMER0 */ 6669 #define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x1UL /**< Bit mask for CMU_WTIMER0 */ 6670 #define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 6671 #define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 6672 #define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 1) /**< Wide Timer 0 Clock Enable */ 6673 #define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 1 /**< Shift value for CMU_WTIMER1 */ 6674 #define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x2UL /**< Bit mask for CMU_WTIMER1 */ 6675 #define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 6676 #define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 6677 #define CMU_HFPERCLKEN1_WTIMER2 (0x1UL << 2) /**< Wide Timer 2 Clock Enable */ 6678 #define _CMU_HFPERCLKEN1_WTIMER2_SHIFT 2 /**< Shift value for CMU_WTIMER2 */ 6679 #define _CMU_HFPERCLKEN1_WTIMER2_MASK 0x4UL /**< Bit mask for CMU_WTIMER2 */ 6680 #define _CMU_HFPERCLKEN1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 6681 #define CMU_HFPERCLKEN1_WTIMER2_DEFAULT (_CMU_HFPERCLKEN1_WTIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 6682 #define CMU_HFPERCLKEN1_WTIMER3 (0x1UL << 3) /**< Wide Timer 3 Clock Enable */ 6683 #define _CMU_HFPERCLKEN1_WTIMER3_SHIFT 3 /**< Shift value for CMU_WTIMER3 */ 6684 #define _CMU_HFPERCLKEN1_WTIMER3_MASK 0x8UL /**< Bit mask for CMU_WTIMER3 */ 6685 #define _CMU_HFPERCLKEN1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 6686 #define CMU_HFPERCLKEN1_WTIMER3_DEFAULT (_CMU_HFPERCLKEN1_WTIMER3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 6687 #define CMU_HFPERCLKEN1_UART0 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ 6688 #define _CMU_HFPERCLKEN1_UART0_SHIFT 4 /**< Shift value for CMU_UART0 */ 6689 #define _CMU_HFPERCLKEN1_UART0_MASK 0x10UL /**< Bit mask for CMU_UART0 */ 6690 #define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 6691 #define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 6692 #define CMU_HFPERCLKEN1_UART1 (0x1UL << 5) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ 6693 #define _CMU_HFPERCLKEN1_UART1_SHIFT 5 /**< Shift value for CMU_UART1 */ 6694 #define _CMU_HFPERCLKEN1_UART1_MASK 0x20UL /**< Bit mask for CMU_UART1 */ 6695 #define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 6696 #define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 6697 #define CMU_HFPERCLKEN1_CAN0 (0x1UL << 6) /**< CAN 0 Clock Enable */ 6698 #define _CMU_HFPERCLKEN1_CAN0_SHIFT 6 /**< Shift value for CMU_CAN0 */ 6699 #define _CMU_HFPERCLKEN1_CAN0_MASK 0x40UL /**< Bit mask for CMU_CAN0 */ 6700 #define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 6701 #define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 6702 #define CMU_HFPERCLKEN1_CAN1 (0x1UL << 7) /**< CAN 1 Clock Enable */ 6703 #define _CMU_HFPERCLKEN1_CAN1_SHIFT 7 /**< Shift value for CMU_CAN1 */ 6704 #define _CMU_HFPERCLKEN1_CAN1_MASK 0x80UL /**< Bit mask for CMU_CAN1 */ 6705 #define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 6706 #define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 6707 #define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 8) /**< Digital to Analog Converter 0 Clock Enable */ 6708 #define _CMU_HFPERCLKEN1_VDAC0_SHIFT 8 /**< Shift value for CMU_VDAC0 */ 6709 #define _CMU_HFPERCLKEN1_VDAC0_MASK 0x100UL /**< Bit mask for CMU_VDAC0 */ 6710 #define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 6711 #define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 6712 #define CMU_HFPERCLKEN1_CSEN (0x1UL << 9) /**< Capacitive touch sense module Clock Enable */ 6713 #define _CMU_HFPERCLKEN1_CSEN_SHIFT 9 /**< Shift value for CMU_CSEN */ 6714 #define _CMU_HFPERCLKEN1_CSEN_MASK 0x200UL /**< Bit mask for CMU_CSEN */ 6715 #define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 6716 #define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 6717 6718 /* Bit fields for CMU LFACLKEN0 */ 6719 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ 6720 #define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ 6721 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ 6722 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ 6723 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ 6724 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 6725 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 6726 #define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ 6727 #define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ 6728 #define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ 6729 #define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 6730 #define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 6731 #define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ 6732 #define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ 6733 #define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ 6734 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 6735 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 6736 #define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ 6737 #define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ 6738 #define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ 6739 #define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 6740 #define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 6741 #define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ 6742 #define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ 6743 #define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ 6744 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 6745 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 6746 6747 /* Bit fields for CMU LFBCLKEN0 */ 6748 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ 6749 #define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ 6750 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ 6751 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ 6752 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ 6753 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 6754 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 6755 #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ 6756 #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ 6757 #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ 6758 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 6759 #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 6760 #define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ 6761 #define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ 6762 #define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ 6763 #define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 6764 #define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 6765 #define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ 6766 #define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ 6767 #define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ 6768 #define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 6769 #define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 6770 6771 /* Bit fields for CMU LFCCLKEN0 */ 6772 #define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ 6773 #define _CMU_LFCCLKEN0_MASK 0x00000000UL /**< Mask for CMU_LFCCLKEN0 */ 6774 6775 /* Bit fields for CMU LFECLKEN0 */ 6776 #define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ 6777 #define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ 6778 #define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ 6779 #define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ 6780 #define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ 6781 #define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ 6782 #define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ 6783 6784 /* Bit fields for CMU HFPRESC */ 6785 #define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ 6786 #define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ 6787 #define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 6788 #define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ 6789 #define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ 6790 #define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ 6791 #define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ 6792 #define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ 6793 #define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ 6794 #define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ 6795 #define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ 6796 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ 6797 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ 6798 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ 6799 #define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ 6800 #define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ 6801 #define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ 6802 #define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ 6803 6804 /* Bit fields for CMU HFBUSPRESC */ 6805 #define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ 6806 #define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ 6807 #define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 6808 #define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ 6809 #define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ 6810 #define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ 6811 #define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ 6812 #define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ 6813 6814 /* Bit fields for CMU HFCOREPRESC */ 6815 #define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ 6816 #define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ 6817 #define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 6818 #define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ 6819 #define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ 6820 #define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ 6821 #define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ 6822 #define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ 6823 6824 /* Bit fields for CMU HFPERPRESC */ 6825 #define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ 6826 #define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ 6827 #define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 6828 #define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ 6829 #define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ 6830 #define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ 6831 #define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ 6832 #define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ 6833 6834 /* Bit fields for CMU HFEXPPRESC */ 6835 #define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ 6836 #define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ 6837 #define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 6838 #define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ 6839 #define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ 6840 #define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ 6841 #define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ 6842 #define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ 6843 6844 /* Bit fields for CMU HFPERPRESCB */ 6845 #define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ 6846 #define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ 6847 #define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 6848 #define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ 6849 #define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ 6850 #define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ 6851 #define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ 6852 #define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ 6853 6854 /* Bit fields for CMU HFPERPRESCC */ 6855 #define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ 6856 #define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ 6857 #define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 6858 #define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ 6859 #define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ 6860 #define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ 6861 #define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ 6862 #define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ 6863 6864 /* Bit fields for CMU LFAPRESC0 */ 6865 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ 6866 #define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ 6867 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ 6868 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ 6869 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 6870 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 6871 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 6872 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 6873 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ 6874 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ 6875 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ 6876 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ 6877 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ 6878 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ 6879 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ 6880 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ 6881 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ 6882 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ 6883 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ 6884 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ 6885 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 6886 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 6887 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 6888 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 6889 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ 6890 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ 6891 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ 6892 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ 6893 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ 6894 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ 6895 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ 6896 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ 6897 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ 6898 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ 6899 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ 6900 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ 6901 #define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ 6902 #define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ 6903 #define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 6904 #define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 6905 #define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 6906 #define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 6907 #define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ 6908 #define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ 6909 #define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ 6910 #define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ 6911 #define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ 6912 #define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ 6913 #define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ 6914 #define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ 6915 #define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ 6916 #define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ 6917 #define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ 6918 #define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ 6919 #define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 6920 #define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 6921 #define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 6922 #define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 6923 #define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ 6924 #define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ 6925 #define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ 6926 #define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ 6927 #define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ 6928 #define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ 6929 #define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ 6930 #define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ 6931 #define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ 6932 #define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ 6933 #define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ 6934 #define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ 6935 #define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ 6936 #define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ 6937 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 6938 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 6939 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 6940 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 6941 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 6942 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 6943 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 6944 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 6945 #define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ 6946 #define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ 6947 #define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 6948 #define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 6949 #define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 6950 #define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 6951 #define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ 6952 #define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ 6953 #define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ 6954 #define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ 6955 #define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 6956 #define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 6957 #define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 6958 #define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 6959 #define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ 6960 #define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ 6961 #define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ 6962 #define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ 6963 #define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ 6964 #define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ 6965 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 6966 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 6967 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 6968 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 6969 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ 6970 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ 6971 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ 6972 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ 6973 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ 6974 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ 6975 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ 6976 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ 6977 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ 6978 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ 6979 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ 6980 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ 6981 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 6982 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 6983 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 6984 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 6985 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ 6986 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ 6987 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ 6988 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ 6989 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ 6990 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ 6991 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ 6992 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ 6993 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ 6994 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ 6995 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ 6996 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ 6997 6998 /* Bit fields for CMU LFBPRESC0 */ 6999 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ 7000 #define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ 7001 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ 7002 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ 7003 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ 7004 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ 7005 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ 7006 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ 7007 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ 7008 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ 7009 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ 7010 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ 7011 #define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ 7012 #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ 7013 #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ 7014 #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ 7015 #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ 7016 #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ 7017 #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ 7018 #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ 7019 #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ 7020 #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ 7021 #define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ 7022 #define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ 7023 #define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ 7024 #define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ 7025 #define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ 7026 #define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ 7027 #define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ 7028 #define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ 7029 #define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ 7030 #define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ 7031 #define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ 7032 #define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ 7033 #define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ 7034 #define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ 7035 7036 /* Bit fields for CMU LFEPRESC0 */ 7037 #define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ 7038 #define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ 7039 #define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ 7040 #define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ 7041 #define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ 7042 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ 7043 #define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ 7044 #define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ 7045 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ 7046 #define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ 7047 7048 /* Bit fields for CMU SYNCBUSY */ 7049 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ 7050 #define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ 7051 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ 7052 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ 7053 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ 7054 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 7055 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 7056 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ 7057 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ 7058 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ 7059 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 7060 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 7061 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ 7062 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ 7063 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ 7064 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 7065 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 7066 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ 7067 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ 7068 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ 7069 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 7070 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 7071 #define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ 7072 #define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ 7073 #define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ 7074 #define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 7075 #define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 7076 #define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ 7077 #define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ 7078 #define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ 7079 #define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 7080 #define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 7081 #define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ 7082 #define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ 7083 #define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ 7084 #define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 7085 #define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 7086 #define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ 7087 #define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ 7088 #define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ 7089 #define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 7090 #define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 7091 #define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ 7092 #define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ 7093 #define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ 7094 #define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 7095 #define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 7096 #define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ 7097 #define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ 7098 #define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ 7099 #define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 7100 #define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 7101 #define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ 7102 #define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ 7103 #define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ 7104 #define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 7105 #define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 7106 #define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ 7107 #define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ 7108 #define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ 7109 #define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 7110 #define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 7111 #define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ 7112 #define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ 7113 #define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ 7114 #define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 7115 #define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 7116 #define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ 7117 #define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ 7118 #define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ 7119 #define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 7120 #define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 7121 7122 /* Bit fields for CMU FREEZE */ 7123 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ 7124 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ 7125 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ 7126 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ 7127 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ 7128 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ 7129 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ 7130 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ 7131 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ 7132 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ 7133 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ 7134 7135 /* Bit fields for CMU PCNTCTRL */ 7136 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ 7137 #define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ 7138 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ 7139 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ 7140 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ 7141 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 7142 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 7143 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ 7144 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ 7145 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ 7146 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 7147 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ 7148 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ 7149 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 7150 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ 7151 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ 7152 #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ 7153 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ 7154 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ 7155 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 7156 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 7157 #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ 7158 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ 7159 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ 7160 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 7161 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ 7162 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ 7163 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 7164 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ 7165 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ 7166 #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ 7167 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ 7168 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ 7169 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 7170 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 7171 #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ 7172 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ 7173 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ 7174 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 7175 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ 7176 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ 7177 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 7178 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ 7179 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ 7180 7181 /* Bit fields for CMU ADCCTRL */ 7182 #define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ 7183 #define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ 7184 #define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ 7185 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ 7186 #define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 7187 #define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ 7188 #define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 7189 #define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ 7190 #define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ 7191 #define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ 7192 #define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 7193 #define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ 7194 #define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ 7195 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ 7196 #define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ 7197 #define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 7198 #define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ 7199 #define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ 7200 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ 7201 #define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ 7202 #define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ 7203 #define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ 7204 #define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ 7205 #define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 7206 #define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 7207 #define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ 7208 #define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ 7209 #define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 7210 #define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ 7211 #define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 7212 #define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ 7213 #define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ 7214 #define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ 7215 #define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 7216 #define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ 7217 #define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ 7218 #define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ 7219 #define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ 7220 #define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 7221 #define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ 7222 #define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ 7223 #define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ 7224 #define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ 7225 #define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ 7226 #define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ 7227 #define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ 7228 #define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 7229 #define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 7230 7231 /* Bit fields for CMU ROUTEPEN */ 7232 #define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ 7233 #define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ 7234 #define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ 7235 #define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ 7236 #define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ 7237 #define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ 7238 #define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ 7239 #define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ 7240 #define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ 7241 #define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ 7242 #define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ 7243 #define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ 7244 #define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ 7245 #define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ 7246 #define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ 7247 #define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ 7248 #define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ 7249 #define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ 7250 #define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ 7251 #define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ 7252 #define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ 7253 #define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ 7254 7255 /* Bit fields for CMU ROUTELOC0 */ 7256 #define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ 7257 #define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ 7258 #define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ 7259 #define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ 7260 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ 7261 #define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ 7262 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ 7263 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ 7264 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ 7265 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ 7266 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ 7267 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ 7268 #define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ 7269 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ 7270 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ 7271 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ 7272 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ 7273 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ 7274 #define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ 7275 #define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ 7276 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ 7277 #define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ 7278 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ 7279 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ 7280 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ 7281 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ 7282 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ 7283 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ 7284 #define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ 7285 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ 7286 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ 7287 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ 7288 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ 7289 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ 7290 #define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ 7291 #define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ 7292 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ 7293 #define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ 7294 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ 7295 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ 7296 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ 7297 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ 7298 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ 7299 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ 7300 #define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ 7301 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ 7302 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ 7303 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ 7304 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ 7305 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ 7306 7307 /* Bit fields for CMU ROUTELOC1 */ 7308 #define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ 7309 #define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ 7310 #define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ 7311 #define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ 7312 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ 7313 #define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ 7314 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ 7315 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ 7316 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ 7317 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ 7318 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ 7319 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ 7320 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ 7321 #define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ 7322 #define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ 7323 #define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ 7324 #define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ 7325 #define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ 7326 #define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ 7327 #define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ 7328 #define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ 7329 #define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ 7330 7331 /* Bit fields for CMU LOCK */ 7332 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ 7333 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ 7334 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ 7335 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ 7336 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ 7337 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ 7338 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ 7339 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ 7340 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ 7341 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ 7342 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ 7343 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ 7344 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ 7345 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ 7346 7347 /* Bit fields for CMU HFRCOSS */ 7348 #define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ 7349 #define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ 7350 #define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ 7351 #define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ 7352 #define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ 7353 #define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ 7354 #define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ 7355 #define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ 7356 #define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ 7357 #define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ 7358 7359 /** @} */ 7360 /** @} End of group EFM32GG11B520F2048GQ100_CMU */ 7361 7362 /***************************************************************************//** 7363 * @addtogroup EFM32GG11B520F2048GQ100_PRS 7364 * @{ 7365 * @defgroup EFM32GG11B520F2048GQ100_PRS_BitFields PRS Bit Fields 7366 * @{ 7367 ******************************************************************************/ 7368 7369 /* Bit fields for PRS SWPULSE */ 7370 #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ 7371 #define _PRS_SWPULSE_MASK 0x00FFFFFFUL /**< Mask for PRS_SWPULSE */ 7372 #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ 7373 #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ 7374 #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ 7375 #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7376 #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7377 #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ 7378 #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ 7379 #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ 7380 #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7381 #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7382 #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ 7383 #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ 7384 #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ 7385 #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7386 #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7387 #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ 7388 #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ 7389 #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ 7390 #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7391 #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7392 #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ 7393 #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ 7394 #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ 7395 #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7396 #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7397 #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ 7398 #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ 7399 #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ 7400 #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7401 #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7402 #define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ 7403 #define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ 7404 #define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ 7405 #define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7406 #define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7407 #define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ 7408 #define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ 7409 #define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ 7410 #define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7411 #define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7412 #define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ 7413 #define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ 7414 #define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ 7415 #define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7416 #define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7417 #define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ 7418 #define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ 7419 #define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ 7420 #define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7421 #define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7422 #define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ 7423 #define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ 7424 #define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ 7425 #define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7426 #define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7427 #define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ 7428 #define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ 7429 #define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ 7430 #define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7431 #define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7432 #define PRS_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel 12 Pulse Generation */ 7433 #define _PRS_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ 7434 #define _PRS_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ 7435 #define _PRS_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7436 #define PRS_SWPULSE_CH12PULSE_DEFAULT (_PRS_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7437 #define PRS_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel 13 Pulse Generation */ 7438 #define _PRS_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ 7439 #define _PRS_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ 7440 #define _PRS_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7441 #define PRS_SWPULSE_CH13PULSE_DEFAULT (_PRS_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7442 #define PRS_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel 14 Pulse Generation */ 7443 #define _PRS_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ 7444 #define _PRS_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ 7445 #define _PRS_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7446 #define PRS_SWPULSE_CH14PULSE_DEFAULT (_PRS_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7447 #define PRS_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel 15 Pulse Generation */ 7448 #define _PRS_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ 7449 #define _PRS_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ 7450 #define _PRS_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7451 #define PRS_SWPULSE_CH15PULSE_DEFAULT (_PRS_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7452 #define PRS_SWPULSE_CH16PULSE (0x1UL << 16) /**< Channel 16 Pulse Generation */ 7453 #define _PRS_SWPULSE_CH16PULSE_SHIFT 16 /**< Shift value for PRS_CH16PULSE */ 7454 #define _PRS_SWPULSE_CH16PULSE_MASK 0x10000UL /**< Bit mask for PRS_CH16PULSE */ 7455 #define _PRS_SWPULSE_CH16PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7456 #define PRS_SWPULSE_CH16PULSE_DEFAULT (_PRS_SWPULSE_CH16PULSE_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7457 #define PRS_SWPULSE_CH17PULSE (0x1UL << 17) /**< Channel 17 Pulse Generation */ 7458 #define _PRS_SWPULSE_CH17PULSE_SHIFT 17 /**< Shift value for PRS_CH17PULSE */ 7459 #define _PRS_SWPULSE_CH17PULSE_MASK 0x20000UL /**< Bit mask for PRS_CH17PULSE */ 7460 #define _PRS_SWPULSE_CH17PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7461 #define PRS_SWPULSE_CH17PULSE_DEFAULT (_PRS_SWPULSE_CH17PULSE_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7462 #define PRS_SWPULSE_CH18PULSE (0x1UL << 18) /**< Channel 18 Pulse Generation */ 7463 #define _PRS_SWPULSE_CH18PULSE_SHIFT 18 /**< Shift value for PRS_CH18PULSE */ 7464 #define _PRS_SWPULSE_CH18PULSE_MASK 0x40000UL /**< Bit mask for PRS_CH18PULSE */ 7465 #define _PRS_SWPULSE_CH18PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7466 #define PRS_SWPULSE_CH18PULSE_DEFAULT (_PRS_SWPULSE_CH18PULSE_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7467 #define PRS_SWPULSE_CH19PULSE (0x1UL << 19) /**< Channel 19 Pulse Generation */ 7468 #define _PRS_SWPULSE_CH19PULSE_SHIFT 19 /**< Shift value for PRS_CH19PULSE */ 7469 #define _PRS_SWPULSE_CH19PULSE_MASK 0x80000UL /**< Bit mask for PRS_CH19PULSE */ 7470 #define _PRS_SWPULSE_CH19PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7471 #define PRS_SWPULSE_CH19PULSE_DEFAULT (_PRS_SWPULSE_CH19PULSE_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7472 #define PRS_SWPULSE_CH20PULSE (0x1UL << 20) /**< Channel 20 Pulse Generation */ 7473 #define _PRS_SWPULSE_CH20PULSE_SHIFT 20 /**< Shift value for PRS_CH20PULSE */ 7474 #define _PRS_SWPULSE_CH20PULSE_MASK 0x100000UL /**< Bit mask for PRS_CH20PULSE */ 7475 #define _PRS_SWPULSE_CH20PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7476 #define PRS_SWPULSE_CH20PULSE_DEFAULT (_PRS_SWPULSE_CH20PULSE_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7477 #define PRS_SWPULSE_CH21PULSE (0x1UL << 21) /**< Channel 21 Pulse Generation */ 7478 #define _PRS_SWPULSE_CH21PULSE_SHIFT 21 /**< Shift value for PRS_CH21PULSE */ 7479 #define _PRS_SWPULSE_CH21PULSE_MASK 0x200000UL /**< Bit mask for PRS_CH21PULSE */ 7480 #define _PRS_SWPULSE_CH21PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7481 #define PRS_SWPULSE_CH21PULSE_DEFAULT (_PRS_SWPULSE_CH21PULSE_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7482 #define PRS_SWPULSE_CH22PULSE (0x1UL << 22) /**< Channel 22 Pulse Generation */ 7483 #define _PRS_SWPULSE_CH22PULSE_SHIFT 22 /**< Shift value for PRS_CH22PULSE */ 7484 #define _PRS_SWPULSE_CH22PULSE_MASK 0x400000UL /**< Bit mask for PRS_CH22PULSE */ 7485 #define _PRS_SWPULSE_CH22PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7486 #define PRS_SWPULSE_CH22PULSE_DEFAULT (_PRS_SWPULSE_CH22PULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7487 #define PRS_SWPULSE_CH23PULSE (0x1UL << 23) /**< Channel 23 Pulse Generation */ 7488 #define _PRS_SWPULSE_CH23PULSE_SHIFT 23 /**< Shift value for PRS_CH23PULSE */ 7489 #define _PRS_SWPULSE_CH23PULSE_MASK 0x800000UL /**< Bit mask for PRS_CH23PULSE */ 7490 #define _PRS_SWPULSE_CH23PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 7491 #define PRS_SWPULSE_CH23PULSE_DEFAULT (_PRS_SWPULSE_CH23PULSE_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 7492 7493 /* Bit fields for PRS SWLEVEL */ 7494 #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ 7495 #define _PRS_SWLEVEL_MASK 0x00FFFFFFUL /**< Mask for PRS_SWLEVEL */ 7496 #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ 7497 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ 7498 #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ 7499 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7500 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7501 #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ 7502 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ 7503 #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ 7504 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7505 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7506 #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ 7507 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ 7508 #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ 7509 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7510 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7511 #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ 7512 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ 7513 #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ 7514 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7515 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7516 #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ 7517 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ 7518 #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ 7519 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7520 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7521 #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ 7522 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ 7523 #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ 7524 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7525 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7526 #define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ 7527 #define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ 7528 #define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ 7529 #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7530 #define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7531 #define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ 7532 #define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ 7533 #define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ 7534 #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7535 #define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7536 #define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ 7537 #define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ 7538 #define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ 7539 #define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7540 #define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7541 #define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ 7542 #define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ 7543 #define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ 7544 #define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7545 #define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7546 #define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ 7547 #define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ 7548 #define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ 7549 #define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7550 #define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7551 #define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ 7552 #define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ 7553 #define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ 7554 #define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7555 #define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7556 #define PRS_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel 12 Software Level */ 7557 #define _PRS_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ 7558 #define _PRS_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ 7559 #define _PRS_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7560 #define PRS_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7561 #define PRS_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel 13 Software Level */ 7562 #define _PRS_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ 7563 #define _PRS_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ 7564 #define _PRS_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7565 #define PRS_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7566 #define PRS_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel 14 Software Level */ 7567 #define _PRS_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ 7568 #define _PRS_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ 7569 #define _PRS_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7570 #define PRS_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7571 #define PRS_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel 15 Software Level */ 7572 #define _PRS_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ 7573 #define _PRS_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ 7574 #define _PRS_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7575 #define PRS_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7576 #define PRS_SWLEVEL_CH16LEVEL (0x1UL << 16) /**< Channel 16 Software Level */ 7577 #define _PRS_SWLEVEL_CH16LEVEL_SHIFT 16 /**< Shift value for PRS_CH16LEVEL */ 7578 #define _PRS_SWLEVEL_CH16LEVEL_MASK 0x10000UL /**< Bit mask for PRS_CH16LEVEL */ 7579 #define _PRS_SWLEVEL_CH16LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7580 #define PRS_SWLEVEL_CH16LEVEL_DEFAULT (_PRS_SWLEVEL_CH16LEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7581 #define PRS_SWLEVEL_CH17LEVEL (0x1UL << 17) /**< Channel 17 Software Level */ 7582 #define _PRS_SWLEVEL_CH17LEVEL_SHIFT 17 /**< Shift value for PRS_CH17LEVEL */ 7583 #define _PRS_SWLEVEL_CH17LEVEL_MASK 0x20000UL /**< Bit mask for PRS_CH17LEVEL */ 7584 #define _PRS_SWLEVEL_CH17LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7585 #define PRS_SWLEVEL_CH17LEVEL_DEFAULT (_PRS_SWLEVEL_CH17LEVEL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7586 #define PRS_SWLEVEL_CH18LEVEL (0x1UL << 18) /**< Channel 18 Software Level */ 7587 #define _PRS_SWLEVEL_CH18LEVEL_SHIFT 18 /**< Shift value for PRS_CH18LEVEL */ 7588 #define _PRS_SWLEVEL_CH18LEVEL_MASK 0x40000UL /**< Bit mask for PRS_CH18LEVEL */ 7589 #define _PRS_SWLEVEL_CH18LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7590 #define PRS_SWLEVEL_CH18LEVEL_DEFAULT (_PRS_SWLEVEL_CH18LEVEL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7591 #define PRS_SWLEVEL_CH19LEVEL (0x1UL << 19) /**< Channel 19 Software Level */ 7592 #define _PRS_SWLEVEL_CH19LEVEL_SHIFT 19 /**< Shift value for PRS_CH19LEVEL */ 7593 #define _PRS_SWLEVEL_CH19LEVEL_MASK 0x80000UL /**< Bit mask for PRS_CH19LEVEL */ 7594 #define _PRS_SWLEVEL_CH19LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7595 #define PRS_SWLEVEL_CH19LEVEL_DEFAULT (_PRS_SWLEVEL_CH19LEVEL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7596 #define PRS_SWLEVEL_CH20LEVEL (0x1UL << 20) /**< Channel 20 Software Level */ 7597 #define _PRS_SWLEVEL_CH20LEVEL_SHIFT 20 /**< Shift value for PRS_CH20LEVEL */ 7598 #define _PRS_SWLEVEL_CH20LEVEL_MASK 0x100000UL /**< Bit mask for PRS_CH20LEVEL */ 7599 #define _PRS_SWLEVEL_CH20LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7600 #define PRS_SWLEVEL_CH20LEVEL_DEFAULT (_PRS_SWLEVEL_CH20LEVEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7601 #define PRS_SWLEVEL_CH21LEVEL (0x1UL << 21) /**< Channel 21 Software Level */ 7602 #define _PRS_SWLEVEL_CH21LEVEL_SHIFT 21 /**< Shift value for PRS_CH21LEVEL */ 7603 #define _PRS_SWLEVEL_CH21LEVEL_MASK 0x200000UL /**< Bit mask for PRS_CH21LEVEL */ 7604 #define _PRS_SWLEVEL_CH21LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7605 #define PRS_SWLEVEL_CH21LEVEL_DEFAULT (_PRS_SWLEVEL_CH21LEVEL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7606 #define PRS_SWLEVEL_CH22LEVEL (0x1UL << 22) /**< Channel 22 Software Level */ 7607 #define _PRS_SWLEVEL_CH22LEVEL_SHIFT 22 /**< Shift value for PRS_CH22LEVEL */ 7608 #define _PRS_SWLEVEL_CH22LEVEL_MASK 0x400000UL /**< Bit mask for PRS_CH22LEVEL */ 7609 #define _PRS_SWLEVEL_CH22LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7610 #define PRS_SWLEVEL_CH22LEVEL_DEFAULT (_PRS_SWLEVEL_CH22LEVEL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7611 #define PRS_SWLEVEL_CH23LEVEL (0x1UL << 23) /**< Channel 23 Software Level */ 7612 #define _PRS_SWLEVEL_CH23LEVEL_SHIFT 23 /**< Shift value for PRS_CH23LEVEL */ 7613 #define _PRS_SWLEVEL_CH23LEVEL_MASK 0x800000UL /**< Bit mask for PRS_CH23LEVEL */ 7614 #define _PRS_SWLEVEL_CH23LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 7615 #define PRS_SWLEVEL_CH23LEVEL_DEFAULT (_PRS_SWLEVEL_CH23LEVEL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 7616 7617 /* Bit fields for PRS ROUTEPEN */ 7618 #define _PRS_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTEPEN */ 7619 #define _PRS_ROUTEPEN_MASK 0x00FFFFFFUL /**< Mask for PRS_ROUTEPEN */ 7620 #define PRS_ROUTEPEN_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ 7621 #define _PRS_ROUTEPEN_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ 7622 #define _PRS_ROUTEPEN_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ 7623 #define _PRS_ROUTEPEN_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7624 #define PRS_ROUTEPEN_CH0PEN_DEFAULT (_PRS_ROUTEPEN_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7625 #define PRS_ROUTEPEN_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ 7626 #define _PRS_ROUTEPEN_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ 7627 #define _PRS_ROUTEPEN_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ 7628 #define _PRS_ROUTEPEN_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7629 #define PRS_ROUTEPEN_CH1PEN_DEFAULT (_PRS_ROUTEPEN_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7630 #define PRS_ROUTEPEN_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ 7631 #define _PRS_ROUTEPEN_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ 7632 #define _PRS_ROUTEPEN_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ 7633 #define _PRS_ROUTEPEN_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7634 #define PRS_ROUTEPEN_CH2PEN_DEFAULT (_PRS_ROUTEPEN_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7635 #define PRS_ROUTEPEN_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ 7636 #define _PRS_ROUTEPEN_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ 7637 #define _PRS_ROUTEPEN_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ 7638 #define _PRS_ROUTEPEN_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7639 #define PRS_ROUTEPEN_CH3PEN_DEFAULT (_PRS_ROUTEPEN_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7640 #define PRS_ROUTEPEN_CH4PEN (0x1UL << 4) /**< CH4 Pin Enable */ 7641 #define _PRS_ROUTEPEN_CH4PEN_SHIFT 4 /**< Shift value for PRS_CH4PEN */ 7642 #define _PRS_ROUTEPEN_CH4PEN_MASK 0x10UL /**< Bit mask for PRS_CH4PEN */ 7643 #define _PRS_ROUTEPEN_CH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7644 #define PRS_ROUTEPEN_CH4PEN_DEFAULT (_PRS_ROUTEPEN_CH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7645 #define PRS_ROUTEPEN_CH5PEN (0x1UL << 5) /**< CH5 Pin Enable */ 7646 #define _PRS_ROUTEPEN_CH5PEN_SHIFT 5 /**< Shift value for PRS_CH5PEN */ 7647 #define _PRS_ROUTEPEN_CH5PEN_MASK 0x20UL /**< Bit mask for PRS_CH5PEN */ 7648 #define _PRS_ROUTEPEN_CH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7649 #define PRS_ROUTEPEN_CH5PEN_DEFAULT (_PRS_ROUTEPEN_CH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7650 #define PRS_ROUTEPEN_CH6PEN (0x1UL << 6) /**< CH6 Pin Enable */ 7651 #define _PRS_ROUTEPEN_CH6PEN_SHIFT 6 /**< Shift value for PRS_CH6PEN */ 7652 #define _PRS_ROUTEPEN_CH6PEN_MASK 0x40UL /**< Bit mask for PRS_CH6PEN */ 7653 #define _PRS_ROUTEPEN_CH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7654 #define PRS_ROUTEPEN_CH6PEN_DEFAULT (_PRS_ROUTEPEN_CH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7655 #define PRS_ROUTEPEN_CH7PEN (0x1UL << 7) /**< CH7 Pin Enable */ 7656 #define _PRS_ROUTEPEN_CH7PEN_SHIFT 7 /**< Shift value for PRS_CH7PEN */ 7657 #define _PRS_ROUTEPEN_CH7PEN_MASK 0x80UL /**< Bit mask for PRS_CH7PEN */ 7658 #define _PRS_ROUTEPEN_CH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7659 #define PRS_ROUTEPEN_CH7PEN_DEFAULT (_PRS_ROUTEPEN_CH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7660 #define PRS_ROUTEPEN_CH8PEN (0x1UL << 8) /**< CH8 Pin Enable */ 7661 #define _PRS_ROUTEPEN_CH8PEN_SHIFT 8 /**< Shift value for PRS_CH8PEN */ 7662 #define _PRS_ROUTEPEN_CH8PEN_MASK 0x100UL /**< Bit mask for PRS_CH8PEN */ 7663 #define _PRS_ROUTEPEN_CH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7664 #define PRS_ROUTEPEN_CH8PEN_DEFAULT (_PRS_ROUTEPEN_CH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7665 #define PRS_ROUTEPEN_CH9PEN (0x1UL << 9) /**< CH9 Pin Enable */ 7666 #define _PRS_ROUTEPEN_CH9PEN_SHIFT 9 /**< Shift value for PRS_CH9PEN */ 7667 #define _PRS_ROUTEPEN_CH9PEN_MASK 0x200UL /**< Bit mask for PRS_CH9PEN */ 7668 #define _PRS_ROUTEPEN_CH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7669 #define PRS_ROUTEPEN_CH9PEN_DEFAULT (_PRS_ROUTEPEN_CH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7670 #define PRS_ROUTEPEN_CH10PEN (0x1UL << 10) /**< CH10 Pin Enable */ 7671 #define _PRS_ROUTEPEN_CH10PEN_SHIFT 10 /**< Shift value for PRS_CH10PEN */ 7672 #define _PRS_ROUTEPEN_CH10PEN_MASK 0x400UL /**< Bit mask for PRS_CH10PEN */ 7673 #define _PRS_ROUTEPEN_CH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7674 #define PRS_ROUTEPEN_CH10PEN_DEFAULT (_PRS_ROUTEPEN_CH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7675 #define PRS_ROUTEPEN_CH11PEN (0x1UL << 11) /**< CH11 Pin Enable */ 7676 #define _PRS_ROUTEPEN_CH11PEN_SHIFT 11 /**< Shift value for PRS_CH11PEN */ 7677 #define _PRS_ROUTEPEN_CH11PEN_MASK 0x800UL /**< Bit mask for PRS_CH11PEN */ 7678 #define _PRS_ROUTEPEN_CH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7679 #define PRS_ROUTEPEN_CH11PEN_DEFAULT (_PRS_ROUTEPEN_CH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7680 #define PRS_ROUTEPEN_CH12PEN (0x1UL << 12) /**< CH12 Pin Enable */ 7681 #define _PRS_ROUTEPEN_CH12PEN_SHIFT 12 /**< Shift value for PRS_CH12PEN */ 7682 #define _PRS_ROUTEPEN_CH12PEN_MASK 0x1000UL /**< Bit mask for PRS_CH12PEN */ 7683 #define _PRS_ROUTEPEN_CH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7684 #define PRS_ROUTEPEN_CH12PEN_DEFAULT (_PRS_ROUTEPEN_CH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7685 #define PRS_ROUTEPEN_CH13PEN (0x1UL << 13) /**< CH13 Pin Enable */ 7686 #define _PRS_ROUTEPEN_CH13PEN_SHIFT 13 /**< Shift value for PRS_CH13PEN */ 7687 #define _PRS_ROUTEPEN_CH13PEN_MASK 0x2000UL /**< Bit mask for PRS_CH13PEN */ 7688 #define _PRS_ROUTEPEN_CH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7689 #define PRS_ROUTEPEN_CH13PEN_DEFAULT (_PRS_ROUTEPEN_CH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7690 #define PRS_ROUTEPEN_CH14PEN (0x1UL << 14) /**< CH14 Pin Enable */ 7691 #define _PRS_ROUTEPEN_CH14PEN_SHIFT 14 /**< Shift value for PRS_CH14PEN */ 7692 #define _PRS_ROUTEPEN_CH14PEN_MASK 0x4000UL /**< Bit mask for PRS_CH14PEN */ 7693 #define _PRS_ROUTEPEN_CH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7694 #define PRS_ROUTEPEN_CH14PEN_DEFAULT (_PRS_ROUTEPEN_CH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7695 #define PRS_ROUTEPEN_CH15PEN (0x1UL << 15) /**< CH15 Pin Enable */ 7696 #define _PRS_ROUTEPEN_CH15PEN_SHIFT 15 /**< Shift value for PRS_CH15PEN */ 7697 #define _PRS_ROUTEPEN_CH15PEN_MASK 0x8000UL /**< Bit mask for PRS_CH15PEN */ 7698 #define _PRS_ROUTEPEN_CH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7699 #define PRS_ROUTEPEN_CH15PEN_DEFAULT (_PRS_ROUTEPEN_CH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7700 #define PRS_ROUTEPEN_CH16PEN (0x1UL << 16) /**< CH16 Pin Enable */ 7701 #define _PRS_ROUTEPEN_CH16PEN_SHIFT 16 /**< Shift value for PRS_CH16PEN */ 7702 #define _PRS_ROUTEPEN_CH16PEN_MASK 0x10000UL /**< Bit mask for PRS_CH16PEN */ 7703 #define _PRS_ROUTEPEN_CH16PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7704 #define PRS_ROUTEPEN_CH16PEN_DEFAULT (_PRS_ROUTEPEN_CH16PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7705 #define PRS_ROUTEPEN_CH17PEN (0x1UL << 17) /**< CH17 Pin Enable */ 7706 #define _PRS_ROUTEPEN_CH17PEN_SHIFT 17 /**< Shift value for PRS_CH17PEN */ 7707 #define _PRS_ROUTEPEN_CH17PEN_MASK 0x20000UL /**< Bit mask for PRS_CH17PEN */ 7708 #define _PRS_ROUTEPEN_CH17PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7709 #define PRS_ROUTEPEN_CH17PEN_DEFAULT (_PRS_ROUTEPEN_CH17PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7710 #define PRS_ROUTEPEN_CH18PEN (0x1UL << 18) /**< CH18 Pin Enable */ 7711 #define _PRS_ROUTEPEN_CH18PEN_SHIFT 18 /**< Shift value for PRS_CH18PEN */ 7712 #define _PRS_ROUTEPEN_CH18PEN_MASK 0x40000UL /**< Bit mask for PRS_CH18PEN */ 7713 #define _PRS_ROUTEPEN_CH18PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7714 #define PRS_ROUTEPEN_CH18PEN_DEFAULT (_PRS_ROUTEPEN_CH18PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7715 #define PRS_ROUTEPEN_CH19PEN (0x1UL << 19) /**< CH19 Pin Enable */ 7716 #define _PRS_ROUTEPEN_CH19PEN_SHIFT 19 /**< Shift value for PRS_CH19PEN */ 7717 #define _PRS_ROUTEPEN_CH19PEN_MASK 0x80000UL /**< Bit mask for PRS_CH19PEN */ 7718 #define _PRS_ROUTEPEN_CH19PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7719 #define PRS_ROUTEPEN_CH19PEN_DEFAULT (_PRS_ROUTEPEN_CH19PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7720 #define PRS_ROUTEPEN_CH20PEN (0x1UL << 20) /**< CH20 Pin Enable */ 7721 #define _PRS_ROUTEPEN_CH20PEN_SHIFT 20 /**< Shift value for PRS_CH20PEN */ 7722 #define _PRS_ROUTEPEN_CH20PEN_MASK 0x100000UL /**< Bit mask for PRS_CH20PEN */ 7723 #define _PRS_ROUTEPEN_CH20PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7724 #define PRS_ROUTEPEN_CH20PEN_DEFAULT (_PRS_ROUTEPEN_CH20PEN_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7725 #define PRS_ROUTEPEN_CH21PEN (0x1UL << 21) /**< CH21 Pin Enable */ 7726 #define _PRS_ROUTEPEN_CH21PEN_SHIFT 21 /**< Shift value for PRS_CH21PEN */ 7727 #define _PRS_ROUTEPEN_CH21PEN_MASK 0x200000UL /**< Bit mask for PRS_CH21PEN */ 7728 #define _PRS_ROUTEPEN_CH21PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7729 #define PRS_ROUTEPEN_CH21PEN_DEFAULT (_PRS_ROUTEPEN_CH21PEN_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7730 #define PRS_ROUTEPEN_CH22PEN (0x1UL << 22) /**< CH22 Pin Enable */ 7731 #define _PRS_ROUTEPEN_CH22PEN_SHIFT 22 /**< Shift value for PRS_CH22PEN */ 7732 #define _PRS_ROUTEPEN_CH22PEN_MASK 0x400000UL /**< Bit mask for PRS_CH22PEN */ 7733 #define _PRS_ROUTEPEN_CH22PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7734 #define PRS_ROUTEPEN_CH22PEN_DEFAULT (_PRS_ROUTEPEN_CH22PEN_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7735 #define PRS_ROUTEPEN_CH23PEN (0x1UL << 23) /**< CH23 Pin Enable */ 7736 #define _PRS_ROUTEPEN_CH23PEN_SHIFT 23 /**< Shift value for PRS_CH23PEN */ 7737 #define _PRS_ROUTEPEN_CH23PEN_MASK 0x800000UL /**< Bit mask for PRS_CH23PEN */ 7738 #define _PRS_ROUTEPEN_CH23PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTEPEN */ 7739 #define PRS_ROUTEPEN_CH23PEN_DEFAULT (_PRS_ROUTEPEN_CH23PEN_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_ROUTEPEN */ 7740 7741 /* Bit fields for PRS ROUTELOC0 */ 7742 #define _PRS_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC0 */ 7743 #define _PRS_ROUTELOC0_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC0 */ 7744 #define _PRS_ROUTELOC0_CH0LOC_SHIFT 0 /**< Shift value for PRS_CH0LOC */ 7745 #define _PRS_ROUTELOC0_CH0LOC_MASK 0x3UL /**< Bit mask for PRS_CH0LOC */ 7746 #define _PRS_ROUTELOC0_CH0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ 7747 #define _PRS_ROUTELOC0_CH0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ 7748 #define _PRS_ROUTELOC0_CH0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ 7749 #define _PRS_ROUTELOC0_CH0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ 7750 #define _PRS_ROUTELOC0_CH0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ 7751 #define PRS_ROUTELOC0_CH0LOC_LOC0 (_PRS_ROUTELOC0_CH0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ 7752 #define PRS_ROUTELOC0_CH0LOC_DEFAULT (_PRS_ROUTELOC0_CH0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ 7753 #define PRS_ROUTELOC0_CH0LOC_LOC1 (_PRS_ROUTELOC0_CH0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ 7754 #define PRS_ROUTELOC0_CH0LOC_LOC2 (_PRS_ROUTELOC0_CH0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ 7755 #define PRS_ROUTELOC0_CH0LOC_LOC3 (_PRS_ROUTELOC0_CH0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ 7756 #define _PRS_ROUTELOC0_CH1LOC_SHIFT 8 /**< Shift value for PRS_CH1LOC */ 7757 #define _PRS_ROUTELOC0_CH1LOC_MASK 0x300UL /**< Bit mask for PRS_CH1LOC */ 7758 #define _PRS_ROUTELOC0_CH1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ 7759 #define _PRS_ROUTELOC0_CH1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ 7760 #define _PRS_ROUTELOC0_CH1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ 7761 #define _PRS_ROUTELOC0_CH1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ 7762 #define _PRS_ROUTELOC0_CH1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ 7763 #define PRS_ROUTELOC0_CH1LOC_LOC0 (_PRS_ROUTELOC0_CH1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ 7764 #define PRS_ROUTELOC0_CH1LOC_DEFAULT (_PRS_ROUTELOC0_CH1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ 7765 #define PRS_ROUTELOC0_CH1LOC_LOC1 (_PRS_ROUTELOC0_CH1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ 7766 #define PRS_ROUTELOC0_CH1LOC_LOC2 (_PRS_ROUTELOC0_CH1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ 7767 #define PRS_ROUTELOC0_CH1LOC_LOC3 (_PRS_ROUTELOC0_CH1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ 7768 #define _PRS_ROUTELOC0_CH2LOC_SHIFT 16 /**< Shift value for PRS_CH2LOC */ 7769 #define _PRS_ROUTELOC0_CH2LOC_MASK 0x30000UL /**< Bit mask for PRS_CH2LOC */ 7770 #define _PRS_ROUTELOC0_CH2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ 7771 #define _PRS_ROUTELOC0_CH2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ 7772 #define _PRS_ROUTELOC0_CH2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ 7773 #define _PRS_ROUTELOC0_CH2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ 7774 #define _PRS_ROUTELOC0_CH2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ 7775 #define PRS_ROUTELOC0_CH2LOC_LOC0 (_PRS_ROUTELOC0_CH2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ 7776 #define PRS_ROUTELOC0_CH2LOC_DEFAULT (_PRS_ROUTELOC0_CH2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ 7777 #define PRS_ROUTELOC0_CH2LOC_LOC1 (_PRS_ROUTELOC0_CH2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ 7778 #define PRS_ROUTELOC0_CH2LOC_LOC2 (_PRS_ROUTELOC0_CH2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ 7779 #define PRS_ROUTELOC0_CH2LOC_LOC3 (_PRS_ROUTELOC0_CH2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ 7780 #define _PRS_ROUTELOC0_CH3LOC_SHIFT 24 /**< Shift value for PRS_CH3LOC */ 7781 #define _PRS_ROUTELOC0_CH3LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH3LOC */ 7782 #define _PRS_ROUTELOC0_CH3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC0 */ 7783 #define _PRS_ROUTELOC0_CH3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC0 */ 7784 #define _PRS_ROUTELOC0_CH3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC0 */ 7785 #define _PRS_ROUTELOC0_CH3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC0 */ 7786 #define _PRS_ROUTELOC0_CH3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTELOC0 */ 7787 #define PRS_ROUTELOC0_CH3LOC_LOC0 (_PRS_ROUTELOC0_CH3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC0 */ 7788 #define PRS_ROUTELOC0_CH3LOC_DEFAULT (_PRS_ROUTELOC0_CH3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC0 */ 7789 #define PRS_ROUTELOC0_CH3LOC_LOC1 (_PRS_ROUTELOC0_CH3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC0 */ 7790 #define PRS_ROUTELOC0_CH3LOC_LOC2 (_PRS_ROUTELOC0_CH3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC0 */ 7791 #define PRS_ROUTELOC0_CH3LOC_LOC3 (_PRS_ROUTELOC0_CH3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PRS_ROUTELOC0 */ 7792 7793 /* Bit fields for PRS ROUTELOC1 */ 7794 #define _PRS_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC1 */ 7795 #define _PRS_ROUTELOC1_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC1 */ 7796 #define _PRS_ROUTELOC1_CH4LOC_SHIFT 0 /**< Shift value for PRS_CH4LOC */ 7797 #define _PRS_ROUTELOC1_CH4LOC_MASK 0x3UL /**< Bit mask for PRS_CH4LOC */ 7798 #define _PRS_ROUTELOC1_CH4LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ 7799 #define _PRS_ROUTELOC1_CH4LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ 7800 #define _PRS_ROUTELOC1_CH4LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ 7801 #define _PRS_ROUTELOC1_CH4LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ 7802 #define PRS_ROUTELOC1_CH4LOC_LOC0 (_PRS_ROUTELOC1_CH4LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ 7803 #define PRS_ROUTELOC1_CH4LOC_DEFAULT (_PRS_ROUTELOC1_CH4LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ 7804 #define PRS_ROUTELOC1_CH4LOC_LOC1 (_PRS_ROUTELOC1_CH4LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ 7805 #define PRS_ROUTELOC1_CH4LOC_LOC2 (_PRS_ROUTELOC1_CH4LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ 7806 #define _PRS_ROUTELOC1_CH5LOC_SHIFT 8 /**< Shift value for PRS_CH5LOC */ 7807 #define _PRS_ROUTELOC1_CH5LOC_MASK 0x300UL /**< Bit mask for PRS_CH5LOC */ 7808 #define _PRS_ROUTELOC1_CH5LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ 7809 #define _PRS_ROUTELOC1_CH5LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ 7810 #define _PRS_ROUTELOC1_CH5LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ 7811 #define _PRS_ROUTELOC1_CH5LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ 7812 #define PRS_ROUTELOC1_CH5LOC_LOC0 (_PRS_ROUTELOC1_CH5LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ 7813 #define PRS_ROUTELOC1_CH5LOC_DEFAULT (_PRS_ROUTELOC1_CH5LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ 7814 #define PRS_ROUTELOC1_CH5LOC_LOC1 (_PRS_ROUTELOC1_CH5LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ 7815 #define PRS_ROUTELOC1_CH5LOC_LOC2 (_PRS_ROUTELOC1_CH5LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ 7816 #define _PRS_ROUTELOC1_CH6LOC_SHIFT 16 /**< Shift value for PRS_CH6LOC */ 7817 #define _PRS_ROUTELOC1_CH6LOC_MASK 0x30000UL /**< Bit mask for PRS_CH6LOC */ 7818 #define _PRS_ROUTELOC1_CH6LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ 7819 #define _PRS_ROUTELOC1_CH6LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ 7820 #define _PRS_ROUTELOC1_CH6LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ 7821 #define _PRS_ROUTELOC1_CH6LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ 7822 #define PRS_ROUTELOC1_CH6LOC_LOC0 (_PRS_ROUTELOC1_CH6LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ 7823 #define PRS_ROUTELOC1_CH6LOC_DEFAULT (_PRS_ROUTELOC1_CH6LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ 7824 #define PRS_ROUTELOC1_CH6LOC_LOC1 (_PRS_ROUTELOC1_CH6LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ 7825 #define PRS_ROUTELOC1_CH6LOC_LOC2 (_PRS_ROUTELOC1_CH6LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ 7826 #define _PRS_ROUTELOC1_CH7LOC_SHIFT 24 /**< Shift value for PRS_CH7LOC */ 7827 #define _PRS_ROUTELOC1_CH7LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH7LOC */ 7828 #define _PRS_ROUTELOC1_CH7LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC1 */ 7829 #define _PRS_ROUTELOC1_CH7LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC1 */ 7830 #define _PRS_ROUTELOC1_CH7LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC1 */ 7831 #define _PRS_ROUTELOC1_CH7LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC1 */ 7832 #define PRS_ROUTELOC1_CH7LOC_LOC0 (_PRS_ROUTELOC1_CH7LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC1 */ 7833 #define PRS_ROUTELOC1_CH7LOC_DEFAULT (_PRS_ROUTELOC1_CH7LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC1 */ 7834 #define PRS_ROUTELOC1_CH7LOC_LOC1 (_PRS_ROUTELOC1_CH7LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC1 */ 7835 #define PRS_ROUTELOC1_CH7LOC_LOC2 (_PRS_ROUTELOC1_CH7LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC1 */ 7836 7837 /* Bit fields for PRS ROUTELOC2 */ 7838 #define _PRS_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC2 */ 7839 #define _PRS_ROUTELOC2_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC2 */ 7840 #define _PRS_ROUTELOC2_CH8LOC_SHIFT 0 /**< Shift value for PRS_CH8LOC */ 7841 #define _PRS_ROUTELOC2_CH8LOC_MASK 0x3UL /**< Bit mask for PRS_CH8LOC */ 7842 #define _PRS_ROUTELOC2_CH8LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ 7843 #define _PRS_ROUTELOC2_CH8LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ 7844 #define _PRS_ROUTELOC2_CH8LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ 7845 #define _PRS_ROUTELOC2_CH8LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ 7846 #define PRS_ROUTELOC2_CH8LOC_LOC0 (_PRS_ROUTELOC2_CH8LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ 7847 #define PRS_ROUTELOC2_CH8LOC_DEFAULT (_PRS_ROUTELOC2_CH8LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ 7848 #define PRS_ROUTELOC2_CH8LOC_LOC1 (_PRS_ROUTELOC2_CH8LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ 7849 #define PRS_ROUTELOC2_CH8LOC_LOC2 (_PRS_ROUTELOC2_CH8LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ 7850 #define _PRS_ROUTELOC2_CH9LOC_SHIFT 8 /**< Shift value for PRS_CH9LOC */ 7851 #define _PRS_ROUTELOC2_CH9LOC_MASK 0x300UL /**< Bit mask for PRS_CH9LOC */ 7852 #define _PRS_ROUTELOC2_CH9LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ 7853 #define _PRS_ROUTELOC2_CH9LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ 7854 #define _PRS_ROUTELOC2_CH9LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ 7855 #define _PRS_ROUTELOC2_CH9LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ 7856 #define PRS_ROUTELOC2_CH9LOC_LOC0 (_PRS_ROUTELOC2_CH9LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ 7857 #define PRS_ROUTELOC2_CH9LOC_DEFAULT (_PRS_ROUTELOC2_CH9LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ 7858 #define PRS_ROUTELOC2_CH9LOC_LOC1 (_PRS_ROUTELOC2_CH9LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ 7859 #define PRS_ROUTELOC2_CH9LOC_LOC2 (_PRS_ROUTELOC2_CH9LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ 7860 #define _PRS_ROUTELOC2_CH10LOC_SHIFT 16 /**< Shift value for PRS_CH10LOC */ 7861 #define _PRS_ROUTELOC2_CH10LOC_MASK 0x30000UL /**< Bit mask for PRS_CH10LOC */ 7862 #define _PRS_ROUTELOC2_CH10LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ 7863 #define _PRS_ROUTELOC2_CH10LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ 7864 #define _PRS_ROUTELOC2_CH10LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ 7865 #define _PRS_ROUTELOC2_CH10LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ 7866 #define PRS_ROUTELOC2_CH10LOC_LOC0 (_PRS_ROUTELOC2_CH10LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ 7867 #define PRS_ROUTELOC2_CH10LOC_DEFAULT (_PRS_ROUTELOC2_CH10LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ 7868 #define PRS_ROUTELOC2_CH10LOC_LOC1 (_PRS_ROUTELOC2_CH10LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ 7869 #define PRS_ROUTELOC2_CH10LOC_LOC2 (_PRS_ROUTELOC2_CH10LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ 7870 #define _PRS_ROUTELOC2_CH11LOC_SHIFT 24 /**< Shift value for PRS_CH11LOC */ 7871 #define _PRS_ROUTELOC2_CH11LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH11LOC */ 7872 #define _PRS_ROUTELOC2_CH11LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC2 */ 7873 #define _PRS_ROUTELOC2_CH11LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC2 */ 7874 #define _PRS_ROUTELOC2_CH11LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC2 */ 7875 #define _PRS_ROUTELOC2_CH11LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC2 */ 7876 #define PRS_ROUTELOC2_CH11LOC_LOC0 (_PRS_ROUTELOC2_CH11LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC2 */ 7877 #define PRS_ROUTELOC2_CH11LOC_DEFAULT (_PRS_ROUTELOC2_CH11LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC2 */ 7878 #define PRS_ROUTELOC2_CH11LOC_LOC1 (_PRS_ROUTELOC2_CH11LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC2 */ 7879 #define PRS_ROUTELOC2_CH11LOC_LOC2 (_PRS_ROUTELOC2_CH11LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC2 */ 7880 7881 /* Bit fields for PRS ROUTELOC3 */ 7882 #define _PRS_ROUTELOC3_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC3 */ 7883 #define _PRS_ROUTELOC3_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC3 */ 7884 #define _PRS_ROUTELOC3_CH12LOC_SHIFT 0 /**< Shift value for PRS_CH12LOC */ 7885 #define _PRS_ROUTELOC3_CH12LOC_MASK 0x3UL /**< Bit mask for PRS_CH12LOC */ 7886 #define _PRS_ROUTELOC3_CH12LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ 7887 #define _PRS_ROUTELOC3_CH12LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ 7888 #define _PRS_ROUTELOC3_CH12LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ 7889 #define _PRS_ROUTELOC3_CH12LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ 7890 #define PRS_ROUTELOC3_CH12LOC_LOC0 (_PRS_ROUTELOC3_CH12LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ 7891 #define PRS_ROUTELOC3_CH12LOC_DEFAULT (_PRS_ROUTELOC3_CH12LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ 7892 #define PRS_ROUTELOC3_CH12LOC_LOC1 (_PRS_ROUTELOC3_CH12LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ 7893 #define PRS_ROUTELOC3_CH12LOC_LOC2 (_PRS_ROUTELOC3_CH12LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ 7894 #define _PRS_ROUTELOC3_CH13LOC_SHIFT 8 /**< Shift value for PRS_CH13LOC */ 7895 #define _PRS_ROUTELOC3_CH13LOC_MASK 0x300UL /**< Bit mask for PRS_CH13LOC */ 7896 #define _PRS_ROUTELOC3_CH13LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ 7897 #define _PRS_ROUTELOC3_CH13LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ 7898 #define _PRS_ROUTELOC3_CH13LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ 7899 #define _PRS_ROUTELOC3_CH13LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ 7900 #define PRS_ROUTELOC3_CH13LOC_LOC0 (_PRS_ROUTELOC3_CH13LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ 7901 #define PRS_ROUTELOC3_CH13LOC_DEFAULT (_PRS_ROUTELOC3_CH13LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ 7902 #define PRS_ROUTELOC3_CH13LOC_LOC1 (_PRS_ROUTELOC3_CH13LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ 7903 #define PRS_ROUTELOC3_CH13LOC_LOC2 (_PRS_ROUTELOC3_CH13LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ 7904 #define _PRS_ROUTELOC3_CH14LOC_SHIFT 16 /**< Shift value for PRS_CH14LOC */ 7905 #define _PRS_ROUTELOC3_CH14LOC_MASK 0x30000UL /**< Bit mask for PRS_CH14LOC */ 7906 #define _PRS_ROUTELOC3_CH14LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ 7907 #define _PRS_ROUTELOC3_CH14LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ 7908 #define _PRS_ROUTELOC3_CH14LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ 7909 #define _PRS_ROUTELOC3_CH14LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ 7910 #define PRS_ROUTELOC3_CH14LOC_LOC0 (_PRS_ROUTELOC3_CH14LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ 7911 #define PRS_ROUTELOC3_CH14LOC_DEFAULT (_PRS_ROUTELOC3_CH14LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ 7912 #define PRS_ROUTELOC3_CH14LOC_LOC1 (_PRS_ROUTELOC3_CH14LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ 7913 #define PRS_ROUTELOC3_CH14LOC_LOC2 (_PRS_ROUTELOC3_CH14LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ 7914 #define _PRS_ROUTELOC3_CH15LOC_SHIFT 24 /**< Shift value for PRS_CH15LOC */ 7915 #define _PRS_ROUTELOC3_CH15LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH15LOC */ 7916 #define _PRS_ROUTELOC3_CH15LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC3 */ 7917 #define _PRS_ROUTELOC3_CH15LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC3 */ 7918 #define _PRS_ROUTELOC3_CH15LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC3 */ 7919 #define _PRS_ROUTELOC3_CH15LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC3 */ 7920 #define PRS_ROUTELOC3_CH15LOC_LOC0 (_PRS_ROUTELOC3_CH15LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC3 */ 7921 #define PRS_ROUTELOC3_CH15LOC_DEFAULT (_PRS_ROUTELOC3_CH15LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC3 */ 7922 #define PRS_ROUTELOC3_CH15LOC_LOC1 (_PRS_ROUTELOC3_CH15LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC3 */ 7923 #define PRS_ROUTELOC3_CH15LOC_LOC2 (_PRS_ROUTELOC3_CH15LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC3 */ 7924 7925 /* Bit fields for PRS ROUTELOC4 */ 7926 #define _PRS_ROUTELOC4_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC4 */ 7927 #define _PRS_ROUTELOC4_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC4 */ 7928 #define _PRS_ROUTELOC4_CH16LOC_SHIFT 0 /**< Shift value for PRS_CH16LOC */ 7929 #define _PRS_ROUTELOC4_CH16LOC_MASK 0x3UL /**< Bit mask for PRS_CH16LOC */ 7930 #define _PRS_ROUTELOC4_CH16LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ 7931 #define _PRS_ROUTELOC4_CH16LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ 7932 #define _PRS_ROUTELOC4_CH16LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ 7933 #define _PRS_ROUTELOC4_CH16LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ 7934 #define PRS_ROUTELOC4_CH16LOC_LOC0 (_PRS_ROUTELOC4_CH16LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ 7935 #define PRS_ROUTELOC4_CH16LOC_DEFAULT (_PRS_ROUTELOC4_CH16LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ 7936 #define PRS_ROUTELOC4_CH16LOC_LOC1 (_PRS_ROUTELOC4_CH16LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ 7937 #define PRS_ROUTELOC4_CH16LOC_LOC2 (_PRS_ROUTELOC4_CH16LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ 7938 #define _PRS_ROUTELOC4_CH17LOC_SHIFT 8 /**< Shift value for PRS_CH17LOC */ 7939 #define _PRS_ROUTELOC4_CH17LOC_MASK 0x300UL /**< Bit mask for PRS_CH17LOC */ 7940 #define _PRS_ROUTELOC4_CH17LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ 7941 #define _PRS_ROUTELOC4_CH17LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ 7942 #define _PRS_ROUTELOC4_CH17LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ 7943 #define _PRS_ROUTELOC4_CH17LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ 7944 #define PRS_ROUTELOC4_CH17LOC_LOC0 (_PRS_ROUTELOC4_CH17LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ 7945 #define PRS_ROUTELOC4_CH17LOC_DEFAULT (_PRS_ROUTELOC4_CH17LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ 7946 #define PRS_ROUTELOC4_CH17LOC_LOC1 (_PRS_ROUTELOC4_CH17LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ 7947 #define PRS_ROUTELOC4_CH17LOC_LOC2 (_PRS_ROUTELOC4_CH17LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ 7948 #define _PRS_ROUTELOC4_CH18LOC_SHIFT 16 /**< Shift value for PRS_CH18LOC */ 7949 #define _PRS_ROUTELOC4_CH18LOC_MASK 0x30000UL /**< Bit mask for PRS_CH18LOC */ 7950 #define _PRS_ROUTELOC4_CH18LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ 7951 #define _PRS_ROUTELOC4_CH18LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ 7952 #define _PRS_ROUTELOC4_CH18LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ 7953 #define _PRS_ROUTELOC4_CH18LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ 7954 #define PRS_ROUTELOC4_CH18LOC_LOC0 (_PRS_ROUTELOC4_CH18LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ 7955 #define PRS_ROUTELOC4_CH18LOC_DEFAULT (_PRS_ROUTELOC4_CH18LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ 7956 #define PRS_ROUTELOC4_CH18LOC_LOC1 (_PRS_ROUTELOC4_CH18LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ 7957 #define PRS_ROUTELOC4_CH18LOC_LOC2 (_PRS_ROUTELOC4_CH18LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ 7958 #define _PRS_ROUTELOC4_CH19LOC_SHIFT 24 /**< Shift value for PRS_CH19LOC */ 7959 #define _PRS_ROUTELOC4_CH19LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH19LOC */ 7960 #define _PRS_ROUTELOC4_CH19LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC4 */ 7961 #define _PRS_ROUTELOC4_CH19LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC4 */ 7962 #define _PRS_ROUTELOC4_CH19LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC4 */ 7963 #define _PRS_ROUTELOC4_CH19LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC4 */ 7964 #define PRS_ROUTELOC4_CH19LOC_LOC0 (_PRS_ROUTELOC4_CH19LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC4 */ 7965 #define PRS_ROUTELOC4_CH19LOC_DEFAULT (_PRS_ROUTELOC4_CH19LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC4 */ 7966 #define PRS_ROUTELOC4_CH19LOC_LOC1 (_PRS_ROUTELOC4_CH19LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC4 */ 7967 #define PRS_ROUTELOC4_CH19LOC_LOC2 (_PRS_ROUTELOC4_CH19LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC4 */ 7968 7969 /* Bit fields for PRS ROUTELOC5 */ 7970 #define _PRS_ROUTELOC5_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTELOC5 */ 7971 #define _PRS_ROUTELOC5_MASK 0x03030303UL /**< Mask for PRS_ROUTELOC5 */ 7972 #define _PRS_ROUTELOC5_CH20LOC_SHIFT 0 /**< Shift value for PRS_CH20LOC */ 7973 #define _PRS_ROUTELOC5_CH20LOC_MASK 0x3UL /**< Bit mask for PRS_CH20LOC */ 7974 #define _PRS_ROUTELOC5_CH20LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ 7975 #define _PRS_ROUTELOC5_CH20LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ 7976 #define _PRS_ROUTELOC5_CH20LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ 7977 #define _PRS_ROUTELOC5_CH20LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ 7978 #define PRS_ROUTELOC5_CH20LOC_LOC0 (_PRS_ROUTELOC5_CH20LOC_LOC0 << 0) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ 7979 #define PRS_ROUTELOC5_CH20LOC_DEFAULT (_PRS_ROUTELOC5_CH20LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ 7980 #define PRS_ROUTELOC5_CH20LOC_LOC1 (_PRS_ROUTELOC5_CH20LOC_LOC1 << 0) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ 7981 #define PRS_ROUTELOC5_CH20LOC_LOC2 (_PRS_ROUTELOC5_CH20LOC_LOC2 << 0) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ 7982 #define _PRS_ROUTELOC5_CH21LOC_SHIFT 8 /**< Shift value for PRS_CH21LOC */ 7983 #define _PRS_ROUTELOC5_CH21LOC_MASK 0x300UL /**< Bit mask for PRS_CH21LOC */ 7984 #define _PRS_ROUTELOC5_CH21LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ 7985 #define _PRS_ROUTELOC5_CH21LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ 7986 #define _PRS_ROUTELOC5_CH21LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ 7987 #define _PRS_ROUTELOC5_CH21LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ 7988 #define PRS_ROUTELOC5_CH21LOC_LOC0 (_PRS_ROUTELOC5_CH21LOC_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ 7989 #define PRS_ROUTELOC5_CH21LOC_DEFAULT (_PRS_ROUTELOC5_CH21LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ 7990 #define PRS_ROUTELOC5_CH21LOC_LOC1 (_PRS_ROUTELOC5_CH21LOC_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ 7991 #define PRS_ROUTELOC5_CH21LOC_LOC2 (_PRS_ROUTELOC5_CH21LOC_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ 7992 #define _PRS_ROUTELOC5_CH22LOC_SHIFT 16 /**< Shift value for PRS_CH22LOC */ 7993 #define _PRS_ROUTELOC5_CH22LOC_MASK 0x30000UL /**< Bit mask for PRS_CH22LOC */ 7994 #define _PRS_ROUTELOC5_CH22LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ 7995 #define _PRS_ROUTELOC5_CH22LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ 7996 #define _PRS_ROUTELOC5_CH22LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ 7997 #define _PRS_ROUTELOC5_CH22LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ 7998 #define PRS_ROUTELOC5_CH22LOC_LOC0 (_PRS_ROUTELOC5_CH22LOC_LOC0 << 16) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ 7999 #define PRS_ROUTELOC5_CH22LOC_DEFAULT (_PRS_ROUTELOC5_CH22LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ 8000 #define PRS_ROUTELOC5_CH22LOC_LOC1 (_PRS_ROUTELOC5_CH22LOC_LOC1 << 16) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ 8001 #define PRS_ROUTELOC5_CH22LOC_LOC2 (_PRS_ROUTELOC5_CH22LOC_LOC2 << 16) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ 8002 #define _PRS_ROUTELOC5_CH23LOC_SHIFT 24 /**< Shift value for PRS_CH23LOC */ 8003 #define _PRS_ROUTELOC5_CH23LOC_MASK 0x3000000UL /**< Bit mask for PRS_CH23LOC */ 8004 #define _PRS_ROUTELOC5_CH23LOC_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTELOC5 */ 8005 #define _PRS_ROUTELOC5_CH23LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTELOC5 */ 8006 #define _PRS_ROUTELOC5_CH23LOC_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTELOC5 */ 8007 #define _PRS_ROUTELOC5_CH23LOC_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTELOC5 */ 8008 #define PRS_ROUTELOC5_CH23LOC_LOC0 (_PRS_ROUTELOC5_CH23LOC_LOC0 << 24) /**< Shifted mode LOC0 for PRS_ROUTELOC5 */ 8009 #define PRS_ROUTELOC5_CH23LOC_DEFAULT (_PRS_ROUTELOC5_CH23LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ROUTELOC5 */ 8010 #define PRS_ROUTELOC5_CH23LOC_LOC1 (_PRS_ROUTELOC5_CH23LOC_LOC1 << 24) /**< Shifted mode LOC1 for PRS_ROUTELOC5 */ 8011 #define PRS_ROUTELOC5_CH23LOC_LOC2 (_PRS_ROUTELOC5_CH23LOC_LOC2 << 24) /**< Shifted mode LOC2 for PRS_ROUTELOC5 */ 8012 8013 /* Bit fields for PRS CTRL */ 8014 #define _PRS_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CTRL */ 8015 #define _PRS_CTRL_MASK 0x0000003FUL /**< Mask for PRS_CTRL */ 8016 #define PRS_CTRL_SEVONPRS (0x1UL << 0) /**< Set Event on PRS */ 8017 #define _PRS_CTRL_SEVONPRS_SHIFT 0 /**< Shift value for PRS_SEVONPRS */ 8018 #define _PRS_CTRL_SEVONPRS_MASK 0x1UL /**< Bit mask for PRS_SEVONPRS */ 8019 #define _PRS_CTRL_SEVONPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ 8020 #define PRS_CTRL_SEVONPRS_DEFAULT (_PRS_CTRL_SEVONPRS_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CTRL */ 8021 #define _PRS_CTRL_SEVONPRSSEL_SHIFT 1 /**< Shift value for PRS_SEVONPRSSEL */ 8022 #define _PRS_CTRL_SEVONPRSSEL_MASK 0x3EUL /**< Bit mask for PRS_SEVONPRSSEL */ 8023 #define _PRS_CTRL_SEVONPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CTRL */ 8024 #define _PRS_CTRL_SEVONPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CTRL */ 8025 #define _PRS_CTRL_SEVONPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CTRL */ 8026 #define _PRS_CTRL_SEVONPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CTRL */ 8027 #define _PRS_CTRL_SEVONPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CTRL */ 8028 #define _PRS_CTRL_SEVONPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CTRL */ 8029 #define _PRS_CTRL_SEVONPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CTRL */ 8030 #define _PRS_CTRL_SEVONPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CTRL */ 8031 #define _PRS_CTRL_SEVONPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CTRL */ 8032 #define _PRS_CTRL_SEVONPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_CTRL */ 8033 #define _PRS_CTRL_SEVONPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_CTRL */ 8034 #define _PRS_CTRL_SEVONPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_CTRL */ 8035 #define _PRS_CTRL_SEVONPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_CTRL */ 8036 #define _PRS_CTRL_SEVONPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_CTRL */ 8037 #define _PRS_CTRL_SEVONPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_CTRL */ 8038 #define _PRS_CTRL_SEVONPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_CTRL */ 8039 #define _PRS_CTRL_SEVONPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_CTRL */ 8040 #define _PRS_CTRL_SEVONPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_CTRL */ 8041 #define _PRS_CTRL_SEVONPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_CTRL */ 8042 #define _PRS_CTRL_SEVONPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_CTRL */ 8043 #define _PRS_CTRL_SEVONPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_CTRL */ 8044 #define _PRS_CTRL_SEVONPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_CTRL */ 8045 #define _PRS_CTRL_SEVONPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_CTRL */ 8046 #define _PRS_CTRL_SEVONPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_CTRL */ 8047 #define _PRS_CTRL_SEVONPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_CTRL */ 8048 #define PRS_CTRL_SEVONPRSSEL_DEFAULT (_PRS_CTRL_SEVONPRSSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_CTRL */ 8049 #define PRS_CTRL_SEVONPRSSEL_PRSCH0 (_PRS_CTRL_SEVONPRSSEL_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_CTRL */ 8050 #define PRS_CTRL_SEVONPRSSEL_PRSCH1 (_PRS_CTRL_SEVONPRSSEL_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_CTRL */ 8051 #define PRS_CTRL_SEVONPRSSEL_PRSCH2 (_PRS_CTRL_SEVONPRSSEL_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_CTRL */ 8052 #define PRS_CTRL_SEVONPRSSEL_PRSCH3 (_PRS_CTRL_SEVONPRSSEL_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_CTRL */ 8053 #define PRS_CTRL_SEVONPRSSEL_PRSCH4 (_PRS_CTRL_SEVONPRSSEL_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_CTRL */ 8054 #define PRS_CTRL_SEVONPRSSEL_PRSCH5 (_PRS_CTRL_SEVONPRSSEL_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_CTRL */ 8055 #define PRS_CTRL_SEVONPRSSEL_PRSCH6 (_PRS_CTRL_SEVONPRSSEL_PRSCH6 << 1) /**< Shifted mode PRSCH6 for PRS_CTRL */ 8056 #define PRS_CTRL_SEVONPRSSEL_PRSCH7 (_PRS_CTRL_SEVONPRSSEL_PRSCH7 << 1) /**< Shifted mode PRSCH7 for PRS_CTRL */ 8057 #define PRS_CTRL_SEVONPRSSEL_PRSCH8 (_PRS_CTRL_SEVONPRSSEL_PRSCH8 << 1) /**< Shifted mode PRSCH8 for PRS_CTRL */ 8058 #define PRS_CTRL_SEVONPRSSEL_PRSCH9 (_PRS_CTRL_SEVONPRSSEL_PRSCH9 << 1) /**< Shifted mode PRSCH9 for PRS_CTRL */ 8059 #define PRS_CTRL_SEVONPRSSEL_PRSCH10 (_PRS_CTRL_SEVONPRSSEL_PRSCH10 << 1) /**< Shifted mode PRSCH10 for PRS_CTRL */ 8060 #define PRS_CTRL_SEVONPRSSEL_PRSCH11 (_PRS_CTRL_SEVONPRSSEL_PRSCH11 << 1) /**< Shifted mode PRSCH11 for PRS_CTRL */ 8061 #define PRS_CTRL_SEVONPRSSEL_PRSCH12 (_PRS_CTRL_SEVONPRSSEL_PRSCH12 << 1) /**< Shifted mode PRSCH12 for PRS_CTRL */ 8062 #define PRS_CTRL_SEVONPRSSEL_PRSCH13 (_PRS_CTRL_SEVONPRSSEL_PRSCH13 << 1) /**< Shifted mode PRSCH13 for PRS_CTRL */ 8063 #define PRS_CTRL_SEVONPRSSEL_PRSCH14 (_PRS_CTRL_SEVONPRSSEL_PRSCH14 << 1) /**< Shifted mode PRSCH14 for PRS_CTRL */ 8064 #define PRS_CTRL_SEVONPRSSEL_PRSCH15 (_PRS_CTRL_SEVONPRSSEL_PRSCH15 << 1) /**< Shifted mode PRSCH15 for PRS_CTRL */ 8065 #define PRS_CTRL_SEVONPRSSEL_PRSCH16 (_PRS_CTRL_SEVONPRSSEL_PRSCH16 << 1) /**< Shifted mode PRSCH16 for PRS_CTRL */ 8066 #define PRS_CTRL_SEVONPRSSEL_PRSCH17 (_PRS_CTRL_SEVONPRSSEL_PRSCH17 << 1) /**< Shifted mode PRSCH17 for PRS_CTRL */ 8067 #define PRS_CTRL_SEVONPRSSEL_PRSCH18 (_PRS_CTRL_SEVONPRSSEL_PRSCH18 << 1) /**< Shifted mode PRSCH18 for PRS_CTRL */ 8068 #define PRS_CTRL_SEVONPRSSEL_PRSCH19 (_PRS_CTRL_SEVONPRSSEL_PRSCH19 << 1) /**< Shifted mode PRSCH19 for PRS_CTRL */ 8069 #define PRS_CTRL_SEVONPRSSEL_PRSCH20 (_PRS_CTRL_SEVONPRSSEL_PRSCH20 << 1) /**< Shifted mode PRSCH20 for PRS_CTRL */ 8070 #define PRS_CTRL_SEVONPRSSEL_PRSCH21 (_PRS_CTRL_SEVONPRSSEL_PRSCH21 << 1) /**< Shifted mode PRSCH21 for PRS_CTRL */ 8071 #define PRS_CTRL_SEVONPRSSEL_PRSCH22 (_PRS_CTRL_SEVONPRSSEL_PRSCH22 << 1) /**< Shifted mode PRSCH22 for PRS_CTRL */ 8072 #define PRS_CTRL_SEVONPRSSEL_PRSCH23 (_PRS_CTRL_SEVONPRSSEL_PRSCH23 << 1) /**< Shifted mode PRSCH23 for PRS_CTRL */ 8073 8074 /* Bit fields for PRS DMAREQ0 */ 8075 #define _PRS_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ0 */ 8076 #define _PRS_DMAREQ0_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ0 */ 8077 #define _PRS_DMAREQ0_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ 8078 #define _PRS_DMAREQ0_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ 8079 #define _PRS_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ0 */ 8080 #define _PRS_DMAREQ0_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ0 */ 8081 #define _PRS_DMAREQ0_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ0 */ 8082 #define _PRS_DMAREQ0_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ0 */ 8083 #define _PRS_DMAREQ0_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ0 */ 8084 #define _PRS_DMAREQ0_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ0 */ 8085 #define _PRS_DMAREQ0_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ0 */ 8086 #define _PRS_DMAREQ0_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ0 */ 8087 #define _PRS_DMAREQ0_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ0 */ 8088 #define _PRS_DMAREQ0_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ0 */ 8089 #define _PRS_DMAREQ0_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ0 */ 8090 #define _PRS_DMAREQ0_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ0 */ 8091 #define _PRS_DMAREQ0_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ0 */ 8092 #define _PRS_DMAREQ0_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ0 */ 8093 #define _PRS_DMAREQ0_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ0 */ 8094 #define _PRS_DMAREQ0_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ0 */ 8095 #define _PRS_DMAREQ0_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ0 */ 8096 #define _PRS_DMAREQ0_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ0 */ 8097 #define _PRS_DMAREQ0_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ0 */ 8098 #define _PRS_DMAREQ0_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ0 */ 8099 #define _PRS_DMAREQ0_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ0 */ 8100 #define _PRS_DMAREQ0_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ0 */ 8101 #define _PRS_DMAREQ0_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ0 */ 8102 #define _PRS_DMAREQ0_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ0 */ 8103 #define _PRS_DMAREQ0_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ0 */ 8104 #define PRS_DMAREQ0_PRSSEL_DEFAULT (_PRS_DMAREQ0_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ0 */ 8105 #define PRS_DMAREQ0_PRSSEL_PRSCH0 (_PRS_DMAREQ0_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ0 */ 8106 #define PRS_DMAREQ0_PRSSEL_PRSCH1 (_PRS_DMAREQ0_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ0 */ 8107 #define PRS_DMAREQ0_PRSSEL_PRSCH2 (_PRS_DMAREQ0_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ0 */ 8108 #define PRS_DMAREQ0_PRSSEL_PRSCH3 (_PRS_DMAREQ0_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ0 */ 8109 #define PRS_DMAREQ0_PRSSEL_PRSCH4 (_PRS_DMAREQ0_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ0 */ 8110 #define PRS_DMAREQ0_PRSSEL_PRSCH5 (_PRS_DMAREQ0_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ0 */ 8111 #define PRS_DMAREQ0_PRSSEL_PRSCH6 (_PRS_DMAREQ0_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ0 */ 8112 #define PRS_DMAREQ0_PRSSEL_PRSCH7 (_PRS_DMAREQ0_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ0 */ 8113 #define PRS_DMAREQ0_PRSSEL_PRSCH8 (_PRS_DMAREQ0_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ0 */ 8114 #define PRS_DMAREQ0_PRSSEL_PRSCH9 (_PRS_DMAREQ0_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ0 */ 8115 #define PRS_DMAREQ0_PRSSEL_PRSCH10 (_PRS_DMAREQ0_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ0 */ 8116 #define PRS_DMAREQ0_PRSSEL_PRSCH11 (_PRS_DMAREQ0_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ0 */ 8117 #define PRS_DMAREQ0_PRSSEL_PRSCH12 (_PRS_DMAREQ0_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ0 */ 8118 #define PRS_DMAREQ0_PRSSEL_PRSCH13 (_PRS_DMAREQ0_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ0 */ 8119 #define PRS_DMAREQ0_PRSSEL_PRSCH14 (_PRS_DMAREQ0_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ0 */ 8120 #define PRS_DMAREQ0_PRSSEL_PRSCH15 (_PRS_DMAREQ0_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ0 */ 8121 #define PRS_DMAREQ0_PRSSEL_PRSCH16 (_PRS_DMAREQ0_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ0 */ 8122 #define PRS_DMAREQ0_PRSSEL_PRSCH17 (_PRS_DMAREQ0_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ0 */ 8123 #define PRS_DMAREQ0_PRSSEL_PRSCH18 (_PRS_DMAREQ0_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ0 */ 8124 #define PRS_DMAREQ0_PRSSEL_PRSCH19 (_PRS_DMAREQ0_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ0 */ 8125 #define PRS_DMAREQ0_PRSSEL_PRSCH20 (_PRS_DMAREQ0_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ0 */ 8126 #define PRS_DMAREQ0_PRSSEL_PRSCH21 (_PRS_DMAREQ0_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ0 */ 8127 #define PRS_DMAREQ0_PRSSEL_PRSCH22 (_PRS_DMAREQ0_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ0 */ 8128 #define PRS_DMAREQ0_PRSSEL_PRSCH23 (_PRS_DMAREQ0_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ0 */ 8129 8130 /* Bit fields for PRS DMAREQ1 */ 8131 #define _PRS_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_DMAREQ1 */ 8132 #define _PRS_DMAREQ1_MASK 0x000007C0UL /**< Mask for PRS_DMAREQ1 */ 8133 #define _PRS_DMAREQ1_PRSSEL_SHIFT 6 /**< Shift value for PRS_PRSSEL */ 8134 #define _PRS_DMAREQ1_PRSSEL_MASK 0x7C0UL /**< Bit mask for PRS_PRSSEL */ 8135 #define _PRS_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_DMAREQ1 */ 8136 #define _PRS_DMAREQ1_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_DMAREQ1 */ 8137 #define _PRS_DMAREQ1_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_DMAREQ1 */ 8138 #define _PRS_DMAREQ1_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_DMAREQ1 */ 8139 #define _PRS_DMAREQ1_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_DMAREQ1 */ 8140 #define _PRS_DMAREQ1_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_DMAREQ1 */ 8141 #define _PRS_DMAREQ1_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_DMAREQ1 */ 8142 #define _PRS_DMAREQ1_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_DMAREQ1 */ 8143 #define _PRS_DMAREQ1_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_DMAREQ1 */ 8144 #define _PRS_DMAREQ1_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PRS_DMAREQ1 */ 8145 #define _PRS_DMAREQ1_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PRS_DMAREQ1 */ 8146 #define _PRS_DMAREQ1_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PRS_DMAREQ1 */ 8147 #define _PRS_DMAREQ1_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PRS_DMAREQ1 */ 8148 #define _PRS_DMAREQ1_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PRS_DMAREQ1 */ 8149 #define _PRS_DMAREQ1_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PRS_DMAREQ1 */ 8150 #define _PRS_DMAREQ1_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PRS_DMAREQ1 */ 8151 #define _PRS_DMAREQ1_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PRS_DMAREQ1 */ 8152 #define _PRS_DMAREQ1_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PRS_DMAREQ1 */ 8153 #define _PRS_DMAREQ1_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PRS_DMAREQ1 */ 8154 #define _PRS_DMAREQ1_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PRS_DMAREQ1 */ 8155 #define _PRS_DMAREQ1_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PRS_DMAREQ1 */ 8156 #define _PRS_DMAREQ1_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PRS_DMAREQ1 */ 8157 #define _PRS_DMAREQ1_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PRS_DMAREQ1 */ 8158 #define _PRS_DMAREQ1_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PRS_DMAREQ1 */ 8159 #define _PRS_DMAREQ1_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PRS_DMAREQ1 */ 8160 #define PRS_DMAREQ1_PRSSEL_DEFAULT (_PRS_DMAREQ1_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_DMAREQ1 */ 8161 #define PRS_DMAREQ1_PRSSEL_PRSCH0 (_PRS_DMAREQ1_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PRS_DMAREQ1 */ 8162 #define PRS_DMAREQ1_PRSSEL_PRSCH1 (_PRS_DMAREQ1_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PRS_DMAREQ1 */ 8163 #define PRS_DMAREQ1_PRSSEL_PRSCH2 (_PRS_DMAREQ1_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PRS_DMAREQ1 */ 8164 #define PRS_DMAREQ1_PRSSEL_PRSCH3 (_PRS_DMAREQ1_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PRS_DMAREQ1 */ 8165 #define PRS_DMAREQ1_PRSSEL_PRSCH4 (_PRS_DMAREQ1_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PRS_DMAREQ1 */ 8166 #define PRS_DMAREQ1_PRSSEL_PRSCH5 (_PRS_DMAREQ1_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PRS_DMAREQ1 */ 8167 #define PRS_DMAREQ1_PRSSEL_PRSCH6 (_PRS_DMAREQ1_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PRS_DMAREQ1 */ 8168 #define PRS_DMAREQ1_PRSSEL_PRSCH7 (_PRS_DMAREQ1_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PRS_DMAREQ1 */ 8169 #define PRS_DMAREQ1_PRSSEL_PRSCH8 (_PRS_DMAREQ1_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PRS_DMAREQ1 */ 8170 #define PRS_DMAREQ1_PRSSEL_PRSCH9 (_PRS_DMAREQ1_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PRS_DMAREQ1 */ 8171 #define PRS_DMAREQ1_PRSSEL_PRSCH10 (_PRS_DMAREQ1_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PRS_DMAREQ1 */ 8172 #define PRS_DMAREQ1_PRSSEL_PRSCH11 (_PRS_DMAREQ1_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PRS_DMAREQ1 */ 8173 #define PRS_DMAREQ1_PRSSEL_PRSCH12 (_PRS_DMAREQ1_PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PRS_DMAREQ1 */ 8174 #define PRS_DMAREQ1_PRSSEL_PRSCH13 (_PRS_DMAREQ1_PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PRS_DMAREQ1 */ 8175 #define PRS_DMAREQ1_PRSSEL_PRSCH14 (_PRS_DMAREQ1_PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PRS_DMAREQ1 */ 8176 #define PRS_DMAREQ1_PRSSEL_PRSCH15 (_PRS_DMAREQ1_PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PRS_DMAREQ1 */ 8177 #define PRS_DMAREQ1_PRSSEL_PRSCH16 (_PRS_DMAREQ1_PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PRS_DMAREQ1 */ 8178 #define PRS_DMAREQ1_PRSSEL_PRSCH17 (_PRS_DMAREQ1_PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PRS_DMAREQ1 */ 8179 #define PRS_DMAREQ1_PRSSEL_PRSCH18 (_PRS_DMAREQ1_PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PRS_DMAREQ1 */ 8180 #define PRS_DMAREQ1_PRSSEL_PRSCH19 (_PRS_DMAREQ1_PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PRS_DMAREQ1 */ 8181 #define PRS_DMAREQ1_PRSSEL_PRSCH20 (_PRS_DMAREQ1_PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PRS_DMAREQ1 */ 8182 #define PRS_DMAREQ1_PRSSEL_PRSCH21 (_PRS_DMAREQ1_PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PRS_DMAREQ1 */ 8183 #define PRS_DMAREQ1_PRSSEL_PRSCH22 (_PRS_DMAREQ1_PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PRS_DMAREQ1 */ 8184 #define PRS_DMAREQ1_PRSSEL_PRSCH23 (_PRS_DMAREQ1_PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PRS_DMAREQ1 */ 8185 8186 /* Bit fields for PRS PEEK */ 8187 #define _PRS_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_PEEK */ 8188 #define _PRS_PEEK_MASK 0x00FFFFFFUL /**< Mask for PRS_PEEK */ 8189 #define PRS_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ 8190 #define _PRS_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ 8191 #define _PRS_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ 8192 #define _PRS_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8193 #define PRS_PEEK_CH0VAL_DEFAULT (_PRS_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_PEEK */ 8194 #define PRS_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ 8195 #define _PRS_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ 8196 #define _PRS_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ 8197 #define _PRS_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8198 #define PRS_PEEK_CH1VAL_DEFAULT (_PRS_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_PEEK */ 8199 #define PRS_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ 8200 #define _PRS_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ 8201 #define _PRS_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ 8202 #define _PRS_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8203 #define PRS_PEEK_CH2VAL_DEFAULT (_PRS_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_PEEK */ 8204 #define PRS_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ 8205 #define _PRS_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ 8206 #define _PRS_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ 8207 #define _PRS_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8208 #define PRS_PEEK_CH3VAL_DEFAULT (_PRS_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_PEEK */ 8209 #define PRS_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ 8210 #define _PRS_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ 8211 #define _PRS_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ 8212 #define _PRS_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8213 #define PRS_PEEK_CH4VAL_DEFAULT (_PRS_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_PEEK */ 8214 #define PRS_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ 8215 #define _PRS_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ 8216 #define _PRS_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ 8217 #define _PRS_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8218 #define PRS_PEEK_CH5VAL_DEFAULT (_PRS_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_PEEK */ 8219 #define PRS_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ 8220 #define _PRS_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ 8221 #define _PRS_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ 8222 #define _PRS_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8223 #define PRS_PEEK_CH6VAL_DEFAULT (_PRS_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_PEEK */ 8224 #define PRS_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ 8225 #define _PRS_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ 8226 #define _PRS_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ 8227 #define _PRS_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8228 #define PRS_PEEK_CH7VAL_DEFAULT (_PRS_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_PEEK */ 8229 #define PRS_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ 8230 #define _PRS_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ 8231 #define _PRS_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ 8232 #define _PRS_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8233 #define PRS_PEEK_CH8VAL_DEFAULT (_PRS_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_PEEK */ 8234 #define PRS_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ 8235 #define _PRS_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ 8236 #define _PRS_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ 8237 #define _PRS_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8238 #define PRS_PEEK_CH9VAL_DEFAULT (_PRS_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_PEEK */ 8239 #define PRS_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ 8240 #define _PRS_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ 8241 #define _PRS_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ 8242 #define _PRS_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8243 #define PRS_PEEK_CH10VAL_DEFAULT (_PRS_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_PEEK */ 8244 #define PRS_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ 8245 #define _PRS_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ 8246 #define _PRS_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ 8247 #define _PRS_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8248 #define PRS_PEEK_CH11VAL_DEFAULT (_PRS_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_PEEK */ 8249 #define PRS_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ 8250 #define _PRS_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ 8251 #define _PRS_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ 8252 #define _PRS_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8253 #define PRS_PEEK_CH12VAL_DEFAULT (_PRS_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_PEEK */ 8254 #define PRS_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 Current Value */ 8255 #define _PRS_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ 8256 #define _PRS_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ 8257 #define _PRS_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8258 #define PRS_PEEK_CH13VAL_DEFAULT (_PRS_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_PEEK */ 8259 #define PRS_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 Current Value */ 8260 #define _PRS_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ 8261 #define _PRS_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ 8262 #define _PRS_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8263 #define PRS_PEEK_CH14VAL_DEFAULT (_PRS_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_PEEK */ 8264 #define PRS_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 Current Value */ 8265 #define _PRS_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ 8266 #define _PRS_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ 8267 #define _PRS_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8268 #define PRS_PEEK_CH15VAL_DEFAULT (_PRS_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_PEEK */ 8269 #define PRS_PEEK_CH16VAL (0x1UL << 16) /**< Channel 16 Current Value */ 8270 #define _PRS_PEEK_CH16VAL_SHIFT 16 /**< Shift value for PRS_CH16VAL */ 8271 #define _PRS_PEEK_CH16VAL_MASK 0x10000UL /**< Bit mask for PRS_CH16VAL */ 8272 #define _PRS_PEEK_CH16VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8273 #define PRS_PEEK_CH16VAL_DEFAULT (_PRS_PEEK_CH16VAL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_PEEK */ 8274 #define PRS_PEEK_CH17VAL (0x1UL << 17) /**< Channel 17 Current Value */ 8275 #define _PRS_PEEK_CH17VAL_SHIFT 17 /**< Shift value for PRS_CH17VAL */ 8276 #define _PRS_PEEK_CH17VAL_MASK 0x20000UL /**< Bit mask for PRS_CH17VAL */ 8277 #define _PRS_PEEK_CH17VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8278 #define PRS_PEEK_CH17VAL_DEFAULT (_PRS_PEEK_CH17VAL_DEFAULT << 17) /**< Shifted mode DEFAULT for PRS_PEEK */ 8279 #define PRS_PEEK_CH18VAL (0x1UL << 18) /**< Channel 18 Current Value */ 8280 #define _PRS_PEEK_CH18VAL_SHIFT 18 /**< Shift value for PRS_CH18VAL */ 8281 #define _PRS_PEEK_CH18VAL_MASK 0x40000UL /**< Bit mask for PRS_CH18VAL */ 8282 #define _PRS_PEEK_CH18VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8283 #define PRS_PEEK_CH18VAL_DEFAULT (_PRS_PEEK_CH18VAL_DEFAULT << 18) /**< Shifted mode DEFAULT for PRS_PEEK */ 8284 #define PRS_PEEK_CH19VAL (0x1UL << 19) /**< Channel 19 Current Value */ 8285 #define _PRS_PEEK_CH19VAL_SHIFT 19 /**< Shift value for PRS_CH19VAL */ 8286 #define _PRS_PEEK_CH19VAL_MASK 0x80000UL /**< Bit mask for PRS_CH19VAL */ 8287 #define _PRS_PEEK_CH19VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8288 #define PRS_PEEK_CH19VAL_DEFAULT (_PRS_PEEK_CH19VAL_DEFAULT << 19) /**< Shifted mode DEFAULT for PRS_PEEK */ 8289 #define PRS_PEEK_CH20VAL (0x1UL << 20) /**< Channel 20 Current Value */ 8290 #define _PRS_PEEK_CH20VAL_SHIFT 20 /**< Shift value for PRS_CH20VAL */ 8291 #define _PRS_PEEK_CH20VAL_MASK 0x100000UL /**< Bit mask for PRS_CH20VAL */ 8292 #define _PRS_PEEK_CH20VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8293 #define PRS_PEEK_CH20VAL_DEFAULT (_PRS_PEEK_CH20VAL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_PEEK */ 8294 #define PRS_PEEK_CH21VAL (0x1UL << 21) /**< Channel 21 Current Value */ 8295 #define _PRS_PEEK_CH21VAL_SHIFT 21 /**< Shift value for PRS_CH21VAL */ 8296 #define _PRS_PEEK_CH21VAL_MASK 0x200000UL /**< Bit mask for PRS_CH21VAL */ 8297 #define _PRS_PEEK_CH21VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8298 #define PRS_PEEK_CH21VAL_DEFAULT (_PRS_PEEK_CH21VAL_DEFAULT << 21) /**< Shifted mode DEFAULT for PRS_PEEK */ 8299 #define PRS_PEEK_CH22VAL (0x1UL << 22) /**< Channel 22 Current Value */ 8300 #define _PRS_PEEK_CH22VAL_SHIFT 22 /**< Shift value for PRS_CH22VAL */ 8301 #define _PRS_PEEK_CH22VAL_MASK 0x400000UL /**< Bit mask for PRS_CH22VAL */ 8302 #define _PRS_PEEK_CH22VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8303 #define PRS_PEEK_CH22VAL_DEFAULT (_PRS_PEEK_CH22VAL_DEFAULT << 22) /**< Shifted mode DEFAULT for PRS_PEEK */ 8304 #define PRS_PEEK_CH23VAL (0x1UL << 23) /**< Channel 23 Current Value */ 8305 #define _PRS_PEEK_CH23VAL_SHIFT 23 /**< Shift value for PRS_CH23VAL */ 8306 #define _PRS_PEEK_CH23VAL_MASK 0x800000UL /**< Bit mask for PRS_CH23VAL */ 8307 #define _PRS_PEEK_CH23VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_PEEK */ 8308 #define PRS_PEEK_CH23VAL_DEFAULT (_PRS_PEEK_CH23VAL_DEFAULT << 23) /**< Shifted mode DEFAULT for PRS_PEEK */ 8309 8310 /* Bit fields for PRS CH_CTRL */ 8311 #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ 8312 #define _PRS_CH_CTRL_MASK 0x5E307F07UL /**< Mask for PRS_CH_CTRL */ 8313 #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ 8314 #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ 8315 #define _PRS_CH_CTRL_SIGSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_CH_CTRL */ 8316 #define _PRS_CH_CTRL_SIGSEL_PRSCH8 0x00000000UL /**< Mode PRSCH8 for PRS_CH_CTRL */ 8317 #define _PRS_CH_CTRL_SIGSEL_PRSCH16 0x00000000UL /**< Mode PRSCH16 for PRS_CH_CTRL */ 8318 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ 8319 #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ 8320 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ 8321 #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ 8322 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ 8323 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ 8324 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ 8325 #define _PRS_CH_CTRL_SIGSEL_LETIMER1CH0 0x00000000UL /**< Mode LETIMER1CH0 for PRS_CH_CTRL */ 8326 #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ 8327 #define _PRS_CH_CTRL_SIGSEL_PCNT1TCC 0x00000000UL /**< Mode PCNT1TCC for PRS_CH_CTRL */ 8328 #define _PRS_CH_CTRL_SIGSEL_PCNT2TCC 0x00000000UL /**< Mode PCNT2TCC for PRS_CH_CTRL */ 8329 #define _PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD 0x00000000UL /**< Mode CRYOTIMERPERIOD for PRS_CH_CTRL */ 8330 #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 0x00000000UL /**< Mode CMUCLKOUT0 for PRS_CH_CTRL */ 8331 #define _PRS_CH_CTRL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for PRS_CH_CTRL */ 8332 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ 8333 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ 8334 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ 8335 #define _PRS_CH_CTRL_SIGSEL_LESENSEMEASACT 0x00000000UL /**< Mode LESENSEMEASACT for PRS_CH_CTRL */ 8336 #define _PRS_CH_CTRL_SIGSEL_ACMP2OUT 0x00000000UL /**< Mode ACMP2OUT for PRS_CH_CTRL */ 8337 #define _PRS_CH_CTRL_SIGSEL_ACMP3OUT 0x00000000UL /**< Mode ACMP3OUT for PRS_CH_CTRL */ 8338 #define _PRS_CH_CTRL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for PRS_CH_CTRL */ 8339 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ 8340 #define _PRS_CH_CTRL_SIGSEL_USART2IRTX 0x00000000UL /**< Mode USART2IRTX for PRS_CH_CTRL */ 8341 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ 8342 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ 8343 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ 8344 #define _PRS_CH_CTRL_SIGSEL_CM4TXEV 0x00000000UL /**< Mode CM4TXEV for PRS_CH_CTRL */ 8345 #define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ 8346 #define _PRS_CH_CTRL_SIGSEL_WTIMER0UF 0x00000000UL /**< Mode WTIMER0UF for PRS_CH_CTRL */ 8347 #define _PRS_CH_CTRL_SIGSEL_WTIMER1UF 0x00000000UL /**< Mode WTIMER1UF for PRS_CH_CTRL */ 8348 #define _PRS_CH_CTRL_SIGSEL_WTIMER2UF 0x00000000UL /**< Mode WTIMER2UF for PRS_CH_CTRL */ 8349 #define _PRS_CH_CTRL_SIGSEL_WTIMER3UF 0x00000000UL /**< Mode WTIMER3UF for PRS_CH_CTRL */ 8350 #define _PRS_CH_CTRL_SIGSEL_TIMER4UF 0x00000000UL /**< Mode TIMER4UF for PRS_CH_CTRL */ 8351 #define _PRS_CH_CTRL_SIGSEL_TIMER5UF 0x00000000UL /**< Mode TIMER5UF for PRS_CH_CTRL */ 8352 #define _PRS_CH_CTRL_SIGSEL_TIMER6UF 0x00000000UL /**< Mode TIMER6UF for PRS_CH_CTRL */ 8353 #define _PRS_CH_CTRL_SIGSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_CH_CTRL */ 8354 #define _PRS_CH_CTRL_SIGSEL_PRSCH9 0x00000001UL /**< Mode PRSCH9 for PRS_CH_CTRL */ 8355 #define _PRS_CH_CTRL_SIGSEL_PRSCH17 0x00000001UL /**< Mode PRSCH17 for PRS_CH_CTRL */ 8356 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ 8357 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ 8358 #define _PRS_CH_CTRL_SIGSEL_RTCCCCV0 0x00000001UL /**< Mode RTCCCCV0 for PRS_CH_CTRL */ 8359 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ 8360 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ 8361 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ 8362 #define _PRS_CH_CTRL_SIGSEL_LETIMER1CH1 0x00000001UL /**< Mode LETIMER1CH1 for PRS_CH_CTRL */ 8363 #define _PRS_CH_CTRL_SIGSEL_PCNT0UFOF 0x00000001UL /**< Mode PCNT0UFOF for PRS_CH_CTRL */ 8364 #define _PRS_CH_CTRL_SIGSEL_PCNT1UFOF 0x00000001UL /**< Mode PCNT1UFOF for PRS_CH_CTRL */ 8365 #define _PRS_CH_CTRL_SIGSEL_PCNT2UFOF 0x00000001UL /**< Mode PCNT2UFOF for PRS_CH_CTRL */ 8366 #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 0x00000001UL /**< Mode CMUCLKOUT1 for PRS_CH_CTRL */ 8367 #define _PRS_CH_CTRL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for PRS_CH_CTRL */ 8368 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ 8369 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ 8370 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ 8371 #define _PRS_CH_CTRL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for PRS_CH_CTRL */ 8372 #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ 8373 #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ 8374 #define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ 8375 #define _PRS_CH_CTRL_SIGSEL_USART3TXC 0x00000001UL /**< Mode USART3TXC for PRS_CH_CTRL */ 8376 #define _PRS_CH_CTRL_SIGSEL_USART4TXC 0x00000001UL /**< Mode USART4TXC for PRS_CH_CTRL */ 8377 #define _PRS_CH_CTRL_SIGSEL_USART5TXC 0x00000001UL /**< Mode USART5TXC for PRS_CH_CTRL */ 8378 #define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ 8379 #define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ 8380 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ 8381 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ 8382 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ 8383 #define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF 0x00000001UL /**< Mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ 8384 #define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ 8385 #define _PRS_CH_CTRL_SIGSEL_WTIMER0OF 0x00000001UL /**< Mode WTIMER0OF for PRS_CH_CTRL */ 8386 #define _PRS_CH_CTRL_SIGSEL_WTIMER1OF 0x00000001UL /**< Mode WTIMER1OF for PRS_CH_CTRL */ 8387 #define _PRS_CH_CTRL_SIGSEL_WTIMER2OF 0x00000001UL /**< Mode WTIMER2OF for PRS_CH_CTRL */ 8388 #define _PRS_CH_CTRL_SIGSEL_WTIMER3OF 0x00000001UL /**< Mode WTIMER3OF for PRS_CH_CTRL */ 8389 #define _PRS_CH_CTRL_SIGSEL_TIMER4OF 0x00000001UL /**< Mode TIMER4OF for PRS_CH_CTRL */ 8390 #define _PRS_CH_CTRL_SIGSEL_TIMER5OF 0x00000001UL /**< Mode TIMER5OF for PRS_CH_CTRL */ 8391 #define _PRS_CH_CTRL_SIGSEL_TIMER6OF 0x00000001UL /**< Mode TIMER6OF for PRS_CH_CTRL */ 8392 #define _PRS_CH_CTRL_SIGSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_CH_CTRL */ 8393 #define _PRS_CH_CTRL_SIGSEL_PRSCH10 0x00000002UL /**< Mode PRSCH10 for PRS_CH_CTRL */ 8394 #define _PRS_CH_CTRL_SIGSEL_PRSCH18 0x00000002UL /**< Mode PRSCH18 for PRS_CH_CTRL */ 8395 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ 8396 #define _PRS_CH_CTRL_SIGSEL_RTCCCCV1 0x00000002UL /**< Mode RTCCCCV1 for PRS_CH_CTRL */ 8397 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ 8398 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ 8399 #define _PRS_CH_CTRL_SIGSEL_PCNT0DIR 0x00000002UL /**< Mode PCNT0DIR for PRS_CH_CTRL */ 8400 #define _PRS_CH_CTRL_SIGSEL_PCNT1DIR 0x00000002UL /**< Mode PCNT1DIR for PRS_CH_CTRL */ 8401 #define _PRS_CH_CTRL_SIGSEL_PCNT2DIR 0x00000002UL /**< Mode PCNT2DIR for PRS_CH_CTRL */ 8402 #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA0 0x00000002UL /**< Mode VDAC0OPA0 for PRS_CH_CTRL */ 8403 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ 8404 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ 8405 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ 8406 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ 8407 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ 8408 #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ 8409 #define _PRS_CH_CTRL_SIGSEL_USART3RXDATAV 0x00000002UL /**< Mode USART3RXDATAV for PRS_CH_CTRL */ 8410 #define _PRS_CH_CTRL_SIGSEL_USART4RXDATAV 0x00000002UL /**< Mode USART4RXDATAV for PRS_CH_CTRL */ 8411 #define _PRS_CH_CTRL_SIGSEL_USART5RXDATAV 0x00000002UL /**< Mode USART5RXDATAV for PRS_CH_CTRL */ 8412 #define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ 8413 #define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ 8414 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ 8415 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ 8416 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ 8417 #define _PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF 0x00000002UL /**< Mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ 8418 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ 8419 #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC0 0x00000002UL /**< Mode WTIMER0CC0 for PRS_CH_CTRL */ 8420 #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC0 0x00000002UL /**< Mode WTIMER1CC0 for PRS_CH_CTRL */ 8421 #define _PRS_CH_CTRL_SIGSEL_WTIMER2CC0 0x00000002UL /**< Mode WTIMER2CC0 for PRS_CH_CTRL */ 8422 #define _PRS_CH_CTRL_SIGSEL_WTIMER3CC0 0x00000002UL /**< Mode WTIMER3CC0 for PRS_CH_CTRL */ 8423 #define _PRS_CH_CTRL_SIGSEL_TIMER4CC0 0x00000002UL /**< Mode TIMER4CC0 for PRS_CH_CTRL */ 8424 #define _PRS_CH_CTRL_SIGSEL_TIMER5CC0 0x00000002UL /**< Mode TIMER5CC0 for PRS_CH_CTRL */ 8425 #define _PRS_CH_CTRL_SIGSEL_TIMER6CC0 0x00000002UL /**< Mode TIMER6CC0 for PRS_CH_CTRL */ 8426 #define _PRS_CH_CTRL_SIGSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_CH_CTRL */ 8427 #define _PRS_CH_CTRL_SIGSEL_PRSCH11 0x00000003UL /**< Mode PRSCH11 for PRS_CH_CTRL */ 8428 #define _PRS_CH_CTRL_SIGSEL_PRSCH19 0x00000003UL /**< Mode PRSCH19 for PRS_CH_CTRL */ 8429 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP2 0x00000003UL /**< Mode RTCCOMP2 for PRS_CH_CTRL */ 8430 #define _PRS_CH_CTRL_SIGSEL_RTCCCCV2 0x00000003UL /**< Mode RTCCCCV2 for PRS_CH_CTRL */ 8431 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ 8432 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ 8433 #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA1 0x00000003UL /**< Mode VDAC0OPA1 for PRS_CH_CTRL */ 8434 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ 8435 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ 8436 #define _PRS_CH_CTRL_SIGSEL_LESENSEDECCMP 0x00000003UL /**< Mode LESENSEDECCMP for PRS_CH_CTRL */ 8437 #define _PRS_CH_CTRL_SIGSEL_USART0RTS 0x00000003UL /**< Mode USART0RTS for PRS_CH_CTRL */ 8438 #define _PRS_CH_CTRL_SIGSEL_USART1RTS 0x00000003UL /**< Mode USART1RTS for PRS_CH_CTRL */ 8439 #define _PRS_CH_CTRL_SIGSEL_USART2RTS 0x00000003UL /**< Mode USART2RTS for PRS_CH_CTRL */ 8440 #define _PRS_CH_CTRL_SIGSEL_USART3RTS 0x00000003UL /**< Mode USART3RTS for PRS_CH_CTRL */ 8441 #define _PRS_CH_CTRL_SIGSEL_USART4RTS 0x00000003UL /**< Mode USART4RTS for PRS_CH_CTRL */ 8442 #define _PRS_CH_CTRL_SIGSEL_USART5RTS 0x00000003UL /**< Mode USART5RTS for PRS_CH_CTRL */ 8443 #define _PRS_CH_CTRL_SIGSEL_UART0RTS 0x00000003UL /**< Mode UART0RTS for PRS_CH_CTRL */ 8444 #define _PRS_CH_CTRL_SIGSEL_UART1RTS 0x00000003UL /**< Mode UART1RTS for PRS_CH_CTRL */ 8445 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ 8446 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ 8447 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ 8448 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ 8449 #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC1 0x00000003UL /**< Mode WTIMER0CC1 for PRS_CH_CTRL */ 8450 #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC1 0x00000003UL /**< Mode WTIMER1CC1 for PRS_CH_CTRL */ 8451 #define _PRS_CH_CTRL_SIGSEL_WTIMER2CC1 0x00000003UL /**< Mode WTIMER2CC1 for PRS_CH_CTRL */ 8452 #define _PRS_CH_CTRL_SIGSEL_WTIMER3CC1 0x00000003UL /**< Mode WTIMER3CC1 for PRS_CH_CTRL */ 8453 #define _PRS_CH_CTRL_SIGSEL_TIMER4CC1 0x00000003UL /**< Mode TIMER4CC1 for PRS_CH_CTRL */ 8454 #define _PRS_CH_CTRL_SIGSEL_TIMER5CC1 0x00000003UL /**< Mode TIMER5CC1 for PRS_CH_CTRL */ 8455 #define _PRS_CH_CTRL_SIGSEL_TIMER6CC1 0x00000003UL /**< Mode TIMER6CC1 for PRS_CH_CTRL */ 8456 #define _PRS_CH_CTRL_SIGSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_CH_CTRL */ 8457 #define _PRS_CH_CTRL_SIGSEL_PRSCH12 0x00000004UL /**< Mode PRSCH12 for PRS_CH_CTRL */ 8458 #define _PRS_CH_CTRL_SIGSEL_PRSCH20 0x00000004UL /**< Mode PRSCH20 for PRS_CH_CTRL */ 8459 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP3 0x00000004UL /**< Mode RTCCOMP3 for PRS_CH_CTRL */ 8460 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ 8461 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ 8462 #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA2 0x00000004UL /**< Mode VDAC0OPA2 for PRS_CH_CTRL */ 8463 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ 8464 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ 8465 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ 8466 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ 8467 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ 8468 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ 8469 #define _PRS_CH_CTRL_SIGSEL_WTIMER0CC2 0x00000004UL /**< Mode WTIMER0CC2 for PRS_CH_CTRL */ 8470 #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC2 0x00000004UL /**< Mode WTIMER1CC2 for PRS_CH_CTRL */ 8471 #define _PRS_CH_CTRL_SIGSEL_WTIMER2CC2 0x00000004UL /**< Mode WTIMER2CC2 for PRS_CH_CTRL */ 8472 #define _PRS_CH_CTRL_SIGSEL_WTIMER3CC2 0x00000004UL /**< Mode WTIMER3CC2 for PRS_CH_CTRL */ 8473 #define _PRS_CH_CTRL_SIGSEL_TIMER4CC2 0x00000004UL /**< Mode TIMER4CC2 for PRS_CH_CTRL */ 8474 #define _PRS_CH_CTRL_SIGSEL_TIMER5CC2 0x00000004UL /**< Mode TIMER5CC2 for PRS_CH_CTRL */ 8475 #define _PRS_CH_CTRL_SIGSEL_TIMER6CC2 0x00000004UL /**< Mode TIMER6CC2 for PRS_CH_CTRL */ 8476 #define _PRS_CH_CTRL_SIGSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_CH_CTRL */ 8477 #define _PRS_CH_CTRL_SIGSEL_PRSCH13 0x00000005UL /**< Mode PRSCH13 for PRS_CH_CTRL */ 8478 #define _PRS_CH_CTRL_SIGSEL_PRSCH21 0x00000005UL /**< Mode PRSCH21 for PRS_CH_CTRL */ 8479 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP4 0x00000005UL /**< Mode RTCCOMP4 for PRS_CH_CTRL */ 8480 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ 8481 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ 8482 #define _PRS_CH_CTRL_SIGSEL_VDAC0OPA3 0x00000005UL /**< Mode VDAC0OPA3 for PRS_CH_CTRL */ 8483 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ 8484 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ 8485 #define _PRS_CH_CTRL_SIGSEL_USART0TX 0x00000005UL /**< Mode USART0TX for PRS_CH_CTRL */ 8486 #define _PRS_CH_CTRL_SIGSEL_USART1TX 0x00000005UL /**< Mode USART1TX for PRS_CH_CTRL */ 8487 #define _PRS_CH_CTRL_SIGSEL_USART2TX 0x00000005UL /**< Mode USART2TX for PRS_CH_CTRL */ 8488 #define _PRS_CH_CTRL_SIGSEL_USART3TX 0x00000005UL /**< Mode USART3TX for PRS_CH_CTRL */ 8489 #define _PRS_CH_CTRL_SIGSEL_USART4TX 0x00000005UL /**< Mode USART4TX for PRS_CH_CTRL */ 8490 #define _PRS_CH_CTRL_SIGSEL_USART5TX 0x00000005UL /**< Mode USART5TX for PRS_CH_CTRL */ 8491 #define _PRS_CH_CTRL_SIGSEL_UART0TX 0x00000005UL /**< Mode UART0TX for PRS_CH_CTRL */ 8492 #define _PRS_CH_CTRL_SIGSEL_UART1TX 0x00000005UL /**< Mode UART1TX for PRS_CH_CTRL */ 8493 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC3 0x00000005UL /**< Mode TIMER1CC3 for PRS_CH_CTRL */ 8494 #define _PRS_CH_CTRL_SIGSEL_WTIMER1CC3 0x00000005UL /**< Mode WTIMER1CC3 for PRS_CH_CTRL */ 8495 #define _PRS_CH_CTRL_SIGSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PRS_CH_CTRL */ 8496 #define _PRS_CH_CTRL_SIGSEL_PRSCH14 0x00000006UL /**< Mode PRSCH14 for PRS_CH_CTRL */ 8497 #define _PRS_CH_CTRL_SIGSEL_PRSCH22 0x00000006UL /**< Mode PRSCH22 for PRS_CH_CTRL */ 8498 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP5 0x00000006UL /**< Mode RTCCOMP5 for PRS_CH_CTRL */ 8499 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ 8500 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ 8501 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ 8502 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ 8503 #define _PRS_CH_CTRL_SIGSEL_USART0CS 0x00000006UL /**< Mode USART0CS for PRS_CH_CTRL */ 8504 #define _PRS_CH_CTRL_SIGSEL_USART1CS 0x00000006UL /**< Mode USART1CS for PRS_CH_CTRL */ 8505 #define _PRS_CH_CTRL_SIGSEL_USART2CS 0x00000006UL /**< Mode USART2CS for PRS_CH_CTRL */ 8506 #define _PRS_CH_CTRL_SIGSEL_USART3CS 0x00000006UL /**< Mode USART3CS for PRS_CH_CTRL */ 8507 #define _PRS_CH_CTRL_SIGSEL_USART4CS 0x00000006UL /**< Mode USART4CS for PRS_CH_CTRL */ 8508 #define _PRS_CH_CTRL_SIGSEL_USART5CS 0x00000006UL /**< Mode USART5CS for PRS_CH_CTRL */ 8509 #define _PRS_CH_CTRL_SIGSEL_UART0CS 0x00000006UL /**< Mode UART0CS for PRS_CH_CTRL */ 8510 #define _PRS_CH_CTRL_SIGSEL_UART1CS 0x00000006UL /**< Mode UART1CS for PRS_CH_CTRL */ 8511 #define _PRS_CH_CTRL_SIGSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PRS_CH_CTRL */ 8512 #define _PRS_CH_CTRL_SIGSEL_PRSCH15 0x00000007UL /**< Mode PRSCH15 for PRS_CH_CTRL */ 8513 #define _PRS_CH_CTRL_SIGSEL_PRSCH23 0x00000007UL /**< Mode PRSCH23 for PRS_CH_CTRL */ 8514 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ 8515 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ 8516 #define _PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 0x00000007UL /**< Mode CMUCLKOUT2 for PRS_CH_CTRL */ 8517 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ 8518 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ 8519 #define PRS_CH_CTRL_SIGSEL_PRSCH0 (_PRS_CH_CTRL_SIGSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PRS_CH_CTRL */ 8520 #define PRS_CH_CTRL_SIGSEL_PRSCH8 (_PRS_CH_CTRL_SIGSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PRS_CH_CTRL */ 8521 #define PRS_CH_CTRL_SIGSEL_PRSCH16 (_PRS_CH_CTRL_SIGSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PRS_CH_CTRL */ 8522 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ 8523 #define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ 8524 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ 8525 #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ 8526 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ 8527 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ 8528 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ 8529 #define PRS_CH_CTRL_SIGSEL_LETIMER1CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH0 << 0) /**< Shifted mode LETIMER1CH0 for PRS_CH_CTRL */ 8530 #define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ 8531 #define PRS_CH_CTRL_SIGSEL_PCNT1TCC (_PRS_CH_CTRL_SIGSEL_PCNT1TCC << 0) /**< Shifted mode PCNT1TCC for PRS_CH_CTRL */ 8532 #define PRS_CH_CTRL_SIGSEL_PCNT2TCC (_PRS_CH_CTRL_SIGSEL_PCNT2TCC << 0) /**< Shifted mode PCNT2TCC for PRS_CH_CTRL */ 8533 #define PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD (_PRS_CH_CTRL_SIGSEL_CRYOTIMERPERIOD << 0) /**< Shifted mode CRYOTIMERPERIOD for PRS_CH_CTRL */ 8534 #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT0 << 0) /**< Shifted mode CMUCLKOUT0 for PRS_CH_CTRL */ 8535 #define PRS_CH_CTRL_SIGSEL_VDAC0CH0 (_PRS_CH_CTRL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for PRS_CH_CTRL */ 8536 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ 8537 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ 8538 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ 8539 #define PRS_CH_CTRL_SIGSEL_LESENSEMEASACT (_PRS_CH_CTRL_SIGSEL_LESENSEMEASACT << 0) /**< Shifted mode LESENSEMEASACT for PRS_CH_CTRL */ 8540 #define PRS_CH_CTRL_SIGSEL_ACMP2OUT (_PRS_CH_CTRL_SIGSEL_ACMP2OUT << 0) /**< Shifted mode ACMP2OUT for PRS_CH_CTRL */ 8541 #define PRS_CH_CTRL_SIGSEL_ACMP3OUT (_PRS_CH_CTRL_SIGSEL_ACMP3OUT << 0) /**< Shifted mode ACMP3OUT for PRS_CH_CTRL */ 8542 #define PRS_CH_CTRL_SIGSEL_ADC1SINGLE (_PRS_CH_CTRL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for PRS_CH_CTRL */ 8543 #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ 8544 #define PRS_CH_CTRL_SIGSEL_USART2IRTX (_PRS_CH_CTRL_SIGSEL_USART2IRTX << 0) /**< Shifted mode USART2IRTX for PRS_CH_CTRL */ 8545 #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ 8546 #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ 8547 #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ 8548 #define PRS_CH_CTRL_SIGSEL_CM4TXEV (_PRS_CH_CTRL_SIGSEL_CM4TXEV << 0) /**< Shifted mode CM4TXEV for PRS_CH_CTRL */ 8549 #define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ 8550 #define PRS_CH_CTRL_SIGSEL_WTIMER0UF (_PRS_CH_CTRL_SIGSEL_WTIMER0UF << 0) /**< Shifted mode WTIMER0UF for PRS_CH_CTRL */ 8551 #define PRS_CH_CTRL_SIGSEL_WTIMER1UF (_PRS_CH_CTRL_SIGSEL_WTIMER1UF << 0) /**< Shifted mode WTIMER1UF for PRS_CH_CTRL */ 8552 #define PRS_CH_CTRL_SIGSEL_WTIMER2UF (_PRS_CH_CTRL_SIGSEL_WTIMER2UF << 0) /**< Shifted mode WTIMER2UF for PRS_CH_CTRL */ 8553 #define PRS_CH_CTRL_SIGSEL_WTIMER3UF (_PRS_CH_CTRL_SIGSEL_WTIMER3UF << 0) /**< Shifted mode WTIMER3UF for PRS_CH_CTRL */ 8554 #define PRS_CH_CTRL_SIGSEL_TIMER4UF (_PRS_CH_CTRL_SIGSEL_TIMER4UF << 0) /**< Shifted mode TIMER4UF for PRS_CH_CTRL */ 8555 #define PRS_CH_CTRL_SIGSEL_TIMER5UF (_PRS_CH_CTRL_SIGSEL_TIMER5UF << 0) /**< Shifted mode TIMER5UF for PRS_CH_CTRL */ 8556 #define PRS_CH_CTRL_SIGSEL_TIMER6UF (_PRS_CH_CTRL_SIGSEL_TIMER6UF << 0) /**< Shifted mode TIMER6UF for PRS_CH_CTRL */ 8557 #define PRS_CH_CTRL_SIGSEL_PRSCH1 (_PRS_CH_CTRL_SIGSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PRS_CH_CTRL */ 8558 #define PRS_CH_CTRL_SIGSEL_PRSCH9 (_PRS_CH_CTRL_SIGSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PRS_CH_CTRL */ 8559 #define PRS_CH_CTRL_SIGSEL_PRSCH17 (_PRS_CH_CTRL_SIGSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PRS_CH_CTRL */ 8560 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ 8561 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ 8562 #define PRS_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_CH_CTRL_SIGSEL_RTCCCCV0 << 0) /**< Shifted mode RTCCCCV0 for PRS_CH_CTRL */ 8563 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ 8564 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ 8565 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ 8566 #define PRS_CH_CTRL_SIGSEL_LETIMER1CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER1CH1 << 0) /**< Shifted mode LETIMER1CH1 for PRS_CH_CTRL */ 8567 #define PRS_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_CH_CTRL_SIGSEL_PCNT0UFOF << 0) /**< Shifted mode PCNT0UFOF for PRS_CH_CTRL */ 8568 #define PRS_CH_CTRL_SIGSEL_PCNT1UFOF (_PRS_CH_CTRL_SIGSEL_PCNT1UFOF << 0) /**< Shifted mode PCNT1UFOF for PRS_CH_CTRL */ 8569 #define PRS_CH_CTRL_SIGSEL_PCNT2UFOF (_PRS_CH_CTRL_SIGSEL_PCNT2UFOF << 0) /**< Shifted mode PCNT2UFOF for PRS_CH_CTRL */ 8570 #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT1 << 0) /**< Shifted mode CMUCLKOUT1 for PRS_CH_CTRL */ 8571 #define PRS_CH_CTRL_SIGSEL_VDAC0CH1 (_PRS_CH_CTRL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for PRS_CH_CTRL */ 8572 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ 8573 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ 8574 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ 8575 #define PRS_CH_CTRL_SIGSEL_ADC1SCAN (_PRS_CH_CTRL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for PRS_CH_CTRL */ 8576 #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ 8577 #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ 8578 #define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ 8579 #define PRS_CH_CTRL_SIGSEL_USART3TXC (_PRS_CH_CTRL_SIGSEL_USART3TXC << 0) /**< Shifted mode USART3TXC for PRS_CH_CTRL */ 8580 #define PRS_CH_CTRL_SIGSEL_USART4TXC (_PRS_CH_CTRL_SIGSEL_USART4TXC << 0) /**< Shifted mode USART4TXC for PRS_CH_CTRL */ 8581 #define PRS_CH_CTRL_SIGSEL_USART5TXC (_PRS_CH_CTRL_SIGSEL_USART5TXC << 0) /**< Shifted mode USART5TXC for PRS_CH_CTRL */ 8582 #define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ 8583 #define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ 8584 #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ 8585 #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ 8586 #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ 8587 #define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCHITSOF << 0) /**< Shifted mode CM4ICACHEPCHITSOF for PRS_CH_CTRL */ 8588 #define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ 8589 #define PRS_CH_CTRL_SIGSEL_WTIMER0OF (_PRS_CH_CTRL_SIGSEL_WTIMER0OF << 0) /**< Shifted mode WTIMER0OF for PRS_CH_CTRL */ 8590 #define PRS_CH_CTRL_SIGSEL_WTIMER1OF (_PRS_CH_CTRL_SIGSEL_WTIMER1OF << 0) /**< Shifted mode WTIMER1OF for PRS_CH_CTRL */ 8591 #define PRS_CH_CTRL_SIGSEL_WTIMER2OF (_PRS_CH_CTRL_SIGSEL_WTIMER2OF << 0) /**< Shifted mode WTIMER2OF for PRS_CH_CTRL */ 8592 #define PRS_CH_CTRL_SIGSEL_WTIMER3OF (_PRS_CH_CTRL_SIGSEL_WTIMER3OF << 0) /**< Shifted mode WTIMER3OF for PRS_CH_CTRL */ 8593 #define PRS_CH_CTRL_SIGSEL_TIMER4OF (_PRS_CH_CTRL_SIGSEL_TIMER4OF << 0) /**< Shifted mode TIMER4OF for PRS_CH_CTRL */ 8594 #define PRS_CH_CTRL_SIGSEL_TIMER5OF (_PRS_CH_CTRL_SIGSEL_TIMER5OF << 0) /**< Shifted mode TIMER5OF for PRS_CH_CTRL */ 8595 #define PRS_CH_CTRL_SIGSEL_TIMER6OF (_PRS_CH_CTRL_SIGSEL_TIMER6OF << 0) /**< Shifted mode TIMER6OF for PRS_CH_CTRL */ 8596 #define PRS_CH_CTRL_SIGSEL_PRSCH2 (_PRS_CH_CTRL_SIGSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PRS_CH_CTRL */ 8597 #define PRS_CH_CTRL_SIGSEL_PRSCH10 (_PRS_CH_CTRL_SIGSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PRS_CH_CTRL */ 8598 #define PRS_CH_CTRL_SIGSEL_PRSCH18 (_PRS_CH_CTRL_SIGSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PRS_CH_CTRL */ 8599 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ 8600 #define PRS_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_CH_CTRL_SIGSEL_RTCCCCV1 << 0) /**< Shifted mode RTCCCCV1 for PRS_CH_CTRL */ 8601 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ 8602 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ 8603 #define PRS_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_CH_CTRL_SIGSEL_PCNT0DIR << 0) /**< Shifted mode PCNT0DIR for PRS_CH_CTRL */ 8604 #define PRS_CH_CTRL_SIGSEL_PCNT1DIR (_PRS_CH_CTRL_SIGSEL_PCNT1DIR << 0) /**< Shifted mode PCNT1DIR for PRS_CH_CTRL */ 8605 #define PRS_CH_CTRL_SIGSEL_PCNT2DIR (_PRS_CH_CTRL_SIGSEL_PCNT2DIR << 0) /**< Shifted mode PCNT2DIR for PRS_CH_CTRL */ 8606 #define PRS_CH_CTRL_SIGSEL_VDAC0OPA0 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA0 << 0) /**< Shifted mode VDAC0OPA0 for PRS_CH_CTRL */ 8607 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ 8608 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ 8609 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ 8610 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ 8611 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ 8612 #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ 8613 #define PRS_CH_CTRL_SIGSEL_USART3RXDATAV (_PRS_CH_CTRL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for PRS_CH_CTRL */ 8614 #define PRS_CH_CTRL_SIGSEL_USART4RXDATAV (_PRS_CH_CTRL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for PRS_CH_CTRL */ 8615 #define PRS_CH_CTRL_SIGSEL_USART5RXDATAV (_PRS_CH_CTRL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for PRS_CH_CTRL */ 8616 #define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ 8617 #define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ 8618 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ 8619 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ 8620 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ 8621 #define PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF (_PRS_CH_CTRL_SIGSEL_CM4ICACHEPCMISSESOF << 0) /**< Shifted mode CM4ICACHEPCMISSESOF for PRS_CH_CTRL */ 8622 #define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ 8623 #define PRS_CH_CTRL_SIGSEL_WTIMER0CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for PRS_CH_CTRL */ 8624 #define PRS_CH_CTRL_SIGSEL_WTIMER1CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for PRS_CH_CTRL */ 8625 #define PRS_CH_CTRL_SIGSEL_WTIMER2CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for PRS_CH_CTRL */ 8626 #define PRS_CH_CTRL_SIGSEL_WTIMER3CC0 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for PRS_CH_CTRL */ 8627 #define PRS_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_CH_CTRL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for PRS_CH_CTRL */ 8628 #define PRS_CH_CTRL_SIGSEL_TIMER5CC0 (_PRS_CH_CTRL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for PRS_CH_CTRL */ 8629 #define PRS_CH_CTRL_SIGSEL_TIMER6CC0 (_PRS_CH_CTRL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for PRS_CH_CTRL */ 8630 #define PRS_CH_CTRL_SIGSEL_PRSCH3 (_PRS_CH_CTRL_SIGSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PRS_CH_CTRL */ 8631 #define PRS_CH_CTRL_SIGSEL_PRSCH11 (_PRS_CH_CTRL_SIGSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PRS_CH_CTRL */ 8632 #define PRS_CH_CTRL_SIGSEL_PRSCH19 (_PRS_CH_CTRL_SIGSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PRS_CH_CTRL */ 8633 #define PRS_CH_CTRL_SIGSEL_RTCCOMP2 (_PRS_CH_CTRL_SIGSEL_RTCCOMP2 << 0) /**< Shifted mode RTCCOMP2 for PRS_CH_CTRL */ 8634 #define PRS_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_CH_CTRL_SIGSEL_RTCCCCV2 << 0) /**< Shifted mode RTCCCCV2 for PRS_CH_CTRL */ 8635 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ 8636 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ 8637 #define PRS_CH_CTRL_SIGSEL_VDAC0OPA1 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA1 << 0) /**< Shifted mode VDAC0OPA1 for PRS_CH_CTRL */ 8638 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ 8639 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ 8640 #define PRS_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) /**< Shifted mode LESENSEDECCMP for PRS_CH_CTRL */ 8641 #define PRS_CH_CTRL_SIGSEL_USART0RTS (_PRS_CH_CTRL_SIGSEL_USART0RTS << 0) /**< Shifted mode USART0RTS for PRS_CH_CTRL */ 8642 #define PRS_CH_CTRL_SIGSEL_USART1RTS (_PRS_CH_CTRL_SIGSEL_USART1RTS << 0) /**< Shifted mode USART1RTS for PRS_CH_CTRL */ 8643 #define PRS_CH_CTRL_SIGSEL_USART2RTS (_PRS_CH_CTRL_SIGSEL_USART2RTS << 0) /**< Shifted mode USART2RTS for PRS_CH_CTRL */ 8644 #define PRS_CH_CTRL_SIGSEL_USART3RTS (_PRS_CH_CTRL_SIGSEL_USART3RTS << 0) /**< Shifted mode USART3RTS for PRS_CH_CTRL */ 8645 #define PRS_CH_CTRL_SIGSEL_USART4RTS (_PRS_CH_CTRL_SIGSEL_USART4RTS << 0) /**< Shifted mode USART4RTS for PRS_CH_CTRL */ 8646 #define PRS_CH_CTRL_SIGSEL_USART5RTS (_PRS_CH_CTRL_SIGSEL_USART5RTS << 0) /**< Shifted mode USART5RTS for PRS_CH_CTRL */ 8647 #define PRS_CH_CTRL_SIGSEL_UART0RTS (_PRS_CH_CTRL_SIGSEL_UART0RTS << 0) /**< Shifted mode UART0RTS for PRS_CH_CTRL */ 8648 #define PRS_CH_CTRL_SIGSEL_UART1RTS (_PRS_CH_CTRL_SIGSEL_UART1RTS << 0) /**< Shifted mode UART1RTS for PRS_CH_CTRL */ 8649 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ 8650 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ 8651 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ 8652 #define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ 8653 #define PRS_CH_CTRL_SIGSEL_WTIMER0CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for PRS_CH_CTRL */ 8654 #define PRS_CH_CTRL_SIGSEL_WTIMER1CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for PRS_CH_CTRL */ 8655 #define PRS_CH_CTRL_SIGSEL_WTIMER2CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for PRS_CH_CTRL */ 8656 #define PRS_CH_CTRL_SIGSEL_WTIMER3CC1 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for PRS_CH_CTRL */ 8657 #define PRS_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_CH_CTRL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for PRS_CH_CTRL */ 8658 #define PRS_CH_CTRL_SIGSEL_TIMER5CC1 (_PRS_CH_CTRL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for PRS_CH_CTRL */ 8659 #define PRS_CH_CTRL_SIGSEL_TIMER6CC1 (_PRS_CH_CTRL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for PRS_CH_CTRL */ 8660 #define PRS_CH_CTRL_SIGSEL_PRSCH4 (_PRS_CH_CTRL_SIGSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PRS_CH_CTRL */ 8661 #define PRS_CH_CTRL_SIGSEL_PRSCH12 (_PRS_CH_CTRL_SIGSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PRS_CH_CTRL */ 8662 #define PRS_CH_CTRL_SIGSEL_PRSCH20 (_PRS_CH_CTRL_SIGSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PRS_CH_CTRL */ 8663 #define PRS_CH_CTRL_SIGSEL_RTCCOMP3 (_PRS_CH_CTRL_SIGSEL_RTCCOMP3 << 0) /**< Shifted mode RTCCOMP3 for PRS_CH_CTRL */ 8664 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ 8665 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ 8666 #define PRS_CH_CTRL_SIGSEL_VDAC0OPA2 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA2 << 0) /**< Shifted mode VDAC0OPA2 for PRS_CH_CTRL */ 8667 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ 8668 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ 8669 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ 8670 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ 8671 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ 8672 #define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ 8673 #define PRS_CH_CTRL_SIGSEL_WTIMER0CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for PRS_CH_CTRL */ 8674 #define PRS_CH_CTRL_SIGSEL_WTIMER1CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for PRS_CH_CTRL */ 8675 #define PRS_CH_CTRL_SIGSEL_WTIMER2CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for PRS_CH_CTRL */ 8676 #define PRS_CH_CTRL_SIGSEL_WTIMER3CC2 (_PRS_CH_CTRL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for PRS_CH_CTRL */ 8677 #define PRS_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_CH_CTRL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for PRS_CH_CTRL */ 8678 #define PRS_CH_CTRL_SIGSEL_TIMER5CC2 (_PRS_CH_CTRL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for PRS_CH_CTRL */ 8679 #define PRS_CH_CTRL_SIGSEL_TIMER6CC2 (_PRS_CH_CTRL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for PRS_CH_CTRL */ 8680 #define PRS_CH_CTRL_SIGSEL_PRSCH5 (_PRS_CH_CTRL_SIGSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PRS_CH_CTRL */ 8681 #define PRS_CH_CTRL_SIGSEL_PRSCH13 (_PRS_CH_CTRL_SIGSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PRS_CH_CTRL */ 8682 #define PRS_CH_CTRL_SIGSEL_PRSCH21 (_PRS_CH_CTRL_SIGSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PRS_CH_CTRL */ 8683 #define PRS_CH_CTRL_SIGSEL_RTCCOMP4 (_PRS_CH_CTRL_SIGSEL_RTCCOMP4 << 0) /**< Shifted mode RTCCOMP4 for PRS_CH_CTRL */ 8684 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ 8685 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ 8686 #define PRS_CH_CTRL_SIGSEL_VDAC0OPA3 (_PRS_CH_CTRL_SIGSEL_VDAC0OPA3 << 0) /**< Shifted mode VDAC0OPA3 for PRS_CH_CTRL */ 8687 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ 8688 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ 8689 #define PRS_CH_CTRL_SIGSEL_USART0TX (_PRS_CH_CTRL_SIGSEL_USART0TX << 0) /**< Shifted mode USART0TX for PRS_CH_CTRL */ 8690 #define PRS_CH_CTRL_SIGSEL_USART1TX (_PRS_CH_CTRL_SIGSEL_USART1TX << 0) /**< Shifted mode USART1TX for PRS_CH_CTRL */ 8691 #define PRS_CH_CTRL_SIGSEL_USART2TX (_PRS_CH_CTRL_SIGSEL_USART2TX << 0) /**< Shifted mode USART2TX for PRS_CH_CTRL */ 8692 #define PRS_CH_CTRL_SIGSEL_USART3TX (_PRS_CH_CTRL_SIGSEL_USART3TX << 0) /**< Shifted mode USART3TX for PRS_CH_CTRL */ 8693 #define PRS_CH_CTRL_SIGSEL_USART4TX (_PRS_CH_CTRL_SIGSEL_USART4TX << 0) /**< Shifted mode USART4TX for PRS_CH_CTRL */ 8694 #define PRS_CH_CTRL_SIGSEL_USART5TX (_PRS_CH_CTRL_SIGSEL_USART5TX << 0) /**< Shifted mode USART5TX for PRS_CH_CTRL */ 8695 #define PRS_CH_CTRL_SIGSEL_UART0TX (_PRS_CH_CTRL_SIGSEL_UART0TX << 0) /**< Shifted mode UART0TX for PRS_CH_CTRL */ 8696 #define PRS_CH_CTRL_SIGSEL_UART1TX (_PRS_CH_CTRL_SIGSEL_UART1TX << 0) /**< Shifted mode UART1TX for PRS_CH_CTRL */ 8697 #define PRS_CH_CTRL_SIGSEL_TIMER1CC3 (_PRS_CH_CTRL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for PRS_CH_CTRL */ 8698 #define PRS_CH_CTRL_SIGSEL_WTIMER1CC3 (_PRS_CH_CTRL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for PRS_CH_CTRL */ 8699 #define PRS_CH_CTRL_SIGSEL_PRSCH6 (_PRS_CH_CTRL_SIGSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PRS_CH_CTRL */ 8700 #define PRS_CH_CTRL_SIGSEL_PRSCH14 (_PRS_CH_CTRL_SIGSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PRS_CH_CTRL */ 8701 #define PRS_CH_CTRL_SIGSEL_PRSCH22 (_PRS_CH_CTRL_SIGSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PRS_CH_CTRL */ 8702 #define PRS_CH_CTRL_SIGSEL_RTCCOMP5 (_PRS_CH_CTRL_SIGSEL_RTCCOMP5 << 0) /**< Shifted mode RTCCOMP5 for PRS_CH_CTRL */ 8703 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ 8704 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ 8705 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ 8706 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ 8707 #define PRS_CH_CTRL_SIGSEL_USART0CS (_PRS_CH_CTRL_SIGSEL_USART0CS << 0) /**< Shifted mode USART0CS for PRS_CH_CTRL */ 8708 #define PRS_CH_CTRL_SIGSEL_USART1CS (_PRS_CH_CTRL_SIGSEL_USART1CS << 0) /**< Shifted mode USART1CS for PRS_CH_CTRL */ 8709 #define PRS_CH_CTRL_SIGSEL_USART2CS (_PRS_CH_CTRL_SIGSEL_USART2CS << 0) /**< Shifted mode USART2CS for PRS_CH_CTRL */ 8710 #define PRS_CH_CTRL_SIGSEL_USART3CS (_PRS_CH_CTRL_SIGSEL_USART3CS << 0) /**< Shifted mode USART3CS for PRS_CH_CTRL */ 8711 #define PRS_CH_CTRL_SIGSEL_USART4CS (_PRS_CH_CTRL_SIGSEL_USART4CS << 0) /**< Shifted mode USART4CS for PRS_CH_CTRL */ 8712 #define PRS_CH_CTRL_SIGSEL_USART5CS (_PRS_CH_CTRL_SIGSEL_USART5CS << 0) /**< Shifted mode USART5CS for PRS_CH_CTRL */ 8713 #define PRS_CH_CTRL_SIGSEL_UART0CS (_PRS_CH_CTRL_SIGSEL_UART0CS << 0) /**< Shifted mode UART0CS for PRS_CH_CTRL */ 8714 #define PRS_CH_CTRL_SIGSEL_UART1CS (_PRS_CH_CTRL_SIGSEL_UART1CS << 0) /**< Shifted mode UART1CS for PRS_CH_CTRL */ 8715 #define PRS_CH_CTRL_SIGSEL_PRSCH7 (_PRS_CH_CTRL_SIGSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PRS_CH_CTRL */ 8716 #define PRS_CH_CTRL_SIGSEL_PRSCH15 (_PRS_CH_CTRL_SIGSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PRS_CH_CTRL */ 8717 #define PRS_CH_CTRL_SIGSEL_PRSCH23 (_PRS_CH_CTRL_SIGSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PRS_CH_CTRL */ 8718 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ 8719 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ 8720 #define PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 (_PRS_CH_CTRL_SIGSEL_CMUCLKOUT2 << 0) /**< Shifted mode CMUCLKOUT2 for PRS_CH_CTRL */ 8721 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ 8722 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ 8723 #define _PRS_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ 8724 #define _PRS_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ 8725 #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ 8726 #define _PRS_CH_CTRL_SOURCESEL_PRSL 0x00000001UL /**< Mode PRSL for PRS_CH_CTRL */ 8727 #define _PRS_CH_CTRL_SOURCESEL_PRS 0x00000002UL /**< Mode PRS for PRS_CH_CTRL */ 8728 #define _PRS_CH_CTRL_SOURCESEL_PRSH 0x00000003UL /**< Mode PRSH for PRS_CH_CTRL */ 8729 #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000004UL /**< Mode ACMP0 for PRS_CH_CTRL */ 8730 #define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000005UL /**< Mode ACMP1 for PRS_CH_CTRL */ 8731 #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000006UL /**< Mode ADC0 for PRS_CH_CTRL */ 8732 #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000007UL /**< Mode RTC for PRS_CH_CTRL */ 8733 #define _PRS_CH_CTRL_SOURCESEL_RTCC 0x00000008UL /**< Mode RTCC for PRS_CH_CTRL */ 8734 #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000009UL /**< Mode GPIOL for PRS_CH_CTRL */ 8735 #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x0000000AUL /**< Mode GPIOH for PRS_CH_CTRL */ 8736 #define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x0000000BUL /**< Mode LETIMER0 for PRS_CH_CTRL */ 8737 #define _PRS_CH_CTRL_SOURCESEL_LETIMER1 0x0000000CUL /**< Mode LETIMER1 for PRS_CH_CTRL */ 8738 #define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x0000000DUL /**< Mode PCNT0 for PRS_CH_CTRL */ 8739 #define _PRS_CH_CTRL_SOURCESEL_PCNT1 0x0000000EUL /**< Mode PCNT1 for PRS_CH_CTRL */ 8740 #define _PRS_CH_CTRL_SOURCESEL_PCNT2 0x0000000FUL /**< Mode PCNT2 for PRS_CH_CTRL */ 8741 #define _PRS_CH_CTRL_SOURCESEL_CRYOTIMER 0x00000010UL /**< Mode CRYOTIMER for PRS_CH_CTRL */ 8742 #define _PRS_CH_CTRL_SOURCESEL_CMU 0x00000011UL /**< Mode CMU for PRS_CH_CTRL */ 8743 #define _PRS_CH_CTRL_SOURCESEL_VDAC0 0x00000017UL /**< Mode VDAC0 for PRS_CH_CTRL */ 8744 #define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000018UL /**< Mode LESENSEL for PRS_CH_CTRL */ 8745 #define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x00000019UL /**< Mode LESENSEH for PRS_CH_CTRL */ 8746 #define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000001AUL /**< Mode LESENSED for PRS_CH_CTRL */ 8747 #define _PRS_CH_CTRL_SOURCESEL_LESENSE 0x0000001BUL /**< Mode LESENSE for PRS_CH_CTRL */ 8748 #define _PRS_CH_CTRL_SOURCESEL_ACMP2 0x0000001CUL /**< Mode ACMP2 for PRS_CH_CTRL */ 8749 #define _PRS_CH_CTRL_SOURCESEL_ACMP3 0x0000001DUL /**< Mode ACMP3 for PRS_CH_CTRL */ 8750 #define _PRS_CH_CTRL_SOURCESEL_ADC1 0x0000001EUL /**< Mode ADC1 for PRS_CH_CTRL */ 8751 #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000030UL /**< Mode USART0 for PRS_CH_CTRL */ 8752 #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000031UL /**< Mode USART1 for PRS_CH_CTRL */ 8753 #define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000032UL /**< Mode USART2 for PRS_CH_CTRL */ 8754 #define _PRS_CH_CTRL_SOURCESEL_USART3 0x00000033UL /**< Mode USART3 for PRS_CH_CTRL */ 8755 #define _PRS_CH_CTRL_SOURCESEL_USART4 0x00000034UL /**< Mode USART4 for PRS_CH_CTRL */ 8756 #define _PRS_CH_CTRL_SOURCESEL_USART5 0x00000035UL /**< Mode USART5 for PRS_CH_CTRL */ 8757 #define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000036UL /**< Mode UART0 for PRS_CH_CTRL */ 8758 #define _PRS_CH_CTRL_SOURCESEL_UART1 0x00000037UL /**< Mode UART1 for PRS_CH_CTRL */ 8759 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000003CUL /**< Mode TIMER0 for PRS_CH_CTRL */ 8760 #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000003DUL /**< Mode TIMER1 for PRS_CH_CTRL */ 8761 #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000003EUL /**< Mode TIMER2 for PRS_CH_CTRL */ 8762 #define _PRS_CH_CTRL_SOURCESEL_CM4 0x00000043UL /**< Mode CM4 for PRS_CH_CTRL */ 8763 #define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x00000050UL /**< Mode TIMER3 for PRS_CH_CTRL */ 8764 #define _PRS_CH_CTRL_SOURCESEL_WTIMER0 0x00000052UL /**< Mode WTIMER0 for PRS_CH_CTRL */ 8765 #define _PRS_CH_CTRL_SOURCESEL_WTIMER1 0x00000053UL /**< Mode WTIMER1 for PRS_CH_CTRL */ 8766 #define _PRS_CH_CTRL_SOURCESEL_WTIMER2 0x00000054UL /**< Mode WTIMER2 for PRS_CH_CTRL */ 8767 #define _PRS_CH_CTRL_SOURCESEL_WTIMER3 0x00000055UL /**< Mode WTIMER3 for PRS_CH_CTRL */ 8768 #define _PRS_CH_CTRL_SOURCESEL_TIMER4 0x00000062UL /**< Mode TIMER4 for PRS_CH_CTRL */ 8769 #define _PRS_CH_CTRL_SOURCESEL_TIMER5 0x00000063UL /**< Mode TIMER5 for PRS_CH_CTRL */ 8770 #define _PRS_CH_CTRL_SOURCESEL_TIMER6 0x00000064UL /**< Mode TIMER6 for PRS_CH_CTRL */ 8771 #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 8) /**< Shifted mode NONE for PRS_CH_CTRL */ 8772 #define PRS_CH_CTRL_SOURCESEL_PRSL (_PRS_CH_CTRL_SOURCESEL_PRSL << 8) /**< Shifted mode PRSL for PRS_CH_CTRL */ 8773 #define PRS_CH_CTRL_SOURCESEL_PRS (_PRS_CH_CTRL_SOURCESEL_PRS << 8) /**< Shifted mode PRS for PRS_CH_CTRL */ 8774 #define PRS_CH_CTRL_SOURCESEL_PRSH (_PRS_CH_CTRL_SOURCESEL_PRSH << 8) /**< Shifted mode PRSH for PRS_CH_CTRL */ 8775 #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 8) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ 8776 #define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 8) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ 8777 #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 8) /**< Shifted mode ADC0 for PRS_CH_CTRL */ 8778 #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 8) /**< Shifted mode RTC for PRS_CH_CTRL */ 8779 #define PRS_CH_CTRL_SOURCESEL_RTCC (_PRS_CH_CTRL_SOURCESEL_RTCC << 8) /**< Shifted mode RTCC for PRS_CH_CTRL */ 8780 #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 8) /**< Shifted mode GPIOL for PRS_CH_CTRL */ 8781 #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 8) /**< Shifted mode GPIOH for PRS_CH_CTRL */ 8782 #define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 8) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ 8783 #define PRS_CH_CTRL_SOURCESEL_LETIMER1 (_PRS_CH_CTRL_SOURCESEL_LETIMER1 << 8) /**< Shifted mode LETIMER1 for PRS_CH_CTRL */ 8784 #define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 8) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ 8785 #define PRS_CH_CTRL_SOURCESEL_PCNT1 (_PRS_CH_CTRL_SOURCESEL_PCNT1 << 8) /**< Shifted mode PCNT1 for PRS_CH_CTRL */ 8786 #define PRS_CH_CTRL_SOURCESEL_PCNT2 (_PRS_CH_CTRL_SOURCESEL_PCNT2 << 8) /**< Shifted mode PCNT2 for PRS_CH_CTRL */ 8787 #define PRS_CH_CTRL_SOURCESEL_CRYOTIMER (_PRS_CH_CTRL_SOURCESEL_CRYOTIMER << 8) /**< Shifted mode CRYOTIMER for PRS_CH_CTRL */ 8788 #define PRS_CH_CTRL_SOURCESEL_CMU (_PRS_CH_CTRL_SOURCESEL_CMU << 8) /**< Shifted mode CMU for PRS_CH_CTRL */ 8789 #define PRS_CH_CTRL_SOURCESEL_VDAC0 (_PRS_CH_CTRL_SOURCESEL_VDAC0 << 8) /**< Shifted mode VDAC0 for PRS_CH_CTRL */ 8790 #define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 8) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ 8791 #define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 8) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ 8792 #define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 8) /**< Shifted mode LESENSED for PRS_CH_CTRL */ 8793 #define PRS_CH_CTRL_SOURCESEL_LESENSE (_PRS_CH_CTRL_SOURCESEL_LESENSE << 8) /**< Shifted mode LESENSE for PRS_CH_CTRL */ 8794 #define PRS_CH_CTRL_SOURCESEL_ACMP2 (_PRS_CH_CTRL_SOURCESEL_ACMP2 << 8) /**< Shifted mode ACMP2 for PRS_CH_CTRL */ 8795 #define PRS_CH_CTRL_SOURCESEL_ACMP3 (_PRS_CH_CTRL_SOURCESEL_ACMP3 << 8) /**< Shifted mode ACMP3 for PRS_CH_CTRL */ 8796 #define PRS_CH_CTRL_SOURCESEL_ADC1 (_PRS_CH_CTRL_SOURCESEL_ADC1 << 8) /**< Shifted mode ADC1 for PRS_CH_CTRL */ 8797 #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 8) /**< Shifted mode USART0 for PRS_CH_CTRL */ 8798 #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 8) /**< Shifted mode USART1 for PRS_CH_CTRL */ 8799 #define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 8) /**< Shifted mode USART2 for PRS_CH_CTRL */ 8800 #define PRS_CH_CTRL_SOURCESEL_USART3 (_PRS_CH_CTRL_SOURCESEL_USART3 << 8) /**< Shifted mode USART3 for PRS_CH_CTRL */ 8801 #define PRS_CH_CTRL_SOURCESEL_USART4 (_PRS_CH_CTRL_SOURCESEL_USART4 << 8) /**< Shifted mode USART4 for PRS_CH_CTRL */ 8802 #define PRS_CH_CTRL_SOURCESEL_USART5 (_PRS_CH_CTRL_SOURCESEL_USART5 << 8) /**< Shifted mode USART5 for PRS_CH_CTRL */ 8803 #define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 8) /**< Shifted mode UART0 for PRS_CH_CTRL */ 8804 #define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 8) /**< Shifted mode UART1 for PRS_CH_CTRL */ 8805 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 8) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ 8806 #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 8) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ 8807 #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 8) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ 8808 #define PRS_CH_CTRL_SOURCESEL_CM4 (_PRS_CH_CTRL_SOURCESEL_CM4 << 8) /**< Shifted mode CM4 for PRS_CH_CTRL */ 8809 #define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 8) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ 8810 #define PRS_CH_CTRL_SOURCESEL_WTIMER0 (_PRS_CH_CTRL_SOURCESEL_WTIMER0 << 8) /**< Shifted mode WTIMER0 for PRS_CH_CTRL */ 8811 #define PRS_CH_CTRL_SOURCESEL_WTIMER1 (_PRS_CH_CTRL_SOURCESEL_WTIMER1 << 8) /**< Shifted mode WTIMER1 for PRS_CH_CTRL */ 8812 #define PRS_CH_CTRL_SOURCESEL_WTIMER2 (_PRS_CH_CTRL_SOURCESEL_WTIMER2 << 8) /**< Shifted mode WTIMER2 for PRS_CH_CTRL */ 8813 #define PRS_CH_CTRL_SOURCESEL_WTIMER3 (_PRS_CH_CTRL_SOURCESEL_WTIMER3 << 8) /**< Shifted mode WTIMER3 for PRS_CH_CTRL */ 8814 #define PRS_CH_CTRL_SOURCESEL_TIMER4 (_PRS_CH_CTRL_SOURCESEL_TIMER4 << 8) /**< Shifted mode TIMER4 for PRS_CH_CTRL */ 8815 #define PRS_CH_CTRL_SOURCESEL_TIMER5 (_PRS_CH_CTRL_SOURCESEL_TIMER5 << 8) /**< Shifted mode TIMER5 for PRS_CH_CTRL */ 8816 #define PRS_CH_CTRL_SOURCESEL_TIMER6 (_PRS_CH_CTRL_SOURCESEL_TIMER6 << 8) /**< Shifted mode TIMER6 for PRS_CH_CTRL */ 8817 #define _PRS_CH_CTRL_EDSEL_SHIFT 20 /**< Shift value for PRS_EDSEL */ 8818 #define _PRS_CH_CTRL_EDSEL_MASK 0x300000UL /**< Bit mask for PRS_EDSEL */ 8819 #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 8820 #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ 8821 #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ 8822 #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ 8823 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ 8824 #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 8825 #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 20) /**< Shifted mode OFF for PRS_CH_CTRL */ 8826 #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 20) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ 8827 #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 20) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ 8828 #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 20) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ 8829 #define PRS_CH_CTRL_STRETCH (0x1UL << 25) /**< Stretch Channel Output */ 8830 #define _PRS_CH_CTRL_STRETCH_SHIFT 25 /**< Shift value for PRS_STRETCH */ 8831 #define _PRS_CH_CTRL_STRETCH_MASK 0x2000000UL /**< Bit mask for PRS_STRETCH */ 8832 #define _PRS_CH_CTRL_STRETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 8833 #define PRS_CH_CTRL_STRETCH_DEFAULT (_PRS_CH_CTRL_STRETCH_DEFAULT << 25) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 8834 #define PRS_CH_CTRL_INV (0x1UL << 26) /**< Invert Channel */ 8835 #define _PRS_CH_CTRL_INV_SHIFT 26 /**< Shift value for PRS_INV */ 8836 #define _PRS_CH_CTRL_INV_MASK 0x4000000UL /**< Bit mask for PRS_INV */ 8837 #define _PRS_CH_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 8838 #define PRS_CH_CTRL_INV_DEFAULT (_PRS_CH_CTRL_INV_DEFAULT << 26) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 8839 #define PRS_CH_CTRL_ORPREV (0x1UL << 27) /**< Or Previous */ 8840 #define _PRS_CH_CTRL_ORPREV_SHIFT 27 /**< Shift value for PRS_ORPREV */ 8841 #define _PRS_CH_CTRL_ORPREV_MASK 0x8000000UL /**< Bit mask for PRS_ORPREV */ 8842 #define _PRS_CH_CTRL_ORPREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 8843 #define PRS_CH_CTRL_ORPREV_DEFAULT (_PRS_CH_CTRL_ORPREV_DEFAULT << 27) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 8844 #define PRS_CH_CTRL_ANDNEXT (0x1UL << 28) /**< And Next */ 8845 #define _PRS_CH_CTRL_ANDNEXT_SHIFT 28 /**< Shift value for PRS_ANDNEXT */ 8846 #define _PRS_CH_CTRL_ANDNEXT_MASK 0x10000000UL /**< Bit mask for PRS_ANDNEXT */ 8847 #define _PRS_CH_CTRL_ANDNEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 8848 #define PRS_CH_CTRL_ANDNEXT_DEFAULT (_PRS_CH_CTRL_ANDNEXT_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 8849 #define PRS_CH_CTRL_ASYNC (0x1UL << 30) /**< Asynchronous Reflex */ 8850 #define _PRS_CH_CTRL_ASYNC_SHIFT 30 /**< Shift value for PRS_ASYNC */ 8851 #define _PRS_CH_CTRL_ASYNC_MASK 0x40000000UL /**< Bit mask for PRS_ASYNC */ 8852 #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 8853 #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 30) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 8854 8855 /** @} */ 8856 /** @} End of group EFM32GG11B520F2048GQ100_PRS */ 8857 8858 /***************************************************************************//** 8859 * @addtogroup EFM32GG11B520F2048GQ100_SMU 8860 * @{ 8861 * @defgroup EFM32GG11B520F2048GQ100_SMU_BitFields SMU Bit Fields 8862 * @{ 8863 ******************************************************************************/ 8864 8865 /* Bit fields for SMU IF */ 8866 #define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ 8867 #define _SMU_IF_MASK 0x00000001UL /**< Mask for SMU_IF */ 8868 #define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ 8869 #define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ 8870 #define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ 8871 #define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ 8872 #define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ 8873 8874 /* Bit fields for SMU IFS */ 8875 #define _SMU_IFS_RESETVALUE 0x00000000UL /**< Default value for SMU_IFS */ 8876 #define _SMU_IFS_MASK 0x00000001UL /**< Mask for SMU_IFS */ 8877 #define SMU_IFS_PPUPRIV (0x1UL << 0) /**< Set PPUPRIV Interrupt Flag */ 8878 #define _SMU_IFS_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ 8879 #define _SMU_IFS_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ 8880 #define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFS */ 8881 #define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFS */ 8882 8883 /* Bit fields for SMU IFC */ 8884 #define _SMU_IFC_RESETVALUE 0x00000000UL /**< Default value for SMU_IFC */ 8885 #define _SMU_IFC_MASK 0x00000001UL /**< Mask for SMU_IFC */ 8886 #define SMU_IFC_PPUPRIV (0x1UL << 0) /**< Clear PPUPRIV Interrupt Flag */ 8887 #define _SMU_IFC_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ 8888 #define _SMU_IFC_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ 8889 #define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IFC */ 8890 #define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IFC */ 8891 8892 /* Bit fields for SMU IEN */ 8893 #define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ 8894 #define _SMU_IEN_MASK 0x00000001UL /**< Mask for SMU_IEN */ 8895 #define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPUPRIV Interrupt Enable */ 8896 #define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ 8897 #define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ 8898 #define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ 8899 #define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ 8900 8901 /* Bit fields for SMU PPUCTRL */ 8902 #define _SMU_PPUCTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUCTRL */ 8903 #define _SMU_PPUCTRL_MASK 0x00000001UL /**< Mask for SMU_PPUCTRL */ 8904 #define SMU_PPUCTRL_ENABLE (0x1UL << 0) /**< */ 8905 #define _SMU_PPUCTRL_ENABLE_SHIFT 0 /**< Shift value for SMU_ENABLE */ 8906 #define _SMU_PPUCTRL_ENABLE_MASK 0x1UL /**< Bit mask for SMU_ENABLE */ 8907 #define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUCTRL */ 8908 #define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUCTRL */ 8909 8910 /* Bit fields for SMU PPUPATD0 */ 8911 #define _SMU_PPUPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD0 */ 8912 #define _SMU_PPUPATD0_MASK 0xFFFEFFFFUL /**< Mask for SMU_PPUPATD0 */ 8913 #define SMU_PPUPATD0_ACMP0 (0x1UL << 0) /**< Analog Comparator 0 access control bit */ 8914 #define _SMU_PPUPATD0_ACMP0_SHIFT 0 /**< Shift value for SMU_ACMP0 */ 8915 #define _SMU_PPUPATD0_ACMP0_MASK 0x1UL /**< Bit mask for SMU_ACMP0 */ 8916 #define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8917 #define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8918 #define SMU_PPUPATD0_ACMP1 (0x1UL << 1) /**< Analog Comparator 1 access control bit */ 8919 #define _SMU_PPUPATD0_ACMP1_SHIFT 1 /**< Shift value for SMU_ACMP1 */ 8920 #define _SMU_PPUPATD0_ACMP1_MASK 0x2UL /**< Bit mask for SMU_ACMP1 */ 8921 #define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8922 #define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8923 #define SMU_PPUPATD0_ACMP2 (0x1UL << 2) /**< Analog Comparator 1 access control bit */ 8924 #define _SMU_PPUPATD0_ACMP2_SHIFT 2 /**< Shift value for SMU_ACMP2 */ 8925 #define _SMU_PPUPATD0_ACMP2_MASK 0x4UL /**< Bit mask for SMU_ACMP2 */ 8926 #define _SMU_PPUPATD0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8927 #define SMU_PPUPATD0_ACMP2_DEFAULT (_SMU_PPUPATD0_ACMP2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8928 #define SMU_PPUPATD0_ACMP3 (0x1UL << 3) /**< Analog Comparator 3 access control bit */ 8929 #define _SMU_PPUPATD0_ACMP3_SHIFT 3 /**< Shift value for SMU_ACMP3 */ 8930 #define _SMU_PPUPATD0_ACMP3_MASK 0x8UL /**< Bit mask for SMU_ACMP3 */ 8931 #define _SMU_PPUPATD0_ACMP3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8932 #define SMU_PPUPATD0_ACMP3_DEFAULT (_SMU_PPUPATD0_ACMP3_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8933 #define SMU_PPUPATD0_ADC0 (0x1UL << 4) /**< Analog to Digital Converter 0 access control bit */ 8934 #define _SMU_PPUPATD0_ADC0_SHIFT 4 /**< Shift value for SMU_ADC0 */ 8935 #define _SMU_PPUPATD0_ADC0_MASK 0x10UL /**< Bit mask for SMU_ADC0 */ 8936 #define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8937 #define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8938 #define SMU_PPUPATD0_ADC1 (0x1UL << 5) /**< Analog to Digital Converter 0 access control bit */ 8939 #define _SMU_PPUPATD0_ADC1_SHIFT 5 /**< Shift value for SMU_ADC1 */ 8940 #define _SMU_PPUPATD0_ADC1_MASK 0x20UL /**< Bit mask for SMU_ADC1 */ 8941 #define _SMU_PPUPATD0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8942 #define SMU_PPUPATD0_ADC1_DEFAULT (_SMU_PPUPATD0_ADC1_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8943 #define SMU_PPUPATD0_CAN0 (0x1UL << 6) /**< CAN 0 access control bit */ 8944 #define _SMU_PPUPATD0_CAN0_SHIFT 6 /**< Shift value for SMU_CAN0 */ 8945 #define _SMU_PPUPATD0_CAN0_MASK 0x40UL /**< Bit mask for SMU_CAN0 */ 8946 #define _SMU_PPUPATD0_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8947 #define SMU_PPUPATD0_CAN0_DEFAULT (_SMU_PPUPATD0_CAN0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8948 #define SMU_PPUPATD0_CAN1 (0x1UL << 7) /**< CAN 1 access control bit */ 8949 #define _SMU_PPUPATD0_CAN1_SHIFT 7 /**< Shift value for SMU_CAN1 */ 8950 #define _SMU_PPUPATD0_CAN1_MASK 0x80UL /**< Bit mask for SMU_CAN1 */ 8951 #define _SMU_PPUPATD0_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8952 #define SMU_PPUPATD0_CAN1_DEFAULT (_SMU_PPUPATD0_CAN1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8953 #define SMU_PPUPATD0_CMU (0x1UL << 8) /**< Clock Management Unit access control bit */ 8954 #define _SMU_PPUPATD0_CMU_SHIFT 8 /**< Shift value for SMU_CMU */ 8955 #define _SMU_PPUPATD0_CMU_MASK 0x100UL /**< Bit mask for SMU_CMU */ 8956 #define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8957 #define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8958 #define SMU_PPUPATD0_CRYOTIMER (0x1UL << 9) /**< CRYOTIMER access control bit */ 8959 #define _SMU_PPUPATD0_CRYOTIMER_SHIFT 9 /**< Shift value for SMU_CRYOTIMER */ 8960 #define _SMU_PPUPATD0_CRYOTIMER_MASK 0x200UL /**< Bit mask for SMU_CRYOTIMER */ 8961 #define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8962 #define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8963 #define SMU_PPUPATD0_CRYPTO0 (0x1UL << 10) /**< Advanced Encryption Standard Accelerator access control bit */ 8964 #define _SMU_PPUPATD0_CRYPTO0_SHIFT 10 /**< Shift value for SMU_CRYPTO0 */ 8965 #define _SMU_PPUPATD0_CRYPTO0_MASK 0x400UL /**< Bit mask for SMU_CRYPTO0 */ 8966 #define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8967 #define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8968 #define SMU_PPUPATD0_CSEN (0x1UL << 11) /**< Capacitive touch sense module access control bit */ 8969 #define _SMU_PPUPATD0_CSEN_SHIFT 11 /**< Shift value for SMU_CSEN */ 8970 #define _SMU_PPUPATD0_CSEN_MASK 0x800UL /**< Bit mask for SMU_CSEN */ 8971 #define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8972 #define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8973 #define SMU_PPUPATD0_VDAC0 (0x1UL << 12) /**< Digital to Analog Converter 0 access control bit */ 8974 #define _SMU_PPUPATD0_VDAC0_SHIFT 12 /**< Shift value for SMU_VDAC0 */ 8975 #define _SMU_PPUPATD0_VDAC0_MASK 0x1000UL /**< Bit mask for SMU_VDAC0 */ 8976 #define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8977 #define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8978 #define SMU_PPUPATD0_PRS (0x1UL << 13) /**< Peripheral Reflex System access control bit */ 8979 #define _SMU_PPUPATD0_PRS_SHIFT 13 /**< Shift value for SMU_PRS */ 8980 #define _SMU_PPUPATD0_PRS_MASK 0x2000UL /**< Bit mask for SMU_PRS */ 8981 #define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8982 #define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8983 #define SMU_PPUPATD0_EBI (0x1UL << 14) /**< External Bus Interface access control bit */ 8984 #define _SMU_PPUPATD0_EBI_SHIFT 14 /**< Shift value for SMU_EBI */ 8985 #define _SMU_PPUPATD0_EBI_MASK 0x4000UL /**< Bit mask for SMU_EBI */ 8986 #define _SMU_PPUPATD0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8987 #define SMU_PPUPATD0_EBI_DEFAULT (_SMU_PPUPATD0_EBI_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8988 #define SMU_PPUPATD0_EMU (0x1UL << 15) /**< Energy Management Unit access control bit */ 8989 #define _SMU_PPUPATD0_EMU_SHIFT 15 /**< Shift value for SMU_EMU */ 8990 #define _SMU_PPUPATD0_EMU_MASK 0x8000UL /**< Bit mask for SMU_EMU */ 8991 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8992 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8993 #define SMU_PPUPATD0_FPUEH (0x1UL << 17) /**< FPU Exception Handler access control bit */ 8994 #define _SMU_PPUPATD0_FPUEH_SHIFT 17 /**< Shift value for SMU_FPUEH */ 8995 #define _SMU_PPUPATD0_FPUEH_MASK 0x20000UL /**< Bit mask for SMU_FPUEH */ 8996 #define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 8997 #define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 8998 #define SMU_PPUPATD0_GPCRC (0x1UL << 18) /**< General Purpose CRC access control bit */ 8999 #define _SMU_PPUPATD0_GPCRC_SHIFT 18 /**< Shift value for SMU_GPCRC */ 9000 #define _SMU_PPUPATD0_GPCRC_MASK 0x40000UL /**< Bit mask for SMU_GPCRC */ 9001 #define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 9002 #define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 9003 #define SMU_PPUPATD0_GPIO (0x1UL << 19) /**< General purpose Input/Output access control bit */ 9004 #define _SMU_PPUPATD0_GPIO_SHIFT 19 /**< Shift value for SMU_GPIO */ 9005 #define _SMU_PPUPATD0_GPIO_MASK 0x80000UL /**< Bit mask for SMU_GPIO */ 9006 #define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 9007 #define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 9008 #define SMU_PPUPATD0_I2C0 (0x1UL << 20) /**< I2C 0 access control bit */ 9009 #define _SMU_PPUPATD0_I2C0_SHIFT 20 /**< Shift value for SMU_I2C0 */ 9010 #define _SMU_PPUPATD0_I2C0_MASK 0x100000UL /**< Bit mask for SMU_I2C0 */ 9011 #define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 9012 #define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 9013 #define SMU_PPUPATD0_I2C1 (0x1UL << 21) /**< I2C 1 access control bit */ 9014 #define _SMU_PPUPATD0_I2C1_SHIFT 21 /**< Shift value for SMU_I2C1 */ 9015 #define _SMU_PPUPATD0_I2C1_MASK 0x200000UL /**< Bit mask for SMU_I2C1 */ 9016 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 9017 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 9018 #define SMU_PPUPATD0_I2C2 (0x1UL << 22) /**< I2C 2 access control bit */ 9019 #define _SMU_PPUPATD0_I2C2_SHIFT 22 /**< Shift value for SMU_I2C2 */ 9020 #define _SMU_PPUPATD0_I2C2_MASK 0x400000UL /**< Bit mask for SMU_I2C2 */ 9021 #define _SMU_PPUPATD0_I2C2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 9022 #define SMU_PPUPATD0_I2C2_DEFAULT (_SMU_PPUPATD0_I2C2_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 9023 #define SMU_PPUPATD0_IDAC0 (0x1UL << 23) /**< Current Digital to Analog Converter 0 access control bit */ 9024 #define _SMU_PPUPATD0_IDAC0_SHIFT 23 /**< Shift value for SMU_IDAC0 */ 9025 #define _SMU_PPUPATD0_IDAC0_MASK 0x800000UL /**< Bit mask for SMU_IDAC0 */ 9026 #define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 9027 #define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 9028 #define SMU_PPUPATD0_MSC (0x1UL << 24) /**< Memory System Controller access control bit */ 9029 #define _SMU_PPUPATD0_MSC_SHIFT 24 /**< Shift value for SMU_MSC */ 9030 #define _SMU_PPUPATD0_MSC_MASK 0x1000000UL /**< Bit mask for SMU_MSC */ 9031 #define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 9032 #define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 9033 #define SMU_PPUPATD0_LCD (0x1UL << 25) /**< Liquid Crystal Display Controller access control bit */ 9034 #define _SMU_PPUPATD0_LCD_SHIFT 25 /**< Shift value for SMU_LCD */ 9035 #define _SMU_PPUPATD0_LCD_MASK 0x2000000UL /**< Bit mask for SMU_LCD */ 9036 #define _SMU_PPUPATD0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 9037 #define SMU_PPUPATD0_LCD_DEFAULT (_SMU_PPUPATD0_LCD_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 9038 #define SMU_PPUPATD0_LDMA (0x1UL << 26) /**< Linked Direct Memory Access Controller access control bit */ 9039 #define _SMU_PPUPATD0_LDMA_SHIFT 26 /**< Shift value for SMU_LDMA */ 9040 #define _SMU_PPUPATD0_LDMA_MASK 0x4000000UL /**< Bit mask for SMU_LDMA */ 9041 #define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 9042 #define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 9043 #define SMU_PPUPATD0_LESENSE (0x1UL << 27) /**< Low Energy Sensor Interface access control bit */ 9044 #define _SMU_PPUPATD0_LESENSE_SHIFT 27 /**< Shift value for SMU_LESENSE */ 9045 #define _SMU_PPUPATD0_LESENSE_MASK 0x8000000UL /**< Bit mask for SMU_LESENSE */ 9046 #define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 9047 #define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 9048 #define SMU_PPUPATD0_LETIMER0 (0x1UL << 28) /**< Low Energy Timer 0 access control bit */ 9049 #define _SMU_PPUPATD0_LETIMER0_SHIFT 28 /**< Shift value for SMU_LETIMER0 */ 9050 #define _SMU_PPUPATD0_LETIMER0_MASK 0x10000000UL /**< Bit mask for SMU_LETIMER0 */ 9051 #define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 9052 #define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 9053 #define SMU_PPUPATD0_LETIMER1 (0x1UL << 29) /**< Low Energy Timer 1 access control bit */ 9054 #define _SMU_PPUPATD0_LETIMER1_SHIFT 29 /**< Shift value for SMU_LETIMER1 */ 9055 #define _SMU_PPUPATD0_LETIMER1_MASK 0x20000000UL /**< Bit mask for SMU_LETIMER1 */ 9056 #define _SMU_PPUPATD0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 9057 #define SMU_PPUPATD0_LETIMER1_DEFAULT (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 9058 #define SMU_PPUPATD0_LEUART0 (0x1UL << 30) /**< Low Energy UART 0 access control bit */ 9059 #define _SMU_PPUPATD0_LEUART0_SHIFT 30 /**< Shift value for SMU_LEUART0 */ 9060 #define _SMU_PPUPATD0_LEUART0_MASK 0x40000000UL /**< Bit mask for SMU_LEUART0 */ 9061 #define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 9062 #define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 9063 #define SMU_PPUPATD0_LEUART1 (0x1UL << 31) /**< Low Energy UART 1 access control bit */ 9064 #define _SMU_PPUPATD0_LEUART1_SHIFT 31 /**< Shift value for SMU_LEUART1 */ 9065 #define _SMU_PPUPATD0_LEUART1_MASK 0x80000000UL /**< Bit mask for SMU_LEUART1 */ 9066 #define _SMU_PPUPATD0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ 9067 #define SMU_PPUPATD0_LEUART1_DEFAULT (_SMU_PPUPATD0_LEUART1_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ 9068 9069 /* Bit fields for SMU PPUPATD1 */ 9070 #define _SMU_PPUPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD1 */ 9071 #define _SMU_PPUPATD1_MASK 0xFDFFFF77UL /**< Mask for SMU_PPUPATD1 */ 9072 #define SMU_PPUPATD1_PCNT0 (0x1UL << 0) /**< Pulse Counter 0 access control bit */ 9073 #define _SMU_PPUPATD1_PCNT0_SHIFT 0 /**< Shift value for SMU_PCNT0 */ 9074 #define _SMU_PPUPATD1_PCNT0_MASK 0x1UL /**< Bit mask for SMU_PCNT0 */ 9075 #define _SMU_PPUPATD1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9076 #define SMU_PPUPATD1_PCNT0_DEFAULT (_SMU_PPUPATD1_PCNT0_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9077 #define SMU_PPUPATD1_PCNT1 (0x1UL << 1) /**< Pulse Counter 1 access control bit */ 9078 #define _SMU_PPUPATD1_PCNT1_SHIFT 1 /**< Shift value for SMU_PCNT1 */ 9079 #define _SMU_PPUPATD1_PCNT1_MASK 0x2UL /**< Bit mask for SMU_PCNT1 */ 9080 #define _SMU_PPUPATD1_PCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9081 #define SMU_PPUPATD1_PCNT1_DEFAULT (_SMU_PPUPATD1_PCNT1_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9082 #define SMU_PPUPATD1_PCNT2 (0x1UL << 2) /**< Pulse Counter 2 access control bit */ 9083 #define _SMU_PPUPATD1_PCNT2_SHIFT 2 /**< Shift value for SMU_PCNT2 */ 9084 #define _SMU_PPUPATD1_PCNT2_MASK 0x4UL /**< Bit mask for SMU_PCNT2 */ 9085 #define _SMU_PPUPATD1_PCNT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9086 #define SMU_PPUPATD1_PCNT2_DEFAULT (_SMU_PPUPATD1_PCNT2_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9087 #define SMU_PPUPATD1_RMU (0x1UL << 4) /**< Reset Management Unit access control bit */ 9088 #define _SMU_PPUPATD1_RMU_SHIFT 4 /**< Shift value for SMU_RMU */ 9089 #define _SMU_PPUPATD1_RMU_MASK 0x10UL /**< Bit mask for SMU_RMU */ 9090 #define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9091 #define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9092 #define SMU_PPUPATD1_RTC (0x1UL << 5) /**< Real-Time Counter access control bit */ 9093 #define _SMU_PPUPATD1_RTC_SHIFT 5 /**< Shift value for SMU_RTC */ 9094 #define _SMU_PPUPATD1_RTC_MASK 0x20UL /**< Bit mask for SMU_RTC */ 9095 #define _SMU_PPUPATD1_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9096 #define SMU_PPUPATD1_RTC_DEFAULT (_SMU_PPUPATD1_RTC_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9097 #define SMU_PPUPATD1_RTCC (0x1UL << 6) /**< Real-Time Counter and Calendar access control bit */ 9098 #define _SMU_PPUPATD1_RTCC_SHIFT 6 /**< Shift value for SMU_RTCC */ 9099 #define _SMU_PPUPATD1_RTCC_MASK 0x40UL /**< Bit mask for SMU_RTCC */ 9100 #define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9101 #define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9102 #define SMU_PPUPATD1_SMU (0x1UL << 8) /**< Security Management Unit access control bit */ 9103 #define _SMU_PPUPATD1_SMU_SHIFT 8 /**< Shift value for SMU_SMU */ 9104 #define _SMU_PPUPATD1_SMU_MASK 0x100UL /**< Bit mask for SMU_SMU */ 9105 #define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9106 #define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9107 #define SMU_PPUPATD1_TIMER0 (0x1UL << 9) /**< Timer 0 access control bit */ 9108 #define _SMU_PPUPATD1_TIMER0_SHIFT 9 /**< Shift value for SMU_TIMER0 */ 9109 #define _SMU_PPUPATD1_TIMER0_MASK 0x200UL /**< Bit mask for SMU_TIMER0 */ 9110 #define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9111 #define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9112 #define SMU_PPUPATD1_TIMER1 (0x1UL << 10) /**< Timer 1 access control bit */ 9113 #define _SMU_PPUPATD1_TIMER1_SHIFT 10 /**< Shift value for SMU_TIMER1 */ 9114 #define _SMU_PPUPATD1_TIMER1_MASK 0x400UL /**< Bit mask for SMU_TIMER1 */ 9115 #define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9116 #define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9117 #define SMU_PPUPATD1_TIMER2 (0x1UL << 11) /**< Timer 2 access control bit */ 9118 #define _SMU_PPUPATD1_TIMER2_SHIFT 11 /**< Shift value for SMU_TIMER2 */ 9119 #define _SMU_PPUPATD1_TIMER2_MASK 0x800UL /**< Bit mask for SMU_TIMER2 */ 9120 #define _SMU_PPUPATD1_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9121 #define SMU_PPUPATD1_TIMER2_DEFAULT (_SMU_PPUPATD1_TIMER2_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9122 #define SMU_PPUPATD1_TIMER3 (0x1UL << 12) /**< Timer 3 access control bit */ 9123 #define _SMU_PPUPATD1_TIMER3_SHIFT 12 /**< Shift value for SMU_TIMER3 */ 9124 #define _SMU_PPUPATD1_TIMER3_MASK 0x1000UL /**< Bit mask for SMU_TIMER3 */ 9125 #define _SMU_PPUPATD1_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9126 #define SMU_PPUPATD1_TIMER3_DEFAULT (_SMU_PPUPATD1_TIMER3_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9127 #define SMU_PPUPATD1_TIMER4 (0x1UL << 13) /**< Timer 4 access control bit */ 9128 #define _SMU_PPUPATD1_TIMER4_SHIFT 13 /**< Shift value for SMU_TIMER4 */ 9129 #define _SMU_PPUPATD1_TIMER4_MASK 0x2000UL /**< Bit mask for SMU_TIMER4 */ 9130 #define _SMU_PPUPATD1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9131 #define SMU_PPUPATD1_TIMER4_DEFAULT (_SMU_PPUPATD1_TIMER4_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9132 #define SMU_PPUPATD1_TIMER5 (0x1UL << 14) /**< Timer 5 access control bit */ 9133 #define _SMU_PPUPATD1_TIMER5_SHIFT 14 /**< Shift value for SMU_TIMER5 */ 9134 #define _SMU_PPUPATD1_TIMER5_MASK 0x4000UL /**< Bit mask for SMU_TIMER5 */ 9135 #define _SMU_PPUPATD1_TIMER5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9136 #define SMU_PPUPATD1_TIMER5_DEFAULT (_SMU_PPUPATD1_TIMER5_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9137 #define SMU_PPUPATD1_TIMER6 (0x1UL << 15) /**< Timer 6 access control bit */ 9138 #define _SMU_PPUPATD1_TIMER6_SHIFT 15 /**< Shift value for SMU_TIMER6 */ 9139 #define _SMU_PPUPATD1_TIMER6_MASK 0x8000UL /**< Bit mask for SMU_TIMER6 */ 9140 #define _SMU_PPUPATD1_TIMER6_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9141 #define SMU_PPUPATD1_TIMER6_DEFAULT (_SMU_PPUPATD1_TIMER6_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9142 #define SMU_PPUPATD1_TRNG0 (0x1UL << 16) /**< True Random Number Generator 0 access control bit */ 9143 #define _SMU_PPUPATD1_TRNG0_SHIFT 16 /**< Shift value for SMU_TRNG0 */ 9144 #define _SMU_PPUPATD1_TRNG0_MASK 0x10000UL /**< Bit mask for SMU_TRNG0 */ 9145 #define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9146 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9147 #define SMU_PPUPATD1_UART0 (0x1UL << 17) /**< Universal Asynchronous Receiver/Transmitter 0 access control bit */ 9148 #define _SMU_PPUPATD1_UART0_SHIFT 17 /**< Shift value for SMU_UART0 */ 9149 #define _SMU_PPUPATD1_UART0_MASK 0x20000UL /**< Bit mask for SMU_UART0 */ 9150 #define _SMU_PPUPATD1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9151 #define SMU_PPUPATD1_UART0_DEFAULT (_SMU_PPUPATD1_UART0_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9152 #define SMU_PPUPATD1_UART1 (0x1UL << 18) /**< Universal Asynchronous Receiver/Transmitter 1 access control bit */ 9153 #define _SMU_PPUPATD1_UART1_SHIFT 18 /**< Shift value for SMU_UART1 */ 9154 #define _SMU_PPUPATD1_UART1_MASK 0x40000UL /**< Bit mask for SMU_UART1 */ 9155 #define _SMU_PPUPATD1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9156 #define SMU_PPUPATD1_UART1_DEFAULT (_SMU_PPUPATD1_UART1_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9157 #define SMU_PPUPATD1_USART0 (0x1UL << 19) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit */ 9158 #define _SMU_PPUPATD1_USART0_SHIFT 19 /**< Shift value for SMU_USART0 */ 9159 #define _SMU_PPUPATD1_USART0_MASK 0x80000UL /**< Bit mask for SMU_USART0 */ 9160 #define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9161 #define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9162 #define SMU_PPUPATD1_USART1 (0x1UL << 20) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit */ 9163 #define _SMU_PPUPATD1_USART1_SHIFT 20 /**< Shift value for SMU_USART1 */ 9164 #define _SMU_PPUPATD1_USART1_MASK 0x100000UL /**< Bit mask for SMU_USART1 */ 9165 #define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9166 #define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9167 #define SMU_PPUPATD1_USART2 (0x1UL << 21) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit */ 9168 #define _SMU_PPUPATD1_USART2_SHIFT 21 /**< Shift value for SMU_USART2 */ 9169 #define _SMU_PPUPATD1_USART2_MASK 0x200000UL /**< Bit mask for SMU_USART2 */ 9170 #define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9171 #define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9172 #define SMU_PPUPATD1_USART3 (0x1UL << 22) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit */ 9173 #define _SMU_PPUPATD1_USART3_SHIFT 22 /**< Shift value for SMU_USART3 */ 9174 #define _SMU_PPUPATD1_USART3_MASK 0x400000UL /**< Bit mask for SMU_USART3 */ 9175 #define _SMU_PPUPATD1_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9176 #define SMU_PPUPATD1_USART3_DEFAULT (_SMU_PPUPATD1_USART3_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9177 #define SMU_PPUPATD1_USART4 (0x1UL << 23) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit */ 9178 #define _SMU_PPUPATD1_USART4_SHIFT 23 /**< Shift value for SMU_USART4 */ 9179 #define _SMU_PPUPATD1_USART4_MASK 0x800000UL /**< Bit mask for SMU_USART4 */ 9180 #define _SMU_PPUPATD1_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9181 #define SMU_PPUPATD1_USART4_DEFAULT (_SMU_PPUPATD1_USART4_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9182 #define SMU_PPUPATD1_USART5 (0x1UL << 24) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit */ 9183 #define _SMU_PPUPATD1_USART5_SHIFT 24 /**< Shift value for SMU_USART5 */ 9184 #define _SMU_PPUPATD1_USART5_MASK 0x1000000UL /**< Bit mask for SMU_USART5 */ 9185 #define _SMU_PPUPATD1_USART5_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9186 #define SMU_PPUPATD1_USART5_DEFAULT (_SMU_PPUPATD1_USART5_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9187 #define SMU_PPUPATD1_WDOG0 (0x1UL << 26) /**< Watchdog access control bit */ 9188 #define _SMU_PPUPATD1_WDOG0_SHIFT 26 /**< Shift value for SMU_WDOG0 */ 9189 #define _SMU_PPUPATD1_WDOG0_MASK 0x4000000UL /**< Bit mask for SMU_WDOG0 */ 9190 #define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9191 #define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9192 #define SMU_PPUPATD1_WDOG1 (0x1UL << 27) /**< Watchdog access control bit */ 9193 #define _SMU_PPUPATD1_WDOG1_SHIFT 27 /**< Shift value for SMU_WDOG1 */ 9194 #define _SMU_PPUPATD1_WDOG1_MASK 0x8000000UL /**< Bit mask for SMU_WDOG1 */ 9195 #define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9196 #define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9197 #define SMU_PPUPATD1_WTIMER0 (0x1UL << 28) /**< Wide Timer 0 access control bit */ 9198 #define _SMU_PPUPATD1_WTIMER0_SHIFT 28 /**< Shift value for SMU_WTIMER0 */ 9199 #define _SMU_PPUPATD1_WTIMER0_MASK 0x10000000UL /**< Bit mask for SMU_WTIMER0 */ 9200 #define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9201 #define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9202 #define SMU_PPUPATD1_WTIMER1 (0x1UL << 29) /**< Wide Timer 0 access control bit */ 9203 #define _SMU_PPUPATD1_WTIMER1_SHIFT 29 /**< Shift value for SMU_WTIMER1 */ 9204 #define _SMU_PPUPATD1_WTIMER1_MASK 0x20000000UL /**< Bit mask for SMU_WTIMER1 */ 9205 #define _SMU_PPUPATD1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9206 #define SMU_PPUPATD1_WTIMER1_DEFAULT (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9207 #define SMU_PPUPATD1_WTIMER2 (0x1UL << 30) /**< Wide Timer 2 access control bit */ 9208 #define _SMU_PPUPATD1_WTIMER2_SHIFT 30 /**< Shift value for SMU_WTIMER2 */ 9209 #define _SMU_PPUPATD1_WTIMER2_MASK 0x40000000UL /**< Bit mask for SMU_WTIMER2 */ 9210 #define _SMU_PPUPATD1_WTIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9211 #define SMU_PPUPATD1_WTIMER2_DEFAULT (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9212 #define SMU_PPUPATD1_WTIMER3 (0x1UL << 31) /**< Wide Timer 3 access control bit */ 9213 #define _SMU_PPUPATD1_WTIMER3_SHIFT 31 /**< Shift value for SMU_WTIMER3 */ 9214 #define _SMU_PPUPATD1_WTIMER3_MASK 0x80000000UL /**< Bit mask for SMU_WTIMER3 */ 9215 #define _SMU_PPUPATD1_WTIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD1 */ 9216 #define SMU_PPUPATD1_WTIMER3_DEFAULT (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ 9217 9218 /* Bit fields for SMU PPUPATD2 */ 9219 #define _SMU_PPUPATD2_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUPATD2 */ 9220 #define _SMU_PPUPATD2_MASK 0x00000000UL /**< Mask for SMU_PPUPATD2 */ 9221 9222 /* Bit fields for SMU PPUFS */ 9223 #define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ 9224 #define _SMU_PPUFS_MASK 0x0000007FUL /**< Mask for SMU_PPUFS */ 9225 #define _SMU_PPUFS_PERIPHID_SHIFT 0 /**< Shift value for SMU_PERIPHID */ 9226 #define _SMU_PPUFS_PERIPHID_MASK 0x7FUL /**< Bit mask for SMU_PERIPHID */ 9227 #define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ 9228 #define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL /**< Mode ACMP0 for SMU_PPUFS */ 9229 #define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL /**< Mode ACMP1 for SMU_PPUFS */ 9230 #define _SMU_PPUFS_PERIPHID_ACMP2 0x00000002UL /**< Mode ACMP2 for SMU_PPUFS */ 9231 #define _SMU_PPUFS_PERIPHID_ACMP3 0x00000003UL /**< Mode ACMP3 for SMU_PPUFS */ 9232 #define _SMU_PPUFS_PERIPHID_ADC0 0x00000004UL /**< Mode ADC0 for SMU_PPUFS */ 9233 #define _SMU_PPUFS_PERIPHID_ADC1 0x00000005UL /**< Mode ADC1 for SMU_PPUFS */ 9234 #define _SMU_PPUFS_PERIPHID_CAN0 0x00000006UL /**< Mode CAN0 for SMU_PPUFS */ 9235 #define _SMU_PPUFS_PERIPHID_CAN1 0x00000007UL /**< Mode CAN1 for SMU_PPUFS */ 9236 #define _SMU_PPUFS_PERIPHID_CMU 0x00000008UL /**< Mode CMU for SMU_PPUFS */ 9237 #define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000009UL /**< Mode CRYOTIMER for SMU_PPUFS */ 9238 #define _SMU_PPUFS_PERIPHID_CRYPTO0 0x0000000AUL /**< Mode CRYPTO0 for SMU_PPUFS */ 9239 #define _SMU_PPUFS_PERIPHID_CSEN 0x0000000BUL /**< Mode CSEN for SMU_PPUFS */ 9240 #define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000CUL /**< Mode VDAC0 for SMU_PPUFS */ 9241 #define _SMU_PPUFS_PERIPHID_PRS 0x0000000DUL /**< Mode PRS for SMU_PPUFS */ 9242 #define _SMU_PPUFS_PERIPHID_EBI 0x0000000EUL /**< Mode EBI for SMU_PPUFS */ 9243 #define _SMU_PPUFS_PERIPHID_EMU 0x0000000FUL /**< Mode EMU for SMU_PPUFS */ 9244 #define _SMU_PPUFS_PERIPHID_FPUEH 0x00000011UL /**< Mode FPUEH for SMU_PPUFS */ 9245 #define _SMU_PPUFS_PERIPHID_GPCRC 0x00000012UL /**< Mode GPCRC for SMU_PPUFS */ 9246 #define _SMU_PPUFS_PERIPHID_GPIO 0x00000013UL /**< Mode GPIO for SMU_PPUFS */ 9247 #define _SMU_PPUFS_PERIPHID_I2C0 0x00000014UL /**< Mode I2C0 for SMU_PPUFS */ 9248 #define _SMU_PPUFS_PERIPHID_I2C1 0x00000015UL /**< Mode I2C1 for SMU_PPUFS */ 9249 #define _SMU_PPUFS_PERIPHID_I2C2 0x00000016UL /**< Mode I2C2 for SMU_PPUFS */ 9250 #define _SMU_PPUFS_PERIPHID_IDAC0 0x00000017UL /**< Mode IDAC0 for SMU_PPUFS */ 9251 #define _SMU_PPUFS_PERIPHID_MSC 0x00000018UL /**< Mode MSC for SMU_PPUFS */ 9252 #define _SMU_PPUFS_PERIPHID_LCD 0x00000019UL /**< Mode LCD for SMU_PPUFS */ 9253 #define _SMU_PPUFS_PERIPHID_LDMA 0x0000001AUL /**< Mode LDMA for SMU_PPUFS */ 9254 #define _SMU_PPUFS_PERIPHID_LESENSE 0x0000001BUL /**< Mode LESENSE for SMU_PPUFS */ 9255 #define _SMU_PPUFS_PERIPHID_LETIMER0 0x0000001CUL /**< Mode LETIMER0 for SMU_PPUFS */ 9256 #define _SMU_PPUFS_PERIPHID_LETIMER1 0x0000001DUL /**< Mode LETIMER1 for SMU_PPUFS */ 9257 #define _SMU_PPUFS_PERIPHID_LEUART0 0x0000001EUL /**< Mode LEUART0 for SMU_PPUFS */ 9258 #define _SMU_PPUFS_PERIPHID_LEUART1 0x0000001FUL /**< Mode LEUART1 for SMU_PPUFS */ 9259 #define _SMU_PPUFS_PERIPHID_PCNT0 0x00000020UL /**< Mode PCNT0 for SMU_PPUFS */ 9260 #define _SMU_PPUFS_PERIPHID_PCNT1 0x00000021UL /**< Mode PCNT1 for SMU_PPUFS */ 9261 #define _SMU_PPUFS_PERIPHID_PCNT2 0x00000022UL /**< Mode PCNT2 for SMU_PPUFS */ 9262 #define _SMU_PPUFS_PERIPHID_RMU 0x00000024UL /**< Mode RMU for SMU_PPUFS */ 9263 #define _SMU_PPUFS_PERIPHID_RTC 0x00000025UL /**< Mode RTC for SMU_PPUFS */ 9264 #define _SMU_PPUFS_PERIPHID_RTCC 0x00000026UL /**< Mode RTCC for SMU_PPUFS */ 9265 #define _SMU_PPUFS_PERIPHID_SMU 0x00000028UL /**< Mode SMU for SMU_PPUFS */ 9266 #define _SMU_PPUFS_PERIPHID_TIMER0 0x00000029UL /**< Mode TIMER0 for SMU_PPUFS */ 9267 #define _SMU_PPUFS_PERIPHID_TIMER1 0x0000002AUL /**< Mode TIMER1 for SMU_PPUFS */ 9268 #define _SMU_PPUFS_PERIPHID_TIMER2 0x0000002BUL /**< Mode TIMER2 for SMU_PPUFS */ 9269 #define _SMU_PPUFS_PERIPHID_TIMER3 0x0000002CUL /**< Mode TIMER3 for SMU_PPUFS */ 9270 #define _SMU_PPUFS_PERIPHID_TIMER4 0x0000002DUL /**< Mode TIMER4 for SMU_PPUFS */ 9271 #define _SMU_PPUFS_PERIPHID_TIMER5 0x0000002EUL /**< Mode TIMER5 for SMU_PPUFS */ 9272 #define _SMU_PPUFS_PERIPHID_TIMER6 0x0000002FUL /**< Mode TIMER6 for SMU_PPUFS */ 9273 #define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for SMU_PPUFS */ 9274 #define _SMU_PPUFS_PERIPHID_UART0 0x00000031UL /**< Mode UART0 for SMU_PPUFS */ 9275 #define _SMU_PPUFS_PERIPHID_UART1 0x00000032UL /**< Mode UART1 for SMU_PPUFS */ 9276 #define _SMU_PPUFS_PERIPHID_USART0 0x00000033UL /**< Mode USART0 for SMU_PPUFS */ 9277 #define _SMU_PPUFS_PERIPHID_USART1 0x00000034UL /**< Mode USART1 for SMU_PPUFS */ 9278 #define _SMU_PPUFS_PERIPHID_USART2 0x00000035UL /**< Mode USART2 for SMU_PPUFS */ 9279 #define _SMU_PPUFS_PERIPHID_USART3 0x00000036UL /**< Mode USART3 for SMU_PPUFS */ 9280 #define _SMU_PPUFS_PERIPHID_USART4 0x00000037UL /**< Mode USART4 for SMU_PPUFS */ 9281 #define _SMU_PPUFS_PERIPHID_USART5 0x00000038UL /**< Mode USART5 for SMU_PPUFS */ 9282 #define _SMU_PPUFS_PERIPHID_WDOG0 0x0000003AUL /**< Mode WDOG0 for SMU_PPUFS */ 9283 #define _SMU_PPUFS_PERIPHID_WDOG1 0x0000003BUL /**< Mode WDOG1 for SMU_PPUFS */ 9284 #define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000003CUL /**< Mode WTIMER0 for SMU_PPUFS */ 9285 #define _SMU_PPUFS_PERIPHID_WTIMER1 0x0000003DUL /**< Mode WTIMER1 for SMU_PPUFS */ 9286 #define _SMU_PPUFS_PERIPHID_WTIMER2 0x0000003EUL /**< Mode WTIMER2 for SMU_PPUFS */ 9287 #define _SMU_PPUFS_PERIPHID_WTIMER3 0x0000003FUL /**< Mode WTIMER3 for SMU_PPUFS */ 9288 #define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ 9289 #define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0) /**< Shifted mode ACMP0 for SMU_PPUFS */ 9290 #define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0) /**< Shifted mode ACMP1 for SMU_PPUFS */ 9291 #define SMU_PPUFS_PERIPHID_ACMP2 (_SMU_PPUFS_PERIPHID_ACMP2 << 0) /**< Shifted mode ACMP2 for SMU_PPUFS */ 9292 #define SMU_PPUFS_PERIPHID_ACMP3 (_SMU_PPUFS_PERIPHID_ACMP3 << 0) /**< Shifted mode ACMP3 for SMU_PPUFS */ 9293 #define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0) /**< Shifted mode ADC0 for SMU_PPUFS */ 9294 #define SMU_PPUFS_PERIPHID_ADC1 (_SMU_PPUFS_PERIPHID_ADC1 << 0) /**< Shifted mode ADC1 for SMU_PPUFS */ 9295 #define SMU_PPUFS_PERIPHID_CAN0 (_SMU_PPUFS_PERIPHID_CAN0 << 0) /**< Shifted mode CAN0 for SMU_PPUFS */ 9296 #define SMU_PPUFS_PERIPHID_CAN1 (_SMU_PPUFS_PERIPHID_CAN1 << 0) /**< Shifted mode CAN1 for SMU_PPUFS */ 9297 #define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0) /**< Shifted mode CMU for SMU_PPUFS */ 9298 #define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0) /**< Shifted mode CRYOTIMER for SMU_PPUFS */ 9299 #define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0) /**< Shifted mode CRYPTO0 for SMU_PPUFS */ 9300 #define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0) /**< Shifted mode CSEN for SMU_PPUFS */ 9301 #define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0) /**< Shifted mode VDAC0 for SMU_PPUFS */ 9302 #define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0) /**< Shifted mode PRS for SMU_PPUFS */ 9303 #define SMU_PPUFS_PERIPHID_EBI (_SMU_PPUFS_PERIPHID_EBI << 0) /**< Shifted mode EBI for SMU_PPUFS */ 9304 #define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0) /**< Shifted mode EMU for SMU_PPUFS */ 9305 #define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0) /**< Shifted mode FPUEH for SMU_PPUFS */ 9306 #define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0) /**< Shifted mode GPCRC for SMU_PPUFS */ 9307 #define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0) /**< Shifted mode GPIO for SMU_PPUFS */ 9308 #define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0) /**< Shifted mode I2C0 for SMU_PPUFS */ 9309 #define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0) /**< Shifted mode I2C1 for SMU_PPUFS */ 9310 #define SMU_PPUFS_PERIPHID_I2C2 (_SMU_PPUFS_PERIPHID_I2C2 << 0) /**< Shifted mode I2C2 for SMU_PPUFS */ 9311 #define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0) /**< Shifted mode IDAC0 for SMU_PPUFS */ 9312 #define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0) /**< Shifted mode MSC for SMU_PPUFS */ 9313 #define SMU_PPUFS_PERIPHID_LCD (_SMU_PPUFS_PERIPHID_LCD << 0) /**< Shifted mode LCD for SMU_PPUFS */ 9314 #define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0) /**< Shifted mode LDMA for SMU_PPUFS */ 9315 #define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0) /**< Shifted mode LESENSE for SMU_PPUFS */ 9316 #define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0) /**< Shifted mode LETIMER0 for SMU_PPUFS */ 9317 #define SMU_PPUFS_PERIPHID_LETIMER1 (_SMU_PPUFS_PERIPHID_LETIMER1 << 0) /**< Shifted mode LETIMER1 for SMU_PPUFS */ 9318 #define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0) /**< Shifted mode LEUART0 for SMU_PPUFS */ 9319 #define SMU_PPUFS_PERIPHID_LEUART1 (_SMU_PPUFS_PERIPHID_LEUART1 << 0) /**< Shifted mode LEUART1 for SMU_PPUFS */ 9320 #define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0) /**< Shifted mode PCNT0 for SMU_PPUFS */ 9321 #define SMU_PPUFS_PERIPHID_PCNT1 (_SMU_PPUFS_PERIPHID_PCNT1 << 0) /**< Shifted mode PCNT1 for SMU_PPUFS */ 9322 #define SMU_PPUFS_PERIPHID_PCNT2 (_SMU_PPUFS_PERIPHID_PCNT2 << 0) /**< Shifted mode PCNT2 for SMU_PPUFS */ 9323 #define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0) /**< Shifted mode RMU for SMU_PPUFS */ 9324 #define SMU_PPUFS_PERIPHID_RTC (_SMU_PPUFS_PERIPHID_RTC << 0) /**< Shifted mode RTC for SMU_PPUFS */ 9325 #define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0) /**< Shifted mode RTCC for SMU_PPUFS */ 9326 #define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0) /**< Shifted mode SMU for SMU_PPUFS */ 9327 #define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0) /**< Shifted mode TIMER0 for SMU_PPUFS */ 9328 #define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0) /**< Shifted mode TIMER1 for SMU_PPUFS */ 9329 #define SMU_PPUFS_PERIPHID_TIMER2 (_SMU_PPUFS_PERIPHID_TIMER2 << 0) /**< Shifted mode TIMER2 for SMU_PPUFS */ 9330 #define SMU_PPUFS_PERIPHID_TIMER3 (_SMU_PPUFS_PERIPHID_TIMER3 << 0) /**< Shifted mode TIMER3 for SMU_PPUFS */ 9331 #define SMU_PPUFS_PERIPHID_TIMER4 (_SMU_PPUFS_PERIPHID_TIMER4 << 0) /**< Shifted mode TIMER4 for SMU_PPUFS */ 9332 #define SMU_PPUFS_PERIPHID_TIMER5 (_SMU_PPUFS_PERIPHID_TIMER5 << 0) /**< Shifted mode TIMER5 for SMU_PPUFS */ 9333 #define SMU_PPUFS_PERIPHID_TIMER6 (_SMU_PPUFS_PERIPHID_TIMER6 << 0) /**< Shifted mode TIMER6 for SMU_PPUFS */ 9334 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode TRNG0 for SMU_PPUFS */ 9335 #define SMU_PPUFS_PERIPHID_UART0 (_SMU_PPUFS_PERIPHID_UART0 << 0) /**< Shifted mode UART0 for SMU_PPUFS */ 9336 #define SMU_PPUFS_PERIPHID_UART1 (_SMU_PPUFS_PERIPHID_UART1 << 0) /**< Shifted mode UART1 for SMU_PPUFS */ 9337 #define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0) /**< Shifted mode USART0 for SMU_PPUFS */ 9338 #define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0) /**< Shifted mode USART1 for SMU_PPUFS */ 9339 #define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0) /**< Shifted mode USART2 for SMU_PPUFS */ 9340 #define SMU_PPUFS_PERIPHID_USART3 (_SMU_PPUFS_PERIPHID_USART3 << 0) /**< Shifted mode USART3 for SMU_PPUFS */ 9341 #define SMU_PPUFS_PERIPHID_USART4 (_SMU_PPUFS_PERIPHID_USART4 << 0) /**< Shifted mode USART4 for SMU_PPUFS */ 9342 #define SMU_PPUFS_PERIPHID_USART5 (_SMU_PPUFS_PERIPHID_USART5 << 0) /**< Shifted mode USART5 for SMU_PPUFS */ 9343 #define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0) /**< Shifted mode WDOG0 for SMU_PPUFS */ 9344 #define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0) /**< Shifted mode WDOG1 for SMU_PPUFS */ 9345 #define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0) /**< Shifted mode WTIMER0 for SMU_PPUFS */ 9346 #define SMU_PPUFS_PERIPHID_WTIMER1 (_SMU_PPUFS_PERIPHID_WTIMER1 << 0) /**< Shifted mode WTIMER1 for SMU_PPUFS */ 9347 #define SMU_PPUFS_PERIPHID_WTIMER2 (_SMU_PPUFS_PERIPHID_WTIMER2 << 0) /**< Shifted mode WTIMER2 for SMU_PPUFS */ 9348 #define SMU_PPUFS_PERIPHID_WTIMER3 (_SMU_PPUFS_PERIPHID_WTIMER3 << 0) /**< Shifted mode WTIMER3 for SMU_PPUFS */ 9349 9350 /** @} */ 9351 /** @} End of group EFM32GG11B520F2048GQ100_SMU */ 9352 9353 /***************************************************************************//** 9354 * @defgroup EFM32GG11B520F2048GQ100_UNLOCK Unlock Codes 9355 * @{ 9356 ******************************************************************************/ 9357 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ 9358 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ 9359 #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ 9360 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ 9361 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ 9362 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ 9363 #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ 9364 9365 /** @} End of group EFM32GG11B520F2048GQ100_UNLOCK */ 9366 9367 /** @} End of group EFM32GG11B520F2048GQ100_BitFields */ 9368 9369 /***************************************************************************//** 9370 * @addtogroup EFM32GG11B520F2048GQ100_Alternate_Function Alternate Function 9371 * @{ 9372 * @defgroup EFM32GG11B520F2048GQ100_AF_Ports Alternate Function Ports 9373 * @{ 9374 ******************************************************************************/ 9375 9376 #define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */ 9377 #define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */ 9378 #define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */ 9379 #define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */ 9380 #define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */ 9381 #define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */ 9382 #define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */ 9383 #define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */ 9384 #define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */ 9385 #define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */ 9386 #define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */ 9387 #define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */ 9388 #define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */ 9389 #define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */ 9390 #define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */ 9391 #define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */ 9392 #define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */ 9393 #define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */ 9394 #define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */ 9395 #define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */ 9396 #define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */ 9397 #define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */ 9398 #define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */ 9399 #define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */ 9400 #define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */ 9401 #define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */ 9402 #define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */ 9403 #define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */ 9404 #define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */ 9405 #define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */ 9406 #define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */ 9407 #define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */ 9408 #define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */ 9409 #define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */ 9410 #define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */ 9411 #define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */ 9412 #define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */ 9413 #define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */ 9414 #define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */ 9415 #define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */ 9416 #define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */ 9417 #define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */ 9418 #define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */ 9419 #define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */ 9420 #define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */ 9421 #define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */ 9422 #define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */ 9423 #define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */ 9424 #define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */ 9425 #define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */ 9426 #define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */ 9427 #define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */ 9428 #define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */ 9429 #define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */ 9430 #define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */ 9431 #define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */ 9432 #define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */ 9433 #define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */ 9434 #define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */ 9435 #define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */ 9436 #define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */ 9437 #define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */ 9438 #define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */ 9439 #define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */ 9440 #define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */ 9441 #define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */ 9442 #define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */ 9443 #define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */ 9444 #define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */ 9445 #define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */ 9446 #define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */ 9447 #define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */ 9448 #define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */ 9449 #define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */ 9450 #define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */ 9451 #define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */ 9452 #define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */ 9453 #define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */ 9454 #define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */ 9455 #define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */ 9456 #define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */ 9457 #define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */ 9458 #define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */ 9459 #define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */ 9460 #define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */ 9461 #define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */ 9462 #define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */ 9463 #define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */ 9464 #define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */ 9465 #define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */ 9466 #define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */ 9467 #define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */ 9468 #define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */ 9469 #define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */ 9470 #define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */ 9471 #define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */ 9472 #define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */ 9473 #define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */ 9474 #define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */ 9475 #define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */ 9476 #define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */ 9477 #define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */ 9478 #define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */ 9479 #define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */ 9480 #define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */ 9481 #define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */ 9482 #define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */ 9483 #define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */ 9484 #define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */ 9485 #define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */ 9486 #define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */ 9487 #define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */ 9488 #define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */ 9489 #define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */ 9490 #define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */ 9491 #define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */ 9492 #define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */ 9493 #define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */ 9494 #define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */ 9495 #define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */ 9496 #define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */ 9497 #define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */ 9498 #define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */ 9499 #define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */ 9500 #define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */ 9501 #define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */ 9502 #define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */ 9503 #define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */ 9504 #define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */ 9505 #define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */ 9506 #define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */ 9507 #define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */ 9508 #define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */ 9509 #define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */ 9510 #define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */ 9511 #define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */ 9512 #define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */ 9513 #define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */ 9514 #define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */ 9515 #define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */ 9516 #define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */ 9517 #define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */ 9518 #define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */ 9519 #define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */ 9520 #define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */ 9521 #define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */ 9522 #define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */ 9523 #define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */ 9524 #define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */ 9525 #define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */ 9526 #define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */ 9527 #define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */ 9528 #define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */ 9529 #define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */ 9530 #define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */ 9531 #define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */ 9532 #define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */ 9533 #define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */ 9534 #define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */ 9535 #define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */ 9536 #define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */ 9537 #define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */ 9538 #define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */ 9539 #define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */ 9540 #define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */ 9541 #define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */ 9542 #define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */ 9543 #define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */ 9544 #define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */ 9545 #define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */ 9546 #define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */ 9547 #define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */ 9548 #define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */ 9549 #define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */ 9550 #define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */ 9551 #define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */ 9552 #define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */ 9553 #define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */ 9554 #define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */ 9555 #define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */ 9556 #define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */ 9557 #define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */ 9558 #define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */ 9559 #define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */ 9560 #define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */ 9561 #define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */ 9562 #define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */ 9563 #define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */ 9564 #define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */ 9565 #define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */ 9566 #define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */ 9567 #define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */ 9568 #define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */ 9569 #define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */ 9570 #define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */ 9571 #define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */ 9572 #define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */ 9573 #define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */ 9574 #define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */ 9575 #define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */ 9576 #define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */ 9577 #define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */ 9578 #define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */ 9579 #define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */ 9580 #define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */ 9581 #define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */ 9582 #define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */ 9583 #define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */ 9584 #define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */ 9585 #define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */ 9586 #define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */ 9587 #define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */ 9588 #define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */ 9589 #define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */ 9590 #define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */ 9591 #define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */ 9592 #define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */ 9593 #define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */ 9594 #define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */ 9595 #define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */ 9596 #define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */ 9597 #define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */ 9598 #define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */ 9599 #define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */ 9600 #define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */ 9601 #define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */ 9602 #define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */ 9603 #define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */ 9604 #define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */ 9605 #define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */ 9606 #define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */ 9607 #define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */ 9608 #define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */ 9609 #define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */ 9610 #define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */ 9611 #define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */ 9612 #define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */ 9613 #define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */ 9614 #define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */ 9615 #define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */ 9616 #define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */ 9617 #define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */ 9618 #define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */ 9619 #define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */ 9620 #define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */ 9621 #define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */ 9622 #define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */ 9623 #define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */ 9624 #define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */ 9625 #define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */ 9626 #define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */ 9627 #define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */ 9628 #define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */ 9629 #define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */ 9630 #define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */ 9631 #define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */ 9632 #define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */ 9633 #define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */ 9634 #define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */ 9635 #define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */ 9636 #define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */ 9637 #define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */ 9638 #define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */ 9639 #define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */ 9640 #define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */ 9641 #define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */ 9642 #define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */ 9643 #define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */ 9644 #define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */ 9645 #define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */ 9646 #define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */ 9647 #define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */ 9648 #define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */ 9649 #define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */ 9650 #define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */ 9651 #define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */ 9652 #define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */ 9653 #define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */ 9654 #define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */ 9655 #define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */ 9656 #define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */ 9657 #define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */ 9658 #define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */ 9659 #define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */ 9660 #define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */ 9661 #define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */ 9662 #define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */ 9663 #define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */ 9664 #define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */ 9665 #define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */ 9666 9667 /** @} */ 9668 /** @} End of group EFM32GG11B520F2048GQ100_AF_Ports */ 9669 9670 /***************************************************************************//** 9671 * @addtogroup EFM32GG11B520F2048GQ100_Alternate_Function Alternate Function 9672 * @{ 9673 * @defgroup EFM32GG11B520F2048GQ100_AF_Pins Alternate Function Pins 9674 * @{ 9675 ******************************************************************************/ 9676 9677 #define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */ 9678 #define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */ 9679 #define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */ 9680 #define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */ 9681 #define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */ 9682 #define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */ 9683 #define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */ 9684 #define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */ 9685 #define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */ 9686 #define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */ 9687 #define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */ 9688 #define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */ 9689 #define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */ 9690 #define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */ 9691 #define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */ 9692 #define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */ 9693 #define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */ 9694 #define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */ 9695 #define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */ 9696 #define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */ 9697 #define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */ 9698 #define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */ 9699 #define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */ 9700 #define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */ 9701 #define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */ 9702 #define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */ 9703 #define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */ 9704 #define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */ 9705 #define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */ 9706 #define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */ 9707 #define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */ 9708 #define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */ 9709 #define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */ 9710 #define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */ 9711 #define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */ 9712 #define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */ 9713 #define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */ 9714 #define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */ 9715 #define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */ 9716 #define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */ 9717 #define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */ 9718 #define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */ 9719 #define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */ 9720 #define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */ 9721 #define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */ 9722 #define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */ 9723 #define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */ 9724 #define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */ 9725 #define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */ 9726 #define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */ 9727 #define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */ 9728 #define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */ 9729 #define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */ 9730 #define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */ 9731 #define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */ 9732 #define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */ 9733 #define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */ 9734 #define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */ 9735 #define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */ 9736 #define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */ 9737 #define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */ 9738 #define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */ 9739 #define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */ 9740 #define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */ 9741 #define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */ 9742 #define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */ 9743 #define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */ 9744 #define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */ 9745 #define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */ 9746 #define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */ 9747 #define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */ 9748 #define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */ 9749 #define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */ 9750 #define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */ 9751 #define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */ 9752 #define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */ 9753 #define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */ 9754 #define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */ 9755 #define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */ 9756 #define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */ 9757 #define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */ 9758 #define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */ 9759 #define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */ 9760 #define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */ 9761 #define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */ 9762 #define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */ 9763 #define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */ 9764 #define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */ 9765 #define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */ 9766 #define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */ 9767 #define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */ 9768 #define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */ 9769 #define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */ 9770 #define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */ 9771 #define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */ 9772 #define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */ 9773 #define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */ 9774 #define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */ 9775 #define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */ 9776 #define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */ 9777 #define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */ 9778 #define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */ 9779 #define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */ 9780 #define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */ 9781 #define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */ 9782 #define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */ 9783 #define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */ 9784 #define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */ 9785 #define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */ 9786 #define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */ 9787 #define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */ 9788 #define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */ 9789 #define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */ 9790 #define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */ 9791 #define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */ 9792 #define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */ 9793 #define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */ 9794 #define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */ 9795 #define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */ 9796 #define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */ 9797 #define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */ 9798 #define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */ 9799 #define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */ 9800 #define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */ 9801 #define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */ 9802 #define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */ 9803 #define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */ 9804 #define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */ 9805 #define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */ 9806 #define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */ 9807 #define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */ 9808 #define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */ 9809 #define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */ 9810 #define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */ 9811 #define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */ 9812 #define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */ 9813 #define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */ 9814 #define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */ 9815 #define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */ 9816 #define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */ 9817 #define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */ 9818 #define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */ 9819 #define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */ 9820 #define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */ 9821 #define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */ 9822 #define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */ 9823 #define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */ 9824 #define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */ 9825 #define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */ 9826 #define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */ 9827 #define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */ 9828 #define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */ 9829 #define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */ 9830 #define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */ 9831 #define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */ 9832 #define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */ 9833 #define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */ 9834 #define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */ 9835 #define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */ 9836 #define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */ 9837 #define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */ 9838 #define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */ 9839 #define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */ 9840 #define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */ 9841 #define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */ 9842 #define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */ 9843 #define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */ 9844 #define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */ 9845 #define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */ 9846 #define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */ 9847 #define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */ 9848 #define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */ 9849 #define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */ 9850 #define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */ 9851 #define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */ 9852 #define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */ 9853 #define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */ 9854 #define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */ 9855 #define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */ 9856 #define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */ 9857 #define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */ 9858 #define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */ 9859 #define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */ 9860 #define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */ 9861 #define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */ 9862 #define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */ 9863 #define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */ 9864 #define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */ 9865 #define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */ 9866 #define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */ 9867 #define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */ 9868 #define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */ 9869 #define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */ 9870 #define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */ 9871 #define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */ 9872 #define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */ 9873 #define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */ 9874 #define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */ 9875 #define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */ 9876 #define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */ 9877 #define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */ 9878 #define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */ 9879 #define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */ 9880 #define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */ 9881 #define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */ 9882 #define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */ 9883 #define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */ 9884 #define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */ 9885 #define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */ 9886 #define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */ 9887 #define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */ 9888 #define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */ 9889 #define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */ 9890 #define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */ 9891 #define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */ 9892 #define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */ 9893 #define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */ 9894 #define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */ 9895 #define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */ 9896 #define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */ 9897 #define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */ 9898 #define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */ 9899 #define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */ 9900 #define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */ 9901 #define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */ 9902 #define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */ 9903 #define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */ 9904 #define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */ 9905 #define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */ 9906 #define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */ 9907 #define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */ 9908 #define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */ 9909 #define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */ 9910 #define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */ 9911 #define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */ 9912 #define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */ 9913 #define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */ 9914 #define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */ 9915 #define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */ 9916 #define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */ 9917 #define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */ 9918 #define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */ 9919 #define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */ 9920 #define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */ 9921 #define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */ 9922 #define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */ 9923 #define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */ 9924 #define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */ 9925 #define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */ 9926 #define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */ 9927 #define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */ 9928 #define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */ 9929 #define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */ 9930 #define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */ 9931 #define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */ 9932 #define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */ 9933 #define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */ 9934 #define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */ 9935 #define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */ 9936 #define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */ 9937 #define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */ 9938 #define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */ 9939 #define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */ 9940 #define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */ 9941 #define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */ 9942 #define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */ 9943 #define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */ 9944 #define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */ 9945 #define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */ 9946 #define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */ 9947 #define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */ 9948 #define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */ 9949 #define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */ 9950 #define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */ 9951 #define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */ 9952 #define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */ 9953 #define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */ 9954 #define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */ 9955 #define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */ 9956 #define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */ 9957 #define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */ 9958 #define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */ 9959 #define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */ 9960 #define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */ 9961 #define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */ 9962 #define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */ 9963 #define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */ 9964 #define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */ 9965 #define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */ 9966 #define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */ 9967 9968 /** @} */ 9969 /** @} End of group EFM32GG11B520F2048GQ100_AF_Pins */ 9970 9971 /** @} End of group EFM32GG11B520F2048GQ100 */ 9972 9973 /** @} End of group Parts */ 9974 9975 #ifdef __cplusplus 9976 } 9977 #endif 9978 #endif /* EFM32GG11B520F2048GQ100_H */ 9979
