1 /***************************************************************************//**
2 * @file
3 * @brief Security Management Unit (SMU) peripheral API
4 *******************************************************************************
5 * # License
6 * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
7 *******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 ******************************************************************************/
30
31 #ifndef EM_SMU_H
32 #define EM_SMU_H
33
34 #include "em_device.h"
35 #if defined(SMU_COUNT) && (SMU_COUNT > 0)
36
37 #include "em_assert.h"
38 #include "em_bus.h"
39
40 #include <stdint.h>
41 #include <stdbool.h>
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 /***************************************************************************//**
48 * @addtogroup smu SMU - Security Management Unit
49 * @brief Security Management Unit (SMU) Peripheral API
50 *
51 * @details
52 * SMU forms the control and status/reporting component of bus-level
53 * security in EFM32/EFR32 devices.
54 *
55 * Peripheral-level protection is provided via the peripheral protection unit
56 * (PPU). PPU provides hardware access barrier to any peripheral that is
57 * configured to be protected. When an attempt is made to access a peripheral
58 * without the required privilege/security level, PPU detects the fault
59 * and intercepts the access. No write or read of the peripheral register
60 * space occurs, and an all-zero value is returned if the access is a read.
61 *
62 * Usage example
63 * @include em_smu_init.c
64 * @{
65 ******************************************************************************/
66
67 /*******************************************************************************
68 ******************************** ENUMS ************************************
69 ******************************************************************************/
70
71 /** SMU peripheral identifiers. */
72 typedef enum {
73 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
74 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */
75 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */
76 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */
77 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */
78 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */
79 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */
80 smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1. */
81 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */
82 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */
83 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */
84 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */
85 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */
86 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */
87 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */
88 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */
89 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */
90 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */
91 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */
92 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */
93 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */
94 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */
95 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */
96 smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */
97 smuPeripheralPCNT1 = _SMU_PPUPATD0_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */
98 smuPeripheralPCNT2 = _SMU_PPUPATD0_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */
99 smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */
100 smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */
101 smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */
102 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */
103 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */
104 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */
105 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */
106 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */
107 smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */
108 smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */
109 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */
110 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */
111 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */
112 smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */
113
114 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
115 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */
116 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */
117 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */
118 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */
119 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */
120 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */
121 smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1. */
122 #if defined(_SMU_PPUPATD0_CSEN_SHIFT)
123 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */
124 #endif
125 #if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
126 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */
127 #endif
128 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */
129 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */
130 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */
131 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */
132 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */
133 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */
134 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */
135 #if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
136 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */
137 #endif
138 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */
139 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */
140 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */
141 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */
142 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */
143 smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */
144 smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */
145 smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */
146 smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */
147 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */
148 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */
149 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */
150 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */
151 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */
152 smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */
153 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */
154 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */
155 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */
156
157 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
158 #if defined(_SMU_PPUPATD0_ACMP0_SHIFT)
159 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */
160 #endif
161 #if defined(_SMU_PPUPATD0_ACMP1_SHIFT)
162 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */
163 #endif
164 #if defined(_SMU_PPUPATD0_ADC0_SHIFT)
165 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */
166 #endif
167 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */
168 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */
169 smuPeripheralCRYPTO = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */
170 #if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
171 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */
172 #endif
173 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */
174 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */
175 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */
176 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */
177 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */
178 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */
179 #if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
180 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */
181 #endif
182 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */
183 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */
184 #if defined(_SMU_PPUPATD0_LESENSE_SHIFT)
185 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */
186 #endif
187 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */
188 smuPeripheralLEUART = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */
189 #if defined(_SMU_PPUPATD0_PCNT0_SHIFT)
190 smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */
191 #endif
192 smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */
193 smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */
194 smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */
195 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */
196 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */
197 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */
198 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */
199 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */
200 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */
201 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */
202 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */
203
204 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
205 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */
206 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */
207 smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2. */
208 smuPeripheralACMP3 = _SMU_PPUPATD0_ACMP3_SHIFT, /**< SMU peripheral identifier for ACMP3. */
209 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */
210 smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1. */
211 smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */
212 smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1. */
213 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */
214 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */
215 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */
216 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */
217 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */
218 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */
219 smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI. */
220 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */
221 #if defined(_SMU_PPUPATD0_ETH_SHIFT)
222 smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH. */
223 #endif
224 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */
225 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */
226 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */
227 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */
228 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */
229 smuPeripheralI2C2 = _SMU_PPUPATD0_I2C2_SHIFT, /**< SMU peripheral identifier for I2C2. */
230 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */
231 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */
232 #if defined(_SMU_PPUPATD0_LCD_SHIFT)
233 smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */
234 #endif
235 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */
236 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */
237 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */
238 smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1. */
239 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */
240 smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1. */
241 smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */
242 smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */
243 smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */
244 #if defined(_SMU_PPUPATD1_QSPI0_SHIFT)
245 smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0. */
246 #endif
247 smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */
248 smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC. */
249 smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */
250 #if defined(_SMU_PPUPATD1_SDIO_SHIFT)
251 smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO. */
252 #endif
253 smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */
254 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */
255 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */
256 smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2. */
257 smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3. */
258 smuPeripheralTIMER4 = 32 + _SMU_PPUPATD1_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4. */
259 smuPeripheralTIMER5 = 32 + _SMU_PPUPATD1_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5. */
260 smuPeripheralTIMER6 = 32 + _SMU_PPUPATD1_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6. */
261 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */
262 smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */
263 smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1. */
264 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */
265 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */
266 smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */
267 smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */
268 smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4. */
269 smuPeripheralUSART5 = 32 + _SMU_PPUPATD1_USART5_SHIFT, /**< SMU peripheral identifier for USART5. */
270 #if defined(_SMU_PPUPATD1_USB_SHIFT)
271 smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB. */
272 #endif
273 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */
274 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */
275 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */
276 smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */
277 smuPeripheralWTIMER2 = 32 + _SMU_PPUPATD1_WTIMER2_SHIFT, /**< SMU peripheral identifier for WTIMER2. */
278 smuPeripheralWTIMER3 = 32 + _SMU_PPUPATD1_WTIMER3_SHIFT, /**< SMU peripheral identifier for WTIMER3. */
279
280 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106)
281 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */
282 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */
283 smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2. */
284 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */
285 smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1. */
286 smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */
287 smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1. */
288 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */
289 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */
290 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */
291 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */
292 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */
293 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */
294 smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI. */
295 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */
296 #if defined(_SMU_PPUPATD0_ETH_SHIFT)
297 smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH. */
298 #endif
299 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */
300 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */
301 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */
302 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */
303 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */
304 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */
305 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */
306 #if defined(_SMU_PPUPATD0_LCD_SHIFT)
307 smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */
308 #endif
309 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */
310 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */
311 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */
312 smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1. */
313 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */
314 smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1. */
315 smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */
316 smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */
317 smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */
318 #if defined(_SMU_PPUPATD1_QSPI0_SHIFT)
319 smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0. */
320 #endif
321 smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */
322 smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC. */
323 smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */
324 #if defined(_SMU_PPUPATD1_SDIO_SHIFT)
325 smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO. */
326 #endif
327 smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */
328 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */
329 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */
330 smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2. */
331 smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3. */
332 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */
333 smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */
334 smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1. */
335 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */
336 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */
337 smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */
338 smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */
339 smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4. */
340 #if defined(_SMU_PPUPATD1_USB_SHIFT)
341 smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB. */
342 #endif
343 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */
344 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */
345 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */
346 smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */
347
348 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
349 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */
350 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */
351 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */
352 smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */
353 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */
354 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */
355 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */
356 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */
357 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */
358 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */
359 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */
360 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */
361 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */
362 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */
363 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */
364 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */
365 #if defined(_SMU_PPUPATD0_LCD_SHIFT)
366 smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */
367 #endif
368 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */
369 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */
370 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */
371 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */
372 smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */
373 smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */
374 smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */
375 smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */
376 smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */
377 smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER0. */
378 smuPeripheralTRNG0 = _SMU_PPUPATD0_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */
379 smuPeripheralUART0 = _SMU_PPUPATD0_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */
380 smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */
381 smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */
382 smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */
383 smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */
384 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */
385 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */
386 smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */
387
388 #elif defined(_SILICON_LABS_32B_SERIES_2)
389 #if defined(SMU_PPUPATD0_SCRATCHPAD)
390 smuPeripheralSCRATCHPAD = _SMU_PPUPATD0_SCRATCHPAD_SHIFT, /**< SMU peripheral identifier for SCRATCHPAD */
391 #endif
392 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
393 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
394 #if defined(_SMU_PPUPATD0_HFXO0_SHIFT)
395 smuPeripheralHFXO = _SMU_PPUPATD0_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */
396 #endif
397 smuPeripheralHFRCO0 = _SMU_PPUPATD0_HFRCO0_SHIFT, /**< SMU peripheral identifier for HFRCO0 */
398 smuPeripheralFSRCO = _SMU_PPUPATD0_FSRCO_SHIFT, /**< SMU peripheral identifier for FSRCO */
399 smuPeripheralDPLL0 = _SMU_PPUPATD0_DPLL0_SHIFT, /**< SMU peripheral identifier for DPLL0 */
400 smuPeripheralLFXO = _SMU_PPUPATD0_LFXO_SHIFT, /**< SMU peripheral identifier for LFXO */
401 smuPeripheralLFRCO = _SMU_PPUPATD0_LFRCO_SHIFT, /**< SMU peripheral identifier for LFRCO */
402 smuPeripheralULFRCO = _SMU_PPUPATD0_ULFRCO_SHIFT, /**< SMU peripheral identifier for ULFRCO */
403 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */
404 smuPeripheralICACHE0 = _SMU_PPUPATD0_ICACHE0_SHIFT, /**< SMU peripheral identifier for ICACHE0 */
405 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
406 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
407 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
408 smuPeripheralLDMAXBAR = _SMU_PPUPATD0_LDMAXBAR_SHIFT, /**< SMU peripheral identifier for LDMAXBAR */
409 smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
410 smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
411 smuPeripheralTIMER2 = _SMU_PPUPATD0_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2 */
412 smuPeripheralTIMER3 = _SMU_PPUPATD0_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3 */
413 #if defined(_SMU_PPUPATD0_TIMER4_SHIFT)
414 smuPeripheralTIMER4 = _SMU_PPUPATD0_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4 */
415 #endif
416 smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
417 #if defined(_SMU_PPUPATD0_USART1_SHIFT)
418 smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
419 #endif
420 #if defined(_SMU_PPUPATD0_USART2_SHIFT)
421 smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
422 #endif
423 smuPeripheralBURTC = _SMU_PPUPATD0_BURTC_SHIFT, /**< SMU peripheral identifier for BURTC */
424 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
425 smuPeripheralCHIPTESTCTRL = _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT, /**< SMU peripheral identifier for CHIPTESTCTRL */
426 #if defined(_SMU_PPUPATD0_SYSCFGCFGNS_SHIFT)
427 smuPeripheralSYSCFGCFGNS = _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT, /**< SMU peripheral identifier for SYSCFGCFGNS */
428 #endif
429
430 #if defined(SMU_PPUPATD0_LVGD)
431 smuPeripheralLVGD = _SMU_PPUPATD0_LVGD_SHIFT, /**< SMU peripheral identifier for LVGD */
432 #endif
433 smuPeripheralSYSCFG = _SMU_PPUPATD0_SYSCFG_SHIFT, /**< SMU peripheral identifier for SYSCFG */
434 smuPeripheralBURAM = _SMU_PPUPATD0_BURAM_SHIFT, /**< SMU peripheral identifier for BURAM */
435 #if defined(_SMU_PPUPATD0_IFADCDEBUG_SHIFT)
436 smuPeripheralIFADCDEBUG = _SMU_PPUPATD0_IFADCDEBUG_SHIFT, /**< SMU peripheral identifier for IFADCDEBUG*/
437 #endif
438 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
439 #if defined(_SMU_PPUPATD0_RTCC_SHIFT)
440 smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
441 #endif
442 #if defined(_SMU_PPUPATD0_HOSTMAILBOX_SHIFT)
443 smuPeripheralHOSTMAILBOX = _SMU_PPUPATD0_HOSTMAILBOX_SHIFT, /**< SMU peripheral identifier for HOSTMAILBOX */
444 #endif
445 #if defined(_SMU_PPUPATD0_EUSART0_SHIFT)
446 smuPeripheralEUSART0 = _SMU_PPUPATD0_EUSART0_SHIFT, /**< SMU peripheral identifier for EUSART0 */
447 #endif
448 #if defined(_SMU_PPUPATD0_EUSART1_SHIFT)
449 smuPeripheralEUSART1 = _SMU_PPUPATD0_EUSART1_SHIFT, /**< SMU peripheral identifier for EUSART1 */
450 #endif
451 #if defined(_SMU_PPUPATD0_EUSART2_SHIFT)
452 smuPeripheralEUSART2 = _SMU_PPUPATD0_EUSART2_SHIFT, /**< SMU peripheral identifier for EUSART2 */
453 #endif
454 #if defined(_SMU_PPUPATD1_RTCC_SHIFT)
455 smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
456 #endif
457 #if defined(_SMU_PPUPATD1_SYSRTC_SHIFT)
458 smuPeripheralSYSRTC = 32 + _SMU_PPUPATD1_SYSRTC_SHIFT, /**< SMU peripheral identifier for SYSRTC */
459 #endif
460 #if defined(_SMU_PPUPATD1_LCD_SHIFT)
461 smuPeripheralLCD = 32 + _SMU_PPUPATD1_LCD_SHIFT, /**< SMU peripheral identifier for LCD */
462 #endif
463 #if defined(_SMU_PPUPATD1_KEYPAD_SHIFT)
464 smuPeripheralKEYPAD = 32 + _SMU_PPUPATD1_KEYPAD_SHIFT, /**< SMU peripheral identifier for KEYPAD */
465 #endif
466 #if defined(_SMU_PPUPATD1_DMEM_SHIFT)
467 smuPeripheralDMEM = 32 + _SMU_PPUPATD1_DMEM_SHIFT, /**< SMU peripheral identifier for DMEM */
468 #endif
469 #if defined(_SMU_PPUPATD1_LCDRF_SHIFT)
470 smuPeripheralLCDRF = 32 + _SMU_PPUPATD1_LCDRF_SHIFT, /**< SMU peripheral identifier for LCDRF */
471 #endif
472 #if defined(_SMU_PPUPATD1_PFMXPPRF_SHIFT)
473 smuPeripheralPFMXPPRF = 32 + _SMU_PPUPATD1_PFMXPPRF_SHIFT, /**< SMU peripheral identifier for PFMXPPRF */
474 #endif
475 #if defined(_SMU_PPUPATD1_VDAC0_SHIFT)
476 smuPeripheralVDAC0 = 32 + _SMU_PPUPATD1_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
477 #endif
478 #if defined(_SMU_PPUPATD1_PCNT_SHIFT)
479 smuPeripheralPCNT = 32 + _SMU_PPUPATD1_PCNT_SHIFT, /**< SMU peripheral identifier for PCNT */
480 #endif
481 #if defined(_SMU_PPUPATD1_LESENSE_SHIFT)
482 smuPeripheralLESENSE = 32 + _SMU_PPUPATD1_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
483 #endif
484 #if defined(_SMU_PPUPATD1_HFRCO1_SHIFT)
485 smuPeripheralHFRCO1 = 32 + _SMU_PPUPATD1_HFRCO1_SHIFT, /**< SMU peripheral identifier for HFRCO1 */
486 #endif
487 #if defined(_SMU_PPUPATD1_HFXO0_SHIFT)
488 smuPeripheralHFXO0 = 32 + _SMU_PPUPATD1_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */
489 #endif
490 #if defined(_SMU_PPUPATD1_DCDC_SHIFT)
491 smuPeripheralDCDC = 32 + _SMU_PPUPATD1_DCDC_SHIFT, /**< SMU peripheral identifier for DCDC */
492 #endif
493 #if defined(_SMU_PPUPATD1_PDM_SHIFT)
494 smuPeripheralPDM = 32 + _SMU_PPUPATD1_PDM_SHIFT, /**< SMU peripheral identifier for PDM */
495 #endif
496 #if defined(_SMU_PPUPATD1_RFSENSE_SHIFT)
497 smuPeripheralRFSENSE = 32 + _SMU_PPUPATD1_RFSENSE_SHIFT, /**< SMU peripheral identifier for RFSENSE */
498 #endif
499 smuPeripheralLETIMER0 = 32 + _SMU_PPUPATD1_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER */
500 smuPeripheralIADC0 = 32 + _SMU_PPUPATD1_IADC0_SHIFT, /**< SMU peripheral identifier for IADC0 */
501 #if defined(_SMU_PPUPATD1_ACMP0_SHIFT)
502 smuPeripheralACMP0 = 32 + _SMU_PPUPATD1_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
503 smuPeripheralACMP1 = 32 + _SMU_PPUPATD1_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
504 #endif
505 smuPeripheralI2C0 = 32 + _SMU_PPUPATD1_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
506 #if defined(_SMU_PPUPATD1_HFRCOEM23_SHIFT)
507 smuPeripheralHFRCOEM23 = 32 + _SMU_PPUPATD1_HFRCOEM23_SHIFT, /**< SMU peripheral identifier for HFRCOEM23 */
508 #endif
509 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
510 #if defined(_SMU_PPUPATD1_WDOG1_SHIFT)
511 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
512 #endif
513 smuPeripheralAMUXCP0 = 32 + _SMU_PPUPATD1_AMUXCP0_SHIFT, /**< SMU peripheral identifier for AMUXCP0 */
514 smuPeripheralRADIOAES = 32 + _SMU_PPUPATD1_RADIOAES_SHIFT, /**< SMU peripheral identifier for RADIOAES */
515 #if defined(_SMU_PPUPATD1_EUART0_SHIFT)
516 smuPeripheralEUART0 = 32 + _SMU_PPUPATD1_EUART0_SHIFT, /**< SMU peripheral identifier for EUART0 */
517 #endif
518 #if defined(_SMU_PPUPATD1_BUFC_SHIFT)
519 smuPeripheralBUFC = 32 + _SMU_PPUPATD1_BUFC_SHIFT, /**< SMU peripheral identifier for BUFC */
520 #endif
521 smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
522 #if defined(_SMU_PPUPATD1_SMUCFGNS_SHIFT)
523 smuPeripheralSMUCFGNS = 32 + _SMU_PPUPATD1_SMUCFGNS_SHIFT, /**< SMU peripheral identifier for SMUCFGNS */
524 #endif
525 smuPeripheralAHBRADIO = 32 + _SMU_PPUPATD1_AHBRADIO_SHIFT, /**< SMU peripheral identifier for AHBRADIO */
526 #if defined(_SMU_PPUPATD1_SEMAILBOX_SHIFT)
527 smuPeripheralSEMAILBOX = 32 + _SMU_PPUPATD1_SEMAILBOX_SHIFT, /**< SMU peripheral identifier for SEMAILBOX */
528 #endif
529 #if defined(_SMU_PPUPATD1_CRYPTOACC_SHIFT)
530 smuPeripheralCRYPTOACC = 32 + _SMU_PPUPATD1_CRYPTOACC_SHIFT, /**< SMU peripheral identifier for CRYPTOACC */
531 #endif
532 #else
533 #error "No peripherals defined for SMU for this device configuration."
534 #endif
535 smuPeripheralEnd
536 } SMU_Peripheral_TypeDef;
537
538 /** SMU peripheral privileged access enablers. */
539 typedef struct {
540 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
541 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */
542 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */
543 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */
544 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */
545 bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */
546 bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */
547 bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */
548 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */
549 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */
550 bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1. */
551 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */
552 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */
553 bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */
554 bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */
555 bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */
556 bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */
557 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */
558 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */
559 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */
560 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */
561 bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */
562 bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */
563 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */
564 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */
565 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */
566 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */
567 bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */
568 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */
569 bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */
570 bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */
571 bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */
572 bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */
573 bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */
574 bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */
575 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */
576 bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */
577 bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */
578 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */
579 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */
580 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */
581 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */
582 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */
583 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */
584 bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */
585 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */
586 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */
587 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */
588 bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */
589
590 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
591 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */
592 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */
593 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */
594 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */
595 bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */
596 bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */
597 bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */
598 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */
599 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */
600 bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1. */
601 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */
602 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */
603 bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */
604 bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */
605 bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */
606 bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */
607 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */
608 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */
609 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */
610 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */
611 bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */
612 bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */
613 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */
614 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */
615 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */
616 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */
617 bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */
618 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */
619 bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */
620 bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */
621 bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */
622 bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */
623 bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */
624 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */
625 bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */
626 bool privilegedReserved9 : 1; /**< Reserved privileged access enabler. */
627 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */
628 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */
629 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */
630 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */
631 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */
632 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */
633 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */
634 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */
635 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */
636
637 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
638 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */
639 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */
640 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */
641 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */
642 bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */
643 bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */
644 bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */
645 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */
646 bool privilegedCRYPTO : 1; /**< Privileged access enabler for CRYPTO. */
647 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */
648 bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */
649 bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */
650 bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */
651 bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */
652 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */
653 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */
654 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */
655 bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */
656 bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */
657 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */
658 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */
659 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */
660 bool privilegedLEUART : 1; /**< Privileged access enabler for LEUART0. */
661 bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */
662 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */
663 bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */
664 bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */
665 bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */
666 bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */
667 bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */
668 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */
669 bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */
670
671 bool privilegedReserved9 : 1; /**< Reserved privileged access enabler. */
672 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */
673 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */
674 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */
675 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */
676 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */
677 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */
678 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */
679 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */
680
681 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
682 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */
683 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */
684 bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2. */
685 bool privilegedACMP3 : 1; /**< Privileged access enabler for ACMP3. */
686 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */
687 bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1. */
688 bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */
689 bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1. */
690 bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */
691 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */
692 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */
693 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */
694 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */
695 bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */
696 bool privilegedEBI : 1; /**< Privileged access enabler for EBI. */
697 bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */
698 bool privilegedETH : 1; /**< Privileged access enabler for ETH. */
699 bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */
700 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */
701 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */
702 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */
703 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */
704 bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2. */
705 bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */
706 bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */
707 bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */
708 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */
709 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */
710 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */
711 bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1. */
712 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */
713 bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1. */
714 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */
715 bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */
716 bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */
717 bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0. */
718 bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */
719 bool privilegedRTC : 1; /**< Privileged access enabler for RTC. */
720 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */
721 bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO. */
722 bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */
723 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */
724 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */
725 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2. */
726 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3. */
727 bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4. */
728 bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5. */
729 bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6. */
730 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */
731 bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */
732 bool privilegedUART1 : 1; /**< Privileged access enabler for UART1. */
733 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */
734 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */
735 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */
736 bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */
737 bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4. */
738 bool privilegedUSART5 : 1; /**< Privileged access enabler for USART5. */
739 bool privilegedUSB : 1; /**< Privileged access enabler for USB. */
740 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */
741 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */
742 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */
743 bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */
744 bool privilegedWTIMER2 : 1; /**< Privileged access enabler for WTIMER2. */
745 bool privilegedWTIMER3 : 1; /**< Privileged access enabler for WTIMER3. */
746
747 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
748 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */
749 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */
750 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */
751 bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */
752 bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */
753 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */
754 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */
755 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */
756 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */
757 bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */
758 bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */
759 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */
760 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */
761 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */
762 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */
763 bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */
764 bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */
765 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */
766 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */
767 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */
768 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */
769 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */
770 bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */
771 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */
772 bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */
773 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */
774 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */
775 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */
776 bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */
777 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */
778 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */
779 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */
780 bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */
781 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */
782 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */
783 bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */
784
785 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106)
786 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */
787 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */
788 bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2. */
789 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */
790 bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1. */
791 bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */
792 bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1. */
793 bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */
794 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */
795 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */
796 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */
797 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */
798 bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */
799 bool privilegedEBI : 1; /**< Privileged access enabler for EBI. */
800 bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */
801 bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */
802 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */
803 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */
804 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */
805 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */
806 bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */
807 bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */
808 bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */
809 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */
810 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */
811 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */
812 bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1. */
813 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */
814 bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1. */
815 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */
816 bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */
817 bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */
818 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */
819 bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */
820 bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */
821 bool privilegedPDM : 1; /**< Privileged access enabler for PDM. */
822 bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0. */
823 bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */
824 bool privilegedRTC : 1; /**< Privileged access enabler for RTC. */
825 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */
826 bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO. */
827 bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */
828 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */
829 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */
830 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2. */
831 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3. */
832 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */
833 bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */
834 bool privilegedUART1 : 1; /**< Privileged access enabler for UART1. */
835 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */
836 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */
837 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */
838 bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */
839 bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4. */
840 bool privilegedUSB : 1; /**< Privileged access enabler for USB. */
841 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */
842 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */
843 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */
844 bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */
845
846 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
847 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */
848 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
849 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
850 bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */
851 bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */
852 bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */
853 bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */
854 bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */
855 bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */
856 bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */
857 bool privilegedMSC : 1; /**< Privileged access enabler for MSC */
858 bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */
859 bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
860 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
861 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
862 bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */
863 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
864 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
865 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
866 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
867 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
868 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
869 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
870 bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */
871 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
872 bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */
873 bool privilegedLVGD : 1; /**< Privileged access enabler for LVGD */
874 bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */
875 bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */
876 bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */
877 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
878 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
879
880 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER */
881 bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */
882 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
883 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
884 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
885 bool privilegedHFRCOEM23 : 1; /**< Privileged access enabler for HFRCOEM23 */
886 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
887 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
888 bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */
889 bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */
890 bool privilegedBUFC : 1; /**< Privileged access enabler for BUFC */
891 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
892 bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */
893 bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */
894
895 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2)
896 bool privilegedSCRATCHPAD : 1; /**< Privileged access enabler for SCRATCHPAD */
897 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
898 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
899 bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */
900 bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */
901 bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */
902 bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */
903 bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */
904 bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */
905 bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */
906 bool privilegedMSC : 1; /**< Privileged access enabler for MSC */
907 bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */
908 bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */
909 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
910 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
911 bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */
912 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
913 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
914 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
915 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
916 bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */
917 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
918 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
919 bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */
920 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
921 bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */
922 bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */
923 bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */
924 bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */
925 bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */
926 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
927 bool privilegedDCI : 1; /**< Privileged access enabler for DCI */
928
929 bool privilegedROOTCFG : 1; /**< Privileged access enabler for ROOTCFG */
930 bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */
931 bool privilegedPDM : 1; /**< Privileged access enabler for PDM */
932 bool privilegedRFSENSE : 1; /**< Privileged access enabler for RFSENSE */
933 bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */
934 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
935 bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */
936 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
937 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
938 bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */
939 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
940 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
941 bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */
942 bool privilegedEUART0 : 1; /**< Privileged access enabler for EUART0 */
943 bool privilegedCRYPTOACC : 1; /**< Privileged access enabler for CRYPTOACC */
944 bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */
945
946 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3)
947 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */
948 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
949 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
950 bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */
951 bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */
952 bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */
953 bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */
954 bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */
955 bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */
956 bool privilegedMSC : 1; /**< Privileged access enabler for MSC */
957 bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */
958 bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */
959 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
960 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
961 bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */
962 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
963 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
964 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
965 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
966 bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */
967 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
968 bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */
969 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
970 bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */
971 bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */
972 bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */
973 bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */
974 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
975 bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */
976 bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */
977 bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */
978 bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */
979
980 bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */
981 bool privilegedLCD : 1; /**< Privileged access enabler for LCD */
982 bool privilegedKEYPAD : 1; /**< Privileged access enabler for KEYPAD */
983 bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */
984 bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */
985 bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */
986 bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */
987 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
988 bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */
989 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
990 bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */
991 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
992 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
993 bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */
994 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
995 bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */
996 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
997 bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */
998 bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */
999 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
1000 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
1001 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
1002 bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */
1003 bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */
1004 bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */
1005
1006 #else
1007 #error "No peripherals defined for SMU for this device configuration"
1008 #endif
1009 } SMU_PrivilegedAccess_TypeDef;
1010
1011 /*******************************************************************************
1012 ****************************** STRUCTS ************************************
1013 ******************************************************************************/
1014
1015 /** SMU initialization structure. */
1016 typedef struct {
1017 union {
1018 uint32_t reg[2]; /**< Peripheral access control array.*/
1019 SMU_PrivilegedAccess_TypeDef access; /**< Peripheral access control array.*/
1020 } ppu; /**< PPU init array.*/
1021 bool enable; /**< SMU enable flag. When set, SMU_Init() will enable SMU.*/
1022 } SMU_Init_TypeDef;
1023
1024 /** Default SMU initialization structure settings. */
1025 #define SMU_INIT_DEFAULT { \
1026 { { 0 } }, /* No peripherals access protected. */ \
1027 true /* Enable SMU.*/ \
1028 }
1029
1030 /*******************************************************************************
1031 ***************************** PROTOTYPES **********************************
1032 ******************************************************************************/
1033
1034 /***************************************************************************//**
1035 * @brief
1036 * Enable or disable PPU of SMU.
1037 *
1038 * @param[in] enable
1039 * Set to true to enable PPU; set to false otherwise.
1040 ******************************************************************************/
SMU_EnablePPU(bool enable)1041 __STATIC_INLINE void SMU_EnablePPU(bool enable)
1042 {
1043 #if defined (_SMU_PPUCTRL_ENABLE_SHIFT)
1044 BUS_RegBitWrite(&SMU->PPUCTRL, _SMU_PPUCTRL_ENABLE_SHIFT, enable);
1045 #else
1046 (void)enable;
1047 #endif
1048 }
1049
1050 /***************************************************************************//**
1051 * @brief
1052 * Initialize PPU of SMU.
1053 *
1054 * @param[in] init
1055 * Pointer to initialization structure that defines which peripherals should
1056 * only be accessed from privileged mode, and if PPU should be enabled.
1057 ******************************************************************************/
SMU_Init(const SMU_Init_TypeDef * init)1058 __STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init)
1059 {
1060 SMU->PPUPATD0 = init->ppu.reg[0];
1061 SMU->PPUPATD1 = init->ppu.reg[1];
1062
1063 SMU_EnablePPU(init->enable);
1064 }
1065
1066 /***************************************************************************//**
1067 * @brief
1068 * Change access settings for a peripheral.
1069 *
1070 * @details
1071 * Set to limit access of a peripheral from privileged mode.
1072 *
1073 * @param[in] peripheral
1074 * ID of the peripheral to change access settings for.
1075 *
1076 * @param[in] privileged
1077 * Set to true if the peripheral should only be accessed from privileged
1078 * mode; set to false otherwise.
1079 ******************************************************************************/
SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral,bool privileged)1080 __STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral,
1081 bool privileged)
1082 {
1083 EFM_ASSERT(peripheral < smuPeripheralEnd);
1084
1085 if (peripheral < 32) {
1086 BUS_RegBitWrite(&SMU->PPUPATD0, peripheral, privileged);
1087 } else {
1088 BUS_RegBitWrite(&SMU->PPUPATD1, peripheral - 32, privileged);
1089 }
1090 }
1091
1092 /***************************************************************************//**
1093 * @brief
1094 * Get ID of the peripheral that caused an access fault.
1095 *
1096 * @note
1097 * The return value is only valid if SMU_IF_PPUPRIV interrupt flag
1098 * is set.
1099 *
1100 * @return
1101 * ID of the peripheral that caused an access fault.
1102 ******************************************************************************/
SMU_GetFaultingPeripheral(void)1103 __STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void)
1104 {
1105 return (SMU_Peripheral_TypeDef)SMU->PPUFS;
1106 }
1107
1108 /***************************************************************************//**
1109 * @brief
1110 * Clear one or more pending SMU interrupts.
1111 *
1112 * @param[in] flags
1113 * Bitwise logic OR of SMU interrupt sources to clear.
1114 ******************************************************************************/
SMU_IntClear(uint32_t flags)1115 __STATIC_INLINE void SMU_IntClear(uint32_t flags)
1116 {
1117 #if defined (SMU_HAS_SET_CLEAR)
1118 SMU->IF_CLR = flags;
1119 #else
1120 SMU->IFC = flags;
1121 #endif
1122 }
1123
1124 /***************************************************************************//**
1125 * @brief
1126 * Disable one or more SMU interrupts.
1127 *
1128 * @param[in] flags
1129 * SMU interrupt sources to disable.
1130 ******************************************************************************/
SMU_IntDisable(uint32_t flags)1131 __STATIC_INLINE void SMU_IntDisable(uint32_t flags)
1132 {
1133 #if defined (SMU_HAS_SET_CLEAR)
1134 SMU->IEN_CLR = flags;
1135 #else
1136 SMU->IEN &= ~flags;
1137 #endif
1138 }
1139
1140 /***************************************************************************//**
1141 * @brief
1142 * Enable one or more SMU interrupts.
1143 *
1144 * @note
1145 * Depending on the use, a pending interrupt may already be set prior to
1146 * enabling the interrupt. To ignore a pending interrupt, consider using
1147 * SMU_IntClear() prior to enabling the interrupt.
1148 *
1149 * @param[in] flags
1150 * SMU interrupt sources to enable.
1151 ******************************************************************************/
SMU_IntEnable(uint32_t flags)1152 __STATIC_INLINE void SMU_IntEnable(uint32_t flags)
1153 {
1154 #if defined (SMU_HAS_SET_CLEAR)
1155 SMU->IEN_SET = flags;
1156 #else
1157 SMU->IEN |= flags;
1158 #endif
1159 }
1160
1161 /***************************************************************************//**
1162 * @brief
1163 * Get pending SMU interrupts.
1164 *
1165 * @return
1166 * SMU interrupt sources pending.
1167 ******************************************************************************/
SMU_IntGet(void)1168 __STATIC_INLINE uint32_t SMU_IntGet(void)
1169 {
1170 return SMU->IF;
1171 }
1172
1173 /***************************************************************************//**
1174 * @brief
1175 * Get enabled and pending SMU interrupt flags.
1176 * Useful for handling more interrupt sources in the same interrupt handler.
1177 *
1178 * @note
1179 * Interrupt flags are not cleared by this function.
1180 *
1181 * @return
1182 * Pending and enabled SMU interrupt sources.
1183 * The return value is the bitwise AND combination of
1184 * - the OR combination of enabled interrupt sources in SMU_IEN register
1185 * and
1186 * - the OR combination of valid interrupt flags in SMU_IF register.
1187 ******************************************************************************/
SMU_IntGetEnabled(void)1188 __STATIC_INLINE uint32_t SMU_IntGetEnabled(void)
1189 {
1190 uint32_t tmp;
1191
1192 // Store SMU->IEN in temporary variable to define explicit order
1193 // of volatile accesses.
1194 tmp = SMU->IEN;
1195
1196 // Bitwise AND of pending and enabled interrupts.
1197 return SMU->IF & tmp;
1198 }
1199
1200 /***************************************************************************//**
1201 * @brief
1202 * Set one or more pending SMU interrupts from SW.
1203 *
1204 * @param[in] flags
1205 * SMU interrupt sources to set to pending.
1206 ******************************************************************************/
SMU_IntSet(uint32_t flags)1207 __STATIC_INLINE void SMU_IntSet(uint32_t flags)
1208 {
1209 #if defined (SMU_HAS_SET_CLEAR)
1210 SMU->IF_SET = flags;
1211 #else
1212 SMU->IFS = flags;
1213 #endif
1214 }
1215
1216 /** @} (end addtogroup smu) */
1217
1218 #ifdef __cplusplus
1219 }
1220 #endif
1221
1222 #endif // defined(SMU_COUNT) && (SMU_COUNT > 0)
1223 #endif // EM_SMU_H
1224
