1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG24 I2C register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG24_I2C_H 31 #define EFR32MG24_I2C_H 32 #define I2C_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG24_I2C I2C 40 * @{ 41 * @brief EFR32MG24 I2C Register Declaration. 42 *****************************************************************************/ 43 44 /** I2C Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP VERSION Register */ 47 __IOM uint32_t EN; /**< Enable Register */ 48 __IOM uint32_t CTRL; /**< Control Register */ 49 __IOM uint32_t CMD; /**< Command Register */ 50 __IM uint32_t STATE; /**< State Register */ 51 __IM uint32_t STATUS; /**< Status Register */ 52 __IOM uint32_t CLKDIV; /**< Clock Division Register */ 53 __IOM uint32_t SADDR; /**< Follower Address Register */ 54 __IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */ 55 __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ 56 __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ 57 __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ 58 __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ 59 __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ 60 __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ 61 __IOM uint32_t IF; /**< Interrupt Flag Register */ 62 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 63 uint32_t RESERVED0[1007U]; /**< Reserved for future use */ 64 __IM uint32_t IPVERSION_SET; /**< IP VERSION Register */ 65 __IOM uint32_t EN_SET; /**< Enable Register */ 66 __IOM uint32_t CTRL_SET; /**< Control Register */ 67 __IOM uint32_t CMD_SET; /**< Command Register */ 68 __IM uint32_t STATE_SET; /**< State Register */ 69 __IM uint32_t STATUS_SET; /**< Status Register */ 70 __IOM uint32_t CLKDIV_SET; /**< Clock Division Register */ 71 __IOM uint32_t SADDR_SET; /**< Follower Address Register */ 72 __IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */ 73 __IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */ 74 __IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */ 75 __IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */ 76 __IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */ 77 __IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */ 78 __IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */ 79 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 80 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 81 uint32_t RESERVED1[1007U]; /**< Reserved for future use */ 82 __IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */ 83 __IOM uint32_t EN_CLR; /**< Enable Register */ 84 __IOM uint32_t CTRL_CLR; /**< Control Register */ 85 __IOM uint32_t CMD_CLR; /**< Command Register */ 86 __IM uint32_t STATE_CLR; /**< State Register */ 87 __IM uint32_t STATUS_CLR; /**< Status Register */ 88 __IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */ 89 __IOM uint32_t SADDR_CLR; /**< Follower Address Register */ 90 __IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */ 91 __IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */ 92 __IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */ 93 __IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */ 94 __IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */ 95 __IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */ 96 __IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */ 97 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 98 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 99 uint32_t RESERVED2[1007U]; /**< Reserved for future use */ 100 __IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */ 101 __IOM uint32_t EN_TGL; /**< Enable Register */ 102 __IOM uint32_t CTRL_TGL; /**< Control Register */ 103 __IOM uint32_t CMD_TGL; /**< Command Register */ 104 __IM uint32_t STATE_TGL; /**< State Register */ 105 __IM uint32_t STATUS_TGL; /**< Status Register */ 106 __IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */ 107 __IOM uint32_t SADDR_TGL; /**< Follower Address Register */ 108 __IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */ 109 __IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */ 110 __IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */ 111 __IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */ 112 __IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */ 113 __IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */ 114 __IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */ 115 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 116 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 117 } I2C_TypeDef; 118 /** @} End of group EFR32MG24_I2C */ 119 120 /**************************************************************************//** 121 * @addtogroup EFR32MG24_I2C 122 * @{ 123 * @defgroup EFR32MG24_I2C_BitFields I2C Bit Fields 124 * @{ 125 *****************************************************************************/ 126 127 /* Bit fields for I2C IPVERSION */ 128 #define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */ 129 #define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */ 130 #define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */ 131 #define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */ 132 #define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */ 133 #define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */ 134 135 /* Bit fields for I2C EN */ 136 #define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */ 137 #define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */ 138 #define I2C_EN_EN (0x1UL << 0) /**< module enable */ 139 #define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */ 140 #define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ 141 #define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */ 142 #define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */ 143 #define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */ 144 #define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */ 145 #define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */ 146 #define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */ 147 148 /* Bit fields for I2C CTRL */ 149 #define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ 150 #define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */ 151 #define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */ 152 #define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */ 153 #define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */ 154 #define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 155 #define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ 156 #define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ 157 #define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ 158 #define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */ 159 #define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */ 160 #define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */ 161 #define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ 162 #define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ 163 #define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 164 #define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ 165 #define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ 166 #define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ 167 #define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */ 168 #define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */ 169 #define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ 170 #define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ 171 #define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ 172 #define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 173 #define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ 174 #define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ 175 #define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ 176 #define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */ 177 #define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */ 178 #define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ 179 #define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ 180 #define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ 181 #define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 182 #define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ 183 #define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ 184 #define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ 185 #define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */ 186 #define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */ 187 #define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ 188 #define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ 189 #define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ 190 #define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 191 #define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ 192 #define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ 193 #define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ 194 #define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */ 195 #define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */ 196 #define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ 197 #define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ 198 #define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ 199 #define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 200 #define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ 201 #define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ 202 #define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ 203 #define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */ 204 #define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */ 205 #define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ 206 #define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ 207 #define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ 208 #define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 209 #define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ 210 #define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ 211 #define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ 212 #define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */ 213 #define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */ 214 #define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ 215 #define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ 216 #define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ 217 #define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 218 #define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ 219 #define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */ 220 #define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ 221 #define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ 222 #define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */ 223 #define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ 224 #define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ 225 #define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 226 #define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ 227 #define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ 228 #define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ 229 #define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ 230 #define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ 231 #define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ 232 #define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ 233 #define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ 234 #define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ 235 #define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 236 #define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ 237 #define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ 238 #define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ 239 #define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ 240 #define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ 241 #define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ 242 #define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */ 243 #define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */ 244 #define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */ 245 #define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ 246 #define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ 247 #define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ 248 #define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 249 #define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ 250 #define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ 251 #define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ 252 #define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */ 253 #define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */ 254 #define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ 255 #define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ 256 #define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 257 #define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ 258 #define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ 259 #define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ 260 #define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ 261 #define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */ 262 #define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */ 263 #define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ 264 #define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ 265 #define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */ 266 #define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */ 267 #define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */ 268 #define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */ 269 #define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */ 270 #define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */ 271 #define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */ 272 #define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */ 273 #define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 274 #define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ 275 #define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ 276 #define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */ 277 #define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */ 278 #define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */ 279 #define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */ 280 #define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */ 281 #define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */ 282 #define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ 283 #define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ 284 #define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ 285 #define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */ 286 #define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */ 287 #define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */ 288 289 /* Bit fields for I2C CMD */ 290 #define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ 291 #define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ 292 #define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ 293 #define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ 294 #define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ 295 #define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 296 #define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ 297 #define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ 298 #define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ 299 #define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ 300 #define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 301 #define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ 302 #define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ 303 #define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ 304 #define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ 305 #define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 306 #define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ 307 #define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ 308 #define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ 309 #define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ 310 #define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 311 #define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ 312 #define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ 313 #define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ 314 #define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ 315 #define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 316 #define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ 317 #define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ 318 #define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ 319 #define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ 320 #define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 321 #define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ 322 #define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ 323 #define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ 324 #define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ 325 #define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 326 #define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ 327 #define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ 328 #define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ 329 #define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ 330 #define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ 331 #define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ 332 333 /* Bit fields for I2C STATE */ 334 #define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ 335 #define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ 336 #define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ 337 #define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ 338 #define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ 339 #define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ 340 #define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ 341 #define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */ 342 #define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ 343 #define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ 344 #define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ 345 #define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ 346 #define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ 347 #define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ 348 #define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ 349 #define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ 350 #define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ 351 #define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ 352 #define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ 353 #define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ 354 #define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ 355 #define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ 356 #define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ 357 #define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ 358 #define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ 359 #define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ 360 #define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ 361 #define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ 362 #define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ 363 #define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ 364 #define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ 365 #define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ 366 #define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ 367 #define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ 368 #define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ 369 #define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ 370 #define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ 371 #define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ 372 #define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ 373 #define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ 374 #define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ 375 #define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ 376 #define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ 377 #define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ 378 #define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ 379 380 /* Bit fields for I2C STATUS */ 381 #define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ 382 #define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */ 383 #define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ 384 #define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ 385 #define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ 386 #define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 387 #define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ 388 #define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ 389 #define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ 390 #define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ 391 #define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 392 #define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ 393 #define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ 394 #define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ 395 #define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ 396 #define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 397 #define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ 398 #define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ 399 #define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ 400 #define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ 401 #define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 402 #define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ 403 #define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ 404 #define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ 405 #define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ 406 #define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 407 #define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ 408 #define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ 409 #define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ 410 #define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ 411 #define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 412 #define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ 413 #define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ 414 #define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ 415 #define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ 416 #define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 417 #define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ 418 #define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ 419 #define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ 420 #define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ 421 #define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ 422 #define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ 423 #define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ 424 #define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ 425 #define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ 426 #define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 427 #define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ 428 #define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ 429 #define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ 430 #define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ 431 #define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 432 #define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ 433 #define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */ 434 #define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */ 435 #define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ 436 #define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */ 437 438 /* Bit fields for I2C CLKDIV */ 439 #define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ 440 #define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ 441 #define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ 442 #define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ 443 #define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ 444 #define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ 445 446 /* Bit fields for I2C SADDR */ 447 #define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ 448 #define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ 449 #define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ 450 #define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ 451 #define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ 452 #define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ 453 454 /* Bit fields for I2C SADDRMASK */ 455 #define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ 456 #define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ 457 #define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */ 458 #define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */ 459 #define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ 460 #define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ 461 462 /* Bit fields for I2C RXDATA */ 463 #define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ 464 #define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ 465 #define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ 466 #define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ 467 #define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ 468 #define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ 469 470 /* Bit fields for I2C RXDOUBLE */ 471 #define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ 472 #define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ 473 #define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ 474 #define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ 475 #define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ 476 #define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ 477 #define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ 478 #define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ 479 #define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ 480 #define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ 481 482 /* Bit fields for I2C RXDATAP */ 483 #define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ 484 #define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ 485 #define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ 486 #define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ 487 #define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ 488 #define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ 489 490 /* Bit fields for I2C RXDOUBLEP */ 491 #define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ 492 #define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ 493 #define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ 494 #define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ 495 #define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ 496 #define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ 497 #define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ 498 #define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ 499 #define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ 500 #define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ 501 502 /* Bit fields for I2C TXDATA */ 503 #define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ 504 #define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ 505 #define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ 506 #define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ 507 #define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ 508 #define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ 509 510 /* Bit fields for I2C TXDOUBLE */ 511 #define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ 512 #define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ 513 #define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ 514 #define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ 515 #define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ 516 #define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ 517 #define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ 518 #define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ 519 #define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ 520 #define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ 521 522 /* Bit fields for I2C IF */ 523 #define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */ 524 #define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */ 525 #define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ 526 #define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ 527 #define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ 528 #define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 529 #define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ 530 #define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ 531 #define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ 532 #define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ 533 #define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 534 #define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ 535 #define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ 536 #define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ 537 #define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ 538 #define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 539 #define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ 540 #define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ 541 #define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ 542 #define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ 543 #define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 544 #define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ 545 #define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ 546 #define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ 547 #define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ 548 #define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 549 #define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ 550 #define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ 551 #define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ 552 #define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ 553 #define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 554 #define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ 555 #define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ 556 #define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ 557 #define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ 558 #define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 559 #define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ 560 #define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ 561 #define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ 562 #define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ 563 #define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 564 #define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ 565 #define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ 566 #define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ 567 #define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ 568 #define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 569 #define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ 570 #define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ 571 #define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ 572 #define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ 573 #define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 574 #define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ 575 #define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ 576 #define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ 577 #define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ 578 #define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 579 #define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ 580 #define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ 581 #define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ 582 #define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ 583 #define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 584 #define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ 585 #define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ 586 #define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ 587 #define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ 588 #define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 589 #define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ 590 #define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ 591 #define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ 592 #define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ 593 #define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 594 #define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ 595 #define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ 596 #define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ 597 #define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ 598 #define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 599 #define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ 600 #define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ 601 #define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ 602 #define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ 603 #define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 604 #define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ 605 #define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ 606 #define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ 607 #define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ 608 #define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 609 #define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ 610 #define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ 611 #define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ 612 #define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ 613 #define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 614 #define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ 615 #define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ 616 #define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ 617 #define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ 618 #define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 619 #define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ 620 #define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ 621 #define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ 622 #define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ 623 #define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 624 #define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */ 625 #define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ 626 #define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ 627 #define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ 628 #define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ 629 #define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */ 630 631 /* Bit fields for I2C IEN */ 632 #define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ 633 #define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */ 634 #define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */ 635 #define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ 636 #define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ 637 #define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 638 #define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ 639 #define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ 640 #define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ 641 #define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ 642 #define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 643 #define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ 644 #define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ 645 #define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ 646 #define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ 647 #define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 648 #define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ 649 #define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ 650 #define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ 651 #define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ 652 #define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 653 #define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ 654 #define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ 655 #define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ 656 #define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ 657 #define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 658 #define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ 659 #define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ 660 #define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ 661 #define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ 662 #define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 663 #define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ 664 #define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ 665 #define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ 666 #define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ 667 #define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 668 #define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ 669 #define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ 670 #define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ 671 #define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ 672 #define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 673 #define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ 674 #define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ 675 #define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ 676 #define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ 677 #define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 678 #define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ 679 #define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ 680 #define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ 681 #define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ 682 #define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 683 #define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ 684 #define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ 685 #define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ 686 #define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ 687 #define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 688 #define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ 689 #define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ 690 #define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ 691 #define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ 692 #define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 693 #define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ 694 #define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ 695 #define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ 696 #define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ 697 #define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 698 #define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ 699 #define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ 700 #define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ 701 #define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ 702 #define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 703 #define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ 704 #define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ 705 #define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ 706 #define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ 707 #define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 708 #define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ 709 #define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ 710 #define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ 711 #define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ 712 #define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 713 #define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ 714 #define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ 715 #define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ 716 #define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ 717 #define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 718 #define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ 719 #define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ 720 #define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ 721 #define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ 722 #define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 723 #define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ 724 #define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ 725 #define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ 726 #define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ 727 #define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 728 #define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ 729 #define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ 730 #define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ 731 #define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ 732 #define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 733 #define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */ 734 #define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ 735 #define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ 736 #define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ 737 #define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ 738 #define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */ 739 740 /** @} End of group EFR32MG24_I2C_BitFields */ 741 /** @} End of group EFR32MG24_I2C */ 742 /** @} End of group Parts */ 743 744 #endif /* EFR32MG24_I2C_H */ 745
