1 /**************************************************************************//** 2 * @file 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File 4 * for EFR32MG21A010F512IM32 5 ****************************************************************************** 6 * # License 7 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 8 ****************************************************************************** 9 * 10 * SPDX-License-Identifier: Zlib 11 * 12 * The licensor of this software is Silicon Laboratories Inc. 13 * 14 * This software is provided 'as-is', without any express or implied 15 * warranty. In no event will the authors be held liable for any damages 16 * arising from the use of this software. 17 * 18 * Permission is granted to anyone to use this software for any purpose, 19 * including commercial applications, and to alter it and redistribute it 20 * freely, subject to the following restrictions: 21 * 22 * 1. The origin of this software must not be misrepresented; you must not 23 * claim that you wrote the original software. If you use this software 24 * in a product, an acknowledgment in the product documentation would be 25 * appreciated but is not required. 26 * 2. Altered source versions must be plainly marked as such, and must not be 27 * misrepresented as being the original software. 28 * 3. This notice may not be removed or altered from any source distribution. 29 * 30 *****************************************************************************/ 31 #ifndef EFR32MG21A010F512IM32_H 32 #define EFR32MG21A010F512IM32_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /**************************************************************************//** 39 * @addtogroup Parts 40 * @{ 41 *****************************************************************************/ 42 43 /**************************************************************************//** 44 * @defgroup EFR32MG21A010F512IM32 EFR32MG21A010F512IM32 45 * @{ 46 *****************************************************************************/ 47 48 /** Interrupt Number Definition */ 49 typedef enum IRQn{ 50 /****** Cortex-M Processor Exceptions Numbers ******************************************/ 51 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ 52 HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ 53 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ 54 BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ 55 UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ 56 SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ 57 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ 58 PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ 59 SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ 60 61 /****** EFR32MG21 Peripheral Interrupt Numbers ******************************************/ 62 63 SETAMPERHOST_IRQn = 0, /*!< 0 EFR32 SETAMPERHOST Interrupt */ 64 SEMBRX_IRQn = 1, /*!< 1 EFR32 SEMBRX Interrupt */ 65 SEMBTX_IRQn = 2, /*!< 2 EFR32 SEMBTX Interrupt */ 66 SMU_SECURE_IRQn = 3, /*!< 3 EFR32 SMU_SECURE Interrupt */ 67 SMU_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_PRIVILEGED Interrupt */ 68 EMU_IRQn = 5, /*!< 5 EFR32 EMU Interrupt */ 69 TIMER0_IRQn = 6, /*!< 6 EFR32 TIMER0 Interrupt */ 70 TIMER1_IRQn = 7, /*!< 7 EFR32 TIMER1 Interrupt */ 71 TIMER2_IRQn = 8, /*!< 8 EFR32 TIMER2 Interrupt */ 72 TIMER3_IRQn = 9, /*!< 9 EFR32 TIMER3 Interrupt */ 73 RTCC_IRQn = 10, /*!< 10 EFR32 RTCC Interrupt */ 74 USART0_RX_IRQn = 11, /*!< 11 EFR32 USART0_RX Interrupt */ 75 USART0_TX_IRQn = 12, /*!< 12 EFR32 USART0_TX Interrupt */ 76 USART1_RX_IRQn = 13, /*!< 13 EFR32 USART1_RX Interrupt */ 77 USART1_TX_IRQn = 14, /*!< 14 EFR32 USART1_TX Interrupt */ 78 USART2_RX_IRQn = 15, /*!< 15 EFR32 USART2_RX Interrupt */ 79 USART2_TX_IRQn = 16, /*!< 16 EFR32 USART2_TX Interrupt */ 80 ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ 81 BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ 82 LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ 83 SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ 84 LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ 85 LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ 86 LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ 87 ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ 88 GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ 89 GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ 90 I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ 91 I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ 92 EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ 93 EMUSE_IRQn = 30, /*!< 30 EFR32 EMUSE Interrupt */ 94 AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ 95 BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ 96 FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ 97 FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ 98 MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ 99 PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ 100 RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ 101 RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ 102 PRORTC_IRQn = 39, /*!< 39 EFR32 PRORTC Interrupt */ 103 SYNTH_IRQn = 40, /*!< 40 EFR32 SYNTH Interrupt */ 104 ACMP0_IRQn = 41, /*!< 41 EFR32 ACMP0 Interrupt */ 105 ACMP1_IRQn = 42, /*!< 42 EFR32 ACMP1 Interrupt */ 106 WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ 107 WDOG1_IRQn = 44, /*!< 44 EFR32 WDOG1 Interrupt */ 108 HFXO00_IRQn = 45, /*!< 45 EFR32 HFXO00 Interrupt */ 109 HFRCO0_IRQn = 46, /*!< 46 EFR32 HFRCO0 Interrupt */ 110 HFRCOEM23_IRQn = 47, /*!< 47 EFR32 HFRCOEM23 Interrupt */ 111 CMU_IRQn = 48, /*!< 48 EFR32 CMU Interrupt */ 112 AES_IRQn = 49, /*!< 49 EFR32 AES Interrupt */ 113 IADC_IRQn = 50, /*!< 50 EFR32 IADC Interrupt */ 114 MSC_IRQn = 51, /*!< 51 EFR32 MSC Interrupt */ 115 DPLL0_IRQn = 52, /*!< 52 EFR32 DPLL0 Interrupt */ 116 SW0_IRQn = 53, /*!< 53 EFR32 SW0 Interrupt */ 117 SW1_IRQn = 54, /*!< 54 EFR32 SW1 Interrupt */ 118 SW2_IRQn = 55, /*!< 55 EFR32 SW2 Interrupt */ 119 SW3_IRQn = 56, /*!< 56 EFR32 SW3 Interrupt */ 120 KERNEL0_IRQn = 57, /*!< 57 EFR32 KERNEL0 Interrupt */ 121 KERNEL1_IRQn = 58, /*!< 58 EFR32 KERNEL1 Interrupt */ 122 M33CTI0_IRQn = 59, /*!< 59 EFR32 M33CTI0 Interrupt */ 123 M33CTI1_IRQn = 60, /*!< 60 EFR32 M33CTI1 Interrupt */ 124 } IRQn_Type; 125 126 /**************************************************************************//** 127 * @defgroup EFR32MG21A010F512IM32_Core EFR32MG21A010F512IM32 Core 128 * @{ 129 * @brief Processor and Core Peripheral Section 130 *****************************************************************************/ 131 132 #define __CM33_REV 0x0003U /**< Cortex-M33 Core revision */ 133 #define __DSP_PRESENT 1U /**< Presence of DSP */ 134 #define __FPU_PRESENT 1U /**< Presence of FPU */ 135 #define __MPU_PRESENT 1U /**< Presence of MPU */ 136 #define __SAUREGION_PRESENT 1U /**< Presence of FPU */ 137 #define __TZ_PRESENT 1U /**< Presence of TrustZone */ 138 #define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ 139 #define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ 140 #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ 141 142 /** @} End of group EFR32MG21A010F512IM32_Core */ 143 144 /**************************************************************************//** 145 * @defgroup EFR32MG21A010F512IM32_Part EFR32MG21A010F512IM32 Part 146 * @{ 147 ******************************************************************************/ 148 149 /** Part number */ 150 151 /* If part number is not defined as compiler option, define it */ 152 #if !defined(EFR32MG21A010F512IM32) 153 #define EFR32MG21A010F512IM32 1 /**< FULL Part */ 154 #endif 155 156 /** Configure part number */ 157 #define PART_NUMBER "EFR32MG21A010F512IM32" /**< Part Number */ 158 159 /** Family / Line / Series / Config */ 160 #define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ 161 #define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ 162 #define _EFR_DEVICE 1 /** Product Line Identifier */ 163 #define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ 164 #define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ 165 #define _SILICON_LABS_32B_SERIES_2_CONFIG_1 /** Product Config Identifier */ 166 #define _SILICON_LABS_32B_SERIES_2_CONFIG 1 /** Product Config Identifier */ 167 #define _SILICON_LABS_GECKO_INTERNAL_SDID 200 /** Silicon Labs internal use only */ 168 #define _SILICON_LABS_GECKO_INTERNAL_SDID_200 /** Silicon Labs internal use only */ 169 #define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ 170 #define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ 171 #define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ 172 #define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ 173 #define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ 174 #define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ 175 #define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ 176 #define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ 177 #define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_NOTUSED /** DCDC feature set */ 178 #define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ 179 #define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ 180 #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ 181 #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ 182 #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ 183 #define _SILICON_LABS_EFR32_2G4HZ_MP_PA_MAX_OUTPUT_DBM 10 /** Radio 2G4HZ MP PA output power */ 184 #define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ 185 #define _SILICON_LABS_EFR32_2G4HZ_MP_PA_PRESENT /** Radio 2G4HZ MP PA is present */ 186 #define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ 187 188 /** Memory Base addresses and limits */ 189 #define FLASH_MEM_BASE (0x00000000UL) /** FLASH_MEM base address */ 190 #define FLASH_MEM_SIZE (0x00100000UL) /** FLASH_MEM available address space */ 191 #define FLASH_MEM_END (0x000FFFFFUL) /** FLASH_MEM end address */ 192 #define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ 193 #define MSC_FLASH_MEM_BASE (0x00000000UL) /** MSC_FLASH_MEM base address */ 194 #define MSC_FLASH_MEM_SIZE (0x00100000UL) /** MSC_FLASH_MEM available address space */ 195 #define MSC_FLASH_MEM_END (0x000FFFFFUL) /** MSC_FLASH_MEM end address */ 196 #define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ 197 #define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ 198 #define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ 199 #define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ 200 #define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ 201 #define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ 202 #define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ 203 #define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ 204 #define USERDATA_BITS (0xBUL) /** USERDATA used bits */ 205 #define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ 206 #define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ 207 #define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ 208 #define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ 209 #define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE0E000UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ 210 #define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000400UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ 211 #define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE0E3FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ 212 #define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ 213 #define MSC_FLASH_RESERVED_MEM_BASE (0x0FF00000UL) /** MSC_FLASH_RESERVED_MEM base address */ 214 #define MSC_FLASH_RESERVED_MEM_SIZE (0x00100000UL) /** MSC_FLASH_RESERVED_MEM available address space */ 215 #define MSC_FLASH_RESERVED_MEM_END (0x0FFFFFFFUL) /** MSC_FLASH_RESERVED_MEM end address */ 216 #define MSC_FLASH_RESERVED_MEM_BITS (0x15UL) /** MSC_FLASH_RESERVED_MEM used bits */ 217 #define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ 218 #define DMEM_RAM0_RAM_MEM_SIZE (0x00018000UL) /** DMEM_RAM0_RAM_MEM available address space */ 219 #define DMEM_RAM0_RAM_MEM_END (0x20017FFFUL) /** DMEM_RAM0_RAM_MEM end address */ 220 #define DMEM_RAM0_RAM_MEM_BITS (0x11UL) /** DMEM_RAM0_RAM_MEM used bits */ 221 #define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ 222 #define RAM_MEM_SIZE (0x00018000UL) /** RAM_MEM available address space */ 223 #define RAM_MEM_END (0x20017FFFUL) /** RAM_MEM end address */ 224 #define RAM_MEM_BITS (0x11UL) /** RAM_MEM used bits */ 225 #define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ 226 #define RDMEM_SEQRAM_S_MEM_SIZE (0x00002000UL) /** RDMEM_SEQRAM_S_MEM available address space */ 227 #define RDMEM_SEQRAM_S_MEM_END (0xA0001FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ 228 #define RDMEM_SEQRAM_S_MEM_BITS (0xEUL) /** RDMEM_SEQRAM_S_MEM used bits */ 229 #define RDMEM_FRCRAM_S_MEM_BASE (0xA0002000UL) /** RDMEM_FRCRAM_S_MEM base address */ 230 #define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ 231 #define RDMEM_FRCRAM_S_MEM_END (0xA0002FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ 232 #define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ 233 #define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ 234 #define RDMEM_SEQRAM_NS_MEM_SIZE (0x00002000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ 235 #define RDMEM_SEQRAM_NS_MEM_END (0xB0001FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ 236 #define RDMEM_SEQRAM_NS_MEM_BITS (0xEUL) /** RDMEM_SEQRAM_NS_MEM used bits */ 237 #define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ 238 #define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00002000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ 239 #define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0001FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ 240 #define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xEUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ 241 #define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0002000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ 242 #define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ 243 #define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0002FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ 244 #define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ 245 #define RDMEM_FRCRAM_NS_MEM_BASE (0xB0002000UL) /** RDMEM_FRCRAM_NS_MEM base address */ 246 #define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ 247 #define RDMEM_FRCRAM_NS_MEM_END (0xB0002FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ 248 #define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ 249 250 /** Flash and SRAM limits for EFR32MG21A010F512IM32 */ 251 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ 252 #define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ 253 #define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ 254 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ 255 #define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */ 256 #define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ 257 #define EXT_IRQ_COUNT 61 /**< Number of External (NVIC) interrupts */ 258 259 /* GPIO Avalibility Info */ 260 #define GPIO_PA_INDEX 0U /**< Index of port PA */ 261 #define GPIO_PA_COUNT 7U /**< Number of pins on port PA */ 262 #define GPIO_PA_MASK (0x007FUL) /**< Port PA pin mask */ 263 #define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ 264 #define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ 265 #define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ 266 #define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ 267 #define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ 268 #define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ 269 #define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ 270 #define GPIO_PB_INDEX 1U /**< Index of port PB */ 271 #define GPIO_PB_COUNT 2U /**< Number of pins on port PB */ 272 #define GPIO_PB_MASK (0x0003UL) /**< Port PB pin mask */ 273 #define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ 274 #define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ 275 #define GPIO_PC_INDEX 2U /**< Index of port PC */ 276 #define GPIO_PC_COUNT 6U /**< Number of pins on port PC */ 277 #define GPIO_PC_MASK (0x003FUL) /**< Port PC pin mask */ 278 #define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ 279 #define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ 280 #define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ 281 #define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ 282 #define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ 283 #define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ 284 #define GPIO_PD_INDEX 3U /**< Index of port PD */ 285 #define GPIO_PD_COUNT 5U /**< Number of pins on port PD */ 286 #define GPIO_PD_MASK (0x001FUL) /**< Port PD pin mask */ 287 #define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ 288 #define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ 289 #define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ 290 #define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ 291 #define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ 292 293 /* Fixed Resource Locations */ 294 #define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ 295 #define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ 296 #define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ 297 #define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ 298 #define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ 299 #define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ 300 #define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ 301 #define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ 302 #define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ 303 #define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ 304 #define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ 305 #define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ 306 #define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ 307 #define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ 308 #define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ 309 #define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ 310 #define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ 311 #define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ 312 #define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ 313 #define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ 314 #define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ 315 #define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ 316 #define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ 317 #define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ 318 #define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ 319 #define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ 320 #define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ 321 #define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ 322 #define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ 323 #define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ 324 #define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ 325 #define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ 326 327 /* Part number capabilities */ 328 #define ACMP_PRESENT /** ACMP is available in this part */ 329 #define ACMP_COUNT 2 /** 2 ACMPs available */ 330 #define AMUXCP_PRESENT /** AMUXCP is available in this part */ 331 #define AMUXCP_COUNT 1 /** 1 AMUXCPs available */ 332 #define BUFC_PRESENT /** BUFC is available in this part */ 333 #define BUFC_COUNT 1 /** 1 BUFCs available */ 334 #define BURAM_PRESENT /** BURAM is available in this part */ 335 #define BURAM_COUNT 1 /** 1 BURAMs available */ 336 #define BURTC_PRESENT /** BURTC is available in this part */ 337 #define BURTC_COUNT 1 /** 1 BURTCs available */ 338 #define CMU_PRESENT /** CMU is available in this part */ 339 #define CMU_COUNT 1 /** 1 CMUs available */ 340 #define DPLL_PRESENT /** DPLL is available in this part */ 341 #define DPLL_COUNT 1 /** 1 DPLLs available */ 342 #define EMU_PRESENT /** EMU is available in this part */ 343 #define EMU_COUNT 1 /** 1 EMUs available */ 344 #define FSRCO_PRESENT /** FSRCO is available in this part */ 345 #define FSRCO_COUNT 1 /** 1 FSRCOs available */ 346 #define GPCRC_PRESENT /** GPCRC is available in this part */ 347 #define GPCRC_COUNT 1 /** 1 GPCRCs available */ 348 #define GPIO_PRESENT /** GPIO is available in this part */ 349 #define GPIO_COUNT 1 /** 1 GPIOs available */ 350 #define HFRCO_PRESENT /** HFRCO is available in this part */ 351 #define HFRCO_COUNT 1 /** 1 HFRCOs available */ 352 #define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ 353 #define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ 354 #define HFXO_PRESENT /** HFXO is available in this part */ 355 #define HFXO_COUNT 1 /** 1 HFXOs available */ 356 #define I2C_PRESENT /** I2C is available in this part */ 357 #define I2C_COUNT 2 /** 2 I2Cs available */ 358 #define IADC_PRESENT /** IADC is available in this part */ 359 #define IADC_COUNT 1 /** 1 IADCs available */ 360 #define ICACHE_PRESENT /** ICACHE is available in this part */ 361 #define ICACHE_COUNT 1 /** 1 ICACHEs available */ 362 #define LDMA_PRESENT /** LDMA is available in this part */ 363 #define LDMA_COUNT 1 /** 1 LDMAs available */ 364 #define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ 365 #define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ 366 #define LETIMER_PRESENT /** LETIMER is available in this part */ 367 #define LETIMER_COUNT 1 /** 1 LETIMERs available */ 368 #define LFRCO_PRESENT /** LFRCO is available in this part */ 369 #define LFRCO_COUNT 1 /** 1 LFRCOs available */ 370 #define LFXO_PRESENT /** LFXO is available in this part */ 371 #define LFXO_COUNT 1 /** 1 LFXOs available */ 372 #define LVGD_PRESENT /** LVGD is available in this part */ 373 #define LVGD_COUNT 1 /** 1 LVGDs available */ 374 #define MSC_PRESENT /** MSC is available in this part */ 375 #define MSC_COUNT 1 /** 1 MSCs available */ 376 #define PRORTC_PRESENT /** PRORTC is available in this part */ 377 #define PRORTC_COUNT 1 /** 1 PRORTCs available */ 378 #define PRS_PRESENT /** PRS is available in this part */ 379 #define PRS_COUNT 1 /** 1 PRSs available */ 380 #define RADIOAES_PRESENT /** RADIOAES is available in this part */ 381 #define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ 382 #define RTCC_PRESENT /** RTCC is available in this part */ 383 #define RTCC_COUNT 1 /** 1 RTCCs available */ 384 #define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ 385 #define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ 386 #define SMU_PRESENT /** SMU is available in this part */ 387 #define SMU_COUNT 1 /** 1 SMUs available */ 388 #define SYSCFG_PRESENT /** SYSCFG is available in this part */ 389 #define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ 390 #define TIMER_PRESENT /** TIMER is available in this part */ 391 #define TIMER_COUNT 4 /** 4 TIMERs available */ 392 #define ULFRCO_PRESENT /** ULFRCO is available in this part */ 393 #define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ 394 #define USART_PRESENT /** USART is available in this part */ 395 #define USART_COUNT 3 /** 3 USARTs available */ 396 #define WDOG_PRESENT /** WDOG is available in this part */ 397 #define WDOG_COUNT 2 /** 2 WDOGs available */ 398 #define DEVINFO_PRESENT /** DEVINFO is available in this part */ 399 #define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ 400 401 /* Include standard ARM headers for the core */ 402 #include "core_cm33.h" /* Core Header File */ 403 #include "system_efr32mg21.h" /* System Header File */ 404 405 /** @} End of group EFR32MG21A010F512IM32_Part */ 406 407 /**************************************************************************//** 408 * @defgroup EFR32MG21A010F512IM32_Peripheral_TypeDefs EFR32MG21A010F512IM32 Peripheral TypeDefs 409 * @{ 410 * @brief Device Specific Peripheral Register Structures 411 *****************************************************************************/ 412 #include "efr32mg21_emu.h" 413 #include "efr32mg21_cmu.h" 414 #include "efr32mg21_hfxo.h" 415 #include "efr32mg21_hfrco.h" 416 #include "efr32mg21_fsrco.h" 417 #include "efr32mg21_dpll.h" 418 #include "efr32mg21_lfxo.h" 419 #include "efr32mg21_lfrco.h" 420 #include "efr32mg21_ulfrco.h" 421 #include "efr32mg21_msc.h" 422 #include "efr32mg21_icache.h" 423 #include "efr32mg21_prs.h" 424 #include "efr32mg21_gpio.h" 425 #include "efr32mg21_ldma.h" 426 #include "efr32mg21_ldmaxbar.h" 427 #include "efr32mg21_timer.h" 428 #include "efr32mg21_usart.h" 429 #include "efr32mg21_burtc.h" 430 #include "efr32mg21_i2c.h" 431 #include "efr32mg21_lvgd.h" 432 #include "efr32mg21_syscfg.h" 433 #include "efr32mg21_buram.h" 434 #include "efr32mg21_gpcrc.h" 435 #include "efr32mg21_aes.h" 436 #include "efr32mg21_bufc.h" 437 #include "efr32mg21_smu.h" 438 #include "efr32mg21_rtcc.h" 439 #include "efr32mg21_letimer.h" 440 #include "efr32mg21_iadc.h" 441 #include "efr32mg21_acmp.h" 442 #include "efr32mg21_wdog.h" 443 #include "efr32mg21_amuxcp.h" 444 #include "efr32mg21_semailbox.h" 445 #include "efr32mg21_devinfo.h" 446 447 /* Custom headers for LDMAXBAR and PRS mappings */ 448 #include "efr32mg21_prs_signals.h" 449 #include "efr32mg21_dma_descriptor.h" 450 #include "efr32mg21_ldmaxbar_defines.h" 451 452 /** @} End of group EFR32MG21A010F512IM32_Peripheral_TypeDefs */ 453 454 /**************************************************************************//** 455 * @defgroup EFR32MG21A010F512IM32_Peripheral_Base EFR32MG21A010F512IM32 Peripheral Memory Map 456 * @{ 457 *****************************************************************************/ 458 459 #define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ 460 #define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ 461 #define HFXO0_S_BASE (0x4000C000UL) /* HFXO0_S base address */ 462 #define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ 463 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ 464 #define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ 465 #define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ 466 #define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ 467 #define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ 468 #define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ 469 #define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ 470 #define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ 471 #define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ 472 #define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ 473 #define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ 474 #define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ 475 #define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ 476 #define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ 477 #define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ 478 #define USART0_S_BASE (0x40058000UL) /* USART0_S base address */ 479 #define USART1_S_BASE (0x4005C000UL) /* USART1_S base address */ 480 #define USART2_S_BASE (0x40060000UL) /* USART2_S base address */ 481 #define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ 482 #define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ 483 #define LVGD_S_BASE (0x40074000UL) /* LVGD_S base address */ 484 #define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ 485 #define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ 486 #define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ 487 #define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ 488 #define BUFC_S_BASE (0x44004000UL) /* BUFC_S base address */ 489 #define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ 490 #define RTCC_S_BASE (0x48000000UL) /* RTCC_S base address */ 491 #define LETIMER0_S_BASE (0x4A000000UL) /* LETIMER0_S base address */ 492 #define IADC0_S_BASE (0x4A004000UL) /* IADC0_S base address */ 493 #define ACMP0_S_BASE (0x4A008000UL) /* ACMP0_S base address */ 494 #define ACMP1_S_BASE (0x4A00C000UL) /* ACMP1_S base address */ 495 #define I2C0_S_BASE (0x4A010000UL) /* I2C0_S base address */ 496 #define HFRCOEM23_S_BASE (0x4A014000UL) /* HFRCOEM23_S base address */ 497 #define WDOG0_S_BASE (0x4A018000UL) /* WDOG0_S base address */ 498 #define WDOG1_S_BASE (0x4A01C000UL) /* WDOG1_S base address */ 499 #define AMUXCP0_S_BASE (0x4A020000UL) /* AMUXCP0_S base address */ 500 #define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ 501 #define PRORTC_S_BASE (0xA8000000UL) /* PRORTC_S base address */ 502 #define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ 503 #define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ 504 #define HFXO0_NS_BASE (0x5000C000UL) /* HFXO0_NS base address */ 505 #define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ 506 #define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ 507 #define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ 508 #define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ 509 #define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ 510 #define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ 511 #define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ 512 #define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ 513 #define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ 514 #define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ 515 #define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ 516 #define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ 517 #define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ 518 #define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ 519 #define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ 520 #define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ 521 #define USART0_NS_BASE (0x50058000UL) /* USART0_NS base address */ 522 #define USART1_NS_BASE (0x5005C000UL) /* USART1_NS base address */ 523 #define USART2_NS_BASE (0x50060000UL) /* USART2_NS base address */ 524 #define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ 525 #define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ 526 #define LVGD_NS_BASE (0x50074000UL) /* LVGD_NS base address */ 527 #define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ 528 #define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ 529 #define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ 530 #define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ 531 #define BUFC_NS_BASE (0x54004000UL) /* BUFC_NS base address */ 532 #define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ 533 #define RTCC_NS_BASE (0x58000000UL) /* RTCC_NS base address */ 534 #define LETIMER0_NS_BASE (0x5A000000UL) /* LETIMER0_NS base address */ 535 #define IADC0_NS_BASE (0x5A004000UL) /* IADC0_NS base address */ 536 #define ACMP0_NS_BASE (0x5A008000UL) /* ACMP0_NS base address */ 537 #define ACMP1_NS_BASE (0x5A00C000UL) /* ACMP1_NS base address */ 538 #define I2C0_NS_BASE (0x5A010000UL) /* I2C0_NS base address */ 539 #define HFRCOEM23_NS_BASE (0x5A014000UL) /* HFRCOEM23_NS base address */ 540 #define WDOG0_NS_BASE (0x5A018000UL) /* WDOG0_NS base address */ 541 #define WDOG1_NS_BASE (0x5A01C000UL) /* WDOG1_NS base address */ 542 #define AMUXCP0_NS_BASE (0x5A020000UL) /* AMUXCP0_NS base address */ 543 #define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ 544 #define PRORTC_NS_BASE (0xB8000000UL) /* PRORTC_NS base address */ 545 546 #if defined(SL_COMPONENT_CATALOG_PRESENT) 547 #include "sl_component_catalog.h" 548 549 #endif 550 #if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) 551 #include "sl_trustzone_secure_config.h" 552 553 #endif 554 555 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) 556 #define EMU_BASE (EMU_S_BASE) /* EMU base address */ 557 #else 558 #define EMU_BASE (EMU_NS_BASE) /* EMU base address */ 559 #endif /* SL_TRUSTZONE_PERIPHERAL_EMU_S */ 560 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) 561 #define CMU_BASE (CMU_S_BASE) /* CMU base address */ 562 #else 563 #define CMU_BASE (CMU_NS_BASE) /* CMU base address */ 564 #endif /* SL_TRUSTZONE_PERIPHERAL_CMU_S */ 565 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) 566 #define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ 567 #else 568 #define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ 569 #endif /* SL_TRUSTZONE_PERIPHERAL_HFXO0_S */ 570 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) 571 #define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ 572 #else 573 #define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ 574 #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCO0_S */ 575 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) 576 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ 577 #else 578 #define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ 579 #endif /* SL_TRUSTZONE_PERIPHERAL_FSRCO_S */ 580 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) 581 #define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ 582 #else 583 #define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ 584 #endif /* SL_TRUSTZONE_PERIPHERAL_DPLL0_S */ 585 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) 586 #define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ 587 #else 588 #define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ 589 #endif /* SL_TRUSTZONE_PERIPHERAL_LFXO_S */ 590 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) 591 #define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ 592 #else 593 #define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ 594 #endif /* SL_TRUSTZONE_PERIPHERAL_LFRCO_S */ 595 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) 596 #define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ 597 #else 598 #define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ 599 #endif /* SL_TRUSTZONE_PERIPHERAL_ULFRCO_S */ 600 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) 601 #define MSC_BASE (MSC_S_BASE) /* MSC base address */ 602 #else 603 #define MSC_BASE (MSC_NS_BASE) /* MSC base address */ 604 #endif /* SL_TRUSTZONE_PERIPHERAL_MSC_S */ 605 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) 606 #define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ 607 #else 608 #define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ 609 #endif /* SL_TRUSTZONE_PERIPHERAL_ICACHE0_S */ 610 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) 611 #define PRS_BASE (PRS_S_BASE) /* PRS base address */ 612 #else 613 #define PRS_BASE (PRS_NS_BASE) /* PRS base address */ 614 #endif /* SL_TRUSTZONE_PERIPHERAL_PRS_S */ 615 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) 616 #define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ 617 #else 618 #define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ 619 #endif /* SL_TRUSTZONE_PERIPHERAL_GPIO_S */ 620 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) 621 #define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ 622 #else 623 #define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ 624 #endif /* SL_TRUSTZONE_PERIPHERAL_LDMA_S */ 625 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) 626 #define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ 627 #else 628 #define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ 629 #endif /* SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S */ 630 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) 631 #define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ 632 #else 633 #define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ 634 #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER0_S */ 635 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) 636 #define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ 637 #else 638 #define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ 639 #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER1_S */ 640 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) 641 #define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ 642 #else 643 #define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ 644 #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER2_S */ 645 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) 646 #define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ 647 #else 648 #define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ 649 #endif /* SL_TRUSTZONE_PERIPHERAL_TIMER3_S */ 650 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) 651 #define USART0_BASE (USART0_S_BASE) /* USART0 base address */ 652 #else 653 #define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ 654 #endif /* SL_TRUSTZONE_PERIPHERAL_USART0_S */ 655 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) 656 #define USART1_BASE (USART1_S_BASE) /* USART1 base address */ 657 #else 658 #define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ 659 #endif /* SL_TRUSTZONE_PERIPHERAL_USART1_S */ 660 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART2_S) && (SL_TRUSTZONE_PERIPHERAL_USART2_S != 0))) 661 #define USART2_BASE (USART2_S_BASE) /* USART2 base address */ 662 #else 663 #define USART2_BASE (USART2_NS_BASE) /* USART2 base address */ 664 #endif /* SL_TRUSTZONE_PERIPHERAL_USART2_S */ 665 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) 666 #define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ 667 #else 668 #define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ 669 #endif /* SL_TRUSTZONE_PERIPHERAL_BURTC_S */ 670 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) 671 #define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ 672 #else 673 #define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ 674 #endif /* SL_TRUSTZONE_PERIPHERAL_I2C1_S */ 675 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LVGD_S) && (SL_TRUSTZONE_PERIPHERAL_LVGD_S != 0))) 676 #define LVGD_BASE (LVGD_S_BASE) /* LVGD base address */ 677 #else 678 #define LVGD_BASE (LVGD_NS_BASE) /* LVGD base address */ 679 #endif /* SL_TRUSTZONE_PERIPHERAL_LVGD_S */ 680 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) 681 #define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ 682 #else 683 #define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ 684 #endif /* SL_TRUSTZONE_PERIPHERAL_SYSCFG_S */ 685 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) 686 #define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ 687 #else 688 #define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ 689 #endif /* SL_TRUSTZONE_PERIPHERAL_BURAM_S */ 690 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) 691 #define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ 692 #else 693 #define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ 694 #endif /* SL_TRUSTZONE_PERIPHERAL_GPCRC_S */ 695 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) 696 #define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ 697 #else 698 #define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ 699 #endif /* SL_TRUSTZONE_PERIPHERAL_RADIOAES_S */ 700 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BUFC_S) && (SL_TRUSTZONE_PERIPHERAL_BUFC_S != 0))) 701 #define BUFC_BASE (BUFC_S_BASE) /* BUFC base address */ 702 #else 703 #define BUFC_BASE (BUFC_NS_BASE) /* BUFC base address */ 704 #endif /* SL_TRUSTZONE_PERIPHERAL_BUFC_S */ 705 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) 706 #define SMU_BASE (SMU_S_BASE) /* SMU base address */ 707 #else 708 #define SMU_BASE (SMU_S_BASE) /* SMU base address */ 709 #endif /* SL_TRUSTZONE_PERIPHERAL_SMU_S */ 710 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) 711 #define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ 712 #else 713 #define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ 714 #endif /* SL_TRUSTZONE_PERIPHERAL_RTCC_S */ 715 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) 716 #define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ 717 #else 718 #define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ 719 #endif /* SL_TRUSTZONE_PERIPHERAL_LETIMER0_S */ 720 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) 721 #define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ 722 #else 723 #define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ 724 #endif /* SL_TRUSTZONE_PERIPHERAL_IADC0_S */ 725 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) 726 #define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ 727 #else 728 #define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ 729 #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP0_S */ 730 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) 731 #define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ 732 #else 733 #define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ 734 #endif /* SL_TRUSTZONE_PERIPHERAL_ACMP1_S */ 735 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) 736 #define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ 737 #else 738 #define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ 739 #endif /* SL_TRUSTZONE_PERIPHERAL_I2C0_S */ 740 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) 741 #define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ 742 #else 743 #define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ 744 #endif /* SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S */ 745 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) 746 #define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ 747 #else 748 #define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ 749 #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG0_S */ 750 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) 751 #define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ 752 #else 753 #define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ 754 #endif /* SL_TRUSTZONE_PERIPHERAL_WDOG1_S */ 755 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S) && (SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S != 0))) 756 #define AMUXCP0_BASE (AMUXCP0_S_BASE) /* AMUXCP0 base address */ 757 #else 758 #define AMUXCP0_BASE (AMUXCP0_NS_BASE) /* AMUXCP0 base address */ 759 #endif /* SL_TRUSTZONE_PERIPHERAL_AMUXCP0_S */ 760 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) 761 #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ 762 #else 763 #define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ 764 #endif /* SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S */ 765 #if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) 766 #define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ 767 #else 768 #define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ 769 #endif /* SL_TRUSTZONE_PERIPHERAL_PRORTC_S */ 770 771 #define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ 772 /** @} End of group EFR32MG21A010F512IM32_Peripheral_Base */ 773 774 /**************************************************************************//** 775 * @defgroup EFR32MG21A010F512IM32_Peripheral_Declaration EFR32MG21A010F512IM32 Peripheral Declarations Map 776 * @{ 777 *****************************************************************************/ 778 779 #define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ 780 #define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ 781 #define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ 782 #define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ 783 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ 784 #define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ 785 #define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ 786 #define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ 787 #define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ 788 #define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ 789 #define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ 790 #define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ 791 #define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ 792 #define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ 793 #define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ 794 #define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ 795 #define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ 796 #define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ 797 #define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ 798 #define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ 799 #define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ 800 #define USART2_S ((USART_TypeDef *) USART2_S_BASE) /**< USART2_S base pointer */ 801 #define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ 802 #define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ 803 #define LVGD_S ((LVGD_TypeDef *) LVGD_S_BASE) /**< LVGD_S base pointer */ 804 #define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ 805 #define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ 806 #define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ 807 #define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ 808 #define BUFC_S ((BUFC_TypeDef *) BUFC_S_BASE) /**< BUFC_S base pointer */ 809 #define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ 810 #define RTCC_S ((RTCC_TypeDef *) RTCC_S_BASE) /**< RTCC_S base pointer */ 811 #define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ 812 #define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ 813 #define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ 814 #define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ 815 #define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ 816 #define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ 817 #define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ 818 #define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ 819 #define AMUXCP0_S ((AMUXCP_TypeDef *) AMUXCP0_S_BASE) /**< AMUXCP0_S base pointer */ 820 #define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ 821 #define PRORTC_S ((RTCC_TypeDef *) PRORTC_S_BASE) /**< PRORTC_S base pointer */ 822 #define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ 823 #define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ 824 #define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ 825 #define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ 826 #define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ 827 #define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ 828 #define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ 829 #define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ 830 #define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ 831 #define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ 832 #define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ 833 #define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ 834 #define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ 835 #define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ 836 #define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ 837 #define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ 838 #define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ 839 #define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ 840 #define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ 841 #define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ 842 #define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ 843 #define USART2_NS ((USART_TypeDef *) USART2_NS_BASE) /**< USART2_NS base pointer */ 844 #define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ 845 #define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ 846 #define LVGD_NS ((LVGD_TypeDef *) LVGD_NS_BASE) /**< LVGD_NS base pointer */ 847 #define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ 848 #define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ 849 #define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ 850 #define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ 851 #define BUFC_NS ((BUFC_TypeDef *) BUFC_NS_BASE) /**< BUFC_NS base pointer */ 852 #define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ 853 #define RTCC_NS ((RTCC_TypeDef *) RTCC_NS_BASE) /**< RTCC_NS base pointer */ 854 #define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ 855 #define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ 856 #define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ 857 #define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ 858 #define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ 859 #define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ 860 #define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ 861 #define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ 862 #define AMUXCP0_NS ((AMUXCP_TypeDef *) AMUXCP0_NS_BASE) /**< AMUXCP0_NS base pointer */ 863 #define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ 864 #define PRORTC_NS ((RTCC_TypeDef *) PRORTC_NS_BASE) /**< PRORTC_NS base pointer */ 865 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ 866 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ 867 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ 868 #define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ 869 #define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ 870 #define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ 871 #define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ 872 #define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ 873 #define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ 874 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ 875 #define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ 876 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ 877 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ 878 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ 879 #define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ 880 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ 881 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ 882 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ 883 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ 884 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ 885 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ 886 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ 887 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ 888 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ 889 #define LVGD ((LVGD_TypeDef *) LVGD_BASE) /**< LVGD base pointer */ 890 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ 891 #define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ 892 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ 893 #define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ 894 #define BUFC ((BUFC_TypeDef *) BUFC_BASE) /**< BUFC base pointer */ 895 #define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ 896 #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ 897 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ 898 #define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ 899 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ 900 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ 901 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ 902 #define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ 903 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ 904 #define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ 905 #define AMUXCP0 ((AMUXCP_TypeDef *) AMUXCP0_BASE) /**< AMUXCP0 base pointer */ 906 #define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ 907 #define PRORTC ((RTCC_TypeDef *) PRORTC_BASE) /**< PRORTC base pointer */ 908 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ 909 /** @} End of group EFR32MG21A010F512IM32_Peripheral_Declaration */ 910 911 /**************************************************************************//** 912 * @defgroup EFR32MG21A010F512IM32_Peripheral_Parameters EFR32MG21A010F512IM32 Peripheral Parameters 913 * @{ 914 * @brief Device peripheral parameter values 915 *****************************************************************************/ 916 917 /* Common peripheral register block offsets. */ 918 #define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ 919 #define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ 920 #define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ 921 #define MSC_FDIO_WIDTH 0x40UL /**> None */ 922 #define MSC_FLASHADDRBITS 0x14UL /**> None */ 923 #define MSC_FLASHBLOCKADDRBITS 0x14UL /**> None */ 924 #define MSC_FLASH_BLOCK_INFO_PCOUNT 0x10UL /**> None */ 925 #define MSC_INFOADDRBITS 0x10UL /**> None */ 926 #define MSC_INFOBLOCKADDRBITS 0x10UL /**> None */ 927 #define MSC_INFO_PSIZE_BITS 0xCUL /**> None */ 928 #define MSC_MAIN_PSIZE_BITS 0xCUL /**> None */ 929 #define MSC_REDUNDANCY 0x2UL /**> None */ 930 #define MSC_YADDRBITS 0x7UL /**> None */ 931 #define DMEM_ADDR_OVERRIDE_BITS 0x8UL /**> Override bits for remapping */ 932 #define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 Size */ 933 #define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 Size */ 934 #define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 Size */ 935 #define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 Size */ 936 #define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 Size */ 937 #define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 Size */ 938 #define DMEM_BANK6_SIZE 0x0UL /**> Bank6 Size */ 939 #define DMEM_BANK7_SIZE 0x0UL /**> Bank7 Size */ 940 #define DMEM_NUM_BANK 0x6UL /**> Number of Banks */ 941 #define DMEM_RAMADDRBITS 0x11UL /**> Total address bits */ 942 #define DMEM_RAMADDRMINBITS 0xEUL /**> address bits for one bank */ 943 #define DMEM_RAM_BWE_WIDTH 0x27UL /**> Bitwise write enable */ 944 #define DMEM_RAM_DATA_WIDTH 0x27UL /**> Data width */ 945 #define DMEM_RAM_DIV_PRESENT 0x0UL /**> Bank0 division present */ 946 #define DMEM_RAM_ECCADDR_WIDTH 0x20UL /**> ECC Address width */ 947 #define DMEM_RAM_ECC_EN 0x1UL /**> RAM_ECC_EN_PRESENT */ 948 #define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ 949 #define LFXO_CTUNE 0x1UL /**> CTUNE Present */ 950 #define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ 951 #define ICACHE0_CACHEABLE_SIZE 0x200UL /**> Cache Size */ 952 #define ICACHE0_CACHEABLE_START 0x12UL /**> Cache Start */ 953 #define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ 954 #define ICACHE0_FLASH_SIZE 0x100000UL /**> Flash size */ 955 #define ICACHE0_FLASH_START 0x0UL /**> Flash start */ 956 #define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ 957 #define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ 958 #define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ 959 #define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ 960 #define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ 961 #define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ 962 #define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ 963 #define ICACHE0_SET_BITS 0x5UL /**> Set bits */ 964 #define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ 965 #define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ 966 #define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ 967 #define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ 968 #define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ 969 #define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ 970 #define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ 971 #define PRS_ASYNC_CH_NUM 0xCUL /**> None */ 972 #define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ 973 #define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ 974 #define PRS_SYNC_CH_NUM 0x4UL /**> None */ 975 #define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ 976 #define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ 977 #define GPIO_NUM_EVEN_PA 0x4UL /**> Num of even pins port A */ 978 #define GPIO_NUM_EVEN_PB 0x1UL /**> Num of even pins port B */ 979 #define GPIO_NUM_EVEN_PC 0x3UL /**> Num of even pins port C */ 980 #define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ 981 #define GPIO_NUM_EXT_INT 0x8UL /**> New Param */ 982 #define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ 983 #define GPIO_NUM_EXT_INT_U 0x0UL /**> New Param */ 984 #define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ 985 #define GPIO_NUM_ODD_PA 0x3UL /**> Num of odd pins port A */ 986 #define GPIO_NUM_ODD_PB 0x1UL /**> Num of odd pins port B */ 987 #define GPIO_NUM_ODD_PC 0x3UL /**> Num of odd pins port C */ 988 #define GPIO_NUM_ODD_PD 0x2UL /**> Num of odd pins port D */ 989 #define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ 990 #define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ 991 #define GPIO_PORT_A_WIDTH 0x7UL /**> Port A Width */ 992 #define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ 993 #define GPIO_PORT_A_WL 0x7UL /**> New Param */ 994 #define GPIO_PORT_A_WU 0x0UL /**> New Param */ 995 #define GPIO_PORT_A_WU_ZERO 0x1UL /**> New Param */ 996 #define GPIO_PORT_B_WIDTH 0x2UL /**> Port B Width */ 997 #define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ 998 #define GPIO_PORT_B_WL 0x2UL /**> New Param */ 999 #define GPIO_PORT_B_WU 0x0UL /**> New Param */ 1000 #define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ 1001 #define GPIO_PORT_C_WIDTH 0x6UL /**> Port C Width */ 1002 #define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ 1003 #define GPIO_PORT_C_WL 0x6UL /**> New Param */ 1004 #define GPIO_PORT_C_WU 0x0UL /**> New Param */ 1005 #define GPIO_PORT_C_WU_ZERO 0x1UL /**> New Param */ 1006 #define GPIO_PORT_D_WIDTH 0x5UL /**> Port D Width */ 1007 #define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ 1008 #define GPIO_PORT_D_WL 0x5UL /**> New Param */ 1009 #define GPIO_PORT_D_WU 0x0UL /**> New Param */ 1010 #define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ 1011 #define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ 1012 #define LDMA_CH_BITS 0x5UL /**> New Param */ 1013 #define LDMA_CH_NUM 0x8UL /**> New Param */ 1014 #define LDMA_FIFO_BITS 0x5UL /**> New Param */ 1015 #define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ 1016 #define LDMAXBAR_CH_BITS 0x5UL /**> None */ 1017 #define LDMAXBAR_CH_NUM 0x8UL /**> None */ 1018 #define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ 1019 #define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ 1020 #define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1021 #define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ 1022 #define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ 1023 #define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1024 #define TIMER0_NO_DTI 0x0UL /**> */ 1025 #define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1026 #define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ 1027 #define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ 1028 #define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1029 #define TIMER1_NO_DTI 0x0UL /**> */ 1030 #define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1031 #define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ 1032 #define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ 1033 #define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1034 #define TIMER2_NO_DTI 0x0UL /**> */ 1035 #define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ 1036 #define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ 1037 #define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ 1038 #define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ 1039 #define TIMER3_NO_DTI 0x0UL /**> */ 1040 #define USART0_AUTOTX_REG 0x1UL /**> None */ 1041 #define USART0_AUTOTX_REG_B 0x0UL /**> None */ 1042 #define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ 1043 #define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ 1044 #define USART0_CLK_PRS 0x1UL /**> None */ 1045 #define USART0_CLK_PRS_B 0x0UL /**> New Param */ 1046 #define USART0_FLOW_CONTROL 0x1UL /**> None */ 1047 #define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ 1048 #define USART0_I2S 0x1UL /**> None */ 1049 #define USART0_I2S_B 0x0UL /**> New Param */ 1050 #define USART0_IRDA_AVAILABLE 0x1UL /**> None */ 1051 #define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ 1052 #define USART0_MVDIS_FUNC 0x1UL /**> None */ 1053 #define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ 1054 #define USART0_RX_PRS 0x1UL /**> None */ 1055 #define USART0_RX_PRS_B 0x0UL /**> New Param */ 1056 #define USART0_SC_AVAILABLE 0x1UL /**> None */ 1057 #define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ 1058 #define USART0_SYNC_AVAILABLE 0x1UL /**> None */ 1059 #define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ 1060 #define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ 1061 #define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ 1062 #define USART0_TIMER 0x1UL /**> New Param */ 1063 #define USART0_TIMER_B 0x0UL /**> New Param */ 1064 #define USART1_AUTOTX_REG 0x1UL /**> None */ 1065 #define USART1_AUTOTX_REG_B 0x0UL /**> None */ 1066 #define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ 1067 #define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ 1068 #define USART1_CLK_PRS 0x1UL /**> None */ 1069 #define USART1_CLK_PRS_B 0x0UL /**> New Param */ 1070 #define USART1_FLOW_CONTROL 0x1UL /**> None */ 1071 #define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ 1072 #define USART1_I2S 0x1UL /**> None */ 1073 #define USART1_I2S_B 0x0UL /**> New Param */ 1074 #define USART1_IRDA_AVAILABLE 0x1UL /**> None */ 1075 #define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ 1076 #define USART1_MVDIS_FUNC 0x1UL /**> None */ 1077 #define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ 1078 #define USART1_RX_PRS 0x1UL /**> None */ 1079 #define USART1_RX_PRS_B 0x0UL /**> New Param */ 1080 #define USART1_SC_AVAILABLE 0x1UL /**> None */ 1081 #define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ 1082 #define USART1_SYNC_AVAILABLE 0x1UL /**> None */ 1083 #define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ 1084 #define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ 1085 #define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ 1086 #define USART1_TIMER 0x1UL /**> New Param */ 1087 #define USART1_TIMER_B 0x0UL /**> New Param */ 1088 #define USART2_AUTOTX_REG 0x1UL /**> None */ 1089 #define USART2_AUTOTX_REG_B 0x0UL /**> None */ 1090 #define USART2_AUTOTX_TRIGGER 0x1UL /**> None */ 1091 #define USART2_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ 1092 #define USART2_CLK_PRS 0x1UL /**> None */ 1093 #define USART2_CLK_PRS_B 0x0UL /**> New Param */ 1094 #define USART2_FLOW_CONTROL 0x1UL /**> None */ 1095 #define USART2_FLOW_CONTROL_B 0x0UL /**> New Param */ 1096 #define USART2_I2S 0x1UL /**> None */ 1097 #define USART2_I2S_B 0x0UL /**> New Param */ 1098 #define USART2_IRDA_AVAILABLE 0x1UL /**> None */ 1099 #define USART2_IRDA_AVAILABLE_B 0x0UL /**> New Param */ 1100 #define USART2_MVDIS_FUNC 0x1UL /**> None */ 1101 #define USART2_MVDIS_FUNC_B 0x0UL /**> New Param */ 1102 #define USART2_RX_PRS 0x1UL /**> None */ 1103 #define USART2_RX_PRS_B 0x0UL /**> New Param */ 1104 #define USART2_SC_AVAILABLE 0x1UL /**> None */ 1105 #define USART2_SC_AVAILABLE_B 0x0UL /**> New Param */ 1106 #define USART2_SYNC_AVAILABLE 0x1UL /**> None */ 1107 #define USART2_SYNC_AVAILABLE_B 0x0UL /**> New Param */ 1108 #define USART2_SYNC_LATE_SAMPLE 0x1UL /**> None */ 1109 #define USART2_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ 1110 #define USART2_TIMER 0x1UL /**> New Param */ 1111 #define USART2_TIMER_B 0x0UL /**> New Param */ 1112 #define BURTC_CNTWIDTH 0x20UL /**> None */ 1113 #define BURTC_PRECNT_WIDTH 0xFUL /**> */ 1114 #define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ 1115 #define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ 1116 #define SYSCFG_CHIP_FAMILY 0x30UL /**> CHIP Family */ 1117 #define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ 1118 #define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ 1119 #define SYSCFG_RAM0_INST_COUNT 0x6UL /**> None */ 1120 #define SYSCFG_SEQRAM_INST_COUNT 0x1UL /**> None */ 1121 #define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ 1122 #define BUFC_LOG2NUMOFBUFS 0x2UL /**> New Param */ 1123 #define BUFC_LOG2NUMOFINPUTS 0x1UL /**> New Param */ 1124 #define BUFC_NUMOFBUFS 0x4UL /**> New Param */ 1125 #define BUFC_NUMOFINPUTS 0x1UL /**> New Param */ 1126 #define RTCC_CC_NUM 0x3UL /**> None */ 1127 #define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ 1128 #define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ 1129 #define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ 1130 #define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ 1131 #define IADC0_ENTRIES 0x10UL /**> ENTRIES */ 1132 #define ACMP0_DAC_INPUT 0x0UL /**> None */ 1133 #define ACMP0_EXT_OVR_IF 0x0UL /**> None */ 1134 #define ACMP1_DAC_INPUT 0x0UL /**> None */ 1135 #define ACMP1_EXT_OVR_IF 0x0UL /**> None */ 1136 #define I2C0_DELAY 0x7D0UL /**> Delay cell selection */ 1137 #define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ 1138 #define WDOG0_PCNUM 0x2UL /**> None */ 1139 #define WDOG1_PCNUM 0x2UL /**> None */ 1140 #define AMUXCP0_AMUXCPNUM 0x0UL /**> AMUXCPNUM */ 1141 #define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ 1142 #define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ 1143 #define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ 1144 #define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ 1145 #define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ 1146 #define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ 1147 #define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ 1148 #define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ 1149 #define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ 1150 #define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ 1151 #define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ 1152 #define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ 1153 #define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ 1154 #define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ 1155 #define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ 1156 #define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ 1157 #define RDMEM_SEQ_BANK1_SIZE 0x0UL /**> SEQ_RAM_BANK1_SIZE */ 1158 #define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ 1159 #define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ 1160 #define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ 1161 #define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ 1162 #define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ 1163 #define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ 1164 #define RDMEM_SEQ_NUM_BANK 0x1UL /**> SEQ_NUM_BANK */ 1165 #define RDMEM_SEQ_RAMADDRBITS 0xDUL /**> SEQ RAM ADDRBITS */ 1166 #define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ 1167 #define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ 1168 #define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ 1169 #define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ 1170 #define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ 1171 #define PRORTC_CC_NUM 0x2UL /**> None */ 1172 1173 /* Instance macros for ACMP */ 1174 #define ACMP(n) (((n) == 0) ? ACMP0 \ 1175 : ((n) == 1) ? ACMP1 \ 1176 : 0x0UL) 1177 #define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ 1178 : ((ref) == ACMP1) ? 1 \ 1179 : -1) 1180 #define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ 1181 : ((n) == 1) ? ACMP1_DAC_INPUT \ 1182 : 0x0UL) 1183 #define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ 1184 : ((n) == 1) ? ACMP1_EXT_OVR_IF \ 1185 : 0x0UL) 1186 1187 /* Instance macros for HFRCO */ 1188 #define HFRCO(n) (((n) == 0) ? HFRCO0 \ 1189 : ((n) == 1) ? HFRCOEM23 \ 1190 : 0x0UL) 1191 #define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ 1192 : ((ref) == HFRCOEM23) ? 1 \ 1193 : -1) 1194 1195 /* Instance macros for I2C */ 1196 #define I2C(n) (((n) == 0) ? I2C0 \ 1197 : ((n) == 1) ? I2C1 \ 1198 : 0x0UL) 1199 #define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ 1200 : ((ref) == I2C1) ? 1 \ 1201 : -1) 1202 #define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ 1203 : ((n) == 1) ? I2C1_DELAY \ 1204 : 0x0UL) 1205 #define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ 1206 : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ 1207 : 0x0UL) 1208 1209 /* Instance macros for TIMER */ 1210 #define TIMER(n) (((n) == 0) ? TIMER0 \ 1211 : ((n) == 1) ? TIMER1 \ 1212 : ((n) == 2) ? TIMER2 \ 1213 : ((n) == 3) ? TIMER3 \ 1214 : 0x0UL) 1215 #define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ 1216 : ((ref) == TIMER1) ? 1 \ 1217 : ((ref) == TIMER2) ? 2 \ 1218 : ((ref) == TIMER3) ? 3 \ 1219 : -1) 1220 #define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ 1221 : ((n) == 1) ? TIMER1_CC_NUM \ 1222 : ((n) == 2) ? TIMER2_CC_NUM \ 1223 : ((n) == 3) ? TIMER3_CC_NUM \ 1224 : 0x0UL) 1225 #define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ 1226 : ((n) == 1) ? TIMER1_CNTWIDTH \ 1227 : ((n) == 2) ? TIMER2_CNTWIDTH \ 1228 : ((n) == 3) ? TIMER3_CNTWIDTH \ 1229 : 0x0UL) 1230 #define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ 1231 : ((n) == 1) ? TIMER1_DTI \ 1232 : ((n) == 2) ? TIMER2_DTI \ 1233 : ((n) == 3) ? TIMER3_DTI \ 1234 : 0x0UL) 1235 #define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ 1236 : ((n) == 1) ? TIMER1_DTI_CC_NUM \ 1237 : ((n) == 2) ? TIMER2_DTI_CC_NUM \ 1238 : ((n) == 3) ? TIMER3_DTI_CC_NUM \ 1239 : 0x0UL) 1240 #define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ 1241 : ((n) == 1) ? TIMER1_NO_DTI \ 1242 : ((n) == 2) ? TIMER2_NO_DTI \ 1243 : ((n) == 3) ? TIMER3_NO_DTI \ 1244 : 0x0UL) 1245 1246 /* Instance macros for USART */ 1247 #define USART(n) (((n) == 0) ? USART0 \ 1248 : ((n) == 1) ? USART1 \ 1249 : ((n) == 2) ? USART2 \ 1250 : 0x0UL) 1251 #define USART_NUM(ref) (((ref) == USART0) ? 0 \ 1252 : ((ref) == USART1) ? 1 \ 1253 : ((ref) == USART2) ? 2 \ 1254 : -1) 1255 #define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ 1256 : ((n) == 1) ? USART1_AUTOTX_REG \ 1257 : ((n) == 2) ? USART2_AUTOTX_REG \ 1258 : 0x0UL) 1259 #define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ 1260 : ((n) == 1) ? USART1_AUTOTX_REG_B \ 1261 : ((n) == 2) ? USART2_AUTOTX_REG_B \ 1262 : 0x0UL) 1263 #define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ 1264 : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ 1265 : ((n) == 2) ? USART2_AUTOTX_TRIGGER \ 1266 : 0x0UL) 1267 #define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ 1268 : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ 1269 : ((n) == 2) ? USART2_AUTOTX_TRIGGER_B \ 1270 : 0x0UL) 1271 #define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ 1272 : ((n) == 1) ? USART1_CLK_PRS \ 1273 : ((n) == 2) ? USART2_CLK_PRS \ 1274 : 0x0UL) 1275 #define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ 1276 : ((n) == 1) ? USART1_CLK_PRS_B \ 1277 : ((n) == 2) ? USART2_CLK_PRS_B \ 1278 : 0x0UL) 1279 #define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ 1280 : ((n) == 1) ? USART1_FLOW_CONTROL \ 1281 : ((n) == 2) ? USART2_FLOW_CONTROL \ 1282 : 0x0UL) 1283 #define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ 1284 : ((n) == 1) ? USART1_FLOW_CONTROL_B \ 1285 : ((n) == 2) ? USART2_FLOW_CONTROL_B \ 1286 : 0x0UL) 1287 #define USART_I2S(n) (((n) == 0) ? USART0_I2S \ 1288 : ((n) == 1) ? USART1_I2S \ 1289 : ((n) == 2) ? USART2_I2S \ 1290 : 0x0UL) 1291 #define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ 1292 : ((n) == 1) ? USART1_I2S_B \ 1293 : ((n) == 2) ? USART2_I2S_B \ 1294 : 0x0UL) 1295 #define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ 1296 : ((n) == 1) ? USART1_IRDA_AVAILABLE \ 1297 : ((n) == 2) ? USART2_IRDA_AVAILABLE \ 1298 : 0x0UL) 1299 #define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ 1300 : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ 1301 : ((n) == 2) ? USART2_IRDA_AVAILABLE_B \ 1302 : 0x0UL) 1303 #define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ 1304 : ((n) == 1) ? USART1_MVDIS_FUNC \ 1305 : ((n) == 2) ? USART2_MVDIS_FUNC \ 1306 : 0x0UL) 1307 #define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ 1308 : ((n) == 1) ? USART1_MVDIS_FUNC_B \ 1309 : ((n) == 2) ? USART2_MVDIS_FUNC_B \ 1310 : 0x0UL) 1311 #define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ 1312 : ((n) == 1) ? USART1_RX_PRS \ 1313 : ((n) == 2) ? USART2_RX_PRS \ 1314 : 0x0UL) 1315 #define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ 1316 : ((n) == 1) ? USART1_RX_PRS_B \ 1317 : ((n) == 2) ? USART2_RX_PRS_B \ 1318 : 0x0UL) 1319 #define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ 1320 : ((n) == 1) ? USART1_SC_AVAILABLE \ 1321 : ((n) == 2) ? USART2_SC_AVAILABLE \ 1322 : 0x0UL) 1323 #define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ 1324 : ((n) == 1) ? USART1_SC_AVAILABLE_B \ 1325 : ((n) == 2) ? USART2_SC_AVAILABLE_B \ 1326 : 0x0UL) 1327 #define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ 1328 : ((n) == 1) ? USART1_SYNC_AVAILABLE \ 1329 : ((n) == 2) ? USART2_SYNC_AVAILABLE \ 1330 : 0x0UL) 1331 #define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ 1332 : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ 1333 : ((n) == 2) ? USART2_SYNC_AVAILABLE_B \ 1334 : 0x0UL) 1335 #define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ 1336 : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ 1337 : ((n) == 2) ? USART2_SYNC_LATE_SAMPLE \ 1338 : 0x0UL) 1339 #define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ 1340 : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ 1341 : ((n) == 2) ? USART2_SYNC_LATE_SAMPLE_B \ 1342 : 0x0UL) 1343 #define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ 1344 : ((n) == 1) ? USART1_TIMER \ 1345 : ((n) == 2) ? USART2_TIMER \ 1346 : 0x0UL) 1347 #define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ 1348 : ((n) == 1) ? USART1_TIMER_B \ 1349 : ((n) == 2) ? USART2_TIMER_B \ 1350 : 0x0UL) 1351 1352 /* Instance macros for WDOG */ 1353 #define WDOG(n) (((n) == 0) ? WDOG0 \ 1354 : ((n) == 1) ? WDOG1 \ 1355 : 0x0UL) 1356 #define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ 1357 : ((ref) == WDOG1) ? 1 \ 1358 : -1) 1359 #define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ 1360 : ((n) == 1) ? WDOG1_PCNUM \ 1361 : 0x0UL) 1362 1363 /** @} End of group EFR32MG21A010F512IM32_Peripheral_Parameters */ 1364 1365 /** @} End of group EFR32MG21A010F512IM32 */ 1366 /** @}} End of group Parts */ 1367 1368 #ifdef __cplusplus 1369 } 1370 #endif 1371 #endif 1372
