1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG21 RFCRC register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2020 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG21_RFCRC_H 31 #define EFR32MG21_RFCRC_H 32 #define RFCRC_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG21_RFCRC RFCRC 40 * @{ 41 * @brief EFR32MG21 RFCRC Register Declaration. 42 *****************************************************************************/ 43 44 /** RFCRC Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP Version */ 47 __IOM uint32_t EN; /**< Enable peripheral clock to this module */ 48 __IOM uint32_t CTRL; /**< Control Register */ 49 __IM uint32_t STATUS; /**< Status Register */ 50 __IOM uint32_t CMD; /**< Command Register */ 51 __IOM uint32_t INPUTDATA; /**< Input Data Register */ 52 __IOM uint32_t INIT; /**< CRC Initialization Value */ 53 __IM uint32_t DATA; /**< CRC Data Register */ 54 __IOM uint32_t POLY; /**< CRC Polynomial Value */ 55 uint32_t RESERVED0[1015U]; /**< Reserved for future use */ 56 __IM uint32_t IPVERSION_SET; /**< IP Version */ 57 __IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */ 58 __IOM uint32_t CTRL_SET; /**< Control Register */ 59 __IM uint32_t STATUS_SET; /**< Status Register */ 60 __IOM uint32_t CMD_SET; /**< Command Register */ 61 __IOM uint32_t INPUTDATA_SET; /**< Input Data Register */ 62 __IOM uint32_t INIT_SET; /**< CRC Initialization Value */ 63 __IM uint32_t DATA_SET; /**< CRC Data Register */ 64 __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ 65 uint32_t RESERVED1[1015U]; /**< Reserved for future use */ 66 __IM uint32_t IPVERSION_CLR; /**< IP Version */ 67 __IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */ 68 __IOM uint32_t CTRL_CLR; /**< Control Register */ 69 __IM uint32_t STATUS_CLR; /**< Status Register */ 70 __IOM uint32_t CMD_CLR; /**< Command Register */ 71 __IOM uint32_t INPUTDATA_CLR; /**< Input Data Register */ 72 __IOM uint32_t INIT_CLR; /**< CRC Initialization Value */ 73 __IM uint32_t DATA_CLR; /**< CRC Data Register */ 74 __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ 75 uint32_t RESERVED2[1015U]; /**< Reserved for future use */ 76 __IM uint32_t IPVERSION_TGL; /**< IP Version */ 77 __IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */ 78 __IOM uint32_t CTRL_TGL; /**< Control Register */ 79 __IM uint32_t STATUS_TGL; /**< Status Register */ 80 __IOM uint32_t CMD_TGL; /**< Command Register */ 81 __IOM uint32_t INPUTDATA_TGL; /**< Input Data Register */ 82 __IOM uint32_t INIT_TGL; /**< CRC Initialization Value */ 83 __IM uint32_t DATA_TGL; /**< CRC Data Register */ 84 __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ 85 } RFCRC_TypeDef; 86 /** @} End of group EFR32MG21_RFCRC */ 87 88 /**************************************************************************//** 89 * @addtogroup EFR32MG21_RFCRC 90 * @{ 91 * @defgroup EFR32MG21_RFCRC_BitFields RFCRC Bit Fields 92 * @{ 93 *****************************************************************************/ 94 95 /* Bit fields for RFCRC IPVERSION */ 96 #define _RFCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for RFCRC_IPVERSION */ 97 #define _RFCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for RFCRC_IPVERSION */ 98 #define _RFCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for RFCRC_IPVERSION */ 99 #define _RFCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for RFCRC_IPVERSION */ 100 #define _RFCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_IPVERSION */ 101 #define RFCRC_IPVERSION_IPVERSION_DEFAULT (_RFCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_IPVERSION */ 102 103 /* Bit fields for RFCRC EN */ 104 #define _RFCRC_EN_RESETVALUE 0x00000000UL /**< Default value for RFCRC_EN */ 105 #define _RFCRC_EN_MASK 0x00000001UL /**< Mask for RFCRC_EN */ 106 #define RFCRC_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */ 107 #define _RFCRC_EN_EN_SHIFT 0 /**< Shift value for RFCRC_EN */ 108 #define _RFCRC_EN_EN_MASK 0x1UL /**< Bit mask for RFCRC_EN */ 109 #define _RFCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_EN */ 110 #define RFCRC_EN_EN_DEFAULT (_RFCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_EN */ 111 112 /* Bit fields for RFCRC CTRL */ 113 #define _RFCRC_CTRL_RESETVALUE 0x00000704UL /**< Default value for RFCRC_CTRL */ 114 #define _RFCRC_CTRL_MASK 0x00001FEFUL /**< Mask for RFCRC_CTRL */ 115 #define RFCRC_CTRL_INPUTINV (0x1UL << 0) /**< Input Invert */ 116 #define _RFCRC_CTRL_INPUTINV_SHIFT 0 /**< Shift value for RFCRC_INPUTINV */ 117 #define _RFCRC_CTRL_INPUTINV_MASK 0x1UL /**< Bit mask for RFCRC_INPUTINV */ 118 #define _RFCRC_CTRL_INPUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */ 119 #define RFCRC_CTRL_INPUTINV_DEFAULT (_RFCRC_CTRL_INPUTINV_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_CTRL */ 120 #define RFCRC_CTRL_OUTPUTINV (0x1UL << 1) /**< Output Invert */ 121 #define _RFCRC_CTRL_OUTPUTINV_SHIFT 1 /**< Shift value for RFCRC_OUTPUTINV */ 122 #define _RFCRC_CTRL_OUTPUTINV_MASK 0x2UL /**< Bit mask for RFCRC_OUTPUTINV */ 123 #define _RFCRC_CTRL_OUTPUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */ 124 #define RFCRC_CTRL_OUTPUTINV_DEFAULT (_RFCRC_CTRL_OUTPUTINV_DEFAULT << 1) /**< Shifted mode DEFAULT for RFCRC_CTRL */ 125 #define _RFCRC_CTRL_CRCWIDTH_SHIFT 2 /**< Shift value for RFCRC_CRCWIDTH */ 126 #define _RFCRC_CTRL_CRCWIDTH_MASK 0xCUL /**< Bit mask for RFCRC_CRCWIDTH */ 127 #define _RFCRC_CTRL_CRCWIDTH_DEFAULT 0x00000001UL /**< Mode DEFAULT for RFCRC_CTRL */ 128 #define _RFCRC_CTRL_CRCWIDTH_CRCWIDTH8 0x00000000UL /**< Mode CRCWIDTH8 for RFCRC_CTRL */ 129 #define _RFCRC_CTRL_CRCWIDTH_CRCWIDTH16 0x00000001UL /**< Mode CRCWIDTH16 for RFCRC_CTRL */ 130 #define _RFCRC_CTRL_CRCWIDTH_CRCWIDTH24 0x00000002UL /**< Mode CRCWIDTH24 for RFCRC_CTRL */ 131 #define _RFCRC_CTRL_CRCWIDTH_CRCWIDTH32 0x00000003UL /**< Mode CRCWIDTH32 for RFCRC_CTRL */ 132 #define RFCRC_CTRL_CRCWIDTH_DEFAULT (_RFCRC_CTRL_CRCWIDTH_DEFAULT << 2) /**< Shifted mode DEFAULT for RFCRC_CTRL */ 133 #define RFCRC_CTRL_CRCWIDTH_CRCWIDTH8 (_RFCRC_CTRL_CRCWIDTH_CRCWIDTH8 << 2) /**< Shifted mode CRCWIDTH8 for RFCRC_CTRL */ 134 #define RFCRC_CTRL_CRCWIDTH_CRCWIDTH16 (_RFCRC_CTRL_CRCWIDTH_CRCWIDTH16 << 2) /**< Shifted mode CRCWIDTH16 for RFCRC_CTRL */ 135 #define RFCRC_CTRL_CRCWIDTH_CRCWIDTH24 (_RFCRC_CTRL_CRCWIDTH_CRCWIDTH24 << 2) /**< Shifted mode CRCWIDTH24 for RFCRC_CTRL */ 136 #define RFCRC_CTRL_CRCWIDTH_CRCWIDTH32 (_RFCRC_CTRL_CRCWIDTH_CRCWIDTH32 << 2) /**< Shifted mode CRCWIDTH32 for RFCRC_CTRL */ 137 #define RFCRC_CTRL_INPUTBITORDER (0x1UL << 5) /**< CRC input bit ordering setting */ 138 #define _RFCRC_CTRL_INPUTBITORDER_SHIFT 5 /**< Shift value for RFCRC_INPUTBITORDER */ 139 #define _RFCRC_CTRL_INPUTBITORDER_MASK 0x20UL /**< Bit mask for RFCRC_INPUTBITORDER */ 140 #define _RFCRC_CTRL_INPUTBITORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */ 141 #define _RFCRC_CTRL_INPUTBITORDER_LSBFIRST 0x00000000UL /**< Mode LSBFIRST for RFCRC_CTRL */ 142 #define _RFCRC_CTRL_INPUTBITORDER_MSBFIRST 0x00000001UL /**< Mode MSBFIRST for RFCRC_CTRL */ 143 #define RFCRC_CTRL_INPUTBITORDER_DEFAULT (_RFCRC_CTRL_INPUTBITORDER_DEFAULT << 5) /**< Shifted mode DEFAULT for RFCRC_CTRL */ 144 #define RFCRC_CTRL_INPUTBITORDER_LSBFIRST (_RFCRC_CTRL_INPUTBITORDER_LSBFIRST << 5) /**< Shifted mode LSBFIRST for RFCRC_CTRL */ 145 #define RFCRC_CTRL_INPUTBITORDER_MSBFIRST (_RFCRC_CTRL_INPUTBITORDER_MSBFIRST << 5) /**< Shifted mode MSBFIRST for RFCRC_CTRL */ 146 #define RFCRC_CTRL_BYTEREVERSE (0x1UL << 6) /**< Reverse CRC byte ordering over air */ 147 #define _RFCRC_CTRL_BYTEREVERSE_SHIFT 6 /**< Shift value for RFCRC_BYTEREVERSE */ 148 #define _RFCRC_CTRL_BYTEREVERSE_MASK 0x40UL /**< Bit mask for RFCRC_BYTEREVERSE */ 149 #define _RFCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */ 150 #define _RFCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for RFCRC_CTRL */ 151 #define _RFCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for RFCRC_CTRL */ 152 #define RFCRC_CTRL_BYTEREVERSE_DEFAULT (_RFCRC_CTRL_BYTEREVERSE_DEFAULT << 6) /**< Shifted mode DEFAULT for RFCRC_CTRL */ 153 #define RFCRC_CTRL_BYTEREVERSE_NORMAL (_RFCRC_CTRL_BYTEREVERSE_NORMAL << 6) /**< Shifted mode NORMAL for RFCRC_CTRL */ 154 #define RFCRC_CTRL_BYTEREVERSE_REVERSED (_RFCRC_CTRL_BYTEREVERSE_REVERSED << 6) /**< Shifted mode REVERSED for RFCRC_CTRL */ 155 #define RFCRC_CTRL_BITREVERSE (0x1UL << 7) /**< Reverse CRC bit ordering over air */ 156 #define _RFCRC_CTRL_BITREVERSE_SHIFT 7 /**< Shift value for RFCRC_BITREVERSE */ 157 #define _RFCRC_CTRL_BITREVERSE_MASK 0x80UL /**< Bit mask for RFCRC_BITREVERSE */ 158 #define _RFCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */ 159 #define _RFCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for RFCRC_CTRL */ 160 #define _RFCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for RFCRC_CTRL */ 161 #define RFCRC_CTRL_BITREVERSE_DEFAULT (_RFCRC_CTRL_BITREVERSE_DEFAULT << 7) /**< Shifted mode DEFAULT for RFCRC_CTRL */ 162 #define RFCRC_CTRL_BITREVERSE_NORMAL (_RFCRC_CTRL_BITREVERSE_NORMAL << 7) /**< Shifted mode NORMAL for RFCRC_CTRL */ 163 #define RFCRC_CTRL_BITREVERSE_REVERSED (_RFCRC_CTRL_BITREVERSE_REVERSED << 7) /**< Shifted mode REVERSED for RFCRC_CTRL */ 164 #define _RFCRC_CTRL_BITSPERWORD_SHIFT 8 /**< Shift value for RFCRC_BITSPERWORD */ 165 #define _RFCRC_CTRL_BITSPERWORD_MASK 0xF00UL /**< Bit mask for RFCRC_BITSPERWORD */ 166 #define _RFCRC_CTRL_BITSPERWORD_DEFAULT 0x00000007UL /**< Mode DEFAULT for RFCRC_CTRL */ 167 #define RFCRC_CTRL_BITSPERWORD_DEFAULT (_RFCRC_CTRL_BITSPERWORD_DEFAULT << 8) /**< Shifted mode DEFAULT for RFCRC_CTRL */ 168 #define RFCRC_CTRL_PADCRCINPUT (0x1UL << 12) /**< Pad CRC input data */ 169 #define _RFCRC_CTRL_PADCRCINPUT_SHIFT 12 /**< Shift value for RFCRC_PADCRCINPUT */ 170 #define _RFCRC_CTRL_PADCRCINPUT_MASK 0x1000UL /**< Bit mask for RFCRC_PADCRCINPUT */ 171 #define _RFCRC_CTRL_PADCRCINPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CTRL */ 172 #define _RFCRC_CTRL_PADCRCINPUT_X0 0x00000000UL /**< Mode X0 for RFCRC_CTRL */ 173 #define _RFCRC_CTRL_PADCRCINPUT_X1 0x00000001UL /**< Mode X1 for RFCRC_CTRL */ 174 #define RFCRC_CTRL_PADCRCINPUT_DEFAULT (_RFCRC_CTRL_PADCRCINPUT_DEFAULT << 12) /**< Shifted mode DEFAULT for RFCRC_CTRL */ 175 #define RFCRC_CTRL_PADCRCINPUT_X0 (_RFCRC_CTRL_PADCRCINPUT_X0 << 12) /**< Shifted mode X0 for RFCRC_CTRL */ 176 #define RFCRC_CTRL_PADCRCINPUT_X1 (_RFCRC_CTRL_PADCRCINPUT_X1 << 12) /**< Shifted mode X1 for RFCRC_CTRL */ 177 178 /* Bit fields for RFCRC STATUS */ 179 #define _RFCRC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RFCRC_STATUS */ 180 #define _RFCRC_STATUS_MASK 0x00000001UL /**< Mask for RFCRC_STATUS */ 181 #define RFCRC_STATUS_BUSY (0x1UL << 0) /**< CRC Running */ 182 #define _RFCRC_STATUS_BUSY_SHIFT 0 /**< Shift value for RFCRC_BUSY */ 183 #define _RFCRC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for RFCRC_BUSY */ 184 #define _RFCRC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_STATUS */ 185 #define RFCRC_STATUS_BUSY_DEFAULT (_RFCRC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_STATUS */ 186 187 /* Bit fields for RFCRC CMD */ 188 #define _RFCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for RFCRC_CMD */ 189 #define _RFCRC_CMD_MASK 0x00000001UL /**< Mask for RFCRC_CMD */ 190 #define RFCRC_CMD_INITIALIZE (0x1UL << 0) /**< Initialize CRC */ 191 #define _RFCRC_CMD_INITIALIZE_SHIFT 0 /**< Shift value for RFCRC_INITIALIZE */ 192 #define _RFCRC_CMD_INITIALIZE_MASK 0x1UL /**< Bit mask for RFCRC_INITIALIZE */ 193 #define _RFCRC_CMD_INITIALIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_CMD */ 194 #define RFCRC_CMD_INITIALIZE_DEFAULT (_RFCRC_CMD_INITIALIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_CMD */ 195 196 /* Bit fields for RFCRC INPUTDATA */ 197 #define _RFCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for RFCRC_INPUTDATA */ 198 #define _RFCRC_INPUTDATA_MASK 0x0000FFFFUL /**< Mask for RFCRC_INPUTDATA */ 199 #define _RFCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for RFCRC_INPUTDATA */ 200 #define _RFCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFUL /**< Bit mask for RFCRC_INPUTDATA */ 201 #define _RFCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_INPUTDATA */ 202 #define RFCRC_INPUTDATA_INPUTDATA_DEFAULT (_RFCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_INPUTDATA */ 203 204 /* Bit fields for RFCRC INIT */ 205 #define _RFCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for RFCRC_INIT */ 206 #define _RFCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for RFCRC_INIT */ 207 #define _RFCRC_INIT_INIT_SHIFT 0 /**< Shift value for RFCRC_INIT */ 208 #define _RFCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for RFCRC_INIT */ 209 #define _RFCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_INIT */ 210 #define RFCRC_INIT_INIT_DEFAULT (_RFCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_INIT */ 211 212 /* Bit fields for RFCRC DATA */ 213 #define _RFCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for RFCRC_DATA */ 214 #define _RFCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for RFCRC_DATA */ 215 #define _RFCRC_DATA_DATA_SHIFT 0 /**< Shift value for RFCRC_DATA */ 216 #define _RFCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for RFCRC_DATA */ 217 #define _RFCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_DATA */ 218 #define RFCRC_DATA_DATA_DEFAULT (_RFCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_DATA */ 219 220 /* Bit fields for RFCRC POLY */ 221 #define _RFCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for RFCRC_POLY */ 222 #define _RFCRC_POLY_MASK 0xFFFFFFFFUL /**< Mask for RFCRC_POLY */ 223 #define _RFCRC_POLY_POLY_SHIFT 0 /**< Shift value for RFCRC_POLY */ 224 #define _RFCRC_POLY_POLY_MASK 0xFFFFFFFFUL /**< Bit mask for RFCRC_POLY */ 225 #define _RFCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RFCRC_POLY */ 226 #define RFCRC_POLY_POLY_DEFAULT (_RFCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for RFCRC_POLY */ 227 228 /** @} End of group EFR32MG21_RFCRC_BitFields */ 229 /** @} End of group EFR32MG21_RFCRC */ 230 /** @} End of group Parts */ 231 232 #endif /* EFR32MG21_RFCRC_H */ 233
