1 /***************************************************************************//** 2 * @file 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File 4 * for EFR32FG1P132F64GM48 5 ******************************************************************************* 6 * # License 7 * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b> 8 ******************************************************************************* 9 * 10 * SPDX-License-Identifier: Zlib 11 * 12 * The licensor of this software is Silicon Laboratories Inc. 13 * 14 * This software is provided 'as-is', without any express or implied 15 * warranty. In no event will the authors be held liable for any damages 16 * arising from the use of this software. 17 * 18 * Permission is granted to anyone to use this software for any purpose, 19 * including commercial applications, and to alter it and redistribute it 20 * freely, subject to the following restrictions: 21 * 22 * 1. The origin of this software must not be misrepresented; you must not 23 * claim that you wrote the original software. If you use this software 24 * in a product, an acknowledgment in the product documentation would be 25 * appreciated but is not required. 26 * 2. Altered source versions must be plainly marked as such, and must not be 27 * misrepresented as being the original software. 28 * 3. This notice may not be removed or altered from any source distribution. 29 * 30 ******************************************************************************/ 31 32 #if defined(__ICCARM__) 33 #pragma system_include /* Treat file as system include file. */ 34 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 35 #pragma clang system_header /* Treat file as system include file. */ 36 #endif 37 38 #ifndef EFR32FG1P132F64GM48_H 39 #define EFR32FG1P132F64GM48_H 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /***************************************************************************//** 46 * @addtogroup Parts 47 * @{ 48 ******************************************************************************/ 49 50 /***************************************************************************//** 51 * @defgroup EFR32FG1P132F64GM48 EFR32FG1P132F64GM48 52 * @{ 53 ******************************************************************************/ 54 55 /** Interrupt Number Definition */ 56 typedef enum IRQn{ 57 /****** Cortex-M4 Processor Exceptions Numbers ********************************************/ 58 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ 59 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ 60 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ 61 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ 62 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ 63 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ 64 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ 65 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ 66 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ 67 68 /****** EFR32FG1P Peripheral Interrupt Numbers ********************************************/ 69 70 EMU_IRQn = 0, /*!< 16+0 EFR32 EMU Interrupt */ 71 FRC_PRI_IRQn = 1, /*!< 16+1 EFR32 FRC_PRI Interrupt */ 72 WDOG0_IRQn = 2, /*!< 16+2 EFR32 WDOG0 Interrupt */ 73 FRC_IRQn = 3, /*!< 16+3 EFR32 FRC Interrupt */ 74 MODEM_IRQn = 4, /*!< 16+4 EFR32 MODEM Interrupt */ 75 RAC_SEQ_IRQn = 5, /*!< 16+5 EFR32 RAC_SEQ Interrupt */ 76 RAC_RSM_IRQn = 6, /*!< 16+6 EFR32 RAC_RSM Interrupt */ 77 BUFC_IRQn = 7, /*!< 16+7 EFR32 BUFC Interrupt */ 78 LDMA_IRQn = 8, /*!< 16+8 EFR32 LDMA Interrupt */ 79 GPIO_EVEN_IRQn = 9, /*!< 16+9 EFR32 GPIO_EVEN Interrupt */ 80 TIMER0_IRQn = 10, /*!< 16+10 EFR32 TIMER0 Interrupt */ 81 USART0_RX_IRQn = 11, /*!< 16+11 EFR32 USART0_RX Interrupt */ 82 USART0_TX_IRQn = 12, /*!< 16+12 EFR32 USART0_TX Interrupt */ 83 ACMP0_IRQn = 13, /*!< 16+13 EFR32 ACMP0 Interrupt */ 84 ADC0_IRQn = 14, /*!< 16+14 EFR32 ADC0 Interrupt */ 85 IDAC0_IRQn = 15, /*!< 16+15 EFR32 IDAC0 Interrupt */ 86 I2C0_IRQn = 16, /*!< 16+16 EFR32 I2C0 Interrupt */ 87 GPIO_ODD_IRQn = 17, /*!< 16+17 EFR32 GPIO_ODD Interrupt */ 88 TIMER1_IRQn = 18, /*!< 16+18 EFR32 TIMER1 Interrupt */ 89 USART1_RX_IRQn = 19, /*!< 16+19 EFR32 USART1_RX Interrupt */ 90 USART1_TX_IRQn = 20, /*!< 16+20 EFR32 USART1_TX Interrupt */ 91 LEUART0_IRQn = 21, /*!< 16+21 EFR32 LEUART0 Interrupt */ 92 PCNT0_IRQn = 22, /*!< 16+22 EFR32 PCNT0 Interrupt */ 93 CMU_IRQn = 23, /*!< 16+23 EFR32 CMU Interrupt */ 94 MSC_IRQn = 24, /*!< 16+24 EFR32 MSC Interrupt */ 95 CRYPTO_IRQn = 25, /*!< 16+25 EFR32 CRYPTO Interrupt */ 96 LETIMER0_IRQn = 26, /*!< 16+26 EFR32 LETIMER0 Interrupt */ 97 AGC_IRQn = 27, /*!< 16+27 EFR32 AGC Interrupt */ 98 PROTIMER_IRQn = 28, /*!< 16+28 EFR32 PROTIMER Interrupt */ 99 RTCC_IRQn = 29, /*!< 16+29 EFR32 RTCC Interrupt */ 100 SYNTH_IRQn = 30, /*!< 16+30 EFR32 SYNTH Interrupt */ 101 CRYOTIMER_IRQn = 31, /*!< 16+31 EFR32 CRYOTIMER Interrupt */ 102 RFSENSE_IRQn = 32, /*!< 16+32 EFR32 RFSENSE Interrupt */ 103 FPUEH_IRQn = 33, /*!< 16+33 EFR32 FPUEH Interrupt */ 104 } IRQn_Type; 105 106 /***************************************************************************//** 107 * @defgroup EFR32FG1P132F64GM48_Core Core 108 * @{ 109 * @brief Processor and Core Peripheral Section 110 ******************************************************************************/ 111 #define __MPU_PRESENT 1U /**< Presence of MPU */ 112 #define __FPU_PRESENT 1U /**< Presence of FPU */ 113 #define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ 114 #define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ 115 #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ 116 117 /** @} End of group EFR32FG1P132F64GM48_Core */ 118 119 /***************************************************************************//** 120 * @defgroup EFR32FG1P132F64GM48_Part Part 121 * @{ 122 ******************************************************************************/ 123 124 /** Part family */ 125 #define _EFR32_FLEX_FAMILY 1 /**< FLEX Gecko RF SoC Family */ 126 #define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ 127 #define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ 128 #define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ 129 #define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ 130 #define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ 131 #define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /**< Silicon Labs internal use only, may change any time */ 132 #define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /**< Silicon Labs internal use only, may change any time */ 133 #define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /**< Radio supports Sub-GHz */ 134 #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /**< Radio supports 2.4 GHz */ 135 #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /**< Radio supports dual band */ 136 #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /**< Radio type */ 137 #define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ 138 #define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ 139 #define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ 140 #define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ 141 142 /* If part number is not defined as compiler option, define it */ 143 #if !defined(EFR32FG1P132F64GM48) 144 #define EFR32FG1P132F64GM48 1 /**< FLEX Gecko Part */ 145 #endif 146 147 /** Configure part number */ 148 #define PART_NUMBER "EFR32FG1P132F64GM48" /**< Part Number */ 149 150 /** Memory Base addresses and limits */ 151 #define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */ 152 #define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */ 153 #define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */ 154 #define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */ 155 #define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ 156 #define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */ 157 #define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */ 158 #define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */ 159 #define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ 160 #define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */ 161 #define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */ 162 #define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */ 163 #define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */ 164 #define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */ 165 #define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */ 166 #define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */ 167 #define PER_MEM_BASE (0x40000000UL) /**< PER base address */ 168 #define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */ 169 #define PER_MEM_END (0x400E7FFFUL) /**< PER end address */ 170 #define PER_MEM_BITS (0x00000014UL) /**< PER used bits */ 171 #define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */ 172 #define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */ 173 #define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */ 174 #define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */ 175 #define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */ 176 #define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */ 177 #define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */ 178 #define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */ 179 #define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ 180 #define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */ 181 #define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */ 182 #define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */ 183 #define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ 184 #define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */ 185 #define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */ 186 #define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */ 187 188 /** Bit banding area */ 189 #define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ 190 #define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ 191 192 /** Flash and SRAM limits for EFR32FG1P132F64GM48 */ 193 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ 194 #define FLASH_SIZE (0x00010000UL) /**< Available Flash Memory */ 195 #define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */ 196 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ 197 #define SRAM_SIZE (0x00004000UL) /**< Available SRAM Memory */ 198 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ 199 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ 200 #define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ 201 #define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */ 202 203 /** AF channels connect the different on-chip peripherals with the af-mux */ 204 #define AFCHAN_MAX 72U 205 /** AF channel maximum location number */ 206 #define AFCHANLOC_MAX 32U 207 /** Analog AF channels */ 208 #define AFACHAN_MAX 61U 209 210 /* Part number capabilities */ 211 212 #define TIMER_PRESENT /**< TIMER is available in this part */ 213 #define TIMER_COUNT 2 /**< 2 TIMERs available */ 214 #define USART_PRESENT /**< USART is available in this part */ 215 #define USART_COUNT 2 /**< 2 USARTs available */ 216 #define LEUART_PRESENT /**< LEUART is available in this part */ 217 #define LEUART_COUNT 1 /**< 1 LEUARTs available */ 218 #define LETIMER_PRESENT /**< LETIMER is available in this part */ 219 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */ 220 #define PCNT_PRESENT /**< PCNT is available in this part */ 221 #define PCNT_COUNT 1 /**< 1 PCNTs available */ 222 #define I2C_PRESENT /**< I2C is available in this part */ 223 #define I2C_COUNT 1 /**< 1 I2Cs available */ 224 #define ADC_PRESENT /**< ADC is available in this part */ 225 #define ADC_COUNT 1 /**< 1 ADCs available */ 226 #define ACMP_PRESENT /**< ACMP is available in this part */ 227 #define ACMP_COUNT 2 /**< 2 ACMPs available */ 228 #define IDAC_PRESENT /**< IDAC is available in this part */ 229 #define IDAC_COUNT 1 /**< 1 IDACs available */ 230 #define WDOG_PRESENT /**< WDOG is available in this part */ 231 #define WDOG_COUNT 1 /**< 1 WDOGs available */ 232 #define MSC_PRESENT /**< MSC is available in this part */ 233 #define MSC_COUNT 1 /**< 1 MSC available */ 234 #define EMU_PRESENT /**< EMU is available in this part */ 235 #define EMU_COUNT 1 /**< 1 EMU available */ 236 #define RMU_PRESENT /**< RMU is available in this part */ 237 #define RMU_COUNT 1 /**< 1 RMU available */ 238 #define CMU_PRESENT /**< CMU is available in this part */ 239 #define CMU_COUNT 1 /**< 1 CMU available */ 240 #define CRYPTO_PRESENT /**< CRYPTO is available in this part */ 241 #define CRYPTO_COUNT 1 /**< 1 CRYPTO available */ 242 #define GPIO_PRESENT /**< GPIO is available in this part */ 243 #define GPIO_COUNT 1 /**< 1 GPIO available */ 244 #define PRS_PRESENT /**< PRS is available in this part */ 245 #define PRS_COUNT 1 /**< 1 PRS available */ 246 #define LDMA_PRESENT /**< LDMA is available in this part */ 247 #define LDMA_COUNT 1 /**< 1 LDMA available */ 248 #define FPUEH_PRESENT /**< FPUEH is available in this part */ 249 #define FPUEH_COUNT 1 /**< 1 FPUEH available */ 250 #define GPCRC_PRESENT /**< GPCRC is available in this part */ 251 #define GPCRC_COUNT 1 /**< 1 GPCRC available */ 252 #define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ 253 #define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ 254 #define RTCC_PRESENT /**< RTCC is available in this part */ 255 #define RTCC_COUNT 1 /**< 1 RTCC available */ 256 #define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ 257 #define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ 258 #define DCDC_PRESENT /**< DCDC is available in this part */ 259 #define DCDC_COUNT 1 /**< 1 DCDC available */ 260 261 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 262 #include "system_efr32fg1p.h" /* System Header File */ 263 264 /** @} End of group EFR32FG1P132F64GM48_Part */ 265 266 /***************************************************************************//** 267 * @defgroup EFR32FG1P132F64GM48_Peripheral_TypeDefs Peripheral TypeDefs 268 * @{ 269 * @brief Device Specific Peripheral Register Structures 270 ******************************************************************************/ 271 272 #include "efr32fg1p_msc.h" 273 #include "efr32fg1p_emu.h" 274 #include "efr32fg1p_rmu.h" 275 #include "efr32fg1p_cmu.h" 276 #include "efr32fg1p_crypto.h" 277 #include "efr32fg1p_gpio_p.h" 278 #include "efr32fg1p_gpio.h" 279 #include "efr32fg1p_prs_ch.h" 280 #include "efr32fg1p_prs.h" 281 #include "efr32fg1p_ldma_ch.h" 282 #include "efr32fg1p_ldma.h" 283 #include "efr32fg1p_fpueh.h" 284 #include "efr32fg1p_gpcrc.h" 285 #include "efr32fg1p_timer_cc.h" 286 #include "efr32fg1p_timer.h" 287 #include "efr32fg1p_usart.h" 288 #include "efr32fg1p_leuart.h" 289 #include "efr32fg1p_letimer.h" 290 #include "efr32fg1p_cryotimer.h" 291 #include "efr32fg1p_pcnt.h" 292 #include "efr32fg1p_i2c.h" 293 #include "efr32fg1p_adc.h" 294 #include "efr32fg1p_acmp.h" 295 #include "efr32fg1p_idac.h" 296 #include "efr32fg1p_rtcc_cc.h" 297 #include "efr32fg1p_rtcc_ret.h" 298 #include "efr32fg1p_rtcc.h" 299 #include "efr32fg1p_wdog_pch.h" 300 #include "efr32fg1p_wdog.h" 301 #include "efr32fg1p_dma_descriptor.h" 302 #include "efr32fg1p_devinfo.h" 303 #include "efr32fg1p_romtable.h" 304 305 /** @} End of group EFR32FG1P132F64GM48_Peripheral_TypeDefs */ 306 307 /***************************************************************************//** 308 * @defgroup EFR32FG1P132F64GM48_Peripheral_Base Peripheral Memory Map 309 * @{ 310 ******************************************************************************/ 311 312 #define MSC_BASE (0x400E0000UL) /**< MSC base address */ 313 #define EMU_BASE (0x400E3000UL) /**< EMU base address */ 314 #define RMU_BASE (0x400E5000UL) /**< RMU base address */ 315 #define CMU_BASE (0x400E4000UL) /**< CMU base address */ 316 #define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */ 317 #define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ 318 #define PRS_BASE (0x400E6000UL) /**< PRS base address */ 319 #define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ 320 #define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ 321 #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ 322 #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ 323 #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ 324 #define USART0_BASE (0x40010000UL) /**< USART0 base address */ 325 #define USART1_BASE (0x40010400UL) /**< USART1 base address */ 326 #define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ 327 #define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ 328 #define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ 329 #define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ 330 #define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ 331 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ 332 #define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ 333 #define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ 334 #define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ 335 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ 336 #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ 337 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ 338 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ 339 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ 340 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ 341 342 /** @} End of group EFR32FG1P132F64GM48_Peripheral_Base */ 343 344 /***************************************************************************//** 345 * @defgroup EFR32FG1P132F64GM48_Peripheral_Declaration Peripheral Declarations 346 * @{ 347 ******************************************************************************/ 348 349 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ 350 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ 351 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ 352 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ 353 #define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */ 354 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ 355 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ 356 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ 357 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ 358 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ 359 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ 360 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ 361 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ 362 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ 363 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ 364 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ 365 #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ 366 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ 367 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ 368 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ 369 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ 370 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ 371 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ 372 #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ 373 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ 374 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ 375 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ 376 377 /** @} End of group EFR32FG1P132F64GM48_Peripheral_Declaration */ 378 379 /***************************************************************************//** 380 * @defgroup EFR32FG1P132F64GM48_Peripheral_Offsets Peripheral Offsets 381 * @{ 382 ******************************************************************************/ 383 384 #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ 385 #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ 386 #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ 387 #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ 388 #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ 389 #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ 390 #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ 391 #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ 392 #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ 393 #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ 394 395 /** @} End of group EFR32FG1P132F64GM48_Peripheral_Offsets */ 396 397 /***************************************************************************//** 398 * @defgroup EFR32FG1P132F64GM48_BitFields Bit Fields 399 * @{ 400 ******************************************************************************/ 401 402 #include "efr32fg1p_prs_signals.h" 403 #include "efr32fg1p_dmareq.h" 404 405 /***************************************************************************//** 406 * @defgroup EFR32FG1P132F64GM48_UNLOCK Unlock Codes 407 * @{ 408 ******************************************************************************/ 409 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ 410 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ 411 #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ 412 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ 413 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ 414 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ 415 #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ 416 417 /** @} End of group EFR32FG1P132F64GM48_UNLOCK */ 418 419 /** @} End of group EFR32FG1P132F64GM48_BitFields */ 420 421 #include "efr32fg1p_af_ports.h" 422 #include "efr32fg1p_af_pins.h" 423 424 /***************************************************************************//** 425 * @brief Set the value of a bit field within a register. 426 * 427 * @param REG 428 * The register to update 429 * @param MASK 430 * The mask for the bit field to update 431 * @param VALUE 432 * The value to write to the bit field 433 * @param OFFSET 434 * The number of bits that the field is offset within the register. 435 * 0 (zero) means LSB. 436 ******************************************************************************/ 437 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ 438 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); 439 440 /** @} End of group EFR32FG1P132F64GM48 */ 441 442 /** @} End of group Parts */ 443 444 #ifdef __cplusplus 445 } 446 #endif 447 #endif /* EFR32FG1P132F64GM48_H */ 448
