1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG27 HFXO register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG27_HFXO_H 31 #define EFR32BG27_HFXO_H 32 #define HFXO_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG27_HFXO HFXO 40 * @{ 41 * @brief EFR32BG27 HFXO Register Declaration. 42 *****************************************************************************/ 43 44 /** HFXO Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP version ID */ 47 uint32_t RESERVED0[3U]; /**< Reserved for future use */ 48 __IOM uint32_t XTALCFG; /**< Crystal Configuration Register */ 49 uint32_t RESERVED1[1U]; /**< Reserved for future use */ 50 __IOM uint32_t XTALCTRL; /**< Crystal Control Register */ 51 uint32_t RESERVED2[1U]; /**< Reserved for future use */ 52 __IOM uint32_t CFG; /**< Configuration Register */ 53 uint32_t RESERVED3[1U]; /**< Reserved for future use */ 54 __IOM uint32_t CTRL; /**< Control Register */ 55 uint32_t RESERVED4[9U]; /**< Reserved for future use */ 56 __IOM uint32_t CMD; /**< Command Register */ 57 uint32_t RESERVED5[1U]; /**< Reserved for future use */ 58 __IM uint32_t STATUS; /**< Status Register */ 59 uint32_t RESERVED6[5U]; /**< Reserved for future use */ 60 __IOM uint32_t IF; /**< Interrupt Flag Register */ 61 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 62 uint32_t RESERVED7[2U]; /**< Reserved for future use */ 63 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 64 uint32_t RESERVED8[991U]; /**< Reserved for future use */ 65 __IM uint32_t IPVERSION_SET; /**< IP version ID */ 66 uint32_t RESERVED9[3U]; /**< Reserved for future use */ 67 __IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */ 68 uint32_t RESERVED10[1U]; /**< Reserved for future use */ 69 __IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */ 70 uint32_t RESERVED11[1U]; /**< Reserved for future use */ 71 __IOM uint32_t CFG_SET; /**< Configuration Register */ 72 uint32_t RESERVED12[1U]; /**< Reserved for future use */ 73 __IOM uint32_t CTRL_SET; /**< Control Register */ 74 uint32_t RESERVED13[9U]; /**< Reserved for future use */ 75 __IOM uint32_t CMD_SET; /**< Command Register */ 76 uint32_t RESERVED14[1U]; /**< Reserved for future use */ 77 __IM uint32_t STATUS_SET; /**< Status Register */ 78 uint32_t RESERVED15[5U]; /**< Reserved for future use */ 79 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 80 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 81 uint32_t RESERVED16[2U]; /**< Reserved for future use */ 82 __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ 83 uint32_t RESERVED17[991U]; /**< Reserved for future use */ 84 __IM uint32_t IPVERSION_CLR; /**< IP version ID */ 85 uint32_t RESERVED18[3U]; /**< Reserved for future use */ 86 __IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */ 87 uint32_t RESERVED19[1U]; /**< Reserved for future use */ 88 __IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */ 89 uint32_t RESERVED20[1U]; /**< Reserved for future use */ 90 __IOM uint32_t CFG_CLR; /**< Configuration Register */ 91 uint32_t RESERVED21[1U]; /**< Reserved for future use */ 92 __IOM uint32_t CTRL_CLR; /**< Control Register */ 93 uint32_t RESERVED22[9U]; /**< Reserved for future use */ 94 __IOM uint32_t CMD_CLR; /**< Command Register */ 95 uint32_t RESERVED23[1U]; /**< Reserved for future use */ 96 __IM uint32_t STATUS_CLR; /**< Status Register */ 97 uint32_t RESERVED24[5U]; /**< Reserved for future use */ 98 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 99 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 100 uint32_t RESERVED25[2U]; /**< Reserved for future use */ 101 __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ 102 uint32_t RESERVED26[991U]; /**< Reserved for future use */ 103 __IM uint32_t IPVERSION_TGL; /**< IP version ID */ 104 uint32_t RESERVED27[3U]; /**< Reserved for future use */ 105 __IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */ 106 uint32_t RESERVED28[1U]; /**< Reserved for future use */ 107 __IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */ 108 uint32_t RESERVED29[1U]; /**< Reserved for future use */ 109 __IOM uint32_t CFG_TGL; /**< Configuration Register */ 110 uint32_t RESERVED30[1U]; /**< Reserved for future use */ 111 __IOM uint32_t CTRL_TGL; /**< Control Register */ 112 uint32_t RESERVED31[9U]; /**< Reserved for future use */ 113 __IOM uint32_t CMD_TGL; /**< Command Register */ 114 uint32_t RESERVED32[1U]; /**< Reserved for future use */ 115 __IM uint32_t STATUS_TGL; /**< Status Register */ 116 uint32_t RESERVED33[5U]; /**< Reserved for future use */ 117 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 118 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 119 uint32_t RESERVED34[2U]; /**< Reserved for future use */ 120 __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ 121 } HFXO_TypeDef; 122 /** @} End of group EFR32BG27_HFXO */ 123 124 /**************************************************************************//** 125 * @addtogroup EFR32BG27_HFXO 126 * @{ 127 * @defgroup EFR32BG27_HFXO_BitFields HFXO Bit Fields 128 * @{ 129 *****************************************************************************/ 130 131 /* Bit fields for HFXO IPVERSION */ 132 #define _HFXO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFXO_IPVERSION */ 133 #define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */ 134 #define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */ 135 #define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */ 136 #define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFXO_IPVERSION */ 137 #define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */ 138 139 /* Bit fields for HFXO XTALCFG */ 140 #define _HFXO_XTALCFG_RESETVALUE 0x044334CBUL /**< Default value for HFXO_XTALCFG */ 141 #define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */ 142 #define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */ 143 #define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */ 144 #define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ 145 #define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ 146 #define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */ 147 #define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */ 148 #define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000013UL /**< Mode DEFAULT for HFXO_XTALCFG */ 149 #define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ 150 #define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */ 151 #define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */ 152 #define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCFG */ 153 #define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ 154 #define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */ 155 #define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */ 156 #define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCFG */ 157 #define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ 158 #define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */ 159 #define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */ 160 #define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_XTALCFG */ 161 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000000UL /**< Mode T16US for HFXO_XTALCFG */ 162 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000001UL /**< Mode T41US for HFXO_XTALCFG */ 163 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000002UL /**< Mode T83US for HFXO_XTALCFG */ 164 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000003UL /**< Mode T125US for HFXO_XTALCFG */ 165 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000004UL /**< Mode T166US for HFXO_XTALCFG */ 166 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000005UL /**< Mode T208US for HFXO_XTALCFG */ 167 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000006UL /**< Mode T250US for HFXO_XTALCFG */ 168 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000007UL /**< Mode T333US for HFXO_XTALCFG */ 169 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000008UL /**< Mode T416US for HFXO_XTALCFG */ 170 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x00000009UL /**< Mode T500US for HFXO_XTALCFG */ 171 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000AUL /**< Mode T666US for HFXO_XTALCFG */ 172 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000BUL /**< Mode T833US for HFXO_XTALCFG */ 173 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000CUL /**< Mode T1666US for HFXO_XTALCFG */ 174 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000DUL /**< Mode T2500US for HFXO_XTALCFG */ 175 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000EUL /**< Mode T4166US for HFXO_XTALCFG */ 176 #define _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US 0x0000000FUL /**< Mode T7500US for HFXO_XTALCFG */ 177 #define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ 178 #define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */ 179 #define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */ 180 #define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */ 181 #define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */ 182 #define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */ 183 #define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */ 184 #define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */ 185 #define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */ 186 #define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */ 187 #define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */ 188 #define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */ 189 #define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */ 190 #define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */ 191 #define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */ 192 #define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */ 193 #define HFXO_XTALCFG_TIMEOUTSTEADY_T7500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T7500US << 20) /**< Shifted mode T7500US for HFXO_XTALCFG */ 194 #define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */ 195 #define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */ 196 #define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_XTALCFG */ 197 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */ 198 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */ 199 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ 200 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */ 201 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */ 202 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */ 203 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */ 204 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */ 205 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */ 206 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */ 207 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */ 208 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */ 209 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ 210 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */ 211 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */ 212 #define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */ 213 #define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ 214 #define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */ 215 #define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */ 216 #define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */ 217 #define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */ 218 #define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */ 219 #define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */ 220 #define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */ 221 #define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */ 222 #define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */ 223 #define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */ 224 #define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */ 225 #define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */ 226 #define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */ 227 #define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */ 228 #define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */ 229 #define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */ 230 231 /* Bit fields for HFXO XTALCTRL */ 232 #define _HFXO_XTALCTRL_RESETVALUE 0x0F8C8C10UL /**< Default value for HFXO_XTALCTRL */ 233 #define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */ 234 #define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */ 235 #define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */ 236 #define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x00000010UL /**< Mode DEFAULT for HFXO_XTALCTRL */ 237 #define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ 238 #define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */ 239 #define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */ 240 #define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000008CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ 241 #define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ 242 #define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */ 243 #define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */ 244 #define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000008CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ 245 #define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ 246 #define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */ 247 #define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */ 248 #define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ 249 #define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ 250 #define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */ 251 #define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */ 252 #define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */ 253 #define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ 254 #define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */ 255 #define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */ 256 #define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */ 257 #define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */ 258 #define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */ 259 #define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */ 260 #define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ 261 #define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ 262 #define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */ 263 #define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */ 264 #define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */ 265 #define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ 266 #define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */ 267 #define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */ 268 #define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */ 269 #define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */ 270 #define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */ 271 #define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */ 272 #define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */ 273 #define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ 274 #define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ 275 276 /* Bit fields for HFXO CFG */ 277 #define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */ 278 #define _HFXO_CFG_MASK 0xF000000DUL /**< Mask for HFXO_CFG */ 279 #define HFXO_CFG_MODE (0x1UL << 0) /**< Crystal Oscillator Mode */ 280 #define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */ 281 #define _HFXO_CFG_MODE_MASK 0x1UL /**< Bit mask for HFXO_MODE */ 282 #define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ 283 #define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */ 284 #define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */ 285 #define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */ 286 #define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */ 287 #define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */ 288 #define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */ 289 #define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */ 290 #define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */ 291 #define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ 292 #define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */ 293 #define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */ 294 #define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */ 295 #define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */ 296 #define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ 297 #define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */ 298 #define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */ 299 #define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */ 300 #define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */ 301 #define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */ 302 303 /* Bit fields for HFXO CTRL */ 304 #define _HFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for HFXO_CTRL */ 305 #define _HFXO_CTRL_MASK 0x80000037UL /**< Mask for HFXO_CTRL */ 306 #define HFXO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ 307 #define _HFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFXO_FORCEEN */ 308 #define _HFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFXO_FORCEEN */ 309 #define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ 310 #define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */ 311 #define HFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand Mode */ 312 #define _HFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFXO_DISONDEMAND */ 313 #define _HFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFXO_DISONDEMAND */ 314 #define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ 315 #define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_CTRL */ 316 #define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */ 317 #define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */ 318 #define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */ 319 #define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ 320 #define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */ 321 #define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */ 322 #define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */ 323 #define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */ 324 #define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ 325 #define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ 326 #define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ 327 #define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */ 328 #define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */ 329 #define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */ 330 #define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */ 331 #define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */ 332 #define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */ 333 #define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ 334 #define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ 335 #define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ 336 #define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */ 337 #define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */ 338 #define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */ 339 340 /* Bit fields for HFXO CMD */ 341 #define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */ 342 #define _HFXO_CMD_MASK 0x00000003UL /**< Mask for HFXO_CMD */ 343 #define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */ 344 #define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */ 345 #define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */ 346 #define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ 347 #define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */ 348 #define HFXO_CMD_MANUALOVERRIDE (0x1UL << 1) /**< Manual Override */ 349 #define _HFXO_CMD_MANUALOVERRIDE_SHIFT 1 /**< Shift value for HFXO_MANUALOVERRIDE */ 350 #define _HFXO_CMD_MANUALOVERRIDE_MASK 0x2UL /**< Bit mask for HFXO_MANUALOVERRIDE */ 351 #define _HFXO_CMD_MANUALOVERRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ 352 #define HFXO_CMD_MANUALOVERRIDE_DEFAULT (_HFXO_CMD_MANUALOVERRIDE_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_CMD */ 353 354 /* Bit fields for HFXO STATUS */ 355 #define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */ 356 #define _HFXO_STATUS_MASK 0xC00F0003UL /**< Mask for HFXO_STATUS */ 357 #define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ 358 #define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ 359 #define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ 360 #define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ 361 #define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */ 362 #define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */ 363 #define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ 364 #define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ 365 #define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ 366 #define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */ 367 #define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ 368 #define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */ 369 #define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */ 370 #define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ 371 #define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */ 372 #define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Hardware */ 373 #define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */ 374 #define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */ 375 #define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ 376 #define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */ 377 #define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */ 378 #define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */ 379 #define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */ 380 #define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ 381 #define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */ 382 #define HFXO_STATUS_FSMLOCK (0x1UL << 30) /**< FSM Lock Status */ 383 #define _HFXO_STATUS_FSMLOCK_SHIFT 30 /**< Shift value for HFXO_FSMLOCK */ 384 #define _HFXO_STATUS_FSMLOCK_MASK 0x40000000UL /**< Bit mask for HFXO_FSMLOCK */ 385 #define _HFXO_STATUS_FSMLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ 386 #define _HFXO_STATUS_FSMLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ 387 #define _HFXO_STATUS_FSMLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ 388 #define HFXO_STATUS_FSMLOCK_DEFAULT (_HFXO_STATUS_FSMLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */ 389 #define HFXO_STATUS_FSMLOCK_UNLOCKED (_HFXO_STATUS_FSMLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for HFXO_STATUS */ 390 #define HFXO_STATUS_FSMLOCK_LOCKED (_HFXO_STATUS_FSMLOCK_LOCKED << 30) /**< Shifted mode LOCKED for HFXO_STATUS */ 391 #define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ 392 #define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */ 393 #define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */ 394 #define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ 395 #define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ 396 #define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ 397 #define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */ 398 #define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */ 399 #define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */ 400 401 /* Bit fields for HFXO IF */ 402 #define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */ 403 #define _HFXO_IF_MASK 0xE0000003UL /**< Mask for HFXO_IF */ 404 #define HFXO_IF_RDY (0x1UL << 0) /**< Ready Interrupt */ 405 #define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ 406 #define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ 407 #define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ 408 #define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */ 409 #define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ 410 #define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ 411 #define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ 412 #define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ 413 #define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */ 414 #define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ 415 #define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ 416 #define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ 417 #define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ 418 #define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */ 419 #define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ 420 #define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ 421 #define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ 422 #define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ 423 #define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */ 424 425 /* Bit fields for HFXO IEN */ 426 #define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */ 427 #define _HFXO_IEN_MASK 0xE0000003UL /**< Mask for HFXO_IEN */ 428 #define HFXO_IEN_RDY (0x1UL << 0) /**< Ready Interrupt */ 429 #define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ 430 #define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ 431 #define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ 432 #define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */ 433 #define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ 434 #define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ 435 #define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ 436 #define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ 437 #define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */ 438 #define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ 439 #define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ 440 #define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ 441 #define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ 442 #define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */ 443 #define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ 444 #define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ 445 #define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ 446 #define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ 447 #define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */ 448 449 /* Bit fields for HFXO LOCK */ 450 #define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */ 451 #define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */ 452 #define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */ 453 #define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */ 454 #define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */ 455 #define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */ 456 #define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */ 457 #define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */ 458 459 /** @} End of group EFR32BG27_HFXO_BitFields */ 460 /** @} End of group EFR32BG27_HFXO */ 461 /** @} End of group Parts */ 462 463 #endif /* EFR32BG27_HFXO_H */ 464
