1/***************************************************************************//** 2 * @file 3 * @brief startup file for Silicon Labs EFR32BG13P devices. 4 * For use with GCC for ARM Embedded Processors 5 ******************************************************************************* 6 * # License 7 * 8 * The licensor of this software is Silicon Laboratories Inc. Your use of this 9 * software is governed by the terms of Silicon Labs Master Software License 10 * Agreement (MSLA) available at 11 * www.silabs.com/about-us/legal/master-software-license-agreement. This 12 * software is Third Party Software licensed by Silicon Labs from a third party 13 * and is governed by the sections of the MSLA applicable to Third Party 14 * Software and the additional terms set forth below. 15 * 16 ******************************************************************************/ 17/* 18 * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 19 * 20 * SPDX-License-Identifier: Apache-2.0 21 * 22 * Licensed under the Apache License, Version 2.0 (the License); you may 23 * not use this file except in compliance with the License. 24 * You may obtain a copy of the License at 25 * 26 * www.apache.org/licenses/LICENSE-2.0 27 * 28 * Unless required by applicable law or agreed to in writing, software 29 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 30 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 31 * See the License for the specific language governing permissions and 32 * limitations under the License. 33 */ 34 35 .syntax unified 36 .arch armv7-m 37 .section .stack 38 .align 3 39#ifdef __STACK_SIZE 40 .equ Stack_Size, __STACK_SIZE 41#else 42 .equ Stack_Size, 0x00000400 43#endif 44 .globl __StackTop 45 .globl __StackLimit 46__StackLimit: 47 .space Stack_Size 48 .size __StackLimit, . - __StackLimit 49__StackTop: 50 .size __StackTop, . - __StackTop 51 52 .section .heap 53 .align 3 54#ifdef __HEAP_SIZE 55 .equ Heap_Size, __HEAP_SIZE 56#else 57 .equ Heap_Size, 0x00000C00 58#endif 59 .globl __HeapBase 60 .globl __HeapLimit 61__HeapBase: 62 .if Heap_Size 63 .space Heap_Size 64 .endif 65 .size __HeapBase, . - __HeapBase 66__HeapLimit: 67 .size __HeapLimit, . - __HeapLimit 68 69 .section .vectors 70 .align 2 71 .globl __Vectors 72__Vectors: 73 .long __StackTop /* Top of Stack */ 74 .long Reset_Handler /* Reset Handler */ 75 .long NMI_Handler /* NMI Handler */ 76 .long HardFault_Handler /* Hard Fault Handler */ 77 .long MemManage_Handler /* MPU Fault Handler */ 78 .long BusFault_Handler /* Bus Fault Handler */ 79 .long UsageFault_Handler /* Usage Fault Handler */ 80 .long Default_Handler /* Reserved */ 81 .long Default_Handler /* Reserved */ 82 .long Default_Handler /* Reserved */ 83 .long Default_Handler /* Reserved */ 84 .long SVC_Handler /* SVCall Handler */ 85 .long DebugMon_Handler /* Debug Monitor Handler */ 86 .long sl_app_properties /* Application properties */ 87 .long PendSV_Handler /* PendSV Handler */ 88 .long SysTick_Handler /* SysTick Handler */ 89 90 /* External interrupts */ 91 .long EMU_IRQHandler /* 0 - EMU */ 92 .long FRC_PRI_IRQHandler /* 1 - FRC_PRI */ 93 .long WDOG0_IRQHandler /* 2 - WDOG0 */ 94 .long WDOG1_IRQHandler /* 3 - WDOG1 */ 95 .long FRC_IRQHandler /* 4 - FRC */ 96 .long MODEM_IRQHandler /* 5 - MODEM */ 97 .long RAC_SEQ_IRQHandler /* 6 - RAC_SEQ */ 98 .long RAC_RSM_IRQHandler /* 7 - RAC_RSM */ 99 .long BUFC_IRQHandler /* 8 - BUFC */ 100 .long LDMA_IRQHandler /* 9 - LDMA */ 101 .long GPIO_EVEN_IRQHandler /* 10 - GPIO_EVEN */ 102 .long TIMER0_IRQHandler /* 11 - TIMER0 */ 103 .long USART0_RX_IRQHandler /* 12 - USART0_RX */ 104 .long USART0_TX_IRQHandler /* 13 - USART0_TX */ 105 .long ACMP0_IRQHandler /* 14 - ACMP0 */ 106 .long ADC0_IRQHandler /* 15 - ADC0 */ 107 .long IDAC0_IRQHandler /* 16 - IDAC0 */ 108 .long I2C0_IRQHandler /* 17 - I2C0 */ 109 .long GPIO_ODD_IRQHandler /* 18 - GPIO_ODD */ 110 .long TIMER1_IRQHandler /* 19 - TIMER1 */ 111 .long USART1_RX_IRQHandler /* 20 - USART1_RX */ 112 .long USART1_TX_IRQHandler /* 21 - USART1_TX */ 113 .long LEUART0_IRQHandler /* 22 - LEUART0 */ 114 .long PCNT0_IRQHandler /* 23 - PCNT0 */ 115 .long CMU_IRQHandler /* 24 - CMU */ 116 .long MSC_IRQHandler /* 25 - MSC */ 117 .long CRYPTO0_IRQHandler /* 26 - CRYPTO0 */ 118 .long LETIMER0_IRQHandler /* 27 - LETIMER0 */ 119 .long AGC_IRQHandler /* 28 - AGC */ 120 .long PROTIMER_IRQHandler /* 29 - PROTIMER */ 121 .long PRORTC_IRQHandler /* 30 - PRORTC */ 122 .long RTCC_IRQHandler /* 31 - RTCC */ 123 .long SYNTH_IRQHandler /* 32 - SYNTH */ 124 .long CRYOTIMER_IRQHandler /* 33 - CRYOTIMER */ 125 .long RFSENSE_IRQHandler /* 34 - RFSENSE */ 126 .long FPUEH_IRQHandler /* 35 - FPUEH */ 127 .long SMU_IRQHandler /* 36 - SMU */ 128 .long WTIMER0_IRQHandler /* 37 - WTIMER0 */ 129 .long USART2_RX_IRQHandler /* 38 - USART2_RX */ 130 .long USART2_TX_IRQHandler /* 39 - USART2_TX */ 131 .long I2C1_IRQHandler /* 40 - I2C1 */ 132 .long VDAC0_IRQHandler /* 41 - VDAC0 */ 133 .long CSEN_IRQHandler /* 42 - CSEN */ 134 .long LESENSE_IRQHandler /* 43 - LESENSE */ 135 .long CRYPTO1_IRQHandler /* 44 - CRYPTO1 */ 136 .long TRNG0_IRQHandler /* 45 - TRNG0 */ 137 .long Default_Handler /* 46 - Reserved */ 138 139 140 .size __Vectors, . - __Vectors 141 142 .text 143 .thumb 144 .thumb_func 145 .align 2 146 .globl Reset_Handler 147 .type Reset_Handler, %function 148Reset_Handler: 149#ifndef __NO_SYSTEM_INIT 150 ldr r0, =SystemInit 151 blx r0 152#endif 153 154/* Firstly it copies data from read only memory to RAM. There are two schemes 155 * to copy. One can copy more than one sections. Another can only copy 156 * one section. The former scheme needs more instructions and read-only 157 * data to implement than the latter. 158 * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. 159 */ 160 161#ifdef __STARTUP_COPY_MULTIPLE 162/* Multiple sections scheme. 163 * 164 * Between symbol address __copy_table_start__ and __copy_table_end__, 165 * there are array of triplets, each of which specify: 166 * offset 0: LMA of start of a section to copy from 167 * offset 4: VMA of start of a section to copy to 168 * offset 8: size of the section to copy. Must be multiply of 4 169 * 170 * All addresses must be aligned to 4 bytes boundary. 171 */ 172 ldr r4, =__copy_table_start__ 173 ldr r5, =__copy_table_end__ 174 175.L_loop0: 176 cmp r4, r5 177 bge .L_loop0_done 178 ldr r1, [r4] 179 ldr r2, [r4, #4] 180 ldr r3, [r4, #8] 181 182.L_loop0_0: 183 subs r3, #4 184 ittt ge 185 ldrge r0, [r1, r3] 186 strge r0, [r2, r3] 187 bge .L_loop0_0 188 189 adds r4, #12 190 b .L_loop0 191 192.L_loop0_done: 193#else 194/* Single section scheme. 195 * 196 * The ranges of copy from/to are specified by following symbols 197 * __etext: LMA of start of the section to copy from. Usually end of text 198 * __data_start__: VMA of start of the section to copy to 199 * __data_end__: VMA of end of the section to copy to 200 * 201 * All addresses must be aligned to 4 bytes boundary. 202 */ 203 ldr r1, =__etext 204 ldr r2, =__data_start__ 205 ldr r3, =__data_end__ 206 207.L_loop1: 208 cmp r2, r3 209 ittt lt 210 ldrlt r0, [r1], #4 211 strlt r0, [r2], #4 212 blt .L_loop1 213#endif /* __STARTUP_COPY_MULTIPLE */ 214 215/* This part of work usually is done in C library startup code. Otherwise, 216 * define this macro to enable it in this startup. 217 * 218 * There are two schemes too. One can clear multiple BSS sections. Another 219 * can only clear one section. The former is more size expensive than the 220 * latter. 221 * 222 * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. 223 * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. 224 */ 225#ifdef __STARTUP_CLEAR_BSS_MULTIPLE 226/* Multiple sections scheme. 227 * 228 * Between symbol address __zero_table_start__ and __zero_table_end__, 229 * there are array of tuples specifying: 230 * offset 0: Start of a BSS section 231 * offset 4: Size of this BSS section. Must be multiply of 4 232 */ 233 ldr r3, =__zero_table_start__ 234 ldr r4, =__zero_table_end__ 235 236.L_loop2: 237 cmp r3, r4 238 bge .L_loop2_done 239 ldr r1, [r3] 240 ldr r2, [r3, #4] 241 movs r0, 0 242 243.L_loop2_0: 244 subs r2, #4 245 itt ge 246 strge r0, [r1, r2] 247 bge .L_loop2_0 248 adds r3, #8 249 b .L_loop2 250.L_loop2_done: 251#elif defined (__STARTUP_CLEAR_BSS) 252/* Single BSS section scheme. 253 * 254 * The BSS section is specified by following symbols 255 * __bss_start__: start of the BSS section. 256 * __bss_end__: end of the BSS section. 257 * 258 * Both addresses must be aligned to 4 bytes boundary. 259 */ 260 ldr r1, =__bss_start__ 261 ldr r2, =__bss_end__ 262 263 movs r0, 0 264.L_loop3: 265 cmp r1, r2 266 itt lt 267 strlt r0, [r1], #4 268 blt .L_loop3 269#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ 270 271#ifndef __START 272#define __START _start 273#endif 274 bl __START 275 276 .pool 277 .size Reset_Handler, . - Reset_Handler 278 279 .align 1 280 .thumb_func 281 .weak Default_Handler 282 .type Default_Handler, %function 283 .weak sl_app_properties 284 .type sl_app_properties, %common 285Default_Handler: 286sl_app_properties: /* Provide a dummy value for the sl_app_properties symbol. */ 287 b . 288 .size Default_Handler, . - Default_Handler 289 290/* Macro to define default handlers. Default handler 291 * will be weak symbol and just dead loops. They can be 292 * overwritten by other handlers. 293 */ 294 .macro def_irq_handler handler_name 295 .weak \handler_name 296 .set \handler_name, Default_Handler 297 .endm 298 299 def_irq_handler NMI_Handler 300 def_irq_handler HardFault_Handler 301 def_irq_handler MemManage_Handler 302 def_irq_handler BusFault_Handler 303 def_irq_handler UsageFault_Handler 304 def_irq_handler SVC_Handler 305 def_irq_handler DebugMon_Handler 306 def_irq_handler PendSV_Handler 307 def_irq_handler SysTick_Handler 308 309 310 def_irq_handler EMU_IRQHandler 311 def_irq_handler FRC_PRI_IRQHandler 312 def_irq_handler WDOG0_IRQHandler 313 def_irq_handler WDOG1_IRQHandler 314 def_irq_handler FRC_IRQHandler 315 def_irq_handler MODEM_IRQHandler 316 def_irq_handler RAC_SEQ_IRQHandler 317 def_irq_handler RAC_RSM_IRQHandler 318 def_irq_handler BUFC_IRQHandler 319 def_irq_handler LDMA_IRQHandler 320 def_irq_handler GPIO_EVEN_IRQHandler 321 def_irq_handler TIMER0_IRQHandler 322 def_irq_handler USART0_RX_IRQHandler 323 def_irq_handler USART0_TX_IRQHandler 324 def_irq_handler ACMP0_IRQHandler 325 def_irq_handler ADC0_IRQHandler 326 def_irq_handler IDAC0_IRQHandler 327 def_irq_handler I2C0_IRQHandler 328 def_irq_handler GPIO_ODD_IRQHandler 329 def_irq_handler TIMER1_IRQHandler 330 def_irq_handler USART1_RX_IRQHandler 331 def_irq_handler USART1_TX_IRQHandler 332 def_irq_handler LEUART0_IRQHandler 333 def_irq_handler PCNT0_IRQHandler 334 def_irq_handler CMU_IRQHandler 335 def_irq_handler MSC_IRQHandler 336 def_irq_handler CRYPTO0_IRQHandler 337 def_irq_handler LETIMER0_IRQHandler 338 def_irq_handler AGC_IRQHandler 339 def_irq_handler PROTIMER_IRQHandler 340 def_irq_handler PRORTC_IRQHandler 341 def_irq_handler RTCC_IRQHandler 342 def_irq_handler SYNTH_IRQHandler 343 def_irq_handler CRYOTIMER_IRQHandler 344 def_irq_handler RFSENSE_IRQHandler 345 def_irq_handler FPUEH_IRQHandler 346 def_irq_handler SMU_IRQHandler 347 def_irq_handler WTIMER0_IRQHandler 348 def_irq_handler USART2_RX_IRQHandler 349 def_irq_handler USART2_TX_IRQHandler 350 def_irq_handler I2C1_IRQHandler 351 def_irq_handler VDAC0_IRQHandler 352 def_irq_handler CSEN_IRQHandler 353 def_irq_handler LESENSE_IRQHandler 354 def_irq_handler CRYPTO1_IRQHandler 355 def_irq_handler TRNG0_IRQHandler 356 357 .end 358
