1 /***************************************************************************//** 2 * @file 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File 4 * for EFM32WG890F128 5 ******************************************************************************* 6 * # License 7 * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b> 8 ******************************************************************************* 9 * 10 * SPDX-License-Identifier: Zlib 11 * 12 * The licensor of this software is Silicon Laboratories Inc. 13 * 14 * This software is provided 'as-is', without any express or implied 15 * warranty. In no event will the authors be held liable for any damages 16 * arising from the use of this software. 17 * 18 * Permission is granted to anyone to use this software for any purpose, 19 * including commercial applications, and to alter it and redistribute it 20 * freely, subject to the following restrictions: 21 * 22 * 1. The origin of this software must not be misrepresented; you must not 23 * claim that you wrote the original software. If you use this software 24 * in a product, an acknowledgment in the product documentation would be 25 * appreciated but is not required. 26 * 2. Altered source versions must be plainly marked as such, and must not be 27 * misrepresented as being the original software. 28 * 3. This notice may not be removed or altered from any source distribution. 29 * 30 ******************************************************************************/ 31 32 #if defined(__ICCARM__) 33 #pragma system_include /* Treat file as system include file. */ 34 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 35 #pragma clang system_header /* Treat file as system include file. */ 36 #endif 37 38 #ifndef EFM32WG890F128_H 39 #define EFM32WG890F128_H 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /***************************************************************************//** 46 * @addtogroup Parts 47 * @{ 48 ******************************************************************************/ 49 50 /***************************************************************************//** 51 * @defgroup EFM32WG890F128 EFM32WG890F128 52 * @{ 53 ******************************************************************************/ 54 55 /** Interrupt Number Definition */ 56 typedef enum IRQn{ 57 /****** Cortex-M4 Processor Exceptions Numbers ********************************************/ 58 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ 59 HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ 60 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ 61 BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ 62 UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ 63 SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ 64 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ 65 PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ 66 SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ 67 68 /****** EFM32WG Peripheral Interrupt Numbers **********************************************/ 69 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */ 70 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */ 71 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */ 72 USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */ 73 USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */ 74 ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */ 75 ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */ 76 DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */ 77 I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */ 78 I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */ 79 GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */ 80 TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */ 81 TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */ 82 TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */ 83 USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */ 84 USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */ 85 LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */ 86 USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */ 87 USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */ 88 UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */ 89 UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */ 90 UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */ 91 UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */ 92 LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */ 93 LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */ 94 LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */ 95 PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */ 96 PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */ 97 PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */ 98 RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */ 99 BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */ 100 CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */ 101 VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */ 102 LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */ 103 MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */ 104 AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */ 105 EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */ 106 EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */ 107 FPUEH_IRQn = 39, /*!< 39 EFM32 FPUEH Interrupt */ 108 } IRQn_Type; 109 110 /***************************************************************************//** 111 * @defgroup EFM32WG890F128_Core EFM32WG890F128 Core 112 * @{ 113 * @brief Processor and Core Peripheral Section 114 ******************************************************************************/ 115 #define __MPU_PRESENT 1U /**< Presence of MPU */ 116 #define __FPU_PRESENT 1U /**< Presence of FPU */ 117 #define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ 118 #define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ 119 #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ 120 121 /** @} End of group EFM32WG890F128_Core */ 122 123 /***************************************************************************//** 124 * @defgroup EFM32WG890F128_Part EFM32WG890F128 Part 125 * @{ 126 ******************************************************************************/ 127 128 /** Part family */ 129 #define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */ 130 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ 131 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ 132 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ 133 #define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /**< Silicon Labs internal use only, may change any time */ 134 #define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /**< Silicon Labs internal use only, may change any time */ 135 #define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ 136 #define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ 137 138 /* If part number is not defined as compiler option, define it */ 139 #if !defined(EFM32WG890F128) 140 #define EFM32WG890F128 1 /**< Wonder Gecko Part */ 141 #endif 142 143 /** Configure part number */ 144 #define PART_NUMBER "EFM32WG890F128" /**< Part Number */ 145 146 /** Memory Base addresses and limits */ 147 #define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ 148 #define RAM_MEM_SIZE (0x40000UL) /**< RAM available address space */ 149 #define RAM_MEM_END (0x2003FFFFUL) /**< RAM end address */ 150 #define RAM_MEM_BITS (0x18UL) /**< RAM used bits */ 151 #define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ 152 #define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ 153 #define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ 154 #define EBI_CODE_MEM_BITS (0x28UL) /**< EBI_CODE used bits */ 155 #define USBC_MEM_BASE (0x40100000UL) /**< USBC base address */ 156 #define USBC_MEM_SIZE (0x40000UL) /**< USBC available address space */ 157 #define USBC_MEM_END (0x4013FFFFUL) /**< USBC end address */ 158 #define USBC_MEM_BITS (0x18UL) /**< USBC used bits */ 159 #define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */ 160 #define RAM_CODE_MEM_SIZE (0x20000UL) /**< RAM_CODE available address space */ 161 #define RAM_CODE_MEM_END (0x1001FFFFUL) /**< RAM_CODE end address */ 162 #define RAM_CODE_MEM_BITS (0x17UL) /**< RAM_CODE used bits */ 163 #define PER_MEM_BASE (0x40000000UL) /**< PER base address */ 164 #define PER_MEM_SIZE (0xE0000UL) /**< PER available address space */ 165 #define PER_MEM_END (0x400DFFFFUL) /**< PER end address */ 166 #define PER_MEM_BITS (0x20UL) /**< PER used bits */ 167 #define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ 168 #define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ 169 #define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ 170 #define EBI_MEM_BITS (0x30UL) /**< EBI used bits */ 171 #define FLASH_MEM_BASE (0x0UL) /**< FLASH base address */ 172 #define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */ 173 #define FLASH_MEM_END (0xFFFFFFFUL) /**< FLASH end address */ 174 #define FLASH_MEM_BITS (0x28UL) /**< FLASH used bits */ 175 #define AES_MEM_BASE (0x400E0000UL) /**< AES base address */ 176 #define AES_MEM_SIZE (0x400UL) /**< AES available address space */ 177 #define AES_MEM_END (0x400E03FFUL) /**< AES end address */ 178 #define AES_MEM_BITS (0x10UL) /**< AES used bits */ 179 180 /** Bit banding area */ 181 #define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ 182 #define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ 183 184 /** Flash and SRAM limits for EFM32WG890F128 */ 185 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ 186 #define FLASH_SIZE (0x00020000UL) /**< Available Flash Memory */ 187 #define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */ 188 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ 189 #define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */ 190 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ 191 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ 192 #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */ 193 #define EXT_IRQ_COUNT 40 /**< Number of External (NVIC) interrupts */ 194 195 /** AF channels connect the different on-chip peripherals with the af-mux */ 196 #define AFCHAN_MAX 163U 197 #define AFCHANLOC_MAX 7U 198 /** Analog AF channels */ 199 #define AFACHAN_MAX 53U 200 201 /* Part number capabilities */ 202 203 #define USART_PRESENT /**< USART is available in this part */ 204 #define USART_COUNT 3 /**< 3 USARTs available */ 205 #define UART_PRESENT /**< UART is available in this part */ 206 #define UART_COUNT 2 /**< 2 UARTs available */ 207 #define TIMER_PRESENT /**< TIMER is available in this part */ 208 #define TIMER_COUNT 4 /**< 4 TIMERs available */ 209 #define ACMP_PRESENT /**< ACMP is available in this part */ 210 #define ACMP_COUNT 2 /**< 2 ACMPs available */ 211 #define LEUART_PRESENT /**< LEUART is available in this part */ 212 #define LEUART_COUNT 2 /**< 2 LEUARTs available */ 213 #define LETIMER_PRESENT /**< LETIMER is available in this part */ 214 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */ 215 #define PCNT_PRESENT /**< PCNT is available in this part */ 216 #define PCNT_COUNT 3 /**< 3 PCNTs available */ 217 #define I2C_PRESENT /**< I2C is available in this part */ 218 #define I2C_COUNT 2 /**< 2 I2Cs available */ 219 #define ADC_PRESENT /**< ADC is available in this part */ 220 #define ADC_COUNT 1 /**< 1 ADCs available */ 221 #define DAC_PRESENT /**< DAC is available in this part */ 222 #define DAC_COUNT 1 /**< 1 DACs available */ 223 #define DMA_PRESENT /**< DMA is available in this part */ 224 #define DMA_COUNT 1 /**< 1 DMA available */ 225 #define AES_PRESENT /**< AES is available in this part */ 226 #define AES_COUNT 1 /**< 1 AES available */ 227 #define LE_PRESENT /**< LE is available in this part */ 228 #define LE_COUNT 1 /**< 1 LE available */ 229 #define MSC_PRESENT /**< MSC is available in this part */ 230 #define MSC_COUNT 1 /**< 1 MSC available */ 231 #define EMU_PRESENT /**< EMU is available in this part */ 232 #define EMU_COUNT 1 /**< 1 EMU available */ 233 #define RMU_PRESENT /**< RMU is available in this part */ 234 #define RMU_COUNT 1 /**< 1 RMU available */ 235 #define CMU_PRESENT /**< CMU is available in this part */ 236 #define CMU_COUNT 1 /**< 1 CMU available */ 237 #define LESENSE_PRESENT /**< LESENSE is available in this part */ 238 #define LESENSE_COUNT 1 /**< 1 LESENSE available */ 239 #define EBI_PRESENT /**< EBI is available in this part */ 240 #define EBI_COUNT 1 /**< 1 EBI available */ 241 #define FPUEH_PRESENT /**< FPUEH is available in this part */ 242 #define FPUEH_COUNT 1 /**< 1 FPUEH available */ 243 #define RTC_PRESENT /**< RTC is available in this part */ 244 #define RTC_COUNT 1 /**< 1 RTC available */ 245 #define GPIO_PRESENT /**< GPIO is available in this part */ 246 #define GPIO_COUNT 1 /**< 1 GPIO available */ 247 #define VCMP_PRESENT /**< VCMP is available in this part */ 248 #define VCMP_COUNT 1 /**< 1 VCMP available */ 249 #define PRS_PRESENT /**< PRS is available in this part */ 250 #define PRS_COUNT 1 /**< 1 PRS available */ 251 #define OPAMP_PRESENT /**< OPAMP is available in this part */ 252 #define OPAMP_COUNT 1 /**< 1 OPAMP available */ 253 #define BU_PRESENT /**< BU is available in this part */ 254 #define BU_COUNT 1 /**< 1 BU available */ 255 #define LCD_PRESENT /**< LCD is available in this part */ 256 #define LCD_COUNT 1 /**< 1 LCD available */ 257 #define BURTC_PRESENT /**< BURTC is available in this part */ 258 #define BURTC_COUNT 1 /**< 1 BURTC available */ 259 #define HFXTAL_PRESENT /**< HFXTAL is available in this part */ 260 #define HFXTAL_COUNT 1 /**< 1 HFXTAL available */ 261 #define LFXTAL_PRESENT /**< LFXTAL is available in this part */ 262 #define LFXTAL_COUNT 1 /**< 1 LFXTAL available */ 263 #define WDOG_PRESENT /**< WDOG is available in this part */ 264 #define WDOG_COUNT 1 /**< 1 WDOG available */ 265 #define DBG_PRESENT /**< DBG is available in this part */ 266 #define DBG_COUNT 1 /**< 1 DBG available */ 267 #define ETM_PRESENT /**< ETM is available in this part */ 268 #define ETM_COUNT 1 /**< 1 ETM available */ 269 #define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ 270 #define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ 271 #define ANALOG_PRESENT /**< ANALOG is available in this part */ 272 #define ANALOG_COUNT 1 /**< 1 ANALOG available */ 273 274 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 275 #include "system_efm32wg.h" /* System Header */ 276 277 /** @} End of group EFM32WG890F128_Part */ 278 279 /***************************************************************************//** 280 * @defgroup EFM32WG890F128_Peripheral_TypeDefs EFM32WG890F128 Peripheral TypeDefs 281 * @{ 282 * @brief Device Specific Peripheral Register Structures 283 ******************************************************************************/ 284 285 #include "efm32wg_dma_ch.h" 286 #include "efm32wg_dma.h" 287 #include "efm32wg_aes.h" 288 #include "efm32wg_msc.h" 289 #include "efm32wg_emu.h" 290 #include "efm32wg_rmu.h" 291 292 /***************************************************************************//** 293 * @defgroup EFM32WG890F128_CMU EFM32WG890F128 CMU 294 * @{ 295 * @brief EFM32WG890F128_CMU Register Declaration 296 ******************************************************************************/ 297 typedef struct { 298 __IOM uint32_t CTRL; /**< CMU Control Register */ 299 __IOM uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */ 300 __IOM uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */ 301 __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ 302 __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ 303 __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ 304 __IOM uint32_t CALCTRL; /**< Calibration Control Register */ 305 __IOM uint32_t CALCNT; /**< Calibration Counter Register */ 306 __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ 307 __IOM uint32_t CMD; /**< Command Register */ 308 __IOM uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */ 309 __IM uint32_t STATUS; /**< Status Register */ 310 __IM uint32_t IF; /**< Interrupt Flag Register */ 311 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 312 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 313 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 314 __IOM uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */ 315 __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ 316 uint32_t RESERVED0[2U]; /**< Reserved for future use **/ 317 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 318 __IOM uint32_t FREEZE; /**< Freeze Register */ 319 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ 320 uint32_t RESERVED1[1U]; /**< Reserved for future use **/ 321 __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ 322 323 uint32_t RESERVED2[1U]; /**< Reserved for future use **/ 324 __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */ 325 uint32_t RESERVED3[1U]; /**< Reserved for future use **/ 326 __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ 327 uint32_t RESERVED4[1U]; /**< Reserved for future use **/ 328 __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ 329 __IOM uint32_t LCDCTRL; /**< LCD Control Register */ 330 __IOM uint32_t ROUTE; /**< I/O Routing Register */ 331 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 332 } CMU_TypeDef; /**< CMU Register Declaration *//** @} */ 333 334 #include "efm32wg_lesense_st.h" 335 #include "efm32wg_lesense_buf.h" 336 #include "efm32wg_lesense_ch.h" 337 #include "efm32wg_lesense.h" 338 #include "efm32wg_ebi.h" 339 #include "efm32wg_fpueh.h" 340 #include "efm32wg_usart.h" 341 #include "efm32wg_timer_cc.h" 342 #include "efm32wg_timer.h" 343 #include "efm32wg_acmp.h" 344 #include "efm32wg_leuart.h" 345 #include "efm32wg_rtc.h" 346 #include "efm32wg_letimer.h" 347 #include "efm32wg_pcnt.h" 348 #include "efm32wg_i2c.h" 349 #include "efm32wg_gpio_p.h" 350 #include "efm32wg_gpio.h" 351 #include "efm32wg_vcmp.h" 352 #include "efm32wg_prs_ch.h" 353 354 /***************************************************************************//** 355 * @defgroup EFM32WG890F128_PRS EFM32WG890F128 PRS 356 * @{ 357 * @brief EFM32WG890F128_PRS Register Declaration 358 ******************************************************************************/ 359 typedef struct { 360 __IOM uint32_t SWPULSE; /**< Software Pulse Register */ 361 __IOM uint32_t SWLEVEL; /**< Software Level Register */ 362 __IOM uint32_t ROUTE; /**< I/O Routing Register */ 363 364 uint32_t RESERVED0[1U]; /**< Reserved registers */ 365 PRS_CH_TypeDef CH[12U]; /**< Channel registers */ 366 } PRS_TypeDef; /**< PRS Register Declaration *//** @} */ 367 368 #include "efm32wg_adc.h" 369 #include "efm32wg_dac.h" 370 #include "efm32wg_lcd.h" 371 #include "efm32wg_burtc_ret.h" 372 #include "efm32wg_burtc.h" 373 #include "efm32wg_wdog.h" 374 #include "efm32wg_etm.h" 375 #include "efm32wg_dma_descriptor.h" 376 #include "efm32wg_devinfo.h" 377 #include "efm32wg_romtable.h" 378 #include "efm32wg_calibrate.h" 379 380 /** @} End of group EFM32WG890F128_Peripheral_TypeDefs */ 381 382 /***************************************************************************//** 383 * @defgroup EFM32WG890F128_Peripheral_Base EFM32WG890F128 Peripheral Memory Map 384 * @{ 385 ******************************************************************************/ 386 387 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ 388 #define AES_BASE (0x400E0000UL) /**< AES base address */ 389 #define MSC_BASE (0x400C0000UL) /**< MSC base address */ 390 #define EMU_BASE (0x400C6000UL) /**< EMU base address */ 391 #define RMU_BASE (0x400CA000UL) /**< RMU base address */ 392 #define CMU_BASE (0x400C8000UL) /**< CMU base address */ 393 #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */ 394 #define EBI_BASE (0x40008000UL) /**< EBI base address */ 395 #define FPUEH_BASE (0x400C1C00UL) /**< FPUEH base address */ 396 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */ 397 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */ 398 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */ 399 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */ 400 #define UART1_BASE (0x4000E400UL) /**< UART1 base address */ 401 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */ 402 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */ 403 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */ 404 #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */ 405 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */ 406 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */ 407 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */ 408 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */ 409 #define RTC_BASE (0x40080000UL) /**< RTC base address */ 410 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */ 411 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */ 412 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */ 413 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */ 414 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */ 415 #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */ 416 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ 417 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */ 418 #define PRS_BASE (0x400CC000UL) /**< PRS base address */ 419 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ 420 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */ 421 #define LCD_BASE (0x4008A000UL) /**< LCD base address */ 422 #define BURTC_BASE (0x40081000UL) /**< BURTC base address */ 423 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */ 424 #define ETM_BASE (0xE0041000UL) /**< ETM base address */ 425 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */ 426 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ 427 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ 428 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ 429 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ 430 431 /** @} End of group EFM32WG890F128_Peripheral_Base */ 432 433 /***************************************************************************//** 434 * @defgroup EFM32WG890F128_Peripheral_Declaration EFM32WG890F128 Peripheral Declarations 435 * @{ 436 ******************************************************************************/ 437 438 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */ 439 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */ 440 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ 441 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ 442 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ 443 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ 444 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ 445 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ 446 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ 447 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ 448 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ 449 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ 450 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ 451 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ 452 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ 453 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ 454 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ 455 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ 456 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ 457 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ 458 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ 459 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ 460 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ 461 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ 462 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ 463 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ 464 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ 465 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ 466 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ 467 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ 468 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */ 469 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ 470 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ 471 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */ 472 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ 473 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ 474 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */ 475 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ 476 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */ 477 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ 478 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ 479 480 /** @} End of group EFM32WG890F128_Peripheral_Declaration */ 481 482 /***************************************************************************//** 483 * @defgroup EFM32WG890F128_BitFields EFM32WG890F128 Bit Fields 484 * @{ 485 ******************************************************************************/ 486 487 /***************************************************************************//** 488 * @addtogroup EFM32WG890F128_PRS_Signals 489 * @{ 490 * @brief PRS Signal names 491 ******************************************************************************/ 492 #define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */ 493 #define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */ 494 #define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */ 495 #define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */ 496 #define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */ 497 #define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */ 498 #define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */ 499 #define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */ 500 #define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */ 501 #define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */ 502 #define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */ 503 #define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */ 504 #define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */ 505 #define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */ 506 #define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */ 507 #define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */ 508 #define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */ 509 #define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */ 510 #define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */ 511 #define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */ 512 #define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */ 513 #define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */ 514 #define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */ 515 #define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */ 516 #define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */ 517 #define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */ 518 #define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */ 519 #define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */ 520 #define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */ 521 #define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */ 522 #define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */ 523 #define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */ 524 #define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */ 525 #define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */ 526 #define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */ 527 #define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */ 528 #define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */ 529 #define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */ 530 #define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */ 531 #define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */ 532 #define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */ 533 #define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */ 534 #define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */ 535 #define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */ 536 #define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */ 537 #define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */ 538 #define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */ 539 #define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */ 540 #define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */ 541 #define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */ 542 #define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */ 543 #define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */ 544 #define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */ 545 #define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */ 546 #define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */ 547 #define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */ 548 #define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */ 549 #define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */ 550 #define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */ 551 #define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */ 552 #define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */ 553 #define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */ 554 #define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */ 555 #define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */ 556 #define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */ 557 #define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */ 558 #define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */ 559 #define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */ 560 #define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */ 561 #define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */ 562 #define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */ 563 #define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */ 564 #define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */ 565 #define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */ 566 #define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */ 567 #define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */ 568 #define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */ 569 #define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */ 570 #define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */ 571 #define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */ 572 573 /** @} End of group EFM32WG890F128_PRS */ 574 575 #include "efm32wg_dmareq.h" 576 #include "efm32wg_dmactrl.h" 577 #include "efm32wg_uart.h" 578 579 /***************************************************************************//** 580 * @defgroup EFM32WG890F128_CMU_BitFields EFM32WG890F128_CMU Bit Fields 581 * @{ 582 ******************************************************************************/ 583 584 /* Bit fields for CMU CTRL */ 585 #define _CMU_CTRL_RESETVALUE 0x000C262CUL /**< Default value for CMU_CTRL */ 586 #define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */ 587 #define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */ 588 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */ 589 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 590 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */ 591 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */ 592 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */ 593 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ 594 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */ 595 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */ 596 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */ 597 #define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */ 598 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */ 599 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */ 600 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */ 601 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */ 602 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */ 603 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */ 604 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */ 605 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */ 606 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */ 607 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */ 608 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */ 609 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */ 610 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */ 611 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ 612 #define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */ 613 #define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */ 614 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ 615 #define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */ 616 #define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */ 617 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */ 618 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */ 619 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */ 620 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 621 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */ 622 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */ 623 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */ 624 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */ 625 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */ 626 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */ 627 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */ 628 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */ 629 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */ 630 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */ 631 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */ 632 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */ 633 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */ 634 #define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */ 635 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */ 636 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 637 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */ 638 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */ 639 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */ 640 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */ 641 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */ 642 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */ 643 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */ 644 #define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */ 645 #define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */ 646 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */ 647 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */ 648 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ 649 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */ 650 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */ 651 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */ 652 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */ 653 #define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */ 654 #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */ 655 #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 656 #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */ 657 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */ 658 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */ 659 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */ 660 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 661 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */ 662 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */ 663 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */ 664 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */ 665 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */ 666 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */ 667 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */ 668 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */ 669 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */ 670 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */ 671 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */ 672 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */ 673 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */ 674 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */ 675 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */ 676 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 677 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */ 678 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */ 679 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */ 680 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */ 681 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */ 682 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */ 683 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */ 684 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */ 685 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ 686 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */ 687 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */ 688 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */ 689 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */ 690 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */ 691 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */ 692 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */ 693 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */ 694 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */ 695 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */ 696 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 697 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */ 698 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */ 699 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */ 700 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */ 701 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */ 702 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */ 703 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */ 704 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */ 705 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */ 706 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */ 707 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */ 708 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */ 709 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */ 710 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */ 711 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */ 712 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */ 713 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ 714 #define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */ 715 #define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */ 716 #define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */ 717 #define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 718 #define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */ 719 #define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */ 720 #define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */ 721 #define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */ 722 #define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */ 723 #define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */ 724 #define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */ 725 #define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */ 726 #define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 727 #define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */ 728 729 /* Bit fields for CMU HFCORECLKDIV */ 730 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */ 731 #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */ 732 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */ 733 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */ 734 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */ 735 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */ 736 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */ 737 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */ 738 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */ 739 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */ 740 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */ 741 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */ 742 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */ 743 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */ 744 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */ 745 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */ 746 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */ 747 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */ 748 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */ 749 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */ 750 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */ 751 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */ 752 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */ 753 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */ 754 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */ 755 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */ 756 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */ 757 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */ 758 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */ 759 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */ 760 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */ 761 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */ 762 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */ 763 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */ 764 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */ 765 766 /* Bit fields for CMU HFPERCLKDIV */ 767 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */ 768 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */ 769 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */ 770 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */ 771 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */ 772 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */ 773 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */ 774 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */ 775 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */ 776 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */ 777 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */ 778 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */ 779 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */ 780 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */ 781 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */ 782 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */ 783 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */ 784 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */ 785 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */ 786 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */ 787 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */ 788 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */ 789 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */ 790 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */ 791 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */ 792 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */ 793 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */ 794 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */ 795 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */ 796 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */ 797 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */ 798 799 /* Bit fields for CMU HFRCOCTRL */ 800 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */ 801 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */ 802 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 803 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */ 804 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 805 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 806 #define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */ 807 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */ 808 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */ 809 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */ 810 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */ 811 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 812 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */ 813 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */ 814 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */ 815 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */ 816 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */ 817 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */ 818 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 819 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */ 820 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */ 821 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */ 822 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */ 823 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */ 824 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 825 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 826 827 /* Bit fields for CMU LFRCOCTRL */ 828 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */ 829 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */ 830 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 831 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 832 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 833 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 834 835 /* Bit fields for CMU AUXHFRCOCTRL */ 836 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */ 837 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */ 838 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 839 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */ 840 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 841 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 842 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */ 843 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */ 844 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 845 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */ 846 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */ 847 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */ 848 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */ 849 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */ 850 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */ 851 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 852 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */ 853 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */ 854 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */ 855 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */ 856 #define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */ 857 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */ 858 859 /* Bit fields for CMU CALCTRL */ 860 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ 861 #define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */ 862 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ 863 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ 864 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 865 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ 866 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ 867 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ 868 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ 869 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ 870 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 871 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ 872 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ 873 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ 874 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ 875 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ 876 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */ 877 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */ 878 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 879 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ 880 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ 881 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ 882 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ 883 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ 884 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ 885 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 886 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */ 887 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */ 888 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */ 889 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */ 890 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */ 891 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ 892 #define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */ 893 #define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */ 894 #define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */ 895 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 896 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 897 898 /* Bit fields for CMU CALCNT */ 899 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ 900 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ 901 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ 902 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ 903 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ 904 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ 905 906 /* Bit fields for CMU OSCENCMD */ 907 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ 908 #define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */ 909 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ 910 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ 911 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ 912 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 913 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 914 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ 915 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ 916 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ 917 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 918 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 919 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ 920 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ 921 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ 922 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 923 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 924 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ 925 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ 926 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ 927 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 928 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 929 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ 930 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ 931 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ 932 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 933 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 934 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ 935 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ 936 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ 937 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 938 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 939 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ 940 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ 941 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ 942 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 943 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 944 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ 945 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ 946 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ 947 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 948 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 949 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ 950 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ 951 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ 952 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 953 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 954 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ 955 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ 956 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ 957 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 958 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 959 960 /* Bit fields for CMU CMD */ 961 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ 962 #define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */ 963 #define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */ 964 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */ 965 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 966 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */ 967 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */ 968 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */ 969 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */ 970 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ 971 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */ 972 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */ 973 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */ 974 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */ 975 #define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */ 976 #define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */ 977 #define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */ 978 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 979 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */ 980 #define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */ 981 #define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */ 982 #define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */ 983 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 984 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ 985 986 /* Bit fields for CMU LFCLKSEL */ 987 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */ 988 #define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */ 989 #define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ 990 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */ 991 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ 992 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */ 993 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */ 994 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */ 995 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ 996 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ 997 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ 998 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */ 999 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */ 1000 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ 1001 #define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */ 1002 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */ 1003 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ 1004 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */ 1005 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */ 1006 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */ 1007 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ 1008 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ 1009 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ 1010 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */ 1011 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */ 1012 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ 1013 #define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */ 1014 #define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */ 1015 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */ 1016 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */ 1017 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ 1018 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */ 1019 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ 1020 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ 1021 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */ 1022 #define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */ 1023 #define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */ 1024 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */ 1025 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */ 1026 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ 1027 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */ 1028 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ 1029 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ 1030 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */ 1031 1032 /* Bit fields for CMU STATUS */ 1033 #define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */ 1034 #define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */ 1035 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ 1036 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ 1037 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ 1038 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 1039 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ 1040 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ 1041 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ 1042 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ 1043 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 1044 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ 1045 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ 1046 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ 1047 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ 1048 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1049 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ 1050 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ 1051 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ 1052 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ 1053 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1054 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ 1055 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ 1056 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ 1057 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ 1058 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1059 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ 1060 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ 1061 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ 1062 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ 1063 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1064 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ 1065 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ 1066 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ 1067 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ 1068 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1069 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ 1070 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ 1071 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ 1072 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ 1073 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1074 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ 1075 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ 1076 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ 1077 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ 1078 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1079 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ 1080 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ 1081 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ 1082 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ 1083 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1084 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ 1085 #define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */ 1086 #define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */ 1087 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */ 1088 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 1089 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ 1090 #define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */ 1091 #define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */ 1092 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */ 1093 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1094 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ 1095 #define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */ 1096 #define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */ 1097 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */ 1098 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1099 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ 1100 #define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */ 1101 #define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */ 1102 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */ 1103 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1104 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ 1105 #define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */ 1106 #define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */ 1107 #define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */ 1108 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1109 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */ 1110 1111 /* Bit fields for CMU IF */ 1112 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ 1113 #define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */ 1114 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ 1115 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1116 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1117 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ 1118 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ 1119 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ 1120 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1121 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1122 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1123 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ 1124 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ 1125 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1126 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1127 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1128 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ 1129 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ 1130 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1131 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1132 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1133 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ 1134 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ 1135 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1136 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1137 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1138 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ 1139 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ 1140 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1141 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1142 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1143 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ 1144 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ 1145 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1146 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1147 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1148 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ 1149 1150 /* Bit fields for CMU IFS */ 1151 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ 1152 #define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */ 1153 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */ 1154 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1155 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1156 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1157 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ 1158 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */ 1159 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1160 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1161 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1162 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ 1163 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */ 1164 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1165 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1166 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1167 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ 1168 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */ 1169 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1170 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1171 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1172 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ 1173 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */ 1174 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1175 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1176 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1177 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ 1178 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */ 1179 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1180 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1181 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1182 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ 1183 #define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */ 1184 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1185 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1186 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1187 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ 1188 1189 /* Bit fields for CMU IFC */ 1190 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ 1191 #define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */ 1192 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */ 1193 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1194 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1195 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1196 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ 1197 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */ 1198 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1199 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1200 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1201 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ 1202 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */ 1203 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1204 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1205 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1206 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ 1207 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */ 1208 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1209 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1210 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1211 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ 1212 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */ 1213 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1214 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1215 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1216 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ 1217 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */ 1218 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1219 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1220 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1221 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ 1222 #define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */ 1223 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1224 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1225 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1226 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ 1227 1228 /* Bit fields for CMU IEN */ 1229 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ 1230 #define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */ 1231 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */ 1232 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1233 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1234 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1235 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ 1236 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */ 1237 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1238 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1239 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1240 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ 1241 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */ 1242 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1243 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1244 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1245 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ 1246 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */ 1247 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1248 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1249 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1250 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ 1251 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */ 1252 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1253 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1254 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1255 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ 1256 #define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */ 1257 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1258 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1259 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1260 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ 1261 #define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */ 1262 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1263 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1264 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1265 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ 1266 1267 /* Bit fields for CMU HFCORECLKEN0 */ 1268 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */ 1269 #define _CMU_HFCORECLKEN0_MASK 0x00000033UL /**< Mask for CMU_HFCORECLKEN0 */ 1270 #define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */ 1271 #define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */ 1272 #define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */ 1273 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ 1274 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ 1275 #define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ 1276 #define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */ 1277 #define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */ 1278 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ 1279 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ 1280 #define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */ 1281 #define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */ 1282 #define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */ 1283 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ 1284 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ 1285 #define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */ 1286 #define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */ 1287 #define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */ 1288 #define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ 1289 #define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ 1290 1291 /* Bit fields for CMU HFPERCLKEN0 */ 1292 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ 1293 #define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */ 1294 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ 1295 #define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */ 1296 #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */ 1297 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1298 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1299 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ 1300 #define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */ 1301 #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */ 1302 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1303 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1304 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ 1305 #define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */ 1306 #define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */ 1307 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1308 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1309 #define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ 1310 #define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */ 1311 #define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */ 1312 #define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1313 #define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1314 #define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ 1315 #define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */ 1316 #define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */ 1317 #define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1318 #define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1319 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */ 1320 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */ 1321 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */ 1322 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1323 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1324 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */ 1325 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */ 1326 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */ 1327 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1328 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1329 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */ 1330 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */ 1331 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */ 1332 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1333 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1334 #define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */ 1335 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */ 1336 #define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */ 1337 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1338 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1339 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */ 1340 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */ 1341 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */ 1342 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1343 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1344 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */ 1345 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */ 1346 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */ 1347 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1348 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1349 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */ 1350 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */ 1351 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */ 1352 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1353 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1354 #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */ 1355 #define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */ 1356 #define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */ 1357 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1358 #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1359 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */ 1360 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */ 1361 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */ 1362 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1363 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1364 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */ 1365 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */ 1366 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */ 1367 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1368 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1369 #define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */ 1370 #define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */ 1371 #define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */ 1372 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1373 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1374 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */ 1375 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */ 1376 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */ 1377 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1378 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1379 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */ 1380 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */ 1381 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */ 1382 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1383 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1384 1385 /* Bit fields for CMU SYNCBUSY */ 1386 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ 1387 #define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */ 1388 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */ 1389 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ 1390 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ 1391 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1392 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1393 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */ 1394 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ 1395 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ 1396 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1397 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1398 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ 1399 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ 1400 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ 1401 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1402 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1403 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ 1404 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ 1405 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ 1406 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1407 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1408 1409 /* Bit fields for CMU FREEZE */ 1410 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ 1411 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ 1412 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ 1413 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ 1414 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ 1415 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ 1416 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ 1417 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ 1418 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ 1419 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ 1420 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ 1421 1422 /* Bit fields for CMU LFACLKEN0 */ 1423 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ 1424 #define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */ 1425 #define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */ 1426 #define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */ 1427 #define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */ 1428 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 1429 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 1430 #define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */ 1431 #define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */ 1432 #define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */ 1433 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 1434 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 1435 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */ 1436 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */ 1437 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */ 1438 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 1439 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 1440 #define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ 1441 #define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ 1442 #define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ 1443 #define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 1444 #define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 1445 1446 /* Bit fields for CMU LFBCLKEN0 */ 1447 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ 1448 #define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */ 1449 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ 1450 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ 1451 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ 1452 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 1453 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 1454 #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ 1455 #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ 1456 #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ 1457 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 1458 #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 1459 1460 /* Bit fields for CMU LFAPRESC0 */ 1461 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ 1462 #define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */ 1463 #define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */ 1464 #define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */ 1465 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 1466 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 1467 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 1468 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 1469 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 1470 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 1471 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 1472 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 1473 #define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ 1474 #define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */ 1475 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 1476 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 1477 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 1478 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 1479 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ 1480 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ 1481 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ 1482 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ 1483 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ 1484 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ 1485 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ 1486 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ 1487 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ 1488 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ 1489 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ 1490 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ 1491 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 1492 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 1493 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 1494 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 1495 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ 1496 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ 1497 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ 1498 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ 1499 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ 1500 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ 1501 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ 1502 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ 1503 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ 1504 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ 1505 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ 1506 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ 1507 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */ 1508 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */ 1509 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 1510 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 1511 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 1512 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 1513 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ 1514 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ 1515 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ 1516 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ 1517 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ 1518 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ 1519 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ 1520 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ 1521 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ 1522 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ 1523 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ 1524 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ 1525 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 1526 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 1527 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 1528 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 1529 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ 1530 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ 1531 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ 1532 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ 1533 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ 1534 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ 1535 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ 1536 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ 1537 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ 1538 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ 1539 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ 1540 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ 1541 #define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ 1542 #define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */ 1543 #define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */ 1544 #define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */ 1545 #define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */ 1546 #define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */ 1547 #define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ 1548 #define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ 1549 #define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ 1550 #define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ 1551 1552 /* Bit fields for CMU LFBPRESC0 */ 1553 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ 1554 #define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */ 1555 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ 1556 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ 1557 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ 1558 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ 1559 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ 1560 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ 1561 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ 1562 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ 1563 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ 1564 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ 1565 #define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ 1566 #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ 1567 #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ 1568 #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ 1569 #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ 1570 #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ 1571 #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ 1572 #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ 1573 #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ 1574 #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ 1575 1576 /* Bit fields for CMU PCNTCTRL */ 1577 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ 1578 #define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ 1579 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ 1580 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ 1581 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ 1582 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 1583 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 1584 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ 1585 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ 1586 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ 1587 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 1588 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ 1589 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ 1590 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 1591 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ 1592 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ 1593 #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ 1594 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ 1595 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ 1596 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 1597 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 1598 #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ 1599 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ 1600 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ 1601 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 1602 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ 1603 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ 1604 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 1605 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ 1606 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ 1607 #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ 1608 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ 1609 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ 1610 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 1611 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 1612 #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ 1613 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ 1614 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ 1615 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 1616 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ 1617 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ 1618 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 1619 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ 1620 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ 1621 1622 /* Bit fields for CMU LCDCTRL */ 1623 #define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */ 1624 #define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */ 1625 #define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */ 1626 #define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */ 1627 #define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */ 1628 #define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */ 1629 #define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */ 1630 #define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */ 1631 #define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */ 1632 #define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */ 1633 #define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */ 1634 #define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */ 1635 #define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */ 1636 #define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */ 1637 #define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */ 1638 #define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */ 1639 #define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */ 1640 #define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */ 1641 #define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */ 1642 #define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */ 1643 #define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */ 1644 #define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */ 1645 #define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */ 1646 #define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */ 1647 #define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */ 1648 #define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */ 1649 #define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */ 1650 #define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */ 1651 #define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */ 1652 #define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */ 1653 #define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */ 1654 1655 /* Bit fields for CMU ROUTE */ 1656 #define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */ 1657 #define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */ 1658 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ 1659 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ 1660 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ 1661 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */ 1662 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */ 1663 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ 1664 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ 1665 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ 1666 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */ 1667 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */ 1668 #define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */ 1669 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */ 1670 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */ 1671 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */ 1672 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */ 1673 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */ 1674 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */ 1675 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */ 1676 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */ 1677 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */ 1678 1679 /* Bit fields for CMU LOCK */ 1680 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ 1681 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ 1682 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ 1683 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ 1684 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ 1685 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ 1686 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ 1687 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ 1688 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ 1689 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ 1690 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ 1691 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ 1692 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ 1693 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ 1694 1695 /** @} End of group EFM32WG890F128_CMU */ 1696 1697 /***************************************************************************//** 1698 * @defgroup EFM32WG890F128_PRS_BitFields EFM32WG890F128_PRS Bit Fields 1699 * @{ 1700 ******************************************************************************/ 1701 1702 /* Bit fields for PRS SWPULSE */ 1703 #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ 1704 #define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */ 1705 #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ 1706 #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ 1707 #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ 1708 #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1709 #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1710 #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ 1711 #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ 1712 #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ 1713 #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1714 #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1715 #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ 1716 #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ 1717 #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ 1718 #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1719 #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1720 #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ 1721 #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ 1722 #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ 1723 #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1724 #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1725 #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ 1726 #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ 1727 #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ 1728 #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1729 #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1730 #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ 1731 #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ 1732 #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ 1733 #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1734 #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1735 #define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */ 1736 #define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ 1737 #define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ 1738 #define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1739 #define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1740 #define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */ 1741 #define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ 1742 #define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ 1743 #define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1744 #define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1745 #define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */ 1746 #define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ 1747 #define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ 1748 #define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1749 #define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1750 #define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */ 1751 #define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ 1752 #define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ 1753 #define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1754 #define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1755 #define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */ 1756 #define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ 1757 #define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ 1758 #define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1759 #define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1760 #define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */ 1761 #define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ 1762 #define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ 1763 #define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1764 #define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1765 1766 /* Bit fields for PRS SWLEVEL */ 1767 #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ 1768 #define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */ 1769 #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ 1770 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ 1771 #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ 1772 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1773 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1774 #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ 1775 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ 1776 #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ 1777 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1778 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1779 #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ 1780 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ 1781 #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ 1782 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1783 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1784 #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ 1785 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ 1786 #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ 1787 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1788 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1789 #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ 1790 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ 1791 #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ 1792 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1793 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1794 #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ 1795 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ 1796 #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ 1797 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1798 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1799 #define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */ 1800 #define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ 1801 #define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ 1802 #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1803 #define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1804 #define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */ 1805 #define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ 1806 #define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ 1807 #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1808 #define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1809 #define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */ 1810 #define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ 1811 #define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ 1812 #define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1813 #define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1814 #define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */ 1815 #define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ 1816 #define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ 1817 #define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1818 #define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1819 #define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */ 1820 #define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ 1821 #define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ 1822 #define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1823 #define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1824 #define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */ 1825 #define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ 1826 #define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ 1827 #define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1828 #define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1829 1830 /* Bit fields for PRS ROUTE */ 1831 #define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */ 1832 #define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */ 1833 #define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ 1834 #define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ 1835 #define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ 1836 #define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ 1837 #define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */ 1838 #define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ 1839 #define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ 1840 #define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ 1841 #define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ 1842 #define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */ 1843 #define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ 1844 #define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ 1845 #define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ 1846 #define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ 1847 #define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */ 1848 #define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ 1849 #define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ 1850 #define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ 1851 #define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ 1852 #define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */ 1853 #define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */ 1854 #define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */ 1855 #define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */ 1856 #define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ 1857 #define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */ 1858 #define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */ 1859 #define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */ 1860 #define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */ 1861 1862 /* Bit fields for PRS CH_CTRL */ 1863 #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ 1864 #define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */ 1865 #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ 1866 #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ 1867 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */ 1868 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ 1869 #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */ 1870 #define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */ 1871 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ 1872 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ 1873 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ 1874 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ 1875 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ 1876 #define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */ 1877 #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ 1878 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ 1879 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ 1880 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */ 1881 #define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */ 1882 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */ 1883 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */ 1884 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */ 1885 #define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */ 1886 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ 1887 #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ 1888 #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ 1889 #define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */ 1890 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ 1891 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ 1892 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ 1893 #define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */ 1894 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ 1895 #define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */ 1896 #define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */ 1897 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ 1898 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ 1899 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */ 1900 #define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */ 1901 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */ 1902 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */ 1903 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */ 1904 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ 1905 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ 1906 #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */ 1907 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ 1908 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ 1909 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ 1910 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */ 1911 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ 1912 #define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */ 1913 #define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */ 1914 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ 1915 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ 1916 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */ 1917 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */ 1918 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */ 1919 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ 1920 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ 1921 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ 1922 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */ 1923 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ 1924 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ 1925 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */ 1926 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */ 1927 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ 1928 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ 1929 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ 1930 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */ 1931 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ 1932 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ 1933 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */ 1934 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */ 1935 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ 1936 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ 1937 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */ 1938 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */ 1939 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ 1940 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ 1941 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */ 1942 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */ 1943 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ 1944 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ 1945 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */ 1946 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */ 1947 #define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */ 1948 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ 1949 #define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */ 1950 #define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */ 1951 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ 1952 #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ 1953 #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ 1954 #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ 1955 #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ 1956 #define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */ 1957 #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ 1958 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ 1959 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ 1960 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */ 1961 #define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */ 1962 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */ 1963 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */ 1964 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */ 1965 #define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */ 1966 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ 1967 #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ 1968 #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ 1969 #define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */ 1970 #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ 1971 #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ 1972 #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ 1973 #define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */ 1974 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ 1975 #define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */ 1976 #define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */ 1977 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ 1978 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ 1979 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */ 1980 #define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */ 1981 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */ 1982 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */ 1983 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */ 1984 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ 1985 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ 1986 #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */ 1987 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ 1988 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ 1989 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ 1990 #define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */ 1991 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ 1992 #define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */ 1993 #define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */ 1994 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ 1995 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ 1996 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */ 1997 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */ 1998 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */ 1999 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ 2000 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ 2001 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ 2002 #define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */ 2003 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ 2004 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ 2005 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */ 2006 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */ 2007 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ 2008 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ 2009 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ 2010 #define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */ 2011 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ 2012 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ 2013 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */ 2014 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */ 2015 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ 2016 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ 2017 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */ 2018 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */ 2019 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ 2020 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ 2021 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */ 2022 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */ 2023 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ 2024 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ 2025 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */ 2026 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */ 2027 #define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */ 2028 #define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */ 2029 #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ 2030 #define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */ 2031 #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */ 2032 #define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */ 2033 #define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */ 2034 #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */ 2035 #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */ 2036 #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */ 2037 #define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */ 2038 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */ 2039 #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */ 2040 #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */ 2041 #define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */ 2042 #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */ 2043 #define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */ 2044 #define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */ 2045 #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */ 2046 #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */ 2047 #define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */ 2048 #define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */ 2049 #define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */ 2050 #define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */ 2051 #define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */ 2052 #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */ 2053 #define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */ 2054 #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ 2055 #define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */ 2056 #define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */ 2057 #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */ 2058 #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */ 2059 #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */ 2060 #define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */ 2061 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ 2062 #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ 2063 #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ 2064 #define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */ 2065 #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */ 2066 #define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */ 2067 #define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */ 2068 #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */ 2069 #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */ 2070 #define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */ 2071 #define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */ 2072 #define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */ 2073 #define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */ 2074 #define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */ 2075 #define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */ 2076 #define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */ 2077 #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 2078 #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ 2079 #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ 2080 #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ 2081 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ 2082 #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 2083 #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */ 2084 #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ 2085 #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ 2086 #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ 2087 #define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */ 2088 #define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */ 2089 #define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */ 2090 #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 2091 #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 2092 2093 /** @} End of group EFM32WG890F128_PRS */ 2094 2095 /***************************************************************************//** 2096 * @defgroup EFM32WG890F128_UNLOCK EFM32WG890F128 Unlock Codes 2097 * @{ 2098 ******************************************************************************/ 2099 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ 2100 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ 2101 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ 2102 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ 2103 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ 2104 #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */ 2105 2106 /** @} End of group EFM32WG890F128_UNLOCK */ 2107 2108 /** @} End of group EFM32WG890F128_BitFields */ 2109 2110 /***************************************************************************//** 2111 * @defgroup EFM32WG890F128_Alternate_Function EFM32WG890F128 Alternate Function 2112 * @{ 2113 ******************************************************************************/ 2114 2115 #include "efm32wg_af_ports.h" 2116 #include "efm32wg_af_pins.h" 2117 2118 /** @} End of group EFM32WG890F128_Alternate_Function */ 2119 2120 /***************************************************************************//** 2121 * @brief Set the value of a bit field within a register. 2122 * 2123 * @param REG 2124 * The register to update 2125 * @param MASK 2126 * The mask for the bit field to update 2127 * @param VALUE 2128 * The value to write to the bit field 2129 * @param OFFSET 2130 * The number of bits that the field is offset within the register. 2131 * 0 (zero) means LSB. 2132 ******************************************************************************/ 2133 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ 2134 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); 2135 2136 /** @} End of group EFM32WG890F128 */ 2137 2138 /** @} End of group Parts */ 2139 2140 #ifdef __cplusplus 2141 } 2142 #endif 2143 #endif /* EFM32WG890F128_H */ 2144
