1 /***************************************************************************//** 2 * @file 3 * @brief EFM32PG12B_RTCC register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32PG12B_RTCC RTCC 43 * @{ 44 * @brief EFM32PG12B_RTCC Register Declaration 45 ******************************************************************************/ 46 /** RTCC Register Declaration */ 47 typedef struct { 48 __IOM uint32_t CTRL; /**< Control Register */ 49 __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ 50 __IOM uint32_t CNT; /**< Counter Value Register */ 51 __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */ 52 __IOM uint32_t TIME; /**< Time of Day Register */ 53 __IOM uint32_t DATE; /**< Date Register */ 54 __IM uint32_t IF; /**< RTCC Interrupt Flags */ 55 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 56 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 57 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 58 __IM uint32_t STATUS; /**< Status Register */ 59 __IOM uint32_t CMD; /**< Command Register */ 60 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 61 __IOM uint32_t POWERDOWN; /**< Retention RAM Power-down Register */ 62 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 63 __IOM uint32_t EM4WUEN; /**< Wake Up Enable */ 64 65 RTCC_CC_TypeDef CC[3U]; /**< Capture/Compare Channel */ 66 67 uint32_t RESERVED0[37U]; /**< Reserved registers */ 68 RTCC_RET_TypeDef RET[32U]; /**< RetentionReg */ 69 } RTCC_TypeDef; /** @} */ 70 71 /***************************************************************************//** 72 * @addtogroup EFM32PG12B_RTCC 73 * @{ 74 * @defgroup EFM32PG12B_RTCC_BitFields RTCC Bit Fields 75 * @{ 76 ******************************************************************************/ 77 78 /* Bit fields for RTCC CTRL */ 79 #define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */ 80 #define _RTCC_CTRL_MASK 0x00039F35UL /**< Mask for RTCC_CTRL */ 81 #define RTCC_CTRL_ENABLE (0x1UL << 0) /**< RTCC Enable */ 82 #define _RTCC_CTRL_ENABLE_SHIFT 0 /**< Shift value for RTCC_ENABLE */ 83 #define _RTCC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for RTCC_ENABLE */ 84 #define _RTCC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ 85 #define RTCC_CTRL_ENABLE_DEFAULT (_RTCC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CTRL */ 86 #define RTCC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */ 87 #define _RTCC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for RTCC_DEBUGRUN */ 88 #define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */ 89 #define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ 90 #define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */ 91 #define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 Top Value Enable */ 92 #define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */ 93 #define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */ 94 #define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ 95 #define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */ 96 #define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 Top Value Enable */ 97 #define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */ 98 #define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */ 99 #define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ 100 #define RTCC_CTRL_CCV1TOP_DEFAULT (_RTCC_CTRL_CCV1TOP_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CTRL */ 101 #define _RTCC_CTRL_CNTPRESC_SHIFT 8 /**< Shift value for RTCC_CNTPRESC */ 102 #define _RTCC_CTRL_CNTPRESC_MASK 0xF00UL /**< Bit mask for RTCC_CNTPRESC */ 103 #define _RTCC_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ 104 #define _RTCC_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CTRL */ 105 #define _RTCC_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CTRL */ 106 #define _RTCC_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CTRL */ 107 #define _RTCC_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CTRL */ 108 #define _RTCC_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CTRL */ 109 #define _RTCC_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CTRL */ 110 #define _RTCC_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CTRL */ 111 #define _RTCC_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CTRL */ 112 #define _RTCC_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CTRL */ 113 #define _RTCC_CTRL_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CTRL */ 114 #define _RTCC_CTRL_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CTRL */ 115 #define _RTCC_CTRL_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CTRL */ 116 #define _RTCC_CTRL_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CTRL */ 117 #define _RTCC_CTRL_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CTRL */ 118 #define _RTCC_CTRL_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CTRL */ 119 #define _RTCC_CTRL_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CTRL */ 120 #define RTCC_CTRL_CNTPRESC_DEFAULT (_RTCC_CTRL_CNTPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CTRL */ 121 #define RTCC_CTRL_CNTPRESC_DIV1 (_RTCC_CTRL_CNTPRESC_DIV1 << 8) /**< Shifted mode DIV1 for RTCC_CTRL */ 122 #define RTCC_CTRL_CNTPRESC_DIV2 (_RTCC_CTRL_CNTPRESC_DIV2 << 8) /**< Shifted mode DIV2 for RTCC_CTRL */ 123 #define RTCC_CTRL_CNTPRESC_DIV4 (_RTCC_CTRL_CNTPRESC_DIV4 << 8) /**< Shifted mode DIV4 for RTCC_CTRL */ 124 #define RTCC_CTRL_CNTPRESC_DIV8 (_RTCC_CTRL_CNTPRESC_DIV8 << 8) /**< Shifted mode DIV8 for RTCC_CTRL */ 125 #define RTCC_CTRL_CNTPRESC_DIV16 (_RTCC_CTRL_CNTPRESC_DIV16 << 8) /**< Shifted mode DIV16 for RTCC_CTRL */ 126 #define RTCC_CTRL_CNTPRESC_DIV32 (_RTCC_CTRL_CNTPRESC_DIV32 << 8) /**< Shifted mode DIV32 for RTCC_CTRL */ 127 #define RTCC_CTRL_CNTPRESC_DIV64 (_RTCC_CTRL_CNTPRESC_DIV64 << 8) /**< Shifted mode DIV64 for RTCC_CTRL */ 128 #define RTCC_CTRL_CNTPRESC_DIV128 (_RTCC_CTRL_CNTPRESC_DIV128 << 8) /**< Shifted mode DIV128 for RTCC_CTRL */ 129 #define RTCC_CTRL_CNTPRESC_DIV256 (_RTCC_CTRL_CNTPRESC_DIV256 << 8) /**< Shifted mode DIV256 for RTCC_CTRL */ 130 #define RTCC_CTRL_CNTPRESC_DIV512 (_RTCC_CTRL_CNTPRESC_DIV512 << 8) /**< Shifted mode DIV512 for RTCC_CTRL */ 131 #define RTCC_CTRL_CNTPRESC_DIV1024 (_RTCC_CTRL_CNTPRESC_DIV1024 << 8) /**< Shifted mode DIV1024 for RTCC_CTRL */ 132 #define RTCC_CTRL_CNTPRESC_DIV2048 (_RTCC_CTRL_CNTPRESC_DIV2048 << 8) /**< Shifted mode DIV2048 for RTCC_CTRL */ 133 #define RTCC_CTRL_CNTPRESC_DIV4096 (_RTCC_CTRL_CNTPRESC_DIV4096 << 8) /**< Shifted mode DIV4096 for RTCC_CTRL */ 134 #define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */ 135 #define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */ 136 #define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */ 137 #define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter Prescaler Mode */ 138 #define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */ 139 #define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */ 140 #define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ 141 #define _RTCC_CTRL_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CTRL */ 142 #define _RTCC_CTRL_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CTRL */ 143 #define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */ 144 #define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */ 145 #define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */ 146 #define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator Failure Detection Enable */ 147 #define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */ 148 #define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */ 149 #define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ 150 #define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */ 151 #define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main Counter Mode */ 152 #define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */ 153 #define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */ 154 #define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ 155 #define _RTCC_CTRL_CNTMODE_NORMAL 0x00000000UL /**< Mode NORMAL for RTCC_CTRL */ 156 #define _RTCC_CTRL_CNTMODE_CALENDAR 0x00000001UL /**< Mode CALENDAR for RTCC_CTRL */ 157 #define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */ 158 #define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */ 159 #define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */ 160 #define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap Year Correction Disabled */ 161 #define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */ 162 #define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */ 163 #define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ 164 #define RTCC_CTRL_LYEARCORRDIS_DEFAULT (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CTRL */ 165 166 /* Bit fields for RTCC PRECNT */ 167 #define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */ 168 #define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */ 169 #define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ 170 #define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ 171 #define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */ 172 #define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */ 173 174 /* Bit fields for RTCC CNT */ 175 #define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */ 176 #define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */ 177 #define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */ 178 #define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */ 179 #define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */ 180 #define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */ 181 182 /* Bit fields for RTCC COMBCNT */ 183 #define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */ 184 #define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */ 185 #define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ 186 #define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ 187 #define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ 188 #define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ 189 #define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */ 190 #define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */ 191 #define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ 192 #define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ 193 194 /* Bit fields for RTCC TIME */ 195 #define _RTCC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_TIME */ 196 #define _RTCC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_TIME */ 197 #define _RTCC_TIME_SECU_SHIFT 0 /**< Shift value for RTCC_SECU */ 198 #define _RTCC_TIME_SECU_MASK 0xFUL /**< Bit mask for RTCC_SECU */ 199 #define _RTCC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ 200 #define RTCC_TIME_SECU_DEFAULT (_RTCC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_TIME */ 201 #define _RTCC_TIME_SECT_SHIFT 4 /**< Shift value for RTCC_SECT */ 202 #define _RTCC_TIME_SECT_MASK 0x70UL /**< Bit mask for RTCC_SECT */ 203 #define _RTCC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ 204 #define RTCC_TIME_SECT_DEFAULT (_RTCC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_TIME */ 205 #define _RTCC_TIME_MINU_SHIFT 8 /**< Shift value for RTCC_MINU */ 206 #define _RTCC_TIME_MINU_MASK 0xF00UL /**< Bit mask for RTCC_MINU */ 207 #define _RTCC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ 208 #define RTCC_TIME_MINU_DEFAULT (_RTCC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_TIME */ 209 #define _RTCC_TIME_MINT_SHIFT 12 /**< Shift value for RTCC_MINT */ 210 #define _RTCC_TIME_MINT_MASK 0x7000UL /**< Bit mask for RTCC_MINT */ 211 #define _RTCC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ 212 #define RTCC_TIME_MINT_DEFAULT (_RTCC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_TIME */ 213 #define _RTCC_TIME_HOURU_SHIFT 16 /**< Shift value for RTCC_HOURU */ 214 #define _RTCC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for RTCC_HOURU */ 215 #define _RTCC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ 216 #define RTCC_TIME_HOURU_DEFAULT (_RTCC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_TIME */ 217 #define _RTCC_TIME_HOURT_SHIFT 20 /**< Shift value for RTCC_HOURT */ 218 #define _RTCC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for RTCC_HOURT */ 219 #define _RTCC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ 220 #define RTCC_TIME_HOURT_DEFAULT (_RTCC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_TIME */ 221 222 /* Bit fields for RTCC DATE */ 223 #define _RTCC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_DATE */ 224 #define _RTCC_DATE_MASK 0x07FF1F3FUL /**< Mask for RTCC_DATE */ 225 #define _RTCC_DATE_DAYOMU_SHIFT 0 /**< Shift value for RTCC_DAYOMU */ 226 #define _RTCC_DATE_DAYOMU_MASK 0xFUL /**< Bit mask for RTCC_DAYOMU */ 227 #define _RTCC_DATE_DAYOMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ 228 #define RTCC_DATE_DAYOMU_DEFAULT (_RTCC_DATE_DAYOMU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_DATE */ 229 #define _RTCC_DATE_DAYOMT_SHIFT 4 /**< Shift value for RTCC_DAYOMT */ 230 #define _RTCC_DATE_DAYOMT_MASK 0x30UL /**< Bit mask for RTCC_DAYOMT */ 231 #define _RTCC_DATE_DAYOMT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ 232 #define RTCC_DATE_DAYOMT_DEFAULT (_RTCC_DATE_DAYOMT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_DATE */ 233 #define _RTCC_DATE_MONTHU_SHIFT 8 /**< Shift value for RTCC_MONTHU */ 234 #define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */ 235 #define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ 236 #define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */ 237 #define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, Tens */ 238 #define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */ 239 #define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */ 240 #define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ 241 #define RTCC_DATE_MONTHT_DEFAULT (_RTCC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_DATE */ 242 #define _RTCC_DATE_YEARU_SHIFT 16 /**< Shift value for RTCC_YEARU */ 243 #define _RTCC_DATE_YEARU_MASK 0xF0000UL /**< Bit mask for RTCC_YEARU */ 244 #define _RTCC_DATE_YEARU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ 245 #define RTCC_DATE_YEARU_DEFAULT (_RTCC_DATE_YEARU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_DATE */ 246 #define _RTCC_DATE_YEART_SHIFT 20 /**< Shift value for RTCC_YEART */ 247 #define _RTCC_DATE_YEART_MASK 0xF00000UL /**< Bit mask for RTCC_YEART */ 248 #define _RTCC_DATE_YEART_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ 249 #define RTCC_DATE_YEART_DEFAULT (_RTCC_DATE_YEART_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_DATE */ 250 #define _RTCC_DATE_DAYOW_SHIFT 24 /**< Shift value for RTCC_DAYOW */ 251 #define _RTCC_DATE_DAYOW_MASK 0x7000000UL /**< Bit mask for RTCC_DAYOW */ 252 #define _RTCC_DATE_DAYOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ 253 #define RTCC_DATE_DAYOW_DEFAULT (_RTCC_DATE_DAYOW_DEFAULT << 24) /**< Shifted mode DEFAULT for RTCC_DATE */ 254 255 /* Bit fields for RTCC IF */ 256 #define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */ 257 #define _RTCC_IF_MASK 0x000007FFUL /**< Mask for RTCC_IF */ 258 #define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ 259 #define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */ 260 #define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ 261 #define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 262 #define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */ 263 #define RTCC_IF_CC0 (0x1UL << 1) /**< Channel 0 Interrupt Flag */ 264 #define _RTCC_IF_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ 265 #define _RTCC_IF_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ 266 #define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 267 #define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */ 268 #define RTCC_IF_CC1 (0x1UL << 2) /**< Channel 1 Interrupt Flag */ 269 #define _RTCC_IF_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ 270 #define _RTCC_IF_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ 271 #define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 272 #define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IF */ 273 #define RTCC_IF_CC2 (0x1UL << 3) /**< Channel 2 Interrupt Flag */ 274 #define _RTCC_IF_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ 275 #define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ 276 #define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 277 #define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */ 278 #define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator Failure Interrupt Flag */ 279 #define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ 280 #define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ 281 #define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 282 #define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */ 283 #define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main Counter Tick */ 284 #define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ 285 #define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ 286 #define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 287 #define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */ 288 #define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute Tick */ 289 #define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ 290 #define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ 291 #define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 292 #define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */ 293 #define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour Tick */ 294 #define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ 295 #define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ 296 #define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 297 #define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */ 298 #define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day Tick */ 299 #define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ 300 #define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ 301 #define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 302 #define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */ 303 #define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of Week Overflow */ 304 #define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ 305 #define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ 306 #define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 307 #define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */ 308 #define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month Tick */ 309 #define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ 310 #define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ 311 #define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ 312 #define RTCC_IF_MONTHTICK_DEFAULT (_RTCC_IF_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IF */ 313 314 /* Bit fields for RTCC IFS */ 315 #define _RTCC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFS */ 316 #define _RTCC_IFS_MASK 0x000007FFUL /**< Mask for RTCC_IFS */ 317 #define RTCC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ 318 #define _RTCC_IFS_OF_SHIFT 0 /**< Shift value for RTCC_OF */ 319 #define _RTCC_IFS_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ 320 #define _RTCC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ 321 #define RTCC_IFS_OF_DEFAULT (_RTCC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFS */ 322 #define RTCC_IFS_CC0 (0x1UL << 1) /**< Set CC0 Interrupt Flag */ 323 #define _RTCC_IFS_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ 324 #define _RTCC_IFS_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ 325 #define _RTCC_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ 326 #define RTCC_IFS_CC0_DEFAULT (_RTCC_IFS_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFS */ 327 #define RTCC_IFS_CC1 (0x1UL << 2) /**< Set CC1 Interrupt Flag */ 328 #define _RTCC_IFS_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ 329 #define _RTCC_IFS_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ 330 #define _RTCC_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ 331 #define RTCC_IFS_CC1_DEFAULT (_RTCC_IFS_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFS */ 332 #define RTCC_IFS_CC2 (0x1UL << 3) /**< Set CC2 Interrupt Flag */ 333 #define _RTCC_IFS_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ 334 #define _RTCC_IFS_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ 335 #define _RTCC_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ 336 #define RTCC_IFS_CC2_DEFAULT (_RTCC_IFS_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFS */ 337 #define RTCC_IFS_OSCFAIL (0x1UL << 4) /**< Set OSCFAIL Interrupt Flag */ 338 #define _RTCC_IFS_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ 339 #define _RTCC_IFS_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ 340 #define _RTCC_IFS_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ 341 #define RTCC_IFS_OSCFAIL_DEFAULT (_RTCC_IFS_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFS */ 342 #define RTCC_IFS_CNTTICK (0x1UL << 5) /**< Set CNTTICK Interrupt Flag */ 343 #define _RTCC_IFS_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ 344 #define _RTCC_IFS_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ 345 #define _RTCC_IFS_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ 346 #define RTCC_IFS_CNTTICK_DEFAULT (_RTCC_IFS_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFS */ 347 #define RTCC_IFS_MINTICK (0x1UL << 6) /**< Set MINTICK Interrupt Flag */ 348 #define _RTCC_IFS_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ 349 #define _RTCC_IFS_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ 350 #define _RTCC_IFS_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ 351 #define RTCC_IFS_MINTICK_DEFAULT (_RTCC_IFS_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFS */ 352 #define RTCC_IFS_HOURTICK (0x1UL << 7) /**< Set HOURTICK Interrupt Flag */ 353 #define _RTCC_IFS_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ 354 #define _RTCC_IFS_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ 355 #define _RTCC_IFS_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ 356 #define RTCC_IFS_HOURTICK_DEFAULT (_RTCC_IFS_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFS */ 357 #define RTCC_IFS_DAYTICK (0x1UL << 8) /**< Set DAYTICK Interrupt Flag */ 358 #define _RTCC_IFS_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ 359 #define _RTCC_IFS_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ 360 #define _RTCC_IFS_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ 361 #define RTCC_IFS_DAYTICK_DEFAULT (_RTCC_IFS_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFS */ 362 #define RTCC_IFS_DAYOWOF (0x1UL << 9) /**< Set DAYOWOF Interrupt Flag */ 363 #define _RTCC_IFS_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ 364 #define _RTCC_IFS_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ 365 #define _RTCC_IFS_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ 366 #define RTCC_IFS_DAYOWOF_DEFAULT (_RTCC_IFS_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFS */ 367 #define RTCC_IFS_MONTHTICK (0x1UL << 10) /**< Set MONTHTICK Interrupt Flag */ 368 #define _RTCC_IFS_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ 369 #define _RTCC_IFS_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ 370 #define _RTCC_IFS_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ 371 #define RTCC_IFS_MONTHTICK_DEFAULT (_RTCC_IFS_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFS */ 372 373 /* Bit fields for RTCC IFC */ 374 #define _RTCC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFC */ 375 #define _RTCC_IFC_MASK 0x000007FFUL /**< Mask for RTCC_IFC */ 376 #define RTCC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ 377 #define _RTCC_IFC_OF_SHIFT 0 /**< Shift value for RTCC_OF */ 378 #define _RTCC_IFC_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ 379 #define _RTCC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ 380 #define RTCC_IFC_OF_DEFAULT (_RTCC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFC */ 381 #define RTCC_IFC_CC0 (0x1UL << 1) /**< Clear CC0 Interrupt Flag */ 382 #define _RTCC_IFC_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ 383 #define _RTCC_IFC_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ 384 #define _RTCC_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ 385 #define RTCC_IFC_CC0_DEFAULT (_RTCC_IFC_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFC */ 386 #define RTCC_IFC_CC1 (0x1UL << 2) /**< Clear CC1 Interrupt Flag */ 387 #define _RTCC_IFC_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ 388 #define _RTCC_IFC_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ 389 #define _RTCC_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ 390 #define RTCC_IFC_CC1_DEFAULT (_RTCC_IFC_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFC */ 391 #define RTCC_IFC_CC2 (0x1UL << 3) /**< Clear CC2 Interrupt Flag */ 392 #define _RTCC_IFC_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ 393 #define _RTCC_IFC_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ 394 #define _RTCC_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ 395 #define RTCC_IFC_CC2_DEFAULT (_RTCC_IFC_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFC */ 396 #define RTCC_IFC_OSCFAIL (0x1UL << 4) /**< Clear OSCFAIL Interrupt Flag */ 397 #define _RTCC_IFC_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ 398 #define _RTCC_IFC_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ 399 #define _RTCC_IFC_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ 400 #define RTCC_IFC_OSCFAIL_DEFAULT (_RTCC_IFC_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFC */ 401 #define RTCC_IFC_CNTTICK (0x1UL << 5) /**< Clear CNTTICK Interrupt Flag */ 402 #define _RTCC_IFC_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ 403 #define _RTCC_IFC_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ 404 #define _RTCC_IFC_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ 405 #define RTCC_IFC_CNTTICK_DEFAULT (_RTCC_IFC_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFC */ 406 #define RTCC_IFC_MINTICK (0x1UL << 6) /**< Clear MINTICK Interrupt Flag */ 407 #define _RTCC_IFC_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ 408 #define _RTCC_IFC_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ 409 #define _RTCC_IFC_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ 410 #define RTCC_IFC_MINTICK_DEFAULT (_RTCC_IFC_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFC */ 411 #define RTCC_IFC_HOURTICK (0x1UL << 7) /**< Clear HOURTICK Interrupt Flag */ 412 #define _RTCC_IFC_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ 413 #define _RTCC_IFC_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ 414 #define _RTCC_IFC_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ 415 #define RTCC_IFC_HOURTICK_DEFAULT (_RTCC_IFC_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFC */ 416 #define RTCC_IFC_DAYTICK (0x1UL << 8) /**< Clear DAYTICK Interrupt Flag */ 417 #define _RTCC_IFC_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ 418 #define _RTCC_IFC_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ 419 #define _RTCC_IFC_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ 420 #define RTCC_IFC_DAYTICK_DEFAULT (_RTCC_IFC_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFC */ 421 #define RTCC_IFC_DAYOWOF (0x1UL << 9) /**< Clear DAYOWOF Interrupt Flag */ 422 #define _RTCC_IFC_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ 423 #define _RTCC_IFC_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ 424 #define _RTCC_IFC_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ 425 #define RTCC_IFC_DAYOWOF_DEFAULT (_RTCC_IFC_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFC */ 426 #define RTCC_IFC_MONTHTICK (0x1UL << 10) /**< Clear MONTHTICK Interrupt Flag */ 427 #define _RTCC_IFC_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ 428 #define _RTCC_IFC_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ 429 #define _RTCC_IFC_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ 430 #define RTCC_IFC_MONTHTICK_DEFAULT (_RTCC_IFC_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFC */ 431 432 /* Bit fields for RTCC IEN */ 433 #define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */ 434 #define _RTCC_IEN_MASK 0x000007FFUL /**< Mask for RTCC_IEN */ 435 #define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ 436 #define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */ 437 #define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ 438 #define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 439 #define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */ 440 #define RTCC_IEN_CC0 (0x1UL << 1) /**< CC0 Interrupt Enable */ 441 #define _RTCC_IEN_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ 442 #define _RTCC_IEN_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ 443 #define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 444 #define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */ 445 #define RTCC_IEN_CC1 (0x1UL << 2) /**< CC1 Interrupt Enable */ 446 #define _RTCC_IEN_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ 447 #define _RTCC_IEN_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ 448 #define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 449 #define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IEN */ 450 #define RTCC_IEN_CC2 (0x1UL << 3) /**< CC2 Interrupt Enable */ 451 #define _RTCC_IEN_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ 452 #define _RTCC_IEN_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ 453 #define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 454 #define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IEN */ 455 #define RTCC_IEN_OSCFAIL (0x1UL << 4) /**< OSCFAIL Interrupt Enable */ 456 #define _RTCC_IEN_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ 457 #define _RTCC_IEN_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ 458 #define _RTCC_IEN_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 459 #define RTCC_IEN_OSCFAIL_DEFAULT (_RTCC_IEN_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */ 460 #define RTCC_IEN_CNTTICK (0x1UL << 5) /**< CNTTICK Interrupt Enable */ 461 #define _RTCC_IEN_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ 462 #define _RTCC_IEN_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ 463 #define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 464 #define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IEN */ 465 #define RTCC_IEN_MINTICK (0x1UL << 6) /**< MINTICK Interrupt Enable */ 466 #define _RTCC_IEN_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ 467 #define _RTCC_IEN_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ 468 #define _RTCC_IEN_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 469 #define RTCC_IEN_MINTICK_DEFAULT (_RTCC_IEN_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */ 470 #define RTCC_IEN_HOURTICK (0x1UL << 7) /**< HOURTICK Interrupt Enable */ 471 #define _RTCC_IEN_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ 472 #define _RTCC_IEN_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ 473 #define _RTCC_IEN_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 474 #define RTCC_IEN_HOURTICK_DEFAULT (_RTCC_IEN_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IEN */ 475 #define RTCC_IEN_DAYTICK (0x1UL << 8) /**< DAYTICK Interrupt Enable */ 476 #define _RTCC_IEN_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ 477 #define _RTCC_IEN_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ 478 #define _RTCC_IEN_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 479 #define RTCC_IEN_DAYTICK_DEFAULT (_RTCC_IEN_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */ 480 #define RTCC_IEN_DAYOWOF (0x1UL << 9) /**< DAYOWOF Interrupt Enable */ 481 #define _RTCC_IEN_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ 482 #define _RTCC_IEN_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ 483 #define _RTCC_IEN_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 484 #define RTCC_IEN_DAYOWOF_DEFAULT (_RTCC_IEN_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IEN */ 485 #define RTCC_IEN_MONTHTICK (0x1UL << 10) /**< MONTHTICK Interrupt Enable */ 486 #define _RTCC_IEN_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ 487 #define _RTCC_IEN_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ 488 #define _RTCC_IEN_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ 489 #define RTCC_IEN_MONTHTICK_DEFAULT (_RTCC_IEN_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IEN */ 490 491 /* Bit fields for RTCC STATUS */ 492 #define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */ 493 #define _RTCC_STATUS_MASK 0x00000000UL /**< Mask for RTCC_STATUS */ 494 495 /* Bit fields for RTCC CMD */ 496 #define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */ 497 #define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */ 498 #define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS Register */ 499 #define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */ 500 #define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */ 501 #define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ 502 #define RTCC_CMD_CLRSTATUS_DEFAULT (_RTCC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */ 503 504 /* Bit fields for RTCC SYNCBUSY */ 505 #define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */ 506 #define _RTCC_SYNCBUSY_MASK 0x00000020UL /**< Mask for RTCC_SYNCBUSY */ 507 #define RTCC_SYNCBUSY_CMD (0x1UL << 5) /**< CMD Register Busy */ 508 #define _RTCC_SYNCBUSY_CMD_SHIFT 5 /**< Shift value for RTCC_CMD */ 509 #define _RTCC_SYNCBUSY_CMD_MASK 0x20UL /**< Bit mask for RTCC_CMD */ 510 #define _RTCC_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ 511 #define RTCC_SYNCBUSY_CMD_DEFAULT (_RTCC_SYNCBUSY_CMD_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ 512 513 /* Bit fields for RTCC POWERDOWN */ 514 #define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */ 515 #define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */ 516 #define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM Power-down */ 517 #define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */ 518 #define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */ 519 #define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */ 520 #define RTCC_POWERDOWN_RAM_DEFAULT (_RTCC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_POWERDOWN */ 521 522 /* Bit fields for RTCC LOCK */ 523 #define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */ 524 #define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */ 525 #define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */ 526 #define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */ 527 #define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */ 528 #define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */ 529 #define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */ 530 #define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */ 531 #define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */ 532 #define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */ 533 #define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */ 534 #define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */ 535 #define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */ 536 #define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */ 537 538 /* Bit fields for RTCC EM4WUEN */ 539 #define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */ 540 #define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */ 541 #define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up Enable */ 542 #define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */ 543 #define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */ 544 #define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */ 545 #define RTCC_EM4WUEN_EM4WU_DEFAULT (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EM4WUEN */ 546 547 /* Bit fields for RTCC CC_CTRL */ 548 #define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */ 549 #define _RTCC_CC_CTRL_MASK 0x0003FBFFUL /**< Mask for RTCC_CC_CTRL */ 550 #define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for CC_MODE */ 551 #define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for CC_MODE */ 552 #define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ 553 #define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */ 554 #define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */ 555 #define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */ 556 #define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ 557 #define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */ 558 #define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */ 559 #define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */ 560 #define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for CC_CMOA */ 561 #define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for CC_CMOA */ 562 #define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ 563 #define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */ 564 #define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */ 565 #define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */ 566 #define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */ 567 #define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ 568 #define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */ 569 #define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */ 570 #define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */ 571 #define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */ 572 #define _RTCC_CC_CTRL_ICEDGE_SHIFT 4 /**< Shift value for CC_ICEDGE */ 573 #define _RTCC_CC_CTRL_ICEDGE_MASK 0x30UL /**< Bit mask for CC_ICEDGE */ 574 #define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ 575 #define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */ 576 #define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */ 577 #define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */ 578 #define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */ 579 #define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ 580 #define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 4) /**< Shifted mode RISING for RTCC_CC_CTRL */ 581 #define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 4) /**< Shifted mode FALLING for RTCC_CC_CTRL */ 582 #define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 4) /**< Shifted mode BOTH for RTCC_CC_CTRL */ 583 #define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 4) /**< Shifted mode NONE for RTCC_CC_CTRL */ 584 #define _RTCC_CC_CTRL_PRSSEL_SHIFT 6 /**< Shift value for CC_PRSSEL */ 585 #define _RTCC_CC_CTRL_PRSSEL_MASK 0x3C0UL /**< Bit mask for CC_PRSSEL */ 586 #define _RTCC_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ 587 #define _RTCC_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for RTCC_CC_CTRL */ 588 #define _RTCC_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for RTCC_CC_CTRL */ 589 #define _RTCC_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for RTCC_CC_CTRL */ 590 #define _RTCC_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for RTCC_CC_CTRL */ 591 #define _RTCC_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for RTCC_CC_CTRL */ 592 #define _RTCC_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for RTCC_CC_CTRL */ 593 #define _RTCC_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for RTCC_CC_CTRL */ 594 #define _RTCC_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for RTCC_CC_CTRL */ 595 #define _RTCC_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for RTCC_CC_CTRL */ 596 #define _RTCC_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for RTCC_CC_CTRL */ 597 #define _RTCC_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for RTCC_CC_CTRL */ 598 #define _RTCC_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for RTCC_CC_CTRL */ 599 #define RTCC_CC_CTRL_PRSSEL_DEFAULT (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ 600 #define RTCC_CC_CTRL_PRSSEL_PRSCH0 (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for RTCC_CC_CTRL */ 601 #define RTCC_CC_CTRL_PRSSEL_PRSCH1 (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for RTCC_CC_CTRL */ 602 #define RTCC_CC_CTRL_PRSSEL_PRSCH2 (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for RTCC_CC_CTRL */ 603 #define RTCC_CC_CTRL_PRSSEL_PRSCH3 (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for RTCC_CC_CTRL */ 604 #define RTCC_CC_CTRL_PRSSEL_PRSCH4 (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for RTCC_CC_CTRL */ 605 #define RTCC_CC_CTRL_PRSSEL_PRSCH5 (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for RTCC_CC_CTRL */ 606 #define RTCC_CC_CTRL_PRSSEL_PRSCH6 (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for RTCC_CC_CTRL */ 607 #define RTCC_CC_CTRL_PRSSEL_PRSCH7 (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for RTCC_CC_CTRL */ 608 #define RTCC_CC_CTRL_PRSSEL_PRSCH8 (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for RTCC_CC_CTRL */ 609 #define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */ 610 #define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */ 611 #define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */ 612 #define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture Compare Channel Comparison Base */ 613 #define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */ 614 #define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */ 615 #define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ 616 #define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */ 617 #define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */ 618 #define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ 619 #define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 11) /**< Shifted mode CNT for RTCC_CC_CTRL */ 620 #define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11) /**< Shifted mode PRECNT for RTCC_CC_CTRL */ 621 #define _RTCC_CC_CTRL_COMPMASK_SHIFT 12 /**< Shift value for CC_COMPMASK */ 622 #define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */ 623 #define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ 624 #define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ 625 #define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare Selection */ 626 #define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */ 627 #define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */ 628 #define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ 629 #define _RTCC_CC_CTRL_DAYCC_MONTH 0x00000000UL /**< Mode MONTH for RTCC_CC_CTRL */ 630 #define _RTCC_CC_CTRL_DAYCC_WEEK 0x00000001UL /**< Mode WEEK for RTCC_CC_CTRL */ 631 #define RTCC_CC_CTRL_DAYCC_DEFAULT (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ 632 #define RTCC_CC_CTRL_DAYCC_MONTH (_RTCC_CC_CTRL_DAYCC_MONTH << 17) /**< Shifted mode MONTH for RTCC_CC_CTRL */ 633 #define RTCC_CC_CTRL_DAYCC_WEEK (_RTCC_CC_CTRL_DAYCC_WEEK << 17) /**< Shifted mode WEEK for RTCC_CC_CTRL */ 634 635 /* Bit fields for RTCC CC_CCV */ 636 #define _RTCC_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CCV */ 637 #define _RTCC_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_CCV */ 638 #define _RTCC_CC_CCV_CCV_SHIFT 0 /**< Shift value for CC_CCV */ 639 #define _RTCC_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for CC_CCV */ 640 #define _RTCC_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CCV */ 641 #define RTCC_CC_CCV_CCV_DEFAULT (_RTCC_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CCV */ 642 643 /* Bit fields for RTCC CC_TIME */ 644 #define _RTCC_CC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_TIME */ 645 #define _RTCC_CC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_CC_TIME */ 646 #define _RTCC_CC_TIME_SECU_SHIFT 0 /**< Shift value for CC_SECU */ 647 #define _RTCC_CC_TIME_SECU_MASK 0xFUL /**< Bit mask for CC_SECU */ 648 #define _RTCC_CC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ 649 #define RTCC_CC_TIME_SECU_DEFAULT (_RTCC_CC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ 650 #define _RTCC_CC_TIME_SECT_SHIFT 4 /**< Shift value for CC_SECT */ 651 #define _RTCC_CC_TIME_SECT_MASK 0x70UL /**< Bit mask for CC_SECT */ 652 #define _RTCC_CC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ 653 #define RTCC_CC_TIME_SECT_DEFAULT (_RTCC_CC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ 654 #define _RTCC_CC_TIME_MINU_SHIFT 8 /**< Shift value for CC_MINU */ 655 #define _RTCC_CC_TIME_MINU_MASK 0xF00UL /**< Bit mask for CC_MINU */ 656 #define _RTCC_CC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ 657 #define RTCC_CC_TIME_MINU_DEFAULT (_RTCC_CC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ 658 #define _RTCC_CC_TIME_MINT_SHIFT 12 /**< Shift value for CC_MINT */ 659 #define _RTCC_CC_TIME_MINT_MASK 0x7000UL /**< Bit mask for CC_MINT */ 660 #define _RTCC_CC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ 661 #define RTCC_CC_TIME_MINT_DEFAULT (_RTCC_CC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ 662 #define _RTCC_CC_TIME_HOURU_SHIFT 16 /**< Shift value for CC_HOURU */ 663 #define _RTCC_CC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for CC_HOURU */ 664 #define _RTCC_CC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ 665 #define RTCC_CC_TIME_HOURU_DEFAULT (_RTCC_CC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ 666 #define _RTCC_CC_TIME_HOURT_SHIFT 20 /**< Shift value for CC_HOURT */ 667 #define _RTCC_CC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for CC_HOURT */ 668 #define _RTCC_CC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ 669 #define RTCC_CC_TIME_HOURT_DEFAULT (_RTCC_CC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ 670 671 /* Bit fields for RTCC CC_DATE */ 672 #define _RTCC_CC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_DATE */ 673 #define _RTCC_CC_DATE_MASK 0x00001F3FUL /**< Mask for RTCC_CC_DATE */ 674 #define _RTCC_CC_DATE_DAYU_SHIFT 0 /**< Shift value for CC_DAYU */ 675 #define _RTCC_CC_DATE_DAYU_MASK 0xFUL /**< Bit mask for CC_DAYU */ 676 #define _RTCC_CC_DATE_DAYU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ 677 #define RTCC_CC_DATE_DAYU_DEFAULT (_RTCC_CC_DATE_DAYU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ 678 #define _RTCC_CC_DATE_DAYT_SHIFT 4 /**< Shift value for CC_DAYT */ 679 #define _RTCC_CC_DATE_DAYT_MASK 0x30UL /**< Bit mask for CC_DAYT */ 680 #define _RTCC_CC_DATE_DAYT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ 681 #define RTCC_CC_DATE_DAYT_DEFAULT (_RTCC_CC_DATE_DAYT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ 682 #define _RTCC_CC_DATE_MONTHU_SHIFT 8 /**< Shift value for CC_MONTHU */ 683 #define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */ 684 #define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ 685 #define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ 686 #define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, Tens */ 687 #define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */ 688 #define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */ 689 #define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ 690 #define RTCC_CC_DATE_MONTHT_DEFAULT (_RTCC_CC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ 691 692 /* Bit fields for RTCC RET_REG */ 693 #define _RTCC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for RTCC_RET_REG */ 694 #define _RTCC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for RTCC_RET_REG */ 695 #define _RTCC_RET_REG_REG_SHIFT 0 /**< Shift value for RET_REG */ 696 #define _RTCC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for RET_REG */ 697 #define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */ 698 #define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */ 699 700 /** @} */ 701 /** @} End of group EFM32PG12B_RTCC */ 702 /** @} End of group Parts */ 703
