1 /***************************************************************************//** 2 * @file 3 * @brief EFM32HG_DMACTRL register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 42 /***************************************************************************//** 43 * @defgroup EFM32HG_DMACTRL_BitFields 44 * @{ 45 ******************************************************************************/ 46 #define _DMA_CTRL_DST_INC_MASK 0xC0000000UL /**< Data increment for destination, bit mask */ 47 #define _DMA_CTRL_DST_INC_SHIFT 30 /**< Data increment for destination, shift value */ 48 #define _DMA_CTRL_DST_INC_BYTE 0x00 /**< Byte/8-bit increment */ 49 #define _DMA_CTRL_DST_INC_HALFWORD 0x01 /**< Half word/16-bit increment */ 50 #define _DMA_CTRL_DST_INC_WORD 0x02 /**< Word/32-bit increment */ 51 #define _DMA_CTRL_DST_INC_NONE 0x03 /**< No increment */ 52 #define DMA_CTRL_DST_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */ 53 #define DMA_CTRL_DST_INC_HALFWORD 0x40000000UL /**< Half word/16-bit increment */ 54 #define DMA_CTRL_DST_INC_WORD 0x80000000UL /**< Word/32-bit increment */ 55 #define DMA_CTRL_DST_INC_NONE 0xC0000000UL /**< No increment */ 56 #define _DMA_CTRL_DST_SIZE_MASK 0x30000000UL /**< Data size for destination - MUST be the same as source, bit mask */ 57 #define _DMA_CTRL_DST_SIZE_SHIFT 28 /**< Data size for destination - MUST be the same as source, shift value */ 58 #define _DMA_CTRL_DST_SIZE_BYTE 0x00 /**< Byte/8-bit data size */ 59 #define _DMA_CTRL_DST_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */ 60 #define _DMA_CTRL_DST_SIZE_WORD 0x02 /**< Word/32-bit data size */ 61 #define _DMA_CTRL_DST_SIZE_RSVD 0x03 /**< Reserved */ 62 #define DMA_CTRL_DST_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */ 63 #define DMA_CTRL_DST_SIZE_HALFWORD 0x10000000UL /**< Half word/16-bit data size */ 64 #define DMA_CTRL_DST_SIZE_WORD 0x20000000UL /**< Word/32-bit data size */ 65 #define DMA_CTRL_DST_SIZE_RSVD 0x30000000UL /**< Reserved - do not use */ 66 #define _DMA_CTRL_SRC_INC_MASK 0x0C000000UL /**< Data increment for source, bit mask */ 67 #define _DMA_CTRL_SRC_INC_SHIFT 26 /**< Data increment for source, shift value */ 68 #define _DMA_CTRL_SRC_INC_BYTE 0x00 /**< Byte/8-bit increment */ 69 #define _DMA_CTRL_SRC_INC_HALFWORD 0x01 /**< Half word/16-bit increment */ 70 #define _DMA_CTRL_SRC_INC_WORD 0x02 /**< Word/32-bit increment */ 71 #define _DMA_CTRL_SRC_INC_NONE 0x03 /**< No increment */ 72 #define DMA_CTRL_SRC_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */ 73 #define DMA_CTRL_SRC_INC_HALFWORD 0x04000000UL /**< Half word/16-bit increment */ 74 #define DMA_CTRL_SRC_INC_WORD 0x08000000UL /**< Word/32-bit increment */ 75 #define DMA_CTRL_SRC_INC_NONE 0x0C000000UL /**< No increment */ 76 #define _DMA_CTRL_SRC_SIZE_MASK 0x03000000UL /**< Data size for source - MUST be the same as destination, bit mask */ 77 #define _DMA_CTRL_SRC_SIZE_SHIFT 24 /**< Data size for source - MUST be the same as destination, shift value */ 78 #define _DMA_CTRL_SRC_SIZE_BYTE 0x00 /**< Byte/8-bit data size */ 79 #define _DMA_CTRL_SRC_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */ 80 #define _DMA_CTRL_SRC_SIZE_WORD 0x02 /**< Word/32-bit data size */ 81 #define _DMA_CTRL_SRC_SIZE_RSVD 0x03 /**< Reserved */ 82 #define DMA_CTRL_SRC_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */ 83 #define DMA_CTRL_SRC_SIZE_HALFWORD 0x01000000UL /**< Half word/16-bit data size */ 84 #define DMA_CTRL_SRC_SIZE_WORD 0x02000000UL /**< Word/32-bit data size */ 85 #define DMA_CTRL_SRC_SIZE_RSVD 0x03000000UL /**< Reserved - do not use */ 86 #define _DMA_CTRL_DST_PROT_CTRL_MASK 0x00E00000UL /**< Protection flag for destination, bit mask */ 87 #define _DMA_CTRL_DST_PROT_CTRL_SHIFT 21 /**< Protection flag for destination, shift value */ 88 #define DMA_CTRL_DST_PROT_PRIVILEGED 0x00200000UL /**< Privileged mode for destination */ 89 #define DMA_CTRL_DST_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for estination */ 90 #define _DMA_CTRL_SRC_PROT_CTRL_MASK 0x001C0000UL /**< Protection flag for source, bit mask */ 91 #define _DMA_CTRL_SRC_PROT_CTRL_SHIFT 18 /**< Protection flag for source, shift value */ 92 #define DMA_CTRL_SRC_PROT_PRIVILEGED 0x00040000UL /**< Privileged mode for destination */ 93 #define DMA_CTRL_SRC_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for estination */ 94 #define _DMA_CTRL_PROT_NON_PRIVILEGED 0x00 /**< Protection bits to indicate non-privileged access */ 95 #define _DMA_CTRL_PROT_PRIVILEGED 0x01 /**< Protection bits to indicate privileged access */ 96 #define _DMA_CTRL_R_POWER_MASK 0x0003C000UL /**< DMA arbitration mask */ 97 #define _DMA_CTRL_R_POWER_SHIFT 14 /**< Number of DMA cycles before controller does new arbitration in 2^R */ 98 #define _DMA_CTRL_R_POWER_1 0x00 /**< Arbitrate after each transfer */ 99 #define _DMA_CTRL_R_POWER_2 0x01 /**< Arbitrate after every 2 transfers */ 100 #define _DMA_CTRL_R_POWER_4 0x02 /**< Arbitrate after every 4 transfers */ 101 #define _DMA_CTRL_R_POWER_8 0x03 /**< Arbitrate after every 8 transfers */ 102 #define _DMA_CTRL_R_POWER_16 0x04 /**< Arbitrate after every 16 transfers */ 103 #define _DMA_CTRL_R_POWER_32 0x05 /**< Arbitrate after every 32 transfers */ 104 #define _DMA_CTRL_R_POWER_64 0x06 /**< Arbitrate after every 64 transfers */ 105 #define _DMA_CTRL_R_POWER_128 0x07 /**< Arbitrate after every 128 transfers */ 106 #define _DMA_CTRL_R_POWER_256 0x08 /**< Arbitrate after every 256 transfers */ 107 #define _DMA_CTRL_R_POWER_512 0x09 /**< Arbitrate after every 512 transfers */ 108 #define _DMA_CTRL_R_POWER_1024 0x0a /**< Arbitrate after every 1024 transfers */ 109 #define DMA_CTRL_R_POWER_1 0x00000000UL /**< Arbitrate after each transfer */ 110 #define DMA_CTRL_R_POWER_2 0x00004000UL /**< Arbitrate after every 2 transfers */ 111 #define DMA_CTRL_R_POWER_4 0x00008000UL /**< Arbitrate after every 4 transfers */ 112 #define DMA_CTRL_R_POWER_8 0x0000c000UL /**< Arbitrate after every 8 transfers */ 113 #define DMA_CTRL_R_POWER_16 0x00010000UL /**< Arbitrate after every 16 transfers */ 114 #define DMA_CTRL_R_POWER_32 0x00014000UL /**< Arbitrate after every 32 transfers */ 115 #define DMA_CTRL_R_POWER_64 0x00018000UL /**< Arbitrate after every 64 transfers */ 116 #define DMA_CTRL_R_POWER_128 0x0001c000UL /**< Arbitrate after every 128 transfers */ 117 #define DMA_CTRL_R_POWER_256 0x00020000UL /**< Arbitrate after every 256 transfers */ 118 #define DMA_CTRL_R_POWER_512 0x00024000UL /**< Arbitrate after every 512 transfers */ 119 #define DMA_CTRL_R_POWER_1024 0x00028000UL /**< Arbitrate after every 1024 transfers */ 120 #define _DMA_CTRL_N_MINUS_1_MASK 0x00003FF0UL /**< Number of DMA transfers minus 1, bit mask. See PL230 documentation */ 121 #define _DMA_CTRL_N_MINUS_1_SHIFT 4 /**< Number of DMA transfers minus 1, shift mask. See PL230 documentation */ 122 #define _DMA_CTRL_NEXT_USEBURST_MASK 0x00000008UL /**< DMA useburst_set[C] is 1 when using scatter-gather DMA and using alternate data */ 123 #define _DMA_CTRL_NEXT_USEBURST_SHIFT 3 /**< DMA useburst shift */ 124 #define _DMA_CTRL_CYCLE_CTRL_MASK 0x00000007UL /**< DMA Cycle control bit mask - basic/auto/ping-poing/scath-gath */ 125 #define _DMA_CTRL_CYCLE_CTRL_SHIFT 0 /**< DMA Cycle control bit shift */ 126 #define _DMA_CTRL_CYCLE_CTRL_INVALID 0x00 /**< Invalid cycle type */ 127 #define _DMA_CTRL_CYCLE_CTRL_BASIC 0x01 /**< Basic cycle type */ 128 #define _DMA_CTRL_CYCLE_CTRL_AUTO 0x02 /**< Auto cycle type */ 129 #define _DMA_CTRL_CYCLE_CTRL_PINGPONG 0x03 /**< PingPong cycle type */ 130 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x04 /**< Memory scatter gather cycle type */ 131 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x05 /**< Memory scatter gather using alternate structure */ 132 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x06 /**< Peripheral scatter gather cycle type */ 133 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x07 /**< Peripheral scatter gather cycle type using alternate structure */ 134 #define DMA_CTRL_CYCLE_CTRL_INVALID 0x00000000UL /**< Invalid cycle type */ 135 #define DMA_CTRL_CYCLE_CTRL_BASIC 0x00000001UL /**< Basic cycle type */ 136 #define DMA_CTRL_CYCLE_CTRL_AUTO 0x00000002UL /**< Auto cycle type */ 137 #define DMA_CTRL_CYCLE_CTRL_PINGPONG 0x00000003UL /**< PingPong cycle type */ 138 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x000000004UL /**< Memory scatter gather cycle type */ 139 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x000000005UL /**< Memory scatter gather using alternate structure */ 140 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x000000006UL /**< Peripheral scatter gather cycle type */ 141 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */ 142 143 /** @} End of group EFM32HG_DMA */ 144 /** @} End of group Parts */ 145
