1 /***************************************************************************//** 2 * @file 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File 4 * for EFM32HG222F64 5 ******************************************************************************* 6 * # License 7 * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b> 8 ******************************************************************************* 9 * 10 * SPDX-License-Identifier: Zlib 11 * 12 * The licensor of this software is Silicon Laboratories Inc. 13 * 14 * This software is provided 'as-is', without any express or implied 15 * warranty. In no event will the authors be held liable for any damages 16 * arising from the use of this software. 17 * 18 * Permission is granted to anyone to use this software for any purpose, 19 * including commercial applications, and to alter it and redistribute it 20 * freely, subject to the following restrictions: 21 * 22 * 1. The origin of this software must not be misrepresented; you must not 23 * claim that you wrote the original software. If you use this software 24 * in a product, an acknowledgment in the product documentation would be 25 * appreciated but is not required. 26 * 2. Altered source versions must be plainly marked as such, and must not be 27 * misrepresented as being the original software. 28 * 3. This notice may not be removed or altered from any source distribution. 29 * 30 ******************************************************************************/ 31 32 #if defined(__ICCARM__) 33 #pragma system_include /* Treat file as system include file. */ 34 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 35 #pragma clang system_header /* Treat file as system include file. */ 36 #endif 37 38 #ifndef EFM32HG222F64_H 39 #define EFM32HG222F64_H 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /***************************************************************************//** 46 * @addtogroup Parts 47 * @{ 48 ******************************************************************************/ 49 50 /***************************************************************************//** 51 * @defgroup EFM32HG222F64 EFM32HG222F64 52 * @{ 53 ******************************************************************************/ 54 55 /** Interrupt Number Definition */ 56 typedef enum IRQn{ 57 /****** Cortex-M0+ Processor Exceptions Numbers *****************************************/ 58 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M0+ Non Maskable Interrupt */ 59 HardFault_IRQn = -13, /*!< -13 Cortex-M0+ Hard Fault Interrupt */ 60 SVCall_IRQn = -5, /*!< -5 Cortex-M0+ SV Call Interrupt */ 61 PendSV_IRQn = -2, /*!< -2 Cortex-M0+ Pend SV Interrupt */ 62 SysTick_IRQn = -1, /*!< -1 Cortex-M0+ System Tick Interrupt */ 63 64 /****** EFM32HG Peripheral Interrupt Numbers ********************************************/ 65 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */ 66 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */ 67 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */ 68 ACMP0_IRQn = 3, /*!< 3 EFM32 ACMP0 Interrupt */ 69 ADC0_IRQn = 4, /*!< 4 EFM32 ADC0 Interrupt */ 70 I2C0_IRQn = 5, /*!< 5 EFM32 I2C0 Interrupt */ 71 GPIO_ODD_IRQn = 6, /*!< 6 EFM32 GPIO_ODD Interrupt */ 72 TIMER1_IRQn = 7, /*!< 7 EFM32 TIMER1 Interrupt */ 73 USART1_RX_IRQn = 8, /*!< 8 EFM32 USART1_RX Interrupt */ 74 USART1_TX_IRQn = 9, /*!< 9 EFM32 USART1_TX Interrupt */ 75 LEUART0_IRQn = 10, /*!< 10 EFM32 LEUART0 Interrupt */ 76 PCNT0_IRQn = 11, /*!< 11 EFM32 PCNT0 Interrupt */ 77 RTC_IRQn = 12, /*!< 12 EFM32 RTC Interrupt */ 78 CMU_IRQn = 13, /*!< 13 EFM32 CMU Interrupt */ 79 VCMP_IRQn = 14, /*!< 14 EFM32 VCMP Interrupt */ 80 MSC_IRQn = 15, /*!< 15 EFM32 MSC Interrupt */ 81 AES_IRQn = 16, /*!< 16 EFM32 AES Interrupt */ 82 USART0_RX_IRQn = 17, /*!< 17 EFM32 USART0_RX Interrupt */ 83 USART0_TX_IRQn = 18, /*!< 18 EFM32 USART0_TX Interrupt */ 84 TIMER2_IRQn = 20, /*!< 20 EFM32 TIMER2 Interrupt */ 85 } IRQn_Type; 86 87 /***************************************************************************//** 88 * @defgroup EFM32HG222F64_Core EFM32HG222F64 Core 89 * @{ 90 * @brief Processor and Core Peripheral Section 91 ******************************************************************************/ 92 #define __MPU_PRESENT 0U /**< MPU not present */ 93 #define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ 94 #define __NVIC_PRIO_BITS 2U /**< NVIC interrupt priority bits */ 95 #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ 96 97 /** @} End of group EFM32HG222F64_Core */ 98 99 /***************************************************************************//** 100 * @defgroup EFM32HG222F64_Part EFM32HG222F64 Part 101 * @{ 102 ******************************************************************************/ 103 104 /** Part family */ 105 #define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */ 106 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */ 107 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */ 108 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */ 109 #define _SILICON_LABS_GECKO_INTERNAL_SDID 77 /**< Silicon Labs internal use only, may change any time */ 110 #define _SILICON_LABS_GECKO_INTERNAL_SDID_77 /**< Silicon Labs internal use only, may change any time */ 111 #define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */ 112 #define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */ 113 114 /* If part number is not defined as compiler option, define it */ 115 #if !defined(EFM32HG222F64) 116 #define EFM32HG222F64 1 /**< Happy Gecko Part */ 117 #endif 118 119 /** Configure part number */ 120 #define PART_NUMBER "EFM32HG222F64" /**< Part Number */ 121 122 /** Memory Base addresses and limits */ 123 #define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ 124 #define RAM_MEM_SIZE (0x40000UL) /**< RAM available address space */ 125 #define RAM_MEM_END (0x2003FFFFUL) /**< RAM end address */ 126 #define RAM_MEM_BITS (0x18UL) /**< RAM used bits */ 127 #define DEVICE_MEM_BASE (0xF0040000UL) /**< DEVICE base address */ 128 #define DEVICE_MEM_SIZE (0x1000UL) /**< DEVICE available address space */ 129 #define DEVICE_MEM_END (0xF0040FFFUL) /**< DEVICE end address */ 130 #define DEVICE_MEM_BITS (0x12UL) /**< DEVICE used bits */ 131 #define USBC_MEM_BASE (0x40100000UL) /**< USBC base address */ 132 #define USBC_MEM_SIZE (0x40000UL) /**< USBC available address space */ 133 #define USBC_MEM_END (0x4013FFFFUL) /**< USBC end address */ 134 #define USBC_MEM_BITS (0x18UL) /**< USBC used bits */ 135 #define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */ 136 #define RAM_CODE_MEM_SIZE (0x20000UL) /**< RAM_CODE available address space */ 137 #define RAM_CODE_MEM_END (0x1001FFFFUL) /**< RAM_CODE end address */ 138 #define RAM_CODE_MEM_BITS (0x17UL) /**< RAM_CODE used bits */ 139 #define PER_MEM_BASE (0x40000000UL) /**< PER base address */ 140 #define PER_MEM_SIZE (0xE0000UL) /**< PER available address space */ 141 #define PER_MEM_END (0x400DFFFFUL) /**< PER end address */ 142 #define PER_MEM_BITS (0x20UL) /**< PER used bits */ 143 #define FLASH_MEM_BASE (0x0UL) /**< FLASH base address */ 144 #define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */ 145 #define FLASH_MEM_END (0xFFFFFFFUL) /**< FLASH end address */ 146 #define FLASH_MEM_BITS (0x28UL) /**< FLASH used bits */ 147 #define AES_MEM_BASE (0x400E0000UL) /**< AES base address */ 148 #define AES_MEM_SIZE (0x400UL) /**< AES available address space */ 149 #define AES_MEM_END (0x400E03FFUL) /**< AES end address */ 150 #define AES_MEM_BITS (0x10UL) /**< AES used bits */ 151 152 /** Flash and SRAM limits for EFM32HG222F64 */ 153 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ 154 #define FLASH_SIZE (0x00010000UL) /**< Available Flash Memory */ 155 #define FLASH_PAGE_SIZE 1024U /**< Flash Memory page size */ 156 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ 157 #define SRAM_SIZE (0x00002000UL) /**< Available SRAM Memory */ 158 #define __CM0PLUS_REV 0x0001U /**< Cortex-M0+ Core revision r0p1 */ 159 #define PRS_CHAN_COUNT 6 /**< Number of PRS channels */ 160 #define DMA_CHAN_COUNT 6 /**< Number of DMA channels */ 161 #define EXT_IRQ_COUNT 21 /**< Number of External (NVIC) interrupts */ 162 163 /** AF channels connect the different on-chip peripherals with the af-mux */ 164 #define AFCHAN_MAX 42U 165 #define AFCHANLOC_MAX 7U 166 /** Analog AF channels */ 167 #define AFACHAN_MAX 27U 168 169 /* Part number capabilities */ 170 171 #define TIMER_PRESENT /**< TIMER is available in this part */ 172 #define TIMER_COUNT 3 /**< 3 TIMERs available */ 173 #define ACMP_PRESENT /**< ACMP is available in this part */ 174 #define ACMP_COUNT 1 /**< 1 ACMPs available */ 175 #define USART_PRESENT /**< USART is available in this part */ 176 #define USART_COUNT 2 /**< 2 USARTs available */ 177 #define IDAC_PRESENT /**< IDAC is available in this part */ 178 #define IDAC_COUNT 1 /**< 1 IDACs available */ 179 #define ADC_PRESENT /**< ADC is available in this part */ 180 #define ADC_COUNT 1 /**< 1 ADCs available */ 181 #define LEUART_PRESENT /**< LEUART is available in this part */ 182 #define LEUART_COUNT 1 /**< 1 LEUARTs available */ 183 #define PCNT_PRESENT /**< PCNT is available in this part */ 184 #define PCNT_COUNT 1 /**< 1 PCNTs available */ 185 #define I2C_PRESENT /**< I2C is available in this part */ 186 #define I2C_COUNT 1 /**< 1 I2Cs available */ 187 #define AES_PRESENT /**< AES is available in this part */ 188 #define AES_COUNT 1 /**< 1 AES available */ 189 #define DMA_PRESENT /**< DMA is available in this part */ 190 #define DMA_COUNT 1 /**< 1 DMA available */ 191 #define LE_PRESENT /**< LE is available in this part */ 192 #define LE_COUNT 1 /**< 1 LE available */ 193 #define USBLE_PRESENT /**< USBLE is available in this part */ 194 #define USBLE_COUNT 1 /**< 1 USBLE available */ 195 #define MSC_PRESENT /**< MSC is available in this part */ 196 #define MSC_COUNT 1 /**< 1 MSC available */ 197 #define EMU_PRESENT /**< EMU is available in this part */ 198 #define EMU_COUNT 1 /**< 1 EMU available */ 199 #define RMU_PRESENT /**< RMU is available in this part */ 200 #define RMU_COUNT 1 /**< 1 RMU available */ 201 #define CMU_PRESENT /**< CMU is available in this part */ 202 #define CMU_COUNT 1 /**< 1 CMU available */ 203 #define PRS_PRESENT /**< PRS is available in this part */ 204 #define PRS_COUNT 1 /**< 1 PRS available */ 205 #define GPIO_PRESENT /**< GPIO is available in this part */ 206 #define GPIO_COUNT 1 /**< 1 GPIO available */ 207 #define VCMP_PRESENT /**< VCMP is available in this part */ 208 #define VCMP_COUNT 1 /**< 1 VCMP available */ 209 #define RTC_PRESENT /**< RTC is available in this part */ 210 #define RTC_COUNT 1 /**< 1 RTC available */ 211 #define HFXTAL_PRESENT /**< HFXTAL is available in this part */ 212 #define HFXTAL_COUNT 1 /**< 1 HFXTAL available */ 213 #define LFXTAL_PRESENT /**< LFXTAL is available in this part */ 214 #define LFXTAL_COUNT 1 /**< 1 LFXTAL available */ 215 #define USHFRCO_PRESENT /**< USHFRCO is available in this part */ 216 #define USHFRCO_COUNT 1 /**< 1 USHFRCO available */ 217 #define WDOG_PRESENT /**< WDOG is available in this part */ 218 #define WDOG_COUNT 1 /**< 1 WDOG available */ 219 #define DBG_PRESENT /**< DBG is available in this part */ 220 #define DBG_COUNT 1 /**< 1 DBG available */ 221 #define MTB_PRESENT /**< MTB is available in this part */ 222 #define MTB_COUNT 1 /**< 1 MTB available */ 223 #define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ 224 #define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ 225 #define ANALOG_PRESENT /**< ANALOG is available in this part */ 226 #define ANALOG_COUNT 1 /**< 1 ANALOG available */ 227 228 /** @} End of group EFM32HG222F64_Part */ 229 230 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ 231 #include "system_efm32hg.h" /* System Header */ 232 233 /***************************************************************************//** 234 * @defgroup EFM32HG222F64_Peripheral_TypeDefs EFM32HG222F64 Peripheral TypeDefs 235 * @{ 236 * @brief Device Specific Peripheral Register Structures 237 ******************************************************************************/ 238 239 #include "efm32hg_aes.h" 240 #include "efm32hg_dma_ch.h" 241 #include "efm32hg_dma.h" 242 #include "efm32hg_msc.h" 243 #include "efm32hg_emu.h" 244 #include "efm32hg_rmu.h" 245 246 /***************************************************************************//** 247 * @defgroup EFM32HG222F64_CMU EFM32HG222F64 CMU 248 * @{ 249 * @brief EFM32HG222F64_CMU Register Declaration 250 ******************************************************************************/ 251 typedef struct { 252 __IOM uint32_t CTRL; /**< CMU Control Register */ 253 __IOM uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */ 254 __IOM uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */ 255 __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ 256 __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ 257 __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ 258 __IOM uint32_t CALCTRL; /**< Calibration Control Register */ 259 __IOM uint32_t CALCNT; /**< Calibration Counter Register */ 260 __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ 261 __IOM uint32_t CMD; /**< Command Register */ 262 __IOM uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */ 263 __IM uint32_t STATUS; /**< Status Register */ 264 __IM uint32_t IF; /**< Interrupt Flag Register */ 265 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 266 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 267 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 268 __IOM uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */ 269 __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ 270 uint32_t RESERVED0[2U]; /**< Reserved for future use **/ 271 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 272 __IOM uint32_t FREEZE; /**< Freeze Register */ 273 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */ 274 uint32_t RESERVED1[1U]; /**< Reserved for future use **/ 275 __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ 276 __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ 277 __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */ 278 uint32_t RESERVED2[1U]; /**< Reserved for future use **/ 279 __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ 280 uint32_t RESERVED3[1U]; /**< Reserved for future use **/ 281 __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ 282 283 uint32_t RESERVED4[1U]; /**< Reserved for future use **/ 284 __IOM uint32_t ROUTE; /**< I/O Routing Register */ 285 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 286 287 uint32_t RESERVED5[18U]; /**< Reserved for future use **/ 288 __IOM uint32_t USBCRCTRL; /**< USB Clock Recovery Control */ 289 __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control */ 290 __IOM uint32_t USHFRCOTUNE; /**< USHFRCO Frequency Tune */ 291 __IOM uint32_t USHFRCOCONF; /**< USHFRCO Configuration */ 292 } CMU_TypeDef; /**< CMU Register Declaration *//** @} */ 293 294 #include "efm32hg_timer_cc.h" 295 #include "efm32hg_timer.h" 296 #include "efm32hg_acmp.h" 297 #include "efm32hg_usart.h" 298 #include "efm32hg_prs_ch.h" 299 300 /***************************************************************************//** 301 * @defgroup EFM32HG222F64_PRS EFM32HG222F64 PRS 302 * @{ 303 * @brief EFM32HG222F64_PRS Register Declaration 304 ******************************************************************************/ 305 typedef struct { 306 __IOM uint32_t SWPULSE; /**< Software Pulse Register */ 307 __IOM uint32_t SWLEVEL; /**< Software Level Register */ 308 __IOM uint32_t ROUTE; /**< I/O Routing Register */ 309 310 uint32_t RESERVED0[1U]; /**< Reserved registers */ 311 PRS_CH_TypeDef CH[6U]; /**< Channel registers */ 312 313 uint32_t RESERVED1[6U]; /**< Reserved for future use **/ 314 __IOM uint32_t TRACECTRL; /**< MTB Trace Control Register */ 315 } PRS_TypeDef; /**< PRS Register Declaration *//** @} */ 316 317 #include "efm32hg_idac.h" 318 #include "efm32hg_gpio_p.h" 319 #include "efm32hg_gpio.h" 320 #include "efm32hg_vcmp.h" 321 #include "efm32hg_adc.h" 322 #include "efm32hg_leuart.h" 323 #include "efm32hg_pcnt.h" 324 #include "efm32hg_i2c.h" 325 #include "efm32hg_rtc.h" 326 #include "efm32hg_wdog.h" 327 #include "efm32hg_mtb.h" 328 #include "efm32hg_dma_descriptor.h" 329 #include "efm32hg_devinfo.h" 330 #include "efm32hg_romtable.h" 331 #include "efm32hg_calibrate.h" 332 333 /** @} End of group EFM32HG222F64_Peripheral_TypeDefs */ 334 335 /***************************************************************************//** 336 * @defgroup EFM32HG222F64_Peripheral_Base EFM32HG222F64 Peripheral Memory Map 337 * @{ 338 ******************************************************************************/ 339 340 #define AES_BASE (0x400E0000UL) /**< AES base address */ 341 #define DMA_BASE (0x400C2000UL) /**< DMA base address */ 342 #define MSC_BASE (0x400C0000UL) /**< MSC base address */ 343 #define EMU_BASE (0x400C6000UL) /**< EMU base address */ 344 #define RMU_BASE (0x400CA000UL) /**< RMU base address */ 345 #define CMU_BASE (0x400C8000UL) /**< CMU base address */ 346 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */ 347 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */ 348 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */ 349 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */ 350 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */ 351 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */ 352 #define PRS_BASE (0x400CC000UL) /**< PRS base address */ 353 #define IDAC0_BASE (0x40004000UL) /**< IDAC0 base address */ 354 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ 355 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */ 356 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ 357 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */ 358 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */ 359 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */ 360 #define RTC_BASE (0x40080000UL) /**< RTC base address */ 361 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */ 362 #define MTB_BASE (0xF0040000UL) /**< MTB base address */ 363 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */ 364 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ 365 #define ROMTABLE_BASE (0xF00FFFD0UL) /**< ROMTABLE base address */ 366 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ 367 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ 368 369 /** @} End of group EFM32HG222F64_Peripheral_Base */ 370 371 /***************************************************************************//** 372 * @defgroup EFM32HG222F64_Peripheral_Declaration EFM32HG222F64 Peripheral Declarations 373 * @{ 374 ******************************************************************************/ 375 376 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */ 377 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */ 378 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ 379 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ 380 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ 381 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ 382 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ 383 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ 384 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ 385 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ 386 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ 387 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ 388 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ 389 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ 390 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ 391 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */ 392 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ 393 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ 394 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ 395 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ 396 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ 397 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */ 398 #define MTB ((MTB_TypeDef *) MTB_BASE) /**< MTB base pointer */ 399 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */ 400 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ 401 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ 402 403 /** @} End of group EFM32HG222F64_Peripheral_Declaration */ 404 405 /***************************************************************************//** 406 * @defgroup EFM32HG222F64_BitFields EFM32HG222F64 Bit Fields 407 * @{ 408 ******************************************************************************/ 409 410 /***************************************************************************//** 411 * @addtogroup EFM32HG222F64_PRS_Signals 412 * @{ 413 * @brief PRS Signal names 414 ******************************************************************************/ 415 #define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */ 416 #define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */ 417 #define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */ 418 #define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */ 419 #define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */ 420 #define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */ 421 #define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */ 422 #define PRS_USART1_IRTX ((17 << 16) + 0) /**< PRS USART 1 IRDA out */ 423 #define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */ 424 #define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */ 425 #define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */ 426 #define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */ 427 #define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */ 428 #define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */ 429 #define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */ 430 #define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */ 431 #define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */ 432 #define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */ 433 #define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */ 434 #define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */ 435 #define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */ 436 #define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */ 437 #define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */ 438 #define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */ 439 #define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */ 440 #define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */ 441 #define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */ 442 #define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */ 443 #define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */ 444 #define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */ 445 #define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */ 446 #define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */ 447 #define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */ 448 #define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */ 449 #define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */ 450 #define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */ 451 #define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */ 452 #define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */ 453 #define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */ 454 #define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */ 455 #define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */ 456 #define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */ 457 #define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */ 458 #define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */ 459 #define PRS_PCNT0_TCC ((54 << 16) + 0) /**< PRS Triggered compare match */ 460 461 /** @} End of group EFM32HG222F64_PRS */ 462 463 #include "efm32hg_dmareq.h" 464 #include "efm32hg_dmactrl.h" 465 466 /***************************************************************************//** 467 * @defgroup EFM32HG222F64_CMU_BitFields EFM32HG222F64_CMU Bit Fields 468 * @{ 469 ******************************************************************************/ 470 471 /* Bit fields for CMU CTRL */ 472 #define _CMU_CTRL_RESETVALUE 0x000C262CUL /**< Default value for CMU_CTRL */ 473 #define _CMU_CTRL_MASK 0x07FFFEEFUL /**< Mask for CMU_CTRL */ 474 #define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */ 475 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */ 476 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 477 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */ 478 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */ 479 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */ 480 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ 481 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */ 482 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */ 483 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */ 484 #define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */ 485 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */ 486 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */ 487 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */ 488 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */ 489 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */ 490 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */ 491 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */ 492 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */ 493 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */ 494 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */ 495 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */ 496 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */ 497 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */ 498 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ 499 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ 500 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */ 501 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */ 502 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */ 503 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 504 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */ 505 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */ 506 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */ 507 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */ 508 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */ 509 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */ 510 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */ 511 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */ 512 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */ 513 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */ 514 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */ 515 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */ 516 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */ 517 #define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */ 518 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */ 519 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 520 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */ 521 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */ 522 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */ 523 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */ 524 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */ 525 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */ 526 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */ 527 #define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */ 528 #define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */ 529 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */ 530 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */ 531 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ 532 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */ 533 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */ 534 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */ 535 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */ 536 #define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */ 537 #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */ 538 #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 539 #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */ 540 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */ 541 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */ 542 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */ 543 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 544 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */ 545 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */ 546 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */ 547 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */ 548 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */ 549 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */ 550 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */ 551 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */ 552 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */ 553 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */ 554 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */ 555 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */ 556 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */ 557 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */ 558 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */ 559 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 560 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */ 561 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */ 562 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */ 563 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */ 564 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */ 565 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */ 566 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */ 567 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */ 568 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ 569 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */ 570 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */ 571 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */ 572 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */ 573 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */ 574 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */ 575 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */ 576 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */ 577 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */ 578 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */ 579 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 580 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */ 581 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */ 582 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */ 583 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */ 584 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */ 585 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */ 586 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */ 587 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */ 588 #define _CMU_CTRL_CLKOUTSEL1_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CTRL */ 589 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */ 590 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */ 591 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */ 592 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */ 593 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */ 594 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */ 595 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */ 596 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */ 597 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ 598 #define CMU_CTRL_CLKOUTSEL1_USHFRCO (_CMU_CTRL_CLKOUTSEL1_USHFRCO << 23) /**< Shifted mode USHFRCO for CMU_CTRL */ 599 600 /* Bit fields for CMU HFCORECLKDIV */ 601 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */ 602 #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */ 603 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */ 604 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */ 605 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */ 606 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */ 607 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */ 608 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */ 609 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */ 610 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */ 611 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */ 612 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */ 613 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */ 614 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */ 615 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */ 616 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */ 617 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */ 618 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */ 619 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */ 620 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */ 621 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */ 622 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */ 623 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */ 624 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */ 625 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */ 626 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */ 627 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */ 628 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */ 629 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */ 630 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */ 631 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */ 632 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */ 633 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */ 634 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */ 635 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */ 636 637 /* Bit fields for CMU HFPERCLKDIV */ 638 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */ 639 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */ 640 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */ 641 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */ 642 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */ 643 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */ 644 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */ 645 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */ 646 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */ 647 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */ 648 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */ 649 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */ 650 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */ 651 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */ 652 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */ 653 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */ 654 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */ 655 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */ 656 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */ 657 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */ 658 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */ 659 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */ 660 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */ 661 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */ 662 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */ 663 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */ 664 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */ 665 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */ 666 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */ 667 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */ 668 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */ 669 670 /* Bit fields for CMU HFRCOCTRL */ 671 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */ 672 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */ 673 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 674 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */ 675 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 676 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 677 #define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */ 678 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */ 679 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */ 680 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */ 681 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */ 682 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 683 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */ 684 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */ 685 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */ 686 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */ 687 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */ 688 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 689 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */ 690 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */ 691 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */ 692 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */ 693 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 694 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 695 696 /* Bit fields for CMU LFRCOCTRL */ 697 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */ 698 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */ 699 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 700 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 701 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 702 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 703 704 /* Bit fields for CMU AUXHFRCOCTRL */ 705 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */ 706 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */ 707 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 708 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */ 709 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 710 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 711 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */ 712 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */ 713 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 714 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */ 715 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */ 716 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */ 717 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */ 718 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */ 719 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 720 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */ 721 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */ 722 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */ 723 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */ 724 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */ 725 726 /* Bit fields for CMU CALCTRL */ 727 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ 728 #define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */ 729 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ 730 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ 731 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 732 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ 733 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ 734 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ 735 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ 736 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ 737 #define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000005UL /**< Mode USHFRCO for CMU_CALCTRL */ 738 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 739 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ 740 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ 741 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ 742 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ 743 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ 744 #define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ 745 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */ 746 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */ 747 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 748 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ 749 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ 750 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ 751 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ 752 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ 753 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ 754 #define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_CALCTRL */ 755 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 756 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */ 757 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */ 758 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */ 759 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */ 760 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */ 761 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ 762 #define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_CALCTRL */ 763 #define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */ 764 #define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */ 765 #define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */ 766 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 767 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 768 769 /* Bit fields for CMU CALCNT */ 770 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ 771 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ 772 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ 773 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ 774 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ 775 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ 776 777 /* Bit fields for CMU OSCENCMD */ 778 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ 779 #define _CMU_OSCENCMD_MASK 0x00000FFFUL /**< Mask for CMU_OSCENCMD */ 780 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ 781 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ 782 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ 783 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 784 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 785 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ 786 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ 787 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ 788 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 789 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 790 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ 791 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ 792 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ 793 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 794 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 795 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ 796 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ 797 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ 798 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 799 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 800 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ 801 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ 802 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ 803 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 804 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 805 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ 806 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ 807 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ 808 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 809 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 810 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ 811 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ 812 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ 813 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 814 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 815 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ 816 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ 817 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ 818 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 819 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 820 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ 821 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ 822 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ 823 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 824 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 825 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ 826 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ 827 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ 828 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 829 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 830 #define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ 831 #define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ 832 #define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ 833 #define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 834 #define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 835 #define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ 836 #define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ 837 #define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ 838 #define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 839 #define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 840 841 /* Bit fields for CMU CMD */ 842 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ 843 #define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */ 844 #define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */ 845 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */ 846 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 847 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */ 848 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */ 849 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */ 850 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */ 851 #define _CMU_CMD_HFCLKSEL_USHFRCODIV2 0x00000005UL /**< Mode USHFRCODIV2 for CMU_CMD */ 852 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ 853 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */ 854 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */ 855 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */ 856 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */ 857 #define CMU_CMD_HFCLKSEL_USHFRCODIV2 (_CMU_CMD_HFCLKSEL_USHFRCODIV2 << 0) /**< Shifted mode USHFRCODIV2 for CMU_CMD */ 858 #define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */ 859 #define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */ 860 #define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */ 861 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 862 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */ 863 #define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */ 864 #define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */ 865 #define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */ 866 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 867 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ 868 869 /* Bit fields for CMU LFCLKSEL */ 870 #define _CMU_LFCLKSEL_RESETVALUE 0x00000015UL /**< Default value for CMU_LFCLKSEL */ 871 #define _CMU_LFCLKSEL_MASK 0x0011003FUL /**< Mask for CMU_LFCLKSEL */ 872 #define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ 873 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */ 874 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ 875 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */ 876 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */ 877 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */ 878 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ 879 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ 880 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ 881 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */ 882 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */ 883 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ 884 #define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */ 885 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */ 886 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ 887 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */ 888 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */ 889 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */ 890 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ 891 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ 892 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ 893 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */ 894 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */ 895 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */ 896 #define _CMU_LFCLKSEL_LFC_SHIFT 4 /**< Shift value for CMU_LFC */ 897 #define _CMU_LFCLKSEL_LFC_MASK 0x30UL /**< Bit mask for CMU_LFC */ 898 #define _CMU_LFCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ 899 #define _CMU_LFCLKSEL_LFC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */ 900 #define _CMU_LFCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */ 901 #define _CMU_LFCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */ 902 #define CMU_LFCLKSEL_LFC_DISABLED (_CMU_LFCLKSEL_LFC_DISABLED << 4) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ 903 #define CMU_LFCLKSEL_LFC_DEFAULT (_CMU_LFCLKSEL_LFC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ 904 #define CMU_LFCLKSEL_LFC_LFRCO (_CMU_LFCLKSEL_LFC_LFRCO << 4) /**< Shifted mode LFRCO for CMU_LFCLKSEL */ 905 #define CMU_LFCLKSEL_LFC_LFXO (_CMU_LFCLKSEL_LFC_LFXO << 4) /**< Shifted mode LFXO for CMU_LFCLKSEL */ 906 #define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */ 907 #define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */ 908 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */ 909 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */ 910 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ 911 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */ 912 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ 913 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ 914 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */ 915 #define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */ 916 #define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */ 917 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */ 918 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */ 919 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */ 920 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */ 921 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */ 922 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */ 923 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */ 924 925 /* Bit fields for CMU STATUS */ 926 #define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */ 927 #define _CMU_STATUS_MASK 0x04E07FFFUL /**< Mask for CMU_STATUS */ 928 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ 929 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ 930 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ 931 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 932 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ 933 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ 934 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ 935 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ 936 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 937 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ 938 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ 939 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ 940 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ 941 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 942 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ 943 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ 944 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ 945 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ 946 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 947 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ 948 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ 949 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ 950 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ 951 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 952 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ 953 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ 954 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ 955 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ 956 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 957 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ 958 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ 959 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ 960 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ 961 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 962 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ 963 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ 964 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ 965 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ 966 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 967 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ 968 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ 969 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ 970 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ 971 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 972 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ 973 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ 974 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ 975 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ 976 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 977 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ 978 #define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */ 979 #define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */ 980 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */ 981 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 982 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ 983 #define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */ 984 #define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */ 985 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */ 986 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 987 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ 988 #define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */ 989 #define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */ 990 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */ 991 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 992 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ 993 #define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */ 994 #define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */ 995 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */ 996 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 997 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ 998 #define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */ 999 #define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */ 1000 #define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */ 1001 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1002 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */ 1003 #define CMU_STATUS_USHFRCOENS (0x1UL << 21) /**< USHFRCO Enable Status */ 1004 #define _CMU_STATUS_USHFRCOENS_SHIFT 21 /**< Shift value for CMU_USHFRCOENS */ 1005 #define _CMU_STATUS_USHFRCOENS_MASK 0x200000UL /**< Bit mask for CMU_USHFRCOENS */ 1006 #define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1007 #define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */ 1008 #define CMU_STATUS_USHFRCORDY (0x1UL << 22) /**< USHFRCO Ready */ 1009 #define _CMU_STATUS_USHFRCORDY_SHIFT 22 /**< Shift value for CMU_USHFRCORDY */ 1010 #define _CMU_STATUS_USHFRCORDY_MASK 0x400000UL /**< Bit mask for CMU_USHFRCORDY */ 1011 #define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1012 #define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ 1013 #define CMU_STATUS_USHFRCOSUSPEND (0x1UL << 23) /**< USHFRCO is suspended */ 1014 #define _CMU_STATUS_USHFRCOSUSPEND_SHIFT 23 /**< Shift value for CMU_USHFRCOSUSPEND */ 1015 #define _CMU_STATUS_USHFRCOSUSPEND_MASK 0x800000UL /**< Bit mask for CMU_USHFRCOSUSPEND */ 1016 #define _CMU_STATUS_USHFRCOSUSPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1017 #define CMU_STATUS_USHFRCOSUSPEND_DEFAULT (_CMU_STATUS_USHFRCOSUSPEND_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */ 1018 #define CMU_STATUS_USHFRCODIV2SEL (0x1UL << 26) /**< USHFRCODIV2 Selected */ 1019 #define _CMU_STATUS_USHFRCODIV2SEL_SHIFT 26 /**< Shift value for CMU_USHFRCODIV2SEL */ 1020 #define _CMU_STATUS_USHFRCODIV2SEL_MASK 0x4000000UL /**< Bit mask for CMU_USHFRCODIV2SEL */ 1021 #define _CMU_STATUS_USHFRCODIV2SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1022 #define CMU_STATUS_USHFRCODIV2SEL_DEFAULT (_CMU_STATUS_USHFRCODIV2SEL_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_STATUS */ 1023 1024 /* Bit fields for CMU IF */ 1025 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ 1026 #define _CMU_IF_MASK 0x0000017FUL /**< Mask for CMU_IF */ 1027 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ 1028 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1029 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1030 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ 1031 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ 1032 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ 1033 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1034 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1035 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1036 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ 1037 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ 1038 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1039 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1040 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1041 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ 1042 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ 1043 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1044 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1045 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1046 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ 1047 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ 1048 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1049 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1050 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1051 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ 1052 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ 1053 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1054 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1055 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1056 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ 1057 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ 1058 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1059 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1060 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1061 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ 1062 #define CMU_IF_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Flag */ 1063 #define _CMU_IF_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */ 1064 #define _CMU_IF_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */ 1065 #define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1066 #define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ 1067 1068 /* Bit fields for CMU IFS */ 1069 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ 1070 #define _CMU_IFS_MASK 0x0000017FUL /**< Mask for CMU_IFS */ 1071 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */ 1072 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1073 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1074 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1075 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ 1076 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */ 1077 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1078 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1079 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1080 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ 1081 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */ 1082 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1083 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1084 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1085 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ 1086 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */ 1087 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1088 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1089 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1090 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ 1091 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */ 1092 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1093 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1094 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1095 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ 1096 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */ 1097 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1098 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1099 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1100 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ 1101 #define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */ 1102 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1103 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1104 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1105 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ 1106 #define CMU_IFS_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Flag Set */ 1107 #define _CMU_IFS_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */ 1108 #define _CMU_IFS_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */ 1109 #define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1110 #define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ 1111 1112 /* Bit fields for CMU IFC */ 1113 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ 1114 #define _CMU_IFC_MASK 0x0000017FUL /**< Mask for CMU_IFC */ 1115 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */ 1116 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1117 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1118 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1119 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ 1120 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */ 1121 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1122 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1123 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1124 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ 1125 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */ 1126 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1127 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1128 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1129 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ 1130 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */ 1131 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1132 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1133 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1134 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ 1135 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */ 1136 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1137 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1138 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1139 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ 1140 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */ 1141 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1142 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1143 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1144 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ 1145 #define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */ 1146 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1147 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1148 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1149 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ 1150 #define CMU_IFC_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Flag Clear */ 1151 #define _CMU_IFC_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */ 1152 #define _CMU_IFC_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */ 1153 #define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1154 #define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ 1155 1156 /* Bit fields for CMU IEN */ 1157 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ 1158 #define _CMU_IEN_MASK 0x0000017FUL /**< Mask for CMU_IEN */ 1159 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */ 1160 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1161 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1162 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1163 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ 1164 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */ 1165 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1166 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1167 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1168 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ 1169 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */ 1170 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1171 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1172 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1173 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ 1174 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */ 1175 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1176 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1177 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1178 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ 1179 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */ 1180 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1181 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1182 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1183 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ 1184 #define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */ 1185 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1186 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1187 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1188 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ 1189 #define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */ 1190 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1191 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1192 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1193 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ 1194 #define CMU_IEN_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Enable */ 1195 #define _CMU_IEN_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */ 1196 #define _CMU_IEN_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */ 1197 #define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1198 #define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ 1199 1200 /* Bit fields for CMU HFCORECLKEN0 */ 1201 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */ 1202 #define _CMU_HFCORECLKEN0_MASK 0x00000007UL /**< Mask for CMU_HFCORECLKEN0 */ 1203 #define CMU_HFCORECLKEN0_AES (0x1UL << 0) /**< Advanced Encryption Standard Accelerator Clock Enable */ 1204 #define _CMU_HFCORECLKEN0_AES_SHIFT 0 /**< Shift value for CMU_AES */ 1205 #define _CMU_HFCORECLKEN0_AES_MASK 0x1UL /**< Bit mask for CMU_AES */ 1206 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ 1207 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ 1208 #define CMU_HFCORECLKEN0_DMA (0x1UL << 1) /**< Direct Memory Access Controller Clock Enable */ 1209 #define _CMU_HFCORECLKEN0_DMA_SHIFT 1 /**< Shift value for CMU_DMA */ 1210 #define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL /**< Bit mask for CMU_DMA */ 1211 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ 1212 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ 1213 #define CMU_HFCORECLKEN0_LE (0x1UL << 2) /**< Low Energy Peripheral Interface Clock Enable */ 1214 #define _CMU_HFCORECLKEN0_LE_SHIFT 2 /**< Shift value for CMU_LE */ 1215 #define _CMU_HFCORECLKEN0_LE_MASK 0x4UL /**< Bit mask for CMU_LE */ 1216 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */ 1217 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */ 1218 1219 /* Bit fields for CMU HFPERCLKEN0 */ 1220 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ 1221 #define _CMU_HFPERCLKEN0_MASK 0x00000FFFUL /**< Mask for CMU_HFPERCLKEN0 */ 1222 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */ 1223 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */ 1224 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */ 1225 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1226 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1227 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */ 1228 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */ 1229 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */ 1230 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1231 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1232 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */ 1233 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */ 1234 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */ 1235 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1236 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1237 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 3) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ 1238 #define _CMU_HFPERCLKEN0_USART0_SHIFT 3 /**< Shift value for CMU_USART0 */ 1239 #define _CMU_HFPERCLKEN0_USART0_MASK 0x8UL /**< Bit mask for CMU_USART0 */ 1240 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1241 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1242 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 4) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ 1243 #define _CMU_HFPERCLKEN0_USART1_SHIFT 4 /**< Shift value for CMU_USART1 */ 1244 #define _CMU_HFPERCLKEN0_USART1_MASK 0x10UL /**< Bit mask for CMU_USART1 */ 1245 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1246 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1247 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 5) /**< Analog Comparator 0 Clock Enable */ 1248 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 5 /**< Shift value for CMU_ACMP0 */ 1249 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x20UL /**< Bit mask for CMU_ACMP0 */ 1250 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1251 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1252 #define CMU_HFPERCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */ 1253 #define _CMU_HFPERCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */ 1254 #define _CMU_HFPERCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */ 1255 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1256 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1257 #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 7) /**< Current Digital to Analog Converter 0 Clock Enable */ 1258 #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 7 /**< Shift value for CMU_IDAC0 */ 1259 #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x80UL /**< Bit mask for CMU_IDAC0 */ 1260 #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1261 #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1262 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 8) /**< General purpose Input/Output Clock Enable */ 1263 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 8 /**< Shift value for CMU_GPIO */ 1264 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x100UL /**< Bit mask for CMU_GPIO */ 1265 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1266 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1267 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 9) /**< Voltage Comparator Clock Enable */ 1268 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 9 /**< Shift value for CMU_VCMP */ 1269 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x200UL /**< Bit mask for CMU_VCMP */ 1270 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1271 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1272 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 10) /**< Analog to Digital Converter 0 Clock Enable */ 1273 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 10 /**< Shift value for CMU_ADC0 */ 1274 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x400UL /**< Bit mask for CMU_ADC0 */ 1275 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1276 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1277 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */ 1278 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */ 1279 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */ 1280 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1281 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1282 1283 /* Bit fields for CMU SYNCBUSY */ 1284 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ 1285 #define _CMU_SYNCBUSY_MASK 0x00000155UL /**< Mask for CMU_SYNCBUSY */ 1286 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */ 1287 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ 1288 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ 1289 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1290 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1291 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */ 1292 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ 1293 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ 1294 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1295 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1296 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ 1297 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ 1298 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ 1299 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1300 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1301 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ 1302 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ 1303 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ 1304 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1305 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1306 #define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ 1307 #define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ 1308 #define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ 1309 #define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 1310 #define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 1311 1312 /* Bit fields for CMU FREEZE */ 1313 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ 1314 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ 1315 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ 1316 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ 1317 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ 1318 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ 1319 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ 1320 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ 1321 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ 1322 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ 1323 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ 1324 1325 /* Bit fields for CMU LFACLKEN0 */ 1326 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ 1327 #define _CMU_LFACLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFACLKEN0 */ 1328 #define CMU_LFACLKEN0_RTC (0x1UL << 0) /**< Real-Time Counter Clock Enable */ 1329 #define _CMU_LFACLKEN0_RTC_SHIFT 0 /**< Shift value for CMU_RTC */ 1330 #define _CMU_LFACLKEN0_RTC_MASK 0x1UL /**< Bit mask for CMU_RTC */ 1331 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 1332 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 1333 1334 /* Bit fields for CMU LFBCLKEN0 */ 1335 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ 1336 #define _CMU_LFBCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFBCLKEN0 */ 1337 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ 1338 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ 1339 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ 1340 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 1341 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 1342 1343 /* Bit fields for CMU LFCCLKEN0 */ 1344 #define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ 1345 #define _CMU_LFCCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFCCLKEN0 */ 1346 #define CMU_LFCCLKEN0_USBLE (0x1UL << 0) /**< Universal Serial Bus Low Energy Clock Clock Enable */ 1347 #define _CMU_LFCCLKEN0_USBLE_SHIFT 0 /**< Shift value for CMU_USBLE */ 1348 #define _CMU_LFCCLKEN0_USBLE_MASK 0x1UL /**< Bit mask for CMU_USBLE */ 1349 #define _CMU_LFCCLKEN0_USBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKEN0 */ 1350 #define CMU_LFCCLKEN0_USBLE_DEFAULT (_CMU_LFCCLKEN0_USBLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKEN0 */ 1351 1352 /* Bit fields for CMU LFAPRESC0 */ 1353 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ 1354 #define _CMU_LFAPRESC0_MASK 0x0000000FUL /**< Mask for CMU_LFAPRESC0 */ 1355 #define _CMU_LFAPRESC0_RTC_SHIFT 0 /**< Shift value for CMU_RTC */ 1356 #define _CMU_LFAPRESC0_RTC_MASK 0xFUL /**< Bit mask for CMU_RTC */ 1357 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 1358 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 1359 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 1360 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 1361 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ 1362 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ 1363 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ 1364 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ 1365 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ 1366 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ 1367 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ 1368 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ 1369 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ 1370 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ 1371 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ 1372 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ 1373 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 1374 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 1375 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 1376 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 1377 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ 1378 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ 1379 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ 1380 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ 1381 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ 1382 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ 1383 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ 1384 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ 1385 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ 1386 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ 1387 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ 1388 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ 1389 1390 /* Bit fields for CMU LFBPRESC0 */ 1391 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ 1392 #define _CMU_LFBPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFBPRESC0 */ 1393 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ 1394 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ 1395 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ 1396 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ 1397 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ 1398 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ 1399 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ 1400 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ 1401 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ 1402 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ 1403 1404 /* Bit fields for CMU PCNTCTRL */ 1405 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ 1406 #define _CMU_PCNTCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNTCTRL */ 1407 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ 1408 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ 1409 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ 1410 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 1411 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 1412 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ 1413 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ 1414 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ 1415 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 1416 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ 1417 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ 1418 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 1419 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ 1420 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ 1421 1422 /* Bit fields for CMU ROUTE */ 1423 #define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */ 1424 #define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */ 1425 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ 1426 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ 1427 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ 1428 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */ 1429 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */ 1430 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ 1431 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ 1432 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ 1433 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */ 1434 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */ 1435 #define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */ 1436 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */ 1437 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */ 1438 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */ 1439 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */ 1440 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */ 1441 #define _CMU_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTE */ 1442 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */ 1443 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */ 1444 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */ 1445 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */ 1446 #define CMU_ROUTE_LOCATION_LOC3 (_CMU_ROUTE_LOCATION_LOC3 << 2) /**< Shifted mode LOC3 for CMU_ROUTE */ 1447 1448 /* Bit fields for CMU LOCK */ 1449 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ 1450 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ 1451 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ 1452 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ 1453 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ 1454 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ 1455 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ 1456 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ 1457 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ 1458 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ 1459 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ 1460 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ 1461 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ 1462 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ 1463 1464 /* Bit fields for CMU USBCRCTRL */ 1465 #define _CMU_USBCRCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_USBCRCTRL */ 1466 #define _CMU_USBCRCTRL_MASK 0x00000003UL /**< Mask for CMU_USBCRCTRL */ 1467 #define CMU_USBCRCTRL_EN (0x1UL << 0) /**< Clock Recovery Enable */ 1468 #define _CMU_USBCRCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ 1469 #define _CMU_USBCRCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ 1470 #define _CMU_USBCRCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCRCTRL */ 1471 #define CMU_USBCRCTRL_EN_DEFAULT (_CMU_USBCRCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USBCRCTRL */ 1472 #define CMU_USBCRCTRL_LSMODE (0x1UL << 1) /**< Low Speed Clock Recovery Mode */ 1473 #define _CMU_USBCRCTRL_LSMODE_SHIFT 1 /**< Shift value for CMU_LSMODE */ 1474 #define _CMU_USBCRCTRL_LSMODE_MASK 0x2UL /**< Bit mask for CMU_LSMODE */ 1475 #define _CMU_USBCRCTRL_LSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCRCTRL */ 1476 #define CMU_USBCRCTRL_LSMODE_DEFAULT (_CMU_USBCRCTRL_LSMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_USBCRCTRL */ 1477 1478 /* Bit fields for CMU USHFRCOCTRL */ 1479 #define _CMU_USHFRCOCTRL_RESETVALUE 0x000FF040UL /**< Default value for CMU_USHFRCOCTRL */ 1480 #define _CMU_USHFRCOCTRL_MASK 0x000FF37FUL /**< Mask for CMU_USHFRCOCTRL */ 1481 #define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 1482 #define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 1483 #define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 1484 #define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 1485 #define CMU_USHFRCOCTRL_DITHEN (0x1UL << 8) /**< USHFRCO dither enable */ 1486 #define _CMU_USHFRCOCTRL_DITHEN_SHIFT 8 /**< Shift value for CMU_DITHEN */ 1487 #define _CMU_USHFRCOCTRL_DITHEN_MASK 0x100UL /**< Bit mask for CMU_DITHEN */ 1488 #define _CMU_USHFRCOCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 1489 #define CMU_USHFRCOCTRL_DITHEN_DEFAULT (_CMU_USHFRCOCTRL_DITHEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 1490 #define CMU_USHFRCOCTRL_SUSPEND (0x1UL << 9) /**< USHFRCO suspend */ 1491 #define _CMU_USHFRCOCTRL_SUSPEND_SHIFT 9 /**< Shift value for CMU_SUSPEND */ 1492 #define _CMU_USHFRCOCTRL_SUSPEND_MASK 0x200UL /**< Bit mask for CMU_SUSPEND */ 1493 #define _CMU_USHFRCOCTRL_SUSPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 1494 #define CMU_USHFRCOCTRL_SUSPEND_DEFAULT (_CMU_USHFRCOCTRL_SUSPEND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 1495 #define _CMU_USHFRCOCTRL_TIMEOUT_SHIFT 12 /**< Shift value for CMU_TIMEOUT */ 1496 #define _CMU_USHFRCOCTRL_TIMEOUT_MASK 0xFF000UL /**< Bit mask for CMU_TIMEOUT */ 1497 #define _CMU_USHFRCOCTRL_TIMEOUT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 1498 #define CMU_USHFRCOCTRL_TIMEOUT_DEFAULT (_CMU_USHFRCOCTRL_TIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 1499 1500 /* Bit fields for CMU USHFRCOTUNE */ 1501 #define _CMU_USHFRCOTUNE_RESETVALUE 0x00000020UL /**< Default value for CMU_USHFRCOTUNE */ 1502 #define _CMU_USHFRCOTUNE_MASK 0x0000003FUL /**< Mask for CMU_USHFRCOTUNE */ 1503 #define _CMU_USHFRCOTUNE_FINETUNING_SHIFT 0 /**< Shift value for CMU_FINETUNING */ 1504 #define _CMU_USHFRCOTUNE_FINETUNING_MASK 0x3FUL /**< Bit mask for CMU_FINETUNING */ 1505 #define _CMU_USHFRCOTUNE_FINETUNING_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_USHFRCOTUNE */ 1506 #define CMU_USHFRCOTUNE_FINETUNING_DEFAULT (_CMU_USHFRCOTUNE_FINETUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOTUNE */ 1507 1508 /* Bit fields for CMU USHFRCOCONF */ 1509 #define _CMU_USHFRCOCONF_RESETVALUE 0x00000001UL /**< Default value for CMU_USHFRCOCONF */ 1510 #define _CMU_USHFRCOCONF_MASK 0x00000017UL /**< Mask for CMU_USHFRCOCONF */ 1511 #define _CMU_USHFRCOCONF_BAND_SHIFT 0 /**< Shift value for CMU_BAND */ 1512 #define _CMU_USHFRCOCONF_BAND_MASK 0x7UL /**< Bit mask for CMU_BAND */ 1513 #define _CMU_USHFRCOCONF_BAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCONF */ 1514 #define _CMU_USHFRCOCONF_BAND_48MHZ 0x00000001UL /**< Mode 48MHZ for CMU_USHFRCOCONF */ 1515 #define _CMU_USHFRCOCONF_BAND_24MHZ 0x00000003UL /**< Mode 24MHZ for CMU_USHFRCOCONF */ 1516 #define CMU_USHFRCOCONF_BAND_DEFAULT (_CMU_USHFRCOCONF_BAND_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCONF */ 1517 #define CMU_USHFRCOCONF_BAND_48MHZ (_CMU_USHFRCOCONF_BAND_48MHZ << 0) /**< Shifted mode 48MHZ for CMU_USHFRCOCONF */ 1518 #define CMU_USHFRCOCONF_BAND_24MHZ (_CMU_USHFRCOCONF_BAND_24MHZ << 0) /**< Shifted mode 24MHZ for CMU_USHFRCOCONF */ 1519 #define CMU_USHFRCOCONF_USHFRCODIV2DIS (0x1UL << 4) /**< USHFRCO divider for HFCLK disable */ 1520 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT 4 /**< Shift value for CMU_USHFRCODIV2DIS */ 1521 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_MASK 0x10UL /**< Bit mask for CMU_USHFRCODIV2DIS */ 1522 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCONF */ 1523 #define CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT (_CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_USHFRCOCONF */ 1524 1525 /** @} End of group EFM32HG222F64_CMU */ 1526 1527 /***************************************************************************//** 1528 * @defgroup EFM32HG222F64_PRS_BitFields EFM32HG222F64_PRS Bit Fields 1529 * @{ 1530 ******************************************************************************/ 1531 1532 /* Bit fields for PRS SWPULSE */ 1533 #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ 1534 #define _PRS_SWPULSE_MASK 0x0000003FUL /**< Mask for PRS_SWPULSE */ 1535 #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ 1536 #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ 1537 #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ 1538 #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1539 #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1540 #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ 1541 #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ 1542 #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ 1543 #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1544 #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1545 #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ 1546 #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ 1547 #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ 1548 #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1549 #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1550 #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ 1551 #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ 1552 #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ 1553 #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1554 #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1555 #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ 1556 #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ 1557 #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ 1558 #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1559 #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1560 #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ 1561 #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ 1562 #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ 1563 #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ 1564 #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ 1565 1566 /* Bit fields for PRS SWLEVEL */ 1567 #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ 1568 #define _PRS_SWLEVEL_MASK 0x0000003FUL /**< Mask for PRS_SWLEVEL */ 1569 #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ 1570 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ 1571 #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ 1572 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1573 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1574 #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ 1575 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ 1576 #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ 1577 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1578 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1579 #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ 1580 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ 1581 #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ 1582 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1583 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1584 #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ 1585 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ 1586 #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ 1587 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1588 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1589 #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ 1590 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ 1591 #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ 1592 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1593 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1594 #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ 1595 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ 1596 #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ 1597 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ 1598 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ 1599 1600 /* Bit fields for PRS ROUTE */ 1601 #define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */ 1602 #define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */ 1603 #define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ 1604 #define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ 1605 #define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ 1606 #define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ 1607 #define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */ 1608 #define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ 1609 #define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ 1610 #define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ 1611 #define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ 1612 #define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */ 1613 #define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ 1614 #define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ 1615 #define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ 1616 #define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ 1617 #define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */ 1618 #define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ 1619 #define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ 1620 #define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ 1621 #define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ 1622 #define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */ 1623 #define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */ 1624 #define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */ 1625 #define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */ 1626 #define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ 1627 #define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */ 1628 #define _PRS_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTE */ 1629 #define _PRS_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTE */ 1630 #define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */ 1631 #define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */ 1632 #define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */ 1633 #define PRS_ROUTE_LOCATION_LOC2 (_PRS_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTE */ 1634 #define PRS_ROUTE_LOCATION_LOC3 (_PRS_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTE */ 1635 1636 /* Bit fields for PRS CH_CTRL */ 1637 #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ 1638 #define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */ 1639 #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ 1640 #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ 1641 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */ 1642 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ 1643 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ 1644 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ 1645 #define _PRS_CH_CTRL_SIGSEL_USART1IRTX 0x00000000UL /**< Mode USART1IRTX for PRS_CH_CTRL */ 1646 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ 1647 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ 1648 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ 1649 #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ 1650 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ 1651 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ 1652 #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ 1653 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ 1654 #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ 1655 #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ 1656 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ 1657 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ 1658 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ 1659 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ 1660 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ 1661 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ 1662 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ 1663 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ 1664 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ 1665 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ 1666 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ 1667 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ 1668 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ 1669 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ 1670 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ 1671 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ 1672 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ 1673 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ 1674 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ 1675 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ 1676 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ 1677 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ 1678 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ 1679 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ 1680 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ 1681 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ 1682 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ 1683 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ 1684 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ 1685 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ 1686 #define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */ 1687 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ 1688 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ 1689 #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ 1690 #define PRS_CH_CTRL_SIGSEL_USART1IRTX (_PRS_CH_CTRL_SIGSEL_USART1IRTX << 0) /**< Shifted mode USART1IRTX for PRS_CH_CTRL */ 1691 #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ 1692 #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ 1693 #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ 1694 #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ 1695 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ 1696 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ 1697 #define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ 1698 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ 1699 #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ 1700 #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ 1701 #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ 1702 #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ 1703 #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ 1704 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ 1705 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ 1706 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ 1707 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ 1708 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ 1709 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ 1710 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ 1711 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ 1712 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ 1713 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ 1714 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ 1715 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ 1716 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ 1717 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ 1718 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ 1719 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ 1720 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ 1721 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ 1722 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ 1723 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ 1724 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ 1725 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ 1726 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ 1727 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ 1728 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ 1729 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ 1730 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ 1731 #define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */ 1732 #define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */ 1733 #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ 1734 #define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */ 1735 #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */ 1736 #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */ 1737 #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */ 1738 #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */ 1739 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */ 1740 #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */ 1741 #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */ 1742 #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */ 1743 #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */ 1744 #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */ 1745 #define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x00000036UL /**< Mode PCNT0 for PRS_CH_CTRL */ 1746 #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */ 1747 #define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */ 1748 #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ 1749 #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */ 1750 #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */ 1751 #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */ 1752 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ 1753 #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ 1754 #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ 1755 #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */ 1756 #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */ 1757 #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */ 1758 #define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 16) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ 1759 #define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */ 1760 #define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */ 1761 #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 1762 #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ 1763 #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ 1764 #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ 1765 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ 1766 #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 1767 #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */ 1768 #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ 1769 #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ 1770 #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ 1771 #define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */ 1772 #define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */ 1773 #define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */ 1774 #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ 1775 #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ 1776 1777 /* Bit fields for PRS TRACECTRL */ 1778 #define _PRS_TRACECTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_TRACECTRL */ 1779 #define _PRS_TRACECTRL_MASK 0x00000F0FUL /**< Mask for PRS_TRACECTRL */ 1780 #define PRS_TRACECTRL_TSTARTEN (0x1UL << 0) /**< PRS TSTART Enable */ 1781 #define _PRS_TRACECTRL_TSTARTEN_SHIFT 0 /**< Shift value for PRS_TSTARTEN */ 1782 #define _PRS_TRACECTRL_TSTARTEN_MASK 0x1UL /**< Bit mask for PRS_TSTARTEN */ 1783 #define _PRS_TRACECTRL_TSTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */ 1784 #define PRS_TRACECTRL_TSTARTEN_DEFAULT (_PRS_TRACECTRL_TSTARTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_TRACECTRL */ 1785 #define _PRS_TRACECTRL_TSTART_SHIFT 1 /**< Shift value for PRS_TSTART */ 1786 #define _PRS_TRACECTRL_TSTART_MASK 0xEUL /**< Bit mask for PRS_TSTART */ 1787 #define _PRS_TRACECTRL_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */ 1788 #define _PRS_TRACECTRL_TSTART_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_TRACECTRL */ 1789 #define _PRS_TRACECTRL_TSTART_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_TRACECTRL */ 1790 #define _PRS_TRACECTRL_TSTART_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_TRACECTRL */ 1791 #define _PRS_TRACECTRL_TSTART_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_TRACECTRL */ 1792 #define _PRS_TRACECTRL_TSTART_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_TRACECTRL */ 1793 #define _PRS_TRACECTRL_TSTART_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_TRACECTRL */ 1794 #define PRS_TRACECTRL_TSTART_DEFAULT (_PRS_TRACECTRL_TSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_TRACECTRL */ 1795 #define PRS_TRACECTRL_TSTART_PRSCH0 (_PRS_TRACECTRL_TSTART_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_TRACECTRL */ 1796 #define PRS_TRACECTRL_TSTART_PRSCH1 (_PRS_TRACECTRL_TSTART_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_TRACECTRL */ 1797 #define PRS_TRACECTRL_TSTART_PRSCH2 (_PRS_TRACECTRL_TSTART_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_TRACECTRL */ 1798 #define PRS_TRACECTRL_TSTART_PRSCH3 (_PRS_TRACECTRL_TSTART_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_TRACECTRL */ 1799 #define PRS_TRACECTRL_TSTART_PRSCH4 (_PRS_TRACECTRL_TSTART_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_TRACECTRL */ 1800 #define PRS_TRACECTRL_TSTART_PRSCH5 (_PRS_TRACECTRL_TSTART_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_TRACECTRL */ 1801 #define PRS_TRACECTRL_TSTOPEN (0x1UL << 8) /**< PRS TSTOP Enable */ 1802 #define _PRS_TRACECTRL_TSTOPEN_SHIFT 8 /**< Shift value for PRS_TSTOPEN */ 1803 #define _PRS_TRACECTRL_TSTOPEN_MASK 0x100UL /**< Bit mask for PRS_TSTOPEN */ 1804 #define _PRS_TRACECTRL_TSTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */ 1805 #define PRS_TRACECTRL_TSTOPEN_DEFAULT (_PRS_TRACECTRL_TSTOPEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_TRACECTRL */ 1806 #define _PRS_TRACECTRL_TSTOP_SHIFT 9 /**< Shift value for PRS_TSTOP */ 1807 #define _PRS_TRACECTRL_TSTOP_MASK 0xE00UL /**< Bit mask for PRS_TSTOP */ 1808 #define _PRS_TRACECTRL_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */ 1809 #define _PRS_TRACECTRL_TSTOP_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_TRACECTRL */ 1810 #define _PRS_TRACECTRL_TSTOP_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_TRACECTRL */ 1811 #define _PRS_TRACECTRL_TSTOP_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_TRACECTRL */ 1812 #define _PRS_TRACECTRL_TSTOP_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_TRACECTRL */ 1813 #define _PRS_TRACECTRL_TSTOP_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_TRACECTRL */ 1814 #define _PRS_TRACECTRL_TSTOP_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_TRACECTRL */ 1815 #define PRS_TRACECTRL_TSTOP_DEFAULT (_PRS_TRACECTRL_TSTOP_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_TRACECTRL */ 1816 #define PRS_TRACECTRL_TSTOP_PRSCH0 (_PRS_TRACECTRL_TSTOP_PRSCH0 << 9) /**< Shifted mode PRSCH0 for PRS_TRACECTRL */ 1817 #define PRS_TRACECTRL_TSTOP_PRSCH1 (_PRS_TRACECTRL_TSTOP_PRSCH1 << 9) /**< Shifted mode PRSCH1 for PRS_TRACECTRL */ 1818 #define PRS_TRACECTRL_TSTOP_PRSCH2 (_PRS_TRACECTRL_TSTOP_PRSCH2 << 9) /**< Shifted mode PRSCH2 for PRS_TRACECTRL */ 1819 #define PRS_TRACECTRL_TSTOP_PRSCH3 (_PRS_TRACECTRL_TSTOP_PRSCH3 << 9) /**< Shifted mode PRSCH3 for PRS_TRACECTRL */ 1820 #define PRS_TRACECTRL_TSTOP_PRSCH4 (_PRS_TRACECTRL_TSTOP_PRSCH4 << 9) /**< Shifted mode PRSCH4 for PRS_TRACECTRL */ 1821 #define PRS_TRACECTRL_TSTOP_PRSCH5 (_PRS_TRACECTRL_TSTOP_PRSCH5 << 9) /**< Shifted mode PRSCH5 for PRS_TRACECTRL */ 1822 1823 /** @} End of group EFM32HG222F64_PRS */ 1824 1825 /***************************************************************************//** 1826 * @defgroup EFM32HG222F64_UNLOCK EFM32HG222F64 Unlock Codes 1827 * @{ 1828 ******************************************************************************/ 1829 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ 1830 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ 1831 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ 1832 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ 1833 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ 1834 1835 /** @} End of group EFM32HG222F64_UNLOCK */ 1836 1837 /** @} End of group EFM32HG222F64_BitFields */ 1838 1839 /***************************************************************************//** 1840 * @defgroup EFM32HG222F64_Alternate_Function EFM32HG222F64 Alternate Function 1841 * @{ 1842 ******************************************************************************/ 1843 1844 #include "efm32hg_af_ports.h" 1845 #include "efm32hg_af_pins.h" 1846 1847 /** @} End of group EFM32HG222F64_Alternate_Function */ 1848 1849 /***************************************************************************//** 1850 * @brief Set the value of a bit field within a register. 1851 * 1852 * @param REG 1853 * The register to update 1854 * @param MASK 1855 * The mask for the bit field to update 1856 * @param VALUE 1857 * The value to write to the bit field 1858 * @param OFFSET 1859 * The number of bits that the field is offset within the register. 1860 * 0 (zero) means LSB. 1861 ******************************************************************************/ 1862 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ 1863 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); 1864 1865 /** @} End of group EFM32HG222F64 */ 1866 1867 /** @} End of group Parts */ 1868 1869 #ifdef __cplusplus 1870 } 1871 #endif 1872 #endif /* EFM32HG222F64_H */ 1873
