1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG12B_CMU register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG12B_CMU CMU 43 * @{ 44 * @brief EFM32GG12B_CMU Register Declaration 45 ******************************************************************************/ 46 /** CMU Register Declaration */ 47 typedef struct { 48 __IOM uint32_t CTRL; /**< CMU Control Register */ 49 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 50 __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control Register */ 51 52 uint32_t RESERVED1[1U]; /**< Reserved for future use **/ 53 __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */ 54 55 uint32_t RESERVED2[1U]; /**< Reserved for future use **/ 56 __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */ 57 58 uint32_t RESERVED3[1U]; /**< Reserved for future use **/ 59 __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */ 60 __IOM uint32_t HFXOCTRL; /**< HFXO Control Register */ 61 __IOM uint32_t HFXOCTRL1; /**< HFXO Control 1 */ 62 __IOM uint32_t HFXOSTARTUPCTRL; /**< HFXO Startup Control */ 63 __IOM uint32_t HFXOSTEADYSTATECTRL; /**< HFXO Steady State Control */ 64 __IOM uint32_t HFXOTIMEOUTCTRL; /**< HFXO Timeout Control */ 65 __IOM uint32_t LFXOCTRL; /**< LFXO Control Register */ 66 67 uint32_t RESERVED4[1U]; /**< Reserved for future use **/ 68 __IOM uint32_t DPLLCTRL; /**< DPLL Control Register */ 69 __IOM uint32_t DPLLCTRL1; /**< DPLL Control Register */ 70 uint32_t RESERVED5[2U]; /**< Reserved for future use **/ 71 __IOM uint32_t CALCTRL; /**< Calibration Control Register */ 72 __IOM uint32_t CALCNT; /**< Calibration Counter Register */ 73 uint32_t RESERVED6[2U]; /**< Reserved for future use **/ 74 __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */ 75 __IOM uint32_t CMD; /**< Command Register */ 76 uint32_t RESERVED7[2U]; /**< Reserved for future use **/ 77 __IOM uint32_t DBGCLKSEL; /**< Debug Trace Clock Select */ 78 __IOM uint32_t HFCLKSEL; /**< High Frequency Clock Select Command Register */ 79 uint32_t RESERVED8[2U]; /**< Reserved for future use **/ 80 __IOM uint32_t LFACLKSEL; /**< Low Frequency A Clock Select Register */ 81 __IOM uint32_t LFBCLKSEL; /**< Low Frequency B Clock Select Register */ 82 __IOM uint32_t LFECLKSEL; /**< Low Frequency E Clock Select Register */ 83 __IOM uint32_t LFCCLKSEL; /**< Low Frequency C Clock Select Register */ 84 __IM uint32_t STATUS; /**< Status Register */ 85 __IM uint32_t HFCLKSTATUS; /**< HFCLK Status Register */ 86 uint32_t RESERVED9[1U]; /**< Reserved for future use **/ 87 __IM uint32_t HFXOTRIMSTATUS; /**< HFXO Trim Status */ 88 __IM uint32_t IF; /**< Interrupt Flag Register */ 89 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 90 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 91 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 92 __IOM uint32_t HFBUSCLKEN0; /**< High Frequency Bus Clock Enable Register 0 */ 93 94 uint32_t RESERVED10[3U]; /**< Reserved for future use **/ 95 __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */ 96 __IOM uint32_t HFPERCLKEN1; /**< High Frequency Peripheral Clock Enable Register 1 */ 97 98 uint32_t RESERVED11[6U]; /**< Reserved for future use **/ 99 __IOM uint32_t LFACLKEN0; /**< Low Frequency a Clock Enable Register 0 (Async Reg) */ 100 uint32_t RESERVED12[1U]; /**< Reserved for future use **/ 101 __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */ 102 __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */ 103 __IOM uint32_t LFECLKEN0; /**< Low Frequency E Clock Enable Register 0 (Async Reg) */ 104 uint32_t RESERVED13[3U]; /**< Reserved for future use **/ 105 __IOM uint32_t HFPRESC; /**< High Frequency Clock Prescaler Register */ 106 __IOM uint32_t HFBUSPRESC; /**< High Frequency Bus Clock Prescaler Register */ 107 __IOM uint32_t HFCOREPRESC; /**< High Frequency Core Clock Prescaler Register */ 108 __IOM uint32_t HFPERPRESC; /**< High Frequency Peripheral Clock Prescaler Register */ 109 110 uint32_t RESERVED14[1U]; /**< Reserved for future use **/ 111 __IOM uint32_t HFEXPPRESC; /**< High Frequency Export Clock Prescaler Register */ 112 __IOM uint32_t HFPERPRESCB; /**< High Frequency Peripheral Clock Prescaler B Register */ 113 __IOM uint32_t HFPERPRESCC; /**< High Frequency Peripheral Clock Prescaler C Register */ 114 __IOM uint32_t LFAPRESC0; /**< Low Frequency a Prescaler Register 0 (Async Reg) */ 115 uint32_t RESERVED15[1U]; /**< Reserved for future use **/ 116 __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */ 117 uint32_t RESERVED16[1U]; /**< Reserved for future use **/ 118 __IOM uint32_t LFEPRESC0; /**< Low Frequency E Prescaler Register 0 (Async Reg) */ 119 120 uint32_t RESERVED17[3U]; /**< Reserved for future use **/ 121 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 122 __IOM uint32_t FREEZE; /**< Freeze Register */ 123 uint32_t RESERVED18[2U]; /**< Reserved for future use **/ 124 __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */ 125 126 uint32_t RESERVED19[2U]; /**< Reserved for future use **/ 127 __IOM uint32_t ADCCTRL; /**< ADC Control Register */ 128 __IOM uint32_t SDIOCTRL; /**< SDIO Control Register */ 129 __IOM uint32_t QSPICTRL; /**< QSPI Control Register */ 130 __IOM uint32_t PDMCTRL; /**< PDM Control Register */ 131 uint32_t RESERVED20[1U]; /**< Reserved for future use **/ 132 __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ 133 __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ 134 __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ 135 uint32_t RESERVED21[1U]; /**< Reserved for future use **/ 136 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 137 __IOM uint32_t HFRCOSS; /**< HFRCO Spread Spectrum Register */ 138 139 uint32_t RESERVED22[26U]; /**< Reserved for future use **/ 140 __IOM uint32_t USBCTRL; /**< USB Control Register */ 141 __IOM uint32_t USBCRCTRL; /**< USB Clock Recovery Control */ 142 } CMU_TypeDef; /** @} */ 143 144 /***************************************************************************//** 145 * @addtogroup EFM32GG12B_CMU 146 * @{ 147 * @defgroup EFM32GG12B_CMU_BitFields CMU Bit Fields 148 * @{ 149 ******************************************************************************/ 150 151 /* Bit fields for CMU CTRL */ 152 #define _CMU_CTRL_RESETVALUE 0x00100000UL /**< Default value for CMU_CTRL */ 153 #define _CMU_CTRL_MASK 0x00117FFFUL /**< Mask for CMU_CTRL */ 154 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ 155 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL /**< Bit mask for CMU_CLKOUTSEL0 */ 156 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 157 #define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ 158 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ 159 #define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ 160 #define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ 161 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ 162 #define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ 163 #define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ 164 #define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ 165 #define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ 166 #define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ 167 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ 168 #define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ 169 #define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ 170 #define _CMU_CTRL_CLKOUTSEL0_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ 171 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */ 172 #define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_CTRL */ 173 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_CTRL */ 174 #define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CTRL */ 175 #define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_CTRL */ 176 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_CTRL */ 177 #define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_CTRL */ 178 #define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0) /**< Shifted mode ULFRCOQ for CMU_CTRL */ 179 #define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0) /**< Shifted mode LFRCOQ for CMU_CTRL */ 180 #define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0) /**< Shifted mode LFXOQ for CMU_CTRL */ 181 #define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0) /**< Shifted mode HFRCOQ for CMU_CTRL */ 182 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ 183 #define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0) /**< Shifted mode HFXOQ for CMU_CTRL */ 184 #define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0) /**< Shifted mode HFSRCCLK for CMU_CTRL */ 185 #define CMU_CTRL_CLKOUTSEL0_USHFRCOQ (_CMU_CTRL_CLKOUTSEL0_USHFRCOQ << 0) /**< Shifted mode USHFRCOQ for CMU_CTRL */ 186 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 5 /**< Shift value for CMU_CLKOUTSEL1 */ 187 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL /**< Bit mask for CMU_CLKOUTSEL1 */ 188 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 189 #define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ 190 #define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ 191 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ 192 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ 193 #define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ 194 #define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ 195 #define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ 196 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ 197 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ 198 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ 199 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ 200 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ 201 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ 202 #define _CMU_CTRL_CLKOUTSEL1_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ 203 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */ 204 #define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5) /**< Shifted mode DISABLED for CMU_CTRL */ 205 #define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5) /**< Shifted mode ULFRCO for CMU_CTRL */ 206 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CTRL */ 207 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5) /**< Shifted mode LFXO for CMU_CTRL */ 208 #define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5) /**< Shifted mode HFXO for CMU_CTRL */ 209 #define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5) /**< Shifted mode HFEXPCLK for CMU_CTRL */ 210 #define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5) /**< Shifted mode ULFRCOQ for CMU_CTRL */ 211 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5) /**< Shifted mode LFRCOQ for CMU_CTRL */ 212 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5) /**< Shifted mode LFXOQ for CMU_CTRL */ 213 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5) /**< Shifted mode HFRCOQ for CMU_CTRL */ 214 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ 215 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5) /**< Shifted mode HFXOQ for CMU_CTRL */ 216 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5) /**< Shifted mode HFSRCCLK for CMU_CTRL */ 217 #define CMU_CTRL_CLKOUTSEL1_USHFRCOQ (_CMU_CTRL_CLKOUTSEL1_USHFRCOQ << 5) /**< Shifted mode USHFRCOQ for CMU_CTRL */ 218 #define _CMU_CTRL_CLKOUTSEL2_SHIFT 10 /**< Shift value for CMU_CLKOUTSEL2 */ 219 #define _CMU_CTRL_CLKOUTSEL2_MASK 0x7C00UL /**< Bit mask for CMU_CLKOUTSEL2 */ 220 #define _CMU_CTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 221 #define _CMU_CTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CTRL */ 222 #define _CMU_CTRL_CLKOUTSEL2_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_CTRL */ 223 #define _CMU_CTRL_CLKOUTSEL2_LFRCO 0x00000002UL /**< Mode LFRCO for CMU_CTRL */ 224 #define _CMU_CTRL_CLKOUTSEL2_LFXO 0x00000003UL /**< Mode LFXO for CMU_CTRL */ 225 #define _CMU_CTRL_CLKOUTSEL2_HFXODIV2Q 0x00000005UL /**< Mode HFXODIV2Q for CMU_CTRL */ 226 #define _CMU_CTRL_CLKOUTSEL2_HFXO 0x00000006UL /**< Mode HFXO for CMU_CTRL */ 227 #define _CMU_CTRL_CLKOUTSEL2_HFEXPCLK 0x00000007UL /**< Mode HFEXPCLK for CMU_CTRL */ 228 #define _CMU_CTRL_CLKOUTSEL2_HFXOX2Q 0x00000008UL /**< Mode HFXOX2Q for CMU_CTRL */ 229 #define _CMU_CTRL_CLKOUTSEL2_ULFRCOQ 0x00000009UL /**< Mode ULFRCOQ for CMU_CTRL */ 230 #define _CMU_CTRL_CLKOUTSEL2_LFRCOQ 0x0000000AUL /**< Mode LFRCOQ for CMU_CTRL */ 231 #define _CMU_CTRL_CLKOUTSEL2_LFXOQ 0x0000000BUL /**< Mode LFXOQ for CMU_CTRL */ 232 #define _CMU_CTRL_CLKOUTSEL2_HFRCOQ 0x0000000CUL /**< Mode HFRCOQ for CMU_CTRL */ 233 #define _CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ 0x0000000DUL /**< Mode AUXHFRCOQ for CMU_CTRL */ 234 #define _CMU_CTRL_CLKOUTSEL2_HFXOQ 0x0000000EUL /**< Mode HFXOQ for CMU_CTRL */ 235 #define _CMU_CTRL_CLKOUTSEL2_HFSRCCLK 0x0000000FUL /**< Mode HFSRCCLK for CMU_CTRL */ 236 #define _CMU_CTRL_CLKOUTSEL2_USHFRCOQ 0x00000012UL /**< Mode USHFRCOQ for CMU_CTRL */ 237 #define CMU_CTRL_CLKOUTSEL2_DEFAULT (_CMU_CTRL_CLKOUTSEL2_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CTRL */ 238 #define CMU_CTRL_CLKOUTSEL2_DISABLED (_CMU_CTRL_CLKOUTSEL2_DISABLED << 10) /**< Shifted mode DISABLED for CMU_CTRL */ 239 #define CMU_CTRL_CLKOUTSEL2_ULFRCO (_CMU_CTRL_CLKOUTSEL2_ULFRCO << 10) /**< Shifted mode ULFRCO for CMU_CTRL */ 240 #define CMU_CTRL_CLKOUTSEL2_LFRCO (_CMU_CTRL_CLKOUTSEL2_LFRCO << 10) /**< Shifted mode LFRCO for CMU_CTRL */ 241 #define CMU_CTRL_CLKOUTSEL2_LFXO (_CMU_CTRL_CLKOUTSEL2_LFXO << 10) /**< Shifted mode LFXO for CMU_CTRL */ 242 #define CMU_CTRL_CLKOUTSEL2_HFXODIV2Q (_CMU_CTRL_CLKOUTSEL2_HFXODIV2Q << 10) /**< Shifted mode HFXODIV2Q for CMU_CTRL */ 243 #define CMU_CTRL_CLKOUTSEL2_HFXO (_CMU_CTRL_CLKOUTSEL2_HFXO << 10) /**< Shifted mode HFXO for CMU_CTRL */ 244 #define CMU_CTRL_CLKOUTSEL2_HFEXPCLK (_CMU_CTRL_CLKOUTSEL2_HFEXPCLK << 10) /**< Shifted mode HFEXPCLK for CMU_CTRL */ 245 #define CMU_CTRL_CLKOUTSEL2_HFXOX2Q (_CMU_CTRL_CLKOUTSEL2_HFXOX2Q << 10) /**< Shifted mode HFXOX2Q for CMU_CTRL */ 246 #define CMU_CTRL_CLKOUTSEL2_ULFRCOQ (_CMU_CTRL_CLKOUTSEL2_ULFRCOQ << 10) /**< Shifted mode ULFRCOQ for CMU_CTRL */ 247 #define CMU_CTRL_CLKOUTSEL2_LFRCOQ (_CMU_CTRL_CLKOUTSEL2_LFRCOQ << 10) /**< Shifted mode LFRCOQ for CMU_CTRL */ 248 #define CMU_CTRL_CLKOUTSEL2_LFXOQ (_CMU_CTRL_CLKOUTSEL2_LFXOQ << 10) /**< Shifted mode LFXOQ for CMU_CTRL */ 249 #define CMU_CTRL_CLKOUTSEL2_HFRCOQ (_CMU_CTRL_CLKOUTSEL2_HFRCOQ << 10) /**< Shifted mode HFRCOQ for CMU_CTRL */ 250 #define CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL2_AUXHFRCOQ << 10) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */ 251 #define CMU_CTRL_CLKOUTSEL2_HFXOQ (_CMU_CTRL_CLKOUTSEL2_HFXOQ << 10) /**< Shifted mode HFXOQ for CMU_CTRL */ 252 #define CMU_CTRL_CLKOUTSEL2_HFSRCCLK (_CMU_CTRL_CLKOUTSEL2_HFSRCCLK << 10) /**< Shifted mode HFSRCCLK for CMU_CTRL */ 253 #define CMU_CTRL_CLKOUTSEL2_USHFRCOQ (_CMU_CTRL_CLKOUTSEL2_USHFRCOQ << 10) /**< Shifted mode USHFRCOQ for CMU_CTRL */ 254 #define CMU_CTRL_WSHFLE (0x1UL << 16) /**< Wait State for High-Frequency LE Interface */ 255 #define _CMU_CTRL_WSHFLE_SHIFT 16 /**< Shift value for CMU_WSHFLE */ 256 #define _CMU_CTRL_WSHFLE_MASK 0x10000UL /**< Bit mask for CMU_WSHFLE */ 257 #define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */ 258 #define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CTRL */ 259 #define CMU_CTRL_HFPERCLKEN (0x1UL << 20) /**< HFPERCLK Enable */ 260 #define _CMU_CTRL_HFPERCLKEN_SHIFT 20 /**< Shift value for CMU_HFPERCLKEN */ 261 #define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL /**< Bit mask for CMU_HFPERCLKEN */ 262 #define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */ 263 #define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */ 264 265 /* Bit fields for CMU USHFRCOCTRL */ 266 #define _CMU_USHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_USHFRCOCTRL */ 267 #define _CMU_USHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_USHFRCOCTRL */ 268 #define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 269 #define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 270 #define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 271 #define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 272 #define _CMU_USHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ 273 #define _CMU_USHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ 274 #define _CMU_USHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 275 #define CMU_USHFRCOCTRL_FINETUNING_DEFAULT (_CMU_USHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 276 #define _CMU_USHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ 277 #define _CMU_USHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ 278 #define _CMU_USHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 279 #define CMU_USHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_USHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 280 #define _CMU_USHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ 281 #define _CMU_USHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ 282 #define _CMU_USHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 283 #define CMU_USHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_USHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 284 #define CMU_USHFRCOCTRL_LDOHP (0x1UL << 24) /**< USHFRCO LDO High Power Mode */ 285 #define _CMU_USHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ 286 #define _CMU_USHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ 287 #define _CMU_USHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 288 #define CMU_USHFRCOCTRL_LDOHP_DEFAULT (_CMU_USHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 289 #define _CMU_USHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ 290 #define _CMU_USHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ 291 #define _CMU_USHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 292 #define _CMU_USHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_USHFRCOCTRL */ 293 #define _CMU_USHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_USHFRCOCTRL */ 294 #define _CMU_USHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_USHFRCOCTRL */ 295 #define CMU_USHFRCOCTRL_CLKDIV_DEFAULT (_CMU_USHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 296 #define CMU_USHFRCOCTRL_CLKDIV_DIV1 (_CMU_USHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_USHFRCOCTRL */ 297 #define CMU_USHFRCOCTRL_CLKDIV_DIV2 (_CMU_USHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_USHFRCOCTRL */ 298 #define CMU_USHFRCOCTRL_CLKDIV_DIV4 (_CMU_USHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_USHFRCOCTRL */ 299 #define CMU_USHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ 300 #define _CMU_USHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ 301 #define _CMU_USHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ 302 #define _CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 303 #define CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_USHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 304 #define _CMU_USHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ 305 #define _CMU_USHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ 306 #define _CMU_USHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */ 307 #define CMU_USHFRCOCTRL_VREFTC_DEFAULT (_CMU_USHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */ 308 309 /* Bit fields for CMU HFRCOCTRL */ 310 #define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_HFRCOCTRL */ 311 #define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_HFRCOCTRL */ 312 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 313 #define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 314 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 315 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 316 #define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ 317 #define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ 318 #define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 319 #define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 320 #define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ 321 #define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ 322 #define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 323 #define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 324 #define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ 325 #define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ 326 #define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 327 #define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 328 #define CMU_HFRCOCTRL_LDOHP (0x1UL << 24) /**< HFRCO LDO High Power Mode */ 329 #define _CMU_HFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ 330 #define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ 331 #define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 332 #define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 333 #define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ 334 #define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ 335 #define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 336 #define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_HFRCOCTRL */ 337 #define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_HFRCOCTRL */ 338 #define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_HFRCOCTRL */ 339 #define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 340 #define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_HFRCOCTRL */ 341 #define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_HFRCOCTRL */ 342 #define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_HFRCOCTRL */ 343 #define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ 344 #define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ 345 #define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ 346 #define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 347 #define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 348 #define _CMU_HFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ 349 #define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ 350 #define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_HFRCOCTRL */ 351 #define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */ 352 353 /* Bit fields for CMU AUXHFRCOCTRL */ 354 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL /**< Default value for CMU_AUXHFRCOCTRL */ 355 #define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL /**< Mask for CMU_AUXHFRCOCTRL */ 356 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 357 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 358 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 359 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 360 #define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8 /**< Shift value for CMU_FINETUNING */ 361 #define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL /**< Bit mask for CMU_FINETUNING */ 362 #define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 363 #define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 364 #define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16 /**< Shift value for CMU_FREQRANGE */ 365 #define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for CMU_FREQRANGE */ 366 #define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 367 #define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 368 #define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21 /**< Shift value for CMU_CMPBIAS */ 369 #define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMU_CMPBIAS */ 370 #define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 371 #define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 372 #define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24) /**< AUXHFRCO LDO High Power Mode */ 373 #define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24 /**< Shift value for CMU_LDOHP */ 374 #define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL /**< Bit mask for CMU_LDOHP */ 375 #define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 376 #define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 377 #define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25 /**< Shift value for CMU_CLKDIV */ 378 #define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL /**< Bit mask for CMU_CLKDIV */ 379 #define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 380 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_AUXHFRCOCTRL */ 381 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_AUXHFRCOCTRL */ 382 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_AUXHFRCOCTRL */ 383 #define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 384 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25) /**< Shifted mode DIV1 for CMU_AUXHFRCOCTRL */ 385 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25) /**< Shifted mode DIV2 for CMU_AUXHFRCOCTRL */ 386 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25) /**< Shifted mode DIV4 for CMU_AUXHFRCOCTRL */ 387 #define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27) /**< Enable Reference for Fine Tuning */ 388 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27 /**< Shift value for CMU_FINETUNINGEN */ 389 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for CMU_FINETUNINGEN */ 390 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 391 #define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 392 #define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28 /**< Shift value for CMU_VREFTC */ 393 #define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL /**< Bit mask for CMU_VREFTC */ 394 #define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */ 395 #define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */ 396 397 /* Bit fields for CMU LFRCOCTRL */ 398 #define _CMU_LFRCOCTRL_RESETVALUE 0x81160100UL /**< Default value for CMU_LFRCOCTRL */ 399 #define _CMU_LFRCOCTRL_MASK 0xF33701FFUL /**< Mask for CMU_LFRCOCTRL */ 400 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 401 #define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL /**< Bit mask for CMU_TUNING */ 402 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 403 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 404 #define CMU_LFRCOCTRL_ENVREF (0x1UL << 16) /**< Enable Duty Cycling of Vref */ 405 #define _CMU_LFRCOCTRL_ENVREF_SHIFT 16 /**< Shift value for CMU_ENVREF */ 406 #define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL /**< Bit mask for CMU_ENVREF */ 407 #define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 408 #define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 409 #define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17) /**< Enable Comparator Chopping */ 410 #define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17 /**< Shift value for CMU_ENCHOP */ 411 #define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL /**< Bit mask for CMU_ENCHOP */ 412 #define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 413 #define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 414 #define CMU_LFRCOCTRL_ENDEM (0x1UL << 18) /**< Enable Dynamic Element Matching */ 415 #define _CMU_LFRCOCTRL_ENDEM_SHIFT 18 /**< Shift value for CMU_ENDEM */ 416 #define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL /**< Bit mask for CMU_ENDEM */ 417 #define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 418 #define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 419 #define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20 /**< Shift value for CMU_VREFUPDATE */ 420 #define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL /**< Bit mask for CMU_VREFUPDATE */ 421 #define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ 422 #define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 423 #define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL /**< Mode 64CYCLES for CMU_LFRCOCTRL */ 424 #define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL /**< Mode 128CYCLES for CMU_LFRCOCTRL */ 425 #define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL /**< Mode 256CYCLES for CMU_LFRCOCTRL */ 426 #define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ 427 #define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 428 #define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20) /**< Shifted mode 64CYCLES for CMU_LFRCOCTRL */ 429 #define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20) /**< Shifted mode 128CYCLES for CMU_LFRCOCTRL */ 430 #define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20) /**< Shifted mode 256CYCLES for CMU_LFRCOCTRL */ 431 #define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ 432 #define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL /**< Bit mask for CMU_TIMEOUT */ 433 #define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFRCOCTRL */ 434 #define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 435 #define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL /**< Mode 16CYCLES for CMU_LFRCOCTRL */ 436 #define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL /**< Mode 32CYCLES for CMU_LFRCOCTRL */ 437 #define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFRCOCTRL */ 438 #define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 439 #define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_LFRCOCTRL */ 440 #define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_LFRCOCTRL */ 441 #define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28 /**< Shift value for CMU_GMCCURTUNE */ 442 #define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL /**< Bit mask for CMU_GMCCURTUNE */ 443 #define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_LFRCOCTRL */ 444 #define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */ 445 446 /* Bit fields for CMU HFXOCTRL */ 447 #define _CMU_HFXOCTRL_RESETVALUE 0x00000008UL /**< Default value for CMU_HFXOCTRL */ 448 #define _CMU_HFXOCTRL_MASK 0x3700003BUL /**< Mask for CMU_HFXOCTRL */ 449 #define _CMU_HFXOCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ 450 #define _CMU_HFXOCTRL_MODE_MASK 0x3UL /**< Bit mask for CMU_MODE */ 451 #define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 452 #define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_HFXOCTRL */ 453 #define _CMU_HFXOCTRL_MODE_ACBUFEXTCLK 0x00000001UL /**< Mode ACBUFEXTCLK for CMU_HFXOCTRL */ 454 #define _CMU_HFXOCTRL_MODE_DCBUFEXTCLK 0x00000002UL /**< Mode DCBUFEXTCLK for CMU_HFXOCTRL */ 455 #define _CMU_HFXOCTRL_MODE_DIGEXTCLK 0x00000003UL /**< Mode DIGEXTCLK for CMU_HFXOCTRL */ 456 #define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 457 #define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0) /**< Shifted mode XTAL for CMU_HFXOCTRL */ 458 #define CMU_HFXOCTRL_MODE_ACBUFEXTCLK (_CMU_HFXOCTRL_MODE_ACBUFEXTCLK << 0) /**< Shifted mode ACBUFEXTCLK for CMU_HFXOCTRL */ 459 #define CMU_HFXOCTRL_MODE_DCBUFEXTCLK (_CMU_HFXOCTRL_MODE_DCBUFEXTCLK << 0) /**< Shifted mode DCBUFEXTCLK for CMU_HFXOCTRL */ 460 #define CMU_HFXOCTRL_MODE_DIGEXTCLK (_CMU_HFXOCTRL_MODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_HFXOCTRL */ 461 #define CMU_HFXOCTRL_HFXOX2EN (0x1UL << 3) /**< Enable Double Frequency on HFXOX2 Clock (compared to HFXO Clock) */ 462 #define _CMU_HFXOCTRL_HFXOX2EN_SHIFT 3 /**< Shift value for CMU_HFXOX2EN */ 463 #define _CMU_HFXOCTRL_HFXOX2EN_MASK 0x8UL /**< Bit mask for CMU_HFXOX2EN */ 464 #define _CMU_HFXOCTRL_HFXOX2EN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 465 #define CMU_HFXOCTRL_HFXOX2EN_DEFAULT (_CMU_HFXOCTRL_HFXOX2EN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 466 #define _CMU_HFXOCTRL_PEAKDETMODE_SHIFT 4 /**< Shift value for CMU_PEAKDETMODE */ 467 #define _CMU_HFXOCTRL_PEAKDETMODE_MASK 0x30UL /**< Bit mask for CMU_PEAKDETMODE */ 468 #define _CMU_HFXOCTRL_PEAKDETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 469 #define _CMU_HFXOCTRL_PEAKDETMODE_ONCECMD 0x00000000UL /**< Mode ONCECMD for CMU_HFXOCTRL */ 470 #define _CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD 0x00000001UL /**< Mode AUTOCMD for CMU_HFXOCTRL */ 471 #define _CMU_HFXOCTRL_PEAKDETMODE_CMD 0x00000002UL /**< Mode CMD for CMU_HFXOCTRL */ 472 #define _CMU_HFXOCTRL_PEAKDETMODE_MANUAL 0x00000003UL /**< Mode MANUAL for CMU_HFXOCTRL */ 473 #define CMU_HFXOCTRL_PEAKDETMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 474 #define CMU_HFXOCTRL_PEAKDETMODE_ONCECMD (_CMU_HFXOCTRL_PEAKDETMODE_ONCECMD << 4) /**< Shifted mode ONCECMD for CMU_HFXOCTRL */ 475 #define CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD << 4) /**< Shifted mode AUTOCMD for CMU_HFXOCTRL */ 476 #define CMU_HFXOCTRL_PEAKDETMODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD << 4) /**< Shifted mode CMD for CMU_HFXOCTRL */ 477 #define CMU_HFXOCTRL_PEAKDETMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETMODE_MANUAL << 4) /**< Shifted mode MANUAL for CMU_HFXOCTRL */ 478 #define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24 /**< Shift value for CMU_LFTIMEOUT */ 479 #define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_LFTIMEOUT */ 480 #define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 481 #define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL /**< Mode 0CYCLES for CMU_HFXOCTRL */ 482 #define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for CMU_HFXOCTRL */ 483 #define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for CMU_HFXOCTRL */ 484 #define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL /**< Mode 16CYCLES for CMU_HFXOCTRL */ 485 #define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL /**< Mode 32CYCLES for CMU_HFXOCTRL */ 486 #define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL /**< Mode 64CYCLES for CMU_HFXOCTRL */ 487 #define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL /**< Mode 1KCYCLES for CMU_HFXOCTRL */ 488 #define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL /**< Mode 4KCYCLES for CMU_HFXOCTRL */ 489 #define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 490 #define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24) /**< Shifted mode 0CYCLES for CMU_HFXOCTRL */ 491 #define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_HFXOCTRL */ 492 #define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24) /**< Shifted mode 4CYCLES for CMU_HFXOCTRL */ 493 #define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24) /**< Shifted mode 16CYCLES for CMU_HFXOCTRL */ 494 #define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24) /**< Shifted mode 32CYCLES for CMU_HFXOCTRL */ 495 #define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24) /**< Shifted mode 64CYCLES for CMU_HFXOCTRL */ 496 #define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_HFXOCTRL */ 497 #define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_HFXOCTRL */ 498 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28) /**< Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ 499 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28 /**< Shift value for CMU_AUTOSTARTEM0EM1 */ 500 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL /**< Bit mask for CMU_AUTOSTARTEM0EM1 */ 501 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 502 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 503 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29) /**< Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3 */ 504 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29 /**< Shift value for CMU_AUTOSTARTSELEM0EM1 */ 505 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL /**< Bit mask for CMU_AUTOSTARTSELEM0EM1 */ 506 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOCTRL */ 507 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_HFXOCTRL */ 508 509 /* Bit fields for CMU HFXOCTRL1 */ 510 #define _CMU_HFXOCTRL1_RESETVALUE 0x00002000UL /**< Default value for CMU_HFXOCTRL1 */ 511 #define _CMU_HFXOCTRL1_MASK 0x00007000UL /**< Mask for CMU_HFXOCTRL1 */ 512 #define _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT 12 /**< Shift value for CMU_PEAKDETTHR */ 513 #define _CMU_HFXOCTRL1_PEAKDETTHR_MASK 0x7000UL /**< Bit mask for CMU_PEAKDETTHR */ 514 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR0 0x00000000UL /**< Mode THR0 for CMU_HFXOCTRL1 */ 515 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR1 0x00000001UL /**< Mode THR1 for CMU_HFXOCTRL1 */ 516 #define _CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_HFXOCTRL1 */ 517 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR2 0x00000002UL /**< Mode THR2 for CMU_HFXOCTRL1 */ 518 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR3 0x00000003UL /**< Mode THR3 for CMU_HFXOCTRL1 */ 519 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR4 0x00000004UL /**< Mode THR4 for CMU_HFXOCTRL1 */ 520 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR5 0x00000005UL /**< Mode THR5 for CMU_HFXOCTRL1 */ 521 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR6 0x00000006UL /**< Mode THR6 for CMU_HFXOCTRL1 */ 522 #define _CMU_HFXOCTRL1_PEAKDETTHR_THR7 0x00000007UL /**< Mode THR7 for CMU_HFXOCTRL1 */ 523 #define CMU_HFXOCTRL1_PEAKDETTHR_THR0 (_CMU_HFXOCTRL1_PEAKDETTHR_THR0 << 12) /**< Shifted mode THR0 for CMU_HFXOCTRL1 */ 524 #define CMU_HFXOCTRL1_PEAKDETTHR_THR1 (_CMU_HFXOCTRL1_PEAKDETTHR_THR1 << 12) /**< Shifted mode THR1 for CMU_HFXOCTRL1 */ 525 #define CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT (_CMU_HFXOCTRL1_PEAKDETTHR_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOCTRL1 */ 526 #define CMU_HFXOCTRL1_PEAKDETTHR_THR2 (_CMU_HFXOCTRL1_PEAKDETTHR_THR2 << 12) /**< Shifted mode THR2 for CMU_HFXOCTRL1 */ 527 #define CMU_HFXOCTRL1_PEAKDETTHR_THR3 (_CMU_HFXOCTRL1_PEAKDETTHR_THR3 << 12) /**< Shifted mode THR3 for CMU_HFXOCTRL1 */ 528 #define CMU_HFXOCTRL1_PEAKDETTHR_THR4 (_CMU_HFXOCTRL1_PEAKDETTHR_THR4 << 12) /**< Shifted mode THR4 for CMU_HFXOCTRL1 */ 529 #define CMU_HFXOCTRL1_PEAKDETTHR_THR5 (_CMU_HFXOCTRL1_PEAKDETTHR_THR5 << 12) /**< Shifted mode THR5 for CMU_HFXOCTRL1 */ 530 #define CMU_HFXOCTRL1_PEAKDETTHR_THR6 (_CMU_HFXOCTRL1_PEAKDETTHR_THR6 << 12) /**< Shifted mode THR6 for CMU_HFXOCTRL1 */ 531 #define CMU_HFXOCTRL1_PEAKDETTHR_THR7 (_CMU_HFXOCTRL1_PEAKDETTHR_THR7 << 12) /**< Shifted mode THR7 for CMU_HFXOCTRL1 */ 532 533 /* Bit fields for CMU HFXOSTARTUPCTRL */ 534 #define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00000600UL /**< Default value for CMU_HFXOSTARTUPCTRL */ 535 #define _CMU_HFXOSTARTUPCTRL_MASK 0x000FFFFFUL /**< Mask for CMU_HFXOSTARTUPCTRL */ 536 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ 537 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ 538 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000600UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 539 #define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 540 #define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ 541 #define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ 542 #define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 543 #define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTARTUPCTRL */ 544 545 /* Bit fields for CMU HFXOSTEADYSTATECTRL */ 546 #define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0x08000100UL /**< Default value for CMU_HFXOSTEADYSTATECTRL */ 547 #define _CMU_HFXOSTEADYSTATECTRL_MASK 0x0C0FFFFFUL /**< Mask for CMU_HFXOSTEADYSTATECTRL */ 548 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ 549 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ 550 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000100UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 551 #define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 552 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11 /**< Shift value for CMU_CTUNE */ 553 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL /**< Bit mask for CMU_CTUNE */ 554 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 555 #define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 556 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26) /**< Enables Oscillator Peak Detectors */ 557 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26 /**< Shift value for CMU_PEAKDETEN */ 558 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL /**< Bit mask for CMU_PEAKDETEN */ 559 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 560 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 561 #define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN (0x1UL << 27) /**< Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO */ 562 #define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_SHIFT 27 /**< Shift value for CMU_PEAKMONEN */ 563 #define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_MASK 0x8000000UL /**< Bit mask for CMU_PEAKMONEN */ 564 #define _CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 565 #define CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKMONEN_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_HFXOSTEADYSTATECTRL */ 566 567 /* Bit fields for CMU HFXOTIMEOUTCTRL */ 568 #define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0000D08EUL /**< Default value for CMU_HFXOTIMEOUTCTRL */ 569 #define _CMU_HFXOTIMEOUTCTRL_MASK 0x0000F0FFUL /**< Mask for CMU_HFXOTIMEOUTCTRL */ 570 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0 /**< Shift value for CMU_STARTUPTIMEOUT */ 571 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL /**< Bit mask for CMU_STARTUPTIMEOUT */ 572 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 573 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 574 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 575 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 576 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ 577 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ 578 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 579 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 580 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 581 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 582 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 583 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 584 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 585 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ 586 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x0000000EUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 587 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ 588 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 589 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 590 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 591 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 592 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64CYCLES << 0) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ 593 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128CYCLES << 0) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ 594 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 595 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 596 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 597 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 598 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 599 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 600 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 601 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_64KCYCLES << 0) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ 602 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 603 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_128KCYCLES << 0) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ 604 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4 /**< Shift value for CMU_STEADYTIMEOUT */ 605 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL /**< Bit mask for CMU_STEADYTIMEOUT */ 606 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 607 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 608 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 609 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 610 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ 611 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ 612 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 613 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 614 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000008UL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 615 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 616 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 617 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 618 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 619 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 620 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ 621 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ 622 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 623 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 624 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 625 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 626 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64CYCLES << 4) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ 627 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128CYCLES << 4) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ 628 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 629 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 630 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 631 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 632 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 633 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 634 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 635 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 636 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_64KCYCLES << 4) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ 637 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_128KCYCLES << 4) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ 638 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12 /**< Shift value for CMU_PEAKDETTIMEOUT */ 639 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL /**< Bit mask for CMU_PEAKDETTIMEOUT */ 640 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 641 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL /**< Mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 642 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL /**< Mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 643 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL /**< Mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 644 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES 0x00000004UL /**< Mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ 645 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES 0x00000005UL /**< Mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ 646 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000006UL /**< Mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 647 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000007UL /**< Mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 648 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000008UL /**< Mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 649 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000009UL /**< Mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 650 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x0000000AUL /**< Mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 651 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x0000000BUL /**< Mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 652 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000CUL /**< Mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 653 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000DUL /**< Mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 654 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES 0x0000000DUL /**< Mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ 655 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES 0x0000000EUL /**< Mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ 656 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12) /**< Shifted mode 2CYCLES for CMU_HFXOTIMEOUTCTRL */ 657 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12) /**< Shifted mode 4CYCLES for CMU_HFXOTIMEOUTCTRL */ 658 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12) /**< Shifted mode 16CYCLES for CMU_HFXOTIMEOUTCTRL */ 659 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12) /**< Shifted mode 32CYCLES for CMU_HFXOTIMEOUTCTRL */ 660 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64CYCLES << 12) /**< Shifted mode 64CYCLES for CMU_HFXOTIMEOUTCTRL */ 661 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128CYCLES << 12) /**< Shifted mode 128CYCLES for CMU_HFXOTIMEOUTCTRL */ 662 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12) /**< Shifted mode 256CYCLES for CMU_HFXOTIMEOUTCTRL */ 663 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12) /**< Shifted mode 1KCYCLES for CMU_HFXOTIMEOUTCTRL */ 664 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12) /**< Shifted mode 2KCYCLES for CMU_HFXOTIMEOUTCTRL */ 665 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12) /**< Shifted mode 4KCYCLES for CMU_HFXOTIMEOUTCTRL */ 666 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12) /**< Shifted mode 8KCYCLES for CMU_HFXOTIMEOUTCTRL */ 667 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12) /**< Shifted mode 16KCYCLES for CMU_HFXOTIMEOUTCTRL */ 668 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12) /**< Shifted mode 32KCYCLES for CMU_HFXOTIMEOUTCTRL */ 669 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFXOTIMEOUTCTRL */ 670 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_64KCYCLES << 12) /**< Shifted mode 64KCYCLES for CMU_HFXOTIMEOUTCTRL */ 671 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_128KCYCLES << 12) /**< Shifted mode 128KCYCLES for CMU_HFXOTIMEOUTCTRL */ 672 673 /* Bit fields for CMU LFXOCTRL */ 674 #define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL /**< Default value for CMU_LFXOCTRL */ 675 #define _CMU_LFXOCTRL_MASK 0x0713DB7FUL /**< Mask for CMU_LFXOCTRL */ 676 #define _CMU_LFXOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */ 677 #define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */ 678 #define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 679 #define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 680 #define _CMU_LFXOCTRL_MODE_SHIFT 8 /**< Shift value for CMU_MODE */ 681 #define _CMU_LFXOCTRL_MODE_MASK 0x300UL /**< Bit mask for CMU_MODE */ 682 #define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 683 #define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_LFXOCTRL */ 684 #define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_LFXOCTRL */ 685 #define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_LFXOCTRL */ 686 #define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 687 #define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8) /**< Shifted mode XTAL for CMU_LFXOCTRL */ 688 #define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8) /**< Shifted mode BUFEXTCLK for CMU_LFXOCTRL */ 689 #define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8) /**< Shifted mode DIGEXTCLK for CMU_LFXOCTRL */ 690 #define _CMU_LFXOCTRL_GAIN_SHIFT 11 /**< Shift value for CMU_GAIN */ 691 #define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL /**< Bit mask for CMU_GAIN */ 692 #define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 693 #define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 694 #define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14) /**< LFXO High XTAL Oscillation Amplitude Enable */ 695 #define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14 /**< Shift value for CMU_HIGHAMPL */ 696 #define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL /**< Bit mask for CMU_HIGHAMPL */ 697 #define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 698 #define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 699 #define CMU_LFXOCTRL_AGC (0x1UL << 15) /**< LFXO AGC Enable */ 700 #define _CMU_LFXOCTRL_AGC_SHIFT 15 /**< Shift value for CMU_AGC */ 701 #define _CMU_LFXOCTRL_AGC_MASK 0x8000UL /**< Bit mask for CMU_AGC */ 702 #define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 703 #define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 704 #define _CMU_LFXOCTRL_CUR_SHIFT 16 /**< Shift value for CMU_CUR */ 705 #define _CMU_LFXOCTRL_CUR_MASK 0x30000UL /**< Bit mask for CMU_CUR */ 706 #define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 707 #define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 708 #define CMU_LFXOCTRL_BUFCUR (0x1UL << 20) /**< LFXO Buffer Bias Current */ 709 #define _CMU_LFXOCTRL_BUFCUR_SHIFT 20 /**< Shift value for CMU_BUFCUR */ 710 #define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL /**< Bit mask for CMU_BUFCUR */ 711 #define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 712 #define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 713 #define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24 /**< Shift value for CMU_TIMEOUT */ 714 #define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL /**< Bit mask for CMU_TIMEOUT */ 715 #define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL /**< Mode 2CYCLES for CMU_LFXOCTRL */ 716 #define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_LFXOCTRL */ 717 #define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_LFXOCTRL */ 718 #define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL /**< Mode 2KCYCLES for CMU_LFXOCTRL */ 719 #define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL /**< Mode 4KCYCLES for CMU_LFXOCTRL */ 720 #define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL /**< Mode 8KCYCLES for CMU_LFXOCTRL */ 721 #define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL /**< Mode 16KCYCLES for CMU_LFXOCTRL */ 722 #define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for CMU_LFXOCTRL */ 723 #define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL /**< Mode 32KCYCLES for CMU_LFXOCTRL */ 724 #define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24) /**< Shifted mode 2CYCLES for CMU_LFXOCTRL */ 725 #define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24) /**< Shifted mode 256CYCLES for CMU_LFXOCTRL */ 726 #define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24) /**< Shifted mode 1KCYCLES for CMU_LFXOCTRL */ 727 #define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24) /**< Shifted mode 2KCYCLES for CMU_LFXOCTRL */ 728 #define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24) /**< Shifted mode 4KCYCLES for CMU_LFXOCTRL */ 729 #define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24) /**< Shifted mode 8KCYCLES for CMU_LFXOCTRL */ 730 #define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24) /**< Shifted mode 16KCYCLES for CMU_LFXOCTRL */ 731 #define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_LFXOCTRL */ 732 #define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24) /**< Shifted mode 32KCYCLES for CMU_LFXOCTRL */ 733 734 /* Bit fields for CMU DPLLCTRL */ 735 #define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL */ 736 #define _CMU_DPLLCTRL_MASK 0x0000005FUL /**< Mask for CMU_DPLLCTRL */ 737 #define CMU_DPLLCTRL_MODE (0x1UL << 0) /**< Operating Mode Control */ 738 #define _CMU_DPLLCTRL_MODE_SHIFT 0 /**< Shift value for CMU_MODE */ 739 #define _CMU_DPLLCTRL_MODE_MASK 0x1UL /**< Bit mask for CMU_MODE */ 740 #define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 741 #define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL /**< Mode FREQLL for CMU_DPLLCTRL */ 742 #define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL /**< Mode PHASELL for CMU_DPLLCTRL */ 743 #define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 744 #define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0) /**< Shifted mode FREQLL for CMU_DPLLCTRL */ 745 #define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0) /**< Shifted mode PHASELL for CMU_DPLLCTRL */ 746 #define CMU_DPLLCTRL_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ 747 #define _CMU_DPLLCTRL_EDGESEL_SHIFT 1 /**< Shift value for CMU_EDGESEL */ 748 #define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL /**< Bit mask for CMU_EDGESEL */ 749 #define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 750 #define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL /**< Mode FALL for CMU_DPLLCTRL */ 751 #define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL /**< Mode RISE for CMU_DPLLCTRL */ 752 #define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 753 #define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1) /**< Shifted mode FALL for CMU_DPLLCTRL */ 754 #define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1) /**< Shifted mode RISE for CMU_DPLLCTRL */ 755 #define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Ctrl */ 756 #define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2 /**< Shift value for CMU_AUTORECOVER */ 757 #define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL /**< Bit mask for CMU_AUTORECOVER */ 758 #define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 759 #define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 760 #define _CMU_DPLLCTRL_REFSEL_SHIFT 3 /**< Shift value for CMU_REFSEL */ 761 #define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL /**< Bit mask for CMU_REFSEL */ 762 #define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 763 #define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_DPLLCTRL */ 764 #define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_DPLLCTRL */ 765 #define _CMU_DPLLCTRL_REFSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_DPLLCTRL */ 766 #define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLCTRL */ 767 #define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 768 #define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_DPLLCTRL */ 769 #define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_DPLLCTRL */ 770 #define CMU_DPLLCTRL_REFSEL_USHFRCO (_CMU_DPLLCTRL_REFSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_DPLLCTRL */ 771 #define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3) /**< Shifted mode CLKIN0 for CMU_DPLLCTRL */ 772 #define CMU_DPLLCTRL_DITHEN (0x1UL << 6) /**< Dither Enable Control */ 773 #define _CMU_DPLLCTRL_DITHEN_SHIFT 6 /**< Shift value for CMU_DITHEN */ 774 #define _CMU_DPLLCTRL_DITHEN_MASK 0x40UL /**< Bit mask for CMU_DITHEN */ 775 #define _CMU_DPLLCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL */ 776 #define CMU_DPLLCTRL_DITHEN_DEFAULT (_CMU_DPLLCTRL_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_DPLLCTRL */ 777 778 /* Bit fields for CMU DPLLCTRL1 */ 779 #define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLCTRL1 */ 780 #define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL /**< Mask for CMU_DPLLCTRL1 */ 781 #define _CMU_DPLLCTRL1_M_SHIFT 0 /**< Shift value for CMU_M */ 782 #define _CMU_DPLLCTRL1_M_MASK 0xFFFUL /**< Bit mask for CMU_M */ 783 #define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ 784 #define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ 785 #define _CMU_DPLLCTRL1_N_SHIFT 16 /**< Shift value for CMU_N */ 786 #define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL /**< Bit mask for CMU_N */ 787 #define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLCTRL1 */ 788 #define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_DPLLCTRL1 */ 789 790 /* Bit fields for CMU CALCTRL */ 791 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ 792 #define _CMU_CALCTRL_MASK 0x0F0F01F7UL /**< Mask for CMU_CALCTRL */ 793 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */ 794 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */ 795 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 796 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */ 797 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */ 798 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */ 799 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */ 800 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */ 801 #define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL /**< Mode PRS for CMU_CALCTRL */ 802 #define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000007UL /**< Mode USHFRCO for CMU_CALCTRL */ 803 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 804 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */ 805 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */ 806 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */ 807 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */ 808 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ 809 #define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0) /**< Shifted mode PRS for CMU_CALCTRL */ 810 #define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */ 811 #define _CMU_CALCTRL_DOWNSEL_SHIFT 4 /**< Shift value for CMU_DOWNSEL */ 812 #define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL /**< Bit mask for CMU_DOWNSEL */ 813 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 814 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */ 815 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */ 816 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */ 817 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */ 818 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */ 819 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */ 820 #define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL /**< Mode PRS for CMU_CALCTRL */ 821 #define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CALCTRL */ 822 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 823 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4) /**< Shifted mode HFCLK for CMU_CALCTRL */ 824 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_CALCTRL */ 825 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4) /**< Shifted mode LFXO for CMU_CALCTRL */ 826 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4) /**< Shifted mode HFRCO for CMU_CALCTRL */ 827 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4) /**< Shifted mode LFRCO for CMU_CALCTRL */ 828 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */ 829 #define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4) /**< Shifted mode PRS for CMU_CALCTRL */ 830 #define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 4) /**< Shifted mode USHFRCO for CMU_CALCTRL */ 831 #define CMU_CALCTRL_CONT (0x1UL << 8) /**< Continuous Calibration */ 832 #define _CMU_CALCTRL_CONT_SHIFT 8 /**< Shift value for CMU_CONT */ 833 #define _CMU_CALCTRL_CONT_MASK 0x100UL /**< Bit mask for CMU_CONT */ 834 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 835 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 836 #define _CMU_CALCTRL_PRSUPSEL_SHIFT 16 /**< Shift value for CMU_PRSUPSEL */ 837 #define _CMU_CALCTRL_PRSUPSEL_MASK 0xF0000UL /**< Bit mask for CMU_PRSUPSEL */ 838 #define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 839 #define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ 840 #define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ 841 #define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ 842 #define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ 843 #define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ 844 #define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ 845 #define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ 846 #define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ 847 #define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ 848 #define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ 849 #define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ 850 #define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ 851 #define _CMU_CALCTRL_PRSUPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ 852 #define _CMU_CALCTRL_PRSUPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ 853 #define _CMU_CALCTRL_PRSUPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ 854 #define _CMU_CALCTRL_PRSUPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ 855 #define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 856 #define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ 857 #define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ 858 #define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ 859 #define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ 860 #define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ 861 #define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ 862 #define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ 863 #define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ 864 #define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ 865 #define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ 866 #define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ 867 #define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ 868 #define CMU_CALCTRL_PRSUPSEL_PRSCH12 (_CMU_CALCTRL_PRSUPSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ 869 #define CMU_CALCTRL_PRSUPSEL_PRSCH13 (_CMU_CALCTRL_PRSUPSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ 870 #define CMU_CALCTRL_PRSUPSEL_PRSCH14 (_CMU_CALCTRL_PRSUPSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ 871 #define CMU_CALCTRL_PRSUPSEL_PRSCH15 (_CMU_CALCTRL_PRSUPSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ 872 #define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24 /**< Shift value for CMU_PRSDOWNSEL */ 873 #define _CMU_CALCTRL_PRSDOWNSEL_MASK 0xF000000UL /**< Bit mask for CMU_PRSDOWNSEL */ 874 #define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 875 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for CMU_CALCTRL */ 876 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for CMU_CALCTRL */ 877 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for CMU_CALCTRL */ 878 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for CMU_CALCTRL */ 879 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for CMU_CALCTRL */ 880 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for CMU_CALCTRL */ 881 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for CMU_CALCTRL */ 882 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for CMU_CALCTRL */ 883 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for CMU_CALCTRL */ 884 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for CMU_CALCTRL */ 885 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for CMU_CALCTRL */ 886 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for CMU_CALCTRL */ 887 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for CMU_CALCTRL */ 888 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for CMU_CALCTRL */ 889 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for CMU_CALCTRL */ 890 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for CMU_CALCTRL */ 891 #define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 892 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24) /**< Shifted mode PRSCH0 for CMU_CALCTRL */ 893 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24) /**< Shifted mode PRSCH1 for CMU_CALCTRL */ 894 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24) /**< Shifted mode PRSCH2 for CMU_CALCTRL */ 895 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24) /**< Shifted mode PRSCH3 for CMU_CALCTRL */ 896 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24) /**< Shifted mode PRSCH4 for CMU_CALCTRL */ 897 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24) /**< Shifted mode PRSCH5 for CMU_CALCTRL */ 898 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24) /**< Shifted mode PRSCH6 for CMU_CALCTRL */ 899 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24) /**< Shifted mode PRSCH7 for CMU_CALCTRL */ 900 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24) /**< Shifted mode PRSCH8 for CMU_CALCTRL */ 901 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24) /**< Shifted mode PRSCH9 for CMU_CALCTRL */ 902 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24) /**< Shifted mode PRSCH10 for CMU_CALCTRL */ 903 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24) /**< Shifted mode PRSCH11 for CMU_CALCTRL */ 904 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH12 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH12 << 24) /**< Shifted mode PRSCH12 for CMU_CALCTRL */ 905 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH13 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH13 << 24) /**< Shifted mode PRSCH13 for CMU_CALCTRL */ 906 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH14 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH14 << 24) /**< Shifted mode PRSCH14 for CMU_CALCTRL */ 907 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH15 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH15 << 24) /**< Shifted mode PRSCH15 for CMU_CALCTRL */ 908 909 /* Bit fields for CMU CALCNT */ 910 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ 911 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ 912 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ 913 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ 914 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ 915 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ 916 917 /* Bit fields for CMU OSCENCMD */ 918 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */ 919 #define _CMU_OSCENCMD_MASK 0x00003FFFUL /**< Mask for CMU_OSCENCMD */ 920 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */ 921 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */ 922 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */ 923 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 924 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 925 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */ 926 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */ 927 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */ 928 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 929 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 930 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */ 931 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */ 932 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */ 933 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 934 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 935 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */ 936 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */ 937 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */ 938 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 939 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 940 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */ 941 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */ 942 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */ 943 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 944 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 945 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */ 946 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */ 947 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */ 948 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 949 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 950 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */ 951 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */ 952 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */ 953 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 954 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 955 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */ 956 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */ 957 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */ 958 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 959 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 960 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */ 961 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */ 962 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */ 963 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 964 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 965 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */ 966 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */ 967 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */ 968 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 969 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 970 #define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */ 971 #define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */ 972 #define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */ 973 #define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 974 #define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 975 #define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */ 976 #define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */ 977 #define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */ 978 #define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 979 #define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 980 #define CMU_OSCENCMD_DPLLEN (0x1UL << 12) /**< DPLL Enable */ 981 #define _CMU_OSCENCMD_DPLLEN_SHIFT 12 /**< Shift value for CMU_DPLLEN */ 982 #define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL /**< Bit mask for CMU_DPLLEN */ 983 #define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 984 #define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 985 #define CMU_OSCENCMD_DPLLDIS (0x1UL << 13) /**< DPLL Disable */ 986 #define _CMU_OSCENCMD_DPLLDIS_SHIFT 13 /**< Shift value for CMU_DPLLDIS */ 987 #define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL /**< Bit mask for CMU_DPLLDIS */ 988 #define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */ 989 #define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_OSCENCMD */ 990 991 /* Bit fields for CMU CMD */ 992 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */ 993 #define _CMU_CMD_MASK 0x00000013UL /**< Mask for CMU_CMD */ 994 #define CMU_CMD_CALSTART (0x1UL << 0) /**< Calibration Start */ 995 #define _CMU_CMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ 996 #define _CMU_CMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ 997 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 998 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */ 999 #define CMU_CMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ 1000 #define _CMU_CMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ 1001 #define _CMU_CMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ 1002 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 1003 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CMD */ 1004 #define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4) /**< HFXO Peak Detection Start */ 1005 #define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4 /**< Shift value for CMU_HFXOPEAKDETSTART */ 1006 #define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL /**< Bit mask for CMU_HFXOPEAKDETSTART */ 1007 #define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */ 1008 #define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */ 1009 1010 /* Bit fields for CMU DBGCLKSEL */ 1011 #define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_DBGCLKSEL */ 1012 #define _CMU_DBGCLKSEL_MASK 0x00000003UL /**< Mask for CMU_DBGCLKSEL */ 1013 #define _CMU_DBGCLKSEL_DBG_SHIFT 0 /**< Shift value for CMU_DBG */ 1014 #define _CMU_DBGCLKSEL_DBG_MASK 0x3UL /**< Bit mask for CMU_DBG */ 1015 #define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DBGCLKSEL */ 1016 #define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_DBGCLKSEL */ 1017 #define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_DBGCLKSEL */ 1018 #define _CMU_DBGCLKSEL_DBG_HFRCODIV2 0x00000002UL /**< Mode HFRCODIV2 for CMU_DBGCLKSEL */ 1019 #define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DBGCLKSEL */ 1020 #define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_DBGCLKSEL */ 1021 #define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0) /**< Shifted mode HFCLK for CMU_DBGCLKSEL */ 1022 #define CMU_DBGCLKSEL_DBG_HFRCODIV2 (_CMU_DBGCLKSEL_DBG_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_DBGCLKSEL */ 1023 1024 /* Bit fields for CMU HFCLKSEL */ 1025 #define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCLKSEL */ 1026 #define _CMU_HFCLKSEL_MASK 0x00000007UL /**< Mask for CMU_HFCLKSEL */ 1027 #define _CMU_HFCLKSEL_HF_SHIFT 0 /**< Shift value for CMU_HF */ 1028 #define _CMU_HFCLKSEL_HF_MASK 0x7UL /**< Bit mask for CMU_HF */ 1029 #define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCLKSEL */ 1030 #define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSEL */ 1031 #define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSEL */ 1032 #define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSEL */ 1033 #define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSEL */ 1034 #define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSEL */ 1035 #define _CMU_HFCLKSEL_HF_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSEL */ 1036 #define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSEL */ 1037 #define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSEL */ 1038 #define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSEL */ 1039 #define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSEL */ 1040 #define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSEL */ 1041 #define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSEL */ 1042 #define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSEL */ 1043 #define CMU_HFCLKSEL_HF_USHFRCO (_CMU_HFCLKSEL_HF_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSEL */ 1044 #define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSEL */ 1045 1046 /* Bit fields for CMU LFACLKSEL */ 1047 #define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKSEL */ 1048 #define _CMU_LFACLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFACLKSEL */ 1049 #define _CMU_LFACLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */ 1050 #define _CMU_LFACLKSEL_LFA_MASK 0x7UL /**< Bit mask for CMU_LFA */ 1051 #define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKSEL */ 1052 #define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFACLKSEL */ 1053 #define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFACLKSEL */ 1054 #define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFACLKSEL */ 1055 #define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFACLKSEL */ 1056 #define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKSEL */ 1057 #define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFACLKSEL */ 1058 #define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFACLKSEL */ 1059 #define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFACLKSEL */ 1060 #define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFACLKSEL */ 1061 1062 /* Bit fields for CMU LFBCLKSEL */ 1063 #define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKSEL */ 1064 #define _CMU_LFBCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFBCLKSEL */ 1065 #define _CMU_LFBCLKSEL_LFB_SHIFT 0 /**< Shift value for CMU_LFB */ 1066 #define _CMU_LFBCLKSEL_LFB_MASK 0x7UL /**< Bit mask for CMU_LFB */ 1067 #define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKSEL */ 1068 #define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFBCLKSEL */ 1069 #define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFBCLKSEL */ 1070 #define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFBCLKSEL */ 1071 #define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL /**< Mode HFCLKLE for CMU_LFBCLKSEL */ 1072 #define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFBCLKSEL */ 1073 #define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKSEL */ 1074 #define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFBCLKSEL */ 1075 #define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFBCLKSEL */ 1076 #define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0) /**< Shifted mode LFXO for CMU_LFBCLKSEL */ 1077 #define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0) /**< Shifted mode HFCLKLE for CMU_LFBCLKSEL */ 1078 #define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFBCLKSEL */ 1079 1080 /* Bit fields for CMU LFECLKSEL */ 1081 #define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKSEL */ 1082 #define _CMU_LFECLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFECLKSEL */ 1083 #define _CMU_LFECLKSEL_LFE_SHIFT 0 /**< Shift value for CMU_LFE */ 1084 #define _CMU_LFECLKSEL_LFE_MASK 0x7UL /**< Bit mask for CMU_LFE */ 1085 #define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKSEL */ 1086 #define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFECLKSEL */ 1087 #define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFECLKSEL */ 1088 #define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFECLKSEL */ 1089 #define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFECLKSEL */ 1090 #define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKSEL */ 1091 #define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFECLKSEL */ 1092 #define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFECLKSEL */ 1093 #define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0) /**< Shifted mode LFXO for CMU_LFECLKSEL */ 1094 #define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFECLKSEL */ 1095 1096 /* Bit fields for CMU LFCCLKSEL */ 1097 #define _CMU_LFCCLKSEL_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKSEL */ 1098 #define _CMU_LFCCLKSEL_MASK 0x00000007UL /**< Mask for CMU_LFCCLKSEL */ 1099 #define _CMU_LFCCLKSEL_LFC_SHIFT 0 /**< Shift value for CMU_LFC */ 1100 #define _CMU_LFCCLKSEL_LFC_MASK 0x7UL /**< Bit mask for CMU_LFC */ 1101 #define _CMU_LFCCLKSEL_LFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKSEL */ 1102 #define _CMU_LFCCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCCLKSEL */ 1103 #define _CMU_LFCCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCCLKSEL */ 1104 #define _CMU_LFCCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCCLKSEL */ 1105 #define _CMU_LFCCLKSEL_LFC_ULFRCO 0x00000004UL /**< Mode ULFRCO for CMU_LFCCLKSEL */ 1106 #define CMU_LFCCLKSEL_LFC_DEFAULT (_CMU_LFCCLKSEL_LFC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKSEL */ 1107 #define CMU_LFCCLKSEL_LFC_DISABLED (_CMU_LFCCLKSEL_LFC_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCCLKSEL */ 1108 #define CMU_LFCCLKSEL_LFC_LFRCO (_CMU_LFCCLKSEL_LFC_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCCLKSEL */ 1109 #define CMU_LFCCLKSEL_LFC_LFXO (_CMU_LFCCLKSEL_LFC_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCCLKSEL */ 1110 #define CMU_LFCCLKSEL_LFC_ULFRCO (_CMU_LFCCLKSEL_LFC_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LFCCLKSEL */ 1111 1112 /* Bit fields for CMU STATUS */ 1113 #define _CMU_STATUS_RESETVALUE 0x00010003UL /**< Default value for CMU_STATUS */ 1114 #define _CMU_STATUS_MASK 0x3A4F3FFFUL /**< Mask for CMU_STATUS */ 1115 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */ 1116 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */ 1117 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */ 1118 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 1119 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ 1120 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */ 1121 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */ 1122 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */ 1123 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 1124 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */ 1125 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */ 1126 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */ 1127 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */ 1128 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1129 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */ 1130 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */ 1131 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */ 1132 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */ 1133 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1134 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */ 1135 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */ 1136 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */ 1137 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */ 1138 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1139 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */ 1140 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */ 1141 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */ 1142 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */ 1143 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1144 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */ 1145 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */ 1146 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */ 1147 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */ 1148 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1149 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */ 1150 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */ 1151 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */ 1152 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */ 1153 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1154 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */ 1155 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */ 1156 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */ 1157 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */ 1158 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1159 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */ 1160 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */ 1161 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */ 1162 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */ 1163 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1164 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */ 1165 #define CMU_STATUS_USHFRCOENS (0x1UL << 10) /**< USHFRCO Enable Status */ 1166 #define _CMU_STATUS_USHFRCOENS_SHIFT 10 /**< Shift value for CMU_USHFRCOENS */ 1167 #define _CMU_STATUS_USHFRCOENS_MASK 0x400UL /**< Bit mask for CMU_USHFRCOENS */ 1168 #define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1169 #define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */ 1170 #define CMU_STATUS_USHFRCORDY (0x1UL << 11) /**< USHFRCO Ready */ 1171 #define _CMU_STATUS_USHFRCORDY_SHIFT 11 /**< Shift value for CMU_USHFRCORDY */ 1172 #define _CMU_STATUS_USHFRCORDY_MASK 0x800UL /**< Bit mask for CMU_USHFRCORDY */ 1173 #define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1174 #define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */ 1175 #define CMU_STATUS_DPLLENS (0x1UL << 12) /**< DPLL Enable Status */ 1176 #define _CMU_STATUS_DPLLENS_SHIFT 12 /**< Shift value for CMU_DPLLENS */ 1177 #define _CMU_STATUS_DPLLENS_MASK 0x1000UL /**< Bit mask for CMU_DPLLENS */ 1178 #define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1179 #define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */ 1180 #define CMU_STATUS_DPLLRDY (0x1UL << 13) /**< DPLL Ready */ 1181 #define _CMU_STATUS_DPLLRDY_SHIFT 13 /**< Shift value for CMU_DPLLRDY */ 1182 #define _CMU_STATUS_DPLLRDY_MASK 0x2000UL /**< Bit mask for CMU_DPLLRDY */ 1183 #define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1184 #define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */ 1185 #define CMU_STATUS_CALRDY (0x1UL << 16) /**< Calibration Ready */ 1186 #define _CMU_STATUS_CALRDY_SHIFT 16 /**< Shift value for CMU_CALRDY */ 1187 #define _CMU_STATUS_CALRDY_MASK 0x10000UL /**< Bit mask for CMU_CALRDY */ 1188 #define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */ 1189 #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */ 1190 #define CMU_STATUS_SDIOCLKENS (0x1UL << 17) /**< SDIO Clock Enabled Status */ 1191 #define _CMU_STATUS_SDIOCLKENS_SHIFT 17 /**< Shift value for CMU_SDIOCLKENS */ 1192 #define _CMU_STATUS_SDIOCLKENS_MASK 0x20000UL /**< Bit mask for CMU_SDIOCLKENS */ 1193 #define _CMU_STATUS_SDIOCLKENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1194 #define CMU_STATUS_SDIOCLKENS_DEFAULT (_CMU_STATUS_SDIOCLKENS_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */ 1195 #define CMU_STATUS_QSPI0CLKENS (0x1UL << 18) /**< QSPI0 Clock Enabled Status */ 1196 #define _CMU_STATUS_QSPI0CLKENS_SHIFT 18 /**< Shift value for CMU_QSPI0CLKENS */ 1197 #define _CMU_STATUS_QSPI0CLKENS_MASK 0x40000UL /**< Bit mask for CMU_QSPI0CLKENS */ 1198 #define _CMU_STATUS_QSPI0CLKENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1199 #define CMU_STATUS_QSPI0CLKENS_DEFAULT (_CMU_STATUS_QSPI0CLKENS_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_STATUS */ 1200 #define CMU_STATUS_PDMCLKENS (0x1UL << 19) /**< PDM Clock Enabled Status */ 1201 #define _CMU_STATUS_PDMCLKENS_SHIFT 19 /**< Shift value for CMU_PDMCLKENS */ 1202 #define _CMU_STATUS_PDMCLKENS_MASK 0x80000UL /**< Bit mask for CMU_PDMCLKENS */ 1203 #define _CMU_STATUS_PDMCLKENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1204 #define CMU_STATUS_PDMCLKENS_DEFAULT (_CMU_STATUS_PDMCLKENS_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_STATUS */ 1205 #define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22) /**< HFXO Peak Detection Ready */ 1206 #define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22 /**< Shift value for CMU_HFXOPEAKDETRDY */ 1207 #define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 1208 #define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1209 #define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */ 1210 #define CMU_STATUS_HFXOAMPLOW (0x1UL << 25) /**< HFXO Amplitude Tuning Value Too Low */ 1211 #define _CMU_STATUS_HFXOAMPLOW_SHIFT 25 /**< Shift value for CMU_HFXOAMPLOW */ 1212 #define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL /**< Bit mask for CMU_HFXOAMPLOW */ 1213 #define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1214 #define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_STATUS */ 1215 #define CMU_STATUS_LFXOPHASE (0x1UL << 27) /**< LFXO Clock Phase */ 1216 #define _CMU_STATUS_LFXOPHASE_SHIFT 27 /**< Shift value for CMU_LFXOPHASE */ 1217 #define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOPHASE */ 1218 #define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1219 #define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_STATUS */ 1220 #define CMU_STATUS_LFRCOPHASE (0x1UL << 28) /**< LFRCO Clock Phase */ 1221 #define _CMU_STATUS_LFRCOPHASE_SHIFT 28 /**< Shift value for CMU_LFRCOPHASE */ 1222 #define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOPHASE */ 1223 #define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1224 #define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_STATUS */ 1225 #define CMU_STATUS_ULFRCOPHASE (0x1UL << 29) /**< ULFRCO Clock Phase */ 1226 #define _CMU_STATUS_ULFRCOPHASE_SHIFT 29 /**< Shift value for CMU_ULFRCOPHASE */ 1227 #define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOPHASE */ 1228 #define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 1229 #define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_STATUS */ 1230 1231 /* Bit fields for CMU HFCLKSTATUS */ 1232 #define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL /**< Default value for CMU_HFCLKSTATUS */ 1233 #define _CMU_HFCLKSTATUS_MASK 0x00000007UL /**< Mask for CMU_HFCLKSTATUS */ 1234 #define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0 /**< Shift value for CMU_SELECTED */ 1235 #define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL /**< Bit mask for CMU_SELECTED */ 1236 #define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFCLKSTATUS */ 1237 #define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_HFCLKSTATUS */ 1238 #define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL /**< Mode HFXO for CMU_HFCLKSTATUS */ 1239 #define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_HFCLKSTATUS */ 1240 #define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL /**< Mode LFXO for CMU_HFCLKSTATUS */ 1241 #define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL /**< Mode HFRCODIV2 for CMU_HFCLKSTATUS */ 1242 #define _CMU_HFCLKSTATUS_SELECTED_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_HFCLKSTATUS */ 1243 #define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL /**< Mode CLKIN0 for CMU_HFCLKSTATUS */ 1244 #define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCLKSTATUS */ 1245 #define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0) /**< Shifted mode HFRCO for CMU_HFCLKSTATUS */ 1246 #define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0) /**< Shifted mode HFXO for CMU_HFCLKSTATUS */ 1247 #define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0) /**< Shifted mode LFRCO for CMU_HFCLKSTATUS */ 1248 #define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0) /**< Shifted mode LFXO for CMU_HFCLKSTATUS */ 1249 #define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0) /**< Shifted mode HFRCODIV2 for CMU_HFCLKSTATUS */ 1250 #define CMU_HFCLKSTATUS_SELECTED_USHFRCO (_CMU_HFCLKSTATUS_SELECTED_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_HFCLKSTATUS */ 1251 #define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_HFCLKSTATUS */ 1252 1253 /* Bit fields for CMU HFXOTRIMSTATUS */ 1254 #define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFXOTRIMSTATUS */ 1255 #define _CMU_HFXOTRIMSTATUS_MASK 0xC7FF07FFUL /**< Mask for CMU_HFXOTRIMSTATUS */ 1256 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0 /**< Shift value for CMU_IBTRIMXOCORE */ 1257 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FFUL /**< Bit mask for CMU_IBTRIMXOCORE */ 1258 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ 1259 #define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ 1260 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_SHIFT 16 /**< Shift value for CMU_IBTRIMXOCOREMON */ 1261 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_MASK 0x7FF0000UL /**< Bit mask for CMU_IBTRIMXOCOREMON */ 1262 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ 1263 #define CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCOREMON_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ 1264 #define CMU_HFXOTRIMSTATUS_VALID (0x1UL << 30) /**< Peak Detection Algorithm Found a Value for IBTRIMXOCORE */ 1265 #define _CMU_HFXOTRIMSTATUS_VALID_SHIFT 30 /**< Shift value for CMU_VALID */ 1266 #define _CMU_HFXOTRIMSTATUS_VALID_MASK 0x40000000UL /**< Bit mask for CMU_VALID */ 1267 #define _CMU_HFXOTRIMSTATUS_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ 1268 #define CMU_HFXOTRIMSTATUS_VALID_DEFAULT (_CMU_HFXOTRIMSTATUS_VALID_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ 1269 #define CMU_HFXOTRIMSTATUS_MONVALID (0x1UL << 31) /**< Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON */ 1270 #define _CMU_HFXOTRIMSTATUS_MONVALID_SHIFT 31 /**< Shift value for CMU_MONVALID */ 1271 #define _CMU_HFXOTRIMSTATUS_MONVALID_MASK 0x80000000UL /**< Bit mask for CMU_MONVALID */ 1272 #define _CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFXOTRIMSTATUS */ 1273 #define CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT (_CMU_HFXOTRIMSTATUS_MONVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_HFXOTRIMSTATUS */ 1274 1275 /* Bit fields for CMU IF */ 1276 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */ 1277 #define _CMU_IF_MASK 0xB803EBFFUL /**< Mask for CMU_IF */ 1278 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */ 1279 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1280 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1281 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */ 1282 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ 1283 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */ 1284 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1285 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1286 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1287 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ 1288 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */ 1289 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1290 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1291 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1292 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */ 1293 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */ 1294 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1295 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1296 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1297 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */ 1298 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */ 1299 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1300 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1301 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1302 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */ 1303 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */ 1304 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1305 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1306 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1307 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */ 1308 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */ 1309 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1310 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1311 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1312 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */ 1313 #define CMU_IF_USHFRCORDY (0x1UL << 7) /**< USHFRCO Ready Interrupt Flag */ 1314 #define _CMU_IF_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ 1315 #define _CMU_IF_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ 1316 #define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1317 #define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */ 1318 #define CMU_IF_HFXODISERR (0x1UL << 8) /**< HFXO Disable Error Interrupt Flag */ 1319 #define _CMU_IF_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 1320 #define _CMU_IF_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 1321 #define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1322 #define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */ 1323 #define CMU_IF_HFXOAUTOSW (0x1UL << 9) /**< HFXO Automatic Switch Interrupt Flag */ 1324 #define _CMU_IF_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 1325 #define _CMU_IF_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 1326 #define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1327 #define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */ 1328 #define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXO Automatic Peak Detection Ready Interrupt Flag */ 1329 #define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 1330 #define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 1331 #define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1332 #define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IF */ 1333 #define CMU_IF_HFRCODIS (0x1UL << 13) /**< HFRCO Disable Interrupt Flag */ 1334 #define _CMU_IF_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 1335 #define _CMU_IF_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 1336 #define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1337 #define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IF */ 1338 #define CMU_IF_LFTIMEOUTERR (0x1UL << 14) /**< Low Frequency Timeout Error Interrupt Flag */ 1339 #define _CMU_IF_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 1340 #define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 1341 #define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1342 #define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IF */ 1343 #define CMU_IF_DPLLRDY (0x1UL << 15) /**< DPLL Lock Interrupt Flag */ 1344 #define _CMU_IF_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 1345 #define _CMU_IF_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 1346 #define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1347 #define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IF */ 1348 #define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLL Lock Failure Low Interrupt Flag */ 1349 #define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 1350 #define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 1351 #define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1352 #define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IF */ 1353 #define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLL Lock Failure Low Interrupt Flag */ 1354 #define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 1355 #define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 1356 #define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1357 #define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IF */ 1358 #define CMU_IF_LFXOEDGE (0x1UL << 27) /**< LFXO Clock Edge Detected Interrupt Flag */ 1359 #define _CMU_IF_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 1360 #define _CMU_IF_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 1361 #define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1362 #define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IF */ 1363 #define CMU_IF_LFRCOEDGE (0x1UL << 28) /**< LFRCO Clock Edge Detected Interrupt Flag */ 1364 #define _CMU_IF_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 1365 #define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 1366 #define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1367 #define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IF */ 1368 #define CMU_IF_ULFRCOEDGE (0x1UL << 29) /**< ULFRCO Clock Edge Detected Interrupt Flag */ 1369 #define _CMU_IF_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 1370 #define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 1371 #define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1372 #define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IF */ 1373 #define CMU_IF_CMUERR (0x1UL << 31) /**< CMU Error Interrupt Flag */ 1374 #define _CMU_IF_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 1375 #define _CMU_IF_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 1376 #define _CMU_IF_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 1377 #define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IF */ 1378 1379 /* Bit fields for CMU IFS */ 1380 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */ 1381 #define _CMU_IFS_MASK 0xB803EBFFUL /**< Mask for CMU_IFS */ 1382 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< Set HFRCORDY Interrupt Flag */ 1383 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1384 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1385 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1386 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */ 1387 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< Set HFXORDY Interrupt Flag */ 1388 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1389 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1390 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1391 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */ 1392 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< Set LFRCORDY Interrupt Flag */ 1393 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1394 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1395 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1396 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */ 1397 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< Set LFXORDY Interrupt Flag */ 1398 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1399 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1400 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1401 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */ 1402 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< Set AUXHFRCORDY Interrupt Flag */ 1403 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1404 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1405 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1406 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */ 1407 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Set CALRDY Interrupt Flag */ 1408 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1409 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1410 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1411 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */ 1412 #define CMU_IFS_CALOF (0x1UL << 6) /**< Set CALOF Interrupt Flag */ 1413 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1414 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1415 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1416 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */ 1417 #define CMU_IFS_USHFRCORDY (0x1UL << 7) /**< Set USHFRCORDY Interrupt Flag */ 1418 #define _CMU_IFS_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ 1419 #define _CMU_IFS_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ 1420 #define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1421 #define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */ 1422 #define CMU_IFS_HFXODISERR (0x1UL << 8) /**< Set HFXODISERR Interrupt Flag */ 1423 #define _CMU_IFS_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 1424 #define _CMU_IFS_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 1425 #define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1426 #define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */ 1427 #define CMU_IFS_HFXOAUTOSW (0x1UL << 9) /**< Set HFXOAUTOSW Interrupt Flag */ 1428 #define _CMU_IFS_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 1429 #define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 1430 #define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1431 #define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */ 1432 #define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11) /**< Set HFXOPEAKDETRDY Interrupt Flag */ 1433 #define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 1434 #define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 1435 #define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1436 #define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFS */ 1437 #define CMU_IFS_HFRCODIS (0x1UL << 13) /**< Set HFRCODIS Interrupt Flag */ 1438 #define _CMU_IFS_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 1439 #define _CMU_IFS_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 1440 #define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1441 #define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFS */ 1442 #define CMU_IFS_LFTIMEOUTERR (0x1UL << 14) /**< Set LFTIMEOUTERR Interrupt Flag */ 1443 #define _CMU_IFS_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 1444 #define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 1445 #define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1446 #define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFS */ 1447 #define CMU_IFS_DPLLRDY (0x1UL << 15) /**< Set DPLLRDY Interrupt Flag */ 1448 #define _CMU_IFS_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 1449 #define _CMU_IFS_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 1450 #define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1451 #define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFS */ 1452 #define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16) /**< Set DPLLLOCKFAILLOW Interrupt Flag */ 1453 #define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 1454 #define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 1455 #define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1456 #define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFS */ 1457 #define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Set DPLLLOCKFAILHIGH Interrupt Flag */ 1458 #define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 1459 #define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 1460 #define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1461 #define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFS */ 1462 #define CMU_IFS_LFXOEDGE (0x1UL << 27) /**< Set LFXOEDGE Interrupt Flag */ 1463 #define _CMU_IFS_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 1464 #define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 1465 #define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1466 #define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFS */ 1467 #define CMU_IFS_LFRCOEDGE (0x1UL << 28) /**< Set LFRCOEDGE Interrupt Flag */ 1468 #define _CMU_IFS_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 1469 #define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 1470 #define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1471 #define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFS */ 1472 #define CMU_IFS_ULFRCOEDGE (0x1UL << 29) /**< Set ULFRCOEDGE Interrupt Flag */ 1473 #define _CMU_IFS_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 1474 #define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 1475 #define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1476 #define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFS */ 1477 #define CMU_IFS_CMUERR (0x1UL << 31) /**< Set CMUERR Interrupt Flag */ 1478 #define _CMU_IFS_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 1479 #define _CMU_IFS_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 1480 #define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */ 1481 #define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFS */ 1482 1483 /* Bit fields for CMU IFC */ 1484 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */ 1485 #define _CMU_IFC_MASK 0xB803EBFFUL /**< Mask for CMU_IFC */ 1486 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< Clear HFRCORDY Interrupt Flag */ 1487 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1488 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1489 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1490 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */ 1491 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< Clear HFXORDY Interrupt Flag */ 1492 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1493 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1494 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1495 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */ 1496 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< Clear LFRCORDY Interrupt Flag */ 1497 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1498 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1499 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1500 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */ 1501 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< Clear LFXORDY Interrupt Flag */ 1502 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1503 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1504 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1505 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */ 1506 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< Clear AUXHFRCORDY Interrupt Flag */ 1507 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1508 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1509 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1510 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */ 1511 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Clear CALRDY Interrupt Flag */ 1512 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1513 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1514 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1515 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */ 1516 #define CMU_IFC_CALOF (0x1UL << 6) /**< Clear CALOF Interrupt Flag */ 1517 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1518 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1519 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1520 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */ 1521 #define CMU_IFC_USHFRCORDY (0x1UL << 7) /**< Clear USHFRCORDY Interrupt Flag */ 1522 #define _CMU_IFC_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ 1523 #define _CMU_IFC_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ 1524 #define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1525 #define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */ 1526 #define CMU_IFC_HFXODISERR (0x1UL << 8) /**< Clear HFXODISERR Interrupt Flag */ 1527 #define _CMU_IFC_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 1528 #define _CMU_IFC_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 1529 #define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1530 #define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */ 1531 #define CMU_IFC_HFXOAUTOSW (0x1UL << 9) /**< Clear HFXOAUTOSW Interrupt Flag */ 1532 #define _CMU_IFC_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 1533 #define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 1534 #define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1535 #define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */ 1536 #define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11) /**< Clear HFXOPEAKDETRDY Interrupt Flag */ 1537 #define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 1538 #define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 1539 #define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1540 #define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IFC */ 1541 #define CMU_IFC_HFRCODIS (0x1UL << 13) /**< Clear HFRCODIS Interrupt Flag */ 1542 #define _CMU_IFC_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 1543 #define _CMU_IFC_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 1544 #define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1545 #define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IFC */ 1546 #define CMU_IFC_LFTIMEOUTERR (0x1UL << 14) /**< Clear LFTIMEOUTERR Interrupt Flag */ 1547 #define _CMU_IFC_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 1548 #define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 1549 #define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1550 #define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IFC */ 1551 #define CMU_IFC_DPLLRDY (0x1UL << 15) /**< Clear DPLLRDY Interrupt Flag */ 1552 #define _CMU_IFC_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 1553 #define _CMU_IFC_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 1554 #define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1555 #define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IFC */ 1556 #define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16) /**< Clear DPLLLOCKFAILLOW Interrupt Flag */ 1557 #define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 1558 #define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 1559 #define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1560 #define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IFC */ 1561 #define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17) /**< Clear DPLLLOCKFAILHIGH Interrupt Flag */ 1562 #define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 1563 #define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 1564 #define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1565 #define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IFC */ 1566 #define CMU_IFC_LFXOEDGE (0x1UL << 27) /**< Clear LFXOEDGE Interrupt Flag */ 1567 #define _CMU_IFC_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 1568 #define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 1569 #define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1570 #define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IFC */ 1571 #define CMU_IFC_LFRCOEDGE (0x1UL << 28) /**< Clear LFRCOEDGE Interrupt Flag */ 1572 #define _CMU_IFC_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 1573 #define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 1574 #define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1575 #define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IFC */ 1576 #define CMU_IFC_ULFRCOEDGE (0x1UL << 29) /**< Clear ULFRCOEDGE Interrupt Flag */ 1577 #define _CMU_IFC_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 1578 #define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 1579 #define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1580 #define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IFC */ 1581 #define CMU_IFC_CMUERR (0x1UL << 31) /**< Clear CMUERR Interrupt Flag */ 1582 #define _CMU_IFC_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 1583 #define _CMU_IFC_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 1584 #define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */ 1585 #define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IFC */ 1586 1587 /* Bit fields for CMU IEN */ 1588 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ 1589 #define _CMU_IEN_MASK 0xB803EBFFUL /**< Mask for CMU_IEN */ 1590 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCORDY Interrupt Enable */ 1591 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */ 1592 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */ 1593 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1594 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ 1595 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXORDY Interrupt Enable */ 1596 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */ 1597 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */ 1598 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1599 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ 1600 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCORDY Interrupt Enable */ 1601 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */ 1602 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */ 1603 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1604 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */ 1605 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXORDY Interrupt Enable */ 1606 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */ 1607 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */ 1608 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1609 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */ 1610 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCORDY Interrupt Enable */ 1611 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */ 1612 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */ 1613 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1614 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */ 1615 #define CMU_IEN_CALRDY (0x1UL << 5) /**< CALRDY Interrupt Enable */ 1616 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */ 1617 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */ 1618 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1619 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */ 1620 #define CMU_IEN_CALOF (0x1UL << 6) /**< CALOF Interrupt Enable */ 1621 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */ 1622 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */ 1623 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1624 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */ 1625 #define CMU_IEN_USHFRCORDY (0x1UL << 7) /**< USHFRCORDY Interrupt Enable */ 1626 #define _CMU_IEN_USHFRCORDY_SHIFT 7 /**< Shift value for CMU_USHFRCORDY */ 1627 #define _CMU_IEN_USHFRCORDY_MASK 0x80UL /**< Bit mask for CMU_USHFRCORDY */ 1628 #define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1629 #define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */ 1630 #define CMU_IEN_HFXODISERR (0x1UL << 8) /**< HFXODISERR Interrupt Enable */ 1631 #define _CMU_IEN_HFXODISERR_SHIFT 8 /**< Shift value for CMU_HFXODISERR */ 1632 #define _CMU_IEN_HFXODISERR_MASK 0x100UL /**< Bit mask for CMU_HFXODISERR */ 1633 #define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1634 #define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */ 1635 #define CMU_IEN_HFXOAUTOSW (0x1UL << 9) /**< HFXOAUTOSW Interrupt Enable */ 1636 #define _CMU_IEN_HFXOAUTOSW_SHIFT 9 /**< Shift value for CMU_HFXOAUTOSW */ 1637 #define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL /**< Bit mask for CMU_HFXOAUTOSW */ 1638 #define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1639 #define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */ 1640 #define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11) /**< HFXOPEAKDETRDY Interrupt Enable */ 1641 #define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11 /**< Shift value for CMU_HFXOPEAKDETRDY */ 1642 #define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL /**< Bit mask for CMU_HFXOPEAKDETRDY */ 1643 #define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1644 #define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_IEN */ 1645 #define CMU_IEN_HFRCODIS (0x1UL << 13) /**< HFRCODIS Interrupt Enable */ 1646 #define _CMU_IEN_HFRCODIS_SHIFT 13 /**< Shift value for CMU_HFRCODIS */ 1647 #define _CMU_IEN_HFRCODIS_MASK 0x2000UL /**< Bit mask for CMU_HFRCODIS */ 1648 #define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1649 #define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_IEN */ 1650 #define CMU_IEN_LFTIMEOUTERR (0x1UL << 14) /**< LFTIMEOUTERR Interrupt Enable */ 1651 #define _CMU_IEN_LFTIMEOUTERR_SHIFT 14 /**< Shift value for CMU_LFTIMEOUTERR */ 1652 #define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL /**< Bit mask for CMU_LFTIMEOUTERR */ 1653 #define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1654 #define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_IEN */ 1655 #define CMU_IEN_DPLLRDY (0x1UL << 15) /**< DPLLRDY Interrupt Enable */ 1656 #define _CMU_IEN_DPLLRDY_SHIFT 15 /**< Shift value for CMU_DPLLRDY */ 1657 #define _CMU_IEN_DPLLRDY_MASK 0x8000UL /**< Bit mask for CMU_DPLLRDY */ 1658 #define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1659 #define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_IEN */ 1660 #define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16) /**< DPLLLOCKFAILLOW Interrupt Enable */ 1661 #define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16 /**< Shift value for CMU_DPLLLOCKFAILLOW */ 1662 #define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL /**< Bit mask for CMU_DPLLLOCKFAILLOW */ 1663 #define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1664 #define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_IEN */ 1665 #define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17) /**< DPLLLOCKFAILHIGH Interrupt Enable */ 1666 #define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17 /**< Shift value for CMU_DPLLLOCKFAILHIGH */ 1667 #define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL /**< Bit mask for CMU_DPLLLOCKFAILHIGH */ 1668 #define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1669 #define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_IEN */ 1670 #define CMU_IEN_LFXOEDGE (0x1UL << 27) /**< LFXOEDGE Interrupt Enable */ 1671 #define _CMU_IEN_LFXOEDGE_SHIFT 27 /**< Shift value for CMU_LFXOEDGE */ 1672 #define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL /**< Bit mask for CMU_LFXOEDGE */ 1673 #define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1674 #define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_IEN */ 1675 #define CMU_IEN_LFRCOEDGE (0x1UL << 28) /**< LFRCOEDGE Interrupt Enable */ 1676 #define _CMU_IEN_LFRCOEDGE_SHIFT 28 /**< Shift value for CMU_LFRCOEDGE */ 1677 #define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL /**< Bit mask for CMU_LFRCOEDGE */ 1678 #define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1679 #define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_IEN */ 1680 #define CMU_IEN_ULFRCOEDGE (0x1UL << 29) /**< ULFRCOEDGE Interrupt Enable */ 1681 #define _CMU_IEN_ULFRCOEDGE_SHIFT 29 /**< Shift value for CMU_ULFRCOEDGE */ 1682 #define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL /**< Bit mask for CMU_ULFRCOEDGE */ 1683 #define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1684 #define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_IEN */ 1685 #define CMU_IEN_CMUERR (0x1UL << 31) /**< CMUERR Interrupt Enable */ 1686 #define _CMU_IEN_CMUERR_SHIFT 31 /**< Shift value for CMU_CMUERR */ 1687 #define _CMU_IEN_CMUERR_MASK 0x80000000UL /**< Bit mask for CMU_CMUERR */ 1688 #define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 1689 #define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_IEN */ 1690 1691 /* Bit fields for CMU HFBUSCLKEN0 */ 1692 #define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSCLKEN0 */ 1693 #define _CMU_HFBUSCLKEN0_MASK 0x000003FFUL /**< Mask for CMU_HFBUSCLKEN0 */ 1694 #define CMU_HFBUSCLKEN0_LE (0x1UL << 0) /**< Low Energy Peripheral Interface Clock Enable */ 1695 #define _CMU_HFBUSCLKEN0_LE_SHIFT 0 /**< Shift value for CMU_LE */ 1696 #define _CMU_HFBUSCLKEN0_LE_MASK 0x1UL /**< Bit mask for CMU_LE */ 1697 #define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1698 #define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1699 #define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */ 1700 #define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 1 /**< Shift value for CMU_CRYPTO0 */ 1701 #define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x2UL /**< Bit mask for CMU_CRYPTO0 */ 1702 #define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1703 #define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1704 #define CMU_HFBUSCLKEN0_EBI (0x1UL << 2) /**< External Bus Interface Clock Enable */ 1705 #define _CMU_HFBUSCLKEN0_EBI_SHIFT 2 /**< Shift value for CMU_EBI */ 1706 #define _CMU_HFBUSCLKEN0_EBI_MASK 0x4UL /**< Bit mask for CMU_EBI */ 1707 #define _CMU_HFBUSCLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1708 #define CMU_HFBUSCLKEN0_EBI_DEFAULT (_CMU_HFBUSCLKEN0_EBI_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1709 #define CMU_HFBUSCLKEN0_SDIO (0x1UL << 3) /**< SDIO Controller Clock Enable */ 1710 #define _CMU_HFBUSCLKEN0_SDIO_SHIFT 3 /**< Shift value for CMU_SDIO */ 1711 #define _CMU_HFBUSCLKEN0_SDIO_MASK 0x8UL /**< Bit mask for CMU_SDIO */ 1712 #define _CMU_HFBUSCLKEN0_SDIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1713 #define CMU_HFBUSCLKEN0_SDIO_DEFAULT (_CMU_HFBUSCLKEN0_SDIO_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1714 #define CMU_HFBUSCLKEN0_GPIO (0x1UL << 4) /**< General purpose Input/Output Clock Enable */ 1715 #define _CMU_HFBUSCLKEN0_GPIO_SHIFT 4 /**< Shift value for CMU_GPIO */ 1716 #define _CMU_HFBUSCLKEN0_GPIO_MASK 0x10UL /**< Bit mask for CMU_GPIO */ 1717 #define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1718 #define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1719 #define CMU_HFBUSCLKEN0_PRS (0x1UL << 5) /**< Peripheral Reflex System Clock Enable */ 1720 #define _CMU_HFBUSCLKEN0_PRS_SHIFT 5 /**< Shift value for CMU_PRS */ 1721 #define _CMU_HFBUSCLKEN0_PRS_MASK 0x20UL /**< Bit mask for CMU_PRS */ 1722 #define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1723 #define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1724 #define CMU_HFBUSCLKEN0_LDMA (0x1UL << 6) /**< Linked Direct Memory Access Controller Clock Enable */ 1725 #define _CMU_HFBUSCLKEN0_LDMA_SHIFT 6 /**< Shift value for CMU_LDMA */ 1726 #define _CMU_HFBUSCLKEN0_LDMA_MASK 0x40UL /**< Bit mask for CMU_LDMA */ 1727 #define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1728 #define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1729 #define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 7) /**< General Purpose CRC Clock Enable */ 1730 #define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 7 /**< Shift value for CMU_GPCRC */ 1731 #define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x80UL /**< Bit mask for CMU_GPCRC */ 1732 #define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1733 #define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1734 #define CMU_HFBUSCLKEN0_QSPI0 (0x1UL << 8) /**< Quad-SPI Clock Enable */ 1735 #define _CMU_HFBUSCLKEN0_QSPI0_SHIFT 8 /**< Shift value for CMU_QSPI0 */ 1736 #define _CMU_HFBUSCLKEN0_QSPI0_MASK 0x100UL /**< Bit mask for CMU_QSPI0 */ 1737 #define _CMU_HFBUSCLKEN0_QSPI0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1738 #define CMU_HFBUSCLKEN0_QSPI0_DEFAULT (_CMU_HFBUSCLKEN0_QSPI0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1739 #define CMU_HFBUSCLKEN0_USB (0x1UL << 9) /**< Universal Serial Bus Interface Clock Enable */ 1740 #define _CMU_HFBUSCLKEN0_USB_SHIFT 9 /**< Shift value for CMU_USB */ 1741 #define _CMU_HFBUSCLKEN0_USB_MASK 0x200UL /**< Bit mask for CMU_USB */ 1742 #define _CMU_HFBUSCLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSCLKEN0 */ 1743 #define CMU_HFBUSCLKEN0_USB_DEFAULT (_CMU_HFBUSCLKEN0_USB_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFBUSCLKEN0 */ 1744 1745 /* Bit fields for CMU HFPERCLKEN0 */ 1746 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */ 1747 #define _CMU_HFPERCLKEN0_MASK 0x000FFFFFUL /**< Mask for CMU_HFPERCLKEN0 */ 1748 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */ 1749 #define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */ 1750 #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */ 1751 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1752 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1753 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */ 1754 #define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */ 1755 #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */ 1756 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1757 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1758 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */ 1759 #define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */ 1760 #define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */ 1761 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1762 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1763 #define CMU_HFPERCLKEN0_USART3 (0x1UL << 3) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable */ 1764 #define _CMU_HFPERCLKEN0_USART3_SHIFT 3 /**< Shift value for CMU_USART3 */ 1765 #define _CMU_HFPERCLKEN0_USART3_MASK 0x8UL /**< Bit mask for CMU_USART3 */ 1766 #define _CMU_HFPERCLKEN0_USART3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1767 #define CMU_HFPERCLKEN0_USART3_DEFAULT (_CMU_HFPERCLKEN0_USART3_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1768 #define CMU_HFPERCLKEN0_USART4 (0x1UL << 4) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable */ 1769 #define _CMU_HFPERCLKEN0_USART4_SHIFT 4 /**< Shift value for CMU_USART4 */ 1770 #define _CMU_HFPERCLKEN0_USART4_MASK 0x10UL /**< Bit mask for CMU_USART4 */ 1771 #define _CMU_HFPERCLKEN0_USART4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1772 #define CMU_HFPERCLKEN0_USART4_DEFAULT (_CMU_HFPERCLKEN0_USART4_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1773 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */ 1774 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */ 1775 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */ 1776 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1777 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1778 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */ 1779 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */ 1780 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */ 1781 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1782 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1783 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */ 1784 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */ 1785 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */ 1786 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1787 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1788 #define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */ 1789 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */ 1790 #define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */ 1791 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1792 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1793 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */ 1794 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */ 1795 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */ 1796 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1797 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1798 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */ 1799 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */ 1800 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */ 1801 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1802 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1803 #define CMU_HFPERCLKEN0_ACMP2 (0x1UL << 11) /**< Analog Comparator 2 Clock Enable */ 1804 #define _CMU_HFPERCLKEN0_ACMP2_SHIFT 11 /**< Shift value for CMU_ACMP2 */ 1805 #define _CMU_HFPERCLKEN0_ACMP2_MASK 0x800UL /**< Bit mask for CMU_ACMP2 */ 1806 #define _CMU_HFPERCLKEN0_ACMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1807 #define CMU_HFPERCLKEN0_ACMP2_DEFAULT (_CMU_HFPERCLKEN0_ACMP2_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1808 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 12) /**< I2C 0 Clock Enable */ 1809 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 12 /**< Shift value for CMU_I2C0 */ 1810 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x1000UL /**< Bit mask for CMU_I2C0 */ 1811 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1812 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1813 #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 13) /**< I2C 1 Clock Enable */ 1814 #define _CMU_HFPERCLKEN0_I2C1_SHIFT 13 /**< Shift value for CMU_I2C1 */ 1815 #define _CMU_HFPERCLKEN0_I2C1_MASK 0x2000UL /**< Bit mask for CMU_I2C1 */ 1816 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1817 #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1818 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 14) /**< Analog to Digital Converter 0 Clock Enable */ 1819 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 14 /**< Shift value for CMU_ADC0 */ 1820 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x4000UL /**< Bit mask for CMU_ADC0 */ 1821 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1822 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1823 #define CMU_HFPERCLKEN0_ADC1 (0x1UL << 15) /**< Analog to Digital Converter 0 Clock Enable */ 1824 #define _CMU_HFPERCLKEN0_ADC1_SHIFT 15 /**< Shift value for CMU_ADC1 */ 1825 #define _CMU_HFPERCLKEN0_ADC1_MASK 0x8000UL /**< Bit mask for CMU_ADC1 */ 1826 #define _CMU_HFPERCLKEN0_ADC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1827 #define CMU_HFPERCLKEN0_ADC1_DEFAULT (_CMU_HFPERCLKEN0_ADC1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1828 #define CMU_HFPERCLKEN0_PDM (0x1UL << 16) /**< PDM Interface Clock Enable */ 1829 #define _CMU_HFPERCLKEN0_PDM_SHIFT 16 /**< Shift value for CMU_PDM */ 1830 #define _CMU_HFPERCLKEN0_PDM_MASK 0x10000UL /**< Bit mask for CMU_PDM */ 1831 #define _CMU_HFPERCLKEN0_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1832 #define CMU_HFPERCLKEN0_PDM_DEFAULT (_CMU_HFPERCLKEN0_PDM_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1833 #define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 17) /**< CRYOTIMER Clock Enable */ 1834 #define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 17 /**< Shift value for CMU_CRYOTIMER */ 1835 #define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x20000UL /**< Bit mask for CMU_CRYOTIMER */ 1836 #define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1837 #define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1838 #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 18) /**< Current Digital to Analog Converter 0 Clock Enable */ 1839 #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 18 /**< Shift value for CMU_IDAC0 */ 1840 #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x40000UL /**< Bit mask for CMU_IDAC0 */ 1841 #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1842 #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1843 #define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 19) /**< True Random Number Generator 0 Clock Enable */ 1844 #define _CMU_HFPERCLKEN0_TRNG0_SHIFT 19 /**< Shift value for CMU_TRNG0 */ 1845 #define _CMU_HFPERCLKEN0_TRNG0_MASK 0x80000UL /**< Bit mask for CMU_TRNG0 */ 1846 #define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ 1847 #define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ 1848 1849 /* Bit fields for CMU HFPERCLKEN1 */ 1850 #define _CMU_HFPERCLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN1 */ 1851 #define _CMU_HFPERCLKEN1_MASK 0x000000FFUL /**< Mask for CMU_HFPERCLKEN1 */ 1852 #define CMU_HFPERCLKEN1_UART0 (0x1UL << 0) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */ 1853 #define _CMU_HFPERCLKEN1_UART0_SHIFT 0 /**< Shift value for CMU_UART0 */ 1854 #define _CMU_HFPERCLKEN1_UART0_MASK 0x1UL /**< Bit mask for CMU_UART0 */ 1855 #define _CMU_HFPERCLKEN1_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 1856 #define CMU_HFPERCLKEN1_UART0_DEFAULT (_CMU_HFPERCLKEN1_UART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 1857 #define CMU_HFPERCLKEN1_UART1 (0x1UL << 1) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */ 1858 #define _CMU_HFPERCLKEN1_UART1_SHIFT 1 /**< Shift value for CMU_UART1 */ 1859 #define _CMU_HFPERCLKEN1_UART1_MASK 0x2UL /**< Bit mask for CMU_UART1 */ 1860 #define _CMU_HFPERCLKEN1_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 1861 #define CMU_HFPERCLKEN1_UART1_DEFAULT (_CMU_HFPERCLKEN1_UART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 1862 #define CMU_HFPERCLKEN1_WTIMER0 (0x1UL << 2) /**< Wide Timer 0 Clock Enable */ 1863 #define _CMU_HFPERCLKEN1_WTIMER0_SHIFT 2 /**< Shift value for CMU_WTIMER0 */ 1864 #define _CMU_HFPERCLKEN1_WTIMER0_MASK 0x4UL /**< Bit mask for CMU_WTIMER0 */ 1865 #define _CMU_HFPERCLKEN1_WTIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 1866 #define CMU_HFPERCLKEN1_WTIMER0_DEFAULT (_CMU_HFPERCLKEN1_WTIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 1867 #define CMU_HFPERCLKEN1_WTIMER1 (0x1UL << 3) /**< Wide Timer 0 Clock Enable */ 1868 #define _CMU_HFPERCLKEN1_WTIMER1_SHIFT 3 /**< Shift value for CMU_WTIMER1 */ 1869 #define _CMU_HFPERCLKEN1_WTIMER1_MASK 0x8UL /**< Bit mask for CMU_WTIMER1 */ 1870 #define _CMU_HFPERCLKEN1_WTIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 1871 #define CMU_HFPERCLKEN1_WTIMER1_DEFAULT (_CMU_HFPERCLKEN1_WTIMER1_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 1872 #define CMU_HFPERCLKEN1_CAN0 (0x1UL << 4) /**< CAN 0 Clock Enable */ 1873 #define _CMU_HFPERCLKEN1_CAN0_SHIFT 4 /**< Shift value for CMU_CAN0 */ 1874 #define _CMU_HFPERCLKEN1_CAN0_MASK 0x10UL /**< Bit mask for CMU_CAN0 */ 1875 #define _CMU_HFPERCLKEN1_CAN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 1876 #define CMU_HFPERCLKEN1_CAN0_DEFAULT (_CMU_HFPERCLKEN1_CAN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 1877 #define CMU_HFPERCLKEN1_CAN1 (0x1UL << 5) /**< CAN 1 Clock Enable */ 1878 #define _CMU_HFPERCLKEN1_CAN1_SHIFT 5 /**< Shift value for CMU_CAN1 */ 1879 #define _CMU_HFPERCLKEN1_CAN1_MASK 0x20UL /**< Bit mask for CMU_CAN1 */ 1880 #define _CMU_HFPERCLKEN1_CAN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 1881 #define CMU_HFPERCLKEN1_CAN1_DEFAULT (_CMU_HFPERCLKEN1_CAN1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 1882 #define CMU_HFPERCLKEN1_VDAC0 (0x1UL << 6) /**< Digital to Analog Converter 0 Clock Enable */ 1883 #define _CMU_HFPERCLKEN1_VDAC0_SHIFT 6 /**< Shift value for CMU_VDAC0 */ 1884 #define _CMU_HFPERCLKEN1_VDAC0_MASK 0x40UL /**< Bit mask for CMU_VDAC0 */ 1885 #define _CMU_HFPERCLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 1886 #define CMU_HFPERCLKEN1_VDAC0_DEFAULT (_CMU_HFPERCLKEN1_VDAC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 1887 #define CMU_HFPERCLKEN1_CSEN (0x1UL << 7) /**< Capacitive touch sense module Clock Enable */ 1888 #define _CMU_HFPERCLKEN1_CSEN_SHIFT 7 /**< Shift value for CMU_CSEN */ 1889 #define _CMU_HFPERCLKEN1_CSEN_MASK 0x80UL /**< Bit mask for CMU_CSEN */ 1890 #define _CMU_HFPERCLKEN1_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN1 */ 1891 #define CMU_HFPERCLKEN1_CSEN_DEFAULT (_CMU_HFPERCLKEN1_CSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN1 */ 1892 1893 /* Bit fields for CMU LFACLKEN0 */ 1894 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */ 1895 #define _CMU_LFACLKEN0_MASK 0x0000001FUL /**< Mask for CMU_LFACLKEN0 */ 1896 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0) /**< Low Energy Timer 0 Clock Enable */ 1897 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ 1898 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL /**< Bit mask for CMU_LETIMER0 */ 1899 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 1900 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 1901 #define CMU_LFACLKEN0_LETIMER1 (0x1UL << 1) /**< Low Energy Timer 1 Clock Enable */ 1902 #define _CMU_LFACLKEN0_LETIMER1_SHIFT 1 /**< Shift value for CMU_LETIMER1 */ 1903 #define _CMU_LFACLKEN0_LETIMER1_MASK 0x2UL /**< Bit mask for CMU_LETIMER1 */ 1904 #define _CMU_LFACLKEN0_LETIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 1905 #define CMU_LFACLKEN0_LETIMER1_DEFAULT (_CMU_LFACLKEN0_LETIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 1906 #define CMU_LFACLKEN0_LESENSE (0x1UL << 2) /**< Low Energy Sensor Interface Clock Enable */ 1907 #define _CMU_LFACLKEN0_LESENSE_SHIFT 2 /**< Shift value for CMU_LESENSE */ 1908 #define _CMU_LFACLKEN0_LESENSE_MASK 0x4UL /**< Bit mask for CMU_LESENSE */ 1909 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 1910 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 1911 #define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */ 1912 #define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */ 1913 #define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */ 1914 #define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 1915 #define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 1916 #define CMU_LFACLKEN0_RTC (0x1UL << 4) /**< Real-Time Counter Clock Enable */ 1917 #define _CMU_LFACLKEN0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */ 1918 #define _CMU_LFACLKEN0_RTC_MASK 0x10UL /**< Bit mask for CMU_RTC */ 1919 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */ 1920 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */ 1921 1922 /* Bit fields for CMU LFBCLKEN0 */ 1923 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */ 1924 #define _CMU_LFBCLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFBCLKEN0 */ 1925 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */ 1926 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ 1927 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */ 1928 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 1929 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 1930 #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */ 1931 #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */ 1932 #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */ 1933 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 1934 #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 1935 #define CMU_LFBCLKEN0_SYSTICK (0x1UL << 2) /**< Clock Enable */ 1936 #define _CMU_LFBCLKEN0_SYSTICK_SHIFT 2 /**< Shift value for CMU_SYSTICK */ 1937 #define _CMU_LFBCLKEN0_SYSTICK_MASK 0x4UL /**< Bit mask for CMU_SYSTICK */ 1938 #define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 1939 #define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 1940 #define CMU_LFBCLKEN0_CSEN (0x1UL << 3) /**< Capacitive touch sense module Clock Enable */ 1941 #define _CMU_LFBCLKEN0_CSEN_SHIFT 3 /**< Shift value for CMU_CSEN */ 1942 #define _CMU_LFBCLKEN0_CSEN_MASK 0x8UL /**< Bit mask for CMU_CSEN */ 1943 #define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */ 1944 #define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */ 1945 1946 /* Bit fields for CMU LFCCLKEN0 */ 1947 #define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */ 1948 #define _CMU_LFCCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFCCLKEN0 */ 1949 #define CMU_LFCCLKEN0_USB (0x1UL << 0) /**< Universal Serial Bus Interface Clock Enable */ 1950 #define _CMU_LFCCLKEN0_USB_SHIFT 0 /**< Shift value for CMU_USB */ 1951 #define _CMU_LFCCLKEN0_USB_MASK 0x1UL /**< Bit mask for CMU_USB */ 1952 #define _CMU_LFCCLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKEN0 */ 1953 #define CMU_LFCCLKEN0_USB_DEFAULT (_CMU_LFCCLKEN0_USB_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKEN0 */ 1954 1955 /* Bit fields for CMU LFECLKEN0 */ 1956 #define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFECLKEN0 */ 1957 #define _CMU_LFECLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFECLKEN0 */ 1958 #define CMU_LFECLKEN0_RTCC (0x1UL << 0) /**< Real-Time Counter and Calendar Clock Enable */ 1959 #define _CMU_LFECLKEN0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ 1960 #define _CMU_LFECLKEN0_RTCC_MASK 0x1UL /**< Bit mask for CMU_RTCC */ 1961 #define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFECLKEN0 */ 1962 #define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFECLKEN0 */ 1963 1964 /* Bit fields for CMU HFPRESC */ 1965 #define _CMU_HFPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPRESC */ 1966 #define _CMU_HFPRESC_MASK 0x03001F00UL /**< Mask for CMU_HFPRESC */ 1967 #define _CMU_HFPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 1968 #define _CMU_HFPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ 1969 #define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ 1970 #define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPRESC */ 1971 #define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPRESC */ 1972 #define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPRESC */ 1973 #define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24 /**< Shift value for CMU_HFCLKLEPRESC */ 1974 #define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x3000000UL /**< Bit mask for CMU_HFCLKLEPRESC */ 1975 #define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPRESC */ 1976 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFPRESC */ 1977 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFPRESC */ 1978 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV8 0x00000002UL /**< Mode DIV8 for CMU_HFPRESC */ 1979 #define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_HFPRESC */ 1980 #define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24) /**< Shifted mode DIV2 for CMU_HFPRESC */ 1981 #define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24) /**< Shifted mode DIV4 for CMU_HFPRESC */ 1982 #define CMU_HFPRESC_HFCLKLEPRESC_DIV8 (_CMU_HFPRESC_HFCLKLEPRESC_DIV8 << 24) /**< Shifted mode DIV8 for CMU_HFPRESC */ 1983 1984 /* Bit fields for CMU HFBUSPRESC */ 1985 #define _CMU_HFBUSPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFBUSPRESC */ 1986 #define _CMU_HFBUSPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFBUSPRESC */ 1987 #define _CMU_HFBUSPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 1988 #define _CMU_HFBUSPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ 1989 #define _CMU_HFBUSPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFBUSPRESC */ 1990 #define _CMU_HFBUSPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFBUSPRESC */ 1991 #define CMU_HFBUSPRESC_PRESC_DEFAULT (_CMU_HFBUSPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFBUSPRESC */ 1992 #define CMU_HFBUSPRESC_PRESC_NODIVISION (_CMU_HFBUSPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFBUSPRESC */ 1993 1994 /* Bit fields for CMU HFCOREPRESC */ 1995 #define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCOREPRESC */ 1996 #define _CMU_HFCOREPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFCOREPRESC */ 1997 #define _CMU_HFCOREPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 1998 #define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ 1999 #define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCOREPRESC */ 2000 #define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFCOREPRESC */ 2001 #define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCOREPRESC */ 2002 #define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFCOREPRESC */ 2003 2004 /* Bit fields for CMU HFPERPRESC */ 2005 #define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESC */ 2006 #define _CMU_HFPERPRESC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESC */ 2007 #define _CMU_HFPERPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 2008 #define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ 2009 #define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESC */ 2010 #define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESC */ 2011 #define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESC */ 2012 #define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESC */ 2013 2014 /* Bit fields for CMU HFEXPPRESC */ 2015 #define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFEXPPRESC */ 2016 #define _CMU_HFEXPPRESC_MASK 0x00001F00UL /**< Mask for CMU_HFEXPPRESC */ 2017 #define _CMU_HFEXPPRESC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 2018 #define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL /**< Bit mask for CMU_PRESC */ 2019 #define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFEXPPRESC */ 2020 #define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFEXPPRESC */ 2021 #define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFEXPPRESC */ 2022 #define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFEXPPRESC */ 2023 2024 /* Bit fields for CMU HFPERPRESCB */ 2025 #define _CMU_HFPERPRESCB_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCB */ 2026 #define _CMU_HFPERPRESCB_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCB */ 2027 #define _CMU_HFPERPRESCB_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 2028 #define _CMU_HFPERPRESCB_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ 2029 #define _CMU_HFPERPRESCB_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCB */ 2030 #define _CMU_HFPERPRESCB_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCB */ 2031 #define CMU_HFPERPRESCB_PRESC_DEFAULT (_CMU_HFPERPRESCB_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCB */ 2032 #define CMU_HFPERPRESCB_PRESC_NODIVISION (_CMU_HFPERPRESCB_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCB */ 2033 2034 /* Bit fields for CMU HFPERPRESCC */ 2035 #define _CMU_HFPERPRESCC_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERPRESCC */ 2036 #define _CMU_HFPERPRESCC_MASK 0x0001FF00UL /**< Mask for CMU_HFPERPRESCC */ 2037 #define _CMU_HFPERPRESCC_PRESC_SHIFT 8 /**< Shift value for CMU_PRESC */ 2038 #define _CMU_HFPERPRESCC_PRESC_MASK 0x1FF00UL /**< Bit mask for CMU_PRESC */ 2039 #define _CMU_HFPERPRESCC_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERPRESCC */ 2040 #define _CMU_HFPERPRESCC_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_HFPERPRESCC */ 2041 #define CMU_HFPERPRESCC_PRESC_DEFAULT (_CMU_HFPERPRESCC_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERPRESCC */ 2042 #define CMU_HFPERPRESCC_PRESC_NODIVISION (_CMU_HFPERPRESCC_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for CMU_HFPERPRESCC */ 2043 2044 /* Bit fields for CMU LFAPRESC0 */ 2045 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */ 2046 #define _CMU_LFAPRESC0_MASK 0x000F73FFUL /**< Mask for CMU_LFAPRESC0 */ 2047 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 0 /**< Shift value for CMU_LETIMER0 */ 2048 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL /**< Bit mask for CMU_LETIMER0 */ 2049 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 2050 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 2051 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 2052 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 2053 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ 2054 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ 2055 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ 2056 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ 2057 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ 2058 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ 2059 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ 2060 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ 2061 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ 2062 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ 2063 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ 2064 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ 2065 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 2066 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 2067 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 2068 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 2069 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ 2070 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ 2071 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ 2072 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ 2073 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ 2074 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ 2075 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ 2076 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ 2077 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ 2078 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ 2079 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ 2080 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ 2081 #define _CMU_LFAPRESC0_LETIMER1_SHIFT 4 /**< Shift value for CMU_LETIMER1 */ 2082 #define _CMU_LFAPRESC0_LETIMER1_MASK 0xF0UL /**< Bit mask for CMU_LETIMER1 */ 2083 #define _CMU_LFAPRESC0_LETIMER1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 2084 #define _CMU_LFAPRESC0_LETIMER1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 2085 #define _CMU_LFAPRESC0_LETIMER1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 2086 #define _CMU_LFAPRESC0_LETIMER1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 2087 #define _CMU_LFAPRESC0_LETIMER1_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ 2088 #define _CMU_LFAPRESC0_LETIMER1_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ 2089 #define _CMU_LFAPRESC0_LETIMER1_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ 2090 #define _CMU_LFAPRESC0_LETIMER1_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ 2091 #define _CMU_LFAPRESC0_LETIMER1_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ 2092 #define _CMU_LFAPRESC0_LETIMER1_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ 2093 #define _CMU_LFAPRESC0_LETIMER1_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ 2094 #define _CMU_LFAPRESC0_LETIMER1_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ 2095 #define _CMU_LFAPRESC0_LETIMER1_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ 2096 #define _CMU_LFAPRESC0_LETIMER1_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ 2097 #define _CMU_LFAPRESC0_LETIMER1_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ 2098 #define _CMU_LFAPRESC0_LETIMER1_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ 2099 #define CMU_LFAPRESC0_LETIMER1_DIV1 (_CMU_LFAPRESC0_LETIMER1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 2100 #define CMU_LFAPRESC0_LETIMER1_DIV2 (_CMU_LFAPRESC0_LETIMER1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 2101 #define CMU_LFAPRESC0_LETIMER1_DIV4 (_CMU_LFAPRESC0_LETIMER1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 2102 #define CMU_LFAPRESC0_LETIMER1_DIV8 (_CMU_LFAPRESC0_LETIMER1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 2103 #define CMU_LFAPRESC0_LETIMER1_DIV16 (_CMU_LFAPRESC0_LETIMER1_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ 2104 #define CMU_LFAPRESC0_LETIMER1_DIV32 (_CMU_LFAPRESC0_LETIMER1_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ 2105 #define CMU_LFAPRESC0_LETIMER1_DIV64 (_CMU_LFAPRESC0_LETIMER1_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ 2106 #define CMU_LFAPRESC0_LETIMER1_DIV128 (_CMU_LFAPRESC0_LETIMER1_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ 2107 #define CMU_LFAPRESC0_LETIMER1_DIV256 (_CMU_LFAPRESC0_LETIMER1_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ 2108 #define CMU_LFAPRESC0_LETIMER1_DIV512 (_CMU_LFAPRESC0_LETIMER1_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ 2109 #define CMU_LFAPRESC0_LETIMER1_DIV1024 (_CMU_LFAPRESC0_LETIMER1_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ 2110 #define CMU_LFAPRESC0_LETIMER1_DIV2048 (_CMU_LFAPRESC0_LETIMER1_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ 2111 #define CMU_LFAPRESC0_LETIMER1_DIV4096 (_CMU_LFAPRESC0_LETIMER1_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ 2112 #define CMU_LFAPRESC0_LETIMER1_DIV8192 (_CMU_LFAPRESC0_LETIMER1_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ 2113 #define CMU_LFAPRESC0_LETIMER1_DIV16384 (_CMU_LFAPRESC0_LETIMER1_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ 2114 #define CMU_LFAPRESC0_LETIMER1_DIV32768 (_CMU_LFAPRESC0_LETIMER1_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ 2115 #define _CMU_LFAPRESC0_LESENSE_SHIFT 8 /**< Shift value for CMU_LESENSE */ 2116 #define _CMU_LFAPRESC0_LESENSE_MASK 0x300UL /**< Bit mask for CMU_LESENSE */ 2117 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 2118 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 2119 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 2120 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 2121 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 2122 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 2123 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 2124 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 2125 #define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ 2126 #define _CMU_LFAPRESC0_LCD_MASK 0x7000UL /**< Bit mask for CMU_LCD */ 2127 #define _CMU_LFAPRESC0_LCD_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 2128 #define _CMU_LFAPRESC0_LCD_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 2129 #define _CMU_LFAPRESC0_LCD_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 2130 #define _CMU_LFAPRESC0_LCD_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 2131 #define _CMU_LFAPRESC0_LCD_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ 2132 #define _CMU_LFAPRESC0_LCD_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ 2133 #define _CMU_LFAPRESC0_LCD_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ 2134 #define _CMU_LFAPRESC0_LCD_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ 2135 #define CMU_LFAPRESC0_LCD_DIV1 (_CMU_LFAPRESC0_LCD_DIV1 << 12) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 2136 #define CMU_LFAPRESC0_LCD_DIV2 (_CMU_LFAPRESC0_LCD_DIV2 << 12) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 2137 #define CMU_LFAPRESC0_LCD_DIV4 (_CMU_LFAPRESC0_LCD_DIV4 << 12) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 2138 #define CMU_LFAPRESC0_LCD_DIV8 (_CMU_LFAPRESC0_LCD_DIV8 << 12) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 2139 #define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ 2140 #define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ 2141 #define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ 2142 #define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ 2143 #define _CMU_LFAPRESC0_RTC_SHIFT 16 /**< Shift value for CMU_RTC */ 2144 #define _CMU_LFAPRESC0_RTC_MASK 0xF0000UL /**< Bit mask for CMU_RTC */ 2145 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */ 2146 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */ 2147 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */ 2148 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */ 2149 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */ 2150 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */ 2151 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */ 2152 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */ 2153 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */ 2154 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */ 2155 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */ 2156 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */ 2157 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */ 2158 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */ 2159 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */ 2160 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */ 2161 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */ 2162 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */ 2163 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 16) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */ 2164 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 16) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */ 2165 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 16) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */ 2166 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 16) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */ 2167 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 16) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */ 2168 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 16) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */ 2169 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 16) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */ 2170 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 16) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */ 2171 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 16) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */ 2172 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 16) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */ 2173 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 16) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */ 2174 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 16) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */ 2175 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 16) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */ 2176 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 16) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */ 2177 2178 /* Bit fields for CMU LFBPRESC0 */ 2179 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */ 2180 #define _CMU_LFBPRESC0_MASK 0x00003F33UL /**< Mask for CMU_LFBPRESC0 */ 2181 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */ 2182 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */ 2183 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ 2184 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ 2185 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ 2186 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ 2187 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ 2188 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ 2189 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ 2190 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ 2191 #define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */ 2192 #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */ 2193 #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ 2194 #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */ 2195 #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */ 2196 #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */ 2197 #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ 2198 #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */ 2199 #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */ 2200 #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */ 2201 #define _CMU_LFBPRESC0_SYSTICK_SHIFT 8 /**< Shift value for CMU_SYSTICK */ 2202 #define _CMU_LFBPRESC0_SYSTICK_MASK 0xF00UL /**< Bit mask for CMU_SYSTICK */ 2203 #define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */ 2204 #define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */ 2205 #define _CMU_LFBPRESC0_CSEN_SHIFT 12 /**< Shift value for CMU_CSEN */ 2206 #define _CMU_LFBPRESC0_CSEN_MASK 0x3000UL /**< Bit mask for CMU_CSEN */ 2207 #define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFBPRESC0 */ 2208 #define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFBPRESC0 */ 2209 #define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFBPRESC0 */ 2210 #define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFBPRESC0 */ 2211 #define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFBPRESC0 */ 2212 #define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFBPRESC0 */ 2213 #define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFBPRESC0 */ 2214 #define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFBPRESC0 */ 2215 2216 /* Bit fields for CMU LFEPRESC0 */ 2217 #define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFEPRESC0 */ 2218 #define _CMU_LFEPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFEPRESC0 */ 2219 #define _CMU_LFEPRESC0_RTCC_SHIFT 0 /**< Shift value for CMU_RTCC */ 2220 #define _CMU_LFEPRESC0_RTCC_MASK 0x3UL /**< Bit mask for CMU_RTCC */ 2221 #define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFEPRESC0 */ 2222 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFEPRESC0 */ 2223 #define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFEPRESC0 */ 2224 #define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFEPRESC0 */ 2225 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFEPRESC0 */ 2226 #define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFEPRESC0 */ 2227 2228 /* Bit fields for CMU SYNCBUSY */ 2229 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */ 2230 #define _CMU_SYNCBUSY_MASK 0x7F050155UL /**< Mask for CMU_SYNCBUSY */ 2231 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency a Clock Enable 0 Busy */ 2232 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */ 2233 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */ 2234 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 2235 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 2236 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency a Prescaler 0 Busy */ 2237 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */ 2238 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */ 2239 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 2240 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 2241 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */ 2242 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */ 2243 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */ 2244 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 2245 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 2246 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */ 2247 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */ 2248 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */ 2249 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 2250 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 2251 #define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */ 2252 #define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */ 2253 #define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */ 2254 #define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 2255 #define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 2256 #define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16) /**< Low Frequency E Clock Enable 0 Busy */ 2257 #define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16 /**< Shift value for CMU_LFECLKEN0 */ 2258 #define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL /**< Bit mask for CMU_LFECLKEN0 */ 2259 #define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 2260 #define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 2261 #define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18) /**< Low Frequency E Prescaler 0 Busy */ 2262 #define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18 /**< Shift value for CMU_LFEPRESC0 */ 2263 #define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL /**< Bit mask for CMU_LFEPRESC0 */ 2264 #define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 2265 #define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 2266 #define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24) /**< HFRCO Busy */ 2267 #define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24 /**< Shift value for CMU_HFRCOBSY */ 2268 #define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL /**< Bit mask for CMU_HFRCOBSY */ 2269 #define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 2270 #define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 2271 #define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25) /**< AUXHFRCO Busy */ 2272 #define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25 /**< Shift value for CMU_AUXHFRCOBSY */ 2273 #define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL /**< Bit mask for CMU_AUXHFRCOBSY */ 2274 #define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 2275 #define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 2276 #define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26) /**< LFRCO Busy */ 2277 #define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26 /**< Shift value for CMU_LFRCOBSY */ 2278 #define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL /**< Bit mask for CMU_LFRCOBSY */ 2279 #define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 2280 #define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 2281 #define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27) /**< LFRCO VREF Busy */ 2282 #define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27 /**< Shift value for CMU_LFRCOVREFBSY */ 2283 #define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL /**< Bit mask for CMU_LFRCOVREFBSY */ 2284 #define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 2285 #define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 2286 #define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28) /**< HFXO Busy */ 2287 #define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28 /**< Shift value for CMU_HFXOBSY */ 2288 #define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL /**< Bit mask for CMU_HFXOBSY */ 2289 #define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 2290 #define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 2291 #define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29) /**< LFXO Busy */ 2292 #define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29 /**< Shift value for CMU_LFXOBSY */ 2293 #define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL /**< Bit mask for CMU_LFXOBSY */ 2294 #define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 2295 #define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 2296 #define CMU_SYNCBUSY_USHFRCOBSY (0x1UL << 30) /**< USHFRCO Busy */ 2297 #define _CMU_SYNCBUSY_USHFRCOBSY_SHIFT 30 /**< Shift value for CMU_USHFRCOBSY */ 2298 #define _CMU_SYNCBUSY_USHFRCOBSY_MASK 0x40000000UL /**< Bit mask for CMU_USHFRCOBSY */ 2299 #define _CMU_SYNCBUSY_USHFRCOBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */ 2300 #define CMU_SYNCBUSY_USHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_USHFRCOBSY_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */ 2301 2302 /* Bit fields for CMU FREEZE */ 2303 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */ 2304 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */ 2305 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ 2306 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */ 2307 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */ 2308 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */ 2309 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */ 2310 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */ 2311 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */ 2312 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */ 2313 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */ 2314 2315 /* Bit fields for CMU PCNTCTRL */ 2316 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */ 2317 #define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */ 2318 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */ 2319 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */ 2320 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */ 2321 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 2322 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 2323 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */ 2324 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */ 2325 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */ 2326 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 2327 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ 2328 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */ 2329 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 2330 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ 2331 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */ 2332 #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */ 2333 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */ 2334 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */ 2335 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 2336 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 2337 #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */ 2338 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */ 2339 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */ 2340 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 2341 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ 2342 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */ 2343 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 2344 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ 2345 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */ 2346 #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */ 2347 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */ 2348 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */ 2349 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 2350 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 2351 #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */ 2352 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */ 2353 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */ 2354 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */ 2355 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */ 2356 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */ 2357 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */ 2358 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */ 2359 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */ 2360 2361 /* Bit fields for CMU ADCCTRL */ 2362 #define _CMU_ADCCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_ADCCTRL */ 2363 #define _CMU_ADCCTRL_MASK 0x01330133UL /**< Mask for CMU_ADCCTRL */ 2364 #define _CMU_ADCCTRL_ADC0CLKDIV_SHIFT 0 /**< Shift value for CMU_ADC0CLKDIV */ 2365 #define _CMU_ADCCTRL_ADC0CLKDIV_MASK 0x3UL /**< Bit mask for CMU_ADC0CLKDIV */ 2366 #define _CMU_ADCCTRL_ADC0CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 2367 #define _CMU_ADCCTRL_ADC0CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ 2368 #define CMU_ADCCTRL_ADC0CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC0CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 2369 #define CMU_ADCCTRL_ADC0CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC0CLKDIV_NODIVISION << 0) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ 2370 #define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4 /**< Shift value for CMU_ADC0CLKSEL */ 2371 #define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL /**< Bit mask for CMU_ADC0CLKSEL */ 2372 #define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 2373 #define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ 2374 #define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ 2375 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ 2376 #define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ 2377 #define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 2378 #define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4) /**< Shifted mode DISABLED for CMU_ADCCTRL */ 2379 #define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ 2380 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4) /**< Shifted mode HFXO for CMU_ADCCTRL */ 2381 #define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ 2382 #define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8) /**< Invert Clock Selected By ADC0CLKSEL */ 2383 #define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8 /**< Shift value for CMU_ADC0CLKINV */ 2384 #define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL /**< Bit mask for CMU_ADC0CLKINV */ 2385 #define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 2386 #define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 2387 #define _CMU_ADCCTRL_ADC1CLKDIV_SHIFT 16 /**< Shift value for CMU_ADC1CLKDIV */ 2388 #define _CMU_ADCCTRL_ADC1CLKDIV_MASK 0x30000UL /**< Bit mask for CMU_ADC1CLKDIV */ 2389 #define _CMU_ADCCTRL_ADC1CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 2390 #define _CMU_ADCCTRL_ADC1CLKDIV_NODIVISION 0x00000000UL /**< Mode NODIVISION for CMU_ADCCTRL */ 2391 #define CMU_ADCCTRL_ADC1CLKDIV_DEFAULT (_CMU_ADCCTRL_ADC1CLKDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 2392 #define CMU_ADCCTRL_ADC1CLKDIV_NODIVISION (_CMU_ADCCTRL_ADC1CLKDIV_NODIVISION << 16) /**< Shifted mode NODIVISION for CMU_ADCCTRL */ 2393 #define _CMU_ADCCTRL_ADC1CLKSEL_SHIFT 20 /**< Shift value for CMU_ADC1CLKSEL */ 2394 #define _CMU_ADCCTRL_ADC1CLKSEL_MASK 0x300000UL /**< Bit mask for CMU_ADC1CLKSEL */ 2395 #define _CMU_ADCCTRL_ADC1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 2396 #define _CMU_ADCCTRL_ADC1CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_ADCCTRL */ 2397 #define _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for CMU_ADCCTRL */ 2398 #define _CMU_ADCCTRL_ADC1CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_ADCCTRL */ 2399 #define _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK 0x00000003UL /**< Mode HFSRCCLK for CMU_ADCCTRL */ 2400 #define CMU_ADCCTRL_ADC1CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC1CLKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 2401 #define CMU_ADCCTRL_ADC1CLKSEL_DISABLED (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << 20) /**< Shifted mode DISABLED for CMU_ADCCTRL */ 2402 #define CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_ADCCTRL */ 2403 #define CMU_ADCCTRL_ADC1CLKSEL_HFXO (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << 20) /**< Shifted mode HFXO for CMU_ADCCTRL */ 2404 #define CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << 20) /**< Shifted mode HFSRCCLK for CMU_ADCCTRL */ 2405 #define CMU_ADCCTRL_ADC1CLKINV (0x1UL << 24) /**< Invert Clock Selected By ADC1CLKSEL */ 2406 #define _CMU_ADCCTRL_ADC1CLKINV_SHIFT 24 /**< Shift value for CMU_ADC1CLKINV */ 2407 #define _CMU_ADCCTRL_ADC1CLKINV_MASK 0x1000000UL /**< Bit mask for CMU_ADC1CLKINV */ 2408 #define _CMU_ADCCTRL_ADC1CLKINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ADCCTRL */ 2409 #define CMU_ADCCTRL_ADC1CLKINV_DEFAULT (_CMU_ADCCTRL_ADC1CLKINV_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_ADCCTRL */ 2410 2411 /* Bit fields for CMU SDIOCTRL */ 2412 #define _CMU_SDIOCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_SDIOCTRL */ 2413 #define _CMU_SDIOCTRL_MASK 0x00000083UL /**< Mask for CMU_SDIOCTRL */ 2414 #define _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT 0 /**< Shift value for CMU_SDIOCLKSEL */ 2415 #define _CMU_SDIOCTRL_SDIOCLKSEL_MASK 0x3UL /**< Bit mask for CMU_SDIOCLKSEL */ 2416 #define _CMU_SDIOCTRL_SDIOCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SDIOCTRL */ 2417 #define _CMU_SDIOCTRL_SDIOCLKSEL_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_SDIOCTRL */ 2418 #define _CMU_SDIOCTRL_SDIOCLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_SDIOCTRL */ 2419 #define _CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO 0x00000002UL /**< Mode AUXHFRCO for CMU_SDIOCTRL */ 2420 #define _CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO 0x00000003UL /**< Mode USHFRCO for CMU_SDIOCTRL */ 2421 #define CMU_SDIOCTRL_SDIOCLKSEL_DEFAULT (_CMU_SDIOCTRL_SDIOCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SDIOCTRL */ 2422 #define CMU_SDIOCTRL_SDIOCLKSEL_HFRCO (_CMU_SDIOCTRL_SDIOCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_SDIOCTRL */ 2423 #define CMU_SDIOCTRL_SDIOCLKSEL_HFXO (_CMU_SDIOCTRL_SDIOCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SDIOCTRL */ 2424 #define CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO (_CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_SDIOCTRL */ 2425 #define CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO (_CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_SDIOCTRL */ 2426 #define CMU_SDIOCTRL_SDIOCLKDIS (0x1UL << 7) /**< SDIO Reference Clock Disable */ 2427 #define _CMU_SDIOCTRL_SDIOCLKDIS_SHIFT 7 /**< Shift value for CMU_SDIOCLKDIS */ 2428 #define _CMU_SDIOCTRL_SDIOCLKDIS_MASK 0x80UL /**< Bit mask for CMU_SDIOCLKDIS */ 2429 #define _CMU_SDIOCTRL_SDIOCLKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SDIOCTRL */ 2430 #define CMU_SDIOCTRL_SDIOCLKDIS_DEFAULT (_CMU_SDIOCTRL_SDIOCLKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_SDIOCTRL */ 2431 2432 /* Bit fields for CMU QSPICTRL */ 2433 #define _CMU_QSPICTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_QSPICTRL */ 2434 #define _CMU_QSPICTRL_MASK 0x00000083UL /**< Mask for CMU_QSPICTRL */ 2435 #define _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT 0 /**< Shift value for CMU_QSPI0CLKSEL */ 2436 #define _CMU_QSPICTRL_QSPI0CLKSEL_MASK 0x3UL /**< Bit mask for CMU_QSPI0CLKSEL */ 2437 #define _CMU_QSPICTRL_QSPI0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_QSPICTRL */ 2438 #define _CMU_QSPICTRL_QSPI0CLKSEL_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_QSPICTRL */ 2439 #define _CMU_QSPICTRL_QSPI0CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_QSPICTRL */ 2440 #define _CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO 0x00000002UL /**< Mode AUXHFRCO for CMU_QSPICTRL */ 2441 #define _CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO 0x00000003UL /**< Mode USHFRCO for CMU_QSPICTRL */ 2442 #define CMU_QSPICTRL_QSPI0CLKSEL_DEFAULT (_CMU_QSPICTRL_QSPI0CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_QSPICTRL */ 2443 #define CMU_QSPICTRL_QSPI0CLKSEL_HFRCO (_CMU_QSPICTRL_QSPI0CLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_QSPICTRL */ 2444 #define CMU_QSPICTRL_QSPI0CLKSEL_HFXO (_CMU_QSPICTRL_QSPI0CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_QSPICTRL */ 2445 #define CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO (_CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_QSPICTRL */ 2446 #define CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO (_CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_QSPICTRL */ 2447 #define CMU_QSPICTRL_QSPI0CLKDIS (0x1UL << 7) /**< QSPI0 Reference Clock Disable */ 2448 #define _CMU_QSPICTRL_QSPI0CLKDIS_SHIFT 7 /**< Shift value for CMU_QSPI0CLKDIS */ 2449 #define _CMU_QSPICTRL_QSPI0CLKDIS_MASK 0x80UL /**< Bit mask for CMU_QSPI0CLKDIS */ 2450 #define _CMU_QSPICTRL_QSPI0CLKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_QSPICTRL */ 2451 #define CMU_QSPICTRL_QSPI0CLKDIS_DEFAULT (_CMU_QSPICTRL_QSPI0CLKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_QSPICTRL */ 2452 2453 /* Bit fields for CMU PDMCTRL */ 2454 #define _CMU_PDMCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PDMCTRL */ 2455 #define _CMU_PDMCTRL_MASK 0x00000083UL /**< Mask for CMU_PDMCTRL */ 2456 #define _CMU_PDMCTRL_PDMCLKSEL_SHIFT 0 /**< Shift value for CMU_PDMCLKSEL */ 2457 #define _CMU_PDMCTRL_PDMCLKSEL_MASK 0x3UL /**< Bit mask for CMU_PDMCLKSEL */ 2458 #define _CMU_PDMCTRL_PDMCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PDMCTRL */ 2459 #define _CMU_PDMCTRL_PDMCLKSEL_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_PDMCTRL */ 2460 #define _CMU_PDMCTRL_PDMCLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_PDMCTRL */ 2461 #define _CMU_PDMCTRL_PDMCLKSEL_USHFRCO 0x00000002UL /**< Mode USHFRCO for CMU_PDMCTRL */ 2462 #define _CMU_PDMCTRL_PDMCLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_PDMCTRL */ 2463 #define CMU_PDMCTRL_PDMCLKSEL_DEFAULT (_CMU_PDMCTRL_PDMCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PDMCTRL */ 2464 #define CMU_PDMCTRL_PDMCLKSEL_HFRCO (_CMU_PDMCTRL_PDMCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_PDMCTRL */ 2465 #define CMU_PDMCTRL_PDMCLKSEL_HFXO (_CMU_PDMCTRL_PDMCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_PDMCTRL */ 2466 #define CMU_PDMCTRL_PDMCLKSEL_USHFRCO (_CMU_PDMCTRL_PDMCLKSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_PDMCTRL */ 2467 #define CMU_PDMCTRL_PDMCLKSEL_CLKIN0 (_CMU_PDMCTRL_PDMCLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_PDMCTRL */ 2468 #define CMU_PDMCTRL_PDMCLKEN (0x1UL << 7) /**< PDM Core Clock Enable */ 2469 #define _CMU_PDMCTRL_PDMCLKEN_SHIFT 7 /**< Shift value for CMU_PDMCLKEN */ 2470 #define _CMU_PDMCTRL_PDMCLKEN_MASK 0x80UL /**< Bit mask for CMU_PDMCLKEN */ 2471 #define _CMU_PDMCTRL_PDMCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PDMCTRL */ 2472 #define CMU_PDMCTRL_PDMCLKEN_DEFAULT (_CMU_PDMCTRL_PDMCLKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_PDMCTRL */ 2473 2474 /* Bit fields for CMU ROUTEPEN */ 2475 #define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTEPEN */ 2476 #define _CMU_ROUTEPEN_MASK 0x10000007UL /**< Mask for CMU_ROUTEPEN */ 2477 #define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */ 2478 #define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */ 2479 #define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */ 2480 #define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ 2481 #define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ 2482 #define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */ 2483 #define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */ 2484 #define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */ 2485 #define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ 2486 #define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ 2487 #define CMU_ROUTEPEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 Pin Enable */ 2488 #define _CMU_ROUTEPEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for CMU_CLKOUT2PEN */ 2489 #define _CMU_ROUTEPEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for CMU_CLKOUT2PEN */ 2490 #define _CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ 2491 #define CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ 2492 #define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28) /**< CLKIN0 Pin Enable */ 2493 #define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28 /**< Shift value for CMU_CLKIN0PEN */ 2494 #define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL /**< Bit mask for CMU_CLKIN0PEN */ 2495 #define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTEPEN */ 2496 #define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_ROUTEPEN */ 2497 2498 /* Bit fields for CMU ROUTELOC0 */ 2499 #define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC0 */ 2500 #define _CMU_ROUTELOC0_MASK 0x00070707UL /**< Mask for CMU_ROUTELOC0 */ 2501 #define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0 /**< Shift value for CMU_CLKOUT0LOC */ 2502 #define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKOUT0LOC */ 2503 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ 2504 #define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ 2505 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ 2506 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ 2507 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ 2508 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ 2509 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ 2510 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ 2511 #define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ 2512 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ 2513 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ 2514 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ 2515 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ 2516 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ 2517 #define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8 /**< Shift value for CMU_CLKOUT1LOC */ 2518 #define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL /**< Bit mask for CMU_CLKOUT1LOC */ 2519 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ 2520 #define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ 2521 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ 2522 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ 2523 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ 2524 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ 2525 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ 2526 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ 2527 #define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ 2528 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ 2529 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ 2530 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ 2531 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ 2532 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ 2533 #define _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT 16 /**< Shift value for CMU_CLKOUT2LOC */ 2534 #define _CMU_ROUTELOC0_CLKOUT2LOC_MASK 0x70000UL /**< Bit mask for CMU_CLKOUT2LOC */ 2535 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC0 */ 2536 #define _CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC0 */ 2537 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC0 */ 2538 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC0 */ 2539 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC0 */ 2540 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC0 */ 2541 #define _CMU_ROUTELOC0_CLKOUT2LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC0 */ 2542 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for CMU_ROUTELOC0 */ 2543 #define CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_ROUTELOC0 */ 2544 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for CMU_ROUTELOC0 */ 2545 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for CMU_ROUTELOC0 */ 2546 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for CMU_ROUTELOC0 */ 2547 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for CMU_ROUTELOC0 */ 2548 #define CMU_ROUTELOC0_CLKOUT2LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT2LOC_LOC5 << 16) /**< Shifted mode LOC5 for CMU_ROUTELOC0 */ 2549 2550 /* Bit fields for CMU ROUTELOC1 */ 2551 #define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTELOC1 */ 2552 #define _CMU_ROUTELOC1_MASK 0x00000007UL /**< Mask for CMU_ROUTELOC1 */ 2553 #define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0 /**< Shift value for CMU_CLKIN0LOC */ 2554 #define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL /**< Bit mask for CMU_CLKIN0LOC */ 2555 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTELOC1 */ 2556 #define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTELOC1 */ 2557 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTELOC1 */ 2558 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTELOC1 */ 2559 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTELOC1 */ 2560 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL /**< Mode LOC4 for CMU_ROUTELOC1 */ 2561 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC5 0x00000005UL /**< Mode LOC5 for CMU_ROUTELOC1 */ 2562 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC6 0x00000006UL /**< Mode LOC6 for CMU_ROUTELOC1 */ 2563 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC7 0x00000007UL /**< Mode LOC7 for CMU_ROUTELOC1 */ 2564 #define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0) /**< Shifted mode LOC0 for CMU_ROUTELOC1 */ 2565 #define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTELOC1 */ 2566 #define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0) /**< Shifted mode LOC1 for CMU_ROUTELOC1 */ 2567 #define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0) /**< Shifted mode LOC2 for CMU_ROUTELOC1 */ 2568 #define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0) /**< Shifted mode LOC3 for CMU_ROUTELOC1 */ 2569 #define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0) /**< Shifted mode LOC4 for CMU_ROUTELOC1 */ 2570 #define CMU_ROUTELOC1_CLKIN0LOC_LOC5 (_CMU_ROUTELOC1_CLKIN0LOC_LOC5 << 0) /**< Shifted mode LOC5 for CMU_ROUTELOC1 */ 2571 #define CMU_ROUTELOC1_CLKIN0LOC_LOC6 (_CMU_ROUTELOC1_CLKIN0LOC_LOC6 << 0) /**< Shifted mode LOC6 for CMU_ROUTELOC1 */ 2572 #define CMU_ROUTELOC1_CLKIN0LOC_LOC7 (_CMU_ROUTELOC1_CLKIN0LOC_LOC7 << 0) /**< Shifted mode LOC7 for CMU_ROUTELOC1 */ 2573 2574 /* Bit fields for CMU LOCK */ 2575 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */ 2576 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ 2577 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ 2578 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ 2579 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */ 2580 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */ 2581 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */ 2582 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */ 2583 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */ 2584 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ 2585 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */ 2586 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */ 2587 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */ 2588 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ 2589 2590 /* Bit fields for CMU HFRCOSS */ 2591 #define _CMU_HFRCOSS_RESETVALUE 0x00000000UL /**< Default value for CMU_HFRCOSS */ 2592 #define _CMU_HFRCOSS_MASK 0x00001F07UL /**< Mask for CMU_HFRCOSS */ 2593 #define _CMU_HFRCOSS_SSAMP_SHIFT 0 /**< Shift value for CMU_SSAMP */ 2594 #define _CMU_HFRCOSS_SSAMP_MASK 0x7UL /**< Bit mask for CMU_SSAMP */ 2595 #define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ 2596 #define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ 2597 #define _CMU_HFRCOSS_SSINV_SHIFT 8 /**< Shift value for CMU_SSINV */ 2598 #define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL /**< Bit mask for CMU_SSINV */ 2599 #define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOSS */ 2600 #define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOSS */ 2601 2602 /* Bit fields for CMU USBCTRL */ 2603 #define _CMU_USBCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_USBCTRL */ 2604 #define _CMU_USBCTRL_MASK 0x00000087UL /**< Mask for CMU_USBCTRL */ 2605 #define _CMU_USBCTRL_USBCLKSEL_SHIFT 0 /**< Shift value for CMU_USBCLKSEL */ 2606 #define _CMU_USBCTRL_USBCLKSEL_MASK 0x7UL /**< Bit mask for CMU_USBCLKSEL */ 2607 #define _CMU_USBCTRL_USBCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCTRL */ 2608 #define _CMU_USBCTRL_USBCLKSEL_USHFRCO 0x00000000UL /**< Mode USHFRCO for CMU_USBCTRL */ 2609 #define _CMU_USBCTRL_USBCLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_USBCTRL */ 2610 #define _CMU_USBCTRL_USBCLKSEL_HFXOX2 0x00000002UL /**< Mode HFXOX2 for CMU_USBCTRL */ 2611 #define _CMU_USBCTRL_USBCLKSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_USBCTRL */ 2612 #define _CMU_USBCTRL_USBCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_USBCTRL */ 2613 #define _CMU_USBCTRL_USBCLKSEL_LFRCO 0x00000005UL /**< Mode LFRCO for CMU_USBCTRL */ 2614 #define CMU_USBCTRL_USBCLKSEL_DEFAULT (_CMU_USBCTRL_USBCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USBCTRL */ 2615 #define CMU_USBCTRL_USBCLKSEL_USHFRCO (_CMU_USBCTRL_USBCLKSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_USBCTRL */ 2616 #define CMU_USBCTRL_USBCLKSEL_HFXO (_CMU_USBCTRL_USBCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_USBCTRL */ 2617 #define CMU_USBCTRL_USBCLKSEL_HFXOX2 (_CMU_USBCTRL_USBCLKSEL_HFXOX2 << 0) /**< Shifted mode HFXOX2 for CMU_USBCTRL */ 2618 #define CMU_USBCTRL_USBCLKSEL_HFRCO (_CMU_USBCTRL_USBCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_USBCTRL */ 2619 #define CMU_USBCTRL_USBCLKSEL_LFXO (_CMU_USBCTRL_USBCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_USBCTRL */ 2620 #define CMU_USBCTRL_USBCLKSEL_LFRCO (_CMU_USBCTRL_USBCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_USBCTRL */ 2621 #define CMU_USBCTRL_USBCLKEN (0x1UL << 7) /**< USB Rate Clock Enable */ 2622 #define _CMU_USBCTRL_USBCLKEN_SHIFT 7 /**< Shift value for CMU_USBCLKEN */ 2623 #define _CMU_USBCTRL_USBCLKEN_MASK 0x80UL /**< Bit mask for CMU_USBCLKEN */ 2624 #define _CMU_USBCTRL_USBCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCTRL */ 2625 #define CMU_USBCTRL_USBCLKEN_DEFAULT (_CMU_USBCTRL_USBCLKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_USBCTRL */ 2626 2627 /* Bit fields for CMU USBCRCTRL */ 2628 #define _CMU_USBCRCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_USBCRCTRL */ 2629 #define _CMU_USBCRCTRL_MASK 0x00000003UL /**< Mask for CMU_USBCRCTRL */ 2630 #define CMU_USBCRCTRL_USBCREN (0x1UL << 0) /**< Clock Recovery Enable */ 2631 #define _CMU_USBCRCTRL_USBCREN_SHIFT 0 /**< Shift value for CMU_USBCREN */ 2632 #define _CMU_USBCRCTRL_USBCREN_MASK 0x1UL /**< Bit mask for CMU_USBCREN */ 2633 #define _CMU_USBCRCTRL_USBCREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCRCTRL */ 2634 #define CMU_USBCRCTRL_USBCREN_DEFAULT (_CMU_USBCRCTRL_USBCREN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USBCRCTRL */ 2635 #define CMU_USBCRCTRL_USBLSCRMD (0x1UL << 1) /**< Low Speed Clock Recovery Mode */ 2636 #define _CMU_USBCRCTRL_USBLSCRMD_SHIFT 1 /**< Shift value for CMU_USBLSCRMD */ 2637 #define _CMU_USBCRCTRL_USBLSCRMD_MASK 0x2UL /**< Bit mask for CMU_USBLSCRMD */ 2638 #define _CMU_USBCRCTRL_USBLSCRMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCRCTRL */ 2639 #define CMU_USBCRCTRL_USBLSCRMD_DEFAULT (_CMU_USBCRCTRL_USBLSCRMD_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_USBCRCTRL */ 2640 2641 /** @} */ 2642 /** @} End of group EFM32GG12B_CMU */ 2643 /** @} End of group Parts */ 2644
