1;/**************************************************************************//** 2; * @file 3; * @brief CMSIS Core Device Startup File for 4; * Silicon Labs EFM32GG11B Device Series 5; ****************************************************************************** 6; * # License 7; * 8; * The licensor of this software is Silicon Laboratories Inc. Your use of this 9; * software is governed by the terms of Silicon Labs Master Software License 10; * Agreement (MSLA) available at 11; * www.silabs.com/about-us/legal/master-software-license-agreement. This 12; * software is Third Party Software licensed by Silicon Labs from a third party 13; * and is governed by the sections of the MSLA applicable to Third Party 14; * Software and the additional terms set forth below. 15; * 16; *****************************************************************************/ 17;/* 18; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 19; * 20; * SPDX-License-Identifier: Apache-2.0 21; * 22; * Licensed under the Apache License, Version 2.0 (the License); you may 23; * not use this file except in compliance with the License. 24; * You may obtain a copy of the License at 25; * 26; * www.apache.org/licenses/LICENSE-2.0 27; * 28; * Unless required by applicable law or agreed to in writing, software 29; * distributed under the License is distributed on an AS IS BASIS, WITHOUT 30; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 31; * See the License for the specific language governing permissions and 32; * limitations under the License. 33; */ 34 35;/* 36;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 37;*/ 38 39; <h> Stack Configuration 40; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 41; </h> 42 IF :DEF: __STACK_SIZE 43Stack_Size EQU __STACK_SIZE 44 ELSE 45Stack_Size EQU 0x00000400 46 ENDIF 47 48 AREA STACK, NOINIT, READWRITE, ALIGN=3 49Stack_Mem SPACE Stack_Size 50__initial_sp 51 52 53; <h> Heap Configuration 54; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 55; </h> 56 IF :DEF: __HEAP_SIZE 57Heap_Size EQU __HEAP_SIZE 58 ELSE 59Heap_Size EQU 0x00000C00 60 ENDIF 61 62 AREA HEAP, NOINIT, READWRITE, ALIGN=3 63__heap_base 64Heap_Mem SPACE Heap_Size 65__heap_limit 66 67 68 PRESERVE8 69 THUMB 70 71 72; Vector Table Mapped to Address 0 at Reset 73 74 AREA RESET, DATA, READONLY, ALIGN=8 75 EXPORT __Vectors 76 EXPORT __Vectors_End 77 EXPORT __Vectors_Size 78 79__Vectors DCD __initial_sp ; Top of Stack 80 DCD Reset_Handler ; Reset Handler 81 DCD NMI_Handler ; NMI Handler 82 DCD HardFault_Handler ; Hard Fault Handler 83 DCD MemManage_Handler ; MPU Fault Handler 84 DCD BusFault_Handler ; Bus Fault Handler 85 DCD UsageFault_Handler ; Usage Fault Handler 86 DCD 0 ; Reserved 87 DCD 0 ; Reserved 88 DCD 0 ; Reserved 89 DCD 0 ; Reserved 90 DCD SVC_Handler ; SVCall Handler 91 DCD DebugMon_Handler ; Debug Monitor Handler 92 DCD sl_app_properties ; Application properties 93 DCD PendSV_Handler ; PendSV Handler 94 DCD SysTick_Handler ; SysTick Handler 95 96 ; External Interrupts 97 98 DCD EMU_IRQHandler ; 0: EMU Interrupt 99 DCD WDOG0_IRQHandler ; 1: WDOG0 Interrupt 100 DCD LDMA_IRQHandler ; 2: LDMA Interrupt 101 DCD GPIO_EVEN_IRQHandler ; 3: GPIO_EVEN Interrupt 102 DCD SMU_IRQHandler ; 4: SMU Interrupt 103 DCD TIMER0_IRQHandler ; 5: TIMER0 Interrupt 104 DCD USART0_RX_IRQHandler ; 6: USART0_RX Interrupt 105 DCD USART0_TX_IRQHandler ; 7: USART0_TX Interrupt 106 DCD ACMP0_IRQHandler ; 8: ACMP0 Interrupt 107 DCD ADC0_IRQHandler ; 9: ADC0 Interrupt 108 DCD IDAC0_IRQHandler ; 10: IDAC0 Interrupt 109 DCD I2C0_IRQHandler ; 11: I2C0 Interrupt 110 DCD I2C1_IRQHandler ; 12: I2C1 Interrupt 111 DCD GPIO_ODD_IRQHandler ; 13: GPIO_ODD Interrupt 112 DCD TIMER1_IRQHandler ; 14: TIMER1 Interrupt 113 DCD TIMER2_IRQHandler ; 15: TIMER2 Interrupt 114 DCD TIMER3_IRQHandler ; 16: TIMER3 Interrupt 115 DCD USART1_RX_IRQHandler ; 17: USART1_RX Interrupt 116 DCD USART1_TX_IRQHandler ; 18: USART1_TX Interrupt 117 DCD USART2_RX_IRQHandler ; 19: USART2_RX Interrupt 118 DCD USART2_TX_IRQHandler ; 20: USART2_TX Interrupt 119 DCD UART0_RX_IRQHandler ; 21: UART0_RX Interrupt 120 DCD UART0_TX_IRQHandler ; 22: UART0_TX Interrupt 121 DCD UART1_RX_IRQHandler ; 23: UART1_RX Interrupt 122 DCD UART1_TX_IRQHandler ; 24: UART1_TX Interrupt 123 DCD LEUART0_IRQHandler ; 25: LEUART0 Interrupt 124 DCD LEUART1_IRQHandler ; 26: LEUART1 Interrupt 125 DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt 126 DCD PCNT0_IRQHandler ; 28: PCNT0 Interrupt 127 DCD PCNT1_IRQHandler ; 29: PCNT1 Interrupt 128 DCD PCNT2_IRQHandler ; 30: PCNT2 Interrupt 129 DCD RTCC_IRQHandler ; 31: RTCC Interrupt 130 DCD CMU_IRQHandler ; 32: CMU Interrupt 131 DCD MSC_IRQHandler ; 33: MSC Interrupt 132 DCD CRYPTO0_IRQHandler ; 34: CRYPTO0 Interrupt 133 DCD CRYOTIMER_IRQHandler ; 35: CRYOTIMER Interrupt 134 DCD FPUEH_IRQHandler ; 36: FPUEH Interrupt 135 DCD USART3_RX_IRQHandler ; 37: USART3_RX Interrupt 136 DCD USART3_TX_IRQHandler ; 38: USART3_TX Interrupt 137 DCD USART4_RX_IRQHandler ; 39: USART4_RX Interrupt 138 DCD USART4_TX_IRQHandler ; 40: USART4_TX Interrupt 139 DCD WTIMER0_IRQHandler ; 41: WTIMER0 Interrupt 140 DCD WTIMER1_IRQHandler ; 42: WTIMER1 Interrupt 141 DCD WTIMER2_IRQHandler ; 43: WTIMER2 Interrupt 142 DCD WTIMER3_IRQHandler ; 44: WTIMER3 Interrupt 143 DCD I2C2_IRQHandler ; 45: I2C2 Interrupt 144 DCD VDAC0_IRQHandler ; 46: VDAC0 Interrupt 145 DCD TIMER4_IRQHandler ; 47: TIMER4 Interrupt 146 DCD TIMER5_IRQHandler ; 48: TIMER5 Interrupt 147 DCD TIMER6_IRQHandler ; 49: TIMER6 Interrupt 148 DCD USART5_RX_IRQHandler ; 50: USART5_RX Interrupt 149 DCD USART5_TX_IRQHandler ; 51: USART5_TX Interrupt 150 DCD CSEN_IRQHandler ; 52: CSEN Interrupt 151 DCD LESENSE_IRQHandler ; 53: LESENSE Interrupt 152 DCD EBI_IRQHandler ; 54: EBI Interrupt 153 DCD ACMP2_IRQHandler ; 55: ACMP2 Interrupt 154 DCD ADC1_IRQHandler ; 56: ADC1 Interrupt 155 DCD LCD_IRQHandler ; 57: LCD Interrupt 156 DCD SDIO_IRQHandler ; 58: SDIO Interrupt 157 DCD ETH_IRQHandler ; 59: ETH Interrupt 158 DCD CAN0_IRQHandler ; 60: CAN0 Interrupt 159 DCD CAN1_IRQHandler ; 61: CAN1 Interrupt 160 DCD USB_IRQHandler ; 62: USB Interrupt 161 DCD RTC_IRQHandler ; 63: RTC Interrupt 162 DCD WDOG1_IRQHandler ; 64: WDOG1 Interrupt 163 DCD LETIMER1_IRQHandler ; 65: LETIMER1 Interrupt 164 DCD TRNG0_IRQHandler ; 66: TRNG0 Interrupt 165 DCD QSPI0_IRQHandler ; 67: QSPI0 Interrupt 166 167__Vectors_End 168__Vectors_Size EQU __Vectors_End - __Vectors 169 170 AREA |.text|, CODE, READONLY 171 172 173; Reset Handler 174 175Reset_Handler PROC 176 EXPORT Reset_Handler [WEAK] 177 IMPORT SystemInit 178 IMPORT __main 179 LDR R0, =SystemInit 180 BLX R0 181 LDR R0, =__main 182 BX R0 183 ENDP 184 185 186; Dummy Exception Handlers (infinite loops which can be modified) 187 188NMI_Handler PROC 189 EXPORT NMI_Handler [WEAK] 190 EXPORT sl_app_properties [WEAK] 191sl_app_properties ; Provide a dummy value for the sl_app_properties symbol. 192 B . 193 ENDP 194HardFault_Handler\ 195 PROC 196 EXPORT HardFault_Handler [WEAK] 197 B . 198 ENDP 199MemManage_Handler\ 200 PROC 201 EXPORT MemManage_Handler [WEAK] 202 B . 203 ENDP 204BusFault_Handler\ 205 PROC 206 EXPORT BusFault_Handler [WEAK] 207 B . 208 ENDP 209UsageFault_Handler\ 210 PROC 211 EXPORT UsageFault_Handler [WEAK] 212 B . 213 ENDP 214SVC_Handler PROC 215 EXPORT SVC_Handler [WEAK] 216 B . 217 ENDP 218DebugMon_Handler\ 219 PROC 220 EXPORT DebugMon_Handler [WEAK] 221 B . 222 ENDP 223PendSV_Handler PROC 224 EXPORT PendSV_Handler [WEAK] 225 B . 226 ENDP 227SysTick_Handler PROC 228 EXPORT SysTick_Handler [WEAK] 229 B . 230 ENDP 231 232Default_Handler PROC 233 234 EXPORT EMU_IRQHandler [WEAK] 235 EXPORT WDOG0_IRQHandler [WEAK] 236 EXPORT LDMA_IRQHandler [WEAK] 237 EXPORT GPIO_EVEN_IRQHandler [WEAK] 238 EXPORT SMU_IRQHandler [WEAK] 239 EXPORT TIMER0_IRQHandler [WEAK] 240 EXPORT USART0_RX_IRQHandler [WEAK] 241 EXPORT USART0_TX_IRQHandler [WEAK] 242 EXPORT ACMP0_IRQHandler [WEAK] 243 EXPORT ADC0_IRQHandler [WEAK] 244 EXPORT IDAC0_IRQHandler [WEAK] 245 EXPORT I2C0_IRQHandler [WEAK] 246 EXPORT I2C1_IRQHandler [WEAK] 247 EXPORT GPIO_ODD_IRQHandler [WEAK] 248 EXPORT TIMER1_IRQHandler [WEAK] 249 EXPORT TIMER2_IRQHandler [WEAK] 250 EXPORT TIMER3_IRQHandler [WEAK] 251 EXPORT USART1_RX_IRQHandler [WEAK] 252 EXPORT USART1_TX_IRQHandler [WEAK] 253 EXPORT USART2_RX_IRQHandler [WEAK] 254 EXPORT USART2_TX_IRQHandler [WEAK] 255 EXPORT UART0_RX_IRQHandler [WEAK] 256 EXPORT UART0_TX_IRQHandler [WEAK] 257 EXPORT UART1_RX_IRQHandler [WEAK] 258 EXPORT UART1_TX_IRQHandler [WEAK] 259 EXPORT LEUART0_IRQHandler [WEAK] 260 EXPORT LEUART1_IRQHandler [WEAK] 261 EXPORT LETIMER0_IRQHandler [WEAK] 262 EXPORT PCNT0_IRQHandler [WEAK] 263 EXPORT PCNT1_IRQHandler [WEAK] 264 EXPORT PCNT2_IRQHandler [WEAK] 265 EXPORT RTCC_IRQHandler [WEAK] 266 EXPORT CMU_IRQHandler [WEAK] 267 EXPORT MSC_IRQHandler [WEAK] 268 EXPORT CRYPTO0_IRQHandler [WEAK] 269 EXPORT CRYOTIMER_IRQHandler [WEAK] 270 EXPORT FPUEH_IRQHandler [WEAK] 271 EXPORT USART3_RX_IRQHandler [WEAK] 272 EXPORT USART3_TX_IRQHandler [WEAK] 273 EXPORT USART4_RX_IRQHandler [WEAK] 274 EXPORT USART4_TX_IRQHandler [WEAK] 275 EXPORT WTIMER0_IRQHandler [WEAK] 276 EXPORT WTIMER1_IRQHandler [WEAK] 277 EXPORT WTIMER2_IRQHandler [WEAK] 278 EXPORT WTIMER3_IRQHandler [WEAK] 279 EXPORT I2C2_IRQHandler [WEAK] 280 EXPORT VDAC0_IRQHandler [WEAK] 281 EXPORT TIMER4_IRQHandler [WEAK] 282 EXPORT TIMER5_IRQHandler [WEAK] 283 EXPORT TIMER6_IRQHandler [WEAK] 284 EXPORT USART5_RX_IRQHandler [WEAK] 285 EXPORT USART5_TX_IRQHandler [WEAK] 286 EXPORT CSEN_IRQHandler [WEAK] 287 EXPORT LESENSE_IRQHandler [WEAK] 288 EXPORT EBI_IRQHandler [WEAK] 289 EXPORT ACMP2_IRQHandler [WEAK] 290 EXPORT ADC1_IRQHandler [WEAK] 291 EXPORT LCD_IRQHandler [WEAK] 292 EXPORT SDIO_IRQHandler [WEAK] 293 EXPORT ETH_IRQHandler [WEAK] 294 EXPORT CAN0_IRQHandler [WEAK] 295 EXPORT CAN1_IRQHandler [WEAK] 296 EXPORT USB_IRQHandler [WEAK] 297 EXPORT RTC_IRQHandler [WEAK] 298 EXPORT WDOG1_IRQHandler [WEAK] 299 EXPORT LETIMER1_IRQHandler [WEAK] 300 EXPORT TRNG0_IRQHandler [WEAK] 301 EXPORT QSPI0_IRQHandler [WEAK] 302 303 304EMU_IRQHandler 305WDOG0_IRQHandler 306LDMA_IRQHandler 307GPIO_EVEN_IRQHandler 308SMU_IRQHandler 309TIMER0_IRQHandler 310USART0_RX_IRQHandler 311USART0_TX_IRQHandler 312ACMP0_IRQHandler 313ADC0_IRQHandler 314IDAC0_IRQHandler 315I2C0_IRQHandler 316I2C1_IRQHandler 317GPIO_ODD_IRQHandler 318TIMER1_IRQHandler 319TIMER2_IRQHandler 320TIMER3_IRQHandler 321USART1_RX_IRQHandler 322USART1_TX_IRQHandler 323USART2_RX_IRQHandler 324USART2_TX_IRQHandler 325UART0_RX_IRQHandler 326UART0_TX_IRQHandler 327UART1_RX_IRQHandler 328UART1_TX_IRQHandler 329LEUART0_IRQHandler 330LEUART1_IRQHandler 331LETIMER0_IRQHandler 332PCNT0_IRQHandler 333PCNT1_IRQHandler 334PCNT2_IRQHandler 335RTCC_IRQHandler 336CMU_IRQHandler 337MSC_IRQHandler 338CRYPTO0_IRQHandler 339CRYOTIMER_IRQHandler 340FPUEH_IRQHandler 341USART3_RX_IRQHandler 342USART3_TX_IRQHandler 343USART4_RX_IRQHandler 344USART4_TX_IRQHandler 345WTIMER0_IRQHandler 346WTIMER1_IRQHandler 347WTIMER2_IRQHandler 348WTIMER3_IRQHandler 349I2C2_IRQHandler 350VDAC0_IRQHandler 351TIMER4_IRQHandler 352TIMER5_IRQHandler 353TIMER6_IRQHandler 354USART5_RX_IRQHandler 355USART5_TX_IRQHandler 356CSEN_IRQHandler 357LESENSE_IRQHandler 358EBI_IRQHandler 359ACMP2_IRQHandler 360ADC1_IRQHandler 361LCD_IRQHandler 362SDIO_IRQHandler 363ETH_IRQHandler 364CAN0_IRQHandler 365CAN1_IRQHandler 366USB_IRQHandler 367RTC_IRQHandler 368WDOG1_IRQHandler 369LETIMER1_IRQHandler 370TRNG0_IRQHandler 371QSPI0_IRQHandler 372 B . 373 ENDP 374 375 ALIGN 376 377; User Initial Stack & Heap 378 379 IF :DEF:__MICROLIB 380 381 EXPORT __initial_sp 382 EXPORT __heap_base 383 EXPORT __heap_limit 384 385 ELSE 386 387 IMPORT __use_two_region_memory 388 EXPORT __user_initial_stackheap 389 390__user_initial_stackheap PROC 391 LDR R0, = Heap_Mem 392 LDR R1, =(Stack_Mem + Stack_Size) 393 LDR R2, = (Heap_Mem + Heap_Size) 394 LDR R3, = Stack_Mem 395 BX LR 396 ENDP 397 398 ALIGN 399 400 ENDIF 401 402 END 403
