1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG11B_EBI register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG11B_EBI EBI 43 * @{ 44 * @brief EFM32GG11B_EBI Register Declaration 45 ******************************************************************************/ 46 /** EBI Register Declaration */ 47 typedef struct { 48 __IOM uint32_t CTRL; /**< Control Register */ 49 __IOM uint32_t ADDRTIMING; /**< Address Timing Register */ 50 __IOM uint32_t RDTIMING; /**< Read Timing Register */ 51 __IOM uint32_t WRTIMING; /**< Write Timing Register */ 52 __IOM uint32_t POLARITY; /**< Polarity Register */ 53 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 54 __IOM uint32_t ADDRTIMING1; /**< Address Timing Register 1 */ 55 __IOM uint32_t RDTIMING1; /**< Read Timing Register 1 */ 56 __IOM uint32_t WRTIMING1; /**< Write Timing Register 1 */ 57 __IOM uint32_t POLARITY1; /**< Polarity Register 1 */ 58 __IOM uint32_t ADDRTIMING2; /**< Address Timing Register 2 */ 59 __IOM uint32_t RDTIMING2; /**< Read Timing Register 2 */ 60 __IOM uint32_t WRTIMING2; /**< Write Timing Register 2 */ 61 __IOM uint32_t POLARITY2; /**< Polarity Register 2 */ 62 __IOM uint32_t ADDRTIMING3; /**< Address Timing Register 3 */ 63 __IOM uint32_t RDTIMING3; /**< Read Timing Register 3 */ 64 __IOM uint32_t WRTIMING3; /**< Write Timing Register 3 */ 65 __IOM uint32_t POLARITY3; /**< Polarity Register 3 */ 66 __IOM uint32_t PAGECTRL; /**< Page Control Register */ 67 __IOM uint32_t NANDCTRL; /**< NAND Control Register */ 68 __IOM uint32_t CMD; /**< Command Register */ 69 __IM uint32_t STATUS; /**< Status Register */ 70 __IM uint32_t ECCPARITY; /**< ECC Parity Register */ 71 __IOM uint32_t TFTCTRL; /**< TFT Control Register */ 72 __IM uint32_t TFTSTATUS; /**< TFT Status Register */ 73 __IOM uint32_t TFTCOLORFORMAT; /**< Color Format Register */ 74 __IOM uint32_t TFTFRAMEBASE; /**< TFT Frame Base Register */ 75 uint32_t RESERVED1[1U]; /**< Reserved for future use **/ 76 __IOM uint32_t TFTSTRIDE; /**< TFT Stride Register */ 77 __IOM uint32_t TFTSIZE; /**< TFT Size Register */ 78 __IOM uint32_t TFTHPORCH; /**< TFT Horizontal Porch Register */ 79 __IOM uint32_t TFTVPORCH; /**< TFT Vertical Porch Register */ 80 __IOM uint32_t TFTTIMING; /**< TFT Timing Register */ 81 __IOM uint32_t TFTPOLARITY; /**< TFT Polarity Register */ 82 __IOM uint32_t TFTDD; /**< TFT Direct Drive Data Register */ 83 __IOM uint32_t TFTALPHA; /**< TFT Alpha Blending Register */ 84 __IOM uint32_t TFTPIXEL0; /**< TFT Pixel 0 Register */ 85 __IOM uint32_t TFTPIXEL1; /**< TFT Pixel 1 Register */ 86 __IM uint32_t TFTPIXEL; /**< TFT Alpha Blending Result Pixel Register */ 87 __IOM uint32_t TFTMASK; /**< TFT Masking Register */ 88 __IM uint32_t IF; /**< Interrupt Flag Register */ 89 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 90 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 91 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 92 __IOM uint32_t ROUTEPEN; /**< I/O Routing Register */ 93 __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ 94 __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ 95 } EBI_TypeDef; /** @} */ 96 97 /***************************************************************************//** 98 * @addtogroup EFM32GG11B_EBI 99 * @{ 100 * @defgroup EFM32GG11B_EBI_BitFields EBI Bit Fields 101 * @{ 102 ******************************************************************************/ 103 104 /* Bit fields for EBI CTRL */ 105 #define _EBI_CTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_CTRL */ 106 #define _EBI_CTRL_MASK 0xCFFFFFFFUL /**< Mask for EBI_CTRL */ 107 #define _EBI_CTRL_MODE_SHIFT 0 /**< Shift value for EBI_MODE */ 108 #define _EBI_CTRL_MODE_MASK 0x3UL /**< Bit mask for EBI_MODE */ 109 #define _EBI_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 110 #define _EBI_CTRL_MODE_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */ 111 #define _EBI_CTRL_MODE_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */ 112 #define _EBI_CTRL_MODE_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */ 113 #define _EBI_CTRL_MODE_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */ 114 #define EBI_CTRL_MODE_DEFAULT (_EBI_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_CTRL */ 115 #define EBI_CTRL_MODE_D8A8 (_EBI_CTRL_MODE_D8A8 << 0) /**< Shifted mode D8A8 for EBI_CTRL */ 116 #define EBI_CTRL_MODE_D16A16ALE (_EBI_CTRL_MODE_D16A16ALE << 0) /**< Shifted mode D16A16ALE for EBI_CTRL */ 117 #define EBI_CTRL_MODE_D8A24ALE (_EBI_CTRL_MODE_D8A24ALE << 0) /**< Shifted mode D8A24ALE for EBI_CTRL */ 118 #define EBI_CTRL_MODE_D16 (_EBI_CTRL_MODE_D16 << 0) /**< Shifted mode D16 for EBI_CTRL */ 119 #define _EBI_CTRL_MODE1_SHIFT 2 /**< Shift value for EBI_MODE1 */ 120 #define _EBI_CTRL_MODE1_MASK 0xCUL /**< Bit mask for EBI_MODE1 */ 121 #define _EBI_CTRL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 122 #define _EBI_CTRL_MODE1_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */ 123 #define _EBI_CTRL_MODE1_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */ 124 #define _EBI_CTRL_MODE1_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */ 125 #define _EBI_CTRL_MODE1_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */ 126 #define EBI_CTRL_MODE1_DEFAULT (_EBI_CTRL_MODE1_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_CTRL */ 127 #define EBI_CTRL_MODE1_D8A8 (_EBI_CTRL_MODE1_D8A8 << 2) /**< Shifted mode D8A8 for EBI_CTRL */ 128 #define EBI_CTRL_MODE1_D16A16ALE (_EBI_CTRL_MODE1_D16A16ALE << 2) /**< Shifted mode D16A16ALE for EBI_CTRL */ 129 #define EBI_CTRL_MODE1_D8A24ALE (_EBI_CTRL_MODE1_D8A24ALE << 2) /**< Shifted mode D8A24ALE for EBI_CTRL */ 130 #define EBI_CTRL_MODE1_D16 (_EBI_CTRL_MODE1_D16 << 2) /**< Shifted mode D16 for EBI_CTRL */ 131 #define _EBI_CTRL_MODE2_SHIFT 4 /**< Shift value for EBI_MODE2 */ 132 #define _EBI_CTRL_MODE2_MASK 0x30UL /**< Bit mask for EBI_MODE2 */ 133 #define _EBI_CTRL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 134 #define _EBI_CTRL_MODE2_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */ 135 #define _EBI_CTRL_MODE2_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */ 136 #define _EBI_CTRL_MODE2_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */ 137 #define _EBI_CTRL_MODE2_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */ 138 #define EBI_CTRL_MODE2_DEFAULT (_EBI_CTRL_MODE2_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_CTRL */ 139 #define EBI_CTRL_MODE2_D8A8 (_EBI_CTRL_MODE2_D8A8 << 4) /**< Shifted mode D8A8 for EBI_CTRL */ 140 #define EBI_CTRL_MODE2_D16A16ALE (_EBI_CTRL_MODE2_D16A16ALE << 4) /**< Shifted mode D16A16ALE for EBI_CTRL */ 141 #define EBI_CTRL_MODE2_D8A24ALE (_EBI_CTRL_MODE2_D8A24ALE << 4) /**< Shifted mode D8A24ALE for EBI_CTRL */ 142 #define EBI_CTRL_MODE2_D16 (_EBI_CTRL_MODE2_D16 << 4) /**< Shifted mode D16 for EBI_CTRL */ 143 #define _EBI_CTRL_MODE3_SHIFT 6 /**< Shift value for EBI_MODE3 */ 144 #define _EBI_CTRL_MODE3_MASK 0xC0UL /**< Bit mask for EBI_MODE3 */ 145 #define _EBI_CTRL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 146 #define _EBI_CTRL_MODE3_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */ 147 #define _EBI_CTRL_MODE3_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */ 148 #define _EBI_CTRL_MODE3_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */ 149 #define _EBI_CTRL_MODE3_D16 0x00000003UL /**< Mode D16 for EBI_CTRL */ 150 #define EBI_CTRL_MODE3_DEFAULT (_EBI_CTRL_MODE3_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_CTRL */ 151 #define EBI_CTRL_MODE3_D8A8 (_EBI_CTRL_MODE3_D8A8 << 6) /**< Shifted mode D8A8 for EBI_CTRL */ 152 #define EBI_CTRL_MODE3_D16A16ALE (_EBI_CTRL_MODE3_D16A16ALE << 6) /**< Shifted mode D16A16ALE for EBI_CTRL */ 153 #define EBI_CTRL_MODE3_D8A24ALE (_EBI_CTRL_MODE3_D8A24ALE << 6) /**< Shifted mode D8A24ALE for EBI_CTRL */ 154 #define EBI_CTRL_MODE3_D16 (_EBI_CTRL_MODE3_D16 << 6) /**< Shifted mode D16 for EBI_CTRL */ 155 #define EBI_CTRL_BANK0EN (0x1UL << 8) /**< Bank 0 Enable */ 156 #define _EBI_CTRL_BANK0EN_SHIFT 8 /**< Shift value for EBI_BANK0EN */ 157 #define _EBI_CTRL_BANK0EN_MASK 0x100UL /**< Bit mask for EBI_BANK0EN */ 158 #define _EBI_CTRL_BANK0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 159 #define EBI_CTRL_BANK0EN_DEFAULT (_EBI_CTRL_BANK0EN_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_CTRL */ 160 #define EBI_CTRL_BANK1EN (0x1UL << 9) /**< Bank 1 Enable */ 161 #define _EBI_CTRL_BANK1EN_SHIFT 9 /**< Shift value for EBI_BANK1EN */ 162 #define _EBI_CTRL_BANK1EN_MASK 0x200UL /**< Bit mask for EBI_BANK1EN */ 163 #define _EBI_CTRL_BANK1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 164 #define EBI_CTRL_BANK1EN_DEFAULT (_EBI_CTRL_BANK1EN_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_CTRL */ 165 #define EBI_CTRL_BANK2EN (0x1UL << 10) /**< Bank 2 Enable */ 166 #define _EBI_CTRL_BANK2EN_SHIFT 10 /**< Shift value for EBI_BANK2EN */ 167 #define _EBI_CTRL_BANK2EN_MASK 0x400UL /**< Bit mask for EBI_BANK2EN */ 168 #define _EBI_CTRL_BANK2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 169 #define EBI_CTRL_BANK2EN_DEFAULT (_EBI_CTRL_BANK2EN_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_CTRL */ 170 #define EBI_CTRL_BANK3EN (0x1UL << 11) /**< Bank 3 Enable */ 171 #define _EBI_CTRL_BANK3EN_SHIFT 11 /**< Shift value for EBI_BANK3EN */ 172 #define _EBI_CTRL_BANK3EN_MASK 0x800UL /**< Bit mask for EBI_BANK3EN */ 173 #define _EBI_CTRL_BANK3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 174 #define EBI_CTRL_BANK3EN_DEFAULT (_EBI_CTRL_BANK3EN_DEFAULT << 11) /**< Shifted mode DEFAULT for EBI_CTRL */ 175 #define EBI_CTRL_NOIDLE (0x1UL << 12) /**< No Idle Cycle Insertion on Bank 0 */ 176 #define _EBI_CTRL_NOIDLE_SHIFT 12 /**< Shift value for EBI_NOIDLE */ 177 #define _EBI_CTRL_NOIDLE_MASK 0x1000UL /**< Bit mask for EBI_NOIDLE */ 178 #define _EBI_CTRL_NOIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 179 #define EBI_CTRL_NOIDLE_DEFAULT (_EBI_CTRL_NOIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_CTRL */ 180 #define EBI_CTRL_NOIDLE1 (0x1UL << 13) /**< No Idle Cycle Insertion on Bank 1 */ 181 #define _EBI_CTRL_NOIDLE1_SHIFT 13 /**< Shift value for EBI_NOIDLE1 */ 182 #define _EBI_CTRL_NOIDLE1_MASK 0x2000UL /**< Bit mask for EBI_NOIDLE1 */ 183 #define _EBI_CTRL_NOIDLE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 184 #define EBI_CTRL_NOIDLE1_DEFAULT (_EBI_CTRL_NOIDLE1_DEFAULT << 13) /**< Shifted mode DEFAULT for EBI_CTRL */ 185 #define EBI_CTRL_NOIDLE2 (0x1UL << 14) /**< No Idle Cycle Insertion on Bank 2 */ 186 #define _EBI_CTRL_NOIDLE2_SHIFT 14 /**< Shift value for EBI_NOIDLE2 */ 187 #define _EBI_CTRL_NOIDLE2_MASK 0x4000UL /**< Bit mask for EBI_NOIDLE2 */ 188 #define _EBI_CTRL_NOIDLE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 189 #define EBI_CTRL_NOIDLE2_DEFAULT (_EBI_CTRL_NOIDLE2_DEFAULT << 14) /**< Shifted mode DEFAULT for EBI_CTRL */ 190 #define EBI_CTRL_NOIDLE3 (0x1UL << 15) /**< No Idle Cycle Insertion on Bank 3 */ 191 #define _EBI_CTRL_NOIDLE3_SHIFT 15 /**< Shift value for EBI_NOIDLE3 */ 192 #define _EBI_CTRL_NOIDLE3_MASK 0x8000UL /**< Bit mask for EBI_NOIDLE3 */ 193 #define _EBI_CTRL_NOIDLE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 194 #define EBI_CTRL_NOIDLE3_DEFAULT (_EBI_CTRL_NOIDLE3_DEFAULT << 15) /**< Shifted mode DEFAULT for EBI_CTRL */ 195 #define EBI_CTRL_ARDYEN (0x1UL << 16) /**< ARDY Enable */ 196 #define _EBI_CTRL_ARDYEN_SHIFT 16 /**< Shift value for EBI_ARDYEN */ 197 #define _EBI_CTRL_ARDYEN_MASK 0x10000UL /**< Bit mask for EBI_ARDYEN */ 198 #define _EBI_CTRL_ARDYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 199 #define EBI_CTRL_ARDYEN_DEFAULT (_EBI_CTRL_ARDYEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_CTRL */ 200 #define EBI_CTRL_ARDYTODIS (0x1UL << 17) /**< ARDY Timeout Disable */ 201 #define _EBI_CTRL_ARDYTODIS_SHIFT 17 /**< Shift value for EBI_ARDYTODIS */ 202 #define _EBI_CTRL_ARDYTODIS_MASK 0x20000UL /**< Bit mask for EBI_ARDYTODIS */ 203 #define _EBI_CTRL_ARDYTODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 204 #define EBI_CTRL_ARDYTODIS_DEFAULT (_EBI_CTRL_ARDYTODIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EBI_CTRL */ 205 #define EBI_CTRL_ARDY1EN (0x1UL << 18) /**< ARDY Enable for Bank 1 */ 206 #define _EBI_CTRL_ARDY1EN_SHIFT 18 /**< Shift value for EBI_ARDY1EN */ 207 #define _EBI_CTRL_ARDY1EN_MASK 0x40000UL /**< Bit mask for EBI_ARDY1EN */ 208 #define _EBI_CTRL_ARDY1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 209 #define EBI_CTRL_ARDY1EN_DEFAULT (_EBI_CTRL_ARDY1EN_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_CTRL */ 210 #define EBI_CTRL_ARDYTO1DIS (0x1UL << 19) /**< ARDY Timeout Disable for Bank 1 */ 211 #define _EBI_CTRL_ARDYTO1DIS_SHIFT 19 /**< Shift value for EBI_ARDYTO1DIS */ 212 #define _EBI_CTRL_ARDYTO1DIS_MASK 0x80000UL /**< Bit mask for EBI_ARDYTO1DIS */ 213 #define _EBI_CTRL_ARDYTO1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 214 #define EBI_CTRL_ARDYTO1DIS_DEFAULT (_EBI_CTRL_ARDYTO1DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EBI_CTRL */ 215 #define EBI_CTRL_ARDY2EN (0x1UL << 20) /**< ARDY Enable for Bank 2 */ 216 #define _EBI_CTRL_ARDY2EN_SHIFT 20 /**< Shift value for EBI_ARDY2EN */ 217 #define _EBI_CTRL_ARDY2EN_MASK 0x100000UL /**< Bit mask for EBI_ARDY2EN */ 218 #define _EBI_CTRL_ARDY2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 219 #define EBI_CTRL_ARDY2EN_DEFAULT (_EBI_CTRL_ARDY2EN_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_CTRL */ 220 #define EBI_CTRL_ARDYTO2DIS (0x1UL << 21) /**< ARDY Timeout Disable for Bank 2 */ 221 #define _EBI_CTRL_ARDYTO2DIS_SHIFT 21 /**< Shift value for EBI_ARDYTO2DIS */ 222 #define _EBI_CTRL_ARDYTO2DIS_MASK 0x200000UL /**< Bit mask for EBI_ARDYTO2DIS */ 223 #define _EBI_CTRL_ARDYTO2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 224 #define EBI_CTRL_ARDYTO2DIS_DEFAULT (_EBI_CTRL_ARDYTO2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EBI_CTRL */ 225 #define EBI_CTRL_ARDY3EN (0x1UL << 22) /**< ARDY Enable for Bank 3 */ 226 #define _EBI_CTRL_ARDY3EN_SHIFT 22 /**< Shift value for EBI_ARDY3EN */ 227 #define _EBI_CTRL_ARDY3EN_MASK 0x400000UL /**< Bit mask for EBI_ARDY3EN */ 228 #define _EBI_CTRL_ARDY3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 229 #define EBI_CTRL_ARDY3EN_DEFAULT (_EBI_CTRL_ARDY3EN_DEFAULT << 22) /**< Shifted mode DEFAULT for EBI_CTRL */ 230 #define EBI_CTRL_ARDYTO3DIS (0x1UL << 23) /**< ARDY Timeout Disable for Bank 3 */ 231 #define _EBI_CTRL_ARDYTO3DIS_SHIFT 23 /**< Shift value for EBI_ARDYTO3DIS */ 232 #define _EBI_CTRL_ARDYTO3DIS_MASK 0x800000UL /**< Bit mask for EBI_ARDYTO3DIS */ 233 #define _EBI_CTRL_ARDYTO3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 234 #define EBI_CTRL_ARDYTO3DIS_DEFAULT (_EBI_CTRL_ARDYTO3DIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EBI_CTRL */ 235 #define EBI_CTRL_BL (0x1UL << 24) /**< Byte Lane Enable for Bank 0 */ 236 #define _EBI_CTRL_BL_SHIFT 24 /**< Shift value for EBI_BL */ 237 #define _EBI_CTRL_BL_MASK 0x1000000UL /**< Bit mask for EBI_BL */ 238 #define _EBI_CTRL_BL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 239 #define EBI_CTRL_BL_DEFAULT (_EBI_CTRL_BL_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_CTRL */ 240 #define EBI_CTRL_BL1 (0x1UL << 25) /**< Byte Lane Enable for Bank 1 */ 241 #define _EBI_CTRL_BL1_SHIFT 25 /**< Shift value for EBI_BL1 */ 242 #define _EBI_CTRL_BL1_MASK 0x2000000UL /**< Bit mask for EBI_BL1 */ 243 #define _EBI_CTRL_BL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 244 #define EBI_CTRL_BL1_DEFAULT (_EBI_CTRL_BL1_DEFAULT << 25) /**< Shifted mode DEFAULT for EBI_CTRL */ 245 #define EBI_CTRL_BL2 (0x1UL << 26) /**< Byte Lane Enable for Bank 2 */ 246 #define _EBI_CTRL_BL2_SHIFT 26 /**< Shift value for EBI_BL2 */ 247 #define _EBI_CTRL_BL2_MASK 0x4000000UL /**< Bit mask for EBI_BL2 */ 248 #define _EBI_CTRL_BL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 249 #define EBI_CTRL_BL2_DEFAULT (_EBI_CTRL_BL2_DEFAULT << 26) /**< Shifted mode DEFAULT for EBI_CTRL */ 250 #define EBI_CTRL_BL3 (0x1UL << 27) /**< Byte Lane Enable for Bank 3 */ 251 #define _EBI_CTRL_BL3_SHIFT 27 /**< Shift value for EBI_BL3 */ 252 #define _EBI_CTRL_BL3_MASK 0x8000000UL /**< Bit mask for EBI_BL3 */ 253 #define _EBI_CTRL_BL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 254 #define EBI_CTRL_BL3_DEFAULT (_EBI_CTRL_BL3_DEFAULT << 27) /**< Shifted mode DEFAULT for EBI_CTRL */ 255 #define EBI_CTRL_ITS (0x1UL << 30) /**< Individual Timing Set, Line Polarity and Mode Definition Enable */ 256 #define _EBI_CTRL_ITS_SHIFT 30 /**< Shift value for EBI_ITS */ 257 #define _EBI_CTRL_ITS_MASK 0x40000000UL /**< Bit mask for EBI_ITS */ 258 #define _EBI_CTRL_ITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 259 #define EBI_CTRL_ITS_DEFAULT (_EBI_CTRL_ITS_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_CTRL */ 260 #define EBI_CTRL_ALTMAP (0x1UL << 31) /**< Alternative Address Map Enable */ 261 #define _EBI_CTRL_ALTMAP_SHIFT 31 /**< Shift value for EBI_ALTMAP */ 262 #define _EBI_CTRL_ALTMAP_MASK 0x80000000UL /**< Bit mask for EBI_ALTMAP */ 263 #define _EBI_CTRL_ALTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */ 264 #define EBI_CTRL_ALTMAP_DEFAULT (_EBI_CTRL_ALTMAP_DEFAULT << 31) /**< Shifted mode DEFAULT for EBI_CTRL */ 265 266 /* Bit fields for EBI ADDRTIMING */ 267 #define _EBI_ADDRTIMING_RESETVALUE 0x00000707UL /**< Default value for EBI_ADDRTIMING */ 268 #define _EBI_ADDRTIMING_MASK 0x10000707UL /**< Mask for EBI_ADDRTIMING */ 269 #define _EBI_ADDRTIMING_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */ 270 #define _EBI_ADDRTIMING_ADDRSETUP_MASK 0x7UL /**< Bit mask for EBI_ADDRSETUP */ 271 #define _EBI_ADDRTIMING_ADDRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING */ 272 #define EBI_ADDRTIMING_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */ 273 #define _EBI_ADDRTIMING_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */ 274 #define _EBI_ADDRTIMING_ADDRHOLD_MASK 0x700UL /**< Bit mask for EBI_ADDRHOLD */ 275 #define _EBI_ADDRTIMING_ADDRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING */ 276 #define EBI_ADDRTIMING_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */ 277 #define EBI_ADDRTIMING_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */ 278 #define _EBI_ADDRTIMING_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */ 279 #define _EBI_ADDRTIMING_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */ 280 #define _EBI_ADDRTIMING_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING */ 281 #define EBI_ADDRTIMING_HALFALE_DEFAULT (_EBI_ADDRTIMING_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */ 282 283 /* Bit fields for EBI RDTIMING */ 284 #define _EBI_RDTIMING_RESETVALUE 0x00077F07UL /**< Default value for EBI_RDTIMING */ 285 #define _EBI_RDTIMING_MASK 0x70077F07UL /**< Mask for EBI_RDTIMING */ 286 #define _EBI_RDTIMING_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */ 287 #define _EBI_RDTIMING_RDSETUP_MASK 0x7UL /**< Bit mask for EBI_RDSETUP */ 288 #define _EBI_RDTIMING_RDSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING */ 289 #define EBI_RDTIMING_RDSETUP_DEFAULT (_EBI_RDTIMING_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING */ 290 #define _EBI_RDTIMING_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */ 291 #define _EBI_RDTIMING_RDSTRB_MASK 0x7F00UL /**< Bit mask for EBI_RDSTRB */ 292 #define _EBI_RDTIMING_RDSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_RDTIMING */ 293 #define EBI_RDTIMING_RDSTRB_DEFAULT (_EBI_RDTIMING_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING */ 294 #define _EBI_RDTIMING_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */ 295 #define _EBI_RDTIMING_RDHOLD_MASK 0x70000UL /**< Bit mask for EBI_RDHOLD */ 296 #define _EBI_RDTIMING_RDHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING */ 297 #define EBI_RDTIMING_RDHOLD_DEFAULT (_EBI_RDTIMING_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING */ 298 #define EBI_RDTIMING_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */ 299 #define _EBI_RDTIMING_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */ 300 #define _EBI_RDTIMING_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */ 301 #define _EBI_RDTIMING_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */ 302 #define EBI_RDTIMING_HALFRE_DEFAULT (_EBI_RDTIMING_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING */ 303 #define EBI_RDTIMING_PREFETCH (0x1UL << 29) /**< Prefetch Enable */ 304 #define _EBI_RDTIMING_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */ 305 #define _EBI_RDTIMING_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */ 306 #define _EBI_RDTIMING_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */ 307 #define EBI_RDTIMING_PREFETCH_DEFAULT (_EBI_RDTIMING_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING */ 308 #define EBI_RDTIMING_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */ 309 #define _EBI_RDTIMING_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */ 310 #define _EBI_RDTIMING_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */ 311 #define _EBI_RDTIMING_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */ 312 #define EBI_RDTIMING_PAGEMODE_DEFAULT (_EBI_RDTIMING_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING */ 313 314 /* Bit fields for EBI WRTIMING */ 315 #define _EBI_WRTIMING_RESETVALUE 0x00077F07UL /**< Default value for EBI_WRTIMING */ 316 #define _EBI_WRTIMING_MASK 0x30077F07UL /**< Mask for EBI_WRTIMING */ 317 #define _EBI_WRTIMING_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */ 318 #define _EBI_WRTIMING_WRSETUP_MASK 0x7UL /**< Bit mask for EBI_WRSETUP */ 319 #define _EBI_WRTIMING_WRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING */ 320 #define EBI_WRTIMING_WRSETUP_DEFAULT (_EBI_WRTIMING_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING */ 321 #define _EBI_WRTIMING_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */ 322 #define _EBI_WRTIMING_WRSTRB_MASK 0x7F00UL /**< Bit mask for EBI_WRSTRB */ 323 #define _EBI_WRTIMING_WRSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_WRTIMING */ 324 #define EBI_WRTIMING_WRSTRB_DEFAULT (_EBI_WRTIMING_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING */ 325 #define _EBI_WRTIMING_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */ 326 #define _EBI_WRTIMING_WRHOLD_MASK 0x70000UL /**< Bit mask for EBI_WRHOLD */ 327 #define _EBI_WRTIMING_WRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING */ 328 #define EBI_WRTIMING_WRHOLD_DEFAULT (_EBI_WRTIMING_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING */ 329 #define EBI_WRTIMING_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */ 330 #define _EBI_WRTIMING_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */ 331 #define _EBI_WRTIMING_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */ 332 #define _EBI_WRTIMING_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */ 333 #define EBI_WRTIMING_HALFWE_DEFAULT (_EBI_WRTIMING_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING */ 334 #define EBI_WRTIMING_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */ 335 #define _EBI_WRTIMING_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */ 336 #define _EBI_WRTIMING_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */ 337 #define _EBI_WRTIMING_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */ 338 #define EBI_WRTIMING_WBUFDIS_DEFAULT (_EBI_WRTIMING_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING */ 339 340 /* Bit fields for EBI POLARITY */ 341 #define _EBI_POLARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY */ 342 #define _EBI_POLARITY_MASK 0x0000003FUL /**< Mask for EBI_POLARITY */ 343 #define EBI_POLARITY_CSPOL (0x1UL << 0) /**< Chip Select Polarity */ 344 #define _EBI_POLARITY_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ 345 #define _EBI_POLARITY_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ 346 #define _EBI_POLARITY_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ 347 #define _EBI_POLARITY_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ 348 #define _EBI_POLARITY_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ 349 #define EBI_POLARITY_CSPOL_DEFAULT (_EBI_POLARITY_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY */ 350 #define EBI_POLARITY_CSPOL_ACTIVELOW (_EBI_POLARITY_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ 351 #define EBI_POLARITY_CSPOL_ACTIVEHIGH (_EBI_POLARITY_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ 352 #define EBI_POLARITY_REPOL (0x1UL << 1) /**< Read Enable Polarity */ 353 #define _EBI_POLARITY_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */ 354 #define _EBI_POLARITY_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */ 355 #define _EBI_POLARITY_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ 356 #define _EBI_POLARITY_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ 357 #define _EBI_POLARITY_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ 358 #define EBI_POLARITY_REPOL_DEFAULT (_EBI_POLARITY_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY */ 359 #define EBI_POLARITY_REPOL_ACTIVELOW (_EBI_POLARITY_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ 360 #define EBI_POLARITY_REPOL_ACTIVEHIGH (_EBI_POLARITY_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ 361 #define EBI_POLARITY_WEPOL (0x1UL << 2) /**< Write Enable Polarity */ 362 #define _EBI_POLARITY_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */ 363 #define _EBI_POLARITY_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */ 364 #define _EBI_POLARITY_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ 365 #define _EBI_POLARITY_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ 366 #define _EBI_POLARITY_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ 367 #define EBI_POLARITY_WEPOL_DEFAULT (_EBI_POLARITY_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY */ 368 #define EBI_POLARITY_WEPOL_ACTIVELOW (_EBI_POLARITY_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ 369 #define EBI_POLARITY_WEPOL_ACTIVEHIGH (_EBI_POLARITY_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ 370 #define EBI_POLARITY_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */ 371 #define _EBI_POLARITY_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */ 372 #define _EBI_POLARITY_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */ 373 #define _EBI_POLARITY_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ 374 #define _EBI_POLARITY_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ 375 #define _EBI_POLARITY_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ 376 #define EBI_POLARITY_ALEPOL_DEFAULT (_EBI_POLARITY_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY */ 377 #define EBI_POLARITY_ALEPOL_ACTIVELOW (_EBI_POLARITY_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ 378 #define EBI_POLARITY_ALEPOL_ACTIVEHIGH (_EBI_POLARITY_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ 379 #define EBI_POLARITY_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */ 380 #define _EBI_POLARITY_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */ 381 #define _EBI_POLARITY_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */ 382 #define _EBI_POLARITY_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ 383 #define _EBI_POLARITY_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ 384 #define _EBI_POLARITY_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ 385 #define EBI_POLARITY_ARDYPOL_DEFAULT (_EBI_POLARITY_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY */ 386 #define EBI_POLARITY_ARDYPOL_ACTIVELOW (_EBI_POLARITY_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ 387 #define EBI_POLARITY_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ 388 #define EBI_POLARITY_BLPOL (0x1UL << 5) /**< BL Polarity */ 389 #define _EBI_POLARITY_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */ 390 #define _EBI_POLARITY_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */ 391 #define _EBI_POLARITY_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */ 392 #define _EBI_POLARITY_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */ 393 #define _EBI_POLARITY_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */ 394 #define EBI_POLARITY_BLPOL_DEFAULT (_EBI_POLARITY_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY */ 395 #define EBI_POLARITY_BLPOL_ACTIVELOW (_EBI_POLARITY_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY */ 396 #define EBI_POLARITY_BLPOL_ACTIVEHIGH (_EBI_POLARITY_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */ 397 398 /* Bit fields for EBI ADDRTIMING1 */ 399 #define _EBI_ADDRTIMING1_RESETVALUE 0x00000707UL /**< Default value for EBI_ADDRTIMING1 */ 400 #define _EBI_ADDRTIMING1_MASK 0x10000707UL /**< Mask for EBI_ADDRTIMING1 */ 401 #define _EBI_ADDRTIMING1_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */ 402 #define _EBI_ADDRTIMING1_ADDRSETUP_MASK 0x7UL /**< Bit mask for EBI_ADDRSETUP */ 403 #define _EBI_ADDRTIMING1_ADDRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING1 */ 404 #define EBI_ADDRTIMING1_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING1_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */ 405 #define _EBI_ADDRTIMING1_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */ 406 #define _EBI_ADDRTIMING1_ADDRHOLD_MASK 0x700UL /**< Bit mask for EBI_ADDRHOLD */ 407 #define _EBI_ADDRTIMING1_ADDRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING1 */ 408 #define EBI_ADDRTIMING1_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING1_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */ 409 #define EBI_ADDRTIMING1_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */ 410 #define _EBI_ADDRTIMING1_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */ 411 #define _EBI_ADDRTIMING1_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */ 412 #define _EBI_ADDRTIMING1_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING1 */ 413 #define EBI_ADDRTIMING1_HALFALE_DEFAULT (_EBI_ADDRTIMING1_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING1 */ 414 415 /* Bit fields for EBI RDTIMING1 */ 416 #define _EBI_RDTIMING1_RESETVALUE 0x00077F07UL /**< Default value for EBI_RDTIMING1 */ 417 #define _EBI_RDTIMING1_MASK 0x70077F07UL /**< Mask for EBI_RDTIMING1 */ 418 #define _EBI_RDTIMING1_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */ 419 #define _EBI_RDTIMING1_RDSETUP_MASK 0x7UL /**< Bit mask for EBI_RDSETUP */ 420 #define _EBI_RDTIMING1_RDSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING1 */ 421 #define EBI_RDTIMING1_RDSETUP_DEFAULT (_EBI_RDTIMING1_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ 422 #define _EBI_RDTIMING1_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */ 423 #define _EBI_RDTIMING1_RDSTRB_MASK 0x7F00UL /**< Bit mask for EBI_RDSTRB */ 424 #define _EBI_RDTIMING1_RDSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_RDTIMING1 */ 425 #define EBI_RDTIMING1_RDSTRB_DEFAULT (_EBI_RDTIMING1_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ 426 #define _EBI_RDTIMING1_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */ 427 #define _EBI_RDTIMING1_RDHOLD_MASK 0x70000UL /**< Bit mask for EBI_RDHOLD */ 428 #define _EBI_RDTIMING1_RDHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING1 */ 429 #define EBI_RDTIMING1_RDHOLD_DEFAULT (_EBI_RDTIMING1_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ 430 #define EBI_RDTIMING1_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */ 431 #define _EBI_RDTIMING1_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */ 432 #define _EBI_RDTIMING1_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */ 433 #define _EBI_RDTIMING1_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING1 */ 434 #define EBI_RDTIMING1_HALFRE_DEFAULT (_EBI_RDTIMING1_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ 435 #define EBI_RDTIMING1_PREFETCH (0x1UL << 29) /**< Prefetch Enable */ 436 #define _EBI_RDTIMING1_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */ 437 #define _EBI_RDTIMING1_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */ 438 #define _EBI_RDTIMING1_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING1 */ 439 #define EBI_RDTIMING1_PREFETCH_DEFAULT (_EBI_RDTIMING1_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ 440 #define EBI_RDTIMING1_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */ 441 #define _EBI_RDTIMING1_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */ 442 #define _EBI_RDTIMING1_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */ 443 #define _EBI_RDTIMING1_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING1 */ 444 #define EBI_RDTIMING1_PAGEMODE_DEFAULT (_EBI_RDTIMING1_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING1 */ 445 446 /* Bit fields for EBI WRTIMING1 */ 447 #define _EBI_WRTIMING1_RESETVALUE 0x00077F07UL /**< Default value for EBI_WRTIMING1 */ 448 #define _EBI_WRTIMING1_MASK 0x30077F07UL /**< Mask for EBI_WRTIMING1 */ 449 #define _EBI_WRTIMING1_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */ 450 #define _EBI_WRTIMING1_WRSETUP_MASK 0x7UL /**< Bit mask for EBI_WRSETUP */ 451 #define _EBI_WRTIMING1_WRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING1 */ 452 #define EBI_WRTIMING1_WRSETUP_DEFAULT (_EBI_WRTIMING1_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */ 453 #define _EBI_WRTIMING1_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */ 454 #define _EBI_WRTIMING1_WRSTRB_MASK 0x7F00UL /**< Bit mask for EBI_WRSTRB */ 455 #define _EBI_WRTIMING1_WRSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_WRTIMING1 */ 456 #define EBI_WRTIMING1_WRSTRB_DEFAULT (_EBI_WRTIMING1_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */ 457 #define _EBI_WRTIMING1_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */ 458 #define _EBI_WRTIMING1_WRHOLD_MASK 0x70000UL /**< Bit mask for EBI_WRHOLD */ 459 #define _EBI_WRTIMING1_WRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING1 */ 460 #define EBI_WRTIMING1_WRHOLD_DEFAULT (_EBI_WRTIMING1_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */ 461 #define EBI_WRTIMING1_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */ 462 #define _EBI_WRTIMING1_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */ 463 #define _EBI_WRTIMING1_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */ 464 #define _EBI_WRTIMING1_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING1 */ 465 #define EBI_WRTIMING1_HALFWE_DEFAULT (_EBI_WRTIMING1_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */ 466 #define EBI_WRTIMING1_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */ 467 #define _EBI_WRTIMING1_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */ 468 #define _EBI_WRTIMING1_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */ 469 #define _EBI_WRTIMING1_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING1 */ 470 #define EBI_WRTIMING1_WBUFDIS_DEFAULT (_EBI_WRTIMING1_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING1 */ 471 472 /* Bit fields for EBI POLARITY1 */ 473 #define _EBI_POLARITY1_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY1 */ 474 #define _EBI_POLARITY1_MASK 0x0000003FUL /**< Mask for EBI_POLARITY1 */ 475 #define EBI_POLARITY1_CSPOL (0x1UL << 0) /**< Chip Select Polarity */ 476 #define _EBI_POLARITY1_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ 477 #define _EBI_POLARITY1_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ 478 #define _EBI_POLARITY1_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ 479 #define _EBI_POLARITY1_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ 480 #define _EBI_POLARITY1_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ 481 #define EBI_POLARITY1_CSPOL_DEFAULT (_EBI_POLARITY1_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ 482 #define EBI_POLARITY1_CSPOL_ACTIVELOW (_EBI_POLARITY1_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ 483 #define EBI_POLARITY1_CSPOL_ACTIVEHIGH (_EBI_POLARITY1_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ 484 #define EBI_POLARITY1_REPOL (0x1UL << 1) /**< Read Enable Polarity */ 485 #define _EBI_POLARITY1_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */ 486 #define _EBI_POLARITY1_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */ 487 #define _EBI_POLARITY1_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ 488 #define _EBI_POLARITY1_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ 489 #define _EBI_POLARITY1_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ 490 #define EBI_POLARITY1_REPOL_DEFAULT (_EBI_POLARITY1_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ 491 #define EBI_POLARITY1_REPOL_ACTIVELOW (_EBI_POLARITY1_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ 492 #define EBI_POLARITY1_REPOL_ACTIVEHIGH (_EBI_POLARITY1_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ 493 #define EBI_POLARITY1_WEPOL (0x1UL << 2) /**< Write Enable Polarity */ 494 #define _EBI_POLARITY1_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */ 495 #define _EBI_POLARITY1_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */ 496 #define _EBI_POLARITY1_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ 497 #define _EBI_POLARITY1_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ 498 #define _EBI_POLARITY1_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ 499 #define EBI_POLARITY1_WEPOL_DEFAULT (_EBI_POLARITY1_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ 500 #define EBI_POLARITY1_WEPOL_ACTIVELOW (_EBI_POLARITY1_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ 501 #define EBI_POLARITY1_WEPOL_ACTIVEHIGH (_EBI_POLARITY1_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ 502 #define EBI_POLARITY1_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */ 503 #define _EBI_POLARITY1_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */ 504 #define _EBI_POLARITY1_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */ 505 #define _EBI_POLARITY1_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ 506 #define _EBI_POLARITY1_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ 507 #define _EBI_POLARITY1_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ 508 #define EBI_POLARITY1_ALEPOL_DEFAULT (_EBI_POLARITY1_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ 509 #define EBI_POLARITY1_ALEPOL_ACTIVELOW (_EBI_POLARITY1_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ 510 #define EBI_POLARITY1_ALEPOL_ACTIVEHIGH (_EBI_POLARITY1_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ 511 #define EBI_POLARITY1_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */ 512 #define _EBI_POLARITY1_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */ 513 #define _EBI_POLARITY1_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */ 514 #define _EBI_POLARITY1_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ 515 #define _EBI_POLARITY1_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ 516 #define _EBI_POLARITY1_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ 517 #define EBI_POLARITY1_ARDYPOL_DEFAULT (_EBI_POLARITY1_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ 518 #define EBI_POLARITY1_ARDYPOL_ACTIVELOW (_EBI_POLARITY1_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ 519 #define EBI_POLARITY1_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY1_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ 520 #define EBI_POLARITY1_BLPOL (0x1UL << 5) /**< BL Polarity */ 521 #define _EBI_POLARITY1_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */ 522 #define _EBI_POLARITY1_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */ 523 #define _EBI_POLARITY1_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY1 */ 524 #define _EBI_POLARITY1_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY1 */ 525 #define _EBI_POLARITY1_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY1 */ 526 #define EBI_POLARITY1_BLPOL_DEFAULT (_EBI_POLARITY1_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY1 */ 527 #define EBI_POLARITY1_BLPOL_ACTIVELOW (_EBI_POLARITY1_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY1 */ 528 #define EBI_POLARITY1_BLPOL_ACTIVEHIGH (_EBI_POLARITY1_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY1 */ 529 530 /* Bit fields for EBI ADDRTIMING2 */ 531 #define _EBI_ADDRTIMING2_RESETVALUE 0x00000707UL /**< Default value for EBI_ADDRTIMING2 */ 532 #define _EBI_ADDRTIMING2_MASK 0x10000707UL /**< Mask for EBI_ADDRTIMING2 */ 533 #define _EBI_ADDRTIMING2_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */ 534 #define _EBI_ADDRTIMING2_ADDRSETUP_MASK 0x7UL /**< Bit mask for EBI_ADDRSETUP */ 535 #define _EBI_ADDRTIMING2_ADDRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING2 */ 536 #define EBI_ADDRTIMING2_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING2_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */ 537 #define _EBI_ADDRTIMING2_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */ 538 #define _EBI_ADDRTIMING2_ADDRHOLD_MASK 0x700UL /**< Bit mask for EBI_ADDRHOLD */ 539 #define _EBI_ADDRTIMING2_ADDRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING2 */ 540 #define EBI_ADDRTIMING2_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING2_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */ 541 #define EBI_ADDRTIMING2_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */ 542 #define _EBI_ADDRTIMING2_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */ 543 #define _EBI_ADDRTIMING2_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */ 544 #define _EBI_ADDRTIMING2_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING2 */ 545 #define EBI_ADDRTIMING2_HALFALE_DEFAULT (_EBI_ADDRTIMING2_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING2 */ 546 547 /* Bit fields for EBI RDTIMING2 */ 548 #define _EBI_RDTIMING2_RESETVALUE 0x00077F07UL /**< Default value for EBI_RDTIMING2 */ 549 #define _EBI_RDTIMING2_MASK 0x70077F07UL /**< Mask for EBI_RDTIMING2 */ 550 #define _EBI_RDTIMING2_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */ 551 #define _EBI_RDTIMING2_RDSETUP_MASK 0x7UL /**< Bit mask for EBI_RDSETUP */ 552 #define _EBI_RDTIMING2_RDSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING2 */ 553 #define EBI_RDTIMING2_RDSETUP_DEFAULT (_EBI_RDTIMING2_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ 554 #define _EBI_RDTIMING2_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */ 555 #define _EBI_RDTIMING2_RDSTRB_MASK 0x7F00UL /**< Bit mask for EBI_RDSTRB */ 556 #define _EBI_RDTIMING2_RDSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_RDTIMING2 */ 557 #define EBI_RDTIMING2_RDSTRB_DEFAULT (_EBI_RDTIMING2_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ 558 #define _EBI_RDTIMING2_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */ 559 #define _EBI_RDTIMING2_RDHOLD_MASK 0x70000UL /**< Bit mask for EBI_RDHOLD */ 560 #define _EBI_RDTIMING2_RDHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING2 */ 561 #define EBI_RDTIMING2_RDHOLD_DEFAULT (_EBI_RDTIMING2_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ 562 #define EBI_RDTIMING2_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */ 563 #define _EBI_RDTIMING2_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */ 564 #define _EBI_RDTIMING2_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */ 565 #define _EBI_RDTIMING2_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING2 */ 566 #define EBI_RDTIMING2_HALFRE_DEFAULT (_EBI_RDTIMING2_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ 567 #define EBI_RDTIMING2_PREFETCH (0x1UL << 29) /**< Prefetch Enable */ 568 #define _EBI_RDTIMING2_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */ 569 #define _EBI_RDTIMING2_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */ 570 #define _EBI_RDTIMING2_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING2 */ 571 #define EBI_RDTIMING2_PREFETCH_DEFAULT (_EBI_RDTIMING2_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ 572 #define EBI_RDTIMING2_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */ 573 #define _EBI_RDTIMING2_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */ 574 #define _EBI_RDTIMING2_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */ 575 #define _EBI_RDTIMING2_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING2 */ 576 #define EBI_RDTIMING2_PAGEMODE_DEFAULT (_EBI_RDTIMING2_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING2 */ 577 578 /* Bit fields for EBI WRTIMING2 */ 579 #define _EBI_WRTIMING2_RESETVALUE 0x00077F07UL /**< Default value for EBI_WRTIMING2 */ 580 #define _EBI_WRTIMING2_MASK 0x30077F07UL /**< Mask for EBI_WRTIMING2 */ 581 #define _EBI_WRTIMING2_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */ 582 #define _EBI_WRTIMING2_WRSETUP_MASK 0x7UL /**< Bit mask for EBI_WRSETUP */ 583 #define _EBI_WRTIMING2_WRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING2 */ 584 #define EBI_WRTIMING2_WRSETUP_DEFAULT (_EBI_WRTIMING2_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */ 585 #define _EBI_WRTIMING2_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */ 586 #define _EBI_WRTIMING2_WRSTRB_MASK 0x7F00UL /**< Bit mask for EBI_WRSTRB */ 587 #define _EBI_WRTIMING2_WRSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_WRTIMING2 */ 588 #define EBI_WRTIMING2_WRSTRB_DEFAULT (_EBI_WRTIMING2_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */ 589 #define _EBI_WRTIMING2_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */ 590 #define _EBI_WRTIMING2_WRHOLD_MASK 0x70000UL /**< Bit mask for EBI_WRHOLD */ 591 #define _EBI_WRTIMING2_WRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING2 */ 592 #define EBI_WRTIMING2_WRHOLD_DEFAULT (_EBI_WRTIMING2_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */ 593 #define EBI_WRTIMING2_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */ 594 #define _EBI_WRTIMING2_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */ 595 #define _EBI_WRTIMING2_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */ 596 #define _EBI_WRTIMING2_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING2 */ 597 #define EBI_WRTIMING2_HALFWE_DEFAULT (_EBI_WRTIMING2_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */ 598 #define EBI_WRTIMING2_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */ 599 #define _EBI_WRTIMING2_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */ 600 #define _EBI_WRTIMING2_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */ 601 #define _EBI_WRTIMING2_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING2 */ 602 #define EBI_WRTIMING2_WBUFDIS_DEFAULT (_EBI_WRTIMING2_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING2 */ 603 604 /* Bit fields for EBI POLARITY2 */ 605 #define _EBI_POLARITY2_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY2 */ 606 #define _EBI_POLARITY2_MASK 0x0000003FUL /**< Mask for EBI_POLARITY2 */ 607 #define EBI_POLARITY2_CSPOL (0x1UL << 0) /**< Chip Select Polarity */ 608 #define _EBI_POLARITY2_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ 609 #define _EBI_POLARITY2_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ 610 #define _EBI_POLARITY2_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ 611 #define _EBI_POLARITY2_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ 612 #define _EBI_POLARITY2_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ 613 #define EBI_POLARITY2_CSPOL_DEFAULT (_EBI_POLARITY2_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ 614 #define EBI_POLARITY2_CSPOL_ACTIVELOW (_EBI_POLARITY2_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ 615 #define EBI_POLARITY2_CSPOL_ACTIVEHIGH (_EBI_POLARITY2_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ 616 #define EBI_POLARITY2_REPOL (0x1UL << 1) /**< Read Enable Polarity */ 617 #define _EBI_POLARITY2_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */ 618 #define _EBI_POLARITY2_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */ 619 #define _EBI_POLARITY2_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ 620 #define _EBI_POLARITY2_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ 621 #define _EBI_POLARITY2_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ 622 #define EBI_POLARITY2_REPOL_DEFAULT (_EBI_POLARITY2_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ 623 #define EBI_POLARITY2_REPOL_ACTIVELOW (_EBI_POLARITY2_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ 624 #define EBI_POLARITY2_REPOL_ACTIVEHIGH (_EBI_POLARITY2_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ 625 #define EBI_POLARITY2_WEPOL (0x1UL << 2) /**< Write Enable Polarity */ 626 #define _EBI_POLARITY2_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */ 627 #define _EBI_POLARITY2_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */ 628 #define _EBI_POLARITY2_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ 629 #define _EBI_POLARITY2_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ 630 #define _EBI_POLARITY2_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ 631 #define EBI_POLARITY2_WEPOL_DEFAULT (_EBI_POLARITY2_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ 632 #define EBI_POLARITY2_WEPOL_ACTIVELOW (_EBI_POLARITY2_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ 633 #define EBI_POLARITY2_WEPOL_ACTIVEHIGH (_EBI_POLARITY2_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ 634 #define EBI_POLARITY2_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */ 635 #define _EBI_POLARITY2_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */ 636 #define _EBI_POLARITY2_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */ 637 #define _EBI_POLARITY2_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ 638 #define _EBI_POLARITY2_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ 639 #define _EBI_POLARITY2_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ 640 #define EBI_POLARITY2_ALEPOL_DEFAULT (_EBI_POLARITY2_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ 641 #define EBI_POLARITY2_ALEPOL_ACTIVELOW (_EBI_POLARITY2_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ 642 #define EBI_POLARITY2_ALEPOL_ACTIVEHIGH (_EBI_POLARITY2_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ 643 #define EBI_POLARITY2_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */ 644 #define _EBI_POLARITY2_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */ 645 #define _EBI_POLARITY2_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */ 646 #define _EBI_POLARITY2_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ 647 #define _EBI_POLARITY2_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ 648 #define _EBI_POLARITY2_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ 649 #define EBI_POLARITY2_ARDYPOL_DEFAULT (_EBI_POLARITY2_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ 650 #define EBI_POLARITY2_ARDYPOL_ACTIVELOW (_EBI_POLARITY2_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ 651 #define EBI_POLARITY2_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY2_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ 652 #define EBI_POLARITY2_BLPOL (0x1UL << 5) /**< BL Polarity */ 653 #define _EBI_POLARITY2_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */ 654 #define _EBI_POLARITY2_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */ 655 #define _EBI_POLARITY2_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY2 */ 656 #define _EBI_POLARITY2_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY2 */ 657 #define _EBI_POLARITY2_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY2 */ 658 #define EBI_POLARITY2_BLPOL_DEFAULT (_EBI_POLARITY2_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY2 */ 659 #define EBI_POLARITY2_BLPOL_ACTIVELOW (_EBI_POLARITY2_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY2 */ 660 #define EBI_POLARITY2_BLPOL_ACTIVEHIGH (_EBI_POLARITY2_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY2 */ 661 662 /* Bit fields for EBI ADDRTIMING3 */ 663 #define _EBI_ADDRTIMING3_RESETVALUE 0x00000707UL /**< Default value for EBI_ADDRTIMING3 */ 664 #define _EBI_ADDRTIMING3_MASK 0x10000707UL /**< Mask for EBI_ADDRTIMING3 */ 665 #define _EBI_ADDRTIMING3_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */ 666 #define _EBI_ADDRTIMING3_ADDRSETUP_MASK 0x7UL /**< Bit mask for EBI_ADDRSETUP */ 667 #define _EBI_ADDRTIMING3_ADDRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING3 */ 668 #define EBI_ADDRTIMING3_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING3_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */ 669 #define _EBI_ADDRTIMING3_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */ 670 #define _EBI_ADDRTIMING3_ADDRHOLD_MASK 0x700UL /**< Bit mask for EBI_ADDRHOLD */ 671 #define _EBI_ADDRTIMING3_ADDRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_ADDRTIMING3 */ 672 #define EBI_ADDRTIMING3_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING3_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */ 673 #define EBI_ADDRTIMING3_HALFALE (0x1UL << 28) /**< Half Cycle ALE Strobe Duration Enable */ 674 #define _EBI_ADDRTIMING3_HALFALE_SHIFT 28 /**< Shift value for EBI_HALFALE */ 675 #define _EBI_ADDRTIMING3_HALFALE_MASK 0x10000000UL /**< Bit mask for EBI_HALFALE */ 676 #define _EBI_ADDRTIMING3_HALFALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING3 */ 677 #define EBI_ADDRTIMING3_HALFALE_DEFAULT (_EBI_ADDRTIMING3_HALFALE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_ADDRTIMING3 */ 678 679 /* Bit fields for EBI RDTIMING3 */ 680 #define _EBI_RDTIMING3_RESETVALUE 0x00077F07UL /**< Default value for EBI_RDTIMING3 */ 681 #define _EBI_RDTIMING3_MASK 0x70077F07UL /**< Mask for EBI_RDTIMING3 */ 682 #define _EBI_RDTIMING3_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */ 683 #define _EBI_RDTIMING3_RDSETUP_MASK 0x7UL /**< Bit mask for EBI_RDSETUP */ 684 #define _EBI_RDTIMING3_RDSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING3 */ 685 #define EBI_RDTIMING3_RDSETUP_DEFAULT (_EBI_RDTIMING3_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ 686 #define _EBI_RDTIMING3_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */ 687 #define _EBI_RDTIMING3_RDSTRB_MASK 0x7F00UL /**< Bit mask for EBI_RDSTRB */ 688 #define _EBI_RDTIMING3_RDSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_RDTIMING3 */ 689 #define EBI_RDTIMING3_RDSTRB_DEFAULT (_EBI_RDTIMING3_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ 690 #define _EBI_RDTIMING3_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */ 691 #define _EBI_RDTIMING3_RDHOLD_MASK 0x70000UL /**< Bit mask for EBI_RDHOLD */ 692 #define _EBI_RDTIMING3_RDHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_RDTIMING3 */ 693 #define EBI_RDTIMING3_RDHOLD_DEFAULT (_EBI_RDTIMING3_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ 694 #define EBI_RDTIMING3_HALFRE (0x1UL << 28) /**< Half Cycle REn Strobe Duration Enable */ 695 #define _EBI_RDTIMING3_HALFRE_SHIFT 28 /**< Shift value for EBI_HALFRE */ 696 #define _EBI_RDTIMING3_HALFRE_MASK 0x10000000UL /**< Bit mask for EBI_HALFRE */ 697 #define _EBI_RDTIMING3_HALFRE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING3 */ 698 #define EBI_RDTIMING3_HALFRE_DEFAULT (_EBI_RDTIMING3_HALFRE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ 699 #define EBI_RDTIMING3_PREFETCH (0x1UL << 29) /**< Prefetch Enable */ 700 #define _EBI_RDTIMING3_PREFETCH_SHIFT 29 /**< Shift value for EBI_PREFETCH */ 701 #define _EBI_RDTIMING3_PREFETCH_MASK 0x20000000UL /**< Bit mask for EBI_PREFETCH */ 702 #define _EBI_RDTIMING3_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING3 */ 703 #define EBI_RDTIMING3_PREFETCH_DEFAULT (_EBI_RDTIMING3_PREFETCH_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ 704 #define EBI_RDTIMING3_PAGEMODE (0x1UL << 30) /**< Page Mode Access Enable */ 705 #define _EBI_RDTIMING3_PAGEMODE_SHIFT 30 /**< Shift value for EBI_PAGEMODE */ 706 #define _EBI_RDTIMING3_PAGEMODE_MASK 0x40000000UL /**< Bit mask for EBI_PAGEMODE */ 707 #define _EBI_RDTIMING3_PAGEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING3 */ 708 #define EBI_RDTIMING3_PAGEMODE_DEFAULT (_EBI_RDTIMING3_PAGEMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for EBI_RDTIMING3 */ 709 710 /* Bit fields for EBI WRTIMING3 */ 711 #define _EBI_WRTIMING3_RESETVALUE 0x00077F07UL /**< Default value for EBI_WRTIMING3 */ 712 #define _EBI_WRTIMING3_MASK 0x30077F07UL /**< Mask for EBI_WRTIMING3 */ 713 #define _EBI_WRTIMING3_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */ 714 #define _EBI_WRTIMING3_WRSETUP_MASK 0x7UL /**< Bit mask for EBI_WRSETUP */ 715 #define _EBI_WRTIMING3_WRSETUP_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING3 */ 716 #define EBI_WRTIMING3_WRSETUP_DEFAULT (_EBI_WRTIMING3_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */ 717 #define _EBI_WRTIMING3_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */ 718 #define _EBI_WRTIMING3_WRSTRB_MASK 0x7F00UL /**< Bit mask for EBI_WRSTRB */ 719 #define _EBI_WRTIMING3_WRSTRB_DEFAULT 0x0000007FUL /**< Mode DEFAULT for EBI_WRTIMING3 */ 720 #define EBI_WRTIMING3_WRSTRB_DEFAULT (_EBI_WRTIMING3_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */ 721 #define _EBI_WRTIMING3_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */ 722 #define _EBI_WRTIMING3_WRHOLD_MASK 0x70000UL /**< Bit mask for EBI_WRHOLD */ 723 #define _EBI_WRTIMING3_WRHOLD_DEFAULT 0x00000007UL /**< Mode DEFAULT for EBI_WRTIMING3 */ 724 #define EBI_WRTIMING3_WRHOLD_DEFAULT (_EBI_WRTIMING3_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */ 725 #define EBI_WRTIMING3_HALFWE (0x1UL << 28) /**< Half Cycle WEn Strobe Duration Enable */ 726 #define _EBI_WRTIMING3_HALFWE_SHIFT 28 /**< Shift value for EBI_HALFWE */ 727 #define _EBI_WRTIMING3_HALFWE_MASK 0x10000000UL /**< Bit mask for EBI_HALFWE */ 728 #define _EBI_WRTIMING3_HALFWE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING3 */ 729 #define EBI_WRTIMING3_HALFWE_DEFAULT (_EBI_WRTIMING3_HALFWE_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */ 730 #define EBI_WRTIMING3_WBUFDIS (0x1UL << 29) /**< Write Buffer Disable */ 731 #define _EBI_WRTIMING3_WBUFDIS_SHIFT 29 /**< Shift value for EBI_WBUFDIS */ 732 #define _EBI_WRTIMING3_WBUFDIS_MASK 0x20000000UL /**< Bit mask for EBI_WBUFDIS */ 733 #define _EBI_WRTIMING3_WBUFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING3 */ 734 #define EBI_WRTIMING3_WBUFDIS_DEFAULT (_EBI_WRTIMING3_WBUFDIS_DEFAULT << 29) /**< Shifted mode DEFAULT for EBI_WRTIMING3 */ 735 736 /* Bit fields for EBI POLARITY3 */ 737 #define _EBI_POLARITY3_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY3 */ 738 #define _EBI_POLARITY3_MASK 0x0000003FUL /**< Mask for EBI_POLARITY3 */ 739 #define EBI_POLARITY3_CSPOL (0x1UL << 0) /**< Chip Select Polarity */ 740 #define _EBI_POLARITY3_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ 741 #define _EBI_POLARITY3_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ 742 #define _EBI_POLARITY3_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ 743 #define _EBI_POLARITY3_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ 744 #define _EBI_POLARITY3_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ 745 #define EBI_POLARITY3_CSPOL_DEFAULT (_EBI_POLARITY3_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ 746 #define EBI_POLARITY3_CSPOL_ACTIVELOW (_EBI_POLARITY3_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ 747 #define EBI_POLARITY3_CSPOL_ACTIVEHIGH (_EBI_POLARITY3_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ 748 #define EBI_POLARITY3_REPOL (0x1UL << 1) /**< Read Enable Polarity */ 749 #define _EBI_POLARITY3_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */ 750 #define _EBI_POLARITY3_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */ 751 #define _EBI_POLARITY3_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ 752 #define _EBI_POLARITY3_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ 753 #define _EBI_POLARITY3_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ 754 #define EBI_POLARITY3_REPOL_DEFAULT (_EBI_POLARITY3_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ 755 #define EBI_POLARITY3_REPOL_ACTIVELOW (_EBI_POLARITY3_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ 756 #define EBI_POLARITY3_REPOL_ACTIVEHIGH (_EBI_POLARITY3_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ 757 #define EBI_POLARITY3_WEPOL (0x1UL << 2) /**< Write Enable Polarity */ 758 #define _EBI_POLARITY3_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */ 759 #define _EBI_POLARITY3_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */ 760 #define _EBI_POLARITY3_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ 761 #define _EBI_POLARITY3_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ 762 #define _EBI_POLARITY3_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ 763 #define EBI_POLARITY3_WEPOL_DEFAULT (_EBI_POLARITY3_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ 764 #define EBI_POLARITY3_WEPOL_ACTIVELOW (_EBI_POLARITY3_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ 765 #define EBI_POLARITY3_WEPOL_ACTIVEHIGH (_EBI_POLARITY3_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ 766 #define EBI_POLARITY3_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */ 767 #define _EBI_POLARITY3_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */ 768 #define _EBI_POLARITY3_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */ 769 #define _EBI_POLARITY3_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ 770 #define _EBI_POLARITY3_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ 771 #define _EBI_POLARITY3_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ 772 #define EBI_POLARITY3_ALEPOL_DEFAULT (_EBI_POLARITY3_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ 773 #define EBI_POLARITY3_ALEPOL_ACTIVELOW (_EBI_POLARITY3_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ 774 #define EBI_POLARITY3_ALEPOL_ACTIVEHIGH (_EBI_POLARITY3_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ 775 #define EBI_POLARITY3_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */ 776 #define _EBI_POLARITY3_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */ 777 #define _EBI_POLARITY3_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */ 778 #define _EBI_POLARITY3_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ 779 #define _EBI_POLARITY3_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ 780 #define _EBI_POLARITY3_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ 781 #define EBI_POLARITY3_ARDYPOL_DEFAULT (_EBI_POLARITY3_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ 782 #define EBI_POLARITY3_ARDYPOL_ACTIVELOW (_EBI_POLARITY3_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ 783 #define EBI_POLARITY3_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY3_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ 784 #define EBI_POLARITY3_BLPOL (0x1UL << 5) /**< BL Polarity */ 785 #define _EBI_POLARITY3_BLPOL_SHIFT 5 /**< Shift value for EBI_BLPOL */ 786 #define _EBI_POLARITY3_BLPOL_MASK 0x20UL /**< Bit mask for EBI_BLPOL */ 787 #define _EBI_POLARITY3_BLPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY3 */ 788 #define _EBI_POLARITY3_BLPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY3 */ 789 #define _EBI_POLARITY3_BLPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY3 */ 790 #define EBI_POLARITY3_BLPOL_DEFAULT (_EBI_POLARITY3_BLPOL_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_POLARITY3 */ 791 #define EBI_POLARITY3_BLPOL_ACTIVELOW (_EBI_POLARITY3_BLPOL_ACTIVELOW << 5) /**< Shifted mode ACTIVELOW for EBI_POLARITY3 */ 792 #define EBI_POLARITY3_BLPOL_ACTIVEHIGH (_EBI_POLARITY3_BLPOL_ACTIVEHIGH << 5) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY3 */ 793 794 /* Bit fields for EBI PAGECTRL */ 795 #define _EBI_PAGECTRL_RESETVALUE 0x00000F00UL /**< Default value for EBI_PAGECTRL */ 796 #define _EBI_PAGECTRL_MASK 0x07F00F13UL /**< Mask for EBI_PAGECTRL */ 797 #define _EBI_PAGECTRL_PAGELEN_SHIFT 0 /**< Shift value for EBI_PAGELEN */ 798 #define _EBI_PAGECTRL_PAGELEN_MASK 0x3UL /**< Bit mask for EBI_PAGELEN */ 799 #define _EBI_PAGECTRL_PAGELEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_PAGECTRL */ 800 #define _EBI_PAGECTRL_PAGELEN_MEMBER4 0x00000000UL /**< Mode MEMBER4 for EBI_PAGECTRL */ 801 #define _EBI_PAGECTRL_PAGELEN_MEMBER8 0x00000001UL /**< Mode MEMBER8 for EBI_PAGECTRL */ 802 #define _EBI_PAGECTRL_PAGELEN_MEMBER16 0x00000002UL /**< Mode MEMBER16 for EBI_PAGECTRL */ 803 #define _EBI_PAGECTRL_PAGELEN_MEMBER32 0x00000003UL /**< Mode MEMBER32 for EBI_PAGECTRL */ 804 #define EBI_PAGECTRL_PAGELEN_DEFAULT (_EBI_PAGECTRL_PAGELEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_PAGECTRL */ 805 #define EBI_PAGECTRL_PAGELEN_MEMBER4 (_EBI_PAGECTRL_PAGELEN_MEMBER4 << 0) /**< Shifted mode MEMBER4 for EBI_PAGECTRL */ 806 #define EBI_PAGECTRL_PAGELEN_MEMBER8 (_EBI_PAGECTRL_PAGELEN_MEMBER8 << 0) /**< Shifted mode MEMBER8 for EBI_PAGECTRL */ 807 #define EBI_PAGECTRL_PAGELEN_MEMBER16 (_EBI_PAGECTRL_PAGELEN_MEMBER16 << 0) /**< Shifted mode MEMBER16 for EBI_PAGECTRL */ 808 #define EBI_PAGECTRL_PAGELEN_MEMBER32 (_EBI_PAGECTRL_PAGELEN_MEMBER32 << 0) /**< Shifted mode MEMBER32 for EBI_PAGECTRL */ 809 #define EBI_PAGECTRL_INCHIT (0x1UL << 4) /**< Intrapage Hit Only on Incremental Addresses */ 810 #define _EBI_PAGECTRL_INCHIT_SHIFT 4 /**< Shift value for EBI_INCHIT */ 811 #define _EBI_PAGECTRL_INCHIT_MASK 0x10UL /**< Bit mask for EBI_INCHIT */ 812 #define _EBI_PAGECTRL_INCHIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_PAGECTRL */ 813 #define EBI_PAGECTRL_INCHIT_DEFAULT (_EBI_PAGECTRL_INCHIT_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_PAGECTRL */ 814 #define _EBI_PAGECTRL_RDPA_SHIFT 8 /**< Shift value for EBI_RDPA */ 815 #define _EBI_PAGECTRL_RDPA_MASK 0xF00UL /**< Bit mask for EBI_RDPA */ 816 #define _EBI_PAGECTRL_RDPA_DEFAULT 0x0000000FUL /**< Mode DEFAULT for EBI_PAGECTRL */ 817 #define EBI_PAGECTRL_RDPA_DEFAULT (_EBI_PAGECTRL_RDPA_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_PAGECTRL */ 818 #define _EBI_PAGECTRL_KEEPOPEN_SHIFT 20 /**< Shift value for EBI_KEEPOPEN */ 819 #define _EBI_PAGECTRL_KEEPOPEN_MASK 0x7F00000UL /**< Bit mask for EBI_KEEPOPEN */ 820 #define _EBI_PAGECTRL_KEEPOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_PAGECTRL */ 821 #define EBI_PAGECTRL_KEEPOPEN_DEFAULT (_EBI_PAGECTRL_KEEPOPEN_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_PAGECTRL */ 822 823 /* Bit fields for EBI NANDCTRL */ 824 #define _EBI_NANDCTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_NANDCTRL */ 825 #define _EBI_NANDCTRL_MASK 0x00000031UL /**< Mask for EBI_NANDCTRL */ 826 #define EBI_NANDCTRL_EN (0x1UL << 0) /**< NAND Flash Control Enable */ 827 #define _EBI_NANDCTRL_EN_SHIFT 0 /**< Shift value for EBI_EN */ 828 #define _EBI_NANDCTRL_EN_MASK 0x1UL /**< Bit mask for EBI_EN */ 829 #define _EBI_NANDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_NANDCTRL */ 830 #define EBI_NANDCTRL_EN_DEFAULT (_EBI_NANDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_NANDCTRL */ 831 #define _EBI_NANDCTRL_BANKSEL_SHIFT 4 /**< Shift value for EBI_BANKSEL */ 832 #define _EBI_NANDCTRL_BANKSEL_MASK 0x30UL /**< Bit mask for EBI_BANKSEL */ 833 #define _EBI_NANDCTRL_BANKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_NANDCTRL */ 834 #define _EBI_NANDCTRL_BANKSEL_BANK0 0x00000000UL /**< Mode BANK0 for EBI_NANDCTRL */ 835 #define _EBI_NANDCTRL_BANKSEL_BANK1 0x00000001UL /**< Mode BANK1 for EBI_NANDCTRL */ 836 #define _EBI_NANDCTRL_BANKSEL_BANK2 0x00000002UL /**< Mode BANK2 for EBI_NANDCTRL */ 837 #define _EBI_NANDCTRL_BANKSEL_BANK3 0x00000003UL /**< Mode BANK3 for EBI_NANDCTRL */ 838 #define EBI_NANDCTRL_BANKSEL_DEFAULT (_EBI_NANDCTRL_BANKSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_NANDCTRL */ 839 #define EBI_NANDCTRL_BANKSEL_BANK0 (_EBI_NANDCTRL_BANKSEL_BANK0 << 4) /**< Shifted mode BANK0 for EBI_NANDCTRL */ 840 #define EBI_NANDCTRL_BANKSEL_BANK1 (_EBI_NANDCTRL_BANKSEL_BANK1 << 4) /**< Shifted mode BANK1 for EBI_NANDCTRL */ 841 #define EBI_NANDCTRL_BANKSEL_BANK2 (_EBI_NANDCTRL_BANKSEL_BANK2 << 4) /**< Shifted mode BANK2 for EBI_NANDCTRL */ 842 #define EBI_NANDCTRL_BANKSEL_BANK3 (_EBI_NANDCTRL_BANKSEL_BANK3 << 4) /**< Shifted mode BANK3 for EBI_NANDCTRL */ 843 844 /* Bit fields for EBI CMD */ 845 #define _EBI_CMD_RESETVALUE 0x00000000UL /**< Default value for EBI_CMD */ 846 #define _EBI_CMD_MASK 0x00000007UL /**< Mask for EBI_CMD */ 847 #define EBI_CMD_ECCSTART (0x1UL << 0) /**< Error Correction Code Generation Start */ 848 #define _EBI_CMD_ECCSTART_SHIFT 0 /**< Shift value for EBI_ECCSTART */ 849 #define _EBI_CMD_ECCSTART_MASK 0x1UL /**< Bit mask for EBI_ECCSTART */ 850 #define _EBI_CMD_ECCSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CMD */ 851 #define EBI_CMD_ECCSTART_DEFAULT (_EBI_CMD_ECCSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_CMD */ 852 #define EBI_CMD_ECCSTOP (0x1UL << 1) /**< Error Correction Code Generation Stop */ 853 #define _EBI_CMD_ECCSTOP_SHIFT 1 /**< Shift value for EBI_ECCSTOP */ 854 #define _EBI_CMD_ECCSTOP_MASK 0x2UL /**< Bit mask for EBI_ECCSTOP */ 855 #define _EBI_CMD_ECCSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CMD */ 856 #define EBI_CMD_ECCSTOP_DEFAULT (_EBI_CMD_ECCSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_CMD */ 857 #define EBI_CMD_ECCCLEAR (0x1UL << 2) /**< Error Correction Code Clear */ 858 #define _EBI_CMD_ECCCLEAR_SHIFT 2 /**< Shift value for EBI_ECCCLEAR */ 859 #define _EBI_CMD_ECCCLEAR_MASK 0x4UL /**< Bit mask for EBI_ECCCLEAR */ 860 #define _EBI_CMD_ECCCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CMD */ 861 #define EBI_CMD_ECCCLEAR_DEFAULT (_EBI_CMD_ECCCLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_CMD */ 862 863 /* Bit fields for EBI STATUS */ 864 #define _EBI_STATUS_RESETVALUE 0x00000000UL /**< Default value for EBI_STATUS */ 865 #define _EBI_STATUS_MASK 0x00003711UL /**< Mask for EBI_STATUS */ 866 #define EBI_STATUS_AHBACT (0x1UL << 0) /**< EBI Busy With AHB Transaction */ 867 #define _EBI_STATUS_AHBACT_SHIFT 0 /**< Shift value for EBI_AHBACT */ 868 #define _EBI_STATUS_AHBACT_MASK 0x1UL /**< Bit mask for EBI_AHBACT */ 869 #define _EBI_STATUS_AHBACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ 870 #define EBI_STATUS_AHBACT_DEFAULT (_EBI_STATUS_AHBACT_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_STATUS */ 871 #define EBI_STATUS_ECCACT (0x1UL << 4) /**< EBI ECC Generation Active */ 872 #define _EBI_STATUS_ECCACT_SHIFT 4 /**< Shift value for EBI_ECCACT */ 873 #define _EBI_STATUS_ECCACT_MASK 0x10UL /**< Bit mask for EBI_ECCACT */ 874 #define _EBI_STATUS_ECCACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ 875 #define EBI_STATUS_ECCACT_DEFAULT (_EBI_STATUS_ECCACT_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_STATUS */ 876 #define EBI_STATUS_TFTPIXEL0EMPTY (0x1UL << 8) /**< EBI_TFTPIXEL0 is Empty */ 877 #define _EBI_STATUS_TFTPIXEL0EMPTY_SHIFT 8 /**< Shift value for EBI_TFTPIXEL0EMPTY */ 878 #define _EBI_STATUS_TFTPIXEL0EMPTY_MASK 0x100UL /**< Bit mask for EBI_TFTPIXEL0EMPTY */ 879 #define _EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ 880 #define EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT (_EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_STATUS */ 881 #define EBI_STATUS_TFTPIXEL1EMPTY (0x1UL << 9) /**< EBI_TFTPIXEL1 is Empty */ 882 #define _EBI_STATUS_TFTPIXEL1EMPTY_SHIFT 9 /**< Shift value for EBI_TFTPIXEL1EMPTY */ 883 #define _EBI_STATUS_TFTPIXEL1EMPTY_MASK 0x200UL /**< Bit mask for EBI_TFTPIXEL1EMPTY */ 884 #define _EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ 885 #define EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT (_EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_STATUS */ 886 #define EBI_STATUS_TFTPIXELFULL (0x1UL << 10) /**< EBI_TFTPIXEL0 is Full */ 887 #define _EBI_STATUS_TFTPIXELFULL_SHIFT 10 /**< Shift value for EBI_TFTPIXELFULL */ 888 #define _EBI_STATUS_TFTPIXELFULL_MASK 0x400UL /**< Bit mask for EBI_TFTPIXELFULL */ 889 #define _EBI_STATUS_TFTPIXELFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ 890 #define EBI_STATUS_TFTPIXELFULL_DEFAULT (_EBI_STATUS_TFTPIXELFULL_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_STATUS */ 891 #define EBI_STATUS_DDACT (0x1UL << 12) /**< EBI Busy With Direct Drive Transactions */ 892 #define _EBI_STATUS_DDACT_SHIFT 12 /**< Shift value for EBI_DDACT */ 893 #define _EBI_STATUS_DDACT_MASK 0x1000UL /**< Bit mask for EBI_DDACT */ 894 #define _EBI_STATUS_DDACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ 895 #define EBI_STATUS_DDACT_DEFAULT (_EBI_STATUS_DDACT_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_STATUS */ 896 #define EBI_STATUS_TFTDDEMPTY (0x1UL << 13) /**< EBI_TFTDD Register is Empty */ 897 #define _EBI_STATUS_TFTDDEMPTY_SHIFT 13 /**< Shift value for EBI_TFTDDEMPTY */ 898 #define _EBI_STATUS_TFTDDEMPTY_MASK 0x2000UL /**< Bit mask for EBI_TFTDDEMPTY */ 899 #define _EBI_STATUS_TFTDDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_STATUS */ 900 #define EBI_STATUS_TFTDDEMPTY_DEFAULT (_EBI_STATUS_TFTDDEMPTY_DEFAULT << 13) /**< Shifted mode DEFAULT for EBI_STATUS */ 901 902 /* Bit fields for EBI ECCPARITY */ 903 #define _EBI_ECCPARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_ECCPARITY */ 904 #define _EBI_ECCPARITY_MASK 0xFFFFFFFFUL /**< Mask for EBI_ECCPARITY */ 905 #define _EBI_ECCPARITY_ECCPARITY_SHIFT 0 /**< Shift value for EBI_ECCPARITY */ 906 #define _EBI_ECCPARITY_ECCPARITY_MASK 0xFFFFFFFFUL /**< Bit mask for EBI_ECCPARITY */ 907 #define _EBI_ECCPARITY_ECCPARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ECCPARITY */ 908 #define EBI_ECCPARITY_ECCPARITY_DEFAULT (_EBI_ECCPARITY_ECCPARITY_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ECCPARITY */ 909 910 /* Bit fields for EBI TFTCTRL */ 911 #define _EBI_TFTCTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTCTRL */ 912 #define _EBI_TFTCTRL_MASK 0x00FB1F3FUL /**< Mask for EBI_TFTCTRL */ 913 #define _EBI_TFTCTRL_DD_SHIFT 0 /**< Shift value for EBI_DD */ 914 #define _EBI_TFTCTRL_DD_MASK 0x3UL /**< Bit mask for EBI_DD */ 915 #define _EBI_TFTCTRL_DD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ 916 #define _EBI_TFTCTRL_DD_DISABLED 0x00000000UL /**< Mode DISABLED for EBI_TFTCTRL */ 917 #define _EBI_TFTCTRL_DD_INTERNAL 0x00000001UL /**< Mode INTERNAL for EBI_TFTCTRL */ 918 #define _EBI_TFTCTRL_DD_EXTERNAL 0x00000002UL /**< Mode EXTERNAL for EBI_TFTCTRL */ 919 #define EBI_TFTCTRL_DD_DEFAULT (_EBI_TFTCTRL_DD_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ 920 #define EBI_TFTCTRL_DD_DISABLED (_EBI_TFTCTRL_DD_DISABLED << 0) /**< Shifted mode DISABLED for EBI_TFTCTRL */ 921 #define EBI_TFTCTRL_DD_INTERNAL (_EBI_TFTCTRL_DD_INTERNAL << 0) /**< Shifted mode INTERNAL for EBI_TFTCTRL */ 922 #define EBI_TFTCTRL_DD_EXTERNAL (_EBI_TFTCTRL_DD_EXTERNAL << 0) /**< Shifted mode EXTERNAL for EBI_TFTCTRL */ 923 #define _EBI_TFTCTRL_MASKBLEND_SHIFT 2 /**< Shift value for EBI_MASKBLEND */ 924 #define _EBI_TFTCTRL_MASKBLEND_MASK 0x3CUL /**< Bit mask for EBI_MASKBLEND */ 925 #define _EBI_TFTCTRL_MASKBLEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ 926 #define _EBI_TFTCTRL_MASKBLEND_DISABLED 0x00000000UL /**< Mode DISABLED for EBI_TFTCTRL */ 927 #define _EBI_TFTCTRL_MASKBLEND_IMASK 0x00000001UL /**< Mode IMASK for EBI_TFTCTRL */ 928 #define _EBI_TFTCTRL_MASKBLEND_IALPHA 0x00000002UL /**< Mode IALPHA for EBI_TFTCTRL */ 929 #define _EBI_TFTCTRL_MASKBLEND_IMASKALPHA 0x00000003UL /**< Mode IMASKALPHA for EBI_TFTCTRL */ 930 #define _EBI_TFTCTRL_MASKBLEND_EFBMASK 0x00000004UL /**< Mode EFBMASK for EBI_TFTCTRL */ 931 #define _EBI_TFTCTRL_MASKBLEND_EFBALPHA 0x00000005UL /**< Mode EFBALPHA for EBI_TFTCTRL */ 932 #define _EBI_TFTCTRL_MASKBLEND_EFBMASKALPHA 0x00000006UL /**< Mode EFBMASKALPHA for EBI_TFTCTRL */ 933 #define _EBI_TFTCTRL_MASKBLEND_IFBMASK 0x00000007UL /**< Mode IFBMASK for EBI_TFTCTRL */ 934 #define _EBI_TFTCTRL_MASKBLEND_IFBALPHA 0x00000008UL /**< Mode IFBALPHA for EBI_TFTCTRL */ 935 #define _EBI_TFTCTRL_MASKBLEND_IFBMASKALPHA 0x00000009UL /**< Mode IFBMASKALPHA for EBI_TFTCTRL */ 936 #define EBI_TFTCTRL_MASKBLEND_DEFAULT (_EBI_TFTCTRL_MASKBLEND_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ 937 #define EBI_TFTCTRL_MASKBLEND_DISABLED (_EBI_TFTCTRL_MASKBLEND_DISABLED << 2) /**< Shifted mode DISABLED for EBI_TFTCTRL */ 938 #define EBI_TFTCTRL_MASKBLEND_IMASK (_EBI_TFTCTRL_MASKBLEND_IMASK << 2) /**< Shifted mode IMASK for EBI_TFTCTRL */ 939 #define EBI_TFTCTRL_MASKBLEND_IALPHA (_EBI_TFTCTRL_MASKBLEND_IALPHA << 2) /**< Shifted mode IALPHA for EBI_TFTCTRL */ 940 #define EBI_TFTCTRL_MASKBLEND_IMASKALPHA (_EBI_TFTCTRL_MASKBLEND_IMASKALPHA << 2) /**< Shifted mode IMASKALPHA for EBI_TFTCTRL */ 941 #define EBI_TFTCTRL_MASKBLEND_EFBMASK (_EBI_TFTCTRL_MASKBLEND_EFBMASK << 2) /**< Shifted mode EFBMASK for EBI_TFTCTRL */ 942 #define EBI_TFTCTRL_MASKBLEND_EFBALPHA (_EBI_TFTCTRL_MASKBLEND_EFBALPHA << 2) /**< Shifted mode EFBALPHA for EBI_TFTCTRL */ 943 #define EBI_TFTCTRL_MASKBLEND_EFBMASKALPHA (_EBI_TFTCTRL_MASKBLEND_EFBMASKALPHA << 2) /**< Shifted mode EFBMASKALPHA for EBI_TFTCTRL */ 944 #define EBI_TFTCTRL_MASKBLEND_IFBMASK (_EBI_TFTCTRL_MASKBLEND_IFBMASK << 2) /**< Shifted mode IFBMASK for EBI_TFTCTRL */ 945 #define EBI_TFTCTRL_MASKBLEND_IFBALPHA (_EBI_TFTCTRL_MASKBLEND_IFBALPHA << 2) /**< Shifted mode IFBALPHA for EBI_TFTCTRL */ 946 #define EBI_TFTCTRL_MASKBLEND_IFBMASKALPHA (_EBI_TFTCTRL_MASKBLEND_IFBMASKALPHA << 2) /**< Shifted mode IFBMASKALPHA for EBI_TFTCTRL */ 947 #define EBI_TFTCTRL_SHIFTDCLKEN (0x1UL << 8) /**< TFT EBI_DCLK Shift Enable */ 948 #define _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT 8 /**< Shift value for EBI_SHIFTDCLKEN */ 949 #define _EBI_TFTCTRL_SHIFTDCLKEN_MASK 0x100UL /**< Bit mask for EBI_SHIFTDCLKEN */ 950 #define _EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ 951 #define EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT (_EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ 952 #define EBI_TFTCTRL_FBCTRIG (0x1UL << 9) /**< TFT Frame Base Copy Trigger */ 953 #define _EBI_TFTCTRL_FBCTRIG_SHIFT 9 /**< Shift value for EBI_FBCTRIG */ 954 #define _EBI_TFTCTRL_FBCTRIG_MASK 0x200UL /**< Bit mask for EBI_FBCTRIG */ 955 #define _EBI_TFTCTRL_FBCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ 956 #define _EBI_TFTCTRL_FBCTRIG_VSYNC 0x00000000UL /**< Mode VSYNC for EBI_TFTCTRL */ 957 #define _EBI_TFTCTRL_FBCTRIG_HSYNC 0x00000001UL /**< Mode HSYNC for EBI_TFTCTRL */ 958 #define EBI_TFTCTRL_FBCTRIG_DEFAULT (_EBI_TFTCTRL_FBCTRIG_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ 959 #define EBI_TFTCTRL_FBCTRIG_VSYNC (_EBI_TFTCTRL_FBCTRIG_VSYNC << 9) /**< Shifted mode VSYNC for EBI_TFTCTRL */ 960 #define EBI_TFTCTRL_FBCTRIG_HSYNC (_EBI_TFTCTRL_FBCTRIG_HSYNC << 9) /**< Shifted mode HSYNC for EBI_TFTCTRL */ 961 #define _EBI_TFTCTRL_INTERLEAVE_SHIFT 10 /**< Shift value for EBI_INTERLEAVE */ 962 #define _EBI_TFTCTRL_INTERLEAVE_MASK 0xC00UL /**< Bit mask for EBI_INTERLEAVE */ 963 #define _EBI_TFTCTRL_INTERLEAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ 964 #define _EBI_TFTCTRL_INTERLEAVE_UNLIMITED 0x00000000UL /**< Mode UNLIMITED for EBI_TFTCTRL */ 965 #define _EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK 0x00000001UL /**< Mode ONEPERDCLK for EBI_TFTCTRL */ 966 #define _EBI_TFTCTRL_INTERLEAVE_PORCH 0x00000002UL /**< Mode PORCH for EBI_TFTCTRL */ 967 #define EBI_TFTCTRL_INTERLEAVE_DEFAULT (_EBI_TFTCTRL_INTERLEAVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ 968 #define EBI_TFTCTRL_INTERLEAVE_UNLIMITED (_EBI_TFTCTRL_INTERLEAVE_UNLIMITED << 10) /**< Shifted mode UNLIMITED for EBI_TFTCTRL */ 969 #define EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK (_EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK << 10) /**< Shifted mode ONEPERDCLK for EBI_TFTCTRL */ 970 #define EBI_TFTCTRL_INTERLEAVE_PORCH (_EBI_TFTCTRL_INTERLEAVE_PORCH << 10) /**< Shifted mode PORCH for EBI_TFTCTRL */ 971 #define EBI_TFTCTRL_COLOR1SRC (0x1UL << 12) /**< Masking/Alpha Blending Color1 Source */ 972 #define _EBI_TFTCTRL_COLOR1SRC_SHIFT 12 /**< Shift value for EBI_COLOR1SRC */ 973 #define _EBI_TFTCTRL_COLOR1SRC_MASK 0x1000UL /**< Bit mask for EBI_COLOR1SRC */ 974 #define _EBI_TFTCTRL_COLOR1SRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ 975 #define _EBI_TFTCTRL_COLOR1SRC_MEM 0x00000000UL /**< Mode MEM for EBI_TFTCTRL */ 976 #define _EBI_TFTCTRL_COLOR1SRC_PIXEL1 0x00000001UL /**< Mode PIXEL1 for EBI_TFTCTRL */ 977 #define EBI_TFTCTRL_COLOR1SRC_DEFAULT (_EBI_TFTCTRL_COLOR1SRC_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ 978 #define EBI_TFTCTRL_COLOR1SRC_MEM (_EBI_TFTCTRL_COLOR1SRC_MEM << 12) /**< Shifted mode MEM for EBI_TFTCTRL */ 979 #define EBI_TFTCTRL_COLOR1SRC_PIXEL1 (_EBI_TFTCTRL_COLOR1SRC_PIXEL1 << 12) /**< Shifted mode PIXEL1 for EBI_TFTCTRL */ 980 #define _EBI_TFTCTRL_WIDTH_SHIFT 16 /**< Shift value for EBI_WIDTH */ 981 #define _EBI_TFTCTRL_WIDTH_MASK 0x30000UL /**< Bit mask for EBI_WIDTH */ 982 #define _EBI_TFTCTRL_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ 983 #define _EBI_TFTCTRL_WIDTH_BYTE 0x00000000UL /**< Mode BYTE for EBI_TFTCTRL */ 984 #define _EBI_TFTCTRL_WIDTH_HALFWORD 0x00000001UL /**< Mode HALFWORD for EBI_TFTCTRL */ 985 #define EBI_TFTCTRL_WIDTH_DEFAULT (_EBI_TFTCTRL_WIDTH_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ 986 #define EBI_TFTCTRL_WIDTH_BYTE (_EBI_TFTCTRL_WIDTH_BYTE << 16) /**< Shifted mode BYTE for EBI_TFTCTRL */ 987 #define EBI_TFTCTRL_WIDTH_HALFWORD (_EBI_TFTCTRL_WIDTH_HALFWORD << 16) /**< Shifted mode HALFWORD for EBI_TFTCTRL */ 988 #define EBI_TFTCTRL_ALIASBANKEN (0x1UL << 19) /**< Alias to Graphics Bank Enable */ 989 #define _EBI_TFTCTRL_ALIASBANKEN_SHIFT 19 /**< Shift value for EBI_ALIASBANKEN */ 990 #define _EBI_TFTCTRL_ALIASBANKEN_MASK 0x80000UL /**< Bit mask for EBI_ALIASBANKEN */ 991 #define _EBI_TFTCTRL_ALIASBANKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ 992 #define _EBI_TFTCTRL_ALIASBANKEN_DISABLE 0x00000000UL /**< Mode DISABLE for EBI_TFTCTRL */ 993 #define _EBI_TFTCTRL_ALIASBANKEN_ENABLE 0x00000001UL /**< Mode ENABLE for EBI_TFTCTRL */ 994 #define EBI_TFTCTRL_ALIASBANKEN_DEFAULT (_EBI_TFTCTRL_ALIASBANKEN_DEFAULT << 19) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ 995 #define EBI_TFTCTRL_ALIASBANKEN_DISABLE (_EBI_TFTCTRL_ALIASBANKEN_DISABLE << 19) /**< Shifted mode DISABLE for EBI_TFTCTRL */ 996 #define EBI_TFTCTRL_ALIASBANKEN_ENABLE (_EBI_TFTCTRL_ALIASBANKEN_ENABLE << 19) /**< Shifted mode ENABLE for EBI_TFTCTRL */ 997 #define _EBI_TFTCTRL_BANKSEL_SHIFT 20 /**< Shift value for EBI_BANKSEL */ 998 #define _EBI_TFTCTRL_BANKSEL_MASK 0x300000UL /**< Bit mask for EBI_BANKSEL */ 999 #define _EBI_TFTCTRL_BANKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ 1000 #define _EBI_TFTCTRL_BANKSEL_BANK0 0x00000000UL /**< Mode BANK0 for EBI_TFTCTRL */ 1001 #define _EBI_TFTCTRL_BANKSEL_BANK1 0x00000001UL /**< Mode BANK1 for EBI_TFTCTRL */ 1002 #define _EBI_TFTCTRL_BANKSEL_BANK2 0x00000002UL /**< Mode BANK2 for EBI_TFTCTRL */ 1003 #define _EBI_TFTCTRL_BANKSEL_BANK3 0x00000003UL /**< Mode BANK3 for EBI_TFTCTRL */ 1004 #define EBI_TFTCTRL_BANKSEL_DEFAULT (_EBI_TFTCTRL_BANKSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ 1005 #define EBI_TFTCTRL_BANKSEL_BANK0 (_EBI_TFTCTRL_BANKSEL_BANK0 << 20) /**< Shifted mode BANK0 for EBI_TFTCTRL */ 1006 #define EBI_TFTCTRL_BANKSEL_BANK1 (_EBI_TFTCTRL_BANKSEL_BANK1 << 20) /**< Shifted mode BANK1 for EBI_TFTCTRL */ 1007 #define EBI_TFTCTRL_BANKSEL_BANK2 (_EBI_TFTCTRL_BANKSEL_BANK2 << 20) /**< Shifted mode BANK2 for EBI_TFTCTRL */ 1008 #define EBI_TFTCTRL_BANKSEL_BANK3 (_EBI_TFTCTRL_BANKSEL_BANK3 << 20) /**< Shifted mode BANK3 for EBI_TFTCTRL */ 1009 #define _EBI_TFTCTRL_ALIASBANK_SHIFT 22 /**< Shift value for EBI_ALIASBANK */ 1010 #define _EBI_TFTCTRL_ALIASBANK_MASK 0xC00000UL /**< Bit mask for EBI_ALIASBANK */ 1011 #define _EBI_TFTCTRL_ALIASBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCTRL */ 1012 #define _EBI_TFTCTRL_ALIASBANK_ALIASBANK0 0x00000000UL /**< Mode ALIASBANK0 for EBI_TFTCTRL */ 1013 #define _EBI_TFTCTRL_ALIASBANK_ALIASBANK1 0x00000001UL /**< Mode ALIASBANK1 for EBI_TFTCTRL */ 1014 #define _EBI_TFTCTRL_ALIASBANK_ALIASBANK2 0x00000002UL /**< Mode ALIASBANK2 for EBI_TFTCTRL */ 1015 #define _EBI_TFTCTRL_ALIASBANK_ALIASBANK3 0x00000003UL /**< Mode ALIASBANK3 for EBI_TFTCTRL */ 1016 #define EBI_TFTCTRL_ALIASBANK_DEFAULT (_EBI_TFTCTRL_ALIASBANK_DEFAULT << 22) /**< Shifted mode DEFAULT for EBI_TFTCTRL */ 1017 #define EBI_TFTCTRL_ALIASBANK_ALIASBANK0 (_EBI_TFTCTRL_ALIASBANK_ALIASBANK0 << 22) /**< Shifted mode ALIASBANK0 for EBI_TFTCTRL */ 1018 #define EBI_TFTCTRL_ALIASBANK_ALIASBANK1 (_EBI_TFTCTRL_ALIASBANK_ALIASBANK1 << 22) /**< Shifted mode ALIASBANK1 for EBI_TFTCTRL */ 1019 #define EBI_TFTCTRL_ALIASBANK_ALIASBANK2 (_EBI_TFTCTRL_ALIASBANK_ALIASBANK2 << 22) /**< Shifted mode ALIASBANK2 for EBI_TFTCTRL */ 1020 #define EBI_TFTCTRL_ALIASBANK_ALIASBANK3 (_EBI_TFTCTRL_ALIASBANK_ALIASBANK3 << 22) /**< Shifted mode ALIASBANK3 for EBI_TFTCTRL */ 1021 1022 /* Bit fields for EBI TFTSTATUS */ 1023 #define _EBI_TFTSTATUS_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTSTATUS */ 1024 #define _EBI_TFTSTATUS_MASK 0x7FFF07FFUL /**< Mask for EBI_TFTSTATUS */ 1025 #define _EBI_TFTSTATUS_HCNT_SHIFT 0 /**< Shift value for EBI_HCNT */ 1026 #define _EBI_TFTSTATUS_HCNT_MASK 0x7FFUL /**< Bit mask for EBI_HCNT */ 1027 #define _EBI_TFTSTATUS_HCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSTATUS */ 1028 #define EBI_TFTSTATUS_HCNT_DEFAULT (_EBI_TFTSTATUS_HCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSTATUS */ 1029 #define _EBI_TFTSTATUS_VCNT_SHIFT 16 /**< Shift value for EBI_VCNT */ 1030 #define _EBI_TFTSTATUS_VCNT_MASK 0x7FFF0000UL /**< Bit mask for EBI_VCNT */ 1031 #define _EBI_TFTSTATUS_VCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSTATUS */ 1032 #define EBI_TFTSTATUS_VCNT_DEFAULT (_EBI_TFTSTATUS_VCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTSTATUS */ 1033 1034 /* Bit fields for EBI TFTCOLORFORMAT */ 1035 #define _EBI_TFTCOLORFORMAT_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTCOLORFORMAT */ 1036 #define _EBI_TFTCOLORFORMAT_MASK 0x00000307UL /**< Mask for EBI_TFTCOLORFORMAT */ 1037 #define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_SHIFT 0 /**< Shift value for EBI_PIXEL0FORMAT */ 1038 #define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_MASK 0x7UL /**< Bit mask for EBI_PIXEL0FORMAT */ 1039 #define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCOLORFORMAT */ 1040 #define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0555 0x00000000UL /**< Mode ARGB0555 for EBI_TFTCOLORFORMAT */ 1041 #define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0565 0x00000001UL /**< Mode ARGB0565 for EBI_TFTCOLORFORMAT */ 1042 #define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0666 0x00000002UL /**< Mode ARGB0666 for EBI_TFTCOLORFORMAT */ 1043 #define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0888 0x00000003UL /**< Mode ARGB0888 for EBI_TFTCOLORFORMAT */ 1044 #define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB5555 0x00000004UL /**< Mode ARGB5555 for EBI_TFTCOLORFORMAT */ 1045 #define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB6565 0x00000005UL /**< Mode ARGB6565 for EBI_TFTCOLORFORMAT */ 1046 #define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB6666 0x00000006UL /**< Mode ARGB6666 for EBI_TFTCOLORFORMAT */ 1047 #define _EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB8888 0x00000007UL /**< Mode ARGB8888 for EBI_TFTCOLORFORMAT */ 1048 #define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_DEFAULT (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTCOLORFORMAT */ 1049 #define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0555 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0555 << 0) /**< Shifted mode ARGB0555 for EBI_TFTCOLORFORMAT */ 1050 #define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0565 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0565 << 0) /**< Shifted mode ARGB0565 for EBI_TFTCOLORFORMAT */ 1051 #define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0666 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0666 << 0) /**< Shifted mode ARGB0666 for EBI_TFTCOLORFORMAT */ 1052 #define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0888 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB0888 << 0) /**< Shifted mode ARGB0888 for EBI_TFTCOLORFORMAT */ 1053 #define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB5555 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB5555 << 0) /**< Shifted mode ARGB5555 for EBI_TFTCOLORFORMAT */ 1054 #define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB6565 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB6565 << 0) /**< Shifted mode ARGB6565 for EBI_TFTCOLORFORMAT */ 1055 #define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB6666 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB6666 << 0) /**< Shifted mode ARGB6666 for EBI_TFTCOLORFORMAT */ 1056 #define EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB8888 (_EBI_TFTCOLORFORMAT_PIXEL0FORMAT_ARGB8888 << 0) /**< Shifted mode ARGB8888 for EBI_TFTCOLORFORMAT */ 1057 #define _EBI_TFTCOLORFORMAT_PIXEL1FORMAT_SHIFT 8 /**< Shift value for EBI_PIXEL1FORMAT */ 1058 #define _EBI_TFTCOLORFORMAT_PIXEL1FORMAT_MASK 0x300UL /**< Bit mask for EBI_PIXEL1FORMAT */ 1059 #define _EBI_TFTCOLORFORMAT_PIXEL1FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTCOLORFORMAT */ 1060 #define _EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB555 0x00000000UL /**< Mode RGB555 for EBI_TFTCOLORFORMAT */ 1061 #define _EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB565 0x00000001UL /**< Mode RGB565 for EBI_TFTCOLORFORMAT */ 1062 #define _EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB666 0x00000002UL /**< Mode RGB666 for EBI_TFTCOLORFORMAT */ 1063 #define _EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB888 0x00000003UL /**< Mode RGB888 for EBI_TFTCOLORFORMAT */ 1064 #define EBI_TFTCOLORFORMAT_PIXEL1FORMAT_DEFAULT (_EBI_TFTCOLORFORMAT_PIXEL1FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTCOLORFORMAT */ 1065 #define EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB555 (_EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB555 << 8) /**< Shifted mode RGB555 for EBI_TFTCOLORFORMAT */ 1066 #define EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB565 (_EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB565 << 8) /**< Shifted mode RGB565 for EBI_TFTCOLORFORMAT */ 1067 #define EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB666 (_EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB666 << 8) /**< Shifted mode RGB666 for EBI_TFTCOLORFORMAT */ 1068 #define EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB888 (_EBI_TFTCOLORFORMAT_PIXEL1FORMAT_RGB888 << 8) /**< Shifted mode RGB888 for EBI_TFTCOLORFORMAT */ 1069 1070 /* Bit fields for EBI TFTFRAMEBASE */ 1071 #define _EBI_TFTFRAMEBASE_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTFRAMEBASE */ 1072 #define _EBI_TFTFRAMEBASE_MASK 0x0FFFFFFFUL /**< Mask for EBI_TFTFRAMEBASE */ 1073 #define _EBI_TFTFRAMEBASE_FRAMEBASE_SHIFT 0 /**< Shift value for EBI_FRAMEBASE */ 1074 #define _EBI_TFTFRAMEBASE_FRAMEBASE_MASK 0xFFFFFFFUL /**< Bit mask for EBI_FRAMEBASE */ 1075 #define _EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTFRAMEBASE */ 1076 #define EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT (_EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTFRAMEBASE */ 1077 1078 /* Bit fields for EBI TFTSTRIDE */ 1079 #define _EBI_TFTSTRIDE_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTSTRIDE */ 1080 #define _EBI_TFTSTRIDE_MASK 0x00000FFFUL /**< Mask for EBI_TFTSTRIDE */ 1081 #define _EBI_TFTSTRIDE_HSTRIDE_SHIFT 0 /**< Shift value for EBI_HSTRIDE */ 1082 #define _EBI_TFTSTRIDE_HSTRIDE_MASK 0xFFFUL /**< Bit mask for EBI_HSTRIDE */ 1083 #define _EBI_TFTSTRIDE_HSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSTRIDE */ 1084 #define EBI_TFTSTRIDE_HSTRIDE_DEFAULT (_EBI_TFTSTRIDE_HSTRIDE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSTRIDE */ 1085 1086 /* Bit fields for EBI TFTSIZE */ 1087 #define _EBI_TFTSIZE_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTSIZE */ 1088 #define _EBI_TFTSIZE_MASK 0x03FF03FFUL /**< Mask for EBI_TFTSIZE */ 1089 #define _EBI_TFTSIZE_HSZ_SHIFT 0 /**< Shift value for EBI_HSZ */ 1090 #define _EBI_TFTSIZE_HSZ_MASK 0x3FFUL /**< Bit mask for EBI_HSZ */ 1091 #define _EBI_TFTSIZE_HSZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSIZE */ 1092 #define EBI_TFTSIZE_HSZ_DEFAULT (_EBI_TFTSIZE_HSZ_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTSIZE */ 1093 #define _EBI_TFTSIZE_VSZ_SHIFT 16 /**< Shift value for EBI_VSZ */ 1094 #define _EBI_TFTSIZE_VSZ_MASK 0x3FF0000UL /**< Bit mask for EBI_VSZ */ 1095 #define _EBI_TFTSIZE_VSZ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTSIZE */ 1096 #define EBI_TFTSIZE_VSZ_DEFAULT (_EBI_TFTSIZE_VSZ_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_TFTSIZE */ 1097 1098 /* Bit fields for EBI TFTHPORCH */ 1099 #define _EBI_TFTHPORCH_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTHPORCH */ 1100 #define _EBI_TFTHPORCH_MASK 0x33FCFF7FUL /**< Mask for EBI_TFTHPORCH */ 1101 #define _EBI_TFTHPORCH_HSYNC_SHIFT 0 /**< Shift value for EBI_HSYNC */ 1102 #define _EBI_TFTHPORCH_HSYNC_MASK 0x7FUL /**< Bit mask for EBI_HSYNC */ 1103 #define _EBI_TFTHPORCH_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */ 1104 #define EBI_TFTHPORCH_HSYNC_DEFAULT (_EBI_TFTHPORCH_HSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */ 1105 #define _EBI_TFTHPORCH_HFPORCH_SHIFT 8 /**< Shift value for EBI_HFPORCH */ 1106 #define _EBI_TFTHPORCH_HFPORCH_MASK 0xFF00UL /**< Bit mask for EBI_HFPORCH */ 1107 #define _EBI_TFTHPORCH_HFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */ 1108 #define EBI_TFTHPORCH_HFPORCH_DEFAULT (_EBI_TFTHPORCH_HFPORCH_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */ 1109 #define _EBI_TFTHPORCH_HBPORCH_SHIFT 18 /**< Shift value for EBI_HBPORCH */ 1110 #define _EBI_TFTHPORCH_HBPORCH_MASK 0x3FC0000UL /**< Bit mask for EBI_HBPORCH */ 1111 #define _EBI_TFTHPORCH_HBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */ 1112 #define EBI_TFTHPORCH_HBPORCH_DEFAULT (_EBI_TFTHPORCH_HBPORCH_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */ 1113 #define _EBI_TFTHPORCH_HSYNCSTART_SHIFT 28 /**< Shift value for EBI_HSYNCSTART */ 1114 #define _EBI_TFTHPORCH_HSYNCSTART_MASK 0x30000000UL /**< Bit mask for EBI_HSYNCSTART */ 1115 #define _EBI_TFTHPORCH_HSYNCSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTHPORCH */ 1116 #define EBI_TFTHPORCH_HSYNCSTART_DEFAULT (_EBI_TFTHPORCH_HSYNCSTART_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_TFTHPORCH */ 1117 1118 /* Bit fields for EBI TFTVPORCH */ 1119 #define _EBI_TFTVPORCH_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTVPORCH */ 1120 #define _EBI_TFTVPORCH_MASK 0xFFFFFF7FUL /**< Mask for EBI_TFTVPORCH */ 1121 #define _EBI_TFTVPORCH_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */ 1122 #define _EBI_TFTVPORCH_VSYNC_MASK 0x7FUL /**< Bit mask for EBI_VSYNC */ 1123 #define _EBI_TFTVPORCH_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTVPORCH */ 1124 #define EBI_TFTVPORCH_VSYNC_DEFAULT (_EBI_TFTVPORCH_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */ 1125 #define _EBI_TFTVPORCH_VFPORCH_SHIFT 8 /**< Shift value for EBI_VFPORCH */ 1126 #define _EBI_TFTVPORCH_VFPORCH_MASK 0xFFF00UL /**< Bit mask for EBI_VFPORCH */ 1127 #define _EBI_TFTVPORCH_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTVPORCH */ 1128 #define EBI_TFTVPORCH_VFPORCH_DEFAULT (_EBI_TFTVPORCH_VFPORCH_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */ 1129 #define _EBI_TFTVPORCH_VBPORCH_SHIFT 20 /**< Shift value for EBI_VBPORCH */ 1130 #define _EBI_TFTVPORCH_VBPORCH_MASK 0xFFF00000UL /**< Bit mask for EBI_VBPORCH */ 1131 #define _EBI_TFTVPORCH_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTVPORCH */ 1132 #define EBI_TFTVPORCH_VBPORCH_DEFAULT (_EBI_TFTVPORCH_VBPORCH_DEFAULT << 20) /**< Shifted mode DEFAULT for EBI_TFTVPORCH */ 1133 1134 /* Bit fields for EBI TFTTIMING */ 1135 #define _EBI_TFTTIMING_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTTIMING */ 1136 #define _EBI_TFTTIMING_MASK 0x77FFFFFFUL /**< Mask for EBI_TFTTIMING */ 1137 #define _EBI_TFTTIMING_DCLKPERIOD_SHIFT 0 /**< Shift value for EBI_DCLKPERIOD */ 1138 #define _EBI_TFTTIMING_DCLKPERIOD_MASK 0xFFFUL /**< Bit mask for EBI_DCLKPERIOD */ 1139 #define _EBI_TFTTIMING_DCLKPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */ 1140 #define EBI_TFTTIMING_DCLKPERIOD_DEFAULT (_EBI_TFTTIMING_DCLKPERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTTIMING */ 1141 #define _EBI_TFTTIMING_TFTSTART_SHIFT 12 /**< Shift value for EBI_TFTSTART */ 1142 #define _EBI_TFTTIMING_TFTSTART_MASK 0xFFF000UL /**< Bit mask for EBI_TFTSTART */ 1143 #define _EBI_TFTTIMING_TFTSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */ 1144 #define EBI_TFTTIMING_TFTSTART_DEFAULT (_EBI_TFTTIMING_TFTSTART_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_TFTTIMING */ 1145 #define _EBI_TFTTIMING_TFTSETUP_SHIFT 24 /**< Shift value for EBI_TFTSETUP */ 1146 #define _EBI_TFTTIMING_TFTSETUP_MASK 0x7000000UL /**< Bit mask for EBI_TFTSETUP */ 1147 #define _EBI_TFTTIMING_TFTSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */ 1148 #define EBI_TFTTIMING_TFTSETUP_DEFAULT (_EBI_TFTTIMING_TFTSETUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_TFTTIMING */ 1149 #define _EBI_TFTTIMING_TFTHOLD_SHIFT 28 /**< Shift value for EBI_TFTHOLD */ 1150 #define _EBI_TFTTIMING_TFTHOLD_MASK 0x70000000UL /**< Bit mask for EBI_TFTHOLD */ 1151 #define _EBI_TFTTIMING_TFTHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTTIMING */ 1152 #define EBI_TFTTIMING_TFTHOLD_DEFAULT (_EBI_TFTTIMING_TFTHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for EBI_TFTTIMING */ 1153 1154 /* Bit fields for EBI TFTPOLARITY */ 1155 #define _EBI_TFTPOLARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPOLARITY */ 1156 #define _EBI_TFTPOLARITY_MASK 0x0000001FUL /**< Mask for EBI_TFTPOLARITY */ 1157 #define EBI_TFTPOLARITY_CSPOL (0x1UL << 0) /**< TFT Chip Select Polarity */ 1158 #define _EBI_TFTPOLARITY_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */ 1159 #define _EBI_TFTPOLARITY_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */ 1160 #define _EBI_TFTPOLARITY_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */ 1161 #define _EBI_TFTPOLARITY_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */ 1162 #define _EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */ 1163 #define EBI_TFTPOLARITY_CSPOL_DEFAULT (_EBI_TFTPOLARITY_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */ 1164 #define EBI_TFTPOLARITY_CSPOL_ACTIVELOW (_EBI_TFTPOLARITY_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */ 1165 #define EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */ 1166 #define EBI_TFTPOLARITY_DCLKPOL (0x1UL << 1) /**< TFT DCLK Polarity */ 1167 #define _EBI_TFTPOLARITY_DCLKPOL_SHIFT 1 /**< Shift value for EBI_DCLKPOL */ 1168 #define _EBI_TFTPOLARITY_DCLKPOL_MASK 0x2UL /**< Bit mask for EBI_DCLKPOL */ 1169 #define _EBI_TFTPOLARITY_DCLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */ 1170 #define _EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING 0x00000000UL /**< Mode ACTIVEFALLING for EBI_TFTPOLARITY */ 1171 #define _EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING 0x00000001UL /**< Mode ACTIVERISING for EBI_TFTPOLARITY */ 1172 #define EBI_TFTPOLARITY_DCLKPOL_DEFAULT (_EBI_TFTPOLARITY_DCLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */ 1173 #define EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING (_EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING << 1) /**< Shifted mode ACTIVEFALLING for EBI_TFTPOLARITY */ 1174 #define EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING (_EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING << 1) /**< Shifted mode ACTIVERISING for EBI_TFTPOLARITY */ 1175 #define EBI_TFTPOLARITY_DATAENPOL (0x1UL << 2) /**< TFT DATAEN Polarity */ 1176 #define _EBI_TFTPOLARITY_DATAENPOL_SHIFT 2 /**< Shift value for EBI_DATAENPOL */ 1177 #define _EBI_TFTPOLARITY_DATAENPOL_MASK 0x4UL /**< Bit mask for EBI_DATAENPOL */ 1178 #define _EBI_TFTPOLARITY_DATAENPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */ 1179 #define _EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */ 1180 #define _EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */ 1181 #define EBI_TFTPOLARITY_DATAENPOL_DEFAULT (_EBI_TFTPOLARITY_DATAENPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */ 1182 #define EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW (_EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */ 1183 #define EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */ 1184 #define EBI_TFTPOLARITY_HSYNCPOL (0x1UL << 3) /**< Address Latch Polarity */ 1185 #define _EBI_TFTPOLARITY_HSYNCPOL_SHIFT 3 /**< Shift value for EBI_HSYNCPOL */ 1186 #define _EBI_TFTPOLARITY_HSYNCPOL_MASK 0x8UL /**< Bit mask for EBI_HSYNCPOL */ 1187 #define _EBI_TFTPOLARITY_HSYNCPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */ 1188 #define _EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */ 1189 #define _EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */ 1190 #define EBI_TFTPOLARITY_HSYNCPOL_DEFAULT (_EBI_TFTPOLARITY_HSYNCPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */ 1191 #define EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW (_EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */ 1192 #define EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */ 1193 #define EBI_TFTPOLARITY_VSYNCPOL (0x1UL << 4) /**< VSYNC Polarity */ 1194 #define _EBI_TFTPOLARITY_VSYNCPOL_SHIFT 4 /**< Shift value for EBI_VSYNCPOL */ 1195 #define _EBI_TFTPOLARITY_VSYNCPOL_MASK 0x10UL /**< Bit mask for EBI_VSYNCPOL */ 1196 #define _EBI_TFTPOLARITY_VSYNCPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPOLARITY */ 1197 #define _EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_TFTPOLARITY */ 1198 #define _EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_TFTPOLARITY */ 1199 #define EBI_TFTPOLARITY_VSYNCPOL_DEFAULT (_EBI_TFTPOLARITY_VSYNCPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_TFTPOLARITY */ 1200 #define EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW (_EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_TFTPOLARITY */ 1201 #define EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_TFTPOLARITY */ 1202 1203 /* Bit fields for EBI TFTDD */ 1204 #define _EBI_TFTDD_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTDD */ 1205 #define _EBI_TFTDD_MASK 0x00FFFFFFUL /**< Mask for EBI_TFTDD */ 1206 #define _EBI_TFTDD_DATA_SHIFT 0 /**< Shift value for EBI_DATA */ 1207 #define _EBI_TFTDD_DATA_MASK 0xFFFFFFUL /**< Bit mask for EBI_DATA */ 1208 #define _EBI_TFTDD_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTDD */ 1209 #define EBI_TFTDD_DATA_DEFAULT (_EBI_TFTDD_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTDD */ 1210 1211 /* Bit fields for EBI TFTALPHA */ 1212 #define _EBI_TFTALPHA_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTALPHA */ 1213 #define _EBI_TFTALPHA_MASK 0x000001FFUL /**< Mask for EBI_TFTALPHA */ 1214 #define _EBI_TFTALPHA_ALPHA_SHIFT 0 /**< Shift value for EBI_ALPHA */ 1215 #define _EBI_TFTALPHA_ALPHA_MASK 0x1FFUL /**< Bit mask for EBI_ALPHA */ 1216 #define _EBI_TFTALPHA_ALPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTALPHA */ 1217 #define EBI_TFTALPHA_ALPHA_DEFAULT (_EBI_TFTALPHA_ALPHA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTALPHA */ 1218 1219 /* Bit fields for EBI TFTPIXEL0 */ 1220 #define _EBI_TFTPIXEL0_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPIXEL0 */ 1221 #define _EBI_TFTPIXEL0_MASK 0x00FFFFFFUL /**< Mask for EBI_TFTPIXEL0 */ 1222 #define _EBI_TFTPIXEL0_DATA_SHIFT 0 /**< Shift value for EBI_DATA */ 1223 #define _EBI_TFTPIXEL0_DATA_MASK 0xFFFFFFUL /**< Bit mask for EBI_DATA */ 1224 #define _EBI_TFTPIXEL0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPIXEL0 */ 1225 #define EBI_TFTPIXEL0_DATA_DEFAULT (_EBI_TFTPIXEL0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL0 */ 1226 1227 /* Bit fields for EBI TFTPIXEL1 */ 1228 #define _EBI_TFTPIXEL1_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPIXEL1 */ 1229 #define _EBI_TFTPIXEL1_MASK 0x00FFFFFFUL /**< Mask for EBI_TFTPIXEL1 */ 1230 #define _EBI_TFTPIXEL1_DATA_SHIFT 0 /**< Shift value for EBI_DATA */ 1231 #define _EBI_TFTPIXEL1_DATA_MASK 0xFFFFFFUL /**< Bit mask for EBI_DATA */ 1232 #define _EBI_TFTPIXEL1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPIXEL1 */ 1233 #define EBI_TFTPIXEL1_DATA_DEFAULT (_EBI_TFTPIXEL1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL1 */ 1234 1235 /* Bit fields for EBI TFTPIXEL */ 1236 #define _EBI_TFTPIXEL_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTPIXEL */ 1237 #define _EBI_TFTPIXEL_MASK 0x00FFFFFFUL /**< Mask for EBI_TFTPIXEL */ 1238 #define _EBI_TFTPIXEL_DATA_SHIFT 0 /**< Shift value for EBI_DATA */ 1239 #define _EBI_TFTPIXEL_DATA_MASK 0xFFFFFFUL /**< Bit mask for EBI_DATA */ 1240 #define _EBI_TFTPIXEL_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTPIXEL */ 1241 #define EBI_TFTPIXEL_DATA_DEFAULT (_EBI_TFTPIXEL_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTPIXEL */ 1242 1243 /* Bit fields for EBI TFTMASK */ 1244 #define _EBI_TFTMASK_RESETVALUE 0x00000000UL /**< Default value for EBI_TFTMASK */ 1245 #define _EBI_TFTMASK_MASK 0x00FFFFFFUL /**< Mask for EBI_TFTMASK */ 1246 #define _EBI_TFTMASK_TFTMASK_SHIFT 0 /**< Shift value for EBI_TFTMASK */ 1247 #define _EBI_TFTMASK_TFTMASK_MASK 0xFFFFFFUL /**< Bit mask for EBI_TFTMASK */ 1248 #define _EBI_TFTMASK_TFTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_TFTMASK */ 1249 #define EBI_TFTMASK_TFTMASK_DEFAULT (_EBI_TFTMASK_TFTMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_TFTMASK */ 1250 1251 /* Bit fields for EBI IF */ 1252 #define _EBI_IF_RESETVALUE 0x00000000UL /**< Default value for EBI_IF */ 1253 #define _EBI_IF_MASK 0x000003FFUL /**< Mask for EBI_IF */ 1254 #define EBI_IF_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Flag */ 1255 #define _EBI_IF_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */ 1256 #define _EBI_IF_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */ 1257 #define _EBI_IF_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ 1258 #define EBI_IF_VSYNC_DEFAULT (_EBI_IF_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IF */ 1259 #define EBI_IF_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Flag */ 1260 #define _EBI_IF_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */ 1261 #define _EBI_IF_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */ 1262 #define _EBI_IF_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ 1263 #define EBI_IF_HSYNC_DEFAULT (_EBI_IF_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IF */ 1264 #define EBI_IF_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Flag */ 1265 #define _EBI_IF_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */ 1266 #define _EBI_IF_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */ 1267 #define _EBI_IF_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ 1268 #define EBI_IF_VBPORCH_DEFAULT (_EBI_IF_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IF */ 1269 #define EBI_IF_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Flag */ 1270 #define _EBI_IF_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */ 1271 #define _EBI_IF_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */ 1272 #define _EBI_IF_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ 1273 #define EBI_IF_VFPORCH_DEFAULT (_EBI_IF_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IF */ 1274 #define EBI_IF_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Flag */ 1275 #define _EBI_IF_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */ 1276 #define _EBI_IF_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */ 1277 #define _EBI_IF_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ 1278 #define EBI_IF_DDEMPTY_DEFAULT (_EBI_IF_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IF */ 1279 #define EBI_IF_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Flag */ 1280 #define _EBI_IF_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */ 1281 #define _EBI_IF_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */ 1282 #define _EBI_IF_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ 1283 #define EBI_IF_DDJIT_DEFAULT (_EBI_IF_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IF */ 1284 #define EBI_IF_TFTPIXEL0EMPTY (0x1UL << 6) /**< EBI_TFTPIXEL0 is Empty Interrupt Flag */ 1285 #define _EBI_IF_TFTPIXEL0EMPTY_SHIFT 6 /**< Shift value for EBI_TFTPIXEL0EMPTY */ 1286 #define _EBI_IF_TFTPIXEL0EMPTY_MASK 0x40UL /**< Bit mask for EBI_TFTPIXEL0EMPTY */ 1287 #define _EBI_IF_TFTPIXEL0EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ 1288 #define EBI_IF_TFTPIXEL0EMPTY_DEFAULT (_EBI_IF_TFTPIXEL0EMPTY_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_IF */ 1289 #define EBI_IF_TFTPIXEL1EMPTY (0x1UL << 7) /**< EBI_TFTPIXEL1 is Empty Interrupt Flag */ 1290 #define _EBI_IF_TFTPIXEL1EMPTY_SHIFT 7 /**< Shift value for EBI_TFTPIXEL1EMPTY */ 1291 #define _EBI_IF_TFTPIXEL1EMPTY_MASK 0x80UL /**< Bit mask for EBI_TFTPIXEL1EMPTY */ 1292 #define _EBI_IF_TFTPIXEL1EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ 1293 #define EBI_IF_TFTPIXEL1EMPTY_DEFAULT (_EBI_IF_TFTPIXEL1EMPTY_DEFAULT << 7) /**< Shifted mode DEFAULT for EBI_IF */ 1294 #define EBI_IF_TFTPIXELFULL (0x1UL << 8) /**< EBI_TFTPIXEL is Full Interrupt Flag */ 1295 #define _EBI_IF_TFTPIXELFULL_SHIFT 8 /**< Shift value for EBI_TFTPIXELFULL */ 1296 #define _EBI_IF_TFTPIXELFULL_MASK 0x100UL /**< Bit mask for EBI_TFTPIXELFULL */ 1297 #define _EBI_IF_TFTPIXELFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ 1298 #define EBI_IF_TFTPIXELFULL_DEFAULT (_EBI_IF_TFTPIXELFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_IF */ 1299 #define EBI_IF_TFTPIXELOF (0x1UL << 9) /**< EBI_TFTPIXEL Register Overflow Interrupt Flag */ 1300 #define _EBI_IF_TFTPIXELOF_SHIFT 9 /**< Shift value for EBI_TFTPIXELOF */ 1301 #define _EBI_IF_TFTPIXELOF_MASK 0x200UL /**< Bit mask for EBI_TFTPIXELOF */ 1302 #define _EBI_IF_TFTPIXELOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IF */ 1303 #define EBI_IF_TFTPIXELOF_DEFAULT (_EBI_IF_TFTPIXELOF_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_IF */ 1304 1305 /* Bit fields for EBI IFS */ 1306 #define _EBI_IFS_RESETVALUE 0x00000000UL /**< Default value for EBI_IFS */ 1307 #define _EBI_IFS_MASK 0x000003FFUL /**< Mask for EBI_IFS */ 1308 #define EBI_IFS_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Flag Set */ 1309 #define _EBI_IFS_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */ 1310 #define _EBI_IFS_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */ 1311 #define _EBI_IFS_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ 1312 #define EBI_IFS_VSYNC_DEFAULT (_EBI_IFS_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IFS */ 1313 #define EBI_IFS_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Flag Set */ 1314 #define _EBI_IFS_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */ 1315 #define _EBI_IFS_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */ 1316 #define _EBI_IFS_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ 1317 #define EBI_IFS_HSYNC_DEFAULT (_EBI_IFS_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IFS */ 1318 #define EBI_IFS_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Flag Set */ 1319 #define _EBI_IFS_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */ 1320 #define _EBI_IFS_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */ 1321 #define _EBI_IFS_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ 1322 #define EBI_IFS_VBPORCH_DEFAULT (_EBI_IFS_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IFS */ 1323 #define EBI_IFS_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Flag Set */ 1324 #define _EBI_IFS_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */ 1325 #define _EBI_IFS_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */ 1326 #define _EBI_IFS_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ 1327 #define EBI_IFS_VFPORCH_DEFAULT (_EBI_IFS_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IFS */ 1328 #define EBI_IFS_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Flag Set */ 1329 #define _EBI_IFS_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */ 1330 #define _EBI_IFS_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */ 1331 #define _EBI_IFS_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ 1332 #define EBI_IFS_DDEMPTY_DEFAULT (_EBI_IFS_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IFS */ 1333 #define EBI_IFS_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Flag Set */ 1334 #define _EBI_IFS_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */ 1335 #define _EBI_IFS_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */ 1336 #define _EBI_IFS_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ 1337 #define EBI_IFS_DDJIT_DEFAULT (_EBI_IFS_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IFS */ 1338 #define EBI_IFS_TFTPIXEL0EMPTY (0x1UL << 6) /**< EBI_TFTPIXEL0 Empty Interrupt Flag Set */ 1339 #define _EBI_IFS_TFTPIXEL0EMPTY_SHIFT 6 /**< Shift value for EBI_TFTPIXEL0EMPTY */ 1340 #define _EBI_IFS_TFTPIXEL0EMPTY_MASK 0x40UL /**< Bit mask for EBI_TFTPIXEL0EMPTY */ 1341 #define _EBI_IFS_TFTPIXEL0EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ 1342 #define EBI_IFS_TFTPIXEL0EMPTY_DEFAULT (_EBI_IFS_TFTPIXEL0EMPTY_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_IFS */ 1343 #define EBI_IFS_TFTPIXEL1EMPTY (0x1UL << 7) /**< EBI_TFTPIXEL1 Empty Interrupt Flag Set */ 1344 #define _EBI_IFS_TFTPIXEL1EMPTY_SHIFT 7 /**< Shift value for EBI_TFTPIXEL1EMPTY */ 1345 #define _EBI_IFS_TFTPIXEL1EMPTY_MASK 0x80UL /**< Bit mask for EBI_TFTPIXEL1EMPTY */ 1346 #define _EBI_IFS_TFTPIXEL1EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ 1347 #define EBI_IFS_TFTPIXEL1EMPTY_DEFAULT (_EBI_IFS_TFTPIXEL1EMPTY_DEFAULT << 7) /**< Shifted mode DEFAULT for EBI_IFS */ 1348 #define EBI_IFS_TFTPIXELFULL (0x1UL << 8) /**< EBI_TFTPIXEL Full Interrupt Flag Set */ 1349 #define _EBI_IFS_TFTPIXELFULL_SHIFT 8 /**< Shift value for EBI_TFTPIXELFULL */ 1350 #define _EBI_IFS_TFTPIXELFULL_MASK 0x100UL /**< Bit mask for EBI_TFTPIXELFULL */ 1351 #define _EBI_IFS_TFTPIXELFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ 1352 #define EBI_IFS_TFTPIXELFULL_DEFAULT (_EBI_IFS_TFTPIXELFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_IFS */ 1353 #define EBI_IFS_TFTPIXELOF (0x1UL << 9) /**< EBI_TFTPIXEL Overflow Interrupt Flag Set */ 1354 #define _EBI_IFS_TFTPIXELOF_SHIFT 9 /**< Shift value for EBI_TFTPIXELOF */ 1355 #define _EBI_IFS_TFTPIXELOF_MASK 0x200UL /**< Bit mask for EBI_TFTPIXELOF */ 1356 #define _EBI_IFS_TFTPIXELOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFS */ 1357 #define EBI_IFS_TFTPIXELOF_DEFAULT (_EBI_IFS_TFTPIXELOF_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_IFS */ 1358 1359 /* Bit fields for EBI IFC */ 1360 #define _EBI_IFC_RESETVALUE 0x00000000UL /**< Default value for EBI_IFC */ 1361 #define _EBI_IFC_MASK 0x000003FFUL /**< Mask for EBI_IFC */ 1362 #define EBI_IFC_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Flag Clear */ 1363 #define _EBI_IFC_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */ 1364 #define _EBI_IFC_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */ 1365 #define _EBI_IFC_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ 1366 #define EBI_IFC_VSYNC_DEFAULT (_EBI_IFC_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IFC */ 1367 #define EBI_IFC_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Flag Clear */ 1368 #define _EBI_IFC_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */ 1369 #define _EBI_IFC_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */ 1370 #define _EBI_IFC_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ 1371 #define EBI_IFC_HSYNC_DEFAULT (_EBI_IFC_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IFC */ 1372 #define EBI_IFC_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Flag Clear */ 1373 #define _EBI_IFC_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */ 1374 #define _EBI_IFC_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */ 1375 #define _EBI_IFC_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ 1376 #define EBI_IFC_VBPORCH_DEFAULT (_EBI_IFC_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IFC */ 1377 #define EBI_IFC_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Flag Clear */ 1378 #define _EBI_IFC_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */ 1379 #define _EBI_IFC_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */ 1380 #define _EBI_IFC_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ 1381 #define EBI_IFC_VFPORCH_DEFAULT (_EBI_IFC_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IFC */ 1382 #define EBI_IFC_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Flag Clear */ 1383 #define _EBI_IFC_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */ 1384 #define _EBI_IFC_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */ 1385 #define _EBI_IFC_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ 1386 #define EBI_IFC_DDEMPTY_DEFAULT (_EBI_IFC_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IFC */ 1387 #define EBI_IFC_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Flag Clear */ 1388 #define _EBI_IFC_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */ 1389 #define _EBI_IFC_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */ 1390 #define _EBI_IFC_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ 1391 #define EBI_IFC_DDJIT_DEFAULT (_EBI_IFC_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IFC */ 1392 #define EBI_IFC_TFTPIXEL0EMPTY (0x1UL << 6) /**< EBI_TFTPIXEL0 Empty Interrupt Flag Clear */ 1393 #define _EBI_IFC_TFTPIXEL0EMPTY_SHIFT 6 /**< Shift value for EBI_TFTPIXEL0EMPTY */ 1394 #define _EBI_IFC_TFTPIXEL0EMPTY_MASK 0x40UL /**< Bit mask for EBI_TFTPIXEL0EMPTY */ 1395 #define _EBI_IFC_TFTPIXEL0EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ 1396 #define EBI_IFC_TFTPIXEL0EMPTY_DEFAULT (_EBI_IFC_TFTPIXEL0EMPTY_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_IFC */ 1397 #define EBI_IFC_TFTPIXEL1EMPTY (0x1UL << 7) /**< EBI_TFTPIXEL1 Empty Interrupt Flag Clear */ 1398 #define _EBI_IFC_TFTPIXEL1EMPTY_SHIFT 7 /**< Shift value for EBI_TFTPIXEL1EMPTY */ 1399 #define _EBI_IFC_TFTPIXEL1EMPTY_MASK 0x80UL /**< Bit mask for EBI_TFTPIXEL1EMPTY */ 1400 #define _EBI_IFC_TFTPIXEL1EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ 1401 #define EBI_IFC_TFTPIXEL1EMPTY_DEFAULT (_EBI_IFC_TFTPIXEL1EMPTY_DEFAULT << 7) /**< Shifted mode DEFAULT for EBI_IFC */ 1402 #define EBI_IFC_TFTPIXELFULL (0x1UL << 8) /**< EBI_TFTPIXEL Full Interrupt Flag Clear */ 1403 #define _EBI_IFC_TFTPIXELFULL_SHIFT 8 /**< Shift value for EBI_TFTPIXELFULL */ 1404 #define _EBI_IFC_TFTPIXELFULL_MASK 0x100UL /**< Bit mask for EBI_TFTPIXELFULL */ 1405 #define _EBI_IFC_TFTPIXELFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ 1406 #define EBI_IFC_TFTPIXELFULL_DEFAULT (_EBI_IFC_TFTPIXELFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_IFC */ 1407 #define EBI_IFC_TFTPIXELOF (0x1UL << 9) /**< EBI_TFTPIXEL Overflow Interrupt Flag Clear */ 1408 #define _EBI_IFC_TFTPIXELOF_SHIFT 9 /**< Shift value for EBI_TFTPIXELOF */ 1409 #define _EBI_IFC_TFTPIXELOF_MASK 0x200UL /**< Bit mask for EBI_TFTPIXELOF */ 1410 #define _EBI_IFC_TFTPIXELOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IFC */ 1411 #define EBI_IFC_TFTPIXELOF_DEFAULT (_EBI_IFC_TFTPIXELOF_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_IFC */ 1412 1413 /* Bit fields for EBI IEN */ 1414 #define _EBI_IEN_RESETVALUE 0x00000000UL /**< Default value for EBI_IEN */ 1415 #define _EBI_IEN_MASK 0x000003FFUL /**< Mask for EBI_IEN */ 1416 #define EBI_IEN_VSYNC (0x1UL << 0) /**< Vertical Sync Interrupt Enable */ 1417 #define _EBI_IEN_VSYNC_SHIFT 0 /**< Shift value for EBI_VSYNC */ 1418 #define _EBI_IEN_VSYNC_MASK 0x1UL /**< Bit mask for EBI_VSYNC */ 1419 #define _EBI_IEN_VSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ 1420 #define EBI_IEN_VSYNC_DEFAULT (_EBI_IEN_VSYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_IEN */ 1421 #define EBI_IEN_HSYNC (0x1UL << 1) /**< Horizontal Sync Interrupt Enable */ 1422 #define _EBI_IEN_HSYNC_SHIFT 1 /**< Shift value for EBI_HSYNC */ 1423 #define _EBI_IEN_HSYNC_MASK 0x2UL /**< Bit mask for EBI_HSYNC */ 1424 #define _EBI_IEN_HSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ 1425 #define EBI_IEN_HSYNC_DEFAULT (_EBI_IEN_HSYNC_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_IEN */ 1426 #define EBI_IEN_VBPORCH (0x1UL << 2) /**< Vertical Back Porch Interrupt Enable */ 1427 #define _EBI_IEN_VBPORCH_SHIFT 2 /**< Shift value for EBI_VBPORCH */ 1428 #define _EBI_IEN_VBPORCH_MASK 0x4UL /**< Bit mask for EBI_VBPORCH */ 1429 #define _EBI_IEN_VBPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ 1430 #define EBI_IEN_VBPORCH_DEFAULT (_EBI_IEN_VBPORCH_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_IEN */ 1431 #define EBI_IEN_VFPORCH (0x1UL << 3) /**< Vertical Front Porch Interrupt Enable */ 1432 #define _EBI_IEN_VFPORCH_SHIFT 3 /**< Shift value for EBI_VFPORCH */ 1433 #define _EBI_IEN_VFPORCH_MASK 0x8UL /**< Bit mask for EBI_VFPORCH */ 1434 #define _EBI_IEN_VFPORCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ 1435 #define EBI_IEN_VFPORCH_DEFAULT (_EBI_IEN_VFPORCH_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_IEN */ 1436 #define EBI_IEN_DDEMPTY (0x1UL << 4) /**< Direct Drive Data Empty Interrupt Enable */ 1437 #define _EBI_IEN_DDEMPTY_SHIFT 4 /**< Shift value for EBI_DDEMPTY */ 1438 #define _EBI_IEN_DDEMPTY_MASK 0x10UL /**< Bit mask for EBI_DDEMPTY */ 1439 #define _EBI_IEN_DDEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ 1440 #define EBI_IEN_DDEMPTY_DEFAULT (_EBI_IEN_DDEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_IEN */ 1441 #define EBI_IEN_DDJIT (0x1UL << 5) /**< Direct Drive Jitter Interrupt Enable */ 1442 #define _EBI_IEN_DDJIT_SHIFT 5 /**< Shift value for EBI_DDJIT */ 1443 #define _EBI_IEN_DDJIT_MASK 0x20UL /**< Bit mask for EBI_DDJIT */ 1444 #define _EBI_IEN_DDJIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ 1445 #define EBI_IEN_DDJIT_DEFAULT (_EBI_IEN_DDJIT_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_IEN */ 1446 #define EBI_IEN_TFTPIXEL0EMPTY (0x1UL << 6) /**< EBI_TFTPIXEL0 Empty Interrupt Enable */ 1447 #define _EBI_IEN_TFTPIXEL0EMPTY_SHIFT 6 /**< Shift value for EBI_TFTPIXEL0EMPTY */ 1448 #define _EBI_IEN_TFTPIXEL0EMPTY_MASK 0x40UL /**< Bit mask for EBI_TFTPIXEL0EMPTY */ 1449 #define _EBI_IEN_TFTPIXEL0EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ 1450 #define EBI_IEN_TFTPIXEL0EMPTY_DEFAULT (_EBI_IEN_TFTPIXEL0EMPTY_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_IEN */ 1451 #define EBI_IEN_TFTPIXEL1EMPTY (0x1UL << 7) /**< EBI_TFTPIXEL1 Empty Interrupt Enable */ 1452 #define _EBI_IEN_TFTPIXEL1EMPTY_SHIFT 7 /**< Shift value for EBI_TFTPIXEL1EMPTY */ 1453 #define _EBI_IEN_TFTPIXEL1EMPTY_MASK 0x80UL /**< Bit mask for EBI_TFTPIXEL1EMPTY */ 1454 #define _EBI_IEN_TFTPIXEL1EMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ 1455 #define EBI_IEN_TFTPIXEL1EMPTY_DEFAULT (_EBI_IEN_TFTPIXEL1EMPTY_DEFAULT << 7) /**< Shifted mode DEFAULT for EBI_IEN */ 1456 #define EBI_IEN_TFTPIXELFULL (0x1UL << 8) /**< EBI_TFTPIXEL Full Interrupt Enable */ 1457 #define _EBI_IEN_TFTPIXELFULL_SHIFT 8 /**< Shift value for EBI_TFTPIXELFULL */ 1458 #define _EBI_IEN_TFTPIXELFULL_MASK 0x100UL /**< Bit mask for EBI_TFTPIXELFULL */ 1459 #define _EBI_IEN_TFTPIXELFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ 1460 #define EBI_IEN_TFTPIXELFULL_DEFAULT (_EBI_IEN_TFTPIXELFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_IEN */ 1461 #define EBI_IEN_TFTPIXELOF (0x1UL << 9) /**< EBI_TFTPIXEL Overflow Interrupt Enable */ 1462 #define _EBI_IEN_TFTPIXELOF_SHIFT 9 /**< Shift value for EBI_TFTPIXELOF */ 1463 #define _EBI_IEN_TFTPIXELOF_MASK 0x200UL /**< Bit mask for EBI_TFTPIXELOF */ 1464 #define _EBI_IEN_TFTPIXELOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_IEN */ 1465 #define EBI_IEN_TFTPIXELOF_DEFAULT (_EBI_IEN_TFTPIXELOF_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_IEN */ 1466 1467 /* Bit fields for EBI ROUTEPEN */ 1468 #define _EBI_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for EBI_ROUTEPEN */ 1469 #define _EBI_ROUTEPEN_MASK 0x077F10FFUL /**< Mask for EBI_ROUTEPEN */ 1470 #define EBI_ROUTEPEN_EBIPEN (0x1UL << 0) /**< EBI Pin Enable */ 1471 #define _EBI_ROUTEPEN_EBIPEN_SHIFT 0 /**< Shift value for EBI_EBIPEN */ 1472 #define _EBI_ROUTEPEN_EBIPEN_MASK 0x1UL /**< Bit mask for EBI_EBIPEN */ 1473 #define _EBI_ROUTEPEN_EBIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ 1474 #define EBI_ROUTEPEN_EBIPEN_DEFAULT (_EBI_ROUTEPEN_EBIPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ 1475 #define EBI_ROUTEPEN_CS0PEN (0x1UL << 1) /**< EBI_CS0 Pin Enable */ 1476 #define _EBI_ROUTEPEN_CS0PEN_SHIFT 1 /**< Shift value for EBI_CS0PEN */ 1477 #define _EBI_ROUTEPEN_CS0PEN_MASK 0x2UL /**< Bit mask for EBI_CS0PEN */ 1478 #define _EBI_ROUTEPEN_CS0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ 1479 #define EBI_ROUTEPEN_CS0PEN_DEFAULT (_EBI_ROUTEPEN_CS0PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ 1480 #define EBI_ROUTEPEN_CS1PEN (0x1UL << 2) /**< EBI_CS1 Pin Enable */ 1481 #define _EBI_ROUTEPEN_CS1PEN_SHIFT 2 /**< Shift value for EBI_CS1PEN */ 1482 #define _EBI_ROUTEPEN_CS1PEN_MASK 0x4UL /**< Bit mask for EBI_CS1PEN */ 1483 #define _EBI_ROUTEPEN_CS1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ 1484 #define EBI_ROUTEPEN_CS1PEN_DEFAULT (_EBI_ROUTEPEN_CS1PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ 1485 #define EBI_ROUTEPEN_CS2PEN (0x1UL << 3) /**< EBI_CS2 Pin Enable */ 1486 #define _EBI_ROUTEPEN_CS2PEN_SHIFT 3 /**< Shift value for EBI_CS2PEN */ 1487 #define _EBI_ROUTEPEN_CS2PEN_MASK 0x8UL /**< Bit mask for EBI_CS2PEN */ 1488 #define _EBI_ROUTEPEN_CS2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ 1489 #define EBI_ROUTEPEN_CS2PEN_DEFAULT (_EBI_ROUTEPEN_CS2PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ 1490 #define EBI_ROUTEPEN_CS3PEN (0x1UL << 4) /**< EBI_CS3 Pin Enable */ 1491 #define _EBI_ROUTEPEN_CS3PEN_SHIFT 4 /**< Shift value for EBI_CS3PEN */ 1492 #define _EBI_ROUTEPEN_CS3PEN_MASK 0x10UL /**< Bit mask for EBI_CS3PEN */ 1493 #define _EBI_ROUTEPEN_CS3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ 1494 #define EBI_ROUTEPEN_CS3PEN_DEFAULT (_EBI_ROUTEPEN_CS3PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ 1495 #define EBI_ROUTEPEN_ALEPEN (0x1UL << 5) /**< EBI_ALE Pin Enable */ 1496 #define _EBI_ROUTEPEN_ALEPEN_SHIFT 5 /**< Shift value for EBI_ALEPEN */ 1497 #define _EBI_ROUTEPEN_ALEPEN_MASK 0x20UL /**< Bit mask for EBI_ALEPEN */ 1498 #define _EBI_ROUTEPEN_ALEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ 1499 #define EBI_ROUTEPEN_ALEPEN_DEFAULT (_EBI_ROUTEPEN_ALEPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ 1500 #define EBI_ROUTEPEN_ARDYPEN (0x1UL << 6) /**< EBI_ARDY Pin Enable */ 1501 #define _EBI_ROUTEPEN_ARDYPEN_SHIFT 6 /**< Shift value for EBI_ARDYPEN */ 1502 #define _EBI_ROUTEPEN_ARDYPEN_MASK 0x40UL /**< Bit mask for EBI_ARDYPEN */ 1503 #define _EBI_ROUTEPEN_ARDYPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ 1504 #define EBI_ROUTEPEN_ARDYPEN_DEFAULT (_EBI_ROUTEPEN_ARDYPEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ 1505 #define EBI_ROUTEPEN_BLPEN (0x1UL << 7) /**< EBI_BL[1:0] Pin Enable */ 1506 #define _EBI_ROUTEPEN_BLPEN_SHIFT 7 /**< Shift value for EBI_BLPEN */ 1507 #define _EBI_ROUTEPEN_BLPEN_MASK 0x80UL /**< Bit mask for EBI_BLPEN */ 1508 #define _EBI_ROUTEPEN_BLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ 1509 #define EBI_ROUTEPEN_BLPEN_DEFAULT (_EBI_ROUTEPEN_BLPEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ 1510 #define EBI_ROUTEPEN_NANDPEN (0x1UL << 12) /**< NANDRE and NANDWE Pin Enable */ 1511 #define _EBI_ROUTEPEN_NANDPEN_SHIFT 12 /**< Shift value for EBI_NANDPEN */ 1512 #define _EBI_ROUTEPEN_NANDPEN_MASK 0x1000UL /**< Bit mask for EBI_NANDPEN */ 1513 #define _EBI_ROUTEPEN_NANDPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ 1514 #define EBI_ROUTEPEN_NANDPEN_DEFAULT (_EBI_ROUTEPEN_NANDPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ 1515 #define _EBI_ROUTEPEN_ALB_SHIFT 16 /**< Shift value for EBI_ALB */ 1516 #define _EBI_ROUTEPEN_ALB_MASK 0x30000UL /**< Bit mask for EBI_ALB */ 1517 #define _EBI_ROUTEPEN_ALB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ 1518 #define _EBI_ROUTEPEN_ALB_A0 0x00000000UL /**< Mode A0 for EBI_ROUTEPEN */ 1519 #define _EBI_ROUTEPEN_ALB_A8 0x00000001UL /**< Mode A8 for EBI_ROUTEPEN */ 1520 #define _EBI_ROUTEPEN_ALB_A16 0x00000002UL /**< Mode A16 for EBI_ROUTEPEN */ 1521 #define _EBI_ROUTEPEN_ALB_A24 0x00000003UL /**< Mode A24 for EBI_ROUTEPEN */ 1522 #define EBI_ROUTEPEN_ALB_DEFAULT (_EBI_ROUTEPEN_ALB_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ 1523 #define EBI_ROUTEPEN_ALB_A0 (_EBI_ROUTEPEN_ALB_A0 << 16) /**< Shifted mode A0 for EBI_ROUTEPEN */ 1524 #define EBI_ROUTEPEN_ALB_A8 (_EBI_ROUTEPEN_ALB_A8 << 16) /**< Shifted mode A8 for EBI_ROUTEPEN */ 1525 #define EBI_ROUTEPEN_ALB_A16 (_EBI_ROUTEPEN_ALB_A16 << 16) /**< Shifted mode A16 for EBI_ROUTEPEN */ 1526 #define EBI_ROUTEPEN_ALB_A24 (_EBI_ROUTEPEN_ALB_A24 << 16) /**< Shifted mode A24 for EBI_ROUTEPEN */ 1527 #define _EBI_ROUTEPEN_APEN_SHIFT 18 /**< Shift value for EBI_APEN */ 1528 #define _EBI_ROUTEPEN_APEN_MASK 0x7C0000UL /**< Bit mask for EBI_APEN */ 1529 #define _EBI_ROUTEPEN_APEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ 1530 #define _EBI_ROUTEPEN_APEN_A0 0x00000000UL /**< Mode A0 for EBI_ROUTEPEN */ 1531 #define _EBI_ROUTEPEN_APEN_A5 0x00000005UL /**< Mode A5 for EBI_ROUTEPEN */ 1532 #define _EBI_ROUTEPEN_APEN_A6 0x00000006UL /**< Mode A6 for EBI_ROUTEPEN */ 1533 #define _EBI_ROUTEPEN_APEN_A7 0x00000007UL /**< Mode A7 for EBI_ROUTEPEN */ 1534 #define _EBI_ROUTEPEN_APEN_A8 0x00000008UL /**< Mode A8 for EBI_ROUTEPEN */ 1535 #define _EBI_ROUTEPEN_APEN_A9 0x00000009UL /**< Mode A9 for EBI_ROUTEPEN */ 1536 #define _EBI_ROUTEPEN_APEN_A10 0x0000000AUL /**< Mode A10 for EBI_ROUTEPEN */ 1537 #define _EBI_ROUTEPEN_APEN_A11 0x0000000BUL /**< Mode A11 for EBI_ROUTEPEN */ 1538 #define _EBI_ROUTEPEN_APEN_A12 0x0000000CUL /**< Mode A12 for EBI_ROUTEPEN */ 1539 #define _EBI_ROUTEPEN_APEN_A13 0x0000000DUL /**< Mode A13 for EBI_ROUTEPEN */ 1540 #define _EBI_ROUTEPEN_APEN_A14 0x0000000EUL /**< Mode A14 for EBI_ROUTEPEN */ 1541 #define _EBI_ROUTEPEN_APEN_A15 0x0000000FUL /**< Mode A15 for EBI_ROUTEPEN */ 1542 #define _EBI_ROUTEPEN_APEN_A16 0x00000010UL /**< Mode A16 for EBI_ROUTEPEN */ 1543 #define _EBI_ROUTEPEN_APEN_A17 0x00000011UL /**< Mode A17 for EBI_ROUTEPEN */ 1544 #define _EBI_ROUTEPEN_APEN_A18 0x00000012UL /**< Mode A18 for EBI_ROUTEPEN */ 1545 #define _EBI_ROUTEPEN_APEN_A19 0x00000013UL /**< Mode A19 for EBI_ROUTEPEN */ 1546 #define _EBI_ROUTEPEN_APEN_A20 0x00000014UL /**< Mode A20 for EBI_ROUTEPEN */ 1547 #define _EBI_ROUTEPEN_APEN_A21 0x00000015UL /**< Mode A21 for EBI_ROUTEPEN */ 1548 #define _EBI_ROUTEPEN_APEN_A22 0x00000016UL /**< Mode A22 for EBI_ROUTEPEN */ 1549 #define _EBI_ROUTEPEN_APEN_A23 0x00000017UL /**< Mode A23 for EBI_ROUTEPEN */ 1550 #define _EBI_ROUTEPEN_APEN_A24 0x00000018UL /**< Mode A24 for EBI_ROUTEPEN */ 1551 #define _EBI_ROUTEPEN_APEN_A25 0x00000019UL /**< Mode A25 for EBI_ROUTEPEN */ 1552 #define _EBI_ROUTEPEN_APEN_A26 0x0000001AUL /**< Mode A26 for EBI_ROUTEPEN */ 1553 #define _EBI_ROUTEPEN_APEN_A27 0x0000001BUL /**< Mode A27 for EBI_ROUTEPEN */ 1554 #define _EBI_ROUTEPEN_APEN_A28 0x0000001CUL /**< Mode A28 for EBI_ROUTEPEN */ 1555 #define EBI_ROUTEPEN_APEN_DEFAULT (_EBI_ROUTEPEN_APEN_DEFAULT << 18) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ 1556 #define EBI_ROUTEPEN_APEN_A0 (_EBI_ROUTEPEN_APEN_A0 << 18) /**< Shifted mode A0 for EBI_ROUTEPEN */ 1557 #define EBI_ROUTEPEN_APEN_A5 (_EBI_ROUTEPEN_APEN_A5 << 18) /**< Shifted mode A5 for EBI_ROUTEPEN */ 1558 #define EBI_ROUTEPEN_APEN_A6 (_EBI_ROUTEPEN_APEN_A6 << 18) /**< Shifted mode A6 for EBI_ROUTEPEN */ 1559 #define EBI_ROUTEPEN_APEN_A7 (_EBI_ROUTEPEN_APEN_A7 << 18) /**< Shifted mode A7 for EBI_ROUTEPEN */ 1560 #define EBI_ROUTEPEN_APEN_A8 (_EBI_ROUTEPEN_APEN_A8 << 18) /**< Shifted mode A8 for EBI_ROUTEPEN */ 1561 #define EBI_ROUTEPEN_APEN_A9 (_EBI_ROUTEPEN_APEN_A9 << 18) /**< Shifted mode A9 for EBI_ROUTEPEN */ 1562 #define EBI_ROUTEPEN_APEN_A10 (_EBI_ROUTEPEN_APEN_A10 << 18) /**< Shifted mode A10 for EBI_ROUTEPEN */ 1563 #define EBI_ROUTEPEN_APEN_A11 (_EBI_ROUTEPEN_APEN_A11 << 18) /**< Shifted mode A11 for EBI_ROUTEPEN */ 1564 #define EBI_ROUTEPEN_APEN_A12 (_EBI_ROUTEPEN_APEN_A12 << 18) /**< Shifted mode A12 for EBI_ROUTEPEN */ 1565 #define EBI_ROUTEPEN_APEN_A13 (_EBI_ROUTEPEN_APEN_A13 << 18) /**< Shifted mode A13 for EBI_ROUTEPEN */ 1566 #define EBI_ROUTEPEN_APEN_A14 (_EBI_ROUTEPEN_APEN_A14 << 18) /**< Shifted mode A14 for EBI_ROUTEPEN */ 1567 #define EBI_ROUTEPEN_APEN_A15 (_EBI_ROUTEPEN_APEN_A15 << 18) /**< Shifted mode A15 for EBI_ROUTEPEN */ 1568 #define EBI_ROUTEPEN_APEN_A16 (_EBI_ROUTEPEN_APEN_A16 << 18) /**< Shifted mode A16 for EBI_ROUTEPEN */ 1569 #define EBI_ROUTEPEN_APEN_A17 (_EBI_ROUTEPEN_APEN_A17 << 18) /**< Shifted mode A17 for EBI_ROUTEPEN */ 1570 #define EBI_ROUTEPEN_APEN_A18 (_EBI_ROUTEPEN_APEN_A18 << 18) /**< Shifted mode A18 for EBI_ROUTEPEN */ 1571 #define EBI_ROUTEPEN_APEN_A19 (_EBI_ROUTEPEN_APEN_A19 << 18) /**< Shifted mode A19 for EBI_ROUTEPEN */ 1572 #define EBI_ROUTEPEN_APEN_A20 (_EBI_ROUTEPEN_APEN_A20 << 18) /**< Shifted mode A20 for EBI_ROUTEPEN */ 1573 #define EBI_ROUTEPEN_APEN_A21 (_EBI_ROUTEPEN_APEN_A21 << 18) /**< Shifted mode A21 for EBI_ROUTEPEN */ 1574 #define EBI_ROUTEPEN_APEN_A22 (_EBI_ROUTEPEN_APEN_A22 << 18) /**< Shifted mode A22 for EBI_ROUTEPEN */ 1575 #define EBI_ROUTEPEN_APEN_A23 (_EBI_ROUTEPEN_APEN_A23 << 18) /**< Shifted mode A23 for EBI_ROUTEPEN */ 1576 #define EBI_ROUTEPEN_APEN_A24 (_EBI_ROUTEPEN_APEN_A24 << 18) /**< Shifted mode A24 for EBI_ROUTEPEN */ 1577 #define EBI_ROUTEPEN_APEN_A25 (_EBI_ROUTEPEN_APEN_A25 << 18) /**< Shifted mode A25 for EBI_ROUTEPEN */ 1578 #define EBI_ROUTEPEN_APEN_A26 (_EBI_ROUTEPEN_APEN_A26 << 18) /**< Shifted mode A26 for EBI_ROUTEPEN */ 1579 #define EBI_ROUTEPEN_APEN_A27 (_EBI_ROUTEPEN_APEN_A27 << 18) /**< Shifted mode A27 for EBI_ROUTEPEN */ 1580 #define EBI_ROUTEPEN_APEN_A28 (_EBI_ROUTEPEN_APEN_A28 << 18) /**< Shifted mode A28 for EBI_ROUTEPEN */ 1581 #define EBI_ROUTEPEN_TFTPEN (0x1UL << 24) /**< EBI_TFT Pin Enable */ 1582 #define _EBI_ROUTEPEN_TFTPEN_SHIFT 24 /**< Shift value for EBI_TFTPEN */ 1583 #define _EBI_ROUTEPEN_TFTPEN_MASK 0x1000000UL /**< Bit mask for EBI_TFTPEN */ 1584 #define _EBI_ROUTEPEN_TFTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ 1585 #define EBI_ROUTEPEN_TFTPEN_DEFAULT (_EBI_ROUTEPEN_TFTPEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ 1586 #define EBI_ROUTEPEN_DATAENPEN (0x1UL << 25) /**< EBI_DATA Pin Enable */ 1587 #define _EBI_ROUTEPEN_DATAENPEN_SHIFT 25 /**< Shift value for EBI_DATAENPEN */ 1588 #define _EBI_ROUTEPEN_DATAENPEN_MASK 0x2000000UL /**< Bit mask for EBI_DATAENPEN */ 1589 #define _EBI_ROUTEPEN_DATAENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ 1590 #define EBI_ROUTEPEN_DATAENPEN_DEFAULT (_EBI_ROUTEPEN_DATAENPEN_DEFAULT << 25) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ 1591 #define EBI_ROUTEPEN_CSTFTPEN (0x1UL << 26) /**< EBI_CSTFT Pin Enable */ 1592 #define _EBI_ROUTEPEN_CSTFTPEN_SHIFT 26 /**< Shift value for EBI_CSTFTPEN */ 1593 #define _EBI_ROUTEPEN_CSTFTPEN_MASK 0x4000000UL /**< Bit mask for EBI_CSTFTPEN */ 1594 #define _EBI_ROUTEPEN_CSTFTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTEPEN */ 1595 #define EBI_ROUTEPEN_CSTFTPEN_DEFAULT (_EBI_ROUTEPEN_CSTFTPEN_DEFAULT << 26) /**< Shifted mode DEFAULT for EBI_ROUTEPEN */ 1596 1597 /* Bit fields for EBI ROUTELOC0 */ 1598 #define _EBI_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for EBI_ROUTELOC0 */ 1599 #define _EBI_ROUTELOC0_MASK 0x03070707UL /**< Mask for EBI_ROUTELOC0 */ 1600 #define _EBI_ROUTELOC0_EBILOC_SHIFT 0 /**< Shift value for EBI_EBILOC */ 1601 #define _EBI_ROUTELOC0_EBILOC_MASK 0x7UL /**< Bit mask for EBI_EBILOC */ 1602 #define _EBI_ROUTELOC0_EBILOC_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTELOC0 */ 1603 #define _EBI_ROUTELOC0_EBILOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTELOC0 */ 1604 #define _EBI_ROUTELOC0_EBILOC_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTELOC0 */ 1605 #define _EBI_ROUTELOC0_EBILOC_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTELOC0 */ 1606 #define _EBI_ROUTELOC0_EBILOC_LOC3 0x00000003UL /**< Mode LOC3 for EBI_ROUTELOC0 */ 1607 #define _EBI_ROUTELOC0_EBILOC_LOC4 0x00000004UL /**< Mode LOC4 for EBI_ROUTELOC0 */ 1608 #define _EBI_ROUTELOC0_EBILOC_LOC5 0x00000005UL /**< Mode LOC5 for EBI_ROUTELOC0 */ 1609 #define EBI_ROUTELOC0_EBILOC_LOC0 (_EBI_ROUTELOC0_EBILOC_LOC0 << 0) /**< Shifted mode LOC0 for EBI_ROUTELOC0 */ 1610 #define EBI_ROUTELOC0_EBILOC_DEFAULT (_EBI_ROUTELOC0_EBILOC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ROUTELOC0 */ 1611 #define EBI_ROUTELOC0_EBILOC_LOC1 (_EBI_ROUTELOC0_EBILOC_LOC1 << 0) /**< Shifted mode LOC1 for EBI_ROUTELOC0 */ 1612 #define EBI_ROUTELOC0_EBILOC_LOC2 (_EBI_ROUTELOC0_EBILOC_LOC2 << 0) /**< Shifted mode LOC2 for EBI_ROUTELOC0 */ 1613 #define EBI_ROUTELOC0_EBILOC_LOC3 (_EBI_ROUTELOC0_EBILOC_LOC3 << 0) /**< Shifted mode LOC3 for EBI_ROUTELOC0 */ 1614 #define EBI_ROUTELOC0_EBILOC_LOC4 (_EBI_ROUTELOC0_EBILOC_LOC4 << 0) /**< Shifted mode LOC4 for EBI_ROUTELOC0 */ 1615 #define EBI_ROUTELOC0_EBILOC_LOC5 (_EBI_ROUTELOC0_EBILOC_LOC5 << 0) /**< Shifted mode LOC5 for EBI_ROUTELOC0 */ 1616 #define _EBI_ROUTELOC0_CSLOC_SHIFT 8 /**< Shift value for EBI_CSLOC */ 1617 #define _EBI_ROUTELOC0_CSLOC_MASK 0x700UL /**< Bit mask for EBI_CSLOC */ 1618 #define _EBI_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTELOC0 */ 1619 #define _EBI_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTELOC0 */ 1620 #define _EBI_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTELOC0 */ 1621 #define _EBI_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTELOC0 */ 1622 #define _EBI_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for EBI_ROUTELOC0 */ 1623 #define _EBI_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for EBI_ROUTELOC0 */ 1624 #define EBI_ROUTELOC0_CSLOC_LOC0 (_EBI_ROUTELOC0_CSLOC_LOC0 << 8) /**< Shifted mode LOC0 for EBI_ROUTELOC0 */ 1625 #define EBI_ROUTELOC0_CSLOC_DEFAULT (_EBI_ROUTELOC0_CSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ROUTELOC0 */ 1626 #define EBI_ROUTELOC0_CSLOC_LOC1 (_EBI_ROUTELOC0_CSLOC_LOC1 << 8) /**< Shifted mode LOC1 for EBI_ROUTELOC0 */ 1627 #define EBI_ROUTELOC0_CSLOC_LOC2 (_EBI_ROUTELOC0_CSLOC_LOC2 << 8) /**< Shifted mode LOC2 for EBI_ROUTELOC0 */ 1628 #define EBI_ROUTELOC0_CSLOC_LOC3 (_EBI_ROUTELOC0_CSLOC_LOC3 << 8) /**< Shifted mode LOC3 for EBI_ROUTELOC0 */ 1629 #define EBI_ROUTELOC0_CSLOC_LOC4 (_EBI_ROUTELOC0_CSLOC_LOC4 << 8) /**< Shifted mode LOC4 for EBI_ROUTELOC0 */ 1630 #define _EBI_ROUTELOC0_NANDLOC_SHIFT 16 /**< Shift value for EBI_NANDLOC */ 1631 #define _EBI_ROUTELOC0_NANDLOC_MASK 0x70000UL /**< Bit mask for EBI_NANDLOC */ 1632 #define _EBI_ROUTELOC0_NANDLOC_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTELOC0 */ 1633 #define _EBI_ROUTELOC0_NANDLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTELOC0 */ 1634 #define _EBI_ROUTELOC0_NANDLOC_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTELOC0 */ 1635 #define _EBI_ROUTELOC0_NANDLOC_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTELOC0 */ 1636 #define _EBI_ROUTELOC0_NANDLOC_LOC3 0x00000003UL /**< Mode LOC3 for EBI_ROUTELOC0 */ 1637 #define _EBI_ROUTELOC0_NANDLOC_LOC4 0x00000004UL /**< Mode LOC4 for EBI_ROUTELOC0 */ 1638 #define _EBI_ROUTELOC0_NANDLOC_LOC5 0x00000005UL /**< Mode LOC5 for EBI_ROUTELOC0 */ 1639 #define EBI_ROUTELOC0_NANDLOC_LOC0 (_EBI_ROUTELOC0_NANDLOC_LOC0 << 16) /**< Shifted mode LOC0 for EBI_ROUTELOC0 */ 1640 #define EBI_ROUTELOC0_NANDLOC_DEFAULT (_EBI_ROUTELOC0_NANDLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_ROUTELOC0 */ 1641 #define EBI_ROUTELOC0_NANDLOC_LOC1 (_EBI_ROUTELOC0_NANDLOC_LOC1 << 16) /**< Shifted mode LOC1 for EBI_ROUTELOC0 */ 1642 #define EBI_ROUTELOC0_NANDLOC_LOC2 (_EBI_ROUTELOC0_NANDLOC_LOC2 << 16) /**< Shifted mode LOC2 for EBI_ROUTELOC0 */ 1643 #define EBI_ROUTELOC0_NANDLOC_LOC3 (_EBI_ROUTELOC0_NANDLOC_LOC3 << 16) /**< Shifted mode LOC3 for EBI_ROUTELOC0 */ 1644 #define EBI_ROUTELOC0_NANDLOC_LOC4 (_EBI_ROUTELOC0_NANDLOC_LOC4 << 16) /**< Shifted mode LOC4 for EBI_ROUTELOC0 */ 1645 #define EBI_ROUTELOC0_NANDLOC_LOC5 (_EBI_ROUTELOC0_NANDLOC_LOC5 << 16) /**< Shifted mode LOC5 for EBI_ROUTELOC0 */ 1646 #define _EBI_ROUTELOC0_TFTLOC_SHIFT 24 /**< Shift value for EBI_TFTLOC */ 1647 #define _EBI_ROUTELOC0_TFTLOC_MASK 0x3000000UL /**< Bit mask for EBI_TFTLOC */ 1648 #define _EBI_ROUTELOC0_TFTLOC_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTELOC0 */ 1649 #define _EBI_ROUTELOC0_TFTLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTELOC0 */ 1650 #define _EBI_ROUTELOC0_TFTLOC_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTELOC0 */ 1651 #define _EBI_ROUTELOC0_TFTLOC_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTELOC0 */ 1652 #define _EBI_ROUTELOC0_TFTLOC_LOC3 0x00000003UL /**< Mode LOC3 for EBI_ROUTELOC0 */ 1653 #define EBI_ROUTELOC0_TFTLOC_LOC0 (_EBI_ROUTELOC0_TFTLOC_LOC0 << 24) /**< Shifted mode LOC0 for EBI_ROUTELOC0 */ 1654 #define EBI_ROUTELOC0_TFTLOC_DEFAULT (_EBI_ROUTELOC0_TFTLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for EBI_ROUTELOC0 */ 1655 #define EBI_ROUTELOC0_TFTLOC_LOC1 (_EBI_ROUTELOC0_TFTLOC_LOC1 << 24) /**< Shifted mode LOC1 for EBI_ROUTELOC0 */ 1656 #define EBI_ROUTELOC0_TFTLOC_LOC2 (_EBI_ROUTELOC0_TFTLOC_LOC2 << 24) /**< Shifted mode LOC2 for EBI_ROUTELOC0 */ 1657 #define EBI_ROUTELOC0_TFTLOC_LOC3 (_EBI_ROUTELOC0_TFTLOC_LOC3 << 24) /**< Shifted mode LOC3 for EBI_ROUTELOC0 */ 1658 1659 /* Bit fields for EBI ROUTELOC1 */ 1660 #define _EBI_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for EBI_ROUTELOC1 */ 1661 #define _EBI_ROUTELOC1_MASK 0x00070303UL /**< Mask for EBI_ROUTELOC1 */ 1662 #define _EBI_ROUTELOC1_ADLOC_SHIFT 0 /**< Shift value for EBI_ADLOC */ 1663 #define _EBI_ROUTELOC1_ADLOC_MASK 0x3UL /**< Bit mask for EBI_ADLOC */ 1664 #define _EBI_ROUTELOC1_ADLOC_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTELOC1 */ 1665 #define _EBI_ROUTELOC1_ADLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTELOC1 */ 1666 #define _EBI_ROUTELOC1_ADLOC_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTELOC1 */ 1667 #define _EBI_ROUTELOC1_ADLOC_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTELOC1 */ 1668 #define EBI_ROUTELOC1_ADLOC_LOC0 (_EBI_ROUTELOC1_ADLOC_LOC0 << 0) /**< Shifted mode LOC0 for EBI_ROUTELOC1 */ 1669 #define EBI_ROUTELOC1_ADLOC_DEFAULT (_EBI_ROUTELOC1_ADLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ROUTELOC1 */ 1670 #define EBI_ROUTELOC1_ADLOC_LOC1 (_EBI_ROUTELOC1_ADLOC_LOC1 << 0) /**< Shifted mode LOC1 for EBI_ROUTELOC1 */ 1671 #define EBI_ROUTELOC1_ADLOC_LOC2 (_EBI_ROUTELOC1_ADLOC_LOC2 << 0) /**< Shifted mode LOC2 for EBI_ROUTELOC1 */ 1672 #define _EBI_ROUTELOC1_ALOC_SHIFT 8 /**< Shift value for EBI_ALOC */ 1673 #define _EBI_ROUTELOC1_ALOC_MASK 0x300UL /**< Bit mask for EBI_ALOC */ 1674 #define _EBI_ROUTELOC1_ALOC_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTELOC1 */ 1675 #define _EBI_ROUTELOC1_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTELOC1 */ 1676 #define _EBI_ROUTELOC1_ALOC_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTELOC1 */ 1677 #define _EBI_ROUTELOC1_ALOC_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTELOC1 */ 1678 #define _EBI_ROUTELOC1_ALOC_LOC3 0x00000003UL /**< Mode LOC3 for EBI_ROUTELOC1 */ 1679 #define EBI_ROUTELOC1_ALOC_LOC0 (_EBI_ROUTELOC1_ALOC_LOC0 << 8) /**< Shifted mode LOC0 for EBI_ROUTELOC1 */ 1680 #define EBI_ROUTELOC1_ALOC_DEFAULT (_EBI_ROUTELOC1_ALOC_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ROUTELOC1 */ 1681 #define EBI_ROUTELOC1_ALOC_LOC1 (_EBI_ROUTELOC1_ALOC_LOC1 << 8) /**< Shifted mode LOC1 for EBI_ROUTELOC1 */ 1682 #define EBI_ROUTELOC1_ALOC_LOC2 (_EBI_ROUTELOC1_ALOC_LOC2 << 8) /**< Shifted mode LOC2 for EBI_ROUTELOC1 */ 1683 #define EBI_ROUTELOC1_ALOC_LOC3 (_EBI_ROUTELOC1_ALOC_LOC3 << 8) /**< Shifted mode LOC3 for EBI_ROUTELOC1 */ 1684 #define _EBI_ROUTELOC1_RDYLOC_SHIFT 16 /**< Shift value for EBI_RDYLOC */ 1685 #define _EBI_ROUTELOC1_RDYLOC_MASK 0x70000UL /**< Bit mask for EBI_RDYLOC */ 1686 #define _EBI_ROUTELOC1_RDYLOC_LOC0 0x00000000UL /**< Mode LOC0 for EBI_ROUTELOC1 */ 1687 #define _EBI_ROUTELOC1_RDYLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTELOC1 */ 1688 #define _EBI_ROUTELOC1_RDYLOC_LOC1 0x00000001UL /**< Mode LOC1 for EBI_ROUTELOC1 */ 1689 #define _EBI_ROUTELOC1_RDYLOC_LOC2 0x00000002UL /**< Mode LOC2 for EBI_ROUTELOC1 */ 1690 #define _EBI_ROUTELOC1_RDYLOC_LOC3 0x00000003UL /**< Mode LOC3 for EBI_ROUTELOC1 */ 1691 #define _EBI_ROUTELOC1_RDYLOC_LOC4 0x00000004UL /**< Mode LOC4 for EBI_ROUTELOC1 */ 1692 #define _EBI_ROUTELOC1_RDYLOC_LOC5 0x00000005UL /**< Mode LOC5 for EBI_ROUTELOC1 */ 1693 #define EBI_ROUTELOC1_RDYLOC_LOC0 (_EBI_ROUTELOC1_RDYLOC_LOC0 << 16) /**< Shifted mode LOC0 for EBI_ROUTELOC1 */ 1694 #define EBI_ROUTELOC1_RDYLOC_DEFAULT (_EBI_ROUTELOC1_RDYLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_ROUTELOC1 */ 1695 #define EBI_ROUTELOC1_RDYLOC_LOC1 (_EBI_ROUTELOC1_RDYLOC_LOC1 << 16) /**< Shifted mode LOC1 for EBI_ROUTELOC1 */ 1696 #define EBI_ROUTELOC1_RDYLOC_LOC2 (_EBI_ROUTELOC1_RDYLOC_LOC2 << 16) /**< Shifted mode LOC2 for EBI_ROUTELOC1 */ 1697 #define EBI_ROUTELOC1_RDYLOC_LOC3 (_EBI_ROUTELOC1_RDYLOC_LOC3 << 16) /**< Shifted mode LOC3 for EBI_ROUTELOC1 */ 1698 #define EBI_ROUTELOC1_RDYLOC_LOC4 (_EBI_ROUTELOC1_RDYLOC_LOC4 << 16) /**< Shifted mode LOC4 for EBI_ROUTELOC1 */ 1699 #define EBI_ROUTELOC1_RDYLOC_LOC5 (_EBI_ROUTELOC1_RDYLOC_LOC5 << 16) /**< Shifted mode LOC5 for EBI_ROUTELOC1 */ 1700 1701 /** @} */ 1702 /** @} End of group EFM32GG11B_EBI */ 1703 /** @} End of group Parts */ 1704
