1 /***************************************************************************//** 2 * @file 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File 4 * for EFM32GG11B820F2048GL120 5 ******************************************************************************* 6 * # License 7 * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b> 8 ******************************************************************************* 9 * 10 * SPDX-License-Identifier: Zlib 11 * 12 * The licensor of this software is Silicon Laboratories Inc. 13 * 14 * This software is provided 'as-is', without any express or implied 15 * warranty. In no event will the authors be held liable for any damages 16 * arising from the use of this software. 17 * 18 * Permission is granted to anyone to use this software for any purpose, 19 * including commercial applications, and to alter it and redistribute it 20 * freely, subject to the following restrictions: 21 * 22 * 1. The origin of this software must not be misrepresented; you must not 23 * claim that you wrote the original software. If you use this software 24 * in a product, an acknowledgment in the product documentation would be 25 * appreciated but is not required. 26 * 2. Altered source versions must be plainly marked as such, and must not be 27 * misrepresented as being the original software. 28 * 3. This notice may not be removed or altered from any source distribution. 29 * 30 ******************************************************************************/ 31 32 #if defined(__ICCARM__) 33 #pragma system_include /* Treat file as system include file. */ 34 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 35 #pragma clang system_header /* Treat file as system include file. */ 36 #endif 37 38 #ifndef EFM32GG11B820F2048GL120_H 39 #define EFM32GG11B820F2048GL120_H 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /***************************************************************************//** 46 * @addtogroup Parts 47 * @{ 48 ******************************************************************************/ 49 50 /***************************************************************************//** 51 * @defgroup EFM32GG11B820F2048GL120 EFM32GG11B820F2048GL120 52 * @{ 53 ******************************************************************************/ 54 55 /** Interrupt Number Definition */ 56 typedef enum IRQn{ 57 /****** Cortex-M4 Processor Exceptions Numbers *******************************************/ 58 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 59 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ 60 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ 61 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ 62 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ 63 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ 64 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ 65 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ 66 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ 67 68 /****** EFM32GG11B Peripheral Interrupt Numbers *********************************************/ 69 70 EMU_IRQn = 0, /*!< 16+0 EFM32 EMU Interrupt */ 71 WDOG0_IRQn = 1, /*!< 16+1 EFM32 WDOG0 Interrupt */ 72 LDMA_IRQn = 2, /*!< 16+2 EFM32 LDMA Interrupt */ 73 GPIO_EVEN_IRQn = 3, /*!< 16+3 EFM32 GPIO_EVEN Interrupt */ 74 SMU_IRQn = 4, /*!< 16+4 EFM32 SMU Interrupt */ 75 TIMER0_IRQn = 5, /*!< 16+5 EFM32 TIMER0 Interrupt */ 76 USART0_RX_IRQn = 6, /*!< 16+6 EFM32 USART0_RX Interrupt */ 77 USART0_TX_IRQn = 7, /*!< 16+7 EFM32 USART0_TX Interrupt */ 78 ACMP0_IRQn = 8, /*!< 16+8 EFM32 ACMP0 Interrupt */ 79 ADC0_IRQn = 9, /*!< 16+9 EFM32 ADC0 Interrupt */ 80 IDAC0_IRQn = 10, /*!< 16+10 EFM32 IDAC0 Interrupt */ 81 I2C0_IRQn = 11, /*!< 16+11 EFM32 I2C0 Interrupt */ 82 I2C1_IRQn = 12, /*!< 16+12 EFM32 I2C1 Interrupt */ 83 GPIO_ODD_IRQn = 13, /*!< 16+13 EFM32 GPIO_ODD Interrupt */ 84 TIMER1_IRQn = 14, /*!< 16+14 EFM32 TIMER1 Interrupt */ 85 TIMER2_IRQn = 15, /*!< 16+15 EFM32 TIMER2 Interrupt */ 86 TIMER3_IRQn = 16, /*!< 16+16 EFM32 TIMER3 Interrupt */ 87 USART1_RX_IRQn = 17, /*!< 16+17 EFM32 USART1_RX Interrupt */ 88 USART1_TX_IRQn = 18, /*!< 16+18 EFM32 USART1_TX Interrupt */ 89 USART2_RX_IRQn = 19, /*!< 16+19 EFM32 USART2_RX Interrupt */ 90 USART2_TX_IRQn = 20, /*!< 16+20 EFM32 USART2_TX Interrupt */ 91 UART0_RX_IRQn = 21, /*!< 16+21 EFM32 UART0_RX Interrupt */ 92 UART0_TX_IRQn = 22, /*!< 16+22 EFM32 UART0_TX Interrupt */ 93 UART1_RX_IRQn = 23, /*!< 16+23 EFM32 UART1_RX Interrupt */ 94 UART1_TX_IRQn = 24, /*!< 16+24 EFM32 UART1_TX Interrupt */ 95 LEUART0_IRQn = 25, /*!< 16+25 EFM32 LEUART0 Interrupt */ 96 LEUART1_IRQn = 26, /*!< 16+26 EFM32 LEUART1 Interrupt */ 97 LETIMER0_IRQn = 27, /*!< 16+27 EFM32 LETIMER0 Interrupt */ 98 PCNT0_IRQn = 28, /*!< 16+28 EFM32 PCNT0 Interrupt */ 99 PCNT1_IRQn = 29, /*!< 16+29 EFM32 PCNT1 Interrupt */ 100 PCNT2_IRQn = 30, /*!< 16+30 EFM32 PCNT2 Interrupt */ 101 RTCC_IRQn = 31, /*!< 16+31 EFM32 RTCC Interrupt */ 102 CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */ 103 MSC_IRQn = 33, /*!< 16+33 EFM32 MSC Interrupt */ 104 CRYPTO0_IRQn = 34, /*!< 16+34 EFM32 CRYPTO0 Interrupt */ 105 CRYOTIMER_IRQn = 35, /*!< 16+35 EFM32 CRYOTIMER Interrupt */ 106 FPUEH_IRQn = 36, /*!< 16+36 EFM32 FPUEH Interrupt */ 107 USART3_RX_IRQn = 37, /*!< 16+37 EFM32 USART3_RX Interrupt */ 108 USART3_TX_IRQn = 38, /*!< 16+38 EFM32 USART3_TX Interrupt */ 109 USART4_RX_IRQn = 39, /*!< 16+39 EFM32 USART4_RX Interrupt */ 110 USART4_TX_IRQn = 40, /*!< 16+40 EFM32 USART4_TX Interrupt */ 111 WTIMER0_IRQn = 41, /*!< 16+41 EFM32 WTIMER0 Interrupt */ 112 WTIMER1_IRQn = 42, /*!< 16+42 EFM32 WTIMER1 Interrupt */ 113 WTIMER2_IRQn = 43, /*!< 16+43 EFM32 WTIMER2 Interrupt */ 114 WTIMER3_IRQn = 44, /*!< 16+44 EFM32 WTIMER3 Interrupt */ 115 I2C2_IRQn = 45, /*!< 16+45 EFM32 I2C2 Interrupt */ 116 VDAC0_IRQn = 46, /*!< 16+46 EFM32 VDAC0 Interrupt */ 117 TIMER4_IRQn = 47, /*!< 16+47 EFM32 TIMER4 Interrupt */ 118 TIMER5_IRQn = 48, /*!< 16+48 EFM32 TIMER5 Interrupt */ 119 TIMER6_IRQn = 49, /*!< 16+49 EFM32 TIMER6 Interrupt */ 120 USART5_RX_IRQn = 50, /*!< 16+50 EFM32 USART5_RX Interrupt */ 121 USART5_TX_IRQn = 51, /*!< 16+51 EFM32 USART5_TX Interrupt */ 122 CSEN_IRQn = 52, /*!< 16+52 EFM32 CSEN Interrupt */ 123 LESENSE_IRQn = 53, /*!< 16+53 EFM32 LESENSE Interrupt */ 124 EBI_IRQn = 54, /*!< 16+54 EFM32 EBI Interrupt */ 125 ACMP2_IRQn = 55, /*!< 16+55 EFM32 ACMP2 Interrupt */ 126 ADC1_IRQn = 56, /*!< 16+56 EFM32 ADC1 Interrupt */ 127 LCD_IRQn = 57, /*!< 16+57 EFM32 LCD Interrupt */ 128 SDIO_IRQn = 58, /*!< 16+58 EFM32 SDIO Interrupt */ 129 ETH_IRQn = 59, /*!< 16+59 EFM32 ETH Interrupt */ 130 CAN0_IRQn = 60, /*!< 16+60 EFM32 CAN0 Interrupt */ 131 CAN1_IRQn = 61, /*!< 16+61 EFM32 CAN1 Interrupt */ 132 USB_IRQn = 62, /*!< 16+62 EFM32 USB Interrupt */ 133 RTC_IRQn = 63, /*!< 16+63 EFM32 RTC Interrupt */ 134 WDOG1_IRQn = 64, /*!< 16+64 EFM32 WDOG1 Interrupt */ 135 LETIMER1_IRQn = 65, /*!< 16+65 EFM32 LETIMER1 Interrupt */ 136 TRNG0_IRQn = 66, /*!< 16+66 EFM32 TRNG0 Interrupt */ 137 QSPI0_IRQn = 67, /*!< 16+67 EFM32 QSPI0 Interrupt */ 138 } IRQn_Type; 139 140 /***************************************************************************//** 141 * @defgroup EFM32GG11B820F2048GL120_Core Core 142 * @{ 143 * @brief Processor and Core Peripheral Section 144 ******************************************************************************/ 145 #define __MPU_PRESENT 1U /**< Presence of MPU */ 146 #define __FPU_PRESENT 1U /**< Presence of FPU */ 147 #define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ 148 #define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ 149 #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ 150 151 /** @} End of group EFM32GG11B820F2048GL120_Core */ 152 153 /***************************************************************************//** 154 * @defgroup EFM32GG11B820F2048GL120_Part Part 155 * @{ 156 ******************************************************************************/ 157 158 /** Part family */ 159 160 #define _EFM32_GIANT_FAMILY 1 /**< GIANT Gecko MCU Family */ 161 #define _EFM_DEVICE /**< Silicon Labs EFM-type MCU */ 162 #define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ 163 #define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ 164 #define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ 165 #define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ 166 #define _SILICON_LABS_GECKO_INTERNAL_SDID 100 /**< Silicon Labs internal use only, may change any time */ 167 #define _SILICON_LABS_GECKO_INTERNAL_SDID_100 /**< Silicon Labs internal use only, may change any time */ 168 #define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ 169 #define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ 170 #define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ 171 #define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ 172 173 /* If part number is not defined as compiler option, define it */ 174 #if !defined(EFM32GG11B820F2048GL120) 175 #define EFM32GG11B820F2048GL120 1 /**< GIANT Gecko Part */ 176 #endif 177 178 /** Configure part number */ 179 #define PART_NUMBER "EFM32GG11B820F2048GL120" /**< Part Number */ 180 181 /** Memory Base addresses and limits */ 182 #define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ 183 #define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ 184 #define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ 185 #define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ 186 #define PER1_BITCLR_MEM_BASE (0x44050000UL) /**< PER1_BITCLR base address */ 187 #define PER1_BITCLR_MEM_SIZE (0xA0000UL) /**< PER1_BITCLR available address space */ 188 #define PER1_BITCLR_MEM_END (0x440EFFFFUL) /**< PER1_BITCLR end address */ 189 #define PER1_BITCLR_MEM_BITS (0x00000014UL) /**< PER1_BITCLR used bits */ 190 #define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ 191 #define RAM2_MEM_SIZE (0x40000UL) /**< RAM2 available address space */ 192 #define RAM2_MEM_END (0x2007FFFFUL) /**< RAM2 end address */ 193 #define RAM2_MEM_BITS (0x00000012UL) /**< RAM2 used bits */ 194 #define QSPI0_CODE_MEM_BASE (0x04000000UL) /**< QSPI0_CODE base address */ 195 #define QSPI0_CODE_MEM_SIZE (0x8000000UL) /**< QSPI0_CODE available address space */ 196 #define QSPI0_CODE_MEM_END (0x0BFFFFFFUL) /**< QSPI0_CODE end address */ 197 #define QSPI0_CODE_MEM_BITS (0x0000001BUL) /**< QSPI0_CODE used bits */ 198 #define PER1_BITSET_MEM_BASE (0x46050000UL) /**< PER1_BITSET base address */ 199 #define PER1_BITSET_MEM_SIZE (0xA0000UL) /**< PER1_BITSET available address space */ 200 #define PER1_BITSET_MEM_END (0x460EFFFFUL) /**< PER1_BITSET end address */ 201 #define PER1_BITSET_MEM_BITS (0x00000014UL) /**< PER1_BITSET used bits */ 202 #define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ 203 #define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ 204 #define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ 205 #define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ 206 #define USB_MEM_BASE (0x40100000UL) /**< USB base address */ 207 #define USB_MEM_SIZE (0x40000UL) /**< USB available address space */ 208 #define USB_MEM_END (0x4013FFFFUL) /**< USB end address */ 209 #define USB_MEM_BITS (0x00000012UL) /**< USB used bits */ 210 #define QSPI0_MEM_BASE (0xC0000000UL) /**< QSPI0 base address */ 211 #define QSPI0_MEM_SIZE (0x10000000UL) /**< QSPI0 available address space */ 212 #define QSPI0_MEM_END (0xCFFFFFFFUL) /**< QSPI0 end address */ 213 #define QSPI0_MEM_BITS (0x0000001CUL) /**< QSPI0 used bits */ 214 #define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ 215 #define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ 216 #define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ 217 #define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ 218 #define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ 219 #define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ 220 #define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ 221 #define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ 222 #define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ 223 #define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ 224 #define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ 225 #define EBI_MEM_BITS (0x0000001EUL) /**< EBI used bits */ 226 #define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ 227 #define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ 228 #define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ 229 #define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ 230 #define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ 231 #define FLASH_MEM_SIZE (0x4000000UL) /**< FLASH available address space */ 232 #define FLASH_MEM_END (0x03FFFFFFUL) /**< FLASH end address */ 233 #define FLASH_MEM_BITS (0x0000001AUL) /**< FLASH used bits */ 234 #define FLASH_INFO_MEM_BASE (0x0F000000UL) /**< FLASH_INFO base address */ 235 #define FLASH_INFO_MEM_SIZE (0x1000000UL) /**< FLASH_INFO available address space */ 236 #define FLASH_INFO_MEM_END (0x0FFFFFFFUL) /**< FLASH_INFO end address */ 237 #define FLASH_INFO_MEM_BITS (0x00000018UL) /**< FLASH_INFO used bits */ 238 #define SDIO_MEM_BASE (0x400F1000UL) /**< SDIO base address */ 239 #define SDIO_MEM_SIZE (0x1000UL) /**< SDIO available address space */ 240 #define SDIO_MEM_END (0x400F1FFFUL) /**< SDIO end address */ 241 #define SDIO_MEM_BITS (0x0000000CUL) /**< SDIO used bits */ 242 #define PER1_MEM_BASE (0x40050000UL) /**< PER1 base address */ 243 #define PER1_MEM_SIZE (0xA0000UL) /**< PER1 available address space */ 244 #define PER1_MEM_END (0x400EFFFFUL) /**< PER1 end address */ 245 #define PER1_MEM_BITS (0x00000014UL) /**< PER1 used bits */ 246 #define RAM0_MEM_BASE (0x20000000UL) /**< RAM0 base address */ 247 #define RAM0_MEM_SIZE (0x20000UL) /**< RAM0 available address space */ 248 #define RAM0_MEM_END (0x2001FFFFUL) /**< RAM0 end address */ 249 #define RAM0_MEM_BITS (0x00000011UL) /**< RAM0 used bits */ 250 #define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ 251 #define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ 252 #define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ 253 #define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ 254 #define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ 255 #define PER_BITSET_MEM_SIZE (0x50000UL) /**< PER_BITSET available address space */ 256 #define PER_BITSET_MEM_END (0x4604FFFFUL) /**< PER_BITSET end address */ 257 #define PER_BITSET_MEM_BITS (0x00000013UL) /**< PER_BITSET used bits */ 258 #define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ 259 #define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ 260 #define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ 261 #define EBI_CODE_MEM_BITS (0x0000001CUL) /**< EBI_CODE used bits */ 262 #define PER_MEM_BASE (0x40000000UL) /**< PER base address */ 263 #define PER_MEM_SIZE (0x50000UL) /**< PER available address space */ 264 #define PER_MEM_END (0x4004FFFFUL) /**< PER end address */ 265 #define PER_MEM_BITS (0x00000013UL) /**< PER used bits */ 266 #define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ 267 #define RAM2_CODE_MEM_SIZE (0x40000UL) /**< RAM2_CODE available address space */ 268 #define RAM2_CODE_MEM_END (0x1007FFFFUL) /**< RAM2_CODE end address */ 269 #define RAM2_CODE_MEM_BITS (0x00000012UL) /**< RAM2_CODE used bits */ 270 #define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ 271 #define PER_BITCLR_MEM_SIZE (0x50000UL) /**< PER_BITCLR available address space */ 272 #define PER_BITCLR_MEM_END (0x4404FFFFUL) /**< PER_BITCLR end address */ 273 #define PER_BITCLR_MEM_BITS (0x00000013UL) /**< PER_BITCLR used bits */ 274 275 /** Single RAM space macros combining both RAM ports to match legacy, single-RAM-port chips */ 276 #define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ 277 #define RAM_MEM_SIZE (0x80000UL) /**< RAM available address space */ 278 #define RAM_MEM_END (0x2007FFFFUL) /**< RAM end address */ 279 #define RAM_MEM_BITS (0x00000013UL) /**< RAM used bits */ 280 281 /** Bit banding area */ 282 #define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ 283 #define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ 284 285 /** Flash and SRAM limits for EFM32GG11B820F2048GL120 */ 286 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ 287 #define FLASH_SIZE (0x00200000UL) /**< Available Flash Memory */ 288 #define FLASH_PAGE_SIZE 4096U /**< Flash Memory page size (interleaving off) */ 289 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ 290 #define SRAM_SIZE (0x00080000UL) /**< Available SRAM Memory */ 291 #define __CM4_REV 0x0001U /**< Cortex-M4 Core revision r0p1 */ 292 #define PRS_CHAN_COUNT 24 /**< Number of PRS channels */ 293 #define DMA_CHAN_COUNT 24 /**< Number of DMA channels */ 294 #define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ 295 296 /** AF channels connect the different on-chip peripherals with the af-mux */ 297 #define AFCHAN_MAX 355U 298 /** AF channel maximum location number */ 299 #define AFCHANLOC_MAX 8U 300 /** Analog AF channels */ 301 #define AFACHAN_MAX 184U 302 303 /* Part number capabilities */ 304 305 #define CRYPTO_PRESENT /**< CRYPTO is available in this part */ 306 #define CRYPTO_COUNT 1 /**< 1 CRYPTOs available */ 307 #define CAN_PRESENT /**< CAN is available in this part */ 308 #define CAN_COUNT 2 /**< 2 CANs available */ 309 #define TIMER_PRESENT /**< TIMER is available in this part */ 310 #define TIMER_COUNT 7 /**< 7 TIMERs available */ 311 #define WTIMER_PRESENT /**< WTIMER is available in this part */ 312 #define WTIMER_COUNT 4 /**< 4 WTIMERs available */ 313 #define USART_PRESENT /**< USART is available in this part */ 314 #define USART_COUNT 6 /**< 6 USARTs available */ 315 #define UART_PRESENT /**< UART is available in this part */ 316 #define UART_COUNT 2 /**< 2 UARTs available */ 317 #define QSPI_PRESENT /**< QSPI is available in this part */ 318 #define QSPI_COUNT 1 /**< 1 QSPIs available */ 319 #define LEUART_PRESENT /**< LEUART is available in this part */ 320 #define LEUART_COUNT 2 /**< 2 LEUARTs available */ 321 #define LETIMER_PRESENT /**< LETIMER is available in this part */ 322 #define LETIMER_COUNT 2 /**< 2 LETIMERs available */ 323 #define PCNT_PRESENT /**< PCNT is available in this part */ 324 #define PCNT_COUNT 3 /**< 3 PCNTs available */ 325 #define I2C_PRESENT /**< I2C is available in this part */ 326 #define I2C_COUNT 3 /**< 3 I2Cs available */ 327 #define ADC_PRESENT /**< ADC is available in this part */ 328 #define ADC_COUNT 2 /**< 2 ADCs available */ 329 #define ACMP_PRESENT /**< ACMP is available in this part */ 330 #define ACMP_COUNT 4 /**< 4 ACMPs available */ 331 #define VDAC_PRESENT /**< VDAC is available in this part */ 332 #define VDAC_COUNT 1 /**< 1 VDACs available */ 333 #define IDAC_PRESENT /**< IDAC is available in this part */ 334 #define IDAC_COUNT 1 /**< 1 IDACs available */ 335 #define WDOG_PRESENT /**< WDOG is available in this part */ 336 #define WDOG_COUNT 2 /**< 2 WDOGs available */ 337 #define TRNG_PRESENT /**< TRNG is available in this part */ 338 #define TRNG_COUNT 1 /**< 1 TRNGs available */ 339 #define MSC_PRESENT /**< MSC is available in this part */ 340 #define MSC_COUNT 1 /**< 1 MSC available */ 341 #define EMU_PRESENT /**< EMU is available in this part */ 342 #define EMU_COUNT 1 /**< 1 EMU available */ 343 #define RMU_PRESENT /**< RMU is available in this part */ 344 #define RMU_COUNT 1 /**< 1 RMU available */ 345 #define CMU_PRESENT /**< CMU is available in this part */ 346 #define CMU_COUNT 1 /**< 1 CMU available */ 347 #define LESENSE_PRESENT /**< LESENSE is available in this part */ 348 #define LESENSE_COUNT 1 /**< 1 LESENSE available */ 349 #define EBI_PRESENT /**< EBI is available in this part */ 350 #define EBI_COUNT 1 /**< 1 EBI available */ 351 #define ETH_PRESENT /**< ETH is available in this part */ 352 #define ETH_COUNT 1 /**< 1 ETH available */ 353 #define SDIO_PRESENT /**< SDIO is available in this part */ 354 #define SDIO_COUNT 1 /**< 1 SDIO available */ 355 #define GPIO_PRESENT /**< GPIO is available in this part */ 356 #define GPIO_COUNT 1 /**< 1 GPIO available */ 357 #define PRS_PRESENT /**< PRS is available in this part */ 358 #define PRS_COUNT 1 /**< 1 PRS available */ 359 #define LDMA_PRESENT /**< LDMA is available in this part */ 360 #define LDMA_COUNT 1 /**< 1 LDMA available */ 361 #define FPUEH_PRESENT /**< FPUEH is available in this part */ 362 #define FPUEH_COUNT 1 /**< 1 FPUEH available */ 363 #define GPCRC_PRESENT /**< GPCRC is available in this part */ 364 #define GPCRC_COUNT 1 /**< 1 GPCRC available */ 365 #define CRYOTIMER_PRESENT /**< CRYOTIMER is available in this part */ 366 #define CRYOTIMER_COUNT 1 /**< 1 CRYOTIMER available */ 367 #define USB_PRESENT /**< USB is available in this part */ 368 #define USB_COUNT 1 /**< 1 USB available */ 369 #define BU_PRESENT /**< BU is available in this part */ 370 #define BU_COUNT 1 /**< 1 BU available */ 371 #define CSEN_PRESENT /**< CSEN is available in this part */ 372 #define CSEN_COUNT 1 /**< 1 CSEN available */ 373 #define LCD_PRESENT /**< LCD is available in this part */ 374 #define LCD_COUNT 1 /**< 1 LCD available */ 375 #define RTC_PRESENT /**< RTC is available in this part */ 376 #define RTC_COUNT 1 /**< 1 RTC available */ 377 #define RTCC_PRESENT /**< RTCC is available in this part */ 378 #define RTCC_COUNT 1 /**< 1 RTCC available */ 379 #define ETM_PRESENT /**< ETM is available in this part */ 380 #define ETM_COUNT 1 /**< 1 ETM available */ 381 #define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */ 382 #define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */ 383 #define SMU_PRESENT /**< SMU is available in this part */ 384 #define SMU_COUNT 1 /**< 1 SMU available */ 385 #define DCDC_PRESENT /**< DCDC is available in this part */ 386 #define DCDC_COUNT 1 /**< 1 DCDC available */ 387 388 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 389 #include "system_efm32gg11b.h" /* System Header File */ 390 391 /** @} End of group EFM32GG11B820F2048GL120_Part */ 392 393 /***************************************************************************//** 394 * @defgroup EFM32GG11B820F2048GL120_Peripheral_TypeDefs Peripheral TypeDefs 395 * @{ 396 * @brief Device Specific Peripheral Register Structures 397 ******************************************************************************/ 398 399 #include "efm32gg11b_msc.h" 400 #include "efm32gg11b_emu.h" 401 #include "efm32gg11b_rmu.h" 402 #include "efm32gg11b_cmu.h" 403 #include "efm32gg11b_crypto.h" 404 #include "efm32gg11b_lesense_st.h" 405 #include "efm32gg11b_lesense_buf.h" 406 #include "efm32gg11b_lesense_ch.h" 407 #include "efm32gg11b_lesense.h" 408 #include "efm32gg11b_ebi.h" 409 #include "efm32gg11b_eth.h" 410 #include "efm32gg11b_sdio.h" 411 #include "efm32gg11b_gpio_p.h" 412 #include "efm32gg11b_gpio.h" 413 #include "efm32gg11b_prs_ch.h" 414 #include "efm32gg11b_prs.h" 415 #include "efm32gg11b_ldma_ch.h" 416 #include "efm32gg11b_ldma.h" 417 #include "efm32gg11b_fpueh.h" 418 #include "efm32gg11b_gpcrc.h" 419 #include "efm32gg11b_can_mir.h" 420 #include "efm32gg11b_can.h" 421 #include "efm32gg11b_timer_cc.h" 422 #include "efm32gg11b_timer.h" 423 #include "efm32gg11b_usart.h" 424 #include "efm32gg11b_qspi.h" 425 #include "efm32gg11b_leuart.h" 426 #include "efm32gg11b_letimer.h" 427 #include "efm32gg11b_cryotimer.h" 428 #include "efm32gg11b_pcnt.h" 429 #include "efm32gg11b_i2c.h" 430 #include "efm32gg11b_adc.h" 431 #include "efm32gg11b_acmp.h" 432 #include "efm32gg11b_vdac_opa.h" 433 #include "efm32gg11b_vdac.h" 434 #include "efm32gg11b_usb_hc.h" 435 #include "efm32gg11b_usb_diep.h" 436 #include "efm32gg11b_usb_doep.h" 437 #include "efm32gg11b_usb.h" 438 #include "efm32gg11b_idac.h" 439 #include "efm32gg11b_csen.h" 440 #include "efm32gg11b_lcd.h" 441 #include "efm32gg11b_rtc_comp.h" 442 #include "efm32gg11b_rtc.h" 443 #include "efm32gg11b_rtcc_cc.h" 444 #include "efm32gg11b_rtcc_ret.h" 445 #include "efm32gg11b_rtcc.h" 446 #include "efm32gg11b_wdog_pch.h" 447 #include "efm32gg11b_wdog.h" 448 #include "efm32gg11b_etm.h" 449 #include "efm32gg11b_smu.h" 450 #include "efm32gg11b_trng.h" 451 #include "efm32gg11b_dma_descriptor.h" 452 #include "efm32gg11b_devinfo.h" 453 #include "efm32gg11b_romtable.h" 454 455 /** @} End of group EFM32GG11B820F2048GL120_Peripheral_TypeDefs */ 456 457 /***************************************************************************//** 458 * @defgroup EFM32GG11B820F2048GL120_Peripheral_Base Peripheral Memory Map 459 * @{ 460 ******************************************************************************/ 461 462 #define MSC_BASE (0x40000000UL) /**< MSC base address */ 463 #define EMU_BASE (0x400E3000UL) /**< EMU base address */ 464 #define RMU_BASE (0x400E5000UL) /**< RMU base address */ 465 #define CMU_BASE (0x400E4000UL) /**< CMU base address */ 466 #define CRYPTO0_BASE (0x400F0000UL) /**< CRYPTO0 base address */ 467 #define LESENSE_BASE (0x40055000UL) /**< LESENSE base address */ 468 #define EBI_BASE (0x4000B000UL) /**< EBI base address */ 469 #define ETH_BASE (0x40024000UL) /**< ETH base address */ 470 #define SDIO_BASE (0x400F1000UL) /**< SDIO base address */ 471 #define GPIO_BASE (0x40088000UL) /**< GPIO base address */ 472 #define PRS_BASE (0x400E6000UL) /**< PRS base address */ 473 #define LDMA_BASE (0x40002000UL) /**< LDMA base address */ 474 #define FPUEH_BASE (0x40001000UL) /**< FPUEH base address */ 475 #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ 476 #define CAN0_BASE (0x40004000UL) /**< CAN0 base address */ 477 #define CAN1_BASE (0x40004400UL) /**< CAN1 base address */ 478 #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ 479 #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ 480 #define TIMER2_BASE (0x40018800UL) /**< TIMER2 base address */ 481 #define TIMER3_BASE (0x40018C00UL) /**< TIMER3 base address */ 482 #define TIMER4_BASE (0x40019000UL) /**< TIMER4 base address */ 483 #define TIMER5_BASE (0x40019400UL) /**< TIMER5 base address */ 484 #define TIMER6_BASE (0x40019800UL) /**< TIMER6 base address */ 485 #define WTIMER0_BASE (0x4001A000UL) /**< WTIMER0 base address */ 486 #define WTIMER1_BASE (0x4001A400UL) /**< WTIMER1 base address */ 487 #define WTIMER2_BASE (0x4001A800UL) /**< WTIMER2 base address */ 488 #define WTIMER3_BASE (0x4001AC00UL) /**< WTIMER3 base address */ 489 #define USART0_BASE (0x40010000UL) /**< USART0 base address */ 490 #define USART1_BASE (0x40010400UL) /**< USART1 base address */ 491 #define USART2_BASE (0x40010800UL) /**< USART2 base address */ 492 #define USART3_BASE (0x40010C00UL) /**< USART3 base address */ 493 #define USART4_BASE (0x40011000UL) /**< USART4 base address */ 494 #define USART5_BASE (0x40011400UL) /**< USART5 base address */ 495 #define UART0_BASE (0x40014000UL) /**< UART0 base address */ 496 #define UART1_BASE (0x40014400UL) /**< UART1 base address */ 497 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ 498 #define LEUART0_BASE (0x4006A000UL) /**< LEUART0 base address */ 499 #define LEUART1_BASE (0x4006A400UL) /**< LEUART1 base address */ 500 #define LETIMER0_BASE (0x40066000UL) /**< LETIMER0 base address */ 501 #define LETIMER1_BASE (0x40066400UL) /**< LETIMER1 base address */ 502 #define CRYOTIMER_BASE (0x4008F000UL) /**< CRYOTIMER base address */ 503 #define PCNT0_BASE (0x4006E000UL) /**< PCNT0 base address */ 504 #define PCNT1_BASE (0x4006E400UL) /**< PCNT1 base address */ 505 #define PCNT2_BASE (0x4006E800UL) /**< PCNT2 base address */ 506 #define I2C0_BASE (0x40089000UL) /**< I2C0 base address */ 507 #define I2C1_BASE (0x40089400UL) /**< I2C1 base address */ 508 #define I2C2_BASE (0x40089800UL) /**< I2C2 base address */ 509 #define ADC0_BASE (0x40082000UL) /**< ADC0 base address */ 510 #define ADC1_BASE (0x40082400UL) /**< ADC1 base address */ 511 #define ACMP0_BASE (0x40080000UL) /**< ACMP0 base address */ 512 #define ACMP1_BASE (0x40080400UL) /**< ACMP1 base address */ 513 #define ACMP2_BASE (0x40080800UL) /**< ACMP2 base address */ 514 #define ACMP3_BASE (0x40080C00UL) /**< ACMP3 base address */ 515 #define VDAC0_BASE (0x40086000UL) /**< VDAC0 base address */ 516 #define USB_BASE (0x40022000UL) /**< USB base address */ 517 #define IDAC0_BASE (0x40084000UL) /**< IDAC0 base address */ 518 #define CSEN_BASE (0x4008E000UL) /**< CSEN base address */ 519 #define LCD_BASE (0x40054000UL) /**< LCD base address */ 520 #define RTC_BASE (0x40060000UL) /**< RTC base address */ 521 #define RTCC_BASE (0x40062000UL) /**< RTCC base address */ 522 #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ 523 #define WDOG1_BASE (0x40052400UL) /**< WDOG1 base address */ 524 #define ETM_BASE (0xE0041000UL) /**< ETM base address */ 525 #define SMU_BASE (0x40020000UL) /**< SMU base address */ 526 #define TRNG0_BASE (0x4001D000UL) /**< TRNG0 base address */ 527 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ 528 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ 529 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ 530 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ 531 532 /** @} End of group EFM32GG11B820F2048GL120_Peripheral_Base */ 533 534 /***************************************************************************//** 535 * @defgroup EFM32GG11B820F2048GL120_Peripheral_Declaration Peripheral Declarations 536 * @{ 537 ******************************************************************************/ 538 539 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ 540 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ 541 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ 542 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ 543 #define CRYPTO0 ((CRYPTO_TypeDef *) CRYPTO0_BASE) /**< CRYPTO0 base pointer */ 544 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ 545 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */ 546 #define ETH ((ETH_TypeDef *) ETH_BASE) /**< ETH base pointer */ 547 #define SDIO ((SDIO_TypeDef *) SDIO_BASE) /**< SDIO base pointer */ 548 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ 549 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ 550 #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ 551 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ 552 #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ 553 #define CAN0 ((CAN_TypeDef *) CAN0_BASE) /**< CAN0 base pointer */ 554 #define CAN1 ((CAN_TypeDef *) CAN1_BASE) /**< CAN1 base pointer */ 555 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ 556 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ 557 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ 558 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ 559 #define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ 560 #define TIMER5 ((TIMER_TypeDef *) TIMER5_BASE) /**< TIMER5 base pointer */ 561 #define TIMER6 ((TIMER_TypeDef *) TIMER6_BASE) /**< TIMER6 base pointer */ 562 #define WTIMER0 ((TIMER_TypeDef *) WTIMER0_BASE) /**< WTIMER0 base pointer */ 563 #define WTIMER1 ((TIMER_TypeDef *) WTIMER1_BASE) /**< WTIMER1 base pointer */ 564 #define WTIMER2 ((TIMER_TypeDef *) WTIMER2_BASE) /**< WTIMER2 base pointer */ 565 #define WTIMER3 ((TIMER_TypeDef *) WTIMER3_BASE) /**< WTIMER3 base pointer */ 566 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ 567 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ 568 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */ 569 #define USART3 ((USART_TypeDef *) USART3_BASE) /**< USART3 base pointer */ 570 #define USART4 ((USART_TypeDef *) USART4_BASE) /**< USART4 base pointer */ 571 #define USART5 ((USART_TypeDef *) USART5_BASE) /**< USART5 base pointer */ 572 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */ 573 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */ 574 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */ 575 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ 576 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */ 577 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ 578 #define LETIMER1 ((LETIMER_TypeDef *) LETIMER1_BASE) /**< LETIMER1 base pointer */ 579 #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ 580 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ 581 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */ 582 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */ 583 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ 584 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ 585 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) /**< I2C2 base pointer */ 586 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ 587 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) /**< ADC1 base pointer */ 588 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ 589 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ 590 #define ACMP2 ((ACMP_TypeDef *) ACMP2_BASE) /**< ACMP2 base pointer */ 591 #define ACMP3 ((ACMP_TypeDef *) ACMP3_BASE) /**< ACMP3 base pointer */ 592 #define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ 593 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */ 594 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ 595 #define CSEN ((CSEN_TypeDef *) CSEN_BASE) /**< CSEN base pointer */ 596 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ 597 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */ 598 #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ 599 #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ 600 #define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ 601 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */ 602 #define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ 603 #define TRNG0 ((TRNG_TypeDef *) TRNG0_BASE) /**< TRNG0 base pointer */ 604 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ 605 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ 606 607 /** @} End of group EFM32GG11B820F2048GL120_Peripheral_Declaration */ 608 609 /***************************************************************************//** 610 * @defgroup EFM32GG11B820F2048GL120_Peripheral_Offsets Peripheral Offsets 611 * @{ 612 ******************************************************************************/ 613 614 #define CRYPTO_OFFSET 0x400 /**< Offset in bytes between CRYPTO instances */ 615 #define CAN_OFFSET 0x400 /**< Offset in bytes between CAN instances */ 616 #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ 617 #define WTIMER_OFFSET 0x400 /**< Offset in bytes between WTIMER instances */ 618 #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ 619 #define UART_OFFSET 0x400 /**< Offset in bytes between UART instances */ 620 #define QSPI_OFFSET 0x400 /**< Offset in bytes between QSPI instances */ 621 #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ 622 #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ 623 #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ 624 #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ 625 #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ 626 #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ 627 #define VDAC_OFFSET 0x400 /**< Offset in bytes between VDAC instances */ 628 #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ 629 #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ 630 #define TRNG_OFFSET 0x400 /**< Offset in bytes between TRNG instances */ 631 632 /** @} End of group EFM32GG11B820F2048GL120_Peripheral_Offsets */ 633 634 /***************************************************************************//** 635 * @defgroup EFM32GG11B820F2048GL120_BitFields Bit Fields 636 * @{ 637 ******************************************************************************/ 638 639 #include "efm32gg11b_prs_signals.h" 640 #include "efm32gg11b_dmareq.h" 641 642 /***************************************************************************//** 643 * @addtogroup EFM32GG11B820F2048GL120_WTIMER 644 * @{ 645 * @defgroup EFM32GG11B820F2048GL120_WTIMER_BitFields WTIMER Bit Fields 646 * @{ 647 ******************************************************************************/ 648 649 /* Bit fields for WTIMER CTRL */ 650 #define _WTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CTRL */ 651 #define _WTIMER_CTRL_MASK 0x3F036FFBUL /**< Mask for WTIMER_CTRL */ 652 #define _WTIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ 653 #define _WTIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ 654 #define _WTIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 655 #define _WTIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for WTIMER_CTRL */ 656 #define _WTIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_CTRL */ 657 #define _WTIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for WTIMER_CTRL */ 658 #define _WTIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for WTIMER_CTRL */ 659 #define WTIMER_CTRL_MODE_DEFAULT (_WTIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 660 #define WTIMER_CTRL_MODE_UP (_WTIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for WTIMER_CTRL */ 661 #define WTIMER_CTRL_MODE_DOWN (_WTIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for WTIMER_CTRL */ 662 #define WTIMER_CTRL_MODE_UPDOWN (_WTIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for WTIMER_CTRL */ 663 #define WTIMER_CTRL_MODE_QDEC (_WTIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for WTIMER_CTRL */ 664 #define WTIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ 665 #define _WTIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ 666 #define _WTIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ 667 #define _WTIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 668 #define WTIMER_CTRL_SYNC_DEFAULT (_WTIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 669 #define WTIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ 670 #define _WTIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ 671 #define _WTIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ 672 #define _WTIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 673 #define WTIMER_CTRL_OSMEN_DEFAULT (_WTIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 674 #define WTIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ 675 #define _WTIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ 676 #define _WTIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ 677 #define _WTIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 678 #define _WTIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for WTIMER_CTRL */ 679 #define _WTIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for WTIMER_CTRL */ 680 #define WTIMER_CTRL_QDM_DEFAULT (_WTIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 681 #define WTIMER_CTRL_QDM_X2 (_WTIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for WTIMER_CTRL */ 682 #define WTIMER_CTRL_QDM_X4 (_WTIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for WTIMER_CTRL */ 683 #define WTIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ 684 #define _WTIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ 685 #define _WTIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ 686 #define _WTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 687 #define WTIMER_CTRL_DEBUGRUN_DEFAULT (_WTIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 688 #define WTIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ 689 #define _WTIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ 690 #define _WTIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ 691 #define _WTIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 692 #define WTIMER_CTRL_DMACLRACT_DEFAULT (_WTIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 693 #define _WTIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */ 694 #define _WTIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */ 695 #define _WTIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 696 #define _WTIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ 697 #define _WTIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ 698 #define _WTIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ 699 #define _WTIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ 700 #define WTIMER_CTRL_RISEA_DEFAULT (_WTIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 701 #define WTIMER_CTRL_RISEA_NONE (_WTIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for WTIMER_CTRL */ 702 #define WTIMER_CTRL_RISEA_START (_WTIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for WTIMER_CTRL */ 703 #define WTIMER_CTRL_RISEA_STOP (_WTIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for WTIMER_CTRL */ 704 #define WTIMER_CTRL_RISEA_RELOADSTART (_WTIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ 705 #define _WTIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */ 706 #define _WTIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */ 707 #define _WTIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 708 #define _WTIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CTRL */ 709 #define _WTIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for WTIMER_CTRL */ 710 #define _WTIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for WTIMER_CTRL */ 711 #define _WTIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for WTIMER_CTRL */ 712 #define WTIMER_CTRL_FALLA_DEFAULT (_WTIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 713 #define WTIMER_CTRL_FALLA_NONE (_WTIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for WTIMER_CTRL */ 714 #define WTIMER_CTRL_FALLA_START (_WTIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for WTIMER_CTRL */ 715 #define WTIMER_CTRL_FALLA_STOP (_WTIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for WTIMER_CTRL */ 716 #define WTIMER_CTRL_FALLA_RELOADSTART (_WTIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for WTIMER_CTRL */ 717 #define WTIMER_CTRL_X2CNT (0x1UL << 13) /**< 2x Count Mode */ 718 #define _WTIMER_CTRL_X2CNT_SHIFT 13 /**< Shift value for TIMER_X2CNT */ 719 #define _WTIMER_CTRL_X2CNT_MASK 0x2000UL /**< Bit mask for TIMER_X2CNT */ 720 #define _WTIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 721 #define WTIMER_CTRL_X2CNT_DEFAULT (_WTIMER_CTRL_X2CNT_DEFAULT << 13) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 722 #define WTIMER_CTRL_DISSYNCOUT (0x1UL << 14) /**< Disable Timer From Start/Stop/Reload Other Synchronized Timers */ 723 #define _WTIMER_CTRL_DISSYNCOUT_SHIFT 14 /**< Shift value for TIMER_DISSYNCOUT */ 724 #define _WTIMER_CTRL_DISSYNCOUT_MASK 0x4000UL /**< Bit mask for TIMER_DISSYNCOUT */ 725 #define _WTIMER_CTRL_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 726 #define WTIMER_CTRL_DISSYNCOUT_DEFAULT (_WTIMER_CTRL_DISSYNCOUT_DEFAULT << 14) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 727 #define _WTIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */ 728 #define _WTIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */ 729 #define _WTIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 730 #define _WTIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for WTIMER_CTRL */ 731 #define _WTIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for WTIMER_CTRL */ 732 #define _WTIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for WTIMER_CTRL */ 733 #define WTIMER_CTRL_CLKSEL_DEFAULT (_WTIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 734 #define WTIMER_CTRL_CLKSEL_PRESCHFPERCLK (_WTIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for WTIMER_CTRL */ 735 #define WTIMER_CTRL_CLKSEL_CC1 (_WTIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for WTIMER_CTRL */ 736 #define WTIMER_CTRL_CLKSEL_TIMEROUF (_WTIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for WTIMER_CTRL */ 737 #define _WTIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */ 738 #define _WTIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */ 739 #define _WTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 740 #define _WTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_CTRL */ 741 #define _WTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_CTRL */ 742 #define _WTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_CTRL */ 743 #define _WTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_CTRL */ 744 #define _WTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_CTRL */ 745 #define _WTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_CTRL */ 746 #define _WTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_CTRL */ 747 #define _WTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_CTRL */ 748 #define _WTIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_CTRL */ 749 #define _WTIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_CTRL */ 750 #define _WTIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_CTRL */ 751 #define WTIMER_CTRL_PRESC_DEFAULT (_WTIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 752 #define WTIMER_CTRL_PRESC_DIV1 (_WTIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for WTIMER_CTRL */ 753 #define WTIMER_CTRL_PRESC_DIV2 (_WTIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for WTIMER_CTRL */ 754 #define WTIMER_CTRL_PRESC_DIV4 (_WTIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for WTIMER_CTRL */ 755 #define WTIMER_CTRL_PRESC_DIV8 (_WTIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for WTIMER_CTRL */ 756 #define WTIMER_CTRL_PRESC_DIV16 (_WTIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for WTIMER_CTRL */ 757 #define WTIMER_CTRL_PRESC_DIV32 (_WTIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for WTIMER_CTRL */ 758 #define WTIMER_CTRL_PRESC_DIV64 (_WTIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for WTIMER_CTRL */ 759 #define WTIMER_CTRL_PRESC_DIV128 (_WTIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for WTIMER_CTRL */ 760 #define WTIMER_CTRL_PRESC_DIV256 (_WTIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for WTIMER_CTRL */ 761 #define WTIMER_CTRL_PRESC_DIV512 (_WTIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for WTIMER_CTRL */ 762 #define WTIMER_CTRL_PRESC_DIV1024 (_WTIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for WTIMER_CTRL */ 763 #define WTIMER_CTRL_ATI (0x1UL << 28) /**< Always Track Inputs */ 764 #define _WTIMER_CTRL_ATI_SHIFT 28 /**< Shift value for TIMER_ATI */ 765 #define _WTIMER_CTRL_ATI_MASK 0x10000000UL /**< Bit mask for TIMER_ATI */ 766 #define _WTIMER_CTRL_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 767 #define WTIMER_CTRL_ATI_DEFAULT (_WTIMER_CTRL_ATI_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 768 #define WTIMER_CTRL_RSSCOIST (0x1UL << 29) /**< Reload-Start Sets Compare Output Initial State */ 769 #define _WTIMER_CTRL_RSSCOIST_SHIFT 29 /**< Shift value for TIMER_RSSCOIST */ 770 #define _WTIMER_CTRL_RSSCOIST_MASK 0x20000000UL /**< Bit mask for TIMER_RSSCOIST */ 771 #define _WTIMER_CTRL_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CTRL */ 772 #define WTIMER_CTRL_RSSCOIST_DEFAULT (_WTIMER_CTRL_RSSCOIST_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CTRL */ 773 774 /* Bit fields for WTIMER CMD */ 775 #define _WTIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CMD */ 776 #define _WTIMER_CMD_MASK 0x00000003UL /**< Mask for WTIMER_CMD */ 777 #define WTIMER_CMD_START (0x1UL << 0) /**< Start Timer */ 778 #define _WTIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ 779 #define _WTIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ 780 #define _WTIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ 781 #define WTIMER_CMD_START_DEFAULT (_WTIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CMD */ 782 #define WTIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ 783 #define _WTIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ 784 #define _WTIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ 785 #define _WTIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CMD */ 786 #define WTIMER_CMD_STOP_DEFAULT (_WTIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_CMD */ 787 788 /* Bit fields for WTIMER STATUS */ 789 #define _WTIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_STATUS */ 790 #define _WTIMER_STATUS_MASK 0x0F0F0F07UL /**< Mask for WTIMER_STATUS */ 791 #define WTIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ 792 #define _WTIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ 793 #define _WTIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ 794 #define _WTIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 795 #define WTIMER_STATUS_RUNNING_DEFAULT (_WTIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 796 #define WTIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ 797 #define _WTIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ 798 #define _WTIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ 799 #define _WTIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 800 #define _WTIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for WTIMER_STATUS */ 801 #define _WTIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for WTIMER_STATUS */ 802 #define WTIMER_STATUS_DIR_DEFAULT (_WTIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 803 #define WTIMER_STATUS_DIR_UP (_WTIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for WTIMER_STATUS */ 804 #define WTIMER_STATUS_DIR_DOWN (_WTIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for WTIMER_STATUS */ 805 #define WTIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */ 806 #define _WTIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ 807 #define _WTIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ 808 #define _WTIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 809 #define WTIMER_STATUS_TOPBV_DEFAULT (_WTIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 810 #define WTIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */ 811 #define _WTIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */ 812 #define _WTIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */ 813 #define _WTIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 814 #define WTIMER_STATUS_CCVBV0_DEFAULT (_WTIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 815 #define WTIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */ 816 #define _WTIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */ 817 #define _WTIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */ 818 #define _WTIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 819 #define WTIMER_STATUS_CCVBV1_DEFAULT (_WTIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 820 #define WTIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */ 821 #define _WTIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */ 822 #define _WTIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */ 823 #define _WTIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 824 #define WTIMER_STATUS_CCVBV2_DEFAULT (_WTIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 825 #define WTIMER_STATUS_CCVBV3 (0x1UL << 11) /**< CC3 CCVB Valid */ 826 #define _WTIMER_STATUS_CCVBV3_SHIFT 11 /**< Shift value for TIMER_CCVBV3 */ 827 #define _WTIMER_STATUS_CCVBV3_MASK 0x800UL /**< Bit mask for TIMER_CCVBV3 */ 828 #define _WTIMER_STATUS_CCVBV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 829 #define WTIMER_STATUS_CCVBV3_DEFAULT (_WTIMER_STATUS_CCVBV3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 830 #define WTIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */ 831 #define _WTIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */ 832 #define _WTIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */ 833 #define _WTIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 834 #define WTIMER_STATUS_ICV0_DEFAULT (_WTIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 835 #define WTIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */ 836 #define _WTIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */ 837 #define _WTIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */ 838 #define _WTIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 839 #define WTIMER_STATUS_ICV1_DEFAULT (_WTIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 840 #define WTIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */ 841 #define _WTIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */ 842 #define _WTIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */ 843 #define _WTIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 844 #define WTIMER_STATUS_ICV2_DEFAULT (_WTIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 845 #define WTIMER_STATUS_ICV3 (0x1UL << 19) /**< CC3 Input Capture Valid */ 846 #define _WTIMER_STATUS_ICV3_SHIFT 19 /**< Shift value for TIMER_ICV3 */ 847 #define _WTIMER_STATUS_ICV3_MASK 0x80000UL /**< Bit mask for TIMER_ICV3 */ 848 #define _WTIMER_STATUS_ICV3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 849 #define WTIMER_STATUS_ICV3_DEFAULT (_WTIMER_STATUS_ICV3_DEFAULT << 19) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 850 #define WTIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */ 851 #define _WTIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ 852 #define _WTIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ 853 #define _WTIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 854 #define _WTIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ 855 #define _WTIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ 856 #define WTIMER_STATUS_CCPOL0_DEFAULT (_WTIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 857 #define WTIMER_STATUS_CCPOL0_LOWRISE (_WTIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for WTIMER_STATUS */ 858 #define WTIMER_STATUS_CCPOL0_HIGHFALL (_WTIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ 859 #define WTIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */ 860 #define _WTIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ 861 #define _WTIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ 862 #define _WTIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 863 #define _WTIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ 864 #define _WTIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ 865 #define WTIMER_STATUS_CCPOL1_DEFAULT (_WTIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 866 #define WTIMER_STATUS_CCPOL1_LOWRISE (_WTIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for WTIMER_STATUS */ 867 #define WTIMER_STATUS_CCPOL1_HIGHFALL (_WTIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ 868 #define WTIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */ 869 #define _WTIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ 870 #define _WTIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ 871 #define _WTIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 872 #define _WTIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ 873 #define _WTIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ 874 #define WTIMER_STATUS_CCPOL2_DEFAULT (_WTIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 875 #define WTIMER_STATUS_CCPOL2_LOWRISE (_WTIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for WTIMER_STATUS */ 876 #define WTIMER_STATUS_CCPOL2_HIGHFALL (_WTIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ 877 #define WTIMER_STATUS_CCPOL3 (0x1UL << 27) /**< CC3 Polarity */ 878 #define _WTIMER_STATUS_CCPOL3_SHIFT 27 /**< Shift value for TIMER_CCPOL3 */ 879 #define _WTIMER_STATUS_CCPOL3_MASK 0x8000000UL /**< Bit mask for TIMER_CCPOL3 */ 880 #define _WTIMER_STATUS_CCPOL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_STATUS */ 881 #define _WTIMER_STATUS_CCPOL3_LOWRISE 0x00000000UL /**< Mode LOWRISE for WTIMER_STATUS */ 882 #define _WTIMER_STATUS_CCPOL3_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for WTIMER_STATUS */ 883 #define WTIMER_STATUS_CCPOL3_DEFAULT (_WTIMER_STATUS_CCPOL3_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_STATUS */ 884 #define WTIMER_STATUS_CCPOL3_LOWRISE (_WTIMER_STATUS_CCPOL3_LOWRISE << 27) /**< Shifted mode LOWRISE for WTIMER_STATUS */ 885 #define WTIMER_STATUS_CCPOL3_HIGHFALL (_WTIMER_STATUS_CCPOL3_HIGHFALL << 27) /**< Shifted mode HIGHFALL for WTIMER_STATUS */ 886 887 /* Bit fields for WTIMER IF */ 888 #define _WTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IF */ 889 #define _WTIMER_IF_MASK 0x00000FF7UL /**< Mask for WTIMER_IF */ 890 #define WTIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ 891 #define _WTIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ 892 #define _WTIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ 893 #define _WTIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 894 #define WTIMER_IF_OF_DEFAULT (_WTIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IF */ 895 #define WTIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ 896 #define _WTIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ 897 #define _WTIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ 898 #define _WTIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 899 #define WTIMER_IF_UF_DEFAULT (_WTIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IF */ 900 #define WTIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ 901 #define _WTIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ 902 #define _WTIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ 903 #define _WTIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 904 #define WTIMER_IF_DIRCHG_DEFAULT (_WTIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IF */ 905 #define WTIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */ 906 #define _WTIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ 907 #define _WTIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ 908 #define _WTIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 909 #define WTIMER_IF_CC0_DEFAULT (_WTIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IF */ 910 #define WTIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */ 911 #define _WTIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ 912 #define _WTIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ 913 #define _WTIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 914 #define WTIMER_IF_CC1_DEFAULT (_WTIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IF */ 915 #define WTIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */ 916 #define _WTIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ 917 #define _WTIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ 918 #define _WTIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 919 #define WTIMER_IF_CC2_DEFAULT (_WTIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IF */ 920 #define WTIMER_IF_CC3 (0x1UL << 7) /**< CC Channel 3 Interrupt Flag */ 921 #define _WTIMER_IF_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ 922 #define _WTIMER_IF_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ 923 #define _WTIMER_IF_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 924 #define WTIMER_IF_CC3_DEFAULT (_WTIMER_IF_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IF */ 925 #define WTIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */ 926 #define _WTIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ 927 #define _WTIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ 928 #define _WTIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 929 #define WTIMER_IF_ICBOF0_DEFAULT (_WTIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IF */ 930 #define WTIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */ 931 #define _WTIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ 932 #define _WTIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ 933 #define _WTIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 934 #define WTIMER_IF_ICBOF1_DEFAULT (_WTIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IF */ 935 #define WTIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */ 936 #define _WTIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ 937 #define _WTIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ 938 #define _WTIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 939 #define WTIMER_IF_ICBOF2_DEFAULT (_WTIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IF */ 940 #define WTIMER_IF_ICBOF3 (0x1UL << 11) /**< CC Channel 3 Input Capture Buffer Overflow Interrupt Flag */ 941 #define _WTIMER_IF_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ 942 #define _WTIMER_IF_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ 943 #define _WTIMER_IF_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IF */ 944 #define WTIMER_IF_ICBOF3_DEFAULT (_WTIMER_IF_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IF */ 945 946 /* Bit fields for WTIMER IFS */ 947 #define _WTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFS */ 948 #define _WTIMER_IFS_MASK 0x00000FF7UL /**< Mask for WTIMER_IFS */ 949 #define WTIMER_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ 950 #define _WTIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */ 951 #define _WTIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ 952 #define _WTIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 953 #define WTIMER_IFS_OF_DEFAULT (_WTIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFS */ 954 #define WTIMER_IFS_UF (0x1UL << 1) /**< Set UF Interrupt Flag */ 955 #define _WTIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */ 956 #define _WTIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ 957 #define _WTIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 958 #define WTIMER_IFS_UF_DEFAULT (_WTIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFS */ 959 #define WTIMER_IFS_DIRCHG (0x1UL << 2) /**< Set DIRCHG Interrupt Flag */ 960 #define _WTIMER_IFS_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ 961 #define _WTIMER_IFS_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ 962 #define _WTIMER_IFS_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 963 #define WTIMER_IFS_DIRCHG_DEFAULT (_WTIMER_IFS_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFS */ 964 #define WTIMER_IFS_CC0 (0x1UL << 4) /**< Set CC0 Interrupt Flag */ 965 #define _WTIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ 966 #define _WTIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ 967 #define _WTIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 968 #define WTIMER_IFS_CC0_DEFAULT (_WTIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFS */ 969 #define WTIMER_IFS_CC1 (0x1UL << 5) /**< Set CC1 Interrupt Flag */ 970 #define _WTIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ 971 #define _WTIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ 972 #define _WTIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 973 #define WTIMER_IFS_CC1_DEFAULT (_WTIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFS */ 974 #define WTIMER_IFS_CC2 (0x1UL << 6) /**< Set CC2 Interrupt Flag */ 975 #define _WTIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ 976 #define _WTIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ 977 #define _WTIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 978 #define WTIMER_IFS_CC2_DEFAULT (_WTIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFS */ 979 #define WTIMER_IFS_CC3 (0x1UL << 7) /**< Set CC3 Interrupt Flag */ 980 #define _WTIMER_IFS_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ 981 #define _WTIMER_IFS_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ 982 #define _WTIMER_IFS_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 983 #define WTIMER_IFS_CC3_DEFAULT (_WTIMER_IFS_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFS */ 984 #define WTIMER_IFS_ICBOF0 (0x1UL << 8) /**< Set ICBOF0 Interrupt Flag */ 985 #define _WTIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ 986 #define _WTIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ 987 #define _WTIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 988 #define WTIMER_IFS_ICBOF0_DEFAULT (_WTIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFS */ 989 #define WTIMER_IFS_ICBOF1 (0x1UL << 9) /**< Set ICBOF1 Interrupt Flag */ 990 #define _WTIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ 991 #define _WTIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ 992 #define _WTIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 993 #define WTIMER_IFS_ICBOF1_DEFAULT (_WTIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFS */ 994 #define WTIMER_IFS_ICBOF2 (0x1UL << 10) /**< Set ICBOF2 Interrupt Flag */ 995 #define _WTIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ 996 #define _WTIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ 997 #define _WTIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 998 #define WTIMER_IFS_ICBOF2_DEFAULT (_WTIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFS */ 999 #define WTIMER_IFS_ICBOF3 (0x1UL << 11) /**< Set ICBOF3 Interrupt Flag */ 1000 #define _WTIMER_IFS_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ 1001 #define _WTIMER_IFS_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ 1002 #define _WTIMER_IFS_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFS */ 1003 #define WTIMER_IFS_ICBOF3_DEFAULT (_WTIMER_IFS_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFS */ 1004 1005 /* Bit fields for WTIMER IFC */ 1006 #define _WTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IFC */ 1007 #define _WTIMER_IFC_MASK 0x00000FF7UL /**< Mask for WTIMER_IFC */ 1008 #define WTIMER_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ 1009 #define _WTIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */ 1010 #define _WTIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ 1011 #define _WTIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1012 #define WTIMER_IFC_OF_DEFAULT (_WTIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1013 #define WTIMER_IFC_UF (0x1UL << 1) /**< Clear UF Interrupt Flag */ 1014 #define _WTIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */ 1015 #define _WTIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ 1016 #define _WTIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1017 #define WTIMER_IFC_UF_DEFAULT (_WTIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1018 #define WTIMER_IFC_DIRCHG (0x1UL << 2) /**< Clear DIRCHG Interrupt Flag */ 1019 #define _WTIMER_IFC_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ 1020 #define _WTIMER_IFC_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ 1021 #define _WTIMER_IFC_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1022 #define WTIMER_IFC_DIRCHG_DEFAULT (_WTIMER_IFC_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1023 #define WTIMER_IFC_CC0 (0x1UL << 4) /**< Clear CC0 Interrupt Flag */ 1024 #define _WTIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ 1025 #define _WTIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ 1026 #define _WTIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1027 #define WTIMER_IFC_CC0_DEFAULT (_WTIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1028 #define WTIMER_IFC_CC1 (0x1UL << 5) /**< Clear CC1 Interrupt Flag */ 1029 #define _WTIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ 1030 #define _WTIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ 1031 #define _WTIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1032 #define WTIMER_IFC_CC1_DEFAULT (_WTIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1033 #define WTIMER_IFC_CC2 (0x1UL << 6) /**< Clear CC2 Interrupt Flag */ 1034 #define _WTIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ 1035 #define _WTIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ 1036 #define _WTIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1037 #define WTIMER_IFC_CC2_DEFAULT (_WTIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1038 #define WTIMER_IFC_CC3 (0x1UL << 7) /**< Clear CC3 Interrupt Flag */ 1039 #define _WTIMER_IFC_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ 1040 #define _WTIMER_IFC_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ 1041 #define _WTIMER_IFC_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1042 #define WTIMER_IFC_CC3_DEFAULT (_WTIMER_IFC_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1043 #define WTIMER_IFC_ICBOF0 (0x1UL << 8) /**< Clear ICBOF0 Interrupt Flag */ 1044 #define _WTIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ 1045 #define _WTIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ 1046 #define _WTIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1047 #define WTIMER_IFC_ICBOF0_DEFAULT (_WTIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1048 #define WTIMER_IFC_ICBOF1 (0x1UL << 9) /**< Clear ICBOF1 Interrupt Flag */ 1049 #define _WTIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ 1050 #define _WTIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ 1051 #define _WTIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1052 #define WTIMER_IFC_ICBOF1_DEFAULT (_WTIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1053 #define WTIMER_IFC_ICBOF2 (0x1UL << 10) /**< Clear ICBOF2 Interrupt Flag */ 1054 #define _WTIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ 1055 #define _WTIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ 1056 #define _WTIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1057 #define WTIMER_IFC_ICBOF2_DEFAULT (_WTIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1058 #define WTIMER_IFC_ICBOF3 (0x1UL << 11) /**< Clear ICBOF3 Interrupt Flag */ 1059 #define _WTIMER_IFC_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ 1060 #define _WTIMER_IFC_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ 1061 #define _WTIMER_IFC_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IFC */ 1062 #define WTIMER_IFC_ICBOF3_DEFAULT (_WTIMER_IFC_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IFC */ 1063 1064 /* Bit fields for WTIMER IEN */ 1065 #define _WTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_IEN */ 1066 #define _WTIMER_IEN_MASK 0x00000FF7UL /**< Mask for WTIMER_IEN */ 1067 #define WTIMER_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ 1068 #define _WTIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ 1069 #define _WTIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ 1070 #define _WTIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1071 #define WTIMER_IEN_OF_DEFAULT (_WTIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1072 #define WTIMER_IEN_UF (0x1UL << 1) /**< UF Interrupt Enable */ 1073 #define _WTIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ 1074 #define _WTIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ 1075 #define _WTIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1076 #define WTIMER_IEN_UF_DEFAULT (_WTIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1077 #define WTIMER_IEN_DIRCHG (0x1UL << 2) /**< DIRCHG Interrupt Enable */ 1078 #define _WTIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ 1079 #define _WTIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ 1080 #define _WTIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1081 #define WTIMER_IEN_DIRCHG_DEFAULT (_WTIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1082 #define WTIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ 1083 #define _WTIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ 1084 #define _WTIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ 1085 #define _WTIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1086 #define WTIMER_IEN_CC0_DEFAULT (_WTIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1087 #define WTIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ 1088 #define _WTIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ 1089 #define _WTIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ 1090 #define _WTIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1091 #define WTIMER_IEN_CC1_DEFAULT (_WTIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1092 #define WTIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ 1093 #define _WTIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ 1094 #define _WTIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ 1095 #define _WTIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1096 #define WTIMER_IEN_CC2_DEFAULT (_WTIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1097 #define WTIMER_IEN_CC3 (0x1UL << 7) /**< CC3 Interrupt Enable */ 1098 #define _WTIMER_IEN_CC3_SHIFT 7 /**< Shift value for TIMER_CC3 */ 1099 #define _WTIMER_IEN_CC3_MASK 0x80UL /**< Bit mask for TIMER_CC3 */ 1100 #define _WTIMER_IEN_CC3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1101 #define WTIMER_IEN_CC3_DEFAULT (_WTIMER_IEN_CC3_DEFAULT << 7) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1102 #define WTIMER_IEN_ICBOF0 (0x1UL << 8) /**< ICBOF0 Interrupt Enable */ 1103 #define _WTIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */ 1104 #define _WTIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */ 1105 #define _WTIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1106 #define WTIMER_IEN_ICBOF0_DEFAULT (_WTIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1107 #define WTIMER_IEN_ICBOF1 (0x1UL << 9) /**< ICBOF1 Interrupt Enable */ 1108 #define _WTIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */ 1109 #define _WTIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */ 1110 #define _WTIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1111 #define WTIMER_IEN_ICBOF1_DEFAULT (_WTIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1112 #define WTIMER_IEN_ICBOF2 (0x1UL << 10) /**< ICBOF2 Interrupt Enable */ 1113 #define _WTIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */ 1114 #define _WTIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */ 1115 #define _WTIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1116 #define WTIMER_IEN_ICBOF2_DEFAULT (_WTIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1117 #define WTIMER_IEN_ICBOF3 (0x1UL << 11) /**< ICBOF3 Interrupt Enable */ 1118 #define _WTIMER_IEN_ICBOF3_SHIFT 11 /**< Shift value for TIMER_ICBOF3 */ 1119 #define _WTIMER_IEN_ICBOF3_MASK 0x800UL /**< Bit mask for TIMER_ICBOF3 */ 1120 #define _WTIMER_IEN_ICBOF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_IEN */ 1121 #define WTIMER_IEN_ICBOF3_DEFAULT (_WTIMER_IEN_ICBOF3_DEFAULT << 11) /**< Shifted mode DEFAULT for WTIMER_IEN */ 1122 1123 /* Bit fields for WTIMER TOP */ 1124 #define _WTIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for WTIMER_TOP */ 1125 #define _WTIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOP */ 1126 #define _WTIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ 1127 #define _WTIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ 1128 #define _WTIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for WTIMER_TOP */ 1129 #define WTIMER_TOP_TOP_DEFAULT (_WTIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOP */ 1130 1131 /* Bit fields for WTIMER TOPB */ 1132 #define _WTIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_TOPB */ 1133 #define _WTIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_TOPB */ 1134 #define _WTIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ 1135 #define _WTIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ 1136 #define _WTIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_TOPB */ 1137 #define WTIMER_TOPB_TOPB_DEFAULT (_WTIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_TOPB */ 1138 1139 /* Bit fields for WTIMER CNT */ 1140 #define _WTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CNT */ 1141 #define _WTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CNT */ 1142 #define _WTIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ 1143 #define _WTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ 1144 #define _WTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CNT */ 1145 #define WTIMER_CNT_CNT_DEFAULT (_WTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CNT */ 1146 1147 /* Bit fields for WTIMER LOCK */ 1148 #define _WTIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_LOCK */ 1149 #define _WTIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_LOCK */ 1150 #define _WTIMER_LOCK_TIMERLOCKKEY_SHIFT 0 /**< Shift value for TIMER_TIMERLOCKKEY */ 1151 #define _WTIMER_LOCK_TIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_TIMERLOCKKEY */ 1152 #define _WTIMER_LOCK_TIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_LOCK */ 1153 #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_LOCK */ 1154 #define _WTIMER_LOCK_TIMERLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_LOCK */ 1155 #define _WTIMER_LOCK_TIMERLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_LOCK */ 1156 #define _WTIMER_LOCK_TIMERLOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_LOCK */ 1157 #define WTIMER_LOCK_TIMERLOCKKEY_DEFAULT (_WTIMER_LOCK_TIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_LOCK */ 1158 #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_LOCK */ 1159 #define WTIMER_LOCK_TIMERLOCKKEY_LOCK (_WTIMER_LOCK_TIMERLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_LOCK */ 1160 #define WTIMER_LOCK_TIMERLOCKKEY_LOCKED (_WTIMER_LOCK_TIMERLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_LOCK */ 1161 #define WTIMER_LOCK_TIMERLOCKKEY_UNLOCK (_WTIMER_LOCK_TIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_LOCK */ 1162 1163 /* Bit fields for WTIMER ROUTEPEN */ 1164 #define _WTIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTEPEN */ 1165 #define _WTIMER_ROUTEPEN_MASK 0x0000070FUL /**< Mask for WTIMER_ROUTEPEN */ 1166 #define WTIMER_ROUTEPEN_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */ 1167 #define _WTIMER_ROUTEPEN_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */ 1168 #define _WTIMER_ROUTEPEN_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */ 1169 #define _WTIMER_ROUTEPEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1170 #define WTIMER_ROUTEPEN_CC0PEN_DEFAULT (_WTIMER_ROUTEPEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1171 #define WTIMER_ROUTEPEN_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */ 1172 #define _WTIMER_ROUTEPEN_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */ 1173 #define _WTIMER_ROUTEPEN_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */ 1174 #define _WTIMER_ROUTEPEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1175 #define WTIMER_ROUTEPEN_CC1PEN_DEFAULT (_WTIMER_ROUTEPEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1176 #define WTIMER_ROUTEPEN_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */ 1177 #define _WTIMER_ROUTEPEN_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */ 1178 #define _WTIMER_ROUTEPEN_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */ 1179 #define _WTIMER_ROUTEPEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1180 #define WTIMER_ROUTEPEN_CC2PEN_DEFAULT (_WTIMER_ROUTEPEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1181 #define WTIMER_ROUTEPEN_CC3PEN (0x1UL << 3) /**< CC Channel 3 Pin Enable */ 1182 #define _WTIMER_ROUTEPEN_CC3PEN_SHIFT 3 /**< Shift value for TIMER_CC3PEN */ 1183 #define _WTIMER_ROUTEPEN_CC3PEN_MASK 0x8UL /**< Bit mask for TIMER_CC3PEN */ 1184 #define _WTIMER_ROUTEPEN_CC3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1185 #define WTIMER_ROUTEPEN_CC3PEN_DEFAULT (_WTIMER_ROUTEPEN_CC3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1186 #define WTIMER_ROUTEPEN_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */ 1187 #define _WTIMER_ROUTEPEN_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */ 1188 #define _WTIMER_ROUTEPEN_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */ 1189 #define _WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1190 #define WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1191 #define WTIMER_ROUTEPEN_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */ 1192 #define _WTIMER_ROUTEPEN_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */ 1193 #define _WTIMER_ROUTEPEN_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */ 1194 #define _WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1195 #define WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1196 #define WTIMER_ROUTEPEN_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */ 1197 #define _WTIMER_ROUTEPEN_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */ 1198 #define _WTIMER_ROUTEPEN_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */ 1199 #define _WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTEPEN */ 1200 #define WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT (_WTIMER_ROUTEPEN_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_ROUTEPEN */ 1201 1202 /* Bit fields for WTIMER ROUTELOC0 */ 1203 #define _WTIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC0 */ 1204 #define _WTIMER_ROUTELOC0_MASK 0x07070707UL /**< Mask for WTIMER_ROUTELOC0 */ 1205 #define _WTIMER_ROUTELOC0_CC0LOC_SHIFT 0 /**< Shift value for TIMER_CC0LOC */ 1206 #define _WTIMER_ROUTELOC0_CC0LOC_MASK 0x7UL /**< Bit mask for TIMER_CC0LOC */ 1207 #define _WTIMER_ROUTELOC0_CC0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ 1208 #define _WTIMER_ROUTELOC0_CC0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ 1209 #define _WTIMER_ROUTELOC0_CC0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ 1210 #define _WTIMER_ROUTELOC0_CC0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ 1211 #define _WTIMER_ROUTELOC0_CC0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ 1212 #define _WTIMER_ROUTELOC0_CC0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ 1213 #define _WTIMER_ROUTELOC0_CC0LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ 1214 #define _WTIMER_ROUTELOC0_CC0LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ 1215 #define _WTIMER_ROUTELOC0_CC0LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ 1216 #define WTIMER_ROUTELOC0_CC0LOC_LOC0 (_WTIMER_ROUTELOC0_CC0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ 1217 #define WTIMER_ROUTELOC0_CC0LOC_DEFAULT (_WTIMER_ROUTELOC0_CC0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ 1218 #define WTIMER_ROUTELOC0_CC0LOC_LOC1 (_WTIMER_ROUTELOC0_CC0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ 1219 #define WTIMER_ROUTELOC0_CC0LOC_LOC2 (_WTIMER_ROUTELOC0_CC0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ 1220 #define WTIMER_ROUTELOC0_CC0LOC_LOC3 (_WTIMER_ROUTELOC0_CC0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ 1221 #define WTIMER_ROUTELOC0_CC0LOC_LOC4 (_WTIMER_ROUTELOC0_CC0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ 1222 #define WTIMER_ROUTELOC0_CC0LOC_LOC5 (_WTIMER_ROUTELOC0_CC0LOC_LOC5 << 0) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ 1223 #define WTIMER_ROUTELOC0_CC0LOC_LOC6 (_WTIMER_ROUTELOC0_CC0LOC_LOC6 << 0) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ 1224 #define WTIMER_ROUTELOC0_CC0LOC_LOC7 (_WTIMER_ROUTELOC0_CC0LOC_LOC7 << 0) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ 1225 #define _WTIMER_ROUTELOC0_CC1LOC_SHIFT 8 /**< Shift value for TIMER_CC1LOC */ 1226 #define _WTIMER_ROUTELOC0_CC1LOC_MASK 0x700UL /**< Bit mask for TIMER_CC1LOC */ 1227 #define _WTIMER_ROUTELOC0_CC1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ 1228 #define _WTIMER_ROUTELOC0_CC1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ 1229 #define _WTIMER_ROUTELOC0_CC1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ 1230 #define _WTIMER_ROUTELOC0_CC1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ 1231 #define _WTIMER_ROUTELOC0_CC1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ 1232 #define _WTIMER_ROUTELOC0_CC1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ 1233 #define _WTIMER_ROUTELOC0_CC1LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ 1234 #define _WTIMER_ROUTELOC0_CC1LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ 1235 #define _WTIMER_ROUTELOC0_CC1LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ 1236 #define WTIMER_ROUTELOC0_CC1LOC_LOC0 (_WTIMER_ROUTELOC0_CC1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ 1237 #define WTIMER_ROUTELOC0_CC1LOC_DEFAULT (_WTIMER_ROUTELOC0_CC1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ 1238 #define WTIMER_ROUTELOC0_CC1LOC_LOC1 (_WTIMER_ROUTELOC0_CC1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ 1239 #define WTIMER_ROUTELOC0_CC1LOC_LOC2 (_WTIMER_ROUTELOC0_CC1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ 1240 #define WTIMER_ROUTELOC0_CC1LOC_LOC3 (_WTIMER_ROUTELOC0_CC1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ 1241 #define WTIMER_ROUTELOC0_CC1LOC_LOC4 (_WTIMER_ROUTELOC0_CC1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ 1242 #define WTIMER_ROUTELOC0_CC1LOC_LOC5 (_WTIMER_ROUTELOC0_CC1LOC_LOC5 << 8) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ 1243 #define WTIMER_ROUTELOC0_CC1LOC_LOC6 (_WTIMER_ROUTELOC0_CC1LOC_LOC6 << 8) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ 1244 #define WTIMER_ROUTELOC0_CC1LOC_LOC7 (_WTIMER_ROUTELOC0_CC1LOC_LOC7 << 8) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ 1245 #define _WTIMER_ROUTELOC0_CC2LOC_SHIFT 16 /**< Shift value for TIMER_CC2LOC */ 1246 #define _WTIMER_ROUTELOC0_CC2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CC2LOC */ 1247 #define _WTIMER_ROUTELOC0_CC2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ 1248 #define _WTIMER_ROUTELOC0_CC2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ 1249 #define _WTIMER_ROUTELOC0_CC2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ 1250 #define _WTIMER_ROUTELOC0_CC2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ 1251 #define _WTIMER_ROUTELOC0_CC2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ 1252 #define _WTIMER_ROUTELOC0_CC2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ 1253 #define _WTIMER_ROUTELOC0_CC2LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ 1254 #define _WTIMER_ROUTELOC0_CC2LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ 1255 #define _WTIMER_ROUTELOC0_CC2LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ 1256 #define WTIMER_ROUTELOC0_CC2LOC_LOC0 (_WTIMER_ROUTELOC0_CC2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ 1257 #define WTIMER_ROUTELOC0_CC2LOC_DEFAULT (_WTIMER_ROUTELOC0_CC2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ 1258 #define WTIMER_ROUTELOC0_CC2LOC_LOC1 (_WTIMER_ROUTELOC0_CC2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ 1259 #define WTIMER_ROUTELOC0_CC2LOC_LOC2 (_WTIMER_ROUTELOC0_CC2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ 1260 #define WTIMER_ROUTELOC0_CC2LOC_LOC3 (_WTIMER_ROUTELOC0_CC2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ 1261 #define WTIMER_ROUTELOC0_CC2LOC_LOC4 (_WTIMER_ROUTELOC0_CC2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ 1262 #define WTIMER_ROUTELOC0_CC2LOC_LOC5 (_WTIMER_ROUTELOC0_CC2LOC_LOC5 << 16) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ 1263 #define WTIMER_ROUTELOC0_CC2LOC_LOC6 (_WTIMER_ROUTELOC0_CC2LOC_LOC6 << 16) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ 1264 #define WTIMER_ROUTELOC0_CC2LOC_LOC7 (_WTIMER_ROUTELOC0_CC2LOC_LOC7 << 16) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ 1265 #define _WTIMER_ROUTELOC0_CC3LOC_SHIFT 24 /**< Shift value for TIMER_CC3LOC */ 1266 #define _WTIMER_ROUTELOC0_CC3LOC_MASK 0x7000000UL /**< Bit mask for TIMER_CC3LOC */ 1267 #define _WTIMER_ROUTELOC0_CC3LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC0 */ 1268 #define _WTIMER_ROUTELOC0_CC3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC0 */ 1269 #define _WTIMER_ROUTELOC0_CC3LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC0 */ 1270 #define _WTIMER_ROUTELOC0_CC3LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC0 */ 1271 #define _WTIMER_ROUTELOC0_CC3LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC0 */ 1272 #define _WTIMER_ROUTELOC0_CC3LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC0 */ 1273 #define _WTIMER_ROUTELOC0_CC3LOC_LOC5 0x00000005UL /**< Mode LOC5 for WTIMER_ROUTELOC0 */ 1274 #define _WTIMER_ROUTELOC0_CC3LOC_LOC6 0x00000006UL /**< Mode LOC6 for WTIMER_ROUTELOC0 */ 1275 #define _WTIMER_ROUTELOC0_CC3LOC_LOC7 0x00000007UL /**< Mode LOC7 for WTIMER_ROUTELOC0 */ 1276 #define WTIMER_ROUTELOC0_CC3LOC_LOC0 (_WTIMER_ROUTELOC0_CC3LOC_LOC0 << 24) /**< Shifted mode LOC0 for WTIMER_ROUTELOC0 */ 1277 #define WTIMER_ROUTELOC0_CC3LOC_DEFAULT (_WTIMER_ROUTELOC0_CC3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC0 */ 1278 #define WTIMER_ROUTELOC0_CC3LOC_LOC1 (_WTIMER_ROUTELOC0_CC3LOC_LOC1 << 24) /**< Shifted mode LOC1 for WTIMER_ROUTELOC0 */ 1279 #define WTIMER_ROUTELOC0_CC3LOC_LOC2 (_WTIMER_ROUTELOC0_CC3LOC_LOC2 << 24) /**< Shifted mode LOC2 for WTIMER_ROUTELOC0 */ 1280 #define WTIMER_ROUTELOC0_CC3LOC_LOC3 (_WTIMER_ROUTELOC0_CC3LOC_LOC3 << 24) /**< Shifted mode LOC3 for WTIMER_ROUTELOC0 */ 1281 #define WTIMER_ROUTELOC0_CC3LOC_LOC4 (_WTIMER_ROUTELOC0_CC3LOC_LOC4 << 24) /**< Shifted mode LOC4 for WTIMER_ROUTELOC0 */ 1282 #define WTIMER_ROUTELOC0_CC3LOC_LOC5 (_WTIMER_ROUTELOC0_CC3LOC_LOC5 << 24) /**< Shifted mode LOC5 for WTIMER_ROUTELOC0 */ 1283 #define WTIMER_ROUTELOC0_CC3LOC_LOC6 (_WTIMER_ROUTELOC0_CC3LOC_LOC6 << 24) /**< Shifted mode LOC6 for WTIMER_ROUTELOC0 */ 1284 #define WTIMER_ROUTELOC0_CC3LOC_LOC7 (_WTIMER_ROUTELOC0_CC3LOC_LOC7 << 24) /**< Shifted mode LOC7 for WTIMER_ROUTELOC0 */ 1285 1286 /* Bit fields for WTIMER ROUTELOC2 */ 1287 #define _WTIMER_ROUTELOC2_RESETVALUE 0x00000000UL /**< Default value for WTIMER_ROUTELOC2 */ 1288 #define _WTIMER_ROUTELOC2_MASK 0x00070707UL /**< Mask for WTIMER_ROUTELOC2 */ 1289 #define _WTIMER_ROUTELOC2_CDTI0LOC_SHIFT 0 /**< Shift value for TIMER_CDTI0LOC */ 1290 #define _WTIMER_ROUTELOC2_CDTI0LOC_MASK 0x7UL /**< Bit mask for TIMER_CDTI0LOC */ 1291 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ 1292 #define _WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ 1293 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ 1294 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ 1295 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ 1296 #define _WTIMER_ROUTELOC2_CDTI0LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ 1297 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC0 << 0) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ 1298 #define WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ 1299 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC1 << 0) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ 1300 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC2 << 0) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ 1301 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC3 << 0) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ 1302 #define WTIMER_ROUTELOC2_CDTI0LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI0LOC_LOC4 << 0) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ 1303 #define _WTIMER_ROUTELOC2_CDTI1LOC_SHIFT 8 /**< Shift value for TIMER_CDTI1LOC */ 1304 #define _WTIMER_ROUTELOC2_CDTI1LOC_MASK 0x700UL /**< Bit mask for TIMER_CDTI1LOC */ 1305 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ 1306 #define _WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ 1307 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ 1308 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ 1309 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ 1310 #define _WTIMER_ROUTELOC2_CDTI1LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ 1311 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC0 << 8) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ 1312 #define WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ 1313 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC1 << 8) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ 1314 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC2 << 8) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ 1315 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC3 << 8) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ 1316 #define WTIMER_ROUTELOC2_CDTI1LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI1LOC_LOC4 << 8) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ 1317 #define _WTIMER_ROUTELOC2_CDTI2LOC_SHIFT 16 /**< Shift value for TIMER_CDTI2LOC */ 1318 #define _WTIMER_ROUTELOC2_CDTI2LOC_MASK 0x70000UL /**< Bit mask for TIMER_CDTI2LOC */ 1319 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC0 0x00000000UL /**< Mode LOC0 for WTIMER_ROUTELOC2 */ 1320 #define _WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_ROUTELOC2 */ 1321 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC1 0x00000001UL /**< Mode LOC1 for WTIMER_ROUTELOC2 */ 1322 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC2 0x00000002UL /**< Mode LOC2 for WTIMER_ROUTELOC2 */ 1323 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC3 0x00000003UL /**< Mode LOC3 for WTIMER_ROUTELOC2 */ 1324 #define _WTIMER_ROUTELOC2_CDTI2LOC_LOC4 0x00000004UL /**< Mode LOC4 for WTIMER_ROUTELOC2 */ 1325 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC0 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC0 << 16) /**< Shifted mode LOC0 for WTIMER_ROUTELOC2 */ 1326 #define WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT (_WTIMER_ROUTELOC2_CDTI2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_ROUTELOC2 */ 1327 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC1 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC1 << 16) /**< Shifted mode LOC1 for WTIMER_ROUTELOC2 */ 1328 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC2 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC2 << 16) /**< Shifted mode LOC2 for WTIMER_ROUTELOC2 */ 1329 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC3 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC3 << 16) /**< Shifted mode LOC3 for WTIMER_ROUTELOC2 */ 1330 #define WTIMER_ROUTELOC2_CDTI2LOC_LOC4 (_WTIMER_ROUTELOC2_CDTI2LOC_LOC4 << 16) /**< Shifted mode LOC4 for WTIMER_ROUTELOC2 */ 1331 1332 /* Bit fields for WTIMER CC_CTRL */ 1333 #define _WTIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CTRL */ 1334 #define _WTIMER_CC_CTRL_MASK 0x7F1F3F17UL /**< Mask for WTIMER_CC_CTRL */ 1335 #define _WTIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ 1336 #define _WTIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ 1337 #define _WTIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1338 #define _WTIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for WTIMER_CC_CTRL */ 1339 #define _WTIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for WTIMER_CC_CTRL */ 1340 #define _WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ 1341 #define _WTIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for WTIMER_CC_CTRL */ 1342 #define WTIMER_CC_CTRL_MODE_DEFAULT (_WTIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1343 #define WTIMER_CC_CTRL_MODE_OFF (_WTIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for WTIMER_CC_CTRL */ 1344 #define WTIMER_CC_CTRL_MODE_INPUTCAPTURE (_WTIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for WTIMER_CC_CTRL */ 1345 #define WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_WTIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for WTIMER_CC_CTRL */ 1346 #define WTIMER_CC_CTRL_MODE_PWM (_WTIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for WTIMER_CC_CTRL */ 1347 #define WTIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ 1348 #define _WTIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ 1349 #define _WTIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ 1350 #define _WTIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1351 #define WTIMER_CC_CTRL_OUTINV_DEFAULT (_WTIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1352 #define WTIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */ 1353 #define _WTIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ 1354 #define _WTIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ 1355 #define _WTIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1356 #define WTIMER_CC_CTRL_COIST_DEFAULT (_WTIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1357 #define _WTIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ 1358 #define _WTIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ 1359 #define _WTIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1360 #define _WTIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ 1361 #define _WTIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ 1362 #define _WTIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ 1363 #define _WTIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ 1364 #define WTIMER_CC_CTRL_CMOA_DEFAULT (_WTIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1365 #define WTIMER_CC_CTRL_CMOA_NONE (_WTIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for WTIMER_CC_CTRL */ 1366 #define WTIMER_CC_CTRL_CMOA_TOGGLE (_WTIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ 1367 #define WTIMER_CC_CTRL_CMOA_CLEAR (_WTIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ 1368 #define WTIMER_CC_CTRL_CMOA_SET (_WTIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for WTIMER_CC_CTRL */ 1369 #define _WTIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ 1370 #define _WTIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ 1371 #define _WTIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1372 #define _WTIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ 1373 #define _WTIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ 1374 #define _WTIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ 1375 #define _WTIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ 1376 #define WTIMER_CC_CTRL_COFOA_DEFAULT (_WTIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1377 #define WTIMER_CC_CTRL_COFOA_NONE (_WTIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for WTIMER_CC_CTRL */ 1378 #define WTIMER_CC_CTRL_COFOA_TOGGLE (_WTIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ 1379 #define WTIMER_CC_CTRL_COFOA_CLEAR (_WTIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ 1380 #define WTIMER_CC_CTRL_COFOA_SET (_WTIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for WTIMER_CC_CTRL */ 1381 #define _WTIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ 1382 #define _WTIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ 1383 #define _WTIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1384 #define _WTIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for WTIMER_CC_CTRL */ 1385 #define _WTIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for WTIMER_CC_CTRL */ 1386 #define _WTIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_CC_CTRL */ 1387 #define _WTIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for WTIMER_CC_CTRL */ 1388 #define WTIMER_CC_CTRL_CUFOA_DEFAULT (_WTIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1389 #define WTIMER_CC_CTRL_CUFOA_NONE (_WTIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for WTIMER_CC_CTRL */ 1390 #define WTIMER_CC_CTRL_CUFOA_TOGGLE (_WTIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for WTIMER_CC_CTRL */ 1391 #define WTIMER_CC_CTRL_CUFOA_CLEAR (_WTIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for WTIMER_CC_CTRL */ 1392 #define WTIMER_CC_CTRL_CUFOA_SET (_WTIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for WTIMER_CC_CTRL */ 1393 #define _WTIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */ 1394 #define _WTIMER_CC_CTRL_PRSSEL_MASK 0x1F0000UL /**< Bit mask for TIMER_PRSSEL */ 1395 #define _WTIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1396 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_CC_CTRL */ 1397 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_CC_CTRL */ 1398 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_CC_CTRL */ 1399 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_CC_CTRL */ 1400 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_CC_CTRL */ 1401 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_CC_CTRL */ 1402 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_CC_CTRL */ 1403 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_CC_CTRL */ 1404 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_CC_CTRL */ 1405 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_CC_CTRL */ 1406 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_CC_CTRL */ 1407 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_CC_CTRL */ 1408 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_CC_CTRL */ 1409 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_CC_CTRL */ 1410 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_CC_CTRL */ 1411 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_CC_CTRL */ 1412 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_CC_CTRL */ 1413 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_CC_CTRL */ 1414 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_CC_CTRL */ 1415 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_CC_CTRL */ 1416 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_CC_CTRL */ 1417 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_CC_CTRL */ 1418 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_CC_CTRL */ 1419 #define _WTIMER_CC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_CC_CTRL */ 1420 #define WTIMER_CC_CTRL_PRSSEL_DEFAULT (_WTIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1421 #define WTIMER_CC_CTRL_PRSSEL_PRSCH0 (_WTIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for WTIMER_CC_CTRL */ 1422 #define WTIMER_CC_CTRL_PRSSEL_PRSCH1 (_WTIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for WTIMER_CC_CTRL */ 1423 #define WTIMER_CC_CTRL_PRSSEL_PRSCH2 (_WTIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for WTIMER_CC_CTRL */ 1424 #define WTIMER_CC_CTRL_PRSSEL_PRSCH3 (_WTIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for WTIMER_CC_CTRL */ 1425 #define WTIMER_CC_CTRL_PRSSEL_PRSCH4 (_WTIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for WTIMER_CC_CTRL */ 1426 #define WTIMER_CC_CTRL_PRSSEL_PRSCH5 (_WTIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for WTIMER_CC_CTRL */ 1427 #define WTIMER_CC_CTRL_PRSSEL_PRSCH6 (_WTIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for WTIMER_CC_CTRL */ 1428 #define WTIMER_CC_CTRL_PRSSEL_PRSCH7 (_WTIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for WTIMER_CC_CTRL */ 1429 #define WTIMER_CC_CTRL_PRSSEL_PRSCH8 (_WTIMER_CC_CTRL_PRSSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for WTIMER_CC_CTRL */ 1430 #define WTIMER_CC_CTRL_PRSSEL_PRSCH9 (_WTIMER_CC_CTRL_PRSSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for WTIMER_CC_CTRL */ 1431 #define WTIMER_CC_CTRL_PRSSEL_PRSCH10 (_WTIMER_CC_CTRL_PRSSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for WTIMER_CC_CTRL */ 1432 #define WTIMER_CC_CTRL_PRSSEL_PRSCH11 (_WTIMER_CC_CTRL_PRSSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for WTIMER_CC_CTRL */ 1433 #define WTIMER_CC_CTRL_PRSSEL_PRSCH12 (_WTIMER_CC_CTRL_PRSSEL_PRSCH12 << 16) /**< Shifted mode PRSCH12 for WTIMER_CC_CTRL */ 1434 #define WTIMER_CC_CTRL_PRSSEL_PRSCH13 (_WTIMER_CC_CTRL_PRSSEL_PRSCH13 << 16) /**< Shifted mode PRSCH13 for WTIMER_CC_CTRL */ 1435 #define WTIMER_CC_CTRL_PRSSEL_PRSCH14 (_WTIMER_CC_CTRL_PRSSEL_PRSCH14 << 16) /**< Shifted mode PRSCH14 for WTIMER_CC_CTRL */ 1436 #define WTIMER_CC_CTRL_PRSSEL_PRSCH15 (_WTIMER_CC_CTRL_PRSSEL_PRSCH15 << 16) /**< Shifted mode PRSCH15 for WTIMER_CC_CTRL */ 1437 #define WTIMER_CC_CTRL_PRSSEL_PRSCH16 (_WTIMER_CC_CTRL_PRSSEL_PRSCH16 << 16) /**< Shifted mode PRSCH16 for WTIMER_CC_CTRL */ 1438 #define WTIMER_CC_CTRL_PRSSEL_PRSCH17 (_WTIMER_CC_CTRL_PRSSEL_PRSCH17 << 16) /**< Shifted mode PRSCH17 for WTIMER_CC_CTRL */ 1439 #define WTIMER_CC_CTRL_PRSSEL_PRSCH18 (_WTIMER_CC_CTRL_PRSSEL_PRSCH18 << 16) /**< Shifted mode PRSCH18 for WTIMER_CC_CTRL */ 1440 #define WTIMER_CC_CTRL_PRSSEL_PRSCH19 (_WTIMER_CC_CTRL_PRSSEL_PRSCH19 << 16) /**< Shifted mode PRSCH19 for WTIMER_CC_CTRL */ 1441 #define WTIMER_CC_CTRL_PRSSEL_PRSCH20 (_WTIMER_CC_CTRL_PRSSEL_PRSCH20 << 16) /**< Shifted mode PRSCH20 for WTIMER_CC_CTRL */ 1442 #define WTIMER_CC_CTRL_PRSSEL_PRSCH21 (_WTIMER_CC_CTRL_PRSSEL_PRSCH21 << 16) /**< Shifted mode PRSCH21 for WTIMER_CC_CTRL */ 1443 #define WTIMER_CC_CTRL_PRSSEL_PRSCH22 (_WTIMER_CC_CTRL_PRSSEL_PRSCH22 << 16) /**< Shifted mode PRSCH22 for WTIMER_CC_CTRL */ 1444 #define WTIMER_CC_CTRL_PRSSEL_PRSCH23 (_WTIMER_CC_CTRL_PRSSEL_PRSCH23 << 16) /**< Shifted mode PRSCH23 for WTIMER_CC_CTRL */ 1445 #define _WTIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ 1446 #define _WTIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ 1447 #define _WTIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1448 #define _WTIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for WTIMER_CC_CTRL */ 1449 #define _WTIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for WTIMER_CC_CTRL */ 1450 #define _WTIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for WTIMER_CC_CTRL */ 1451 #define _WTIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for WTIMER_CC_CTRL */ 1452 #define WTIMER_CC_CTRL_ICEDGE_DEFAULT (_WTIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1453 #define WTIMER_CC_CTRL_ICEDGE_RISING (_WTIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for WTIMER_CC_CTRL */ 1454 #define WTIMER_CC_CTRL_ICEDGE_FALLING (_WTIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ 1455 #define WTIMER_CC_CTRL_ICEDGE_BOTH (_WTIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for WTIMER_CC_CTRL */ 1456 #define WTIMER_CC_CTRL_ICEDGE_NONE (_WTIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for WTIMER_CC_CTRL */ 1457 #define _WTIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ 1458 #define _WTIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ 1459 #define _WTIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1460 #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for WTIMER_CC_CTRL */ 1461 #define _WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ 1462 #define _WTIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for WTIMER_CC_CTRL */ 1463 #define _WTIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for WTIMER_CC_CTRL */ 1464 #define WTIMER_CC_CTRL_ICEVCTRL_DEFAULT (_WTIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1465 #define WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for WTIMER_CC_CTRL */ 1466 #define WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_WTIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for WTIMER_CC_CTRL */ 1467 #define WTIMER_CC_CTRL_ICEVCTRL_RISING (_WTIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for WTIMER_CC_CTRL */ 1468 #define WTIMER_CC_CTRL_ICEVCTRL_FALLING (_WTIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for WTIMER_CC_CTRL */ 1469 #define WTIMER_CC_CTRL_PRSCONF (0x1UL << 28) /**< PRS Configuration */ 1470 #define _WTIMER_CC_CTRL_PRSCONF_SHIFT 28 /**< Shift value for TIMER_PRSCONF */ 1471 #define _WTIMER_CC_CTRL_PRSCONF_MASK 0x10000000UL /**< Bit mask for TIMER_PRSCONF */ 1472 #define _WTIMER_CC_CTRL_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1473 #define _WTIMER_CC_CTRL_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for WTIMER_CC_CTRL */ 1474 #define _WTIMER_CC_CTRL_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for WTIMER_CC_CTRL */ 1475 #define WTIMER_CC_CTRL_PRSCONF_DEFAULT (_WTIMER_CC_CTRL_PRSCONF_DEFAULT << 28) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1476 #define WTIMER_CC_CTRL_PRSCONF_PULSE (_WTIMER_CC_CTRL_PRSCONF_PULSE << 28) /**< Shifted mode PULSE for WTIMER_CC_CTRL */ 1477 #define WTIMER_CC_CTRL_PRSCONF_LEVEL (_WTIMER_CC_CTRL_PRSCONF_LEVEL << 28) /**< Shifted mode LEVEL for WTIMER_CC_CTRL */ 1478 #define WTIMER_CC_CTRL_INSEL (0x1UL << 29) /**< Input Selection */ 1479 #define _WTIMER_CC_CTRL_INSEL_SHIFT 29 /**< Shift value for TIMER_INSEL */ 1480 #define _WTIMER_CC_CTRL_INSEL_MASK 0x20000000UL /**< Bit mask for TIMER_INSEL */ 1481 #define _WTIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1482 #define _WTIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for WTIMER_CC_CTRL */ 1483 #define _WTIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for WTIMER_CC_CTRL */ 1484 #define WTIMER_CC_CTRL_INSEL_DEFAULT (_WTIMER_CC_CTRL_INSEL_DEFAULT << 29) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1485 #define WTIMER_CC_CTRL_INSEL_PIN (_WTIMER_CC_CTRL_INSEL_PIN << 29) /**< Shifted mode PIN for WTIMER_CC_CTRL */ 1486 #define WTIMER_CC_CTRL_INSEL_PRS (_WTIMER_CC_CTRL_INSEL_PRS << 29) /**< Shifted mode PRS for WTIMER_CC_CTRL */ 1487 #define WTIMER_CC_CTRL_FILT (0x1UL << 30) /**< Digital Filter */ 1488 #define _WTIMER_CC_CTRL_FILT_SHIFT 30 /**< Shift value for TIMER_FILT */ 1489 #define _WTIMER_CC_CTRL_FILT_MASK 0x40000000UL /**< Bit mask for TIMER_FILT */ 1490 #define _WTIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CTRL */ 1491 #define _WTIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for WTIMER_CC_CTRL */ 1492 #define _WTIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for WTIMER_CC_CTRL */ 1493 #define WTIMER_CC_CTRL_FILT_DEFAULT (_WTIMER_CC_CTRL_FILT_DEFAULT << 30) /**< Shifted mode DEFAULT for WTIMER_CC_CTRL */ 1494 #define WTIMER_CC_CTRL_FILT_DISABLE (_WTIMER_CC_CTRL_FILT_DISABLE << 30) /**< Shifted mode DISABLE for WTIMER_CC_CTRL */ 1495 #define WTIMER_CC_CTRL_FILT_ENABLE (_WTIMER_CC_CTRL_FILT_ENABLE << 30) /**< Shifted mode ENABLE for WTIMER_CC_CTRL */ 1496 1497 /* Bit fields for WTIMER CC_CCV */ 1498 #define _WTIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCV */ 1499 #define _WTIMER_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCV */ 1500 #define _WTIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */ 1501 #define _WTIMER_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCV */ 1502 #define _WTIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCV */ 1503 #define WTIMER_CC_CCV_CCV_DEFAULT (_WTIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCV */ 1504 1505 /* Bit fields for WTIMER CC_CCVP */ 1506 #define _WTIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVP */ 1507 #define _WTIMER_CC_CCVP_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVP */ 1508 #define _WTIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */ 1509 #define _WTIMER_CC_CCVP_CCVP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVP */ 1510 #define _WTIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVP */ 1511 #define WTIMER_CC_CCVP_CCVP_DEFAULT (_WTIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVP */ 1512 1513 /* Bit fields for WTIMER CC_CCVB */ 1514 #define _WTIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for WTIMER_CC_CCVB */ 1515 #define _WTIMER_CC_CCVB_MASK 0xFFFFFFFFUL /**< Mask for WTIMER_CC_CCVB */ 1516 #define _WTIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */ 1517 #define _WTIMER_CC_CCVB_CCVB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CCVB */ 1518 #define _WTIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_CC_CCVB */ 1519 #define WTIMER_CC_CCVB_CCVB_DEFAULT (_WTIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_CC_CCVB */ 1520 1521 /* Bit fields for WTIMER DTCTRL */ 1522 #define _WTIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTCTRL */ 1523 #define _WTIMER_DTCTRL_MASK 0x010007FFUL /**< Mask for WTIMER_DTCTRL */ 1524 #define WTIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */ 1525 #define _WTIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ 1526 #define _WTIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ 1527 #define _WTIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1528 #define WTIMER_DTCTRL_DTEN_DEFAULT (_WTIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1529 #define WTIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ 1530 #define _WTIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ 1531 #define _WTIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ 1532 #define _WTIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1533 #define _WTIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for WTIMER_DTCTRL */ 1534 #define _WTIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for WTIMER_DTCTRL */ 1535 #define WTIMER_DTCTRL_DTDAS_DEFAULT (_WTIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1536 #define WTIMER_DTCTRL_DTDAS_NORESTART (_WTIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for WTIMER_DTCTRL */ 1537 #define WTIMER_DTCTRL_DTDAS_RESTART (_WTIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for WTIMER_DTCTRL */ 1538 #define WTIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */ 1539 #define _WTIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */ 1540 #define _WTIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */ 1541 #define _WTIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1542 #define WTIMER_DTCTRL_DTIPOL_DEFAULT (_WTIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1543 #define WTIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert */ 1544 #define _WTIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */ 1545 #define _WTIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */ 1546 #define _WTIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1547 #define WTIMER_DTCTRL_DTCINV_DEFAULT (_WTIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1548 #define _WTIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */ 1549 #define _WTIMER_DTCTRL_DTPRSSEL_MASK 0x1F0UL /**< Bit mask for TIMER_DTPRSSEL */ 1550 #define _WTIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1551 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTCTRL */ 1552 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTCTRL */ 1553 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTCTRL */ 1554 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTCTRL */ 1555 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTCTRL */ 1556 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTCTRL */ 1557 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTCTRL */ 1558 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTCTRL */ 1559 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTCTRL */ 1560 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTCTRL */ 1561 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTCTRL */ 1562 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTCTRL */ 1563 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTCTRL */ 1564 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTCTRL */ 1565 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTCTRL */ 1566 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTCTRL */ 1567 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTCTRL */ 1568 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTCTRL */ 1569 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTCTRL */ 1570 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTCTRL */ 1571 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTCTRL */ 1572 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTCTRL */ 1573 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTCTRL */ 1574 #define _WTIMER_DTCTRL_DTPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTCTRL */ 1575 #define WTIMER_DTCTRL_DTPRSSEL_DEFAULT (_WTIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1576 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH0 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for WTIMER_DTCTRL */ 1577 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH1 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for WTIMER_DTCTRL */ 1578 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH2 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for WTIMER_DTCTRL */ 1579 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH3 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for WTIMER_DTCTRL */ 1580 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH4 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for WTIMER_DTCTRL */ 1581 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH5 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for WTIMER_DTCTRL */ 1582 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH6 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for WTIMER_DTCTRL */ 1583 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH7 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for WTIMER_DTCTRL */ 1584 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH8 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for WTIMER_DTCTRL */ 1585 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH9 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for WTIMER_DTCTRL */ 1586 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH10 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for WTIMER_DTCTRL */ 1587 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH11 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for WTIMER_DTCTRL */ 1588 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH12 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH12 << 4) /**< Shifted mode PRSCH12 for WTIMER_DTCTRL */ 1589 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH13 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH13 << 4) /**< Shifted mode PRSCH13 for WTIMER_DTCTRL */ 1590 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH14 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH14 << 4) /**< Shifted mode PRSCH14 for WTIMER_DTCTRL */ 1591 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH15 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH15 << 4) /**< Shifted mode PRSCH15 for WTIMER_DTCTRL */ 1592 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH16 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH16 << 4) /**< Shifted mode PRSCH16 for WTIMER_DTCTRL */ 1593 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH17 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH17 << 4) /**< Shifted mode PRSCH17 for WTIMER_DTCTRL */ 1594 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH18 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH18 << 4) /**< Shifted mode PRSCH18 for WTIMER_DTCTRL */ 1595 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH19 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH19 << 4) /**< Shifted mode PRSCH19 for WTIMER_DTCTRL */ 1596 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH20 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH20 << 4) /**< Shifted mode PRSCH20 for WTIMER_DTCTRL */ 1597 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH21 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH21 << 4) /**< Shifted mode PRSCH21 for WTIMER_DTCTRL */ 1598 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH22 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH22 << 4) /**< Shifted mode PRSCH22 for WTIMER_DTCTRL */ 1599 #define WTIMER_DTCTRL_DTPRSSEL_PRSCH23 (_WTIMER_DTCTRL_DTPRSSEL_PRSCH23 << 4) /**< Shifted mode PRSCH23 for WTIMER_DTCTRL */ 1600 #define WTIMER_DTCTRL_DTAR (0x1UL << 9) /**< DTI Always Run */ 1601 #define _WTIMER_DTCTRL_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ 1602 #define _WTIMER_DTCTRL_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ 1603 #define _WTIMER_DTCTRL_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1604 #define WTIMER_DTCTRL_DTAR_DEFAULT (_WTIMER_DTCTRL_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1605 #define WTIMER_DTCTRL_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ 1606 #define _WTIMER_DTCTRL_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ 1607 #define _WTIMER_DTCTRL_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ 1608 #define _WTIMER_DTCTRL_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1609 #define WTIMER_DTCTRL_DTFATS_DEFAULT (_WTIMER_DTCTRL_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1610 #define WTIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */ 1611 #define _WTIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */ 1612 #define _WTIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */ 1613 #define _WTIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTCTRL */ 1614 #define WTIMER_DTCTRL_DTPRSEN_DEFAULT (_WTIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTCTRL */ 1615 1616 /* Bit fields for WTIMER DTTIME */ 1617 #define _WTIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTTIME */ 1618 #define _WTIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for WTIMER_DTTIME */ 1619 #define _WTIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ 1620 #define _WTIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */ 1621 #define _WTIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ 1622 #define _WTIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for WTIMER_DTTIME */ 1623 #define _WTIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for WTIMER_DTTIME */ 1624 #define _WTIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for WTIMER_DTTIME */ 1625 #define _WTIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for WTIMER_DTTIME */ 1626 #define _WTIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for WTIMER_DTTIME */ 1627 #define _WTIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for WTIMER_DTTIME */ 1628 #define _WTIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for WTIMER_DTTIME */ 1629 #define _WTIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for WTIMER_DTTIME */ 1630 #define _WTIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for WTIMER_DTTIME */ 1631 #define _WTIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for WTIMER_DTTIME */ 1632 #define _WTIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for WTIMER_DTTIME */ 1633 #define WTIMER_DTTIME_DTPRESC_DEFAULT (_WTIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ 1634 #define WTIMER_DTTIME_DTPRESC_DIV1 (_WTIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for WTIMER_DTTIME */ 1635 #define WTIMER_DTTIME_DTPRESC_DIV2 (_WTIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for WTIMER_DTTIME */ 1636 #define WTIMER_DTTIME_DTPRESC_DIV4 (_WTIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for WTIMER_DTTIME */ 1637 #define WTIMER_DTTIME_DTPRESC_DIV8 (_WTIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for WTIMER_DTTIME */ 1638 #define WTIMER_DTTIME_DTPRESC_DIV16 (_WTIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for WTIMER_DTTIME */ 1639 #define WTIMER_DTTIME_DTPRESC_DIV32 (_WTIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for WTIMER_DTTIME */ 1640 #define WTIMER_DTTIME_DTPRESC_DIV64 (_WTIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for WTIMER_DTTIME */ 1641 #define WTIMER_DTTIME_DTPRESC_DIV128 (_WTIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for WTIMER_DTTIME */ 1642 #define WTIMER_DTTIME_DTPRESC_DIV256 (_WTIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for WTIMER_DTTIME */ 1643 #define WTIMER_DTTIME_DTPRESC_DIV512 (_WTIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for WTIMER_DTTIME */ 1644 #define WTIMER_DTTIME_DTPRESC_DIV1024 (_WTIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for WTIMER_DTTIME */ 1645 #define _WTIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */ 1646 #define _WTIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */ 1647 #define _WTIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ 1648 #define WTIMER_DTTIME_DTRISET_DEFAULT (_WTIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ 1649 #define _WTIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ 1650 #define _WTIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ 1651 #define _WTIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTTIME */ 1652 #define WTIMER_DTTIME_DTFALLT_DEFAULT (_WTIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTTIME */ 1653 1654 /* Bit fields for WTIMER DTFC */ 1655 #define _WTIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFC */ 1656 #define _WTIMER_DTFC_MASK 0x0F031F1FUL /**< Mask for WTIMER_DTFC */ 1657 #define _WTIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */ 1658 #define _WTIMER_DTFC_DTPRS0FSEL_MASK 0x1FUL /**< Bit mask for TIMER_DTPRS0FSEL */ 1659 #define _WTIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 1660 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ 1661 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ 1662 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ 1663 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ 1664 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ 1665 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ 1666 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ 1667 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ 1668 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ 1669 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ 1670 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ 1671 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ 1672 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ 1673 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ 1674 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ 1675 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ 1676 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ 1677 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ 1678 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ 1679 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ 1680 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ 1681 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ 1682 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ 1683 #define _WTIMER_DTFC_DTPRS0FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ 1684 #define WTIMER_DTFC_DTPRS0FSEL_DEFAULT (_WTIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 1685 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ 1686 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ 1687 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ 1688 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ 1689 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ 1690 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ 1691 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ 1692 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ 1693 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ 1694 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ 1695 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ 1696 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ 1697 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ 1698 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ 1699 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ 1700 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ 1701 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ 1702 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ 1703 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ 1704 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ 1705 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ 1706 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ 1707 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ 1708 #define WTIMER_DTFC_DTPRS0FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS0FSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ 1709 #define _WTIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */ 1710 #define _WTIMER_DTFC_DTPRS1FSEL_MASK 0x1F00UL /**< Bit mask for TIMER_DTPRS1FSEL */ 1711 #define _WTIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 1712 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for WTIMER_DTFC */ 1713 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for WTIMER_DTFC */ 1714 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for WTIMER_DTFC */ 1715 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for WTIMER_DTFC */ 1716 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for WTIMER_DTFC */ 1717 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for WTIMER_DTFC */ 1718 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for WTIMER_DTFC */ 1719 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for WTIMER_DTFC */ 1720 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for WTIMER_DTFC */ 1721 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for WTIMER_DTFC */ 1722 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for WTIMER_DTFC */ 1723 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for WTIMER_DTFC */ 1724 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for WTIMER_DTFC */ 1725 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for WTIMER_DTFC */ 1726 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for WTIMER_DTFC */ 1727 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for WTIMER_DTFC */ 1728 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for WTIMER_DTFC */ 1729 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for WTIMER_DTFC */ 1730 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for WTIMER_DTFC */ 1731 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for WTIMER_DTFC */ 1732 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for WTIMER_DTFC */ 1733 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for WTIMER_DTFC */ 1734 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for WTIMER_DTFC */ 1735 #define _WTIMER_DTFC_DTPRS1FSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for WTIMER_DTFC */ 1736 #define WTIMER_DTFC_DTPRS1FSEL_DEFAULT (_WTIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 1737 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH0 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for WTIMER_DTFC */ 1738 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH1 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for WTIMER_DTFC */ 1739 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH2 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for WTIMER_DTFC */ 1740 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH3 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for WTIMER_DTFC */ 1741 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH4 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for WTIMER_DTFC */ 1742 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH5 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for WTIMER_DTFC */ 1743 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH6 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for WTIMER_DTFC */ 1744 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH7 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for WTIMER_DTFC */ 1745 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH8 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for WTIMER_DTFC */ 1746 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH9 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for WTIMER_DTFC */ 1747 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH10 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for WTIMER_DTFC */ 1748 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH11 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for WTIMER_DTFC */ 1749 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH12 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH12 << 8) /**< Shifted mode PRSCH12 for WTIMER_DTFC */ 1750 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH13 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH13 << 8) /**< Shifted mode PRSCH13 for WTIMER_DTFC */ 1751 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH14 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH14 << 8) /**< Shifted mode PRSCH14 for WTIMER_DTFC */ 1752 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH15 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH15 << 8) /**< Shifted mode PRSCH15 for WTIMER_DTFC */ 1753 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH16 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH16 << 8) /**< Shifted mode PRSCH16 for WTIMER_DTFC */ 1754 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH17 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH17 << 8) /**< Shifted mode PRSCH17 for WTIMER_DTFC */ 1755 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH18 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH18 << 8) /**< Shifted mode PRSCH18 for WTIMER_DTFC */ 1756 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH19 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH19 << 8) /**< Shifted mode PRSCH19 for WTIMER_DTFC */ 1757 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH20 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH20 << 8) /**< Shifted mode PRSCH20 for WTIMER_DTFC */ 1758 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH21 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH21 << 8) /**< Shifted mode PRSCH21 for WTIMER_DTFC */ 1759 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH22 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH22 << 8) /**< Shifted mode PRSCH22 for WTIMER_DTFC */ 1760 #define WTIMER_DTFC_DTPRS1FSEL_PRSCH23 (_WTIMER_DTFC_DTPRS1FSEL_PRSCH23 << 8) /**< Shifted mode PRSCH23 for WTIMER_DTFC */ 1761 #define _WTIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ 1762 #define _WTIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ 1763 #define _WTIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 1764 #define _WTIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for WTIMER_DTFC */ 1765 #define _WTIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for WTIMER_DTFC */ 1766 #define _WTIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for WTIMER_DTFC */ 1767 #define _WTIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for WTIMER_DTFC */ 1768 #define WTIMER_DTFC_DTFA_DEFAULT (_WTIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 1769 #define WTIMER_DTFC_DTFA_NONE (_WTIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for WTIMER_DTFC */ 1770 #define WTIMER_DTFC_DTFA_INACTIVE (_WTIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for WTIMER_DTFC */ 1771 #define WTIMER_DTFC_DTFA_CLEAR (_WTIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for WTIMER_DTFC */ 1772 #define WTIMER_DTFC_DTFA_TRISTATE (_WTIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for WTIMER_DTFC */ 1773 #define WTIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ 1774 #define _WTIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ 1775 #define _WTIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ 1776 #define _WTIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 1777 #define WTIMER_DTFC_DTPRS0FEN_DEFAULT (_WTIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 1778 #define WTIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ 1779 #define _WTIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ 1780 #define _WTIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ 1781 #define _WTIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 1782 #define WTIMER_DTFC_DTPRS1FEN_DEFAULT (_WTIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 1783 #define WTIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ 1784 #define _WTIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ 1785 #define _WTIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ 1786 #define _WTIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 1787 #define WTIMER_DTFC_DTDBGFEN_DEFAULT (_WTIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 1788 #define WTIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ 1789 #define _WTIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ 1790 #define _WTIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ 1791 #define _WTIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFC */ 1792 #define WTIMER_DTFC_DTLOCKUPFEN_DEFAULT (_WTIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for WTIMER_DTFC */ 1793 1794 /* Bit fields for WTIMER DTOGEN */ 1795 #define _WTIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTOGEN */ 1796 #define _WTIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for WTIMER_DTOGEN */ 1797 #define WTIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */ 1798 #define _WTIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ 1799 #define _WTIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ 1800 #define _WTIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 1801 #define WTIMER_DTOGEN_DTOGCC0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 1802 #define WTIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */ 1803 #define _WTIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ 1804 #define _WTIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ 1805 #define _WTIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 1806 #define WTIMER_DTOGEN_DTOGCC1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 1807 #define WTIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */ 1808 #define _WTIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ 1809 #define _WTIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ 1810 #define _WTIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 1811 #define WTIMER_DTOGEN_DTOGCC2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 1812 #define WTIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */ 1813 #define _WTIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ 1814 #define _WTIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ 1815 #define _WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 1816 #define WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 1817 #define WTIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */ 1818 #define _WTIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ 1819 #define _WTIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ 1820 #define _WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 1821 #define WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 1822 #define WTIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */ 1823 #define _WTIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ 1824 #define _WTIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ 1825 #define _WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTOGEN */ 1826 #define WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_WTIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for WTIMER_DTOGEN */ 1827 1828 /* Bit fields for WTIMER DTFAULT */ 1829 #define _WTIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULT */ 1830 #define _WTIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULT */ 1831 #define WTIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ 1832 #define _WTIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ 1833 #define _WTIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ 1834 #define _WTIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ 1835 #define WTIMER_DTFAULT_DTPRS0F_DEFAULT (_WTIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ 1836 #define WTIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ 1837 #define _WTIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ 1838 #define _WTIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ 1839 #define _WTIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ 1840 #define WTIMER_DTFAULT_DTPRS1F_DEFAULT (_WTIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ 1841 #define WTIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ 1842 #define _WTIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ 1843 #define _WTIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ 1844 #define _WTIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ 1845 #define WTIMER_DTFAULT_DTDBGF_DEFAULT (_WTIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ 1846 #define WTIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ 1847 #define _WTIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ 1848 #define _WTIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ 1849 #define _WTIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULT */ 1850 #define WTIMER_DTFAULT_DTLOCKUPF_DEFAULT (_WTIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULT */ 1851 1852 /* Bit fields for WTIMER DTFAULTC */ 1853 #define _WTIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTFAULTC */ 1854 #define _WTIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for WTIMER_DTFAULTC */ 1855 #define WTIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ 1856 #define _WTIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ 1857 #define _WTIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ 1858 #define _WTIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ 1859 #define WTIMER_DTFAULTC_DTPRS0FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ 1860 #define WTIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ 1861 #define _WTIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ 1862 #define _WTIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ 1863 #define _WTIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ 1864 #define WTIMER_DTFAULTC_DTPRS1FC_DEFAULT (_WTIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ 1865 #define WTIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ 1866 #define _WTIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ 1867 #define _WTIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ 1868 #define _WTIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ 1869 #define WTIMER_DTFAULTC_DTDBGFC_DEFAULT (_WTIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ 1870 #define WTIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ 1871 #define _WTIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */ 1872 #define _WTIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */ 1873 #define _WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTFAULTC */ 1874 #define WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_WTIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for WTIMER_DTFAULTC */ 1875 1876 /* Bit fields for WTIMER DTLOCK */ 1877 #define _WTIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for WTIMER_DTLOCK */ 1878 #define _WTIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for WTIMER_DTLOCK */ 1879 #define _WTIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ 1880 #define _WTIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ 1881 #define _WTIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for WTIMER_DTLOCK */ 1882 #define _WTIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WTIMER_DTLOCK */ 1883 #define _WTIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WTIMER_DTLOCK */ 1884 #define _WTIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for WTIMER_DTLOCK */ 1885 #define _WTIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for WTIMER_DTLOCK */ 1886 #define WTIMER_DTLOCK_LOCKKEY_DEFAULT (_WTIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WTIMER_DTLOCK */ 1887 #define WTIMER_DTLOCK_LOCKKEY_UNLOCKED (_WTIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for WTIMER_DTLOCK */ 1888 #define WTIMER_DTLOCK_LOCKKEY_LOCK (_WTIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WTIMER_DTLOCK */ 1889 #define WTIMER_DTLOCK_LOCKKEY_LOCKED (_WTIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for WTIMER_DTLOCK */ 1890 #define WTIMER_DTLOCK_LOCKKEY_UNLOCK (_WTIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WTIMER_DTLOCK */ 1891 1892 /** @} */ 1893 /** @} End of group EFM32GG11B820F2048GL120_WTIMER */ 1894 1895 #include "efm32gg11b_uart.h" 1896 1897 /***************************************************************************//** 1898 * @defgroup EFM32GG11B820F2048GL120_UNLOCK Unlock Codes 1899 * @{ 1900 ******************************************************************************/ 1901 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ 1902 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ 1903 #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ 1904 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ 1905 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ 1906 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ 1907 #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ 1908 1909 /** @} End of group EFM32GG11B820F2048GL120_UNLOCK */ 1910 1911 /** @} End of group EFM32GG11B820F2048GL120_BitFields */ 1912 1913 #include "efm32gg11b_af_ports.h" 1914 #include "efm32gg11b_af_pins.h" 1915 1916 /** @} End of group EFM32GG11B820F2048GL120 */ 1917 1918 /** @} End of group Parts */ 1919 1920 #ifdef __cplusplus 1921 } 1922 #endif 1923 #endif /* EFM32GG11B820F2048GL120_H */ 1924
