1 /*
2 * SPDX-FileCopyrightText: 2019-2025 SiFli Technologies(Nanjing) Co., Ltd
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <string.h>
8 #include "flash_table.h"
9
10
11 typedef enum
12 {
13 NAND_TYPE0 = 0, // normal type, base on winbond w25n01gw, with NON-BUF, NO QE, EB with 4 dummy
14 NAND_TYPE1, // based on XT26G01D, BUF, QE, EB, EB with 2 dummy
15 NAND_TYPE2, // based on ds35x1gaxxx, BUF , QE, NO EB
16 NAND_TYPE3, // based on tc58cyg0s3hraij, BUF, NO QE, NO EB
17 NAND_TYPE4, // based on FM25LS01, BUF, NO QE, EB with 4 dummy
18 NAND_TYPE5, // based on GD5F1GM7RE, BUF, QE, EB, EB with 4 dummy
19 NAND_CMD_TABLE_CNT
20 } NAND_CMD_TABLE_ID_T;
21
22
23 __weak FT_CONST SPI_FLASH_FACT_CFG_T nand_cmd_table_list[] =
24 {
25 {
26 //winb_w25n01gw_ops
27 1, /* NAND flash */
28 0XEF, /* winbond manuf id */
29 0xba, /* Device ID*/
30 0x21, /* device id, for winbond, they have 16 bit device, just use 8 now */
31 0xC0, /* bit0 as busy, bit1 as WEL */
32 0xA0, /* protect, WPE */
33 0xB0, /* bit3 as buf mode, bit4 as ECC-C */
34 0x30, /* bit 4 and 5 in status register C0*/
35 0x00, /* not support QE configure */
36 0x08, /* bit 3 in mode register B0 for continue mode*/
37 0x10, /* bit 4 in mode register B0 for ecc enable */
38 64,
39 131072, /* 128KB */
40 {
41 {0x06, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_WREN*/
42 {0x04, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_WRDI*/
43 {0x0f, 0, 1, 0, 0, 0, 0, 1, 1}, /* SPI_FLASH_CMD_RDSR*/
44 {0x1f, 1, 1, 0, 0, 0, 0, 1, 1}, /* SPI_FLASH_CMD_WRSR*/
45 {0x13, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_PREAD*/
46 {0x03, 0, 1, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_READ*/
47 {0x0b, 0, 1, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_FREAD*/
48 {0x3b, 0, 2, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_DREAD*/
49 {0x6b, 0, 3, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QREAD*/
50 {0xbb, 0, 2, 4, 0, 0, 1, 2, 1}, /* SPI_FLASH_CMD_2READ*/
51 {0xeb, 0, 3, 4, 0, 0, 1, 3, 1}, /* SPI_FLASH_CMD_4READ*/
52 {0x9f, 0, 1, 8, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_RDID*/
53 {0x02, 1, 1, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_PLD*/
54 {0x32, 1, 3, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QPLD*/
55 {0x84, 1, 1, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_PLDR*/
56 {0x34, 1, 3, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QPLDR*/
57 {0x10, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_PEXE*/
58 {0xd8, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_BE*/
59 {0xff, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_RST*/
60 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RST_EN*/
61 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSR2*/
62 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WVSR*/
63 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PP*/
64 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_QPP*/
65 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDEAR*/
66 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WREAR*/
67 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PE*/
68 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_SE*/
69 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE32*/
70 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE64*/
71 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_CE*/
72 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSR3*/
73 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WRSR3*/
74 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_EN4BM*/
75 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_ET4BM*/
76 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RD4BA*/
77 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_FR4BA*/
78 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_FQR4BA*/
79 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_4RD4BA*/
80 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PP4BA*/
81 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_QPP4BA*/
82 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_SE4BA*/
83 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE4BA*/
84 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WRSR2*/
85 {0xA9, 0, 1, 8, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_LEFPA*/
86 {0xA1, 0, 0, 0, 0, 0, 3, 1, 1}, /* SPI_FLASH_CMD_BBM*/
87 {0xA5, 0, 1, 8, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_RBLUT*/
88 {0x0B, 0, 3, 32, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_CFREAD*/
89 {0xEB, 0, 3, 12, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_C4READ*/
90 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RUID*/
91 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSCUR*/
92 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PRSCUR*/
93 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_ERSCUR*/
94 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_DPD*/
95 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDP*/
96 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_DTR4R*/
97 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSFDP*/
98 }
99 },
100 {
101 //gd5f1gq4xc_ops
102 1, /* NAND flash */
103 0XC8, /* giga device manuf id */
104 0xA1, /* Device ID*/
105 0x48, /* device id, for winbond, they have 16 bit device, just use 8 now */
106 0xC0, /* bit0 as busy, bit1 as WEL */
107 0xA0, /* protect, WPE */
108 0xB0, /* bit3 as buf mode, bit4 as ECC-C */
109 0x30, /* bit 4 and 5 and 6in status register C0*/
110 0x01, /* bit 1 in mode register B0 for QE set*/
111 0x00, /* Not support continue mode, only buf mode */
112 0x10, /* bit 4 in mode register B0 for ecc enable*/
113 128,
114 131072, /* 128KB */
115 {
116 {0x06, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_WREN*/
117 {0x04, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_WRDI*/
118 {0x0F, 0, 1, 0, 0, 0, 0, 1, 1}, /* SPI_FLASH_CMD_RDSR*/
119 {0x1F, 1, 1, 0, 0, 0, 0, 1, 1}, /* SPI_FLASH_CMD_WRSR*/
120 {0x13, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_PREAD*/
121 {0x03, 0, 1, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_READ*/
122 {0x0b, 0, 1, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_FREAD*/
123 {0x3b, 0, 2, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_DREAD*/
124 {0x6b, 0, 3, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QREAD*/
125 {0xbb, 0, 2, 4, 0, 0, 1, 2, 1}, /* SPI_FLASH_CMD_2READ*/
126 {0xeb, 0, 3, 2, 0, 0, 1, 3, 1}, /* SPI_FLASH_CMD_4READ*/
127 {0x9f, 0, 1, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_RDID*/
128 {0x02, 1, 1, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_PLD*/
129 {0x32, 1, 3, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QPLD*/
130 {0x84, 1, 1, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_PLDR*/
131 {0x34, 1, 3, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QPLDR*/
132 {0x10, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_PEXE*/
133 {0xd8, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_BE*/
134 {0xff, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_RST*/
135 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RST_EN*/
136 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSR2*/
137 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WVSR*/
138 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PP*/
139 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_QPP*/
140 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDEAR*/
141 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WREAR*/
142 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PE*/
143 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_SE*/
144 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE32*/
145 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE64*/
146 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_CE*/
147 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSR3*/
148 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WRSR3*/
149 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_EN4BM*/
150 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_ET4BM*/
151 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RD4BA*/
152 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_FR4BA*/
153 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_FQR4BA*/
154 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_4RD4BA*/
155 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PP4BA*/
156 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_QPP4BA*/
157 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_SE4BA*/
158 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE4BA*/
159 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WRSR2*/
160 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_LEFPA*/
161 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BBM*/
162 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RBLUT*/
163 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_CFREAD*/
164 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_C4READ*/
165 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RUID*/
166 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSCUR*/
167 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PRSCUR*/
168 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_ERSCUR*/
169 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_DPD*/
170 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDP*/
171 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_DTR4R*/
172 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSFDP*/
173 }
174 },
175 {
176 //ds35x1gaxxx_ops
177 1, /* NAND flash */
178 0XE5, /* manuf id */
179 0x21, /* Device ID*/
180 0XE5, /* device id, for winbond, they have 16 bit device, just use 8 now */
181 0xC0, /* bit0 as busy, bit1 as WEL */
182 0xA0, /* protect, WPE */
183 0xB0, /* bit3 as buf mode, bit4 as ECC-C */
184 0x30, /* bit 4 and 5 in status register C0*/
185 0x01, /* bit 1 in mode register B0 for QE set*/
186 0x00, /* Not support continue mode, only buf mode */
187 0x10, /* bit 4 in mode register B0 for ecc enable*/
188 64,
189 131072, /* 128KB */
190 {
191 {0x06, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_WREN*/
192 {0x04, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_WRDI*/
193 {0x0F, 0, 1, 0, 0, 0, 0, 1, 1}, /* SPI_FLASH_CMD_RDSR*/
194 {0x1F, 1, 1, 0, 0, 0, 0, 1, 1}, /* SPI_FLASH_CMD_WRSR*/
195 {0x13, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_PREAD*/
196 {0x03, 0, 1, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_READ*/
197 {0x0b, 0, 1, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_FREAD*/
198 {0x3b, 0, 2, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_DREAD*/
199 {0x6b, 0, 3, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QREAD*/
200 {0xbb, 0, 2, 4, 0, 0, 1, 2, 1}, /* SPI_FLASH_CMD_2READ*/
201 // {0xeb, 0, 3, 4, 0, 0, 1, 3}, /* SPI_FLASH_CMD_4READ*/
202 {0x6b, 0, 3, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_4READ*/
203 {0x9f, 0, 1, 8, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_RDID*/
204 {0x02, 1, 1, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_PLD*/
205 {0x32, 1, 3, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QPLD*/
206 {0x84, 1, 1, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_PLDR*/
207 {0x34, 1, 3, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QPLDR*/
208 {0x10, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_PEXE*/
209 {0xd8, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_BE*/
210 {0xff, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_RST*/
211 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RST_EN*/
212 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSR2*/
213 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WVSR*/
214 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PP*/
215 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_QPP*/
216 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDEAR*/
217 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WREAR*/
218 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PE*/
219 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_SE*/
220 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE32*/
221 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE64*/
222 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_CE*/
223 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSR3*/
224 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WRSR3*/
225 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_EN4BM*/
226 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_ET4BM*/
227 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RD4BA*/
228 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_FR4BA*/
229 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_FQR4BA*/
230 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_4RD4BA*/
231 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PP4BA*/
232 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_QPP4BA*/
233 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_SE4BA*/
234 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE4BA*/
235 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WRSR2*/
236 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_LEFPA*/
237 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BBM*/
238 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RBLUT*/
239 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_CFREAD*/
240 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_C4READ*/
241 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RUID*/
242 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSCUR*/
243 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PRSCUR*/
244 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_ERSCUR*/
245 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_DPD*/
246 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDP*/
247 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_DTR4R*/
248 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSFDP*/
249 }
250 },
251 {
252 //kioxia_tc58cyg0s3hraij_ops
253 1, /* NAND flash */
254 0X98, /* manufacture ID : KIOXIA*/
255 0xd2, /* Device ID*/
256 0X40, /* Organization ID */
257 0xC0, /* status regiser ,bit0 as busy, bit1 as WEL */
258 0xA0, /* protect register address, WPE */
259 0xB0, /* for qe/continue/ecc-e mode register */
260 0x30, /* ecc status bits: bit 4 and 5 in status register C0*/
261 0x00, /* no need set qe setting bits*/
262 0x00, /* Not support continue mode, only buf mode */
263 0x10, /* ecc enable bits: 4 in mode register B0*/
264 64,
265 131072, /* 128KB */
266 {
267 {0x06, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_WREN*/
268 {0x04, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_WRDI*/
269 {0x0F, 0, 1, 0, 0, 0, 0, 1, 1}, /* SPI_FLASH_CMD_RDSR*/
270 {0x1F, 1, 1, 0, 0, 0, 0, 1, 1}, /* SPI_FLASH_CMD_WRSR*/
271 {0x13, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_PREAD*/
272 {0x03, 0, 1, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_READ*/
273 {0x0b, 0, 1, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_FREAD*/
274 {0x3b, 0, 2, 8, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_DREAD*/
275 {0x6b, 0, 3, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QREAD*/
276 {0xbb, 0, 2, 4, 0, 0, 1, 2, 1}, /* SPI_FLASH_CMD_2READ*/
277 // {0xeb, 0, 3, 4, 0, 0, 1, 3}, /* SPI_FLASH_CMD_4READ*/
278 {0x6b, 0, 3, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_4READ*/
279 {0x9f, 0, 1, 8, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_RDID*/
280 {0x02, 1, 1, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_PLD*/
281 {0x32, 1, 3, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QPLD*/
282 {0x84, 1, 1, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_PLDR*/
283 {0x34, 1, 3, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QPLDR*/
284 {0x10, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_PEXE*/
285 {0xd8, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_BE*/
286 {0xff, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_RST*/
287 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RST_EN*/
288 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSR2*/
289 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WVSR*/
290 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PP*/
291 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_QPP*/
292 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDEAR*/
293 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WREAR*/
294 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PE*/
295 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_SE*/
296 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE32*/
297 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE64*/
298 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_CE*/
299 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSR3*/
300 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WRSR3*/
301 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_EN4BM*/
302 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_ET4BM*/
303 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RD4BA*/
304 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_FR4BA*/
305 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_FQR4BA*/
306 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_4RD4BA*/
307 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PP4BA*/
308 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_QPP4BA*/
309 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_SE4BA*/
310 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE4BA*/
311 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WRSR2*/
312 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_LEFPA*/
313 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BBM*/
314 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RBLUT*/
315 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_CFREAD*/
316 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_C4READ*/
317 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RUID*/
318 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSCUR*/
319 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PRSCUR*/
320 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_ERSCUR*/
321 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_DPD*/
322 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDP*/
323 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_DTR4R*/
324 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSFDP*/
325 }
326 },
327 {
328 //FUDAN_FM25LS01_ops
329 1, /* NAND flash */
330 0XA1, /* manufacture ID : FUDAN MICRO*/
331 0xA5, /* Device ID*/
332 0X7F, /* Organization ID, NO USE FOR this type */
333 0xC0, /* status regiser ,bit0 as busy, bit1 as WEL */
334 0xA0, /* protect register address, WPE */
335 0xB0, /* for qe/continue/ecc-e mode register */
336 0x30, /* ecc status bits: bit 4 and 5 in status register C0*/
337 0x00, /* no need set qe setting bits*/
338 0x00, /* Not support continue mode, only buf mode */
339 0x10, /* ecc enable bits: 4 in mode register B0*/
340 64,
341 131072, /* 128KB */
342 {
343 {0x06, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_WREN*/
344 {0x04, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_WRDI*/
345 {0x0F, 0, 1, 0, 0, 0, 0, 1, 1}, /* SPI_FLASH_CMD_RDSR*/
346 {0x1F, 1, 1, 0, 0, 0, 0, 1, 1}, /* SPI_FLASH_CMD_WRSR*/
347 {0x13, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_PREAD*/
348 {0x03, 0, 1, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_READ*/
349 {0x0b, 0, 1, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_FREAD*/
350 {0x3b, 0, 2, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_DREAD*/
351 {0x6b, 0, 3, 8, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QREAD*/
352 {0xbb, 0, 2, 4, 0, 0, 1, 2, 1}, /* SPI_FLASH_CMD_2READ*/
353 {0xeb, 0, 3, 4, 0, 0, 1, 3, 1}, /* SPI_FLASH_CMD_4READ*/
354 {0x9f, 0, 1, 8, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_RDID*/
355 {0x02, 1, 1, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_PLD*/
356 {0x32, 1, 3, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QPLD*/
357 {0x84, 1, 1, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_PLDR*/
358 {0x34, 1, 3, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QPLDR*/
359 {0x10, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_PEXE*/
360 {0xd8, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_BE*/
361 {0xff, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_RST*/
362 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RST_EN*/
363 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSR2*/
364 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WVSR*/
365 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PP*/
366 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_QPP*/
367 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDEAR*/
368 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WREAR*/
369 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PE*/
370 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_SE*/
371 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE32*/
372 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE64*/
373 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_CE*/
374 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSR3*/
375 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WRSR3*/
376 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_EN4BM*/
377 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_ET4BM*/
378 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RD4BA*/
379 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_FR4BA*/
380 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_FQR4BA*/
381 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_4RD4BA*/
382 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PP4BA*/
383 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_QPP4BA*/
384 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_SE4BA*/
385 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE4BA*/
386 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WRSR2*/
387 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_LEFPA*/
388 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BBM*/
389 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RBLUT*/
390 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_CFREAD*/
391 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_C4READ*/
392 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RUID*/
393 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSCUR*/
394 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PRSCUR*/
395 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_ERSCUR*/
396 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_DPD*/
397 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDP*/
398 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_DTR4R*/
399 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSFDP*/
400 }
401 },
402 {
403 //gd5f1gm7re_ops
404 1, /* NAND flash */
405 0XC8, /* winbond manuf id */
406 0x81, /* Device ID*/
407 0xC8, /* device id, for winbond, they have 16 bit device, just use 8 now */
408 0xC0, /* bit0 as busy, bit1 as WEL */
409 0xA0, /* protect, WPE */
410 0xB0, /* bit3 as buf mode, bit4 as ECC-C */
411 0x30, /* bit 4 and 5 in status register C0*/
412 0x01, /* bit 1 in mode register B0 for QE set*/
413 0x00, /* Not support continue mode, only buf mode */
414 0x10, /* bit 4 in mode register B0 for ecc enable*/
415 128,
416 131072, /* 128KB */
417 {
418 {0x06, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_WREN*/
419 {0x04, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_WRDI*/
420 {0x0F, 0, 1, 0, 0, 0, 0, 1, 1}, /* SPI_FLASH_CMD_RDSR*/
421 {0x1F, 1, 1, 0, 0, 0, 0, 1, 1}, /* SPI_FLASH_CMD_WRSR*/
422 {0x13, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_PREAD*/
423 {0x03, 0, 1, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_READ*/
424 {0x0b, 0, 1, 8, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_FREAD*/
425 {0x3b, 0, 2, 8, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_DREAD*/
426 {0x6b, 0, 3, 8, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_QREAD*/
427 {0xbb, 0, 2, 4, 0, 0, 1, 2, 1}, /* SPI_FLASH_CMD_2READ*/
428 {0xeb, 0, 3, 4, 0, 0, 1, 3, 1}, /* SPI_FLASH_CMD_4READ*/
429 {0x9f, 0, 1, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_RDID*/
430 {0x02, 1, 1, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_PLD*/
431 {0x32, 1, 3, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QPLD*/
432 {0x84, 1, 1, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_PLDR*/
433 {0x34, 1, 3, 0, 0, 0, 1, 1, 1}, /* SPI_FLASH_CMD_QPLDR*/
434 {0x10, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_PEXE*/
435 {0xd8, 0, 0, 0, 0, 0, 2, 1, 1}, /* SPI_FLASH_CMD_BE*/
436 {0xff, 0, 0, 0, 0, 0, 0, 0, 1}, /* SPI_FLASH_CMD_RST*/
437 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RST_EN*/
438 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSR2*/
439 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WVSR*/
440 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PP*/
441 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_QPP*/
442 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDEAR*/
443 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WREAR*/
444 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PE*/
445 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_SE*/
446 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE32*/
447 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE64*/
448 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_CE*/
449 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSR3*/
450 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WRSR3*/
451 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_EN4BM*/
452 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_ET4BM*/
453 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RD4BA*/
454 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_FR4BA*/
455 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_FQR4BA*/
456 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_4RD4BA*/
457 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PP4BA*/
458 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_QPP4BA*/
459 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_SE4BA*/
460 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BE4BA*/
461 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_WRSR2*/
462 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_LEFPA*/
463 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_BBM*/
464 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RBLUT*/
465 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_CFREAD*/
466 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_C4READ*/
467 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RUID*/
468 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSCUR*/
469 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_PRSCUR*/
470 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_ERSCUR*/
471 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_DPD*/
472 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDP*/
473 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_DTR4R*/
474 {0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SPI_FLASH_CMD_RDSFDP*/
475 }
476 },
477 };
478
479 FT_CONST FLASH_RDID_TYPE_T nand_cmd_id_pool_type0[] =
480 {
481 {0xef, 0xba, 0x21, 0, 0x8000000}, //W25N01GW_RDID
482 {0xef, 0xaa, 0x21, 0, 0x8000000}, //W25N01GV_RDID
483 {0xef, 0xba, 0x23, 0, 0x20000000}, //W25N04KW_RDID
484 {FLASH_INVALID_ID, 0, 0, 0, 0}, //last one
485 };
486
487 FT_CONST FLASH_RDID_TYPE_T nand_cmd_id_pool_type1[] =
488 {
489 {0xC9, 0x81, 0x00, 0x10, 0x8000000}, //HYF1GQ4IDACAE_RDID
490 {0x81, 0xc9, 0x81, 0x10, 0x8000000}, //HYF1GQ4IDACAE_RDID
491 {0x01, 0x81, 0xc9, 0x10, 0x8000000}, //HYF1GQ4IDACAE_RDID
492 {0x01, 0xc9, 0x81, 0x10, 0x8000000}, //HYF1GQ4IDACAE_RDID
493 {0x5e, 0x44, 0x5e, 0, 0x20000000}, //ZB35Q04A_RDID, used as 2KB page
494 {0x0b, 0x31, 0x00, 0x40, 0x8000000}, //XT26G01DXXX_RDID
495 {0x8c, 0x01, 0x8c, 0x10, 0x8000000}, //XCSP1AAPK-IT_RDID
496 {0x8c, 0xb1, 0x8c, 0x18, 0x20000000}, //XCSP4AAPK-IT_RDID
497 {0x0b, 0x33, 0X00, 0x44, 0x20000000},//XT26G04DXXX_RDID
498 {0xc8, 0xd9, 0xc8, 0x10, 0x8000000}, //GD5F1GQ4UxxH_RDID
499 {0xc8, 0xc9, 0xc8, 0x10, 0x8000000}, //GD5F1GQ4RxxH_RDID
500 {FLASH_INVALID_ID, 0, 0, 0, 0}, //last one
501 };
502
503 FT_CONST FLASH_RDID_TYPE_T nand_cmd_id_pool_type2[] =
504 {
505 {0xE5, 0x21, 0XE5, 0, 0x8000000}, //DS35X1GAXXX_RDID
506 {0xE5, 0xA5, 0XE5, 0x20, 0x4000000}, //DS35M12BXXX_RDID
507 {0xE5, 0xF5, 0XE5, 0x20, 0x4000000}, //DS35Q12BXXX_RDID
508 {0xE5, 0xF1, 0XE5, 0x20, 0x8000000}, //DS35Q1GBXXX_RDID
509 {0xE5, 0xA1, 0XE5, 0x20, 0x8000000}, //DS35M1GBXXX_RDID
510 {0xE5, 0xA2, 0XE5, 0x22, 0x10000000}, //DS35M2GBXXX_RDID
511 {0xE5, 0xF4, 0XE5, 0x22, 0x20000000}, //DS35X4GMXXX_RDID rev01
512 {0xE5, 0x74, 0xE5, 0x22, 0x20000000}, //DS35X4GMXXX_RDID diff version?
513 {0xE5, 0xB4, 0XE5, 0x20, 0x20000000}, //DS35Q4GBXXX_RDID
514 {0xE5, 0x75, 0XE5, 0x20, 0x4000000}, //DS35Q12CXXX_RDID
515 {0xCD, 0x70, 0X70, 0, 0x4000000}, //F35SQA512MX_RDID
516 {0xCD, 0x60, 0X60, 0, 0x4000000}, //F35UQA512MXXX_RDID
517 {0xCD, 0x61, 0x61, 0, 0x8000000}, //F35UQA001GXXX_RDID
518 {0xCD, 0x71, 0X71, 0, 0x8000000}, //F35SQA0001GXXX_RDID
519 {0xCD, 0x72, 0X72, 0, 0x10000000}, //F35SQA0002GXXX_RDID
520 {0xCD, 0x53, 0X53, 0x34, 0x20000000}, //F35SQB004G_RDID
521 {0x0B, 0x51, 0X00, 0x40, 0x8000000}, //XT26Q01DXXX_RDID
522 {0x0B, 0x11, 0X00, 0x50, 0x8000000}, //XT26G01CXXX_RDID
523 {0x3C, 0xD1, 0xD1, 0, 0x8000000}, //HSESYHDSW1G_RDID
524 {0x3C, 0xD2, 0xD2, 0, 0x10000000}, //HSESYHDSW2G_RDID
525 {0xa1, 0xd4, 0xa1, 0x20, 0x8000000}, //FM25S01BI3_RDID
526 {0xc9, 0xd4, 0xc9, 0x14, 0x20000000}, //HYF4GQ4UAACBE_RDID
527 {0xE5, 0xB2, 0XE5, 0x20, 0x10000000}, //DS35Q2GBS-IB_RDID
528 {0xB0, 0x14, 0xB0, 0x20, 0x8000000}, //UM19A0HISW_RDID
529 {FLASH_INVALID_ID, 0, 0, 0, 0}, //last one
530 };
531
532 FT_CONST FLASH_RDID_TYPE_T nand_cmd_id_pool_type3[] =
533 {
534 {0x98, 0xd2, 0X40, 0x10, 0x8000000}, //TC58CYG0S3HRAIJ_RDID
535 {0x3C, 0xD1, 0x3C, 0, 0x8000000}, //HSESDDDSW1G_RDID
536 {0x01, 0x15, 0X01, 0x60, 0x8000000}, //HYF1GQ4UTXCAE_RDID
537 {0x01, 0x35, 0X01, 0x60, 0x20000000}, //HYF4GQ4UTACAE_RDID
538 {FLASH_INVALID_ID, 0, 0, 0, 0}, //last one
539 };
540
541 FT_CONST FLASH_RDID_TYPE_T nand_cmd_id_pool_type4[] =
542 {
543 {0xa1, 0xa5, 0X7f, 0, 0x8000000}, //FM25LS01_RDID
544 {0xc9, 0x21, 0xc9, 0x10, 0x8000000}, //HYF1GQ4UDA_RDID
545 {0x5e, 0xa1, 0xa1, 0, 0x8000000}, //ZB35Q01B_RDID
546 {0x5e, 0xa2, 0xa1, 0, 0x10000000}, //ZB35Q02BYIG_RDID
547 {FLASH_INVALID_ID, 0, 0, 0, 0}, //last one
548 };
549
550 FT_CONST FLASH_RDID_TYPE_T nand_cmd_id_pool_type5[] =
551 {
552 {0xc8, 0x81, 0xc8, 0x10, 0x8000000}, //GD5F1GM7RE_RDID
553 {0xc8, 0x91, 0xc8, 0x10, 0x8000000}, //GD5F1GM7UE_RDID
554 {0xc8, 0x92, 0xc8, 0x10, 0x10000000}, //GD5F2GM7UE_RDID
555 {0xc8, 0x82, 0xc8, 0x10, 0x10000000}, //GD5F2GM7RE_RDID
556 {0xc8, 0x95, 0xc8, 0x10, 0x20000000}, //GD5F4GM8UE_RDID
557 {0xc8, 0x85, 0xc8, 0x10, 0x20000000}, //GD5F4GM8RE_RDID
558 {0x52, 0xCA, 0x13, 0x10, 0x8000000}, //GSS01GSAX1_RDID
559 {FLASH_INVALID_ID, 0, 0, 0, 0}, //last one
560 };
561
562
563 #if defined(JLINK) || defined(KEIL)
564 /* For Jlink device, as it does not have scatter loading, need assign this table in Jlink init code.*/
565 FLASH_RDID_TYPE_T *nand_cmd_id_pool[NAND_CMD_TABLE_CNT];
566 #else
567 /* For bootloader, need compress to reduce code size */
568 __weak FT_CONST FLASH_RDID_TYPE_T *FT_CONST nand_cmd_id_pool[] =
569 {
570 &nand_cmd_id_pool_type0[0], // type 0, NON-BUF,NO QE, EB with 4 dummy
571 &nand_cmd_id_pool_type1[0], // type 1, BUF, QE, EB, EB with 2 dummy
572 &nand_cmd_id_pool_type2[0], // type 2, BUF, QE, NO EB
573 &nand_cmd_id_pool_type3[0], // type 3, BUF, NO QE, NO EB
574 &nand_cmd_id_pool_type4[0], // type 4, BUF, NO QE, EB with 4 dummy
575 &nand_cmd_id_pool_type5[0], // type 5, BUF, QE, EB, EB with 4 dummy
576 };
577 #endif /* JLINK || KEIL */
578
579 #if defined(CFG_FACTORY_DEBUG)
get_user_flash_cfg(uint8_t isnand,uint8_t fid,uint8_t did,uint8_t type,uint8_t * flash_type)580 __WEAK void *get_user_flash_cfg(uint8_t isnand, uint8_t fid, uint8_t did, uint8_t type, uint8_t *flash_type)
581 {
582 return NULL;
583 }
584 #endif
585
586
587 #if defined(JLINK) || defined(KEIL)
spi_nand_table_init(void)588 __weak void spi_nand_table_init(void)
589 {
590 if (NAND_CMD_TABLE_CNT != 6)
591 {
592 while (1);
593 }
594
595 nand_cmd_id_pool[0] = &nand_cmd_id_pool_type0[0];
596 nand_cmd_id_pool[1] = &nand_cmd_id_pool_type1[0];
597 nand_cmd_id_pool[2] = &nand_cmd_id_pool_type2[0];
598 nand_cmd_id_pool[3] = &nand_cmd_id_pool_type3[0];
599 nand_cmd_id_pool[4] = &nand_cmd_id_pool_type4[0];
600 nand_cmd_id_pool[5] = &nand_cmd_id_pool_type5[0];
601 }
602 #endif /* JLINK || KEIL */
603
604
spi_nand_get_rdid(uint8_t fid,uint8_t did,uint8_t type,uint8_t * flash_type)605 FT_CONST FLASH_RDID_TYPE_T *spi_nand_get_rdid(uint8_t fid, uint8_t did, uint8_t type, uint8_t *flash_type)
606 {
607 int i;
608 FT_CONST FLASH_RDID_TYPE_T *res;
609
610 // check flash id valid
611 if ((fid == FLASH_INVALID_ID) || (fid == FLASH_UNKNOW_ID))
612 return NULL;
613
614 for (i = 0; i < NAND_CMD_TABLE_CNT; i++)
615 {
616 res = nand_cmd_id_pool[i];
617 while (res->manufacture_id != FLASH_INVALID_ID)
618 {
619 if (fid == res->manufacture_id &&
620 type == res->memory_type &&
621 did == res->memory_density)
622 break;
623 res++;
624 };
625 if (res->manufacture_id != FLASH_INVALID_ID) // Found flash ID
626 break;
627 }
628
629 if (i == NAND_CMD_TABLE_CNT)
630 {
631 #if defined(CFG_FACTORY_DEBUG)
632 res = (FLASH_RDID_TYPE_T *)get_user_flash_cfg(1, fid, did, type, flash_type);
633 #else
634 res = NULL;
635 #endif
636 }
637 else if (flash_type)
638 {
639 *flash_type = i;
640 }
641 return res;
642 }
643
644 // get command table by index from register table
spi_nand_get_cmd_by_id(uint8_t fid,uint8_t did,uint8_t type)645 const SPI_FLASH_FACT_CFG_T *spi_nand_get_cmd_by_id(uint8_t fid, uint8_t did, uint8_t type)
646 {
647 uint8_t i;
648 const SPI_FLASH_FACT_CFG_T *res = NULL;
649
650 FT_CONST FLASH_RDID_TYPE_T *rdid = spi_nand_get_rdid(fid, did, type, &i);
651 if (rdid)
652 res = (const SPI_FLASH_FACT_CFG_T *)&nand_cmd_table_list[i];
653
654 return res;
655 }
656
HAL_GET_FLASH_DEFAUT_INX(void)657 __weak int HAL_GET_FLASH_DEFAUT_INX(void)
658 {
659 return -1;
660 }
661
662 // get default command table if default index valid
spi_nand_get_default_ctable(void)663 const SPI_FLASH_FACT_CFG_T *spi_nand_get_default_ctable(void)
664 {
665 int deft;
666 const SPI_FLASH_FACT_CFG_T *res = NULL;
667
668 deft = HAL_GET_FLASH_DEFAUT_INX();
669 if (deft >= 0)
670 {
671 res = (const SPI_FLASH_FACT_CFG_T *)&nand_cmd_table_list[deft];
672 }
673
674 return res;
675 }
676
677 // get nand size by id from register table
spi_nand_get_size_by_id(uint8_t fid,uint8_t did,uint8_t type)678 int spi_nand_get_size_by_id(uint8_t fid, uint8_t did, uint8_t type)
679 {
680 int res = 0x4000000;
681
682 FT_CONST FLASH_RDID_TYPE_T *rdid = spi_nand_get_rdid(fid, did, type, NULL);
683 if (rdid)
684 res = rdid->mem_size;
685
686 return res;
687 }
688
689 // get plane slect flag by id from register table
spi_nand_get_plane_select_flag(uint8_t fid,uint8_t did,uint8_t type)690 int spi_nand_get_plane_select_flag(uint8_t fid, uint8_t did, uint8_t type)
691 {
692 int res = 0;
693
694 FT_CONST FLASH_RDID_TYPE_T *rdid = spi_nand_get_rdid(fid, did, type, NULL);
695 if (rdid && (rdid->ext_flags & PLANE_SELEC_FLAG) != 0)
696 res = 1;
697
698 return res;
699 }
700
spi_nand_get_big_page_flag(uint8_t fid,uint8_t did,uint8_t type)701 int spi_nand_get_big_page_flag(uint8_t fid, uint8_t did, uint8_t type)
702 {
703 int res = 0;
704
705 FT_CONST FLASH_RDID_TYPE_T *rdid = spi_nand_get_rdid(fid, did, type, NULL);
706 if (rdid)
707 res = (rdid->ext_flags & (BIG_PAGE_FLAG | BIG_BLK_FLAG)) >> 2;
708 return res;
709 }
710
spi_nand_get_ecc_mode(uint8_t fid,uint8_t did,uint8_t type)711 int spi_nand_get_ecc_mode(uint8_t fid, uint8_t did, uint8_t type)
712 {
713 int res = 0;
714
715 FT_CONST FLASH_RDID_TYPE_T *rdid = spi_nand_get_rdid(fid, did, type, NULL);
716 if (rdid)
717 res = (rdid->ext_flags & NAND_ECC_FULL_RESERVED) >> NAND_ECC_START_POS;
718 return res;
719 }
