1 /*
2 * SPDX-FileCopyrightText: 2019-2025 SiFli Technologies(Nanjing) Co., Ltd
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "bf0_hal.h"
8 #include <string.h>
9 #include "mem_map.h"
10 #include "rtconfig.h"
11 #include "register.h"
12 /** @addtogroup BF0_HAL_Driver
13 * @{
14 */
15
16 #ifdef HAL_SYSTEM_CONFIG_ENABLED
17
18 #if defined(LCPU_RUN_SEPERATE_IMG) || defined(LCPU_RUN_ROM_ONLY)
19 #define BSP_CFG_IN_HCPU (1)
20 #else
21 #define BSP_CFG_IN_HCPU (0)
22 #endif // SF32LB52X
23
24
25
26 //static uint32_t conf_buf[CFG_SYS_SIZE / 4];
27 HAL_RETM_BSS_SECT(sip1_mode, static uint8_t sip1_mode);
28 HAL_RETM_BSS_SECT(sip2_mode, static uint8_t sip2_mode);
29
30 static uint32_t conf_user[CFG_USER_SIZE / 4];
31 static uint32_t conf_cust[CFG_USER_SIZE / 4];
32
BSP_OTP_CFG_READ(uint8_t id,uint8_t * data,uint8_t size,uint8_t * buf,uint32_t buf_size)33 static uint8_t BSP_OTP_CFG_READ(uint8_t id, uint8_t *data, uint8_t size, uint8_t *buf, uint32_t buf_size)
34 {
35 int i = 0;
36 int len = 0;
37 uint32_t fac_cfg_size = 0;
38
39 if (buf == NULL)
40 {
41 return 0;
42 }
43 fac_cfg_size = buf_size ;
44
45 uint8_t *p = buf ;
46
47 while (p[i] != FACTORY_CFG_ID_UNINIT)
48 {
49 len = p[i + 1];
50 if (p[i] == id) // Found config
51 {
52 break;
53 }
54
55 if ((i + len + SYSCFG_FACTORY_HDR_SIZE) >= (int)fac_cfg_size) // More than max configuration area?
56 {
57 len = 0;
58 break;
59 }
60
61 i += (len + SYSCFG_FACTORY_HDR_SIZE); // Next config
62 len = 0;
63 }
64 if (len) // Found config
65 {
66 if (len > size)
67 len = size;
68 memcpy(data, &p[i + SYSCFG_FACTORY_HDR_SIZE], len);
69 }
70
71 return len;
72 }
73
BSP_OTP_CUST_CFG_READ(uint8_t id,uint8_t * data,uint8_t size,uint8_t * buf,uint32_t buf_size)74 static uint8_t BSP_OTP_CUST_CFG_READ(uint8_t id, uint8_t *data, uint8_t size, uint8_t *buf, uint32_t buf_size)
75 {
76 uint8_t res;
77 uint8_t *buf_user;
78 res = BSP_OTP_CFG_READ(id, data, size, buf, buf_size);
79 if (res > 0)
80 goto end;
81 buf_user = (uint8_t *)conf_user;
82 res = BSP_OTP_CFG_READ(id, data, size, buf_user, CFG_USER_SIZE);
83 if (res > 0)
84 goto end;
85 buf_user = (uint8_t *)conf_cust;
86 res = BSP_OTP_CFG_READ(id, data, size, buf_user, CFG_USER_SIZE);
87 end:
88 return res;
89 }
90
91 #ifndef SF32LB55X
BSP_GetFlashByAddr(uint32_t addr)92 static MPI_TypeDef *BSP_GetFlashByAddr(uint32_t addr)
93 {
94 MPI_TypeDef *fhandle = NULL;
95
96 if ((addr >= QSPI1_MEM_BASE) && (addr < (QSPI1_MEM_BASE + QSPI1_MAX_SIZE)))
97 fhandle = FLASH1;
98 else if ((addr >= QSPI2_MEM_BASE) && (addr < (QSPI2_MEM_BASE + QSPI2_MAX_SIZE)))
99 fhandle = FLASH2;
100 #ifdef FLASH3
101 else if ((addr >= QSPI3_MEM_BASE) && (addr < (QSPI3_MEM_BASE + QSPI3_MAX_SIZE)))
102 fhandle = FLASH3;
103 #endif
104 #ifdef FLASH4
105 else if ((addr >= QSPI4_MEM_BASE) && (addr < (QSPI4_MEM_BASE + QSPI4_MAX_SIZE)))
106 fhandle = FLASH4;
107 #endif
108 #ifdef FLASH5
109 else if ((addr >= QSPI5_MEM_BASE) && (addr < (QSPI5_MEM_BASE + QSPI5_MAX_SIZE)))
110 fhandle = FLASH5;
111 #endif
112 return fhandle;
113 }
114 #else //!55x
BSP_GetFlashByAddr(uint32_t addr)115 static QSPI_TypeDef *BSP_GetFlashByAddr(uint32_t addr)
116 {
117 QSPI_TypeDef *fhandle = NULL;
118
119 if ((addr >= QSPI1_MEM_BASE) && (addr < (QSPI1_MEM_BASE + QSPI1_MAX_SIZE)))
120 fhandle = FLASH1;
121 else if ((addr >= QSPI2_MEM_BASE) && (addr < (QSPI2_MEM_BASE + QSPI2_MAX_SIZE)))
122 fhandle = FLASH2;
123 else if ((addr >= QSPI3_MEM_BASE) && (addr < (QSPI3_MEM_BASE + QSPI3_MAX_SIZE)))
124 fhandle = FLASH3;
125 else if ((addr >= QSPI4_MEM_BASE) && (addr < (QSPI4_MEM_BASE + QSPI4_MAX_SIZE)))
126 fhandle = FLASH4;
127
128 return fhandle;
129 }
130 #endif /* !SF32LB55X */
131
132 #ifdef SOC_BF0_HCPU
133
HAL_RAM_RET_CODE_SECT(BSP_HxtCbank_Config,void BSP_HxtCbank_Config (uint32_t cbank_sel))134 HAL_RAM_RET_CODE_SECT(BSP_HxtCbank_Config, void BSP_HxtCbank_Config(uint32_t cbank_sel))
135 {
136 int clk_src = HAL_RCC_HCPU_GetClockSrc(RCC_CLK_MOD_SYS);
137
138 HAL_RCC_HCPU_ClockSelect(RCC_CLK_MOD_SYS, RCC_SYSCLK_HRC48);
139 uint32_t dll1_freq = HAL_RCC_HCPU_GetDLL1Freq();
140 uint32_t dll2_freq = HAL_RCC_HCPU_GetDLL2Freq();
141
142 HAL_PMU_SET_HXT_CBANK(cbank_sel);
143
144 HAL_Delay_us(0);
145 HAL_Delay_us(40);
146
147 HAL_RCC_HCPU_DisableDLL1();
148 HAL_RCC_HCPU_DisableDLL2();
149
150 HAL_RCC_HCPU_EnableDLL1(dll1_freq);
151 HAL_RCC_HCPU_EnableDLL2(dll2_freq);
152
153
154 HAL_RCC_HCPU_ClockSelect(RCC_CLK_MOD_SYS, clk_src);
155 HAL_Delay_us(0);
156
157 return;
158 }
159 #endif
160
161 #ifdef SF32LB52X
162
163 static uint32_t conf_sys[CFG_SYS_SIZE / 4];
164
BSP_System_Config(void)165 int BSP_System_Config(void)
166 {
167 int res, i;
168 uint8_t *data;
169 uint16_t ate_efuse_offset = 256; // bank1 , offset 0
170 FLASH_HandleTypeDef fhandle;
171 int len;
172 uint8_t *buf;
173 FACTORY_CFG_BATTERY_CALI_T battery_cfg;
174 uint32_t conf_buf[CFG_SYS_SIZE / 4];
175 FACTORY_CFG_CRYSTAL_T xtal_cfg;
176
177 data = (uint8_t *)&conf_sys[0];
178 res = HAL_EFUSE_Init();
179 if (res != 0)
180 {
181 //rt_kprintf("efuse init fail %d\n", res);
182 return 1;
183 }
184 HAL_Delay_us(0);
185 HAL_Delay_us(10);
186
187 // initial data buffer to 0
188 for (i = 0; i < CFG_SYS_SIZE / 4; i++)
189 conf_sys[i] = 0;
190
191 res = HAL_EFUSE_Read(ate_efuse_offset, data, CFG_SYS_SIZE);
192 if (res != CFG_SYS_SIZE)
193 {
194 //rt_kprintf("Read EFUSE fail\n");
195 return 2;
196 }
197
198 HAL_PMU_LoadCalData();
199
200 #if defined(CFG_SUPPORT_NON_OTP)
201 return 0;
202 #endif /* CFG_SUPPORT_NON_OTP */
203
204 uint32_t addr = BSP_GetOtpBase();
205 memset(&fhandle, 0, sizeof(fhandle));
206 fhandle.Instance = BSP_GetFlashByAddr(addr);
207 HAL_ASSERT(fhandle.Instance);
208 res = HAL_FLASH_PreInit(&fhandle);
209 HAL_ASSERT(0 == res);
210
211 // load sys otp page to cache buffer
212 buf = (uint8_t *)conf_buf;
213 len = HAL_QSPI_READ_OTP(&fhandle, CFG_IN_OTP_PAGE << 12, buf, CFG_SYS_SIZE);
214 HAL_ASSERT(len > 0);
215
216 // load user otp page to cache buffer
217 buf = (uint8_t *)conf_user;
218 len = HAL_QSPI_READ_OTP(&fhandle, CFG_USER_OTP_PAGE << 12, buf, CFG_USER_SIZE);
219 HAL_ASSERT(len > 0);
220
221 buf = (uint8_t *)conf_cust;
222 len = HAL_QSPI_READ_OTP(&fhandle, CFG_CUST_OTP_PAGE << 12, buf, CFG_USER_SIZE);
223 HAL_ASSERT(len > 0);
224
225 /* set hxt_cbank */
226 res = BSP_OTP_CUST_CFG_READ(FACTORY_CFG_ID_CRYSTAL, (uint8_t *)&xtal_cfg, sizeof(FACTORY_CFG_CRYSTAL_T), (uint8_t *)conf_buf, len);
227 if ((res > 0) && (xtal_cfg.cbank_sel != 0) && (xtal_cfg.cbank_sel != 0x3ff)) // add xtal invalid data check
228 {
229 #ifdef SOC_BF0_HCPU
230 BSP_HxtCbank_Config(xtal_cfg.cbank_sel);
231 #endif
232 }
233
234 return 0;
235 }
236
BSP_Get_SysCfg_Cache()237 char *BSP_Get_SysCfg_Cache()
238 {
239 return (char *)conf_sys;
240 }
241
242 // split to adc/pmu/charge and move to driver code later?
BSP_CONFIG_get(int type,uint8_t * buf,int length)243 int BSP_CONFIG_get(int type, uint8_t *buf, int length)
244 {
245 int ret = 0;
246 uint8_t *data = (uint8_t *)conf_sys;
247 uint8_t pid = __HAL_SYSCFG_GET_PID();
248 uint8_t avdd_v18_en = 0, pvdd_v18_en = 0;
249
250 #if defined(AVDD_V18_ENABLE)
251 avdd_v18_en = 1;
252 #endif/* AVDD_V18_ENABLE */
253 #if defined(PVDD_V18_ENABLE)
254 pvdd_v18_en = 1;
255 #endif/* PVDD_1V8_ENABLE */
256
257 if (buf == NULL || length <= 0)
258 return 0;
259
260 #if 1
261 // data[0] include PMU TRIM/POLAR/VOUT, it should not be 0 if do ate calibrate
262 if (data[0] == 0)
263 return 0;
264 #else
265 // add debug data
266 data[0] = (0xa << 4) | 0xd;
267 #endif
268 if (type == FACTORY_CFG_ID_ADC)
269 {
270 if (length >= (int)sizeof(FACTORY_CFG_ADC_T))
271 {
272 FACTORY_CFG_ADC_T *cfg = (FACTORY_CFG_ADC_T *)buf;
273 ret = length;
274 if (!SF32LB52X_LETTER_SERIES() && avdd_v18_en)
275 {
276 HAL_ASSERT(0);
277 }
278
279 if (SF32LB52X_LETTER_SERIES() && avdd_v18_en)
280 {
281 cfg->vol10 = (uint16_t)data[22] | ((uint16_t)(data[23] & 0xf) << 8);
282 cfg->low_mv = ((data[23] & 0xf0) >> 4) | ((data[24] & 1) << 4);
283 cfg->vol25 = (uint16_t)((data[24] & 0xfe) >> 1) | ((uint16_t)(data[25] & 0x1f) << 7);
284 cfg->high_mv = ((data[25] & 0xe0) >> 5) | ((data[26] & 0x3) << 3);
285 cfg->vbat_reg = ((uint16_t)(data[26] & 0xfc) >> 2) | ((uint16_t)(data[27] & 0x3f) << 6);
286 cfg->vbat_mv = ((data[27] & 0xc0) >> 6) | ((data[28] & 0xf) << 2);
287 cfg->low_mv *= 100; // data in efuse with 100 mv based
288 cfg->high_mv *= 100;
289 cfg->vbat_mv *= 100;
290 }
291 else
292 {
293 cfg->vol10 = (uint16_t)data[4] | ((uint16_t)(data[5] & 0xf) << 8);
294 cfg->low_mv = ((data[5] & 0xf0) >> 4) | ((data[6] & 1) << 4);
295 cfg->vol25 = (uint16_t)((data[6] & 0xfe) >> 1) | ((uint16_t)(data[7] & 0x1f) << 7);
296 cfg->high_mv = ((data[7] & 0xe0) >> 5) | ((data[8] & 0x3) << 3);
297 cfg->vbat_reg = ((uint16_t)(data[8] & 0xfc) >> 2) | ((uint16_t)(data[9] & 0x3f) << 6);
298 cfg->vbat_mv = ((data[9] & 0xc0) >> 6) | ((data[10] & 0xf) << 2);
299 cfg->low_mv *= 100; // data in efuse with 100 mv based
300 cfg->high_mv *= 100;
301 cfg->vbat_mv *= 100;
302 }
303
304 if (SF32LB52X_LETTER_SERIES())
305 {
306 cfg->ldovref_flag = (data[17] & 0x8) >> 3;
307 cfg->ldovref_sel = (data[17] & 0xf0) >> 4;
308 }
309
310
311 #if 0
312 cfg->vol10 = 1758;
313 cfg->low_mv = 1000;
314 cfg->vol25 = 3162; //3170; //3162
315 cfg->high_mv = 2500;
316 cfg->vbat_reg = 2788;
317 cfg->vbat_mv = 4200;
318 #endif
319 if (cfg->vol10 == 0 || cfg->low_mv == 0 || cfg->vol25 == 0
320 || cfg->high_mv == 0 || cfg->vbat_reg == 0 || cfg->vbat_mv == 0) // all data should be valid
321 ret = 0;
322 }
323 }
324 else if (type == FACTORY_CFG_ID_VBUCK)
325 {
326 if (length >= (int)sizeof(FACTORY_CFG_VBK_LDO_T))
327 {
328 FACTORY_CFG_VBK_LDO_T *cfg = (FACTORY_CFG_VBK_LDO_T *)buf;
329 ret = length;
330 if (!SF32LB52X_LETTER_SERIES() && pvdd_v18_en)
331 {
332 HAL_ASSERT(0);
333 }
334 /*only 52D 3.3v use new*/
335 if (((SF32LB52X_LETTER_SERIES()) && (pid == 4) && !pvdd_v18_en) || ((SF32LB52X_LETTER_SERIES()) && (pid != 4) && pvdd_v18_en)) /*52D 3v3, 52A 1v8*/
336 {
337 cfg->buck_vos_trim = data[20] & 7;
338 cfg->buck_vos_polar = (data[20] & 8) >> 3;
339 cfg->hpsys_ldo_vout = (data[20] & 0xf0) >> 4;
340 cfg->lpsys_ldo_vout = data[21] & 0xf;
341 cfg->vret_trim = (data[21] & 0xf0) >> 4;
342 cfg->hpsys_ldo_vout2 = (data[28] & 0x78) >> 3;
343 }
344 else
345 {
346 cfg->buck_vos_trim = data[0] & 7;
347 cfg->buck_vos_polar = (data[0] & 8) >> 3;
348 cfg->hpsys_ldo_vout = (data[0] & 0xf0) >> 4;
349 cfg->lpsys_ldo_vout = data[1] & 0xf;
350 cfg->vret_trim = (data[1] & 0xf0) >> 4;
351
352 //cfg->buck_vos_trim2 = data[13] & 7;
353 //cfg->buck_vos_polar2 = (data[13] & 8) >> 3;
354 cfg->hpsys_ldo_vout2 = (data[13] & 0xf0) >> 4;
355 cfg->lpsys_ldo_vout2 = data[14] & 0xf;
356 }
357
358
359 if (!SF32LB52X_LETTER_SERIES())
360 {
361 cfg->vdd33_ldo2_vout = (data[2] & 0xf0) >> 4;
362 cfg->vdd33_ldo3_vout = data[3] & 0xf;
363 cfg->aon_vos_trim = (data[3] & 0x70) >> 4;
364 cfg->aon_vos_polar = (data[3] & 0x80) >> 7;
365 }
366
367 if (!(SF32LB52X_LETTER_SERIES()) || ((SF32LB52X_LETTER_SERIES()) && !pvdd_v18_en))
368 cfg->ldo18_vref_sel = data[2] & 0xf;
369
370 if (cfg->hpsys_ldo_vout == 0 || cfg->hpsys_ldo_vout2 == 0)
371 ret = 0;
372 }
373 }
374 else if (type == FACTORY_CFG_ID_CHARGER)
375 {
376 if (length >= (int)sizeof(FACTORY_CFG_CHARGER_T))
377 {
378 FACTORY_CFG_CHARGER_T *cfg = (FACTORY_CFG_CHARGER_T *)buf;
379 ret = length;
380 cfg->prog_v1p2 = (data[10] & 0xf0) >> 4;
381 cfg->cv_vctrl = data[11] & 0x3f;
382 cfg->cc_mn = (data[11] >> 6) | ((data[12] & 7) << 2);
383 cfg->cc_mp = data[12] >> 3;
384
385 cfg->chg_step = ((data[14] & 0xf0) >> 4) | ((data[15] & 0xf) << 4);
386 }
387 }
388 else
389 {
390 ret = 0;
391 }
392 return ret;
393 }
394
395 #else //52x
396
397 typedef struct
398 {
399 #ifndef SF32LB55X
400 uint32_t adc_cal[2];
401 #else
402 uint32_t adc_cal;
403 #endif
404 uint32_t sdadc_cal[2];
405 uint8_t sn[HAL_LCPU_CONFIG_SN_MAX_NUM];
406 uint16_t sn_len;
407 uint8_t chip_rev;
408 uint8_t reserved;
409 uint32_t battery_a;
410 uint32_t battery_b;
411 } HAL_HCPU_CONFIG_T;
412
413 #if BSP_CFG_IN_HCPU
414
415 HAL_HCPU_CONFIG_T g_bsp_hcpu_config;
416
BSP_CONFIG_set(int type,uint8_t * value,int length)417 HAL_StatusTypeDef BSP_CONFIG_set(int type, uint8_t *value, int length)
418 {
419 HAL_StatusTypeDef ret = HAL_ERROR;
420 #ifdef SOC_BF0_HCPU
421
422 switch (type)
423 {
424 case FACTORY_CFG_ID_ADC:
425 {
426 #ifndef SF32LB55X
427 if (length == 8) // 64 bit
428 {
429 memcpy((void *)&g_bsp_hcpu_config.adc_cal[0], value, length);
430 ret = HAL_OK;
431 }
432 #else
433 if (length == 4) // 32 bit
434 {
435 memcpy((void *)&g_bsp_hcpu_config.adc_cal, value, length);
436 ret = HAL_OK;
437 }
438 #endif
439 break;
440 }
441 case FACTORY_CFG_ID_SDMADC:
442 {
443 if (length == 8) // 64 bit
444 {
445 memcpy((void *)&g_bsp_hcpu_config.sdadc_cal, value, 8);
446 ret = HAL_OK;
447 }
448 break;
449 }
450 case FACTORY_CFG_ID_BATTERY:
451 {
452 if (length == 8)
453 {
454 uint32_t *p = (uint32_t *)value;
455 g_bsp_hcpu_config.battery_a = p[0];
456 g_bsp_hcpu_config.battery_b = p[1];
457 ret = HAL_OK;
458 }
459 else if (length == 12) //maybe 12 bytes
460 {
461 uint32_t *p = (uint32_t *)value;
462 g_bsp_hcpu_config.battery_a = p[1];
463 g_bsp_hcpu_config.battery_b = p[2];
464 ret = HAL_OK;
465 }
466 break;
467 }
468 default:
469 break;
470 }
471 #endif // No need set in LCPU currently
472
473 return ret;
474 }
475
476
BSP_CONFIG_get(int type,uint8_t * value,int length)477 int BSP_CONFIG_get(int type, uint8_t *value, int length)
478 {
479 int ret = 0;
480
481 switch (type)
482 {
483 case FACTORY_CFG_ID_ADC:
484 {
485 #ifndef SF32LB55X
486 if (length == 8) // 64 bit
487 {
488 memcpy((void *)value, (void *)&g_bsp_hcpu_config.adc_cal[0], 8);
489 ret = length;
490 }
491 #else
492 if (length == 4) // 32 bit
493 {
494 memcpy((void *)value, (void *)&g_bsp_hcpu_config.adc_cal, 4);
495 ret = length;
496 }
497 #endif
498 break;
499 }
500 case FACTORY_CFG_ID_SDMADC:
501 {
502 if (length == 8) // 64 bit
503 {
504 memcpy((void *)value, (void *)&g_bsp_hcpu_config.sdadc_cal, 8);
505 ret = length;
506 }
507 break;
508 }
509 case FACTORY_CFG_ID_BATTERY:
510 {
511 if (length == 8)
512 {
513 uint32_t *p = (uint32_t *)value;
514 p[0] = g_bsp_hcpu_config.battery_a;
515 p[1] = g_bsp_hcpu_config.battery_b;
516 ret = length;
517 }
518 else if (length == 12)
519 {
520 uint32_t *p = (uint32_t *)value;
521 p[0] = 0xe8091ad7;
522 p[1] = g_bsp_hcpu_config.battery_a;
523 p[2] = g_bsp_hcpu_config.battery_b;
524 ret = length;
525 }
526 break;
527 }
528 default:
529 break;
530 }
531 return ret;
532
533 }
534 #else
BSP_get_lcpu_type(int type)535 HAL_LCPU_CONFIG_TYPE_T BSP_get_lcpu_type(int type)
536 {
537 HAL_LCPU_CONFIG_TYPE_T lcpu_type = HAL_LCPU_CONFIG_MAX;
538
539 switch (type)
540 {
541 case FACTORY_CFG_ID_ADC:
542 {
543 lcpu_type = HAL_LCPU_CONFIG_ADC_CALIBRATION;
544 break;
545 }
546 case FACTORY_CFG_ID_SDMADC:
547 {
548 lcpu_type = HAL_LCPU_CONFIG_SDADC_CALIBRATION;
549 break;
550 }
551 case FACTORY_CFG_ID_BATTERY:
552 {
553 lcpu_type = HAL_LCPU_CONFIG_BATTERY_CALIBRATION;
554 break;
555 }
556 default:
557 break;
558 }
559 return lcpu_type;
560 }
BSP_CONFIG_set(int type,uint8_t * buf,int length)561 HAL_StatusTypeDef BSP_CONFIG_set(int type, uint8_t *buf, int length)
562 {
563 HAL_StatusTypeDef ret;
564 HAL_LCPU_CONFIG_TYPE_T lcpu_type;
565
566 lcpu_type = BSP_get_lcpu_type(type);
567
568 ret = HAL_LCPU_CONFIG_set(lcpu_type, buf, (uint16_t)length);
569
570 return ret;
571 }
BSP_CONFIG_get(int type,uint8_t * buf,int length)572 int BSP_CONFIG_get(int type, uint8_t *buf, int length)
573 {
574 HAL_StatusTypeDef ret;
575 HAL_LCPU_CONFIG_TYPE_T lcpu_type;
576 uint16_t len = (uint16_t)length;
577
578 lcpu_type = BSP_get_lcpu_type(type);
579
580 ret = HAL_LCPU_CONFIG_get(lcpu_type, buf, &len);
581
582 if (ret == HAL_OK)
583 {
584 return length;
585 }
586 else
587 {
588 return 0;
589 }
590 }
591 #endif
592
593 #ifdef SF32LB55X
BSP_CFG_CALIB_PMU(FACTORY_CFG_VBK_LDO_T * cfg)594 static void BSP_CFG_CALIB_PMU(FACTORY_CFG_VBK_LDO_T *cfg)
595 {
596 if (cfg == NULL)
597 return;
598
599 MODIFY_REG(hwp_pmuc->BG1_CR, PMUC_BG1_CR_BG1_VREF12_Msk, cfg->vbuck1 << PMUC_BG1_CR_BG1_VREF12_Pos);
600 MODIFY_REG(hwp_pmuc->LDO_CR, PMUC_LDO_CR_HPSYS_LDO_VREF_Msk, cfg->hp_ldo << PMUC_LDO_CR_HPSYS_LDO_VREF_Pos);
601 MODIFY_REG(hwp_pmuc->LDO_CR, PMUC_LDO_CR_LPSYS_LDO_VREF_Msk, cfg->lp_ldo << PMUC_LDO_CR_LPSYS_LDO_VREF_Pos);
602 MODIFY_REG(hwp_pmuc->VRET_CR, PMUC_VRET_CR_TRIM_Msk, cfg->vret << PMUC_VRET_CR_TRIM_Pos);
603 MODIFY_REG(hwp_pmuc->BG2_CR, PMUC_BG2_CR_BG2_VREF12_Msk, cfg->vbuck2 << PMUC_BG2_CR_BG2_VREF12_Pos);
604 }
605 #elif defined(SF32LB58X)
BSP_CFG_CALIB_PMU(FACTORY_CFG_VBK_LDO_T * cfg)606 static void BSP_CFG_CALIB_PMU(FACTORY_CFG_VBK_LDO_T *cfg)
607 {
608 if (cfg == NULL)
609 return;
610
611 MODIFY_REG(hwp_pmuc->BG1_CR, PMUC_BG1_CR_BG1_VREF12_Msk, cfg->vbuck1 << PMUC_BG1_CR_BG1_VREF12_Pos);
612 MODIFY_REG(hwp_pmuc->LDO_CR, PMUC_LDO_CR_HPSYS_LDO_VREF_Msk, cfg->hp_ldo << PMUC_LDO_CR_HPSYS_LDO_VREF_Pos);
613 MODIFY_REG(hwp_pmuc->VRET_CR, PMUC_VRET_CR_TRIM_Msk, cfg->vret << PMUC_VRET_CR_TRIM_Pos);
614 MODIFY_REG(hwp_pmuc->BG2_CR, PMUC_BG2_CR_BG2_VREF12_Msk, cfg->vbuck2 << PMUC_BG2_CR_BG2_VREF12_Pos);
615 }
616 #elif defined(SF32LB56X)
BSP_CFG_CALIB_PMU(FACTORY_CFG_VBK_LDO_T * cfg)617 static void BSP_CFG_CALIB_PMU(FACTORY_CFG_VBK_LDO_T *cfg)
618 {
619 if (cfg == NULL)
620 return;
621
622 MODIFY_REG(hwp_pmuc->BG1_CR, PMUC_BG1_CR_BG1_VREF12_Msk, cfg->vbuck1 << PMUC_BG1_CR_BG1_VREF12_Pos);
623 MODIFY_REG(hwp_pmuc->HPSYS_LDO, PMUC_HPSYS_LDO_VREF_Msk, cfg->hp_ldo << PMUC_HPSYS_LDO_VREF_Pos);
624 MODIFY_REG(hwp_pmuc->LPSYS_LDO, PMUC_LPSYS_LDO_VREF_Msk, cfg->lp_ldo << PMUC_LPSYS_LDO_VREF_Pos);
625 MODIFY_REG(hwp_pmuc->VRET_CR, PMUC_VRET_CR_TRIM_Msk, cfg->vret << PMUC_VRET_CR_TRIM_Pos);
626
627 HAL_PMU_SaveCalData(cfg);
628 }
629
630 #else // 52x?
BSP_CFG_CALIB_PMU(FACTORY_CFG_VBK_LDO_T * cfg)631 static void BSP_CFG_CALIB_PMU(FACTORY_CFG_VBK_LDO_T *cfg)
632 {
633 if (cfg == NULL)
634 return;
635 }
636
637 #endif //55x
638
BSP_System_Config(void)639 int BSP_System_Config(void)
640 {
641 FLASH_HandleTypeDef fhandle;
642 int res, len;
643 uint8_t *buf;
644 FACTORY_CFG_SDMADC_T sdm_cfg;
645 FACTORY_CFG_BATTERY_CALI_T battery_cfg;
646 FACTORY_CFG_VBK_LDO_T vbk_cfg;
647 FACTORY_CFG_SIP_MOD_T sip_cfg;
648 uint32_t conf_buf[CFG_SYS_SIZE / 4];
649 FACTORY_CFG_CRYSTAL_T xtal_cfg;
650
651 buf = (uint8_t *)conf_buf;
652
653 #if defined(CFG_SUPPORT_NON_OTP)
654 return 0;
655 #endif
656
657 uint32_t addr = BSP_GetOtpBase();
658 memset(&fhandle, 0, sizeof(fhandle));
659 fhandle.Instance = BSP_GetFlashByAddr(addr);
660 HAL_ASSERT(fhandle.Instance);
661 res = HAL_FLASH_PreInit(&fhandle);
662 HAL_ASSERT(0 == res);
663
664 len = HAL_QSPI_READ_OTP(&fhandle, CFG_IN_OTP_PAGE << 12, buf, CFG_SYS_SIZE);
665 HAL_ASSERT(len > 0);
666
667 #ifndef SF32LB52X
668 res = BSP_OTP_CFG_READ(FACTORY_CFG_ID_VBUCK, (uint8_t *)&vbk_cfg, sizeof(FACTORY_CFG_VBK_LDO_T), buf, len);
669 if (res > 0)
670 {
671 // set vbuck / ldo as configure.
672 BSP_CFG_CALIB_PMU(&vbk_cfg);
673 }
674 else // change default
675 {
676 HAL_PMU_SET_HPSYS_LDO_VREF(PMU_HPSYS_LDO_VREF_DEFAULT);
677 }
678 #endif
679 #ifdef SF32LB55X
680 res = BSP_OTP_CFG_READ(FACTORY_CFG_ID_CRYSTAL, (uint8_t *)&xtal_cfg, sizeof(FACTORY_CFG_CRYSTAL_T), buf, len);
681 if ((res > 0) && (xtal_cfg.cbank_sel != 0) && (xtal_cfg.cbank_sel != 0x3ff)) // add xtal invalid data check
682 {
683 // set crystal configure.
684 HAL_PMU_SET_HXT_CBANK(xtal_cfg.cbank_sel);
685 }
686 else // do not set by factory test, use defualt 0x1ea;
687 {
688 HAL_PMU_SET_HXT_CBANK(0x1EA);
689 }
690 #endif /* SF32LB55X */
691
692
693 FACTORY_CFG_ADC_T adc_cfg;
694 res = BSP_OTP_CFG_READ(FACTORY_CFG_ID_ADC, (uint8_t *)&adc_cfg, sizeof(FACTORY_CFG_ADC_T), buf, len);
695 if (res > 0)
696 {
697 BSP_CONFIG_set(FACTORY_CFG_ID_ADC, (uint8_t *)&adc_cfg, sizeof(FACTORY_CFG_ADC_T));
698 }
699 res = BSP_OTP_CFG_READ(FACTORY_CFG_ID_SDMADC, (uint8_t *)&sdm_cfg, sizeof(FACTORY_CFG_SDMADC_T), buf, len);
700 if (res > 0)
701 {
702 BSP_CONFIG_set(FACTORY_CFG_ID_SDMADC, (uint8_t *)&sdm_cfg, sizeof(FACTORY_CFG_SDMADC_T));
703 }
704 res = BSP_OTP_CFG_READ(FACTORY_CFG_ID_BATTERY, (uint8_t *)&battery_cfg, sizeof(FACTORY_CFG_BATTERY_CALI_T), buf, len);
705 if (res > 0)
706 {
707 BSP_CONFIG_set(FACTORY_CFG_ID_BATTERY, (uint8_t *)&battery_cfg, sizeof(FACTORY_CFG_BATTERY_CALI_T));
708 }
709
710 res = BSP_OTP_CFG_READ(FACTORY_CFG_ID_SIPMODE, (uint8_t *)&sip_cfg, sizeof(FACTORY_CFG_SIP_MOD_T), buf, len);
711 if (res <= 0)
712 {
713 sip1_mode = 0;
714 sip2_mode = 0;
715 }
716 else
717 {
718 sip1_mode = sip_cfg.mpi1_mode;
719 sip2_mode = sip_cfg.mpi2_mode;
720 }
721
722 // load user otp page to cache buffer
723 buf = (uint8_t *)conf_user;
724 len = HAL_QSPI_READ_OTP(&fhandle, CFG_USER_OTP_PAGE << 12, buf, CFG_USER_SIZE);
725 HAL_ASSERT(len > 0);
726
727 buf = (uint8_t *)conf_cust;
728 len = HAL_QSPI_READ_OTP(&fhandle, CFG_CUST_OTP_PAGE << 12, buf, CFG_USER_SIZE);
729 HAL_ASSERT(len > 0);
730
731 #ifndef SF32LB55X
732 res = BSP_OTP_CUST_CFG_READ(FACTORY_CFG_ID_CRYSTAL, (uint8_t *)&xtal_cfg, sizeof(FACTORY_CFG_CRYSTAL_T), (uint8_t *)conf_buf, CFG_SYS_SIZE);
733 if ((res > 0) && (xtal_cfg.cbank_sel != 0) && (xtal_cfg.cbank_sel != 0x3ff)) // add xtal invalid data check
734 {
735 #ifdef SOC_BF0_HCPU
736 BSP_HxtCbank_Config(xtal_cfg.cbank_sel);
737 #endif
738 }
739 #endif /* !SF32LB55X */
740
741 return 0;
742 }
743 #endif // SF32LB52X
744
BSP_Get_UserOTP_Cache()745 char *BSP_Get_UserOTP_Cache()
746 {
747 return (char *)conf_user;
748 }
749
BSP_Get_CustOTP_Cache()750 char *BSP_Get_CustOTP_Cache()
751 {
752 return (char *)conf_cust;
753 }
754
HAL_RAM_RET_CODE_SECT(BSP_Get_Sip1_Mode,uint32_t BSP_Get_Sip1_Mode ())755 HAL_RAM_RET_CODE_SECT(BSP_Get_Sip1_Mode, uint32_t BSP_Get_Sip1_Mode())
756 {
757 return (uint32_t)sip1_mode;
758 }
759
HAL_RAM_RET_CODE_SECT(BSP_Get_Sip2_Mode,uint32_t BSP_Get_Sip2_Mode ())760 HAL_RAM_RET_CODE_SECT(BSP_Get_Sip2_Mode, uint32_t BSP_Get_Sip2_Mode())
761 {
762 return (uint32_t)sip2_mode;
763 }
764
BSP_GetOtpBase(void)765 __weak uint32_t BSP_GetOtpBase(void)
766 {
767 #if defined(SF32LB56X)||defined(SF32LB58X)
768 return 0x1C000000;
769 #else
770 return 0x10000000;
771 #endif
772 }
773
774 #endif //HAL_SYSTEM_CONFIG_ENABLED
775 /**
776 * @}
777 */
