1 /*
2 * SPDX-FileCopyrightText: 2016 STMicroelectronics
3 * SPDX-FileCopyrightText: 2019-2025 SiFli Technologies(Nanjing) Co., Ltd
4 *
5 * SPDX-License-Identifier: BSD-3-Clause AND Apache-2.0
6 */
7
8 #include "bf0_hal.h"
9 #include "bf0_hal_tim.h"
10 /*
11 #ifdef __HAL_GPT_MOE_ENABLE
12 #undef __HAL_GPT_MOE_ENABLE
13 #define __HAL_GPT_MOE_ENABLE(hdl)
14 #endif
15
16 #ifdef __HAL_GPT_MOE_DISABLE
17 #undef __HAL_GPT_MOE_DISABLE
18 #define __HAL_GPT_MOE_DISABLE(hdl)
19 #endif
20 */
21 /** @addtogroup BF0_HAL_Driver
22 * @{
23 */
24
25 /** @defgroup TIM Hardware Timer
26 * @brief TIM HAL module driver
27 * @{
28 */
29 #if defined(HAL_GPT_MODULE_ENABLED)||defined(_SIFLI_DOXYGEN_)
30
31 /* Private typedef -----------------------------------------------------------*/
32 /* Private define ------------------------------------------------------------*/
33 /* Private macro -------------------------------------------------------------*/
34 /* Private variables ---------------------------------------------------------*/
35 /** @addtogroup GPT_Private_Functions
36 * @{
37 */
38 /* Private function prototypes -----------------------------------------------*/
39 static void GPT_OC1_SetConfig(GPT_TypeDef *TIMx, GPT_OC_InitTypeDef *OC_Config);
40 static void GPT_OC3_SetConfig(GPT_TypeDef *TIMx, GPT_OC_InitTypeDef *OC_Config);
41 static void GPT_OC4_SetConfig(GPT_TypeDef *TIMx, GPT_OC_InitTypeDef *OC_Config);
42
43 static void GPT_TI1_ConfigInputStage(GPT_TypeDef *TIMx, uint32_t GPT_ICPolarity, uint32_t GPT_ICFilter);
44 static void GPT_TI2_SetConfig(GPT_TypeDef *TIMx, uint32_t GPT_ICPolarity, uint32_t GPT_ICSelection,
45 uint32_t GPT_ICFilter);
46 static void GPT_TI2_ConfigInputStage(GPT_TypeDef *TIMx, uint32_t GPT_ICPolarity, uint32_t GPT_ICFilter);
47 static void GPT_TI3_SetConfig(GPT_TypeDef *TIMx, uint32_t GPT_ICPolarity, uint32_t GPT_ICSelection,
48 uint32_t GPT_ICFilter);
49 static void GPT_TI4_SetConfig(GPT_TypeDef *TIMx, uint32_t GPT_ICPolarity, uint32_t GPT_ICSelection,
50 uint32_t GPT_ICFilter);
51
52 static void GPT_ETR_SetConfig(GPT_TypeDef *TIMx, uint32_t GPT_ExtTRGPrescaler,
53 uint32_t GPT_ExtTRGPolarity, uint32_t ExtTRGFilter);
54
55 static void GPT_ITRx_SetConfig(GPT_TypeDef *TIMx, uint16_t GPT_ITRx);
56 static void GPT_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
57 static void GPT_DMATriggerCplt(DMA_HandleTypeDef *hdma);
58 static void GPT_SlaveTimer_SetConfig(GPT_HandleTypeDef *htim,
59 GPT_SlaveConfigTypeDef *sSlaveConfig);
60 /**
61 * @}
62 */
63
64 /* Exported functions --------------------------------------------------------*/
65 /** @defgroup GPT_Exported_Functions TIM Exported Functions
66 * @{
67 */
68
69 /** @defgroup GPT_Exported_Functions_Group1 Time Base functions
70 * @brief Time Base functions
71 *
72 @verbatim
73 ==============================================================================
74 ##### Time Base functions #####
75 ==============================================================================
76 [..]
77 This section provides functions allowing to:
78 (+) Initialize and configure the TIM base.
79 (+) De-initialize the TIM base.
80 (+) Start the Time Base.
81 (+) Stop the Time Base.
82 (+) Start the Time Base and enable interrupt.
83 (+) Stop the Time Base and disable interrupt.
84 (+) Start the Time Base and enable DMA transfer.
85 (+) Stop the Time Base and disable DMA transfer.
86
87 @endverbatim
88 * @{
89 */
90 /**
91 * @brief Initializes the TIM Time base Unit according to the specified
92 * parameters in the GPT_HandleTypeDef and create the associated handle.
93 * @param htim pointer to a GPT_HandleTypeDef structure that contains
94 * the configuration information for TIM module.
95 * @retval HAL status
96 */
HAL_GPT_Base_Init(GPT_HandleTypeDef * htim)97 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Base_Init(GPT_HandleTypeDef *htim)
98 {
99 /* Check the TIM handle allocation */
100 if (htim == NULL)
101 {
102 return HAL_ERROR;
103 }
104
105 #ifdef hwp_gptim1
106 if (htim->Instance == hwp_gptim1)
107 HAL_RCC_EnableModule(RCC_MOD_GPTIM1);
108 #endif /* hwp_gptim1 */
109 #ifdef hwp_gptim2
110 if (htim->Instance == hwp_gptim2)
111 HAL_RCC_EnableModule(RCC_MOD_GPTIM2);
112 #endif /* hwp_gptim2 */
113 #ifdef hwp_gptim3
114 if (htim->Instance == hwp_gptim3)
115 HAL_RCC_EnableModule(RCC_MOD_GPTIM3);
116 #endif /* hwp_gptim3 */
117 #ifdef hwp_gptim4
118 if (htim->Instance == hwp_gptim4)
119 HAL_RCC_EnableModule(RCC_MOD_GPTIM4);
120 #endif /* hwp_gptim4 */
121 #ifdef hwp_gptim5
122 if (htim->Instance == hwp_gptim5)
123 HAL_RCC_EnableModule(RCC_MOD_GPTIM5);
124 #endif /* hwp_gptim5 */
125 #ifdef hwp_atim1
126 if (htim->Instance == (GPT_TypeDef *)hwp_atim1)
127 HAL_RCC_EnableModule(RCC_MOD_ATIM1);
128 #endif /* hwp_atim1 */
129 #ifdef hwp_atim2
130 if (htim->Instance == (GPT_TypeDef *)hwp_atim2)
131 HAL_RCC_EnableModule(RCC_MOD_ATIM2);
132 #endif /* hwp_atim2 */
133 #ifdef hwp_btim1
134 if (htim->Instance == (GPT_TypeDef *)hwp_btim1)
135 HAL_RCC_EnableModule(RCC_MOD_BTIM1);
136 #endif /* hwp_btim1 */
137 #ifdef hwp_btim2
138 if (htim->Instance == (GPT_TypeDef *)hwp_btim2)
139 HAL_RCC_EnableModule(RCC_MOD_BTIM2);
140 #endif /* hwp_btim2 */
141 #ifdef hwp_btim3
142 if (htim->Instance == (GPT_TypeDef *)hwp_btim3)
143 HAL_RCC_EnableModule(RCC_MOD_BTIM3);
144 #endif /* hwp_btim3 */
145 #ifdef hwp_btim4
146 if (htim->Instance == (GPT_TypeDef *)hwp_btim4)
147 HAL_RCC_EnableModule(RCC_MOD_BTIM4);
148 #endif /* hwp_btim4 */
149
150 /* Check the parameters */
151 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
152 HAL_ASSERT(IS_GPT_COUNTER_MODE(htim->Init.CounterMode));
153
154 if (htim->State == HAL_GPT_STATE_RESET)
155 {
156 /* Allocate lock resource and initialize it */
157 htim->Lock = HAL_UNLOCKED;
158 /* Init the low level hardware : GPIO, CLOCK, NVIC */
159 HAL_GPT_Base_MspInit(htim);
160 }
161
162 /* Set the TIM state */
163 htim->State = HAL_GPT_STATE_BUSY;
164
165 /* Set the Time Base configuration */
166 GPT_Base_SetConfig(htim->Instance, &htim->Init);
167
168 __HAL_GPT_CLEAR_FLAG(htim, GPT_FLAG_UPDATE); /* clear update flag */
169 __HAL_GPT_URS_ENABLE(htim); /* enable update request source */
170 /* Initialize the TIM state*/
171 htim->State = HAL_GPT_STATE_READY;
172
173 return HAL_OK;
174 }
175
176 /**
177 * @brief DeInitializes the TIM Base peripheral
178 * @param htim pointer to a GPT_HandleTypeDef structure that contains
179 * the configuration information for TIM module.
180 * @retval HAL status
181 */
HAL_GPT_Base_DeInit(GPT_HandleTypeDef * htim)182 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Base_DeInit(GPT_HandleTypeDef *htim)
183 {
184 /* Check the parameters */
185 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
186
187 htim->State = HAL_GPT_STATE_BUSY;
188
189 /* Disable the TIM Peripheral Clock */
190 __HAL_GPT_DISABLE(htim);
191
192 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
193 HAL_GPT_Base_MspDeInit(htim);
194
195 /* Change TIM state */
196 htim->State = HAL_GPT_STATE_RESET;
197
198 /* Release Lock */
199 __HAL_UNLOCK(htim);
200
201 return HAL_OK;
202 }
203
204 /**
205 * @brief Initializes the TIM Base MSP.
206 * @param htim pointer to a GPT_HandleTypeDef structure that contains
207 * the configuration information for TIM module.
208 * @retval None
209 */
HAL_GPT_Base_MspInit(GPT_HandleTypeDef * htim)210 __weak void HAL_GPT_Base_MspInit(GPT_HandleTypeDef *htim)
211 {
212 /* Prevent unused argument(s) compilation warning */
213 UNUSED(htim);
214 /* NOTE : This function Should not be modified, when the callback is needed,
215 the HAL_GPT_Base_MspInit could be implemented in the user file
216 */
217 }
218
219 /**
220 * @brief DeInitializes TIM Base MSP.
221 * @param htim pointer to a GPT_HandleTypeDef structure that contains
222 * the configuration information for TIM module.
223 * @retval None
224 */
HAL_GPT_Base_MspDeInit(GPT_HandleTypeDef * htim)225 __weak void HAL_GPT_Base_MspDeInit(GPT_HandleTypeDef *htim)
226 {
227 /* Prevent unused argument(s) compilation warning */
228 UNUSED(htim);
229 /* NOTE : This function Should not be modified, when the callback is needed,
230 the HAL_GPT_Base_MspDeInit could be implemented in the user file
231 */
232 }
233
234 /**
235 * @brief Starts the TIM Base generation.
236 * @param htim pointer to a GPT_HandleTypeDef structure that contains
237 * the configuration information for TIM module.
238 * @retval HAL status
239 */
HAL_GPT_Base_Start(GPT_HandleTypeDef * htim)240 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Base_Start(GPT_HandleTypeDef *htim)
241 {
242 /* Check the parameters */
243 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
244
245 /* Set the TIM state */
246 htim->State = HAL_GPT_STATE_BUSY;
247
248 /* Enable the Peripheral */
249 __HAL_GPT_ENABLE(htim);
250
251 /* Change the TIM state*/
252 htim->State = HAL_GPT_STATE_READY;
253
254 /* Return function status */
255 return HAL_OK;
256 }
257
258 /**
259 * @brief Stops the TIM Base generation.
260 * @param htim pointer to a GPT_HandleTypeDef structure that contains
261 * the configuration information for TIM module.
262 * @retval HAL status
263 */
HAL_GPT_Base_Stop(GPT_HandleTypeDef * htim)264 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Base_Stop(GPT_HandleTypeDef *htim)
265 {
266 /* Check the parameters */
267 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
268
269 /* Set the TIM state */
270 htim->State = HAL_GPT_STATE_BUSY;
271
272 /* Disable the Peripheral */
273 __HAL_GPT_DISABLE(htim);
274
275 /* Change the TIM state*/
276 htim->State = HAL_GPT_STATE_READY;
277
278 /* Return function status */
279 return HAL_OK;
280 }
281
282 /**
283 * @brief Starts the TIM Base generation in interrupt mode.
284 * @param htim pointer to a GPT_HandleTypeDef structure that contains
285 * the configuration information for TIM module.
286 * @retval HAL status
287 */
HAL_GPT_Base_Start_IT(GPT_HandleTypeDef * htim)288 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Base_Start_IT(GPT_HandleTypeDef *htim)
289 {
290 /* Check the parameters */
291 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
292
293 /* Enable the TIM Update interrupt */
294 __HAL_GPT_ENABLE_IT(htim, GPT_IT_UPDATE);
295
296 /* Enable the Peripheral */
297 __HAL_GPT_ENABLE(htim);
298
299 /* Return function status */
300 return HAL_OK;
301 }
302
303 /**
304 * @brief Stops the TIM Base generation in interrupt mode.
305 * @param htim pointer to a GPT_HandleTypeDef structure that contains
306 * the configuration information for TIM module.
307 * @retval HAL status
308 */
HAL_GPT_Base_Stop_IT(GPT_HandleTypeDef * htim)309 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Base_Stop_IT(GPT_HandleTypeDef *htim)
310 {
311 /* Check the parameters */
312 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
313 /* Disable the TIM Update interrupt */
314 __HAL_GPT_DISABLE_IT(htim, GPT_IT_UPDATE);
315
316 /* Disable the Peripheral */
317 __HAL_GPT_DISABLE(htim);
318
319 /* Return function status */
320 return HAL_OK;
321 }
322
323 /**
324 * @brief Starts the TIM Base generation in DMA mode.
325 * @param htim pointer to a GPT_HandleTypeDef structure that contains
326 * the configuration information for TIM module.
327 * @param pData The source Buffer address.
328 * @param Length The length of data to be transferred from memory to peripheral.
329 * @retval HAL status
330 */
HAL_GPT_Base_Start_DMA(GPT_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)331 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Base_Start_DMA(GPT_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
332 {
333 /* Check the parameters */
334 HAL_ASSERT(IS_GPT_DMA_INSTANCE(htim->Instance));
335
336 if (htim->State == HAL_GPT_STATE_BUSY)
337 {
338 return HAL_BUSY;
339 }
340 else if (htim->State == HAL_GPT_STATE_READY)
341 {
342 if ((pData == 0U) && (Length > 0))
343 {
344 return HAL_ERROR;
345 }
346 else
347 {
348 htim->State = HAL_GPT_STATE_BUSY;
349 }
350 }
351 /* Set the DMA Period elapsed callback */
352 htim->hdma[GPT_DMA_ID_UPDATE]->XferCpltCallback = GPT_DMAPeriodElapsedCplt;
353
354 /* Set the DMA error callback */
355 htim->hdma[GPT_DMA_ID_UPDATE]->XferErrorCallback = GPT_DMAError ;
356
357 /* Enable the DMA Stream */
358 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
359
360 /* Enable the TIM Update DMA request */
361 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_UPDATE);
362
363 /* Enable the Peripheral */
364 __HAL_GPT_ENABLE(htim);
365
366 /* Return function status */
367 return HAL_OK;
368 }
369
370 /**
371 * @brief Stops the TIM Base generation in DMA mode.
372 * @param htim pointer to a GPT_HandleTypeDef structure that contains
373 * the configuration information for TIM module.
374 * @retval HAL status
375 */
HAL_GPT_Base_Stop_DMA(GPT_HandleTypeDef * htim)376 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Base_Stop_DMA(GPT_HandleTypeDef *htim)
377 {
378 /* Check the parameters */
379 HAL_ASSERT(IS_GPT_DMA_INSTANCE(htim->Instance));
380
381 /* Disable the TIM Update DMA request */
382 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_UPDATE);
383
384 /* Disable the Peripheral */
385 __HAL_GPT_DISABLE(htim);
386
387 /* Change the htim state */
388 htim->State = HAL_GPT_STATE_READY;
389
390 /* Return function status */
391 return HAL_OK;
392 }
393 /**
394 * @}
395 */
396
397 /** @defgroup GPT_Exported_Functions_Group2 Time Output Compare functions
398 * @brief Time Output Compare functions
399 *
400 @verbatim
401 ==============================================================================
402 ##### Time Output Compare functions #####
403 ==============================================================================
404 [..]
405 This section provides functions allowing to:
406 (+) Initialize and configure the TIM Output Compare.
407 (+) De-initialize the TIM Output Compare.
408 (+) Start the Time Output Compare.
409 (+) Stop the Time Output Compare.
410 (+) Start the Time Output Compare and enable interrupt.
411 (+) Stop the Time Output Compare and disable interrupt.
412 (+) Start the Time Output Compare and enable DMA transfer.
413 (+) Stop the Time Output Compare and disable DMA transfer.
414
415 @endverbatim
416 * @{
417 */
418 /**
419 * @brief Initializes the TIM Output Compare according to the specified
420 * parameters in the GPT_HandleTypeDef and create the associated handle.
421 * @param htim pointer to a GPT_HandleTypeDef structure that contains
422 * the configuration information for TIM module.
423 * @retval HAL status
424 */
HAL_GPT_OC_Init(GPT_HandleTypeDef * htim)425 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OC_Init(GPT_HandleTypeDef *htim)
426 {
427 /* Check the TIM handle allocation */
428 if (htim == NULL)
429 {
430 return HAL_ERROR;
431 }
432
433 /* Check the parameters */
434 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
435 HAL_ASSERT(IS_GPT_COUNTER_MODE(htim->Init.CounterMode));
436
437 if (htim->State == HAL_GPT_STATE_RESET)
438 {
439 /* Allocate lock resource and initialize it */
440 htim->Lock = HAL_UNLOCKED;
441 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
442 HAL_GPT_OC_MspInit(htim);
443 }
444
445 /* Set the TIM state */
446 htim->State = HAL_GPT_STATE_BUSY;
447
448 /* Init the base time for the Output Compare */
449 GPT_Base_SetConfig(htim->Instance, &htim->Init);
450
451 /* Initialize the TIM state*/
452 htim->State = HAL_GPT_STATE_READY;
453
454 return HAL_OK;
455 }
456
457 /**
458 * @brief DeInitializes the TIM peripheral
459 * @param htim pointer to a GPT_HandleTypeDef structure that contains
460 * the configuration information for TIM module.
461 * @retval HAL status
462 */
HAL_GPT_OC_DeInit(GPT_HandleTypeDef * htim)463 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OC_DeInit(GPT_HandleTypeDef *htim)
464 {
465 /* Check the parameters */
466 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
467
468 htim->State = HAL_GPT_STATE_BUSY;
469
470 /* Disable the TIM Peripheral Clock */
471 __HAL_GPT_DISABLE(htim);
472
473 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
474 HAL_GPT_OC_MspDeInit(htim);
475
476 /* Change TIM state */
477 htim->State = HAL_GPT_STATE_RESET;
478
479 /* Release Lock */
480 __HAL_UNLOCK(htim);
481
482 return HAL_OK;
483 }
484
485 /**
486 * @brief Initializes the TIM Output Compare MSP.
487 * @param htim pointer to a GPT_HandleTypeDef structure that contains
488 * the configuration information for TIM module.
489 * @retval None
490 */
HAL_GPT_OC_MspInit(GPT_HandleTypeDef * htim)491 __weak void HAL_GPT_OC_MspInit(GPT_HandleTypeDef *htim)
492 {
493 /* Prevent unused argument(s) compilation warning */
494 UNUSED(htim);
495 /* NOTE : This function Should not be modified, when the callback is needed,
496 the HAL_GPT_OC_MspInit could be implemented in the user file
497 */
498 }
499
500 /**
501 * @brief DeInitializes TIM Output Compare MSP.
502 * @param htim pointer to a GPT_HandleTypeDef structure that contains
503 * the configuration information for TIM module.
504 * @retval None
505 */
HAL_GPT_OC_MspDeInit(GPT_HandleTypeDef * htim)506 __weak void HAL_GPT_OC_MspDeInit(GPT_HandleTypeDef *htim)
507 {
508 /* Prevent unused argument(s) compilation warning */
509 UNUSED(htim);
510 /* NOTE : This function Should not be modified, when the callback is needed,
511 the HAL_GPT_OC_MspDeInit could be implemented in the user file
512 */
513 }
514
515 /**
516 * @brief Starts the TIM Output Compare signal generation.
517 * @param htim pointer to a GPT_HandleTypeDef structure that contains
518 * the configuration information for TIM module.
519 * @param Channel TIM Channel to be enabled.
520 * This parameter can be one of the following values:
521 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
522 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
523 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
524 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
525 * @retval HAL status
526 */
HAL_GPT_OC_Start(GPT_HandleTypeDef * htim,uint32_t Channel)527 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OC_Start(GPT_HandleTypeDef *htim, uint32_t Channel)
528 {
529 /* Check the parameters */
530 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
531
532 /* Enable the Output compare channel */
533 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_ENABLE);
534
535 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
536 {
537 /* Enable the main output */
538 __HAL_GPT_MOE_ENABLE(htim);
539 }
540
541 /* Enable the Peripheral */
542 __HAL_GPT_ENABLE(htim);
543
544 /* Return function status */
545 return HAL_OK;
546 }
547
548 /**
549 * @brief Stops the TIM Output Compare signal generation.
550 * @param htim pointer to a GPT_HandleTypeDef structure that contains
551 * the configuration information for TIM module.
552 * @param Channel TIM Channel to be disabled.
553 * This parameter can be one of the following values:
554 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
555 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
556 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
557 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
558 * @retval HAL status
559 */
HAL_GPT_OC_Stop(GPT_HandleTypeDef * htim,uint32_t Channel)560 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OC_Stop(GPT_HandleTypeDef *htim, uint32_t Channel)
561 {
562 /* Check the parameters */
563 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
564
565 /* Disable the Output compare channel */
566 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_DISABLE);
567
568 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
569 {
570 /* Disable the Main Output */
571 __HAL_GPT_MOE_DISABLE(htim);
572 }
573
574 /* Disable the Peripheral */
575 __HAL_GPT_DISABLE(htim);
576
577 /* Return function status */
578 return HAL_OK;
579 }
580
581 /**
582 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
583 * @param htim pointer to a GPT_HandleTypeDef structure that contains
584 * the configuration information for TIM module.
585 * @param Channel TIM Channel to be enabled.
586 * This parameter can be one of the following values:
587 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
588 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
589 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
590 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
591 * @retval HAL status
592 */
HAL_GPT_OC_Start_IT(GPT_HandleTypeDef * htim,uint32_t Channel)593 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OC_Start_IT(GPT_HandleTypeDef *htim, uint32_t Channel)
594 {
595 /* Check the parameters */
596 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
597
598 switch (Channel)
599 {
600 case GPT_CHANNEL_1:
601 {
602 /* Enable the TIM Capture/Compare 1 interrupt */
603 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC1);
604 }
605 break;
606
607 case GPT_CHANNEL_2:
608 {
609 /* Enable the TIM Capture/Compare 2 interrupt */
610 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC2);
611 }
612 break;
613
614 case GPT_CHANNEL_3:
615 {
616 /* Enable the TIM Capture/Compare 3 interrupt */
617 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC3);
618 }
619 break;
620
621 case GPT_CHANNEL_4:
622 {
623 /* Enable the TIM Capture/Compare 4 interrupt */
624 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC4);
625 }
626 break;
627
628 default:
629 break;
630 }
631
632 /* Enable the Output compare channel */
633 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_ENABLE);
634
635 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
636 {
637 /* Enable the main output */
638 __HAL_GPT_MOE_ENABLE(htim);
639 }
640
641 /* Enable the Peripheral */
642 __HAL_GPT_ENABLE(htim);
643
644 /* Return function status */
645 return HAL_OK;
646 }
647
648 /**
649 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
650 * @param htim pointer to a GPT_HandleTypeDef structure that contains
651 * the configuration information for TIM module.
652 * @param Channel TIM Channel to be disabled.
653 * This parameter can be one of the following values:
654 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
655 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
656 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
657 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
658 * @retval HAL status
659 */
HAL_GPT_OC_Stop_IT(GPT_HandleTypeDef * htim,uint32_t Channel)660 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OC_Stop_IT(GPT_HandleTypeDef *htim, uint32_t Channel)
661 {
662 /* Check the parameters */
663 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
664
665 switch (Channel)
666 {
667 case GPT_CHANNEL_1:
668 {
669 /* Disable the TIM Capture/Compare 1 interrupt */
670 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC1);
671 }
672 break;
673
674 case GPT_CHANNEL_2:
675 {
676 /* Disable the TIM Capture/Compare 2 interrupt */
677 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC2);
678 }
679 break;
680
681 case GPT_CHANNEL_3:
682 {
683 /* Disable the TIM Capture/Compare 3 interrupt */
684 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC3);
685 }
686 break;
687
688 case GPT_CHANNEL_4:
689 {
690 /* Disable the TIM Capture/Compare 4 interrupt */
691 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC4);
692 }
693 break;
694
695 default:
696 break;
697 }
698
699 /* Disable the Output compare channel */
700 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_DISABLE);
701
702 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
703 {
704 /* Disable the Main Output */
705 __HAL_GPT_MOE_DISABLE(htim);
706 }
707
708 /* Disable the Peripheral */
709 __HAL_GPT_DISABLE(htim);
710
711 /* Return function status */
712 return HAL_OK;
713 }
714
715 /**
716 * @brief Starts the TIM Output Compare signal generation in DMA mode.
717 * @param htim pointer to a GPT_HandleTypeDef structure that contains
718 * the configuration information for TIM module.
719 * @param Channel TIM Channel to be enabled.
720 * This parameter can be one of the following values:
721 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
722 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
723 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
724 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
725 * @param pData The source Buffer address.
726 * @param Length The length of data to be transferred from memory to TIM peripheral
727 * @retval HAL status
728 */
HAL_GPT_OC_Start_DMA(GPT_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)729 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OC_Start_DMA(GPT_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
730 {
731 /* Check the parameters */
732 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
733
734 if (htim->State == HAL_GPT_STATE_BUSY)
735 {
736 return HAL_BUSY;
737 }
738 else if (htim->State == HAL_GPT_STATE_READY)
739 {
740 if (((uint32_t)pData == 0U) && (Length > 0))
741 {
742 return HAL_ERROR;
743 }
744 else
745 {
746 htim->State = HAL_GPT_STATE_BUSY;
747 }
748 }
749 switch (Channel)
750 {
751 case GPT_CHANNEL_1:
752 {
753 /* Set the DMA Period elapsed callback */
754 htim->hdma[GPT_DMA_ID_CC1]->XferCpltCallback = GPT_DMADelayPulseCplt;
755
756 /* Set the DMA error callback */
757 htim->hdma[GPT_DMA_ID_CC1]->XferErrorCallback = GPT_DMAError ;
758
759 /* Enable the DMA Stream */
760 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
761
762 /* Enable the TIM Capture/Compare 1 DMA request */
763 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC1);
764 }
765 break;
766
767 case GPT_CHANNEL_2:
768 {
769 /* Set the DMA Period elapsed callback */
770 htim->hdma[GPT_DMA_ID_CC2]->XferCpltCallback = GPT_DMADelayPulseCplt;
771
772 /* Set the DMA error callback */
773 htim->hdma[GPT_DMA_ID_CC2]->XferErrorCallback = GPT_DMAError ;
774
775 /* Enable the DMA Stream */
776 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
777
778 /* Enable the TIM Capture/Compare 2 DMA request */
779 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC2);
780 }
781 break;
782
783 case GPT_CHANNEL_3:
784 {
785 /* Set the DMA Period elapsed callback */
786 htim->hdma[GPT_DMA_ID_CC3]->XferCpltCallback = GPT_DMADelayPulseCplt;
787
788 /* Set the DMA error callback */
789 htim->hdma[GPT_DMA_ID_CC3]->XferErrorCallback = GPT_DMAError ;
790
791 /* Enable the DMA Stream */
792 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length);
793
794 /* Enable the TIM Capture/Compare 3 DMA request */
795 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC3);
796 }
797 break;
798
799 case GPT_CHANNEL_4:
800 {
801 /* Set the DMA Period elapsed callback */
802 htim->hdma[GPT_DMA_ID_CC4]->XferCpltCallback = GPT_DMADelayPulseCplt;
803
804 /* Set the DMA error callback */
805 htim->hdma[GPT_DMA_ID_CC4]->XferErrorCallback = GPT_DMAError ;
806
807 /* Enable the DMA Stream */
808 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
809
810 /* Enable the TIM Capture/Compare 4 DMA request */
811 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC4);
812 }
813 break;
814
815 default:
816 break;
817 }
818
819 /* Enable the Output compare channel */
820 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_ENABLE);
821
822 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
823 {
824 /* Enable the main output */
825 __HAL_GPT_MOE_ENABLE(htim);
826 }
827
828 /* Enable the Peripheral */
829 __HAL_GPT_ENABLE(htim);
830
831 /* Return function status */
832 return HAL_OK;
833 }
834
835 /**
836 * @brief Stops the TIM Output Compare signal generation in DMA mode.
837 * @param htim pointer to a GPT_HandleTypeDef structure that contains
838 * the configuration information for TIM module.
839 * @param Channel TIM Channel to be disabled.
840 * This parameter can be one of the following values:
841 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
842 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
843 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
844 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
845 * @retval HAL status
846 */
HAL_GPT_OC_Stop_DMA(GPT_HandleTypeDef * htim,uint32_t Channel)847 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OC_Stop_DMA(GPT_HandleTypeDef *htim, uint32_t Channel)
848 {
849 /* Check the parameters */
850 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
851
852 switch (Channel)
853 {
854 case GPT_CHANNEL_1:
855 {
856 /* Disable the TIM Capture/Compare 1 DMA request */
857 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC1);
858 }
859 break;
860
861 case GPT_CHANNEL_2:
862 {
863 /* Disable the TIM Capture/Compare 2 DMA request */
864 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC2);
865 }
866 break;
867
868 case GPT_CHANNEL_3:
869 {
870 /* Disable the TIM Capture/Compare 3 DMA request */
871 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC3);
872 }
873 break;
874
875 case GPT_CHANNEL_4:
876 {
877 /* Disable the TIM Capture/Compare 4 interrupt */
878 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC4);
879 }
880 break;
881
882 default:
883 break;
884 }
885
886 /* Disable the Output compare channel */
887 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_DISABLE);
888
889 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
890 {
891 /* Disable the Main Output */
892 __HAL_GPT_MOE_DISABLE(htim);
893 }
894
895 /* Disable the Peripheral */
896 __HAL_GPT_DISABLE(htim);
897
898 /* Change the htim state */
899 htim->State = HAL_GPT_STATE_READY;
900
901 /* Return function status */
902 return HAL_OK;
903 }
904 /**
905 * @}
906 */
907
908 /** @defgroup GPT_Exported_Functions_Group3 Time PWM functions
909 * @brief Time PWM functions
910 *
911 @verbatim
912 ==============================================================================
913 ##### Time PWM functions #####
914 ==============================================================================
915 [..]
916 This section provides functions allowing to:
917 (+) Initialize and configure the TIM OPWM.
918 (+) De-initialize the TIM PWM.
919 (+) Start the Time PWM.
920 (+) Stop the Time PWM.
921 (+) Start the Time PWM and enable interrupt.
922 (+) Stop the Time PWM and disable interrupt.
923 (+) Start the Time PWM and enable DMA transfer.
924 (+) Stop the Time PWM and disable DMA transfer.
925
926 @endverbatim
927 * @{
928 */
929 /**
930 * @brief Initializes the TIM PWM Time Base according to the specified
931 * parameters in the GPT_HandleTypeDef and create the associated handle.
932 * @param htim pointer to a GPT_HandleTypeDef structure that contains
933 * the configuration information for TIM module.
934 * @retval HAL status
935 */
HAL_GPT_PWM_Init(GPT_HandleTypeDef * htim)936 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_PWM_Init(GPT_HandleTypeDef *htim)
937 {
938 /* Check the TIM handle allocation */
939 if (htim == NULL)
940 {
941 return HAL_ERROR;
942 }
943
944 /* Check the parameters */
945 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
946 HAL_ASSERT(IS_GPT_COUNTER_MODE(htim->Init.CounterMode));
947
948 if (htim->State == HAL_GPT_STATE_RESET)
949 {
950 /* Allocate lock resource and initialize it */
951 htim->Lock = HAL_UNLOCKED;
952 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
953 HAL_GPT_PWM_MspInit(htim);
954 }
955
956 /* Set the TIM state */
957 htim->State = HAL_GPT_STATE_BUSY;
958
959 /* Init the base time for the PWM */
960 GPT_Base_SetConfig(htim->Instance, &htim->Init);
961
962 /* Initialize the TIM state*/
963 htim->State = HAL_GPT_STATE_READY;
964
965 return HAL_OK;
966 }
967
968 /**
969 * @brief DeInitializes the TIM peripheral
970 * @param htim pointer to a GPT_HandleTypeDef structure that contains
971 * the configuration information for TIM module.
972 * @retval HAL status
973 */
HAL_GPT_PWM_DeInit(GPT_HandleTypeDef * htim)974 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_PWM_DeInit(GPT_HandleTypeDef *htim)
975 {
976 /* Check the parameters */
977 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
978
979 htim->State = HAL_GPT_STATE_BUSY;
980
981 /* Disable the TIM Peripheral Clock */
982 __HAL_GPT_DISABLE(htim);
983
984 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
985 HAL_GPT_PWM_MspDeInit(htim);
986
987 /* Change TIM state */
988 htim->State = HAL_GPT_STATE_RESET;
989
990 /* Release Lock */
991 __HAL_UNLOCK(htim);
992
993 return HAL_OK;
994 }
995
996 /**
997 * @brief Initializes the TIM PWM MSP.
998 * @param htim pointer to a GPT_HandleTypeDef structure that contains
999 * the configuration information for TIM module.
1000 * @retval None
1001 */
HAL_GPT_PWM_MspInit(GPT_HandleTypeDef * htim)1002 __weak void HAL_GPT_PWM_MspInit(GPT_HandleTypeDef *htim)
1003 {
1004 /* Prevent unused argument(s) compilation warning */
1005 UNUSED(htim);
1006 /* NOTE : This function Should not be modified, when the callback is needed,
1007 the HAL_GPT_PWM_MspInit could be implemented in the user file
1008 */
1009 }
1010
1011 /**
1012 * @brief DeInitializes TIM PWM MSP.
1013 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1014 * the configuration information for TIM module.
1015 * @retval None
1016 */
HAL_GPT_PWM_MspDeInit(GPT_HandleTypeDef * htim)1017 __weak void HAL_GPT_PWM_MspDeInit(GPT_HandleTypeDef *htim)
1018 {
1019 /* Prevent unused argument(s) compilation warning */
1020 UNUSED(htim);
1021 /* NOTE : This function Should not be modified, when the callback is needed,
1022 the HAL_GPT_PWM_MspDeInit could be implemented in the user file
1023 */
1024 }
1025
1026 /**
1027 * @brief Starts the PWM signal generation.
1028 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1029 * the configuration information for TIM module.
1030 * @param Channel TIM Channels to be enabled.
1031 * This parameter can be one of the following values:
1032 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
1033 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
1034 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
1035 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
1036 * @retval HAL status
1037 */
HAL_GPT_PWM_Start(GPT_HandleTypeDef * htim,uint32_t Channel)1038 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_PWM_Start(GPT_HandleTypeDef *htim, uint32_t Channel)
1039 {
1040 /* Check the parameters */
1041 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
1042
1043 /* Enable the Capture compare channel */
1044 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_ENABLE);
1045
1046 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
1047 {
1048 /* Enable the main output */
1049 __HAL_GPT_MOE_ENABLE(htim);
1050 }
1051
1052 /* Enable the Peripheral */
1053 __HAL_GPT_ENABLE(htim);
1054
1055 /* Return function status */
1056 return HAL_OK;
1057 }
1058
1059 /**
1060 * @brief Stops the PWM signal generation.
1061 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1062 * the configuration information for TIM module.
1063 * @param Channel TIM Channels to be disabled.
1064 * This parameter can be one of the following values:
1065 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
1066 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
1067 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
1068 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
1069 * @retval HAL status
1070 */
HAL_GPT_PWM_Stop(GPT_HandleTypeDef * htim,uint32_t Channel)1071 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_PWM_Stop(GPT_HandleTypeDef *htim, uint32_t Channel)
1072 {
1073 /* Check the parameters */
1074 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
1075
1076 /* Disable the Capture compare channel */
1077 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_DISABLE);
1078
1079 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
1080 {
1081 /* Disable the Main Output */
1082 __HAL_GPT_MOE_DISABLE(htim);
1083 }
1084
1085 /* Disable the Peripheral */
1086 __HAL_GPT_DISABLE(htim);
1087
1088 /* Change the htim state */
1089 htim->State = HAL_GPT_STATE_READY;
1090
1091 /* Return function status */
1092 return HAL_OK;
1093 }
1094
1095 /**
1096 * @brief Starts the PWM signal generation in interrupt mode.
1097 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1098 * the configuration information for TIM module.
1099 * @param Channel TIM Channel to be enabled.
1100 * This parameter can be one of the following values:
1101 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
1102 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
1103 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
1104 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
1105 * @retval HAL status
1106 */
HAL_GPT_PWM_Start_IT(GPT_HandleTypeDef * htim,uint32_t Channel)1107 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_PWM_Start_IT(GPT_HandleTypeDef *htim, uint32_t Channel)
1108 {
1109 /* Check the parameters */
1110 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
1111
1112 switch (Channel)
1113 {
1114 case GPT_CHANNEL_1:
1115 {
1116 /* Enable the TIM Capture/Compare 1 interrupt */
1117 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC1);
1118 }
1119 break;
1120
1121 case GPT_CHANNEL_2:
1122 {
1123 /* Enable the TIM Capture/Compare 2 interrupt */
1124 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC2);
1125 }
1126 break;
1127
1128 case GPT_CHANNEL_3:
1129 {
1130 /* Enable the TIM Capture/Compare 3 interrupt */
1131 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC3);
1132 }
1133 break;
1134
1135 case GPT_CHANNEL_4:
1136 {
1137 /* Enable the TIM Capture/Compare 4 interrupt */
1138 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC4);
1139 }
1140 break;
1141
1142 default:
1143 break;
1144 }
1145
1146 /* Enable the Capture compare channel */
1147 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_ENABLE);
1148
1149 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
1150 {
1151 /* Enable the main output */
1152 __HAL_GPT_MOE_ENABLE(htim);
1153 }
1154
1155 /* Enable the Peripheral */
1156 __HAL_GPT_ENABLE(htim);
1157
1158 /* Return function status */
1159 return HAL_OK;
1160 }
1161
1162 /**
1163 * @brief Stops the PWM signal generation in interrupt mode.
1164 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1165 * the configuration information for TIM module.
1166 * @param Channel TIM Channels to be disabled.
1167 * This parameter can be one of the following values:
1168 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
1169 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
1170 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
1171 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
1172 * @retval HAL status
1173 */
HAL_GPT_PWM_Stop_IT(GPT_HandleTypeDef * htim,uint32_t Channel)1174 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_PWM_Stop_IT(GPT_HandleTypeDef *htim, uint32_t Channel)
1175 {
1176 /* Check the parameters */
1177 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
1178
1179 switch (Channel)
1180 {
1181 case GPT_CHANNEL_1:
1182 {
1183 /* Disable the TIM Capture/Compare 1 interrupt */
1184 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC1);
1185 }
1186 break;
1187
1188 case GPT_CHANNEL_2:
1189 {
1190 /* Disable the TIM Capture/Compare 2 interrupt */
1191 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC2);
1192 }
1193 break;
1194
1195 case GPT_CHANNEL_3:
1196 {
1197 /* Disable the TIM Capture/Compare 3 interrupt */
1198 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC3);
1199 }
1200 break;
1201
1202 case GPT_CHANNEL_4:
1203 {
1204 /* Disable the TIM Capture/Compare 4 interrupt */
1205 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC4);
1206 }
1207 break;
1208
1209 default:
1210 break;
1211 }
1212
1213 /* Disable the Capture compare channel */
1214 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_DISABLE);
1215
1216 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
1217 {
1218 /* Disable the Main Output */
1219 __HAL_GPT_MOE_DISABLE(htim);
1220 }
1221
1222 /* Disable the Peripheral */
1223 __HAL_GPT_DISABLE(htim);
1224
1225 /* Return function status */
1226 return HAL_OK;
1227 }
1228
1229 /**
1230 * @brief Starts the TIM PWM signal generation in CCX DMA mode.
1231 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1232 * the configuration information for TIM module.
1233 * @param Channel TIM Channels to be enabled.
1234 * This parameter can be one of the following values:
1235 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
1236 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
1237 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
1238 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
1239 * @param pData The source Buffer address.
1240 * @param Length The length of data to be transferred from memory to TIM peripheral
1241 * @retval HAL status
1242 */
HAL_GPT_PWM_Start_DMA(GPT_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1243 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_PWM_Start_DMA(GPT_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1244 {
1245 /* Check the parameters */
1246 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
1247
1248 if (htim->State == HAL_GPT_STATE_BUSY)
1249 {
1250 return HAL_BUSY;
1251 }
1252 else if (htim->State == HAL_GPT_STATE_READY)
1253 {
1254 if (((uint32_t)pData == 0U) && (Length > 0))
1255 {
1256 return HAL_ERROR;
1257 }
1258 else
1259 {
1260 htim->State = HAL_GPT_STATE_BUSY;
1261 }
1262 }
1263 switch (Channel)
1264 {
1265 case GPT_CHANNEL_1:
1266 {
1267 /* Set the DMA Period elapsed callback */
1268 htim->hdma[GPT_DMA_ID_CC1]->XferCpltCallback = GPT_DMADelayPulseCplt;
1269
1270 /* Set the DMA error callback */
1271 htim->hdma[GPT_DMA_ID_CC1]->XferErrorCallback = GPT_DMAError ;
1272
1273 /* Enable the DMA Stream */
1274 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
1275
1276 /* Enable the TIM Capture/Compare 1 DMA request */
1277 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC1);
1278 }
1279 break;
1280
1281 case GPT_CHANNEL_2:
1282 {
1283 /* Set the DMA Period elapsed callback */
1284 htim->hdma[GPT_DMA_ID_CC2]->XferCpltCallback = GPT_DMADelayPulseCplt;
1285
1286 /* Set the DMA error callback */
1287 htim->hdma[GPT_DMA_ID_CC2]->XferErrorCallback = GPT_DMAError ;
1288
1289 /* Enable the DMA Stream */
1290 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
1291
1292 /* Enable the TIM Capture/Compare 2 DMA request */
1293 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC2);
1294 }
1295 break;
1296
1297 case GPT_CHANNEL_3:
1298 {
1299 /* Set the DMA Period elapsed callback */
1300 htim->hdma[GPT_DMA_ID_CC3]->XferCpltCallback = GPT_DMADelayPulseCplt;
1301
1302 /* Set the DMA error callback */
1303 htim->hdma[GPT_DMA_ID_CC3]->XferErrorCallback = GPT_DMAError ;
1304
1305 /* Enable the DMA Stream */
1306 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length);
1307
1308 /* Enable the TIM Output Capture/Compare 3 request */
1309 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC3);
1310 }
1311 break;
1312
1313 case GPT_CHANNEL_4:
1314 {
1315 /* Set the DMA Period elapsed callback */
1316 htim->hdma[GPT_DMA_ID_CC4]->XferCpltCallback = GPT_DMADelayPulseCplt;
1317
1318 /* Set the DMA error callback */
1319 htim->hdma[GPT_DMA_ID_CC4]->XferErrorCallback = GPT_DMAError ;
1320
1321 /* Enable the DMA Stream */
1322 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
1323
1324 /* Enable the TIM Capture/Compare 4 DMA request */
1325 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC4);
1326 }
1327 break;
1328
1329 default:
1330 break;
1331 }
1332
1333 /* Enable the Capture compare channel */
1334 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_ENABLE);
1335
1336 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
1337 {
1338 /* Enable the main output */
1339 __HAL_GPT_MOE_ENABLE(htim);
1340 }
1341
1342 /* Enable the Peripheral */
1343 __HAL_GPT_ENABLE(htim);
1344
1345 /* Return function status */
1346 return HAL_OK;
1347 }
1348
1349 /**
1350 * @brief Starts the TIM PWM signal generation in Update DMA mode.
1351 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1352 * the configuration information for TIM module.
1353 * @param Channel TIM Channels to be enabled.
1354 * This parameter can be one of the following values:
1355 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
1356 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
1357 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
1358 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
1359 * @param pData The source Buffer address.
1360 * @param Length The length of data to be transferred from memory to TIM peripheral
1361 * @retval HAL status
1362 */
HAL_GPT_PWM_Update_Start_DMA(GPT_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1363 HAL_StatusTypeDef HAL_GPT_PWM_Update_Start_DMA(GPT_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1364 {
1365 /* Check the parameters */
1366 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
1367
1368 if (htim->State == HAL_GPT_STATE_BUSY)
1369 {
1370 return HAL_BUSY;
1371 }
1372 else if (htim->State == HAL_GPT_STATE_READY)
1373 {
1374 if (((uint32_t)pData == 0U) && (Length > 0))
1375 {
1376 return HAL_ERROR;
1377 }
1378 else
1379 {
1380 htim->State = HAL_GPT_STATE_BUSY;
1381 }
1382 }
1383
1384 /* Set the DMA Period elapsed callback */
1385 htim->hdma[GPT_DMA_ID_UPDATE]->XferCpltCallback = GPT_DMADelayPulseCplt;
1386
1387 /* Set the DMA error callback */
1388 htim->hdma[GPT_DMA_ID_UPDATE]->XferErrorCallback = GPT_DMAError ;
1389
1390 switch (Channel)
1391 {
1392 case GPT_CHANNEL_1:
1393 {
1394 /* Enable the DMA Stream */
1395 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
1396 }
1397 break;
1398
1399 case GPT_CHANNEL_2:
1400 {
1401 /* Enable the DMA Stream */
1402 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
1403
1404 }
1405 break;
1406
1407 case GPT_CHANNEL_3:
1408 {
1409 /* Enable the DMA Stream */
1410 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length);
1411 }
1412 break;
1413
1414 case GPT_CHANNEL_4:
1415 {
1416 /* Enable the DMA Stream */
1417 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
1418 }
1419 break;
1420
1421 default:
1422 break;
1423 }
1424
1425 /* Enable the TIM Update DMA request */
1426 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_UPDATE);
1427
1428 /* Enable the Capture compare channel */
1429 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_ENABLE);
1430
1431 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
1432 {
1433 /* Enable the main output */
1434 __HAL_GPT_MOE_ENABLE(htim);
1435 }
1436
1437 /* Enable the Peripheral */
1438 __HAL_GPT_ENABLE(htim);
1439
1440 /* Return function status */
1441 return HAL_OK;
1442 }
1443
1444 /**
1445 * @brief Stops the TIM PWM signal generation in CCX DMA mode.
1446 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1447 * the configuration information for TIM module.
1448 * @param Channel TIM Channels to be disabled.
1449 * This parameter can be one of the following values:
1450 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
1451 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
1452 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
1453 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
1454 * @retval HAL status
1455 */
HAL_GPT_PWM_Stop_DMA(GPT_HandleTypeDef * htim,uint32_t Channel)1456 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_PWM_Stop_DMA(GPT_HandleTypeDef *htim, uint32_t Channel)
1457 {
1458 /* Check the parameters */
1459 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
1460
1461 switch (Channel)
1462 {
1463 case GPT_CHANNEL_1:
1464 {
1465 /* Disable the TIM Capture/Compare 1 DMA request */
1466 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC1);
1467 }
1468 break;
1469
1470 case GPT_CHANNEL_2:
1471 {
1472 /* Disable the TIM Capture/Compare 2 DMA request */
1473 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC2);
1474 }
1475 break;
1476
1477 case GPT_CHANNEL_3:
1478 {
1479 /* Disable the TIM Capture/Compare 3 DMA request */
1480 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC3);
1481 }
1482 break;
1483
1484 case GPT_CHANNEL_4:
1485 {
1486 /* Disable the TIM Capture/Compare 4 interrupt */
1487 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC4);
1488 }
1489 break;
1490
1491 default:
1492 break;
1493 }
1494
1495 /* Disable the Capture compare channel */
1496 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_DISABLE);
1497
1498 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
1499 {
1500 /* Disable the Main Output */
1501 __HAL_GPT_MOE_DISABLE(htim);
1502 }
1503
1504 /* Disable the Peripheral */
1505 __HAL_GPT_DISABLE(htim);
1506
1507 /* Change the htim state */
1508 htim->State = HAL_GPT_STATE_READY;
1509
1510 /* Return function status */
1511 return HAL_OK;
1512 }
1513
1514 /**
1515 * @brief Stops the TIM PWM signal generation in Update DMA mode.
1516 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1517 * the configuration information for TIM module.
1518 * @param Channel TIM Channels to be disabled.
1519 * This parameter can be one of the following values:
1520 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
1521 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
1522 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
1523 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
1524 * @retval HAL status
1525 */
HAL_GPT_PWM_Update_Stop_DMA(GPT_HandleTypeDef * htim,uint32_t Channel)1526 HAL_StatusTypeDef HAL_GPT_PWM_Update_Stop_DMA(GPT_HandleTypeDef *htim, uint32_t Channel)
1527 {
1528 /* Check the parameters */
1529 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
1530
1531 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_UPDATE);
1532
1533 /* Disable the Capture compare channel */
1534 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_DISABLE);
1535
1536 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
1537 {
1538 /* Disable the Main Output */
1539 __HAL_GPT_MOE_DISABLE(htim);
1540 }
1541
1542 /* Disable the Peripheral */
1543 __HAL_GPT_DISABLE(htim);
1544
1545 /* Change the htim state */
1546 htim->State = HAL_GPT_STATE_READY;
1547
1548 /* Return function status */
1549 return HAL_OK;
1550 }
1551
1552 /**
1553 * @}
1554 */
1555
1556 /** @defgroup GPT_Exported_Functions_Group4 Time Input Capture functions
1557 * @brief Time Input Capture functions
1558 *
1559 @verbatim
1560 ==============================================================================
1561 ##### Time Input Capture functions #####
1562 ==============================================================================
1563 [..]
1564 This section provides functions allowing to:
1565 (+) Initialize and configure the TIM Input Capture.
1566 (+) De-initialize the TIM Input Capture.
1567 (+) Start the Time Input Capture.
1568 (+) Stop the Time Input Capture.
1569 (+) Start the Time Input Capture and enable interrupt.
1570 (+) Stop the Time Input Capture and disable interrupt.
1571 (+) Start the Time Input Capture and enable DMA transfer.
1572 (+) Stop the Time Input Capture and disable DMA transfer.
1573
1574 @endverbatim
1575 * @{
1576 */
1577 /**
1578 * @brief Initializes the TIM Input Capture Time base according to the specified
1579 * parameters in the GPT_HandleTypeDef and create the associated handle.
1580 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1581 * the configuration information for TIM module.
1582 * @retval HAL status
1583 */
HAL_GPT_IC_Init(GPT_HandleTypeDef * htim)1584 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_IC_Init(GPT_HandleTypeDef *htim)
1585 {
1586 /* Check the TIM handle allocation */
1587 if (htim == NULL)
1588 {
1589 return HAL_ERROR;
1590 }
1591
1592 /* Check the parameters */
1593 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
1594 HAL_ASSERT(IS_GPT_COUNTER_MODE(htim->Init.CounterMode));
1595
1596 if (htim->State == HAL_GPT_STATE_RESET)
1597 {
1598 /* Allocate lock resource and initialize it */
1599 htim->Lock = HAL_UNLOCKED;
1600 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1601 HAL_GPT_IC_MspInit(htim);
1602 }
1603
1604 /* Set the TIM state */
1605 htim->State = HAL_GPT_STATE_BUSY;
1606
1607 /* Init the base time for the input capture */
1608 GPT_Base_SetConfig(htim->Instance, &htim->Init);
1609
1610 /* Initialize the TIM state*/
1611 htim->State = HAL_GPT_STATE_READY;
1612
1613 return HAL_OK;
1614 }
1615
1616 /**
1617 * @brief DeInitializes the TIM peripheral
1618 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1619 * the configuration information for TIM module.
1620 * @retval HAL status
1621 */
HAL_GPT_IC_DeInit(GPT_HandleTypeDef * htim)1622 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_IC_DeInit(GPT_HandleTypeDef *htim)
1623 {
1624 /* Check the parameters */
1625 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
1626
1627 htim->State = HAL_GPT_STATE_BUSY;
1628
1629 /* Disable the TIM Peripheral Clock */
1630 __HAL_GPT_DISABLE(htim);
1631
1632 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1633 HAL_GPT_IC_MspDeInit(htim);
1634
1635 /* Change TIM state */
1636 htim->State = HAL_GPT_STATE_RESET;
1637
1638 /* Release Lock */
1639 __HAL_UNLOCK(htim);
1640
1641 return HAL_OK;
1642 }
1643
1644 /**
1645 * @brief Initializes the TIM INput Capture MSP.
1646 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1647 * the configuration information for TIM module.
1648 * @retval None
1649 */
HAL_GPT_IC_MspInit(GPT_HandleTypeDef * htim)1650 __weak void HAL_GPT_IC_MspInit(GPT_HandleTypeDef *htim)
1651 {
1652 /* Prevent unused argument(s) compilation warning */
1653 UNUSED(htim);
1654 /* NOTE : This function Should not be modified, when the callback is needed,
1655 the HAL_GPT_IC_MspInit could be implemented in the user file
1656 */
1657 }
1658
1659 /**
1660 * @brief DeInitializes TIM Input Capture MSP.
1661 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1662 * the configuration information for TIM module.
1663 * @retval None
1664 */
HAL_GPT_IC_MspDeInit(GPT_HandleTypeDef * htim)1665 __weak void HAL_GPT_IC_MspDeInit(GPT_HandleTypeDef *htim)
1666 {
1667 /* Prevent unused argument(s) compilation warning */
1668 UNUSED(htim);
1669 /* NOTE : This function Should not be modified, when the callback is needed,
1670 the HAL_GPT_IC_MspDeInit could be implemented in the user file
1671 */
1672 }
1673
1674 /**
1675 * @brief Starts the TIM Input Capture measurement.
1676 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1677 * the configuration information for TIM module.
1678 * @param Channel TIM Channels to be enabled.
1679 * This parameter can be one of the following values:
1680 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
1681 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
1682 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
1683 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
1684 * @retval HAL status
1685 */
HAL_GPT_IC_Start(GPT_HandleTypeDef * htim,uint32_t Channel)1686 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_IC_Start(GPT_HandleTypeDef *htim, uint32_t Channel)
1687 {
1688 /* Check the parameters */
1689 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
1690
1691 /* Enable the Input Capture channel */
1692 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_ENABLE);
1693
1694 /* Enable the Peripheral */
1695 __HAL_GPT_ENABLE(htim);
1696
1697 /* Return function status */
1698 return HAL_OK;
1699 }
1700
1701 /**
1702 * @brief Stops the TIM Input Capture measurement.
1703 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1704 * the configuration information for TIM module.
1705 * @param Channel TIM Channels to be disabled.
1706 * This parameter can be one of the following values:
1707 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
1708 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
1709 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
1710 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
1711 * @retval HAL status
1712 */
HAL_GPT_IC_Stop(GPT_HandleTypeDef * htim,uint32_t Channel)1713 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_IC_Stop(GPT_HandleTypeDef *htim, uint32_t Channel)
1714 {
1715 /* Check the parameters */
1716 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
1717
1718 /* Disable the Input Capture channel */
1719 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_DISABLE);
1720
1721 /* Disable the Peripheral */
1722 __HAL_GPT_DISABLE(htim);
1723
1724 /* Return function status */
1725 return HAL_OK;
1726 }
1727
1728 /**
1729 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1730 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1731 * the configuration information for TIM module.
1732 * @param Channel TIM Channels to be enabled.
1733 * This parameter can be one of the following values:
1734 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
1735 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
1736 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
1737 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
1738 * @retval HAL status
1739 */
HAL_GPT_IC_Start_IT(GPT_HandleTypeDef * htim,uint32_t Channel)1740 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_IC_Start_IT(GPT_HandleTypeDef *htim, uint32_t Channel)
1741 {
1742 /* Check the parameters */
1743 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
1744
1745 switch (Channel)
1746 {
1747 case GPT_CHANNEL_1:
1748 {
1749 /* Enable the TIM Capture/Compare 1 interrupt */
1750 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC1);
1751 }
1752 break;
1753
1754 case GPT_CHANNEL_2:
1755 {
1756 /* Enable the TIM Capture/Compare 2 interrupt */
1757 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC2);
1758 }
1759 break;
1760
1761 case GPT_CHANNEL_3:
1762 {
1763 /* Enable the TIM Capture/Compare 3 interrupt */
1764 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC3);
1765 }
1766 break;
1767
1768 case GPT_CHANNEL_4:
1769 {
1770 /* Enable the TIM Capture/Compare 4 interrupt */
1771 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC4);
1772 }
1773 break;
1774
1775 default:
1776 break;
1777 }
1778 /* Enable the Input Capture channel */
1779 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_ENABLE);
1780
1781 /* Enable the Peripheral */
1782 __HAL_GPT_ENABLE(htim);
1783
1784 /* Return function status */
1785 return HAL_OK;
1786 }
1787
1788 /**
1789 * @brief Stops the TIM Input Capture measurement in interrupt mode.
1790 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1791 * the configuration information for TIM module.
1792 * @param Channel TIM Channels to be disabled.
1793 * This parameter can be one of the following values:
1794 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
1795 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
1796 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
1797 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
1798 * @retval HAL status
1799 */
HAL_GPT_IC_Stop_IT(GPT_HandleTypeDef * htim,uint32_t Channel)1800 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_IC_Stop_IT(GPT_HandleTypeDef *htim, uint32_t Channel)
1801 {
1802 /* Check the parameters */
1803 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
1804
1805 switch (Channel)
1806 {
1807 case GPT_CHANNEL_1:
1808 {
1809 /* Disable the TIM Capture/Compare 1 interrupt */
1810 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC1);
1811 }
1812 break;
1813
1814 case GPT_CHANNEL_2:
1815 {
1816 /* Disable the TIM Capture/Compare 2 interrupt */
1817 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC2);
1818 }
1819 break;
1820
1821 case GPT_CHANNEL_3:
1822 {
1823 /* Disable the TIM Capture/Compare 3 interrupt */
1824 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC3);
1825 }
1826 break;
1827
1828 case GPT_CHANNEL_4:
1829 {
1830 /* Disable the TIM Capture/Compare 4 interrupt */
1831 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC4);
1832 }
1833 break;
1834
1835 default:
1836 break;
1837 }
1838
1839 /* Disable the Input Capture channel */
1840 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_DISABLE);
1841
1842 /* Disable the Peripheral */
1843 __HAL_GPT_DISABLE(htim);
1844
1845 /* Return function status */
1846 return HAL_OK;
1847 }
1848
1849 /**
1850 * @brief Starts the TIM Input Capture measurement on in DMA mode.
1851 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1852 * the configuration information for TIM module.
1853 * @param Channel TIM Channels to be enabled.
1854 * This parameter can be one of the following values:
1855 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
1856 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
1857 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
1858 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
1859 * @param pData The destination Buffer address.
1860 * @param Length The length of data to be transferred from TIM peripheral to memory.
1861 * @retval HAL status
1862 */
HAL_GPT_IC_Start_DMA(GPT_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1863 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_IC_Start_DMA(GPT_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1864 {
1865 /* Check the parameters */
1866 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
1867 HAL_ASSERT(IS_GPT_DMA_CC_INSTANCE(htim->Instance));
1868
1869 if (htim->State == HAL_GPT_STATE_BUSY)
1870 {
1871 return HAL_BUSY;
1872 }
1873 else if (htim->State == HAL_GPT_STATE_READY)
1874 {
1875 if ((pData == 0U) && (Length > 0))
1876 {
1877 return HAL_ERROR;
1878 }
1879 else
1880 {
1881 htim->State = HAL_GPT_STATE_BUSY;
1882 }
1883 }
1884
1885 switch (Channel)
1886 {
1887 case GPT_CHANNEL_1:
1888 {
1889 /* Set the DMA Period elapsed callback */
1890 htim->hdma[GPT_DMA_ID_CC1]->XferCpltCallback = GPT_DMACaptureCplt;
1891
1892 /* Set the DMA error callback */
1893 htim->hdma[GPT_DMA_ID_CC1]->XferErrorCallback = GPT_DMAError ;
1894
1895 /* Enable the DMA Stream */
1896 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
1897
1898 /* Enable the TIM Capture/Compare 1 DMA request */
1899 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC1);
1900 }
1901 break;
1902
1903 case GPT_CHANNEL_2:
1904 {
1905 /* Set the DMA Period elapsed callback */
1906 htim->hdma[GPT_DMA_ID_CC2]->XferCpltCallback = GPT_DMACaptureCplt;
1907
1908 /* Set the DMA error callback */
1909 htim->hdma[GPT_DMA_ID_CC2]->XferErrorCallback = GPT_DMAError ;
1910
1911 /* Enable the DMA Stream */
1912 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
1913
1914 /* Enable the TIM Capture/Compare 2 DMA request */
1915 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC2);
1916 }
1917 break;
1918
1919 case GPT_CHANNEL_3:
1920 {
1921 /* Set the DMA Period elapsed callback */
1922 htim->hdma[GPT_DMA_ID_CC3]->XferCpltCallback = GPT_DMACaptureCplt;
1923
1924 /* Set the DMA error callback */
1925 htim->hdma[GPT_DMA_ID_CC3]->XferErrorCallback = GPT_DMAError ;
1926
1927 /* Enable the DMA Stream */
1928 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
1929
1930 /* Enable the TIM Capture/Compare 3 DMA request */
1931 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC3);
1932 }
1933 break;
1934
1935 case GPT_CHANNEL_4:
1936 {
1937 /* Set the DMA Period elapsed callback */
1938 htim->hdma[GPT_DMA_ID_CC4]->XferCpltCallback = GPT_DMACaptureCplt;
1939
1940 /* Set the DMA error callback */
1941 htim->hdma[GPT_DMA_ID_CC4]->XferErrorCallback = GPT_DMAError ;
1942
1943 /* Enable the DMA Stream */
1944 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
1945
1946 /* Enable the TIM Capture/Compare 4 DMA request */
1947 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC4);
1948 }
1949 break;
1950
1951 default:
1952 break;
1953 }
1954
1955 /* Enable the Input Capture channel */
1956 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_ENABLE);
1957
1958 /* Enable the Peripheral */
1959 __HAL_GPT_ENABLE(htim);
1960
1961 /* Return function status */
1962 return HAL_OK;
1963 }
1964
1965 /**
1966 * @brief Stops the TIM Input Capture measurement on in DMA mode.
1967 * @param htim pointer to a GPT_HandleTypeDef structure that contains
1968 * the configuration information for TIM module.
1969 * @param Channel TIM Channels to be disabled.
1970 * This parameter can be one of the following values:
1971 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
1972 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
1973 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
1974 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
1975 * @retval HAL status
1976 */
HAL_GPT_IC_Stop_DMA(GPT_HandleTypeDef * htim,uint32_t Channel)1977 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_IC_Stop_DMA(GPT_HandleTypeDef *htim, uint32_t Channel)
1978 {
1979 /* Check the parameters */
1980 HAL_ASSERT(IS_GPT_CCX_INSTANCE(htim->Instance, Channel));
1981 HAL_ASSERT(IS_GPT_DMA_CC_INSTANCE(htim->Instance));
1982
1983 switch (Channel)
1984 {
1985 case GPT_CHANNEL_1:
1986 {
1987 /* Disable the TIM Capture/Compare 1 DMA request */
1988 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC1);
1989 }
1990 break;
1991
1992 case GPT_CHANNEL_2:
1993 {
1994 /* Disable the TIM Capture/Compare 2 DMA request */
1995 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC2);
1996 }
1997 break;
1998
1999 case GPT_CHANNEL_3:
2000 {
2001 /* Disable the TIM Capture/Compare 3 DMA request */
2002 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC3);
2003 }
2004 break;
2005
2006 case GPT_CHANNEL_4:
2007 {
2008 /* Disable the TIM Capture/Compare 4 DMA request */
2009 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC4);
2010 }
2011 break;
2012
2013 default:
2014 break;
2015 }
2016
2017 /* Disable the Input Capture channel */
2018 GPT_CCxChannelCmd(htim->Instance, Channel, GPT_CCx_DISABLE);
2019
2020 /* Disable the Peripheral */
2021 __HAL_GPT_DISABLE(htim);
2022
2023 /* Change the htim state */
2024 htim->State = HAL_GPT_STATE_READY;
2025
2026 /* Return function status */
2027 return HAL_OK;
2028 }
2029 /**
2030 * @}
2031 */
2032
2033 /** @defgroup GPT_Exported_Functions_Group5 Time One Pulse functions
2034 * @brief Time One Pulse functions
2035 *
2036 @verbatim
2037 ==============================================================================
2038 ##### Time One Pulse functions #####
2039 ==============================================================================
2040 [..]
2041 This section provides functions allowing to:
2042 (+) Initialize and configure the TIM One Pulse.
2043 (+) De-initialize the TIM One Pulse.
2044 (+) Start the Time One Pulse.
2045 (+) Stop the Time One Pulse.
2046 (+) Start the Time One Pulse and enable interrupt.
2047 (+) Stop the Time One Pulse and disable interrupt.
2048 (+) Start the Time One Pulse and enable DMA transfer.
2049 (+) Stop the Time One Pulse and disable DMA transfer.
2050
2051 @endverbatim
2052 * @{
2053 */
2054 /**
2055 * @brief Initializes the TIM One Pulse Time Base according to the specified
2056 * parameters in the GPT_HandleTypeDef and create the associated handle.
2057 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2058 * the configuration information for TIM module.
2059 * @param OnePulseMode Select the One pulse mode.
2060 * This parameter can be one of the following values:
2061 * @arg GPT_OPMODE_SINGLE: Only one pulse will be generated.
2062 * @arg GPT_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2063 * @retval HAL status
2064 */
HAL_GPT_OnePulse_Init(GPT_HandleTypeDef * htim,uint32_t OnePulseMode)2065 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OnePulse_Init(GPT_HandleTypeDef *htim, uint32_t OnePulseMode)
2066 {
2067 /* Check the TIM handle allocation */
2068 if (htim == NULL)
2069 {
2070 return HAL_ERROR;
2071 }
2072
2073 /* Check the parameters */
2074 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
2075 HAL_ASSERT(IS_GPT_COUNTER_MODE(htim->Init.CounterMode));
2076 HAL_ASSERT(IS_GPT_OPM_MODE(OnePulseMode));
2077
2078 if (htim->State == HAL_GPT_STATE_RESET)
2079 {
2080 /* Allocate lock resource and initialize it */
2081 htim->Lock = HAL_UNLOCKED;
2082 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2083 HAL_GPT_OnePulse_MspInit(htim);
2084 }
2085
2086 /* Set the TIM state */
2087 htim->State = HAL_GPT_STATE_BUSY;
2088
2089 /* Configure the Time base in the One Pulse Mode */
2090 GPT_Base_SetConfig(htim->Instance, &htim->Init);
2091
2092 /* Reset the OPM Bit */
2093 htim->Instance->CR1 &= ~GPT_CR1_OPM;
2094
2095 /* Configure the OPM Mode */
2096 htim->Instance->CR1 |= OnePulseMode;
2097
2098 /* Initialize the TIM state*/
2099 htim->State = HAL_GPT_STATE_READY;
2100
2101 return HAL_OK;
2102 }
2103
2104 /**
2105 * @brief DeInitializes the TIM One Pulse
2106 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2107 * the configuration information for TIM module.
2108 * @retval HAL status
2109 */
HAL_GPT_OnePulse_DeInit(GPT_HandleTypeDef * htim)2110 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OnePulse_DeInit(GPT_HandleTypeDef *htim)
2111 {
2112 /* Check the parameters */
2113 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
2114
2115 htim->State = HAL_GPT_STATE_BUSY;
2116
2117 /* Disable the TIM Peripheral Clock */
2118 __HAL_GPT_DISABLE(htim);
2119
2120 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2121 HAL_GPT_OnePulse_MspDeInit(htim);
2122
2123 /* Change TIM state */
2124 htim->State = HAL_GPT_STATE_RESET;
2125
2126 /* Release Lock */
2127 __HAL_UNLOCK(htim);
2128
2129 return HAL_OK;
2130 }
2131
2132 /**
2133 * @brief Initializes the TIM One Pulse MSP.
2134 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2135 * the configuration information for TIM module.
2136 * @retval None
2137 */
HAL_GPT_OnePulse_MspInit(GPT_HandleTypeDef * htim)2138 __weak void HAL_GPT_OnePulse_MspInit(GPT_HandleTypeDef *htim)
2139 {
2140 /* Prevent unused argument(s) compilation warning */
2141 UNUSED(htim);
2142 /* NOTE : This function Should not be modified, when the callback is needed,
2143 the HAL_GPT_OnePulse_MspInit could be implemented in the user file
2144 */
2145 }
2146
2147 /**
2148 * @brief DeInitializes TIM One Pulse MSP.
2149 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2150 * the configuration information for TIM module.
2151 * @retval None
2152 */
HAL_GPT_OnePulse_MspDeInit(GPT_HandleTypeDef * htim)2153 __weak void HAL_GPT_OnePulse_MspDeInit(GPT_HandleTypeDef *htim)
2154 {
2155 /* Prevent unused argument(s) compilation warning */
2156 UNUSED(htim);
2157 /* NOTE : This function Should not be modified, when the callback is needed,
2158 the HAL_GPT_OnePulse_MspDeInit could be implemented in the user file
2159 */
2160 }
2161
2162 /**
2163 * @brief Starts the TIM One Pulse signal generation.
2164 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2165 * the configuration information for TIM module.
2166 * @param OutputChannel TIM Channels to be enabled.
2167 * This parameter can be one of the following values:
2168 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
2169 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
2170 * @retval HAL status
2171 */
HAL_GPT_OnePulse_Start(GPT_HandleTypeDef * htim,uint32_t OutputChannel)2172 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OnePulse_Start(GPT_HandleTypeDef *htim, uint32_t OutputChannel)
2173 {
2174 /* Prevent unused argument(s) compilation warning */
2175 UNUSED(OutputChannel);
2176
2177 /* Enable the Capture compare and the Input Capture channels
2178 (in the OPM Mode the two possible channels that can be used are GPT_CHANNEL_1 and GPT_CHANNEL_2)
2179 if GPT_CHANNEL_1 is used as output, the GPT_CHANNEL_2 will be used as input and
2180 if GPT_CHANNEL_1 is used as input, the GPT_CHANNEL_2 will be used as output
2181 in all combinations, the GPT_CHANNEL_1 and GPT_CHANNEL_2 should be enabled together
2182
2183 No need to enable the counter, it's enabled automatically by hardware
2184 (the counter starts in response to a stimulus and generate a pulse */
2185
2186 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_ENABLE);
2187 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_ENABLE);
2188
2189 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
2190 {
2191 /* Enable the main output */
2192 __HAL_GPT_MOE_ENABLE(htim);
2193 }
2194
2195 /* Return function status */
2196 return HAL_OK;
2197 }
2198
2199 /**
2200 * @brief Stops the TIM One Pulse signal generation.
2201 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2202 * the configuration information for TIM module.
2203 * @param OutputChannel TIM Channels to be disable.
2204 * This parameter can be one of the following values:
2205 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
2206 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
2207 * @retval HAL status
2208 */
HAL_GPT_OnePulse_Stop(GPT_HandleTypeDef * htim,uint32_t OutputChannel)2209 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OnePulse_Stop(GPT_HandleTypeDef *htim, uint32_t OutputChannel)
2210 {
2211 /* Prevent unused argument(s) compilation warning */
2212 UNUSED(OutputChannel);
2213
2214 /* Disable the Capture compare and the Input Capture channels
2215 (in the OPM Mode the two possible channels that can be used are GPT_CHANNEL_1 and GPT_CHANNEL_2)
2216 if GPT_CHANNEL_1 is used as output, the GPT_CHANNEL_2 will be used as input and
2217 if GPT_CHANNEL_1 is used as input, the GPT_CHANNEL_2 will be used as output
2218 in all combinations, the GPT_CHANNEL_1 and GPT_CHANNEL_2 should be disabled together */
2219
2220 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_DISABLE);
2221 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_DISABLE);
2222
2223 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
2224 {
2225 /* Disable the Main Output */
2226 __HAL_GPT_MOE_DISABLE(htim);
2227 }
2228
2229 /* Disable the Peripheral */
2230 __HAL_GPT_DISABLE(htim);
2231
2232 /* Return function status */
2233 return HAL_OK;
2234 }
2235
2236 /**
2237 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2238 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2239 * the configuration information for TIM module.
2240 * @param OutputChannel TIM Channels to be enabled.
2241 * This parameter can be one of the following values:
2242 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
2243 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
2244 * @retval HAL status
2245 */
HAL_GPT_OnePulse_Start_IT(GPT_HandleTypeDef * htim,uint32_t OutputChannel)2246 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OnePulse_Start_IT(GPT_HandleTypeDef *htim, uint32_t OutputChannel)
2247 {
2248 /* Enable the Capture compare and the Input Capture channels
2249 (in the OPM Mode the two possible channels that can be used are GPT_CHANNEL_1 and GPT_CHANNEL_2)
2250 if GPT_CHANNEL_1 is used as output, the GPT_CHANNEL_2 will be used as input and
2251 if GPT_CHANNEL_1 is used as input, the GPT_CHANNEL_2 will be used as output
2252 in all combinations, the GPT_CHANNEL_1 and GPT_CHANNEL_2 should be enabled together
2253
2254 No need to enable the counter, it's enabled automatically by hardware
2255 (the counter starts in response to a stimulus and generate a pulse */
2256
2257 /* Prevent unused argument(s) compilation warning */
2258 UNUSED(OutputChannel);
2259
2260 /* Enable the TIM Capture/Compare 1 interrupt */
2261 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC1);
2262
2263 /* Enable the TIM Capture/Compare 2 interrupt */
2264 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC2);
2265
2266 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_ENABLE);
2267 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_ENABLE);
2268
2269 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
2270 {
2271 /* Enable the main output */
2272 __HAL_GPT_MOE_ENABLE(htim);
2273 }
2274
2275 /* Return function status */
2276 return HAL_OK;
2277 }
2278
2279 /**
2280 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2281 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2282 * the configuration information for TIM module.
2283 * @param OutputChannel TIM Channels to be enabled.
2284 * This parameter can be one of the following values:
2285 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
2286 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
2287 * @retval HAL status
2288 */
HAL_GPT_OnePulse_Stop_IT(GPT_HandleTypeDef * htim,uint32_t OutputChannel)2289 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OnePulse_Stop_IT(GPT_HandleTypeDef *htim, uint32_t OutputChannel)
2290 {
2291 /* Prevent unused argument(s) compilation warning */
2292 UNUSED(OutputChannel);
2293
2294 /* Disable the TIM Capture/Compare 1 interrupt */
2295 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC1);
2296
2297 /* Disable the TIM Capture/Compare 2 interrupt */
2298 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC2);
2299
2300 /* Disable the Capture compare and the Input Capture channels
2301 (in the OPM Mode the two possible channels that can be used are GPT_CHANNEL_1 and GPT_CHANNEL_2)
2302 if GPT_CHANNEL_1 is used as output, the GPT_CHANNEL_2 will be used as input and
2303 if GPT_CHANNEL_1 is used as input, the GPT_CHANNEL_2 will be used as output
2304 in all combinations, the GPT_CHANNEL_1 and GPT_CHANNEL_2 should be disabled together */
2305 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_DISABLE);
2306 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_DISABLE);
2307
2308 if (IS_GPT_ADVANCED_INSTANCE(htim->Instance) != RESET)
2309 {
2310 /* Disable the Main Output */
2311 __HAL_GPT_MOE_DISABLE(htim);
2312 }
2313
2314 /* Disable the Peripheral */
2315 __HAL_GPT_DISABLE(htim);
2316
2317 /* Return function status */
2318 return HAL_OK;
2319 }
2320 /**
2321 * @}
2322 */
2323
2324 /** @defgroup GPT_Exported_Functions_Group6 Time Encoder functions
2325 * @brief Time Encoder functions
2326 *
2327 @verbatim
2328 ==============================================================================
2329 ##### Time Encoder functions #####
2330 ==============================================================================
2331 [..]
2332 This section provides functions allowing to:
2333 (+) Initialize and configure the TIM Encoder.
2334 (+) De-initialize the TIM Encoder.
2335 (+) Start the Time Encoder.
2336 (+) Stop the Time Encoder.
2337 (+) Start the Time Encoder and enable interrupt.
2338 (+) Stop the Time Encoder and disable interrupt.
2339 (+) Start the Time Encoder and enable DMA transfer.
2340 (+) Stop the Time Encoder and disable DMA transfer.
2341
2342 @endverbatim
2343 * @{
2344 */
2345 /**
2346 * @brief Initializes the TIM Encoder Interface and create the associated handle.
2347 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2348 * the configuration information for TIM module.
2349 * @param sConfig TIM Encoder Interface configuration structure
2350 * @retval HAL status
2351 */
HAL_GPT_Encoder_Init(GPT_HandleTypeDef * htim,GPT_Encoder_InitTypeDef * sConfig)2352 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Encoder_Init(GPT_HandleTypeDef *htim, GPT_Encoder_InitTypeDef *sConfig)
2353 {
2354 uint32_t tmpsmcr = 0U;
2355 uint32_t tmpccmr1 = 0U;
2356 uint32_t tmpccer = 0U;
2357
2358 /* Check the TIM handle allocation */
2359 if (htim == NULL)
2360 {
2361 return HAL_ERROR;
2362 }
2363
2364 /* Check the parameters */
2365 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
2366 //TODO: wrong defintion of GPT_ENCODERMODE_TI1
2367 //HAL_ASSERT(IS_GPT_ENCODER_MODE(sConfig->EncoderMode));
2368 HAL_ASSERT(IS_GPT_IC_SELECTION(sConfig->IC1Selection));
2369 HAL_ASSERT(IS_GPT_IC_SELECTION(sConfig->IC2Selection));
2370 HAL_ASSERT(IS_GPT_IC_POLARITY(sConfig->IC1Polarity));
2371 HAL_ASSERT(IS_GPT_IC_POLARITY(sConfig->IC2Polarity));
2372 HAL_ASSERT(IS_GPT_IC_PRESCALER(sConfig->IC1Prescaler));
2373 HAL_ASSERT(IS_GPT_IC_PRESCALER(sConfig->IC2Prescaler));
2374 HAL_ASSERT(IS_GPT_IC_FILTER(sConfig->IC1Filter));
2375 HAL_ASSERT(IS_GPT_IC_FILTER(sConfig->IC2Filter));
2376
2377 if (htim->State == HAL_GPT_STATE_RESET)
2378 {
2379 /* Allocate lock resource and initialize it */
2380 htim->Lock = HAL_UNLOCKED;
2381 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2382 HAL_GPT_Encoder_MspInit(htim);
2383 }
2384
2385 /* Set the TIM state */
2386 htim->State = HAL_GPT_STATE_BUSY;
2387
2388 /* Reset the SMS bits */
2389 htim->Instance->SMCR &= ~GPT_SMCR_SMS;
2390
2391 /* Configure the Time base in the Encoder Mode */
2392 GPT_Base_SetConfig(htim->Instance, &htim->Init);
2393
2394 /* Get the TIMx SMCR register value */
2395 tmpsmcr = htim->Instance->SMCR;
2396
2397 /* Get the TIMx CCMR1 register value */
2398 tmpccmr1 = htim->Instance->CCMR1;
2399
2400 /* Get the TIMx CCER register value */
2401 tmpccer = htim->Instance->CCER;
2402
2403 /* Set the encoder Mode */
2404 tmpsmcr |= sConfig->EncoderMode;
2405
2406 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2407 tmpccmr1 &= ~(GPT_CCMR1_CC1S | GPT_CCMR1_CC2S);
2408 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
2409
2410 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2411 tmpccmr1 &= ~(GPT_CCMR1_IC1PSC | GPT_CCMR1_IC2PSC);
2412 tmpccmr1 &= ~(GPT_CCMR1_IC1F | GPT_CCMR1_IC2F);
2413 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
2414 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
2415
2416 /* Set the TI1 and the TI2 Polarities */
2417 tmpccer &= ~(GPT_CCER_CC1P | GPT_CCER_CC2P);
2418 tmpccer &= ~(GPT_CCER_CC1NP | GPT_CCER_CC2NP);
2419 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
2420
2421 /* Write to TIMx SMCR */
2422 htim->Instance->SMCR = tmpsmcr;
2423
2424 /* Write to TIMx CCMR1 */
2425 htim->Instance->CCMR1 = tmpccmr1;
2426
2427 /* Write to TIMx CCER */
2428 htim->Instance->CCER = tmpccer;
2429
2430 /* Initialize the TIM state*/
2431 htim->State = HAL_GPT_STATE_READY;
2432
2433 return HAL_OK;
2434 }
2435
2436 /**
2437 * @brief DeInitializes the TIM Encoder interface
2438 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2439 * the configuration information for TIM module.
2440 * @retval HAL status
2441 */
HAL_GPT_Encoder_DeInit(GPT_HandleTypeDef * htim)2442 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Encoder_DeInit(GPT_HandleTypeDef *htim)
2443 {
2444 /* Check the parameters */
2445 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
2446
2447 htim->State = HAL_GPT_STATE_BUSY;
2448
2449 /* Disable the TIM Peripheral Clock */
2450 __HAL_GPT_DISABLE(htim);
2451
2452 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2453 HAL_GPT_Encoder_MspDeInit(htim);
2454
2455 /* Change TIM state */
2456 htim->State = HAL_GPT_STATE_RESET;
2457
2458 /* Release Lock */
2459 __HAL_UNLOCK(htim);
2460
2461 return HAL_OK;
2462 }
2463
2464 /**
2465 * @brief Initializes the TIM Encoder Interface MSP.
2466 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2467 * the configuration information for TIM module.
2468 * @retval None
2469 */
HAL_GPT_Encoder_MspInit(GPT_HandleTypeDef * htim)2470 __weak void HAL_GPT_Encoder_MspInit(GPT_HandleTypeDef *htim)
2471 {
2472 /* Prevent unused argument(s) compilation warning */
2473 UNUSED(htim);
2474 /* NOTE : This function Should not be modified, when the callback is needed,
2475 the HAL_GPT_Encoder_MspInit could be implemented in the user file
2476 */
2477 }
2478
2479 /**
2480 * @brief DeInitializes TIM Encoder Interface MSP.
2481 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2482 * the configuration information for TIM module.
2483 * @retval None
2484 */
HAL_GPT_Encoder_MspDeInit(GPT_HandleTypeDef * htim)2485 __weak void HAL_GPT_Encoder_MspDeInit(GPT_HandleTypeDef *htim)
2486 {
2487 /* Prevent unused argument(s) compilation warning */
2488 UNUSED(htim);
2489 /* NOTE : This function Should not be modified, when the callback is needed,
2490 the HAL_GPT_Encoder_MspDeInit could be implemented in the user file
2491 */
2492 }
2493
2494 /**
2495 * @brief Starts the TIM Encoder Interface.
2496 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2497 * the configuration information for TIM module.
2498 * @param Channel TIM Channels to be enabled.
2499 * This parameter can be one of the following values:
2500 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
2501 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
2502 * @arg GPT_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2503 * @retval HAL status
2504 */
HAL_GPT_Encoder_Start(GPT_HandleTypeDef * htim,uint32_t Channel)2505 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Encoder_Start(GPT_HandleTypeDef *htim, uint32_t Channel)
2506 {
2507 /* Check the parameters */
2508 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
2509
2510 /* Enable the encoder interface channels */
2511 switch (Channel)
2512 {
2513 case GPT_CHANNEL_1:
2514 {
2515 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_ENABLE);
2516 break;
2517 }
2518 case GPT_CHANNEL_2:
2519 {
2520 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_ENABLE);
2521 break;
2522 }
2523 default :
2524 {
2525 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_ENABLE);
2526 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_ENABLE);
2527 break;
2528 }
2529 }
2530 /* Enable the Peripheral */
2531 __HAL_GPT_ENABLE(htim);
2532
2533 /* Return function status */
2534 return HAL_OK;
2535 }
2536
2537 /**
2538 * @brief Stops the TIM Encoder Interface.
2539 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2540 * the configuration information for TIM module.
2541 * @param Channel TIM Channels to be disabled.
2542 * This parameter can be one of the following values:
2543 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
2544 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
2545 * @arg GPT_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2546 * @retval HAL status
2547 */
HAL_GPT_Encoder_Stop(GPT_HandleTypeDef * htim,uint32_t Channel)2548 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Encoder_Stop(GPT_HandleTypeDef *htim, uint32_t Channel)
2549 {
2550 /* Check the parameters */
2551 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
2552
2553 /* Disable the Input Capture channels 1 and 2
2554 (in the EncoderInterface the two possible channels that can be used are GPT_CHANNEL_1 and GPT_CHANNEL_2) */
2555 switch (Channel)
2556 {
2557 case GPT_CHANNEL_1:
2558 {
2559 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_DISABLE);
2560 break;
2561 }
2562 case GPT_CHANNEL_2:
2563 {
2564 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_DISABLE);
2565 break;
2566 }
2567 default :
2568 {
2569 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_DISABLE);
2570 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_DISABLE);
2571 break;
2572 }
2573 }
2574 /* Disable the Peripheral */
2575 __HAL_GPT_DISABLE(htim);
2576
2577 /* Return function status */
2578 return HAL_OK;
2579 }
2580
2581 /**
2582 * @brief Starts the TIM Encoder Interface in interrupt mode.
2583 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2584 * the configuration information for TIM module.
2585 * @param Channel TIM Channels to be enabled.
2586 * This parameter can be one of the following values:
2587 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
2588 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
2589 * @arg GPT_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2590 * @retval HAL status
2591 */
HAL_GPT_Encoder_Start_IT(GPT_HandleTypeDef * htim,uint32_t Channel)2592 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Encoder_Start_IT(GPT_HandleTypeDef *htim, uint32_t Channel)
2593 {
2594 /* Check the parameters */
2595 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
2596
2597 /* Enable the encoder interface channels */
2598 /* Enable the capture compare Interrupts 1 and/or 2 */
2599 switch (Channel)
2600 {
2601 case GPT_CHANNEL_1:
2602 {
2603 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_ENABLE);
2604 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC1);
2605 break;
2606 }
2607 case GPT_CHANNEL_2:
2608 {
2609 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_ENABLE);
2610 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC2);
2611 break;
2612 }
2613 default :
2614 {
2615 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_ENABLE);
2616 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_ENABLE);
2617 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC1);
2618 __HAL_GPT_ENABLE_IT(htim, GPT_IT_CC2);
2619 break;
2620 }
2621 }
2622
2623 /* Enable the Peripheral */
2624 __HAL_GPT_ENABLE(htim);
2625
2626 /* Return function status */
2627 return HAL_OK;
2628 }
2629
2630 /**
2631 * @brief Stops the TIM Encoder Interface in interrupt mode.
2632 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2633 * the configuration information for TIM module.
2634 * @param Channel TIM Channels to be disabled.
2635 * This parameter can be one of the following values:
2636 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
2637 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
2638 * @arg GPT_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2639 * @retval HAL status
2640 */
HAL_GPT_Encoder_Stop_IT(GPT_HandleTypeDef * htim,uint32_t Channel)2641 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Encoder_Stop_IT(GPT_HandleTypeDef *htim, uint32_t Channel)
2642 {
2643 /* Check the parameters */
2644 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
2645
2646 /* Disable the Input Capture channels 1 and 2
2647 (in the EncoderInterface the two possible channels that can be used are GPT_CHANNEL_1 and GPT_CHANNEL_2) */
2648 if (Channel == GPT_CHANNEL_1)
2649 {
2650 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_DISABLE);
2651
2652 /* Disable the capture compare Interrupts 1 */
2653 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC1);
2654 }
2655 else if (Channel == GPT_CHANNEL_2)
2656 {
2657 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_DISABLE);
2658
2659 /* Disable the capture compare Interrupts 2 */
2660 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC2);
2661 }
2662 else
2663 {
2664 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_DISABLE);
2665 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_DISABLE);
2666
2667 /* Disable the capture compare Interrupts 1 and 2 */
2668 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC1);
2669 __HAL_GPT_DISABLE_IT(htim, GPT_IT_CC2);
2670 }
2671
2672 /* Disable the Peripheral */
2673 __HAL_GPT_DISABLE(htim);
2674
2675 /* Change the htim state */
2676 htim->State = HAL_GPT_STATE_READY;
2677
2678 /* Return function status */
2679 return HAL_OK;
2680 }
2681
2682 /**
2683 * @brief Starts the TIM Encoder Interface in DMA mode.
2684 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2685 * the configuration information for TIM module.
2686 * @param Channel TIM Channels to be enabled.
2687 * This parameter can be one of the following values:
2688 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
2689 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
2690 * @arg GPT_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2691 * @param pData1 The destination Buffer address for IC1.
2692 * @param pData2 The destination Buffer address for IC2.
2693 * @param Length The length of data to be transferred from TIM peripheral to memory.
2694 * @retval HAL status
2695 */
HAL_GPT_Encoder_Start_DMA(GPT_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)2696 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Encoder_Start_DMA(GPT_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
2697 {
2698 /* Check the parameters */
2699 HAL_ASSERT(IS_GPT_DMA_CC_INSTANCE(htim->Instance));
2700
2701 if (htim->State == HAL_GPT_STATE_BUSY)
2702 {
2703 return HAL_BUSY;
2704 }
2705 else if (htim->State == HAL_GPT_STATE_READY)
2706 {
2707 if ((((pData1 == 0U) || (pData2 == 0U))) && (Length > 0))
2708 {
2709 return HAL_ERROR;
2710 }
2711 else
2712 {
2713 htim->State = HAL_GPT_STATE_BUSY;
2714 }
2715 }
2716
2717 switch (Channel)
2718 {
2719 case GPT_CHANNEL_1:
2720 {
2721 /* Set the DMA Period elapsed callback */
2722 htim->hdma[GPT_DMA_ID_CC1]->XferCpltCallback = GPT_DMACaptureCplt;
2723
2724 /* Set the DMA error callback */
2725 htim->hdma[GPT_DMA_ID_CC1]->XferErrorCallback = GPT_DMAError ;
2726
2727 /* Enable the DMA Stream */
2728 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
2729
2730 /* Enable the TIM Input Capture DMA request */
2731 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC1);
2732
2733 /* Enable the Peripheral */
2734 __HAL_GPT_ENABLE(htim);
2735
2736 /* Enable the Capture compare channel */
2737 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_ENABLE);
2738 }
2739 break;
2740
2741 case GPT_CHANNEL_2:
2742 {
2743 /* Set the DMA Period elapsed callback */
2744 htim->hdma[GPT_DMA_ID_CC2]->XferCpltCallback = GPT_DMACaptureCplt;
2745
2746 /* Set the DMA error callback */
2747 htim->hdma[GPT_DMA_ID_CC2]->XferErrorCallback = GPT_DMAError;
2748 /* Enable the DMA Stream */
2749 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2750
2751 /* Enable the TIM Input Capture DMA request */
2752 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC2);
2753
2754 /* Enable the Peripheral */
2755 __HAL_GPT_ENABLE(htim);
2756
2757 /* Enable the Capture compare channel */
2758 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_ENABLE);
2759 }
2760 break;
2761
2762 case GPT_CHANNEL_ALL:
2763 {
2764 /* Set the DMA Period elapsed callback */
2765 htim->hdma[GPT_DMA_ID_CC1]->XferCpltCallback = GPT_DMACaptureCplt;
2766
2767 /* Set the DMA error callback */
2768 htim->hdma[GPT_DMA_ID_CC1]->XferErrorCallback = GPT_DMAError ;
2769
2770 /* Enable the DMA Stream */
2771 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
2772
2773 /* Set the DMA Period elapsed callback */
2774 htim->hdma[GPT_DMA_ID_CC2]->XferCpltCallback = GPT_DMACaptureCplt;
2775
2776 /* Set the DMA error callback */
2777 htim->hdma[GPT_DMA_ID_CC2]->XferErrorCallback = GPT_DMAError ;
2778
2779 /* Enable the DMA Stream */
2780 HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2781
2782 /* Enable the Peripheral */
2783 __HAL_GPT_ENABLE(htim);
2784
2785 /* Enable the Capture compare channel */
2786 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_ENABLE);
2787 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_ENABLE);
2788
2789 /* Enable the TIM Input Capture DMA request */
2790 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC1);
2791 /* Enable the TIM Input Capture DMA request */
2792 __HAL_GPT_ENABLE_DMA(htim, GPT_DMA_CC2);
2793 }
2794 break;
2795
2796 default:
2797 break;
2798 }
2799 /* Return function status */
2800 return HAL_OK;
2801 }
2802
2803 /**
2804 * @brief Stops the TIM Encoder Interface in DMA mode.
2805 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2806 * the configuration information for TIM module.
2807 * @param Channel TIM Channels to be enabled.
2808 * This parameter can be one of the following values:
2809 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
2810 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
2811 * @arg GPT_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2812 * @retval HAL status
2813 */
HAL_GPT_Encoder_Stop_DMA(GPT_HandleTypeDef * htim,uint32_t Channel)2814 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_Encoder_Stop_DMA(GPT_HandleTypeDef *htim, uint32_t Channel)
2815 {
2816 /* Check the parameters */
2817 HAL_ASSERT(IS_GPT_DMA_CC_INSTANCE(htim->Instance));
2818
2819 /* Disable the Input Capture channels 1 and 2
2820 (in the EncoderInterface the two possible channels that can be used are GPT_CHANNEL_1 and GPT_CHANNEL_2) */
2821 if (Channel == GPT_CHANNEL_1)
2822 {
2823 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_DISABLE);
2824
2825 /* Disable the capture compare DMA Request 1 */
2826 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC1);
2827 }
2828 else if (Channel == GPT_CHANNEL_2)
2829 {
2830 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_DISABLE);
2831
2832 /* Disable the capture compare DMA Request 2 */
2833 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC2);
2834 }
2835 else
2836 {
2837 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_1, GPT_CCx_DISABLE);
2838 GPT_CCxChannelCmd(htim->Instance, GPT_CHANNEL_2, GPT_CCx_DISABLE);
2839
2840 /* Disable the capture compare DMA Request 1 and 2 */
2841 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC1);
2842 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_CC2);
2843 }
2844
2845 /* Disable the Peripheral */
2846 __HAL_GPT_DISABLE(htim);
2847
2848 /* Change the htim state */
2849 htim->State = HAL_GPT_STATE_READY;
2850
2851 /* Return function status */
2852 return HAL_OK;
2853 }
2854 /**
2855 * @}
2856 */
2857
2858 /** @defgroup GPT_Exported_Functions_Group7 TIM IRQ handler management
2859 * @brief IRQ handler management
2860 *
2861 @verbatim
2862 ==============================================================================
2863 ##### IRQ handler management #####
2864 ==============================================================================
2865 [..]
2866 This section provides Timer IRQ handler function.
2867
2868 @endverbatim
2869 * @{
2870 */
2871 /**
2872 * @brief This function handles TIM interrupts requests.
2873 * @param htim pointer to a GPT_HandleTypeDef structure that contains
2874 * the configuration information for TIM module.
2875 * @retval None
2876 */
HAL_GPT_IRQHandler(GPT_HandleTypeDef * htim)2877 __HAL_ROM_USED void HAL_GPT_IRQHandler(GPT_HandleTypeDef *htim)
2878 {
2879 /* Capture compare 1 event */
2880 if (__HAL_GPT_GET_FLAG(htim, GPT_FLAG_CC1) != RESET)
2881 {
2882 if (__HAL_GPT_GET_IT_SOURCE(htim, GPT_IT_CC1) != RESET)
2883 {
2884 {
2885 __HAL_GPT_CLEAR_IT(htim, GPT_IT_CC1);
2886 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_1;
2887
2888 /* Input capture event */
2889 if ((htim->Instance->CCMR1 & GPT_CCMR1_CC1S) != 0x00U)
2890 {
2891 HAL_GPT_IC_CaptureCallback(htim);
2892 }
2893 /* Output compare event */
2894 else
2895 {
2896 HAL_GPT_OC_DelayElapsedCallback(htim);
2897 HAL_GPT_PWM_PulseFinishedCallback(htim);
2898 }
2899 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_CLEARED;
2900 }
2901 }
2902 }
2903 /* Capture compare 2 event */
2904 if (__HAL_GPT_GET_FLAG(htim, GPT_FLAG_CC2) != RESET)
2905 {
2906 if (__HAL_GPT_GET_IT_SOURCE(htim, GPT_IT_CC2) != RESET)
2907 {
2908 __HAL_GPT_CLEAR_IT(htim, GPT_IT_CC2);
2909 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_2;
2910 /* Input capture event */
2911 if ((htim->Instance->CCMR1 & GPT_CCMR1_CC2S) != 0x00U)
2912 {
2913 HAL_GPT_IC_CaptureCallback(htim);
2914 }
2915 /* Output compare event */
2916 else
2917 {
2918 HAL_GPT_OC_DelayElapsedCallback(htim);
2919 HAL_GPT_PWM_PulseFinishedCallback(htim);
2920 }
2921 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_CLEARED;
2922 }
2923 }
2924 /* Capture compare 3 event */
2925 if (__HAL_GPT_GET_FLAG(htim, GPT_FLAG_CC3) != RESET)
2926 {
2927 if (__HAL_GPT_GET_IT_SOURCE(htim, GPT_IT_CC3) != RESET)
2928 {
2929 __HAL_GPT_CLEAR_IT(htim, GPT_IT_CC3);
2930 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_3;
2931 /* Input capture event */
2932 if ((htim->Instance->CCMR2 & GPT_CCMR2_CC3S) != 0x00U)
2933 {
2934 HAL_GPT_IC_CaptureCallback(htim);
2935 }
2936 /* Output compare event */
2937 else
2938 {
2939 HAL_GPT_OC_DelayElapsedCallback(htim);
2940 HAL_GPT_PWM_PulseFinishedCallback(htim);
2941 }
2942 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_CLEARED;
2943 }
2944 }
2945 /* Capture compare 4 event */
2946 if (__HAL_GPT_GET_FLAG(htim, GPT_FLAG_CC4) != RESET)
2947 {
2948 if (__HAL_GPT_GET_IT_SOURCE(htim, GPT_IT_CC4) != RESET)
2949 {
2950 __HAL_GPT_CLEAR_IT(htim, GPT_IT_CC4);
2951 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_4;
2952 /* Input capture event */
2953 if ((htim->Instance->CCMR2 & GPT_CCMR2_CC4S) != 0x00U)
2954 {
2955 HAL_GPT_IC_CaptureCallback(htim);
2956 }
2957 /* Output compare event */
2958 else
2959 {
2960 HAL_GPT_OC_DelayElapsedCallback(htim);
2961 HAL_GPT_PWM_PulseFinishedCallback(htim);
2962 }
2963 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_CLEARED;
2964 }
2965 }
2966 /* TIM Update event */
2967 if (__HAL_GPT_GET_FLAG(htim, GPT_FLAG_UPDATE) != RESET)
2968 {
2969 if (__HAL_GPT_GET_IT_SOURCE(htim, GPT_IT_UPDATE) != RESET)
2970 {
2971 __HAL_GPT_CLEAR_IT(htim, GPT_IT_UPDATE);
2972 HAL_GPT_PeriodElapsedCallback(htim);
2973 }
2974 }
2975 /* TIM Break input event */
2976 if (__HAL_GPT_GET_FLAG(htim, GPT_FLAG_BREAK) != RESET)
2977 {
2978 if (__HAL_GPT_GET_IT_SOURCE(htim, GPT_IT_BREAK) != RESET)
2979 {
2980 __HAL_GPT_CLEAR_IT(htim, GPT_IT_BREAK);
2981 HAL_TIMEx_BreakCallback(htim);
2982 }
2983 }
2984 /* TIM Trigger detection event */
2985 if (__HAL_GPT_GET_FLAG(htim, GPT_FLAG_TRIGGER) != RESET)
2986 {
2987 if (__HAL_GPT_GET_IT_SOURCE(htim, GPT_IT_TRIGGER) != RESET)
2988 {
2989 __HAL_GPT_CLEAR_IT(htim, GPT_IT_TRIGGER);
2990 HAL_GPT_TriggerCallback(htim);
2991 }
2992 }
2993 /* TIM commutation event */
2994 if (__HAL_GPT_GET_FLAG(htim, GPT_FLAG_COM) != RESET)
2995 {
2996 if (__HAL_GPT_GET_IT_SOURCE(htim, GPT_IT_COM) != RESET)
2997 {
2998 __HAL_GPT_CLEAR_IT(htim, GPT_FLAG_COM);
2999 HAL_TIMEx_CommutationCallback(htim);
3000 }
3001 }
3002 }
3003 /**
3004 * @}
3005 */
3006
3007 /** @defgroup GPT_Exported_Functions_Group8 Peripheral Control functions
3008 * @brief Peripheral Control functions
3009 *
3010 @verbatim
3011 ==============================================================================
3012 ##### Peripheral Control functions #####
3013 ==============================================================================
3014 [..]
3015 This section provides functions allowing to:
3016 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
3017 (+) Configure External Clock source.
3018 (+) Configure Complementary channels, break features and dead time.
3019 (+) Configure Master and the Slave synchronization.
3020 (+) Configure the DMA Burst Mode.
3021
3022 @endverbatim
3023 * @{
3024 */
3025
3026 /**
3027 * @brief Initializes the TIM Output Compare Channels according to the specified
3028 * parameters in the GPT_OC_InitTypeDef.
3029 * @param htim pointer to a GPT_HandleTypeDef structure that contains
3030 * the configuration information for TIM module.
3031 * @param sConfig TIM Output Compare configuration structure
3032 * @param Channel TIM Channels to be enabled.
3033 * This parameter can be one of the following values:
3034 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
3035 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
3036 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
3037 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
3038 * @retval HAL status
3039 */
HAL_GPT_OC_ConfigChannel(GPT_HandleTypeDef * htim,GPT_OC_InitTypeDef * sConfig,uint32_t Channel)3040 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OC_ConfigChannel(GPT_HandleTypeDef *htim, GPT_OC_InitTypeDef *sConfig, uint32_t Channel)
3041 {
3042 /* Check the parameters */
3043 HAL_ASSERT(IS_GPT_CHANNELS(Channel));
3044 HAL_ASSERT(IS_GPT_OC_MODE(sConfig->OCMode));
3045 HAL_ASSERT(IS_GPT_OC_POLARITY(sConfig->OCPolarity));
3046
3047 /* Check input state */
3048 __HAL_LOCK(htim);
3049
3050 htim->State = HAL_GPT_STATE_BUSY;
3051
3052 switch (Channel)
3053 {
3054 case GPT_CHANNEL_1:
3055 {
3056 HAL_ASSERT(IS_GPT_CC1_INSTANCE(htim->Instance));
3057 /* Configure the TIM Channel 1 in Output Compare */
3058 GPT_OC1_SetConfig(htim->Instance, sConfig);
3059 }
3060 break;
3061
3062 case GPT_CHANNEL_2:
3063 {
3064 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
3065 /* Configure the TIM Channel 2 in Output Compare */
3066 GPT_OC2_SetConfig(htim->Instance, sConfig);
3067 }
3068 break;
3069
3070 case GPT_CHANNEL_3:
3071 {
3072 HAL_ASSERT(IS_GPT_CC3_INSTANCE(htim->Instance));
3073 /* Configure the TIM Channel 3 in Output Compare */
3074 GPT_OC3_SetConfig(htim->Instance, sConfig);
3075 }
3076 break;
3077
3078 case GPT_CHANNEL_4:
3079 {
3080 HAL_ASSERT(IS_GPT_CC4_INSTANCE(htim->Instance));
3081 /* Configure the TIM Channel 4 in Output Compare */
3082 GPT_OC4_SetConfig(htim->Instance, sConfig);
3083 }
3084 break;
3085
3086 default:
3087 break;
3088 }
3089 htim->State = HAL_GPT_STATE_READY;
3090
3091 __HAL_UNLOCK(htim);
3092
3093 return HAL_OK;
3094 }
3095
3096 /**
3097 * @brief Initializes the TIM Input Capture Channels according to the specified
3098 * parameters in the GPT_IC_InitTypeDef.
3099 * @param htim pointer to a GPT_HandleTypeDef structure that contains
3100 * the configuration information for TIM module.
3101 * @param sConfig TIM Input Capture configuration structure
3102 * @param Channel TIM Channels to be enabled.
3103 * This parameter can be one of the following values:
3104 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
3105 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
3106 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
3107 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
3108 * @retval HAL status
3109 */
HAL_GPT_IC_ConfigChannel(GPT_HandleTypeDef * htim,GPT_IC_InitTypeDef * sConfig,uint32_t Channel)3110 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_IC_ConfigChannel(GPT_HandleTypeDef *htim, GPT_IC_InitTypeDef *sConfig, uint32_t Channel)
3111 {
3112 /* Check the parameters */
3113 HAL_ASSERT(IS_GPT_CC1_INSTANCE(htim->Instance));
3114 HAL_ASSERT(IS_GPT_IC_POLARITY(sConfig->ICPolarity));
3115 HAL_ASSERT(IS_GPT_IC_SELECTION(sConfig->ICSelection));
3116 HAL_ASSERT(IS_GPT_IC_PRESCALER(sConfig->ICPrescaler));
3117 HAL_ASSERT(IS_GPT_IC_FILTER(sConfig->ICFilter));
3118
3119 __HAL_LOCK(htim);
3120
3121 htim->State = HAL_GPT_STATE_BUSY;
3122
3123 if (Channel == GPT_CHANNEL_1)
3124 {
3125 /* TI1 Configuration */
3126 GPT_TI1_SetConfig(htim->Instance,
3127 sConfig->ICPolarity,
3128 sConfig->ICSelection,
3129 sConfig->ICFilter);
3130
3131 /* Reset the IC1PSC Bits */
3132 htim->Instance->CCMR1 &= ~GPT_CCMR1_IC1PSC;
3133
3134 /* Set the IC1PSC value */
3135 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
3136 }
3137 else if (Channel == GPT_CHANNEL_2)
3138 {
3139 /* TI2 Configuration */
3140 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
3141
3142 GPT_TI2_SetConfig(htim->Instance,
3143 sConfig->ICPolarity,
3144 sConfig->ICSelection,
3145 sConfig->ICFilter);
3146
3147 /* Reset the IC2PSC Bits */
3148 htim->Instance->CCMR1 &= ~GPT_CCMR1_IC2PSC;
3149
3150 /* Set the IC2PSC value */
3151 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
3152 }
3153 else if (Channel == GPT_CHANNEL_3)
3154 {
3155 /* TI3 Configuration */
3156 HAL_ASSERT(IS_GPT_CC3_INSTANCE(htim->Instance));
3157
3158 GPT_TI3_SetConfig(htim->Instance,
3159 sConfig->ICPolarity,
3160 sConfig->ICSelection,
3161 sConfig->ICFilter);
3162
3163 /* Reset the IC3PSC Bits */
3164 htim->Instance->CCMR2 &= ~GPT_CCMR2_IC3PSC;
3165
3166 /* Set the IC3PSC value */
3167 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
3168 }
3169 else
3170 {
3171 /* TI4 Configuration */
3172 HAL_ASSERT(IS_GPT_CC4_INSTANCE(htim->Instance));
3173
3174 GPT_TI4_SetConfig(htim->Instance,
3175 sConfig->ICPolarity,
3176 sConfig->ICSelection,
3177 sConfig->ICFilter);
3178
3179 /* Reset the IC4PSC Bits */
3180 htim->Instance->CCMR2 &= ~GPT_CCMR2_IC4PSC;
3181
3182 /* Set the IC4PSC value */
3183 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
3184 }
3185
3186 htim->State = HAL_GPT_STATE_READY;
3187
3188 __HAL_UNLOCK(htim);
3189
3190 return HAL_OK;
3191 }
3192
3193 /**
3194 * @brief Initializes the TIM PWM channels according to the specified
3195 * parameters in the GPT_OC_InitTypeDef.
3196 * @param htim pointer to a GPT_HandleTypeDef structure that contains
3197 * the configuration information for TIM module.
3198 * @param sConfig TIM PWM configuration structure
3199 * @param Channel TIM Channels to be enabled.
3200 * This parameter can be one of the following values:
3201 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
3202 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
3203 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
3204 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
3205 * @retval HAL status
3206 */
HAL_GPT_PWM_ConfigChannel(GPT_HandleTypeDef * htim,GPT_OC_InitTypeDef * sConfig,uint32_t Channel)3207 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_PWM_ConfigChannel(GPT_HandleTypeDef *htim, GPT_OC_InitTypeDef *sConfig, uint32_t Channel)
3208 {
3209 __HAL_LOCK(htim);
3210
3211 /* Check the parameters */
3212 HAL_ASSERT(IS_GPT_CHANNELS(Channel));
3213 HAL_ASSERT(IS_GPT_PWM_MODE(sConfig->OCMode));
3214 HAL_ASSERT(IS_GPT_OC_POLARITY(sConfig->OCPolarity));
3215 //HAL_ASSERT(IS_GPT_FAST_STATE(sConfig->OCFastMode));
3216
3217 htim->State = HAL_GPT_STATE_BUSY;
3218
3219 switch (Channel)
3220 {
3221 case GPT_CHANNEL_1:
3222 {
3223 HAL_ASSERT(IS_GPT_CC1_INSTANCE(htim->Instance));
3224 /* Configure the Channel 1 in PWM mode */
3225 GPT_OC1_SetConfig(htim->Instance, sConfig);
3226
3227 /* Set the Preload enable bit for channel1 */
3228 htim->Instance->CCMR1 |= GPT_CCMR1_OC1PE;
3229 }
3230 break;
3231
3232 case GPT_CHANNEL_2:
3233 {
3234 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
3235 /* Configure the Channel 2 in PWM mode */
3236 GPT_OC2_SetConfig(htim->Instance, sConfig);
3237
3238 /* Set the Preload enable bit for channel2 */
3239 htim->Instance->CCMR1 |= GPT_CCMR1_OC2PE;
3240 }
3241 break;
3242
3243 case GPT_CHANNEL_3:
3244 {
3245 HAL_ASSERT(IS_GPT_CC3_INSTANCE(htim->Instance));
3246 /* Configure the Channel 3 in PWM mode */
3247 GPT_OC3_SetConfig(htim->Instance, sConfig);
3248
3249 /* Set the Preload enable bit for channel3 */
3250 htim->Instance->CCMR2 |= GPT_CCMR2_OC3PE;
3251
3252 }
3253 break;
3254
3255 case GPT_CHANNEL_4:
3256 {
3257 HAL_ASSERT(IS_GPT_CC4_INSTANCE(htim->Instance));
3258 /* Configure the Channel 4 in PWM mode */
3259 GPT_OC4_SetConfig(htim->Instance, sConfig);
3260
3261 /* Set the Preload enable bit for channel4 */
3262 htim->Instance->CCMR2 |= GPT_CCMR2_OC4PE;
3263 }
3264 break;
3265
3266 default:
3267 break;
3268 }
3269
3270 htim->State = HAL_GPT_STATE_READY;
3271
3272 __HAL_UNLOCK(htim);
3273
3274 return HAL_OK;
3275 }
3276
3277 /**
3278 * @brief Initializes the TIM One Pulse Channels according to the specified
3279 * parameters in the GPT_OnePulse_InitTypeDef.
3280 * @param htim pointer to a GPT_HandleTypeDef structure that contains
3281 * the configuration information for TIM module.
3282 * @param sConfig TIM One Pulse configuration structure
3283 * @param OutputChannel TIM Channels to be enabled.
3284 * This parameter can be one of the following values:
3285 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
3286 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
3287 * @param InputChannel TIM Channels to be enabled.
3288 * This parameter can be one of the following values:
3289 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
3290 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
3291 * @retval HAL status
3292 */
HAL_GPT_OnePulse_ConfigChannel(GPT_HandleTypeDef * htim,GPT_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)3293 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_OnePulse_ConfigChannel(GPT_HandleTypeDef *htim, GPT_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
3294 {
3295 GPT_OC_InitTypeDef temp1;
3296
3297 /* Check the parameters */
3298 HAL_ASSERT(IS_GPT_OPM_CHANNELS(OutputChannel));
3299 HAL_ASSERT(IS_GPT_OPM_CHANNELS(InputChannel));
3300
3301 if (OutputChannel != InputChannel)
3302 {
3303 __HAL_LOCK(htim);
3304
3305 htim->State = HAL_GPT_STATE_BUSY;
3306
3307 /* Extract the Output compare configuration from sConfig structure */
3308 temp1.OCMode = sConfig->OCMode;
3309 temp1.Pulse = sConfig->Pulse;
3310 temp1.OCPolarity = sConfig->OCPolarity;
3311 temp1.OCNPolarity = sConfig->OCNPolarity;
3312 temp1.OCIdleState = sConfig->OCIdleState;
3313 temp1.OCNIdleState = sConfig->OCNIdleState;
3314
3315 switch (OutputChannel)
3316 {
3317 case GPT_CHANNEL_1:
3318 {
3319 HAL_ASSERT(IS_GPT_CC1_INSTANCE(htim->Instance));
3320
3321 GPT_OC1_SetConfig(htim->Instance, &temp1);
3322 }
3323 break;
3324 case GPT_CHANNEL_2:
3325 {
3326 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
3327
3328 GPT_OC2_SetConfig(htim->Instance, &temp1);
3329 }
3330 break;
3331 default:
3332 break;
3333 }
3334 switch (InputChannel)
3335 {
3336 case GPT_CHANNEL_1:
3337 {
3338 HAL_ASSERT(IS_GPT_CC1_INSTANCE(htim->Instance));
3339
3340 GPT_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
3341 sConfig->ICSelection, sConfig->ICFilter);
3342
3343 /* Reset the IC1PSC Bits */
3344 htim->Instance->CCMR1 &= ~GPT_CCMR1_IC1PSC;
3345
3346 /* Select the Trigger source */
3347 htim->Instance->SMCR &= ~GPT_SMCR_TS;
3348 htim->Instance->SMCR |= GPT_TS_TI1FP1;
3349
3350 /* Select the Slave Mode */
3351 htim->Instance->SMCR &= ~GPT_SMCR_SMS;
3352 htim->Instance->SMCR |= GPT_SLAVEMODE_TRIGGER;
3353 }
3354 break;
3355 case GPT_CHANNEL_2:
3356 {
3357 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
3358
3359 GPT_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
3360 sConfig->ICSelection, sConfig->ICFilter);
3361
3362 /* Reset the IC2PSC Bits */
3363 htim->Instance->CCMR1 &= ~GPT_CCMR1_IC2PSC;
3364
3365 /* Select the Trigger source */
3366 htim->Instance->SMCR &= ~GPT_SMCR_TS;
3367 htim->Instance->SMCR |= GPT_TS_TI2FP2;
3368
3369 /* Select the Slave Mode */
3370 htim->Instance->SMCR &= ~GPT_SMCR_SMS;
3371 htim->Instance->SMCR |= GPT_SLAVEMODE_TRIGGER;
3372 }
3373 break;
3374
3375 default:
3376 break;
3377 }
3378
3379 htim->State = HAL_GPT_STATE_READY;
3380
3381 __HAL_UNLOCK(htim);
3382
3383 return HAL_OK;
3384 }
3385 else
3386 {
3387 return HAL_ERROR;
3388 }
3389 }
3390
3391 /**
3392 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3393 * @param htim pointer to a GPT_HandleTypeDef structure that contains
3394 * the configuration information for TIM module.
3395 * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write.
3396 * This parameters can be on of the following values:
3397 * @arg GPT_DMABASE_CR1
3398 * @arg GPT_DMABASE_CR2
3399 * @arg GPT_DMABASE_SMCR
3400 * @arg GPT_DMABASE_DIER
3401 * @arg GPT_DMABASE_SR
3402 * @arg GPT_DMABASE_EGR
3403 * @arg GPT_DMABASE_CCMR1
3404 * @arg GPT_DMABASE_CCMR2
3405 * @arg GPT_DMABASE_CCER
3406 * @arg GPT_DMABASE_CNT
3407 * @arg GPT_DMABASE_PSC
3408 * @arg GPT_DMABASE_ARR
3409 * @arg GPT_DMABASE_RCR
3410 * @arg GPT_DMABASE_CCR1
3411 * @arg GPT_DMABASE_CCR2
3412 * @arg GPT_DMABASE_CCR3
3413 * @arg GPT_DMABASE_CCR4
3414 * @arg GPT_DMABASE_BDTR
3415 * @arg GPT_DMABASE_DCR
3416 * @param BurstRequestSrc TIM DMA Request sources.
3417 * This parameters can be on of the following values:
3418 * @arg GPT_DMA_UPDATE: TIM update Interrupt source
3419 * @arg GPT_DMA_CC1: TIM Capture Compare 1 DMA source
3420 * @arg GPT_DMA_CC2: TIM Capture Compare 2 DMA source
3421 * @arg GPT_DMA_CC3: TIM Capture Compare 3 DMA source
3422 * @arg GPT_DMA_CC4: TIM Capture Compare 4 DMA source
3423 * @arg GPT_DMA_COM: TIM Commutation DMA source
3424 * @arg GPT_DMA_TRIGGER: TIM Trigger DMA source
3425 * @param BurstBuffer The Buffer address.
3426 * @param BurstLength DMA Burst length. This parameter can be one value
3427 * between GPT_DMABURSTLENGTH_1TRANSFER and GPT_DMABURSTLENGTH_18TRANSFERS.
3428 * @retval HAL status
3429 */
HAL_GPT_DMABurst_WriteStart(GPT_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)3430 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_DMABurst_WriteStart(GPT_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3431 uint32_t *BurstBuffer, uint32_t BurstLength)
3432 {
3433 /* Check the parameters */
3434 HAL_ASSERT(IS_GPT_DMABURST_INSTANCE(htim->Instance));
3435 HAL_ASSERT(IS_GPT_DMA_BASE(BurstBaseAddress));
3436 HAL_ASSERT(IS_GPT_DMA_SOURCE(BurstRequestSrc));
3437 HAL_ASSERT(IS_GPT_DMA_LENGTH(BurstLength));
3438
3439 /* TODO: not support */
3440 return HAL_ERROR;
3441
3442 if (htim->State == HAL_GPT_STATE_BUSY)
3443 {
3444 return HAL_BUSY;
3445 }
3446 else if (htim->State == HAL_GPT_STATE_READY)
3447 {
3448 if ((BurstBuffer == 0U) && (BurstLength > 0U))
3449 {
3450 return HAL_ERROR;
3451 }
3452 else
3453 {
3454 htim->State = HAL_GPT_STATE_BUSY;
3455 }
3456 }
3457 switch (BurstRequestSrc)
3458 {
3459 case GPT_DMA_UPDATE:
3460 {
3461 /* Set the DMA Period elapsed callback */
3462 htim->hdma[GPT_DMA_ID_UPDATE]->XferCpltCallback = GPT_DMAPeriodElapsedCplt;
3463
3464 /* Set the DMA error callback */
3465 htim->hdma[GPT_DMA_ID_UPDATE]->XferErrorCallback = GPT_DMAError ;
3466
3467 /* Enable the DMA Stream */
3468 // HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
3469 }
3470 break;
3471 case GPT_DMA_CC1:
3472 {
3473 /* Set the DMA Period elapsed callback */
3474 htim->hdma[GPT_DMA_ID_CC1]->XferCpltCallback = GPT_DMADelayPulseCplt;
3475
3476 /* Set the DMA error callback */
3477 htim->hdma[GPT_DMA_ID_CC1]->XferErrorCallback = GPT_DMAError ;
3478
3479 /* Enable the DMA Stream */
3480 // HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
3481 }
3482 break;
3483 case GPT_DMA_CC2:
3484 {
3485 /* Set the DMA Period elapsed callback */
3486 htim->hdma[GPT_DMA_ID_CC2]->XferCpltCallback = GPT_DMADelayPulseCplt;
3487
3488 /* Set the DMA error callback */
3489 htim->hdma[GPT_DMA_ID_CC2]->XferErrorCallback = GPT_DMAError ;
3490
3491 /* Enable the DMA Stream */
3492 // HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
3493 }
3494 break;
3495 case GPT_DMA_CC3:
3496 {
3497 /* Set the DMA Period elapsed callback */
3498 htim->hdma[GPT_DMA_ID_CC3]->XferCpltCallback = GPT_DMADelayPulseCplt;
3499
3500 /* Set the DMA error callback */
3501 htim->hdma[GPT_DMA_ID_CC3]->XferErrorCallback = GPT_DMAError ;
3502
3503 /* Enable the DMA Stream */
3504 // HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
3505 }
3506 break;
3507 case GPT_DMA_CC4:
3508 {
3509 /* Set the DMA Period elapsed callback */
3510 htim->hdma[GPT_DMA_ID_CC4]->XferCpltCallback = GPT_DMADelayPulseCplt;
3511
3512 /* Set the DMA error callback */
3513 htim->hdma[GPT_DMA_ID_CC4]->XferErrorCallback = GPT_DMAError ;
3514
3515 /* Enable the DMA Stream */
3516 // HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
3517 }
3518 break;
3519 case GPT_DMA_COM:
3520 {
3521 /* Set the DMA Period elapsed callback */
3522 htim->hdma[GPT_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
3523
3524 /* Set the DMA error callback */
3525 htim->hdma[GPT_DMA_ID_COMMUTATION]->XferErrorCallback = GPT_DMAError ;
3526
3527 /* Enable the DMA Stream */
3528 // HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
3529 }
3530 break;
3531 case GPT_DMA_TRIGGER:
3532 {
3533 /* Set the DMA Period elapsed callback */
3534 htim->hdma[GPT_DMA_ID_TRIGGER]->XferCpltCallback = GPT_DMATriggerCplt;
3535
3536 /* Set the DMA error callback */
3537 htim->hdma[GPT_DMA_ID_TRIGGER]->XferErrorCallback = GPT_DMAError ;
3538
3539 /* Enable the DMA Stream */
3540 // HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
3541 }
3542 break;
3543 default:
3544 break;
3545 }
3546 /* configure the DMA Burst Mode */
3547 // htim->Instance->DCR = BurstBaseAddress | BurstLength;
3548
3549 /* Enable the TIM DMA Request */
3550 __HAL_GPT_ENABLE_DMA(htim, BurstRequestSrc);
3551
3552 htim->State = HAL_GPT_STATE_READY;
3553
3554 /* Return function status */
3555 return HAL_OK;
3556 }
3557
3558 /**
3559 * @brief Stops the TIM DMA Burst mode
3560 * @param htim pointer to a GPT_HandleTypeDef structure that contains
3561 * the configuration information for TIM module.
3562 * @param BurstRequestSrc TIM DMA Request sources to disable
3563 * @retval HAL status
3564 */
HAL_GPT_DMABurst_WriteStop(GPT_HandleTypeDef * htim,uint32_t BurstRequestSrc)3565 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_DMABurst_WriteStop(GPT_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3566 {
3567 /* Check the parameters */
3568 HAL_ASSERT(IS_GPT_DMA_SOURCE(BurstRequestSrc));
3569
3570 /* Abort the DMA transfer (at least disable the DMA channel) */
3571 switch (BurstRequestSrc)
3572 {
3573 case GPT_DMA_UPDATE:
3574 {
3575 HAL_DMA_Abort(htim->hdma[GPT_DMA_ID_UPDATE]);
3576 }
3577 break;
3578 case GPT_DMA_CC1:
3579 {
3580 HAL_DMA_Abort(htim->hdma[GPT_DMA_ID_CC1]);
3581 }
3582 break;
3583 case GPT_DMA_CC2:
3584 {
3585 HAL_DMA_Abort(htim->hdma[GPT_DMA_ID_CC2]);
3586 }
3587 break;
3588 case GPT_DMA_CC3:
3589 {
3590 HAL_DMA_Abort(htim->hdma[GPT_DMA_ID_CC3]);
3591 }
3592 break;
3593 case GPT_DMA_CC4:
3594 {
3595 HAL_DMA_Abort(htim->hdma[GPT_DMA_ID_CC4]);
3596 }
3597 break;
3598 case GPT_DMA_COM:
3599 {
3600 HAL_DMA_Abort(htim->hdma[GPT_DMA_ID_COMMUTATION]);
3601 }
3602 break;
3603 case GPT_DMA_TRIGGER:
3604 {
3605 HAL_DMA_Abort(htim->hdma[GPT_DMA_ID_TRIGGER]);
3606 }
3607 break;
3608 default:
3609 break;
3610 }
3611
3612 /* Disable the TIM Update DMA request */
3613 __HAL_GPT_DISABLE_DMA(htim, BurstRequestSrc);
3614
3615 /* Return function status */
3616 return HAL_OK;
3617 }
3618
3619 /**
3620 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
3621 * @param htim pointer to a GPT_HandleTypeDef structure that contains
3622 * the configuration information for TIM module.
3623 * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read.
3624 * This parameters can be on of the following values:
3625 * @arg GPT_DMABASE_CR1
3626 * @arg GPT_DMABASE_CR2
3627 * @arg GPT_DMABASE_SMCR
3628 * @arg GPT_DMABASE_DIER
3629 * @arg GPT_DMABASE_SR
3630 * @arg GPT_DMABASE_EGR
3631 * @arg GPT_DMABASE_CCMR1
3632 * @arg GPT_DMABASE_CCMR2
3633 * @arg GPT_DMABASE_CCER
3634 * @arg GPT_DMABASE_CNT
3635 * @arg GPT_DMABASE_PSC
3636 * @arg GPT_DMABASE_ARR
3637 * @arg GPT_DMABASE_RCR
3638 * @arg GPT_DMABASE_CCR1
3639 * @arg GPT_DMABASE_CCR2
3640 * @arg GPT_DMABASE_CCR3
3641 * @arg GPT_DMABASE_CCR4
3642 * @arg GPT_DMABASE_BDTR
3643 * @arg GPT_DMABASE_DCR
3644 * @param BurstRequestSrc TIM DMA Request sources.
3645 * This parameters can be on of the following values:
3646 * @arg GPT_DMA_UPDATE: TIM update Interrupt source
3647 * @arg GPT_DMA_CC1: TIM Capture Compare 1 DMA source
3648 * @arg GPT_DMA_CC2: TIM Capture Compare 2 DMA source
3649 * @arg GPT_DMA_CC3: TIM Capture Compare 3 DMA source
3650 * @arg GPT_DMA_CC4: TIM Capture Compare 4 DMA source
3651 * @arg GPT_DMA_COM: TIM Commutation DMA source
3652 * @arg GPT_DMA_TRIGGER: TIM Trigger DMA source
3653 * @param BurstBuffer The Buffer address.
3654 * @param BurstLength DMA Burst length. This parameter can be one value
3655 * between GPT_DMABURSTLENGTH_1TRANSFER and GPT_DMABURSTLENGTH_18TRANSFERS.
3656 * @retval HAL status
3657 */
HAL_GPT_DMABurst_ReadStart(GPT_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)3658 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_DMABurst_ReadStart(GPT_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3659 uint32_t *BurstBuffer, uint32_t BurstLength)
3660 {
3661 /* Check the parameters */
3662 HAL_ASSERT(IS_GPT_DMABURST_INSTANCE(htim->Instance));
3663 HAL_ASSERT(IS_GPT_DMA_BASE(BurstBaseAddress));
3664 HAL_ASSERT(IS_GPT_DMA_SOURCE(BurstRequestSrc));
3665 HAL_ASSERT(IS_GPT_DMA_LENGTH(BurstLength));
3666
3667 /* TODO: not support */
3668 return HAL_ERROR;
3669
3670 if (htim->State == HAL_GPT_STATE_BUSY)
3671 {
3672 return HAL_BUSY;
3673 }
3674 else if (htim->State == HAL_GPT_STATE_READY)
3675 {
3676 if ((BurstBuffer == 0U) && (BurstLength > 0U))
3677 {
3678 return HAL_ERROR;
3679 }
3680 else
3681 {
3682 htim->State = HAL_GPT_STATE_BUSY;
3683 }
3684 }
3685 switch (BurstRequestSrc)
3686 {
3687 case GPT_DMA_UPDATE:
3688 {
3689 /* Set the DMA Period elapsed callback */
3690 htim->hdma[GPT_DMA_ID_UPDATE]->XferCpltCallback = GPT_DMAPeriodElapsedCplt;
3691
3692 /* Set the DMA error callback */
3693 htim->hdma[GPT_DMA_ID_UPDATE]->XferErrorCallback = GPT_DMAError ;
3694
3695 /* Enable the DMA Stream */
3696 // HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
3697 }
3698 break;
3699 case GPT_DMA_CC1:
3700 {
3701 /* Set the DMA Period elapsed callback */
3702 htim->hdma[GPT_DMA_ID_CC1]->XferCpltCallback = GPT_DMACaptureCplt;
3703
3704 /* Set the DMA error callback */
3705 htim->hdma[GPT_DMA_ID_CC1]->XferErrorCallback = GPT_DMAError ;
3706
3707 /* Enable the DMA Stream */
3708 // HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
3709 }
3710 break;
3711 case GPT_DMA_CC2:
3712 {
3713 /* Set the DMA Period elapsed callback */
3714 htim->hdma[GPT_DMA_ID_CC2]->XferCpltCallback = GPT_DMACaptureCplt;
3715
3716 /* Set the DMA error callback */
3717 htim->hdma[GPT_DMA_ID_CC2]->XferErrorCallback = GPT_DMAError ;
3718
3719 /* Enable the DMA Stream */
3720 // HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
3721 }
3722 break;
3723 case GPT_DMA_CC3:
3724 {
3725 /* Set the DMA Period elapsed callback */
3726 htim->hdma[GPT_DMA_ID_CC3]->XferCpltCallback = GPT_DMACaptureCplt;
3727
3728 /* Set the DMA error callback */
3729 htim->hdma[GPT_DMA_ID_CC3]->XferErrorCallback = GPT_DMAError ;
3730
3731 /* Enable the DMA Stream */
3732 // HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
3733 }
3734 break;
3735 case GPT_DMA_CC4:
3736 {
3737 /* Set the DMA Period elapsed callback */
3738 htim->hdma[GPT_DMA_ID_CC4]->XferCpltCallback = GPT_DMACaptureCplt;
3739
3740 /* Set the DMA error callback */
3741 htim->hdma[GPT_DMA_ID_CC4]->XferErrorCallback = GPT_DMAError ;
3742
3743 /* Enable the DMA Stream */
3744 // HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
3745 }
3746 break;
3747 case GPT_DMA_COM:
3748 {
3749 /* Set the DMA Period elapsed callback */
3750 htim->hdma[GPT_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
3751
3752 /* Set the DMA error callback */
3753 htim->hdma[GPT_DMA_ID_COMMUTATION]->XferErrorCallback = GPT_DMAError ;
3754
3755 /* Enable the DMA Stream */
3756 // HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
3757 }
3758 break;
3759 case GPT_DMA_TRIGGER:
3760 {
3761 /* Set the DMA Period elapsed callback */
3762 htim->hdma[GPT_DMA_ID_TRIGGER]->XferCpltCallback = GPT_DMATriggerCplt;
3763
3764 /* Set the DMA error callback */
3765 htim->hdma[GPT_DMA_ID_TRIGGER]->XferErrorCallback = GPT_DMAError ;
3766
3767 /* Enable the DMA Stream */
3768 // HAL_DMA_Start_IT(htim->hdma[GPT_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
3769 }
3770 break;
3771 default:
3772 break;
3773 }
3774
3775 /* configure the DMA Burst Mode */
3776 // htim->Instance->DCR = BurstBaseAddress | BurstLength;
3777
3778 /* Enable the TIM DMA Request */
3779 __HAL_GPT_ENABLE_DMA(htim, BurstRequestSrc);
3780
3781 htim->State = HAL_GPT_STATE_READY;
3782
3783 /* Return function status */
3784 return HAL_OK;
3785 }
3786
3787 /**
3788 * @brief Stop the DMA burst reading
3789 * @param htim pointer to a GPT_HandleTypeDef structure that contains
3790 * the configuration information for TIM module.
3791 * @param BurstRequestSrc TIM DMA Request sources to disable.
3792 * @retval HAL status
3793 */
HAL_GPT_DMABurst_ReadStop(GPT_HandleTypeDef * htim,uint32_t BurstRequestSrc)3794 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_DMABurst_ReadStop(GPT_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3795 {
3796 /* Check the parameters */
3797 HAL_ASSERT(IS_GPT_DMA_SOURCE(BurstRequestSrc));
3798
3799 /* Abort the DMA transfer (at least disable the DMA channel) */
3800 switch (BurstRequestSrc)
3801 {
3802 case GPT_DMA_UPDATE:
3803 {
3804 HAL_DMA_Abort(htim->hdma[GPT_DMA_ID_UPDATE]);
3805 }
3806 break;
3807 case GPT_DMA_CC1:
3808 {
3809 HAL_DMA_Abort(htim->hdma[GPT_DMA_ID_CC1]);
3810 }
3811 break;
3812 case GPT_DMA_CC2:
3813 {
3814 HAL_DMA_Abort(htim->hdma[GPT_DMA_ID_CC2]);
3815 }
3816 break;
3817 case GPT_DMA_CC3:
3818 {
3819 HAL_DMA_Abort(htim->hdma[GPT_DMA_ID_CC3]);
3820 }
3821 break;
3822 case GPT_DMA_CC4:
3823 {
3824 HAL_DMA_Abort(htim->hdma[GPT_DMA_ID_CC4]);
3825 }
3826 break;
3827 case GPT_DMA_COM:
3828 {
3829 HAL_DMA_Abort(htim->hdma[GPT_DMA_ID_COMMUTATION]);
3830 }
3831 break;
3832 case GPT_DMA_TRIGGER:
3833 {
3834 HAL_DMA_Abort(htim->hdma[GPT_DMA_ID_TRIGGER]);
3835 }
3836 break;
3837 default:
3838 break;
3839 }
3840
3841 /* Disable the TIM Update DMA request */
3842 __HAL_GPT_DISABLE_DMA(htim, BurstRequestSrc);
3843
3844 /* Return function status */
3845 return HAL_OK;
3846 }
3847
3848 /**
3849 * @brief Generate a software event
3850 * @param htim pointer to a GPT_HandleTypeDef structure that contains
3851 * the configuration information for TIM module.
3852 * @param EventSource specifies the event source.
3853 * This parameter can be one of the following values:
3854 * @arg GPT_EVENTSOURCE_UPDATE: Timer update Event source
3855 * @arg GPT_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
3856 * @arg GPT_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
3857 * @arg GPT_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
3858 * @arg GPT_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
3859 * @arg GPT_EVENTSOURCE_COM: Timer COM event source
3860 * @arg GPT_EVENTSOURCE_TRIGGER: Timer Trigger Event source
3861 * @arg GPT_EVENTSOURCE_BREAK: Timer Break event source
3862 * @note TIM6 and TIM7 can only generate an update event.
3863 * @note GPT_EVENTSOURCE_COM and GPT_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
3864 * @retval HAL status
3865 */
3866
HAL_GPT_GenerateEvent(GPT_HandleTypeDef * htim,uint32_t EventSource)3867 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_GenerateEvent(GPT_HandleTypeDef *htim, uint32_t EventSource)
3868 {
3869 /* Check the parameters */
3870 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
3871 HAL_ASSERT(IS_GPT_EVENT_SOURCE(EventSource));
3872
3873 /* Process Locked */
3874 __HAL_LOCK(htim);
3875
3876 /* Change the TIM state */
3877 htim->State = HAL_GPT_STATE_BUSY;
3878
3879 /* Set the event sources */
3880 htim->Instance->EGR = EventSource;
3881
3882 /* Change the TIM state */
3883 htim->State = HAL_GPT_STATE_READY;
3884
3885 __HAL_UNLOCK(htim);
3886
3887 /* Return function status */
3888 return HAL_OK;
3889 }
3890
3891 /**
3892 * @brief Configures the OCRef clear feature
3893 * @param htim pointer to a GPT_HandleTypeDef structure that contains
3894 * the configuration information for TIM module.
3895 * @param sClearInputConfig pointer to a GPT_ClearInputConfigTypeDef structure that
3896 * contains the OCREF clear feature and parameters for the TIM peripheral.
3897 * @param Channel specifies the TIM Channel.
3898 * This parameter can be one of the following values:
3899 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
3900 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
3901 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
3902 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
3903 * @retval HAL status
3904 */
HAL_GPT_ConfigOCrefClear(GPT_HandleTypeDef * htim,GPT_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)3905 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_ConfigOCrefClear(GPT_HandleTypeDef *htim, GPT_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
3906 {
3907 /* Check the parameters */
3908 HAL_ASSERT(IS_GPT_CC1_INSTANCE(htim->Instance));
3909 HAL_ASSERT(IS_GPT_CHANNELS(Channel));
3910 HAL_ASSERT(IS_GPT_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
3911 HAL_ASSERT(IS_GPT_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
3912 HAL_ASSERT(IS_GPT_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
3913 HAL_ASSERT(IS_GPT_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
3914
3915 /* Process Locked */
3916 __HAL_LOCK(htim);
3917
3918 htim->State = HAL_GPT_STATE_BUSY;
3919
3920 if (sClearInputConfig->ClearInputSource == GPT_CLEARINPUTSOURCE_ETR)
3921 {
3922 GPT_ETR_SetConfig(htim->Instance,
3923 sClearInputConfig->ClearInputPrescaler,
3924 sClearInputConfig->ClearInputPolarity,
3925 sClearInputConfig->ClearInputFilter);
3926 }
3927
3928 switch (Channel)
3929 {
3930 case GPT_CHANNEL_1:
3931 {
3932 if (sClearInputConfig->ClearInputState != RESET)
3933 {
3934 /* Enable the Ocref clear feature for Channel 1 */
3935 htim->Instance->CCMR1 |= GPT_CCMR1_OC1CE;
3936 }
3937 else
3938 {
3939 /* Disable the Ocref clear feature for Channel 1 */
3940 htim->Instance->CCMR1 &= ~GPT_CCMR1_OC1CE;
3941 }
3942 }
3943 break;
3944 case GPT_CHANNEL_2:
3945 {
3946 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
3947 if (sClearInputConfig->ClearInputState != RESET)
3948 {
3949 /* Enable the Ocref clear feature for Channel 2 */
3950 htim->Instance->CCMR1 |= GPT_CCMR1_OC2CE;
3951 }
3952 else
3953 {
3954 /* Disable the Ocref clear feature for Channel 2 */
3955 htim->Instance->CCMR1 &= ~GPT_CCMR1_OC2CE;
3956 }
3957 }
3958 break;
3959 case GPT_CHANNEL_3:
3960 {
3961 HAL_ASSERT(IS_GPT_CC3_INSTANCE(htim->Instance));
3962 if (sClearInputConfig->ClearInputState != RESET)
3963 {
3964 /* Enable the Ocref clear feature for Channel 3 */
3965 htim->Instance->CCMR2 |= GPT_CCMR2_OC3CE;
3966 }
3967 else
3968 {
3969 /* Disable the Ocref clear feature for Channel 3 */
3970 htim->Instance->CCMR2 &= ~GPT_CCMR2_OC3CE;
3971 }
3972 }
3973 break;
3974 case GPT_CHANNEL_4:
3975 {
3976 HAL_ASSERT(IS_GPT_CC4_INSTANCE(htim->Instance));
3977 if (sClearInputConfig->ClearInputState != RESET)
3978 {
3979 /* Enable the Ocref clear feature for Channel 4 */
3980 htim->Instance->CCMR2 |= GPT_CCMR2_OC4CE;
3981 }
3982 else
3983 {
3984 /* Disable the Ocref clear feature for Channel 4 */
3985 htim->Instance->CCMR2 &= ~GPT_CCMR2_OC4CE;
3986 }
3987 }
3988 break;
3989 default:
3990 break;
3991 }
3992
3993 htim->State = HAL_GPT_STATE_READY;
3994
3995 __HAL_UNLOCK(htim);
3996
3997 return HAL_OK;
3998 }
3999
4000 /**
4001 * @brief Configures the clock source to be used
4002 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4003 * the configuration information for TIM module.
4004 * @param sClockSourceConfig pointer to a GPT_ClockConfigTypeDef structure that
4005 * contains the clock source information for the TIM peripheral.
4006 * @retval HAL status
4007 */
HAL_GPT_ConfigClockSource(GPT_HandleTypeDef * htim,GPT_ClockConfigTypeDef * sClockSourceConfig)4008 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_ConfigClockSource(GPT_HandleTypeDef *htim, GPT_ClockConfigTypeDef *sClockSourceConfig)
4009 {
4010 uint32_t tmpsmcr = 0U;
4011
4012 /* Process Locked */
4013 __HAL_LOCK(htim);
4014
4015 htim->State = HAL_GPT_STATE_BUSY;
4016
4017 /* Check the parameters */
4018 HAL_ASSERT(IS_GPT_CLOCKSOURCE(sClockSourceConfig->ClockSource));
4019
4020 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
4021 tmpsmcr = htim->Instance->SMCR;
4022 tmpsmcr &= ~(GPT_SMCR_SMS | GPT_SMCR_TS);
4023 tmpsmcr &= ~(GPT_SMCR_ETF | GPT_SMCR_ETPS | GPT_SMCR_ECE | GPT_SMCR_ETP);
4024 htim->Instance->SMCR = tmpsmcr;
4025
4026 switch (sClockSourceConfig->ClockSource)
4027 {
4028 case GPT_CLOCKSOURCE_INTERNAL:
4029 {
4030 HAL_ASSERT(IS_GPT_INSTANCE(htim->Instance));
4031
4032 /* Disable slave mode to clock the prescaler directly with the internal clock */
4033 htim->Instance->SMCR &= ~GPT_SMCR_SMS;
4034 }
4035 break;
4036
4037 case GPT_CLOCKSOURCE_ETRMODE1:
4038 {
4039 HAL_ASSERT(IS_GPT_ETR_INSTANCE(htim->Instance));
4040
4041 HAL_ASSERT(IS_GPT_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4042 HAL_ASSERT(IS_GPT_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
4043 HAL_ASSERT(IS_GPT_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4044
4045 /* Configure the ETR Clock source */
4046 GPT_ETR_SetConfig(htim->Instance,
4047 sClockSourceConfig->ClockPrescaler,
4048 sClockSourceConfig->ClockPolarity,
4049 sClockSourceConfig->ClockFilter);
4050 /* Get the TIMx SMCR register value */
4051 tmpsmcr = htim->Instance->SMCR;
4052 /* Reset the SMS and TS Bits */
4053 tmpsmcr &= ~(GPT_SMCR_SMS | GPT_SMCR_TS);
4054 /* Select the External clock mode1 and the ETRF trigger */
4055 tmpsmcr |= (GPT_SLAVEMODE_EXTERNAL1 | GPT_CLOCKSOURCE_ETRMODE1);
4056 /* Write to TIMx SMCR */
4057 htim->Instance->SMCR = tmpsmcr;
4058 }
4059 break;
4060
4061 case GPT_CLOCKSOURCE_ETRMODE2:
4062 {
4063 HAL_ASSERT(IS_GPT_ETR_INSTANCE(htim->Instance));
4064
4065 HAL_ASSERT(IS_GPT_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4066 HAL_ASSERT(IS_GPT_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
4067 HAL_ASSERT(IS_GPT_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4068
4069 /* Configure the ETR Clock source */
4070 GPT_ETR_SetConfig(htim->Instance,
4071 sClockSourceConfig->ClockPrescaler,
4072 sClockSourceConfig->ClockPolarity,
4073 sClockSourceConfig->ClockFilter);
4074 /* Enable the External clock mode2 */
4075 htim->Instance->SMCR |= GPT_SMCR_ECE;
4076 }
4077 break;
4078
4079 case GPT_CLOCKSOURCE_TI1:
4080 {
4081 HAL_ASSERT(IS_GPT_CC1_INSTANCE(htim->Instance));
4082
4083 /* Check TI1 input conditioning related parameters */
4084 HAL_ASSERT(IS_GPT_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4085 HAL_ASSERT(IS_GPT_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4086
4087 GPT_TI1_ConfigInputStage(htim->Instance,
4088 sClockSourceConfig->ClockPolarity,
4089 sClockSourceConfig->ClockFilter);
4090 GPT_ITRx_SetConfig(htim->Instance, GPT_CLOCKSOURCE_TI1);
4091 }
4092 break;
4093 case GPT_CLOCKSOURCE_TI2:
4094 {
4095 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
4096
4097 /* Check TI1 input conditioning related parameters */
4098 HAL_ASSERT(IS_GPT_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4099 HAL_ASSERT(IS_GPT_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4100
4101 GPT_TI2_ConfigInputStage(htim->Instance,
4102 sClockSourceConfig->ClockPolarity,
4103 sClockSourceConfig->ClockFilter);
4104 GPT_ITRx_SetConfig(htim->Instance, GPT_CLOCKSOURCE_TI2);
4105 }
4106 break;
4107 case GPT_CLOCKSOURCE_TI1ED:
4108 {
4109 HAL_ASSERT(IS_GPT_CC1_INSTANCE(htim->Instance));
4110
4111 /* Check TI1 input conditioning related parameters */
4112 HAL_ASSERT(IS_GPT_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4113 HAL_ASSERT(IS_GPT_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4114
4115 GPT_TI1_ConfigInputStage(htim->Instance,
4116 sClockSourceConfig->ClockPolarity,
4117 sClockSourceConfig->ClockFilter);
4118 GPT_ITRx_SetConfig(htim->Instance, GPT_CLOCKSOURCE_TI1ED);
4119 }
4120 break;
4121 case GPT_CLOCKSOURCE_ITR0:
4122 {
4123 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
4124 GPT_ITRx_SetConfig(htim->Instance, GPT_CLOCKSOURCE_ITR0);
4125 }
4126 break;
4127 case GPT_CLOCKSOURCE_ITR1:
4128 {
4129 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
4130 GPT_ITRx_SetConfig(htim->Instance, GPT_CLOCKSOURCE_ITR1);
4131 }
4132 break;
4133 case GPT_CLOCKSOURCE_ITR2:
4134 {
4135 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
4136 GPT_ITRx_SetConfig(htim->Instance, GPT_CLOCKSOURCE_ITR2);
4137 }
4138 break;
4139 case GPT_CLOCKSOURCE_ITR3:
4140 {
4141 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
4142 GPT_ITRx_SetConfig(htim->Instance, GPT_CLOCKSOURCE_ITR3);
4143 }
4144 break;
4145
4146 default:
4147 break;
4148 }
4149 htim->State = HAL_GPT_STATE_READY;
4150
4151 __HAL_UNLOCK(htim);
4152
4153 return HAL_OK;
4154 }
4155
4156 /**
4157 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
4158 * or a XOR combination between CH1_input, CH2_input & CH3_input
4159 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4160 * the configuration information for TIM module.
4161 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
4162 * output of a XOR gate.
4163 * This parameter can be one of the following values:
4164 * @arg GPT_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
4165 * @arg GPT_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
4166 * pins are connected to the TI1 input (XOR combination)
4167 * @retval HAL status
4168 */
HAL_GPT_ConfigTI1Input(GPT_HandleTypeDef * htim,uint32_t TI1_Selection)4169 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_ConfigTI1Input(GPT_HandleTypeDef *htim, uint32_t TI1_Selection)
4170 {
4171 uint32_t tmpcr2 = 0U;
4172
4173 /* Check the parameters */
4174 HAL_ASSERT(IS_GPT_XOR_INSTANCE(htim->Instance));
4175 HAL_ASSERT(IS_GPT_TI1SELECTION(TI1_Selection));
4176
4177 /* Get the TIMx CR2 register value */
4178 tmpcr2 = htim->Instance->CR2;
4179
4180 /* Reset the TI1 selection */
4181 tmpcr2 &= ~GPT_CR2_TI1S;
4182
4183 /* Set the TI1 selection */
4184 tmpcr2 |= TI1_Selection;
4185
4186 /* Write to TIMxCR2 */
4187 htim->Instance->CR2 = tmpcr2;
4188
4189 return HAL_OK;
4190 }
4191
4192 /**
4193 * @brief Configures the TIM in Slave mode
4194 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4195 * the configuration information for TIM module.
4196 * @param sSlaveConfig pointer to a GPT_SlaveConfigTypeDef structure that
4197 * contains the selected trigger (internal trigger input, filtered
4198 * timer input or external trigger input) and the ) and the Slave
4199 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4200 * @retval HAL status
4201 */
HAL_GPT_SlaveConfigSynchronization(GPT_HandleTypeDef * htim,GPT_SlaveConfigTypeDef * sSlaveConfig)4202 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_SlaveConfigSynchronization(GPT_HandleTypeDef *htim, GPT_SlaveConfigTypeDef *sSlaveConfig)
4203 {
4204 /* Check the parameters */
4205 HAL_ASSERT(IS_GPT_SLAVE_INSTANCE(htim->Instance));
4206 HAL_ASSERT(IS_GPT_SLAVE_MODE(sSlaveConfig->SlaveMode));
4207 HAL_ASSERT(IS_GPT_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4208
4209 __HAL_LOCK(htim);
4210
4211 htim->State = HAL_GPT_STATE_BUSY;
4212
4213 GPT_SlaveTimer_SetConfig(htim, sSlaveConfig);
4214
4215 /* Disable Trigger Interrupt */
4216 __HAL_GPT_DISABLE_IT(htim, GPT_IT_TRIGGER);
4217
4218 /* Disable Trigger DMA request */
4219 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_TRIGGER);
4220
4221 htim->State = HAL_GPT_STATE_READY;
4222
4223 __HAL_UNLOCK(htim);
4224
4225 return HAL_OK;
4226 }
4227
4228 /**
4229 * @brief Configures the TIM in Slave mode in interrupt mode
4230 * @param htim TIM handle.
4231 * @param sSlaveConfig pointer to a GPT_SlaveConfigTypeDef structure that
4232 * contains the selected trigger (internal trigger input, filtered
4233 * timer input or external trigger input) and the ) and the Slave
4234 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4235 * @retval HAL status
4236 */
HAL_GPT_SlaveConfigSynchronization_IT(GPT_HandleTypeDef * htim,GPT_SlaveConfigTypeDef * sSlaveConfig)4237 __HAL_ROM_USED HAL_StatusTypeDef HAL_GPT_SlaveConfigSynchronization_IT(GPT_HandleTypeDef *htim,
4238 GPT_SlaveConfigTypeDef *sSlaveConfig)
4239 {
4240 /* Check the parameters */
4241 HAL_ASSERT(IS_GPT_SLAVE_INSTANCE(htim->Instance));
4242 HAL_ASSERT(IS_GPT_SLAVE_MODE(sSlaveConfig->SlaveMode));
4243 HAL_ASSERT(IS_GPT_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4244
4245 __HAL_LOCK(htim);
4246
4247 htim->State = HAL_GPT_STATE_BUSY;
4248
4249 GPT_SlaveTimer_SetConfig(htim, sSlaveConfig);
4250
4251 /* Enable Trigger Interrupt */
4252 __HAL_GPT_ENABLE_IT(htim, GPT_IT_TRIGGER);
4253
4254 /* Disable Trigger DMA request */
4255 __HAL_GPT_DISABLE_DMA(htim, GPT_DMA_TRIGGER);
4256
4257 htim->State = HAL_GPT_STATE_READY;
4258
4259 __HAL_UNLOCK(htim);
4260
4261 return HAL_OK;
4262 }
4263
4264 /**
4265 * @brief Read the captured value from Capture Compare unit
4266 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4267 * the configuration information for TIM module.
4268 * @param Channel TIM Channels to be enabled.
4269 * This parameter can be one of the following values:
4270 * @arg GPT_CHANNEL_1: TIM Channel 1 selected
4271 * @arg GPT_CHANNEL_2: TIM Channel 2 selected
4272 * @arg GPT_CHANNEL_3: TIM Channel 3 selected
4273 * @arg GPT_CHANNEL_4: TIM Channel 4 selected
4274 * @retval Captured value
4275 */
HAL_GPT_ReadCapturedValue(GPT_HandleTypeDef * htim,uint32_t Channel)4276 __HAL_ROM_USED uint32_t HAL_GPT_ReadCapturedValue(GPT_HandleTypeDef *htim, uint32_t Channel)
4277 {
4278 uint32_t tmpreg = 0U;
4279
4280 __HAL_LOCK(htim);
4281
4282 switch (Channel)
4283 {
4284 case GPT_CHANNEL_1:
4285 {
4286 /* Check the parameters */
4287 HAL_ASSERT(IS_GPT_CC1_INSTANCE(htim->Instance));
4288
4289 /* Return the capture 1 value */
4290 tmpreg = htim->Instance->CCR1;
4291
4292 break;
4293 }
4294 case GPT_CHANNEL_2:
4295 {
4296 /* Check the parameters */
4297 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
4298
4299 /* Return the capture 2 value */
4300 tmpreg = htim->Instance->CCR2;
4301
4302 break;
4303 }
4304
4305 case GPT_CHANNEL_3:
4306 {
4307 /* Check the parameters */
4308 HAL_ASSERT(IS_GPT_CC3_INSTANCE(htim->Instance));
4309
4310 /* Return the capture 3 value */
4311 tmpreg = htim->Instance->CCR3;
4312
4313 break;
4314 }
4315
4316 case GPT_CHANNEL_4:
4317 {
4318 /* Check the parameters */
4319 HAL_ASSERT(IS_GPT_CC4_INSTANCE(htim->Instance));
4320
4321 /* Return the capture 4 value */
4322 tmpreg = htim->Instance->CCR4;
4323
4324 break;
4325 }
4326
4327 default:
4328 break;
4329 }
4330
4331 __HAL_UNLOCK(htim);
4332 return tmpreg;
4333 }
4334 /**
4335 * @}
4336 */
4337
4338 /** @defgroup GPT_Exported_Functions_Group9 TIM Callbacks functions
4339 * @brief TIM Callbacks functions
4340 *
4341 @verbatim
4342 ==============================================================================
4343 ##### TIM Callbacks functions #####
4344 ==============================================================================
4345 [..]
4346 This section provides TIM callback functions:
4347 (+) Timer Period elapsed callback
4348 (+) Timer Output Compare callback
4349 (+) Timer Input capture callback
4350 (+) Timer Trigger callback
4351 (+) Timer Error callback
4352
4353 @endverbatim
4354 * @{
4355 */
4356
4357 /**
4358 * @brief Period elapsed callback in non blocking mode
4359 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4360 * the configuration information for TIM module.
4361 * @retval None
4362 */
HAL_GPT_PeriodElapsedCallback(GPT_HandleTypeDef * htim)4363 __weak void HAL_GPT_PeriodElapsedCallback(GPT_HandleTypeDef *htim)
4364 {
4365 /* Prevent unused argument(s) compilation warning */
4366 UNUSED(htim);
4367 /* NOTE : This function Should not be modified, when the callback is needed,
4368 the __HAL_GPT_PeriodElapsedCallback could be implemented in the user file
4369 */
4370 }
4371
4372 /**
4373 * @brief Output Compare callback in non blocking mode
4374 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4375 * the configuration information for TIM module.
4376 * @retval None
4377 */
HAL_GPT_OC_DelayElapsedCallback(GPT_HandleTypeDef * htim)4378 __weak void HAL_GPT_OC_DelayElapsedCallback(GPT_HandleTypeDef *htim)
4379 {
4380 /* Prevent unused argument(s) compilation warning */
4381 UNUSED(htim);
4382 /* NOTE : This function Should not be modified, when the callback is needed,
4383 the __HAL_GPT_OC_DelayElapsedCallback could be implemented in the user file
4384 */
4385 }
4386
4387 /**
4388 * @brief Input Capture callback in non blocking mode
4389 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4390 * the configuration information for TIM module.
4391 * @retval None
4392 */
HAL_GPT_IC_CaptureCallback(GPT_HandleTypeDef * htim)4393 __weak void HAL_GPT_IC_CaptureCallback(GPT_HandleTypeDef *htim)
4394 {
4395 /* Prevent unused argument(s) compilation warning */
4396 UNUSED(htim);
4397 /* NOTE : This function Should not be modified, when the callback is needed,
4398 the __HAL_GPT_IC_CaptureCallback could be implemented in the user file
4399 */
4400 }
4401
4402 /**
4403 * @brief Input Capture half complete callback in non-blocking mode
4404 * @param htim TIM IC handle
4405 * @retval None
4406 */
HAL_GPT_IC_CaptureHalfCpltCallback(GPT_HandleTypeDef * htim)4407 __weak void HAL_GPT_IC_CaptureHalfCpltCallback(GPT_HandleTypeDef *htim)
4408 {
4409 /* Prevent unused argument(s) compilation warning */
4410 UNUSED(htim);
4411
4412 /* NOTE : This function should not be modified, when the callback is needed,
4413 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
4414 */
4415 }
4416
4417 /**
4418 * @brief PWM Pulse finished callback in non blocking mode
4419 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4420 * the configuration information for TIM module.
4421 * @retval None
4422 */
HAL_GPT_PWM_PulseFinishedCallback(GPT_HandleTypeDef * htim)4423 __weak void HAL_GPT_PWM_PulseFinishedCallback(GPT_HandleTypeDef *htim)
4424 {
4425 /* Prevent unused argument(s) compilation warning */
4426 UNUSED(htim);
4427 /* NOTE : This function Should not be modified, when the callback is needed,
4428 the __HAL_GPT_PWM_PulseFinishedCallback could be implemented in the user file
4429 */
4430 }
4431
4432 /**
4433 * @brief PWM Pulse finished half complete callback in non-blocking mode
4434 * @param htim TIM handle
4435 * @retval None
4436 */
HAL_GPT_PWM_PulseFinishedHalfCpltCallback(GPT_HandleTypeDef * htim)4437 __weak void HAL_GPT_PWM_PulseFinishedHalfCpltCallback(GPT_HandleTypeDef *htim)
4438 {
4439 /* Prevent unused argument(s) compilation warning */
4440 UNUSED(htim);
4441
4442 /* NOTE : This function should not be modified, when the callback is needed,
4443 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
4444 */
4445 }
4446
4447
4448 /**
4449 * @brief Hall Trigger detection callback in non blocking mode
4450 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4451 * the configuration information for TIM module.
4452 * @retval None
4453 */
HAL_GPT_TriggerCallback(GPT_HandleTypeDef * htim)4454 __weak void HAL_GPT_TriggerCallback(GPT_HandleTypeDef *htim)
4455 {
4456 /* Prevent unused argument(s) compilation warning */
4457 UNUSED(htim);
4458 /* NOTE : This function Should not be modified, when the callback is needed,
4459 the HAL_GPT_TriggerCallback could be implemented in the user file
4460 */
4461 }
4462
4463 /**
4464 * @brief Timer error callback in non blocking mode
4465 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4466 * the configuration information for TIM module.
4467 * @retval None
4468 */
HAL_GPT_ErrorCallback(GPT_HandleTypeDef * htim)4469 __weak void HAL_GPT_ErrorCallback(GPT_HandleTypeDef *htim)
4470 {
4471 /* Prevent unused argument(s) compilation warning */
4472 UNUSED(htim);
4473 /* NOTE : This function Should not be modified, when the callback is needed,
4474 the HAL_GPT_ErrorCallback could be implemented in the user file
4475 */
4476 }
4477 /**
4478 * @}
4479 */
4480
4481 /** @defgroup GPT_Exported_Functions_Group10 Peripheral State functions
4482 * @brief Peripheral State functions
4483 *
4484 @verbatim
4485 ==============================================================================
4486 ##### Peripheral State functions #####
4487 ==============================================================================
4488 [..]
4489 This subsection permits to get in run-time the status of the peripheral
4490 and the data flow.
4491
4492 @endverbatim
4493 * @{
4494 */
4495
4496 /**
4497 * @brief Return the TIM Base state
4498 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4499 * the configuration information for TIM module.
4500 * @retval HAL state
4501 */
HAL_GPT_Base_GetState(GPT_HandleTypeDef * htim)4502 __HAL_ROM_USED HAL_GPT_StateTypeDef HAL_GPT_Base_GetState(GPT_HandleTypeDef *htim)
4503 {
4504 return htim->State;
4505 }
4506
4507 /**
4508 * @brief Return the TIM OC state
4509 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4510 * the configuration information for TIM module.
4511 * @retval HAL state
4512 */
HAL_GPT_OC_GetState(GPT_HandleTypeDef * htim)4513 __HAL_ROM_USED HAL_GPT_StateTypeDef HAL_GPT_OC_GetState(GPT_HandleTypeDef *htim)
4514 {
4515 return htim->State;
4516 }
4517
4518 /**
4519 * @brief Return the TIM PWM state
4520 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4521 * the configuration information for TIM module.
4522 * @retval HAL state
4523 */
HAL_GPT_PWM_GetState(GPT_HandleTypeDef * htim)4524 __HAL_ROM_USED HAL_GPT_StateTypeDef HAL_GPT_PWM_GetState(GPT_HandleTypeDef *htim)
4525 {
4526 return htim->State;
4527 }
4528
4529 /**
4530 * @brief Return the TIM Input Capture state
4531 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4532 * the configuration information for TIM module.
4533 * @retval HAL state
4534 */
HAL_GPT_IC_GetState(GPT_HandleTypeDef * htim)4535 __HAL_ROM_USED HAL_GPT_StateTypeDef HAL_GPT_IC_GetState(GPT_HandleTypeDef *htim)
4536 {
4537 return htim->State;
4538 }
4539
4540 /**
4541 * @brief Return the TIM One Pulse Mode state
4542 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4543 * the configuration information for TIM module.
4544 * @retval HAL state
4545 */
HAL_GPT_OnePulse_GetState(GPT_HandleTypeDef * htim)4546 __HAL_ROM_USED HAL_GPT_StateTypeDef HAL_GPT_OnePulse_GetState(GPT_HandleTypeDef *htim)
4547 {
4548 return htim->State;
4549 }
4550
4551 /**
4552 * @brief Return the TIM Encoder Mode state
4553 * @param htim pointer to a GPT_HandleTypeDef structure that contains
4554 * the configuration information for TIM module.
4555 * @retval HAL state
4556 */
HAL_GPT_Encoder_GetState(GPT_HandleTypeDef * htim)4557 __HAL_ROM_USED HAL_GPT_StateTypeDef HAL_GPT_Encoder_GetState(GPT_HandleTypeDef *htim)
4558 {
4559 return htim->State;
4560 }
4561 /**
4562 * @}
4563 */
4564
4565 /**
4566 * @brief Time Base configuration
4567 * @param TIMx TIM peripheral
4568 * @param Structure pointer on TIM Time Base required parameters
4569 * @retval None
4570 */
GPT_Base_SetConfig(GPT_TypeDef * TIMx,GPT_Base_InitTypeDef * Structure)4571 __HAL_ROM_USED void GPT_Base_SetConfig(GPT_TypeDef *TIMx, GPT_Base_InitTypeDef *Structure)
4572 {
4573 uint32_t tmpcr1 = 0U;
4574 tmpcr1 = TIMx->CR1;
4575
4576 /* Set TIM Time Base Unit parameters ---------------------------------------*/
4577 if (IS_GPT_CC3_INSTANCE(TIMx) != RESET)
4578 {
4579 /* Select the Counter Mode */
4580 tmpcr1 &= ~(GPT_CR1_DIR | GPT_CR1_CMS);
4581 tmpcr1 |= Structure->CounterMode;
4582 }
4583
4584 TIMx->CR1 = tmpcr1;
4585
4586 /* Set the Auto-reload value */
4587 TIMx->ARR = (uint32_t)Structure->Period ;
4588
4589 /* Set the Prescaler value */
4590 TIMx->PSC = (uint32_t)Structure->Prescaler;
4591
4592 if (IS_GPT_ADVANCED_INSTANCE(TIMx) != RESET)
4593 {
4594 /* Set the Repetition Counter value */
4595 #if 1 // Revisit for advanced timer ????
4596 TIMx->RCR = Structure->RepetitionCounter;
4597 #endif
4598 }
4599
4600 /* Generate an update event to reload the Prescaler
4601 and the repetition counter(only for TIM1 and TIM8) value immediately */
4602 TIMx->EGR = GPT_EGR_UG;
4603 }
4604
4605 /**
4606 * @brief Configure the TI1 as Input.
4607 * @param TIMx to select the TIM peripheral.
4608 * @param GPT_ICPolarity The Input Polarity.
4609 * This parameter can be one of the following values:
4610 * @arg GPT_ICPolarity_Rising
4611 * @arg GPT_ICPolarity_Falling
4612 * @arg GPT_ICPolarity_BothEdge
4613 * @param GPT_ICSelection specifies the input to be used.
4614 * This parameter can be one of the following values:
4615 * @arg GPT_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
4616 * @arg GPT_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
4617 * @arg GPT_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
4618 * @param GPT_ICFilter Specifies the Input Capture Filter.
4619 * This parameter must be a value between 0x00 and 0x0F.
4620 * @note GPT_ICFilter and GPT_ICPolarity are not used in INDIRECT mode as TI2FP1
4621 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
4622 * protected against un-initialized filter and polarity values.
4623 * @retval None
4624 */
GPT_TI1_SetConfig(GPT_TypeDef * TIMx,uint32_t GPT_ICPolarity,uint32_t GPT_ICSelection,uint32_t GPT_ICFilter)4625 __HAL_ROM_USED void GPT_TI1_SetConfig(GPT_TypeDef *TIMx, uint32_t GPT_ICPolarity, uint32_t GPT_ICSelection,
4626 uint32_t GPT_ICFilter)
4627 {
4628 uint32_t tmpccmr1 = 0U;
4629 uint32_t tmpccer = 0U;
4630
4631 /* Disable the Channel 1: Reset the CC1E Bit */
4632 TIMx->CCER &= ~GPT_CCER_CC1E;
4633 tmpccmr1 = TIMx->CCMR1;
4634 tmpccer = TIMx->CCER;
4635
4636 /* Select the Input */
4637 if (IS_GPT_CC2_INSTANCE(TIMx) != RESET)
4638 {
4639 tmpccmr1 &= ~GPT_CCMR1_CC1S;
4640 tmpccmr1 |= GPT_ICSelection;
4641 }
4642 else
4643 {
4644 tmpccmr1 &= ~GPT_CCMR1_CC1S;
4645 tmpccmr1 |= GPT_CCMR1_CC1S_0;
4646 }
4647
4648 /* Set the filter */
4649 tmpccmr1 &= ~GPT_CCMR1_IC1F;
4650 tmpccmr1 |= ((GPT_ICFilter << 4U) & GPT_CCMR1_IC1F);
4651
4652 /* Select the Polarity and set the CC1E Bit */
4653 tmpccer &= ~(GPT_CCER_CC1P | GPT_CCER_CC1NP);
4654 tmpccer |= (GPT_ICPolarity & (GPT_CCER_CC1P | GPT_CCER_CC1NP));
4655
4656 /* Write to TIMx CCMR1 and CCER registers */
4657 TIMx->CCMR1 = tmpccmr1;
4658 TIMx->CCER = tmpccer;
4659 }
4660
4661 /**
4662 * @brief Time Output Compare 2 configuration
4663 * @param TIMx to select the TIM peripheral
4664 * @param OC_Config The output configuration structure
4665 * @retval None
4666 */
GPT_OC2_SetConfig(GPT_TypeDef * TIMx,GPT_OC_InitTypeDef * OC_Config)4667 __HAL_ROM_USED void GPT_OC2_SetConfig(GPT_TypeDef *TIMx, GPT_OC_InitTypeDef *OC_Config)
4668 {
4669 uint32_t tmpccmrx = 0U;
4670 uint32_t tmpccer = 0U;
4671 uint32_t tmpcr2 = 0U;
4672
4673 /* Disable the Channel 2: Reset the CC2E Bit */
4674 TIMx->CCER &= ~GPT_CCER_CC2E;
4675
4676 /* Get the TIMx CCER register value */
4677 tmpccer = TIMx->CCER;
4678 /* Get the TIMx CR2 register value */
4679 tmpcr2 = TIMx->CR2;
4680
4681 /* Get the TIMx CCMR1 register value */
4682 tmpccmrx = TIMx->CCMR1;
4683
4684 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4685 tmpccmrx &= ~GPT_CCMR1_OC2M;
4686 tmpccmrx &= ~GPT_CCMR1_CC2S;
4687
4688 /* Select the Output Compare Mode */
4689 tmpccmrx |= (OC_Config->OCMode << 8U);
4690
4691 /* Reset the Output Polarity level */
4692 tmpccer &= ~GPT_CCER_CC2P;
4693 /* Set the Output Compare Polarity */
4694 tmpccer |= (OC_Config->OCPolarity << 4U);
4695
4696 if (IS_GPT_ADVANCED_INSTANCE(TIMx) != RESET)
4697 {
4698 HAL_ASSERT(IS_GPT_OCN_POLARITY(OC_Config->OCNPolarity));
4699
4700 /* Reset the Output N Polarity level */
4701 tmpccer &= ~GPT_CCER_CC2NP;
4702 /* Set the Output N Polarity */
4703 tmpccer |= (OC_Config->OCNPolarity << 4U);
4704 /* Reset the Output N State */
4705 tmpccer &= ~GPT_CCER_CC2NE;
4706
4707 /* Reset the Output Compare and Output Compare N IDLE State */
4708 tmpcr2 &= ~GPT_CR2_OIS2;
4709 tmpcr2 &= ~GPT_CR2_OIS2N;
4710 /* Set the Output Idle state */
4711 tmpcr2 |= (OC_Config->OCIdleState << 2U);
4712 /* Set the Output N Idle state */
4713 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
4714 }
4715 /* Write to TIMx CR2 */
4716 TIMx->CR2 = tmpcr2;
4717
4718 /* Write to TIMx CCMR1 */
4719 TIMx->CCMR1 = tmpccmrx;
4720
4721 /* Set the Capture Compare Register value */
4722 TIMx->CCR2 = OC_Config->Pulse;
4723
4724 /* Write to TIMx CCER */
4725 TIMx->CCER = tmpccer;
4726 }
4727
4728 /**
4729 * @brief TIM DMA Delay Pulse complete callback.
4730 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
4731 * the configuration information for the specified DMA module.
4732 * @retval None
4733 */
GPT_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)4734 __HAL_ROM_USED void GPT_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
4735 {
4736 GPT_HandleTypeDef *htim = (GPT_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
4737
4738 htim->State = HAL_GPT_STATE_READY;
4739
4740 if (hdma == htim->hdma[GPT_DMA_ID_CC1])
4741 {
4742 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_1;
4743 }
4744 else if (hdma == htim->hdma[GPT_DMA_ID_CC2])
4745 {
4746 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_2;
4747 }
4748 else if (hdma == htim->hdma[GPT_DMA_ID_CC3])
4749 {
4750 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_3;
4751 }
4752 else if (hdma == htim->hdma[GPT_DMA_ID_CC4])
4753 {
4754 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_4;
4755 }
4756
4757 HAL_GPT_PWM_PulseFinishedCallback(htim);
4758
4759 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_CLEARED;
4760 }
4761
4762 /**
4763 * @brief TIM DMA error callback
4764 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
4765 * the configuration information for the specified DMA module.
4766 * @retval None
4767 */
GPT_DMAError(DMA_HandleTypeDef * hdma)4768 __HAL_ROM_USED void GPT_DMAError(DMA_HandleTypeDef *hdma)
4769 {
4770 GPT_HandleTypeDef *htim = (GPT_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
4771
4772 htim->State = HAL_GPT_STATE_READY;
4773
4774 HAL_GPT_ErrorCallback(htim);
4775 }
4776
4777 /**
4778 * @brief TIM DMA Capture complete callback.
4779 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
4780 * the configuration information for the specified DMA module.
4781 * @retval None
4782 */
GPT_DMACaptureCplt(DMA_HandleTypeDef * hdma)4783 void GPT_DMACaptureCplt(DMA_HandleTypeDef *hdma)
4784 {
4785 GPT_HandleTypeDef *htim = (GPT_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
4786
4787 htim->State = HAL_GPT_STATE_READY;
4788
4789 if (hdma == htim->hdma[GPT_DMA_ID_CC1])
4790 {
4791 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_1;
4792 }
4793 else if (hdma == htim->hdma[GPT_DMA_ID_CC2])
4794 {
4795 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_2;
4796 }
4797 else if (hdma == htim->hdma[GPT_DMA_ID_CC3])
4798 {
4799 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_3;
4800 }
4801 else if (hdma == htim->hdma[GPT_DMA_ID_CC4])
4802 {
4803 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_4;
4804 }
4805
4806 HAL_GPT_IC_CaptureCallback(htim);
4807
4808 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_CLEARED;
4809 }
4810
4811 /**
4812 * @brief TIM DMA Capture half complete callback.
4813 * @param hdma pointer to DMA handle.
4814 * @retval None
4815 */
GPT_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)4816 void GPT_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
4817 {
4818 GPT_HandleTypeDef *htim = (GPT_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
4819
4820 if (hdma == htim->hdma[GPT_DMA_ID_CC1])
4821 {
4822 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_1;
4823 }
4824 else if (hdma == htim->hdma[GPT_DMA_ID_CC2])
4825 {
4826 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_2;
4827 }
4828 else if (hdma == htim->hdma[GPT_DMA_ID_CC3])
4829 {
4830 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_3;
4831 }
4832 else if (hdma == htim->hdma[GPT_DMA_ID_CC4])
4833 {
4834 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_4;
4835 }
4836 else
4837 {
4838 /* nothing to do */
4839 }
4840
4841 HAL_GPT_IC_CaptureHalfCpltCallback(htim);
4842
4843 htim->Channel = HAL_GPT_ACTIVE_CHANNEL_CLEARED;
4844 }
4845
4846
4847 /**
4848 * @brief Enables or disables the TIM Capture Compare Channel x.
4849 * @param TIMx to select the TIM peripheral
4850 * @param Channel specifies the TIM Channel
4851 * This parameter can be one of the following values:
4852 * @arg GPT_Channel_1: TIM Channel 1
4853 * @arg GPT_Channel_2: TIM Channel 2
4854 * @arg GPT_Channel_3: TIM Channel 3
4855 * @arg GPT_Channel_4: TIM Channel 4
4856 * @param ChannelState specifies the TIM Channel CCxE bit new state.
4857 * This parameter can be: GPT_CCx_ENABLE or GPT_CCx_Disable.
4858 * @retval None
4859 */
GPT_CCxChannelCmd(GPT_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)4860 void GPT_CCxChannelCmd(GPT_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
4861 {
4862 uint32_t tmp = 0U;
4863
4864 /* Check the parameters */
4865 HAL_ASSERT(IS_GPT_CC1_INSTANCE(TIMx));
4866 HAL_ASSERT(IS_GPT_CHANNELS(Channel));
4867
4868 tmp = GPT_CCER_CC1E << Channel;
4869
4870 /* Reset the CCxE Bit */
4871 TIMx->CCER &= ~tmp;
4872
4873 /* Set or reset the CCxE Bit */
4874 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
4875 }
4876
4877 /**
4878 * @brief TIM DMA Period Elapse complete callback.
4879 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
4880 * the configuration information for the specified DMA module.
4881 * @retval None
4882 */
GPT_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)4883 static void GPT_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
4884 {
4885 GPT_HandleTypeDef *htim = (GPT_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
4886
4887 htim->State = HAL_GPT_STATE_READY;
4888
4889 HAL_GPT_PeriodElapsedCallback(htim);
4890 }
4891
4892 /**
4893 * @brief TIM DMA Trigger callback.
4894 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
4895 * the configuration information for the specified DMA module.
4896 * @retval None
4897 */
GPT_DMATriggerCplt(DMA_HandleTypeDef * hdma)4898 static void GPT_DMATriggerCplt(DMA_HandleTypeDef *hdma)
4899 {
4900 GPT_HandleTypeDef *htim = (GPT_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
4901
4902 htim->State = HAL_GPT_STATE_READY;
4903
4904 HAL_GPT_TriggerCallback(htim);
4905 }
4906
4907 /**
4908 * @brief Time Output Compare 1 configuration
4909 * @param TIMx to select the TIM peripheral
4910 * @param OC_Config The output configuration structure
4911 * @retval None
4912 */
GPT_OC1_SetConfig(GPT_TypeDef * TIMx,GPT_OC_InitTypeDef * OC_Config)4913 static void GPT_OC1_SetConfig(GPT_TypeDef *TIMx, GPT_OC_InitTypeDef *OC_Config)
4914 {
4915 uint32_t tmpccmrx = 0U;
4916 uint32_t tmpccer = 0U;
4917 uint32_t tmpcr2 = 0U;
4918
4919 /* Disable the Channel 1: Reset the CC1E Bit */
4920 TIMx->CCER &= ~GPT_CCER_CC1E;
4921
4922 /* Get the TIMx CCER register value */
4923 tmpccer = TIMx->CCER;
4924 /* Get the TIMx CR2 register value */
4925 tmpcr2 = TIMx->CR2;
4926
4927 /* Get the TIMx CCMR1 register value */
4928 tmpccmrx = TIMx->CCMR1;
4929
4930 /* Reset the Output Compare Mode Bits */
4931 tmpccmrx &= ~GPT_CCMR1_OC1M;
4932 tmpccmrx &= ~GPT_CCMR1_CC1S;
4933 /* Select the Output Compare Mode */
4934 tmpccmrx |= OC_Config->OCMode;
4935
4936 /* Reset the Output Polarity level */
4937 tmpccer &= ~GPT_CCER_CC1P;
4938 /* Set the Output Compare Polarity */
4939 tmpccer |= OC_Config->OCPolarity;
4940
4941
4942 if (IS_GPT_ADVANCED_INSTANCE(TIMx) != RESET)
4943 {
4944 /* Reset the Output N Polarity level */
4945 tmpccer &= ~GPT_CCER_CC1NP;
4946 /* Set the Output N Polarity */
4947 tmpccer |= OC_Config->OCNPolarity;
4948 /* Reset the Output N State */
4949 tmpccer &= ~GPT_CCER_CC1NE;
4950
4951 /* Reset the Output Compare and Output Compare N IDLE State */
4952 tmpcr2 &= ~GPT_CR2_OIS1;
4953 tmpcr2 &= ~GPT_CR2_OIS1N;
4954 /* Set the Output Idle state */
4955 tmpcr2 |= OC_Config->OCIdleState;
4956 /* Set the Output N Idle state */
4957 tmpcr2 |= OC_Config->OCNIdleState;
4958 }
4959 /* Write to TIMx CR2 */
4960 TIMx->CR2 = tmpcr2;
4961
4962 /* Write to TIMx CCMR1 */
4963 TIMx->CCMR1 = tmpccmrx;
4964
4965 /* Set the Capture Compare Register value */
4966 TIMx->CCR1 = OC_Config->Pulse;
4967
4968 /* Write to TIMx CCER */
4969 TIMx->CCER = tmpccer;
4970 }
4971
4972 /**
4973 * @brief Time Output Compare 3 configuration
4974 * @param TIMx to select the TIM peripheral
4975 * @param OC_Config The output configuration structure
4976 * @retval None
4977 */
GPT_OC3_SetConfig(GPT_TypeDef * TIMx,GPT_OC_InitTypeDef * OC_Config)4978 static void GPT_OC3_SetConfig(GPT_TypeDef *TIMx, GPT_OC_InitTypeDef *OC_Config)
4979 {
4980 uint32_t tmpccmrx = 0U;
4981 uint32_t tmpccer = 0U;
4982 uint32_t tmpcr2 = 0U;
4983
4984 /* Disable the Channel 3: Reset the CC2E Bit */
4985 TIMx->CCER &= ~GPT_CCER_CC3E;
4986
4987 /* Get the TIMx CCER register value */
4988 tmpccer = TIMx->CCER;
4989 /* Get the TIMx CR2 register value */
4990 tmpcr2 = TIMx->CR2;
4991
4992 /* Get the TIMx CCMR2 register value */
4993 tmpccmrx = TIMx->CCMR2;
4994
4995 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4996 tmpccmrx &= ~GPT_CCMR2_OC3M;
4997 tmpccmrx &= ~GPT_CCMR2_CC3S;
4998 /* Select the Output Compare Mode */
4999 tmpccmrx |= OC_Config->OCMode;
5000
5001 /* Reset the Output Polarity level */
5002 tmpccer &= ~GPT_CCER_CC3P;
5003 /* Set the Output Compare Polarity */
5004 tmpccer |= (OC_Config->OCPolarity << 8U);
5005
5006 if (IS_GPT_ADVANCED_INSTANCE(TIMx) != RESET)
5007 {
5008 HAL_ASSERT(IS_GPT_OCN_POLARITY(OC_Config->OCNPolarity));
5009 HAL_ASSERT(IS_GPT_OCNIDLE_STATE(OC_Config->OCNIdleState));
5010 HAL_ASSERT(IS_GPT_OCIDLE_STATE(OC_Config->OCIdleState));
5011
5012 /* Reset the Output N Polarity level */
5013 tmpccer &= ~GPT_CCER_CC3NP;
5014 /* Set the Output N Polarity */
5015 tmpccer |= (OC_Config->OCNPolarity << 8U);
5016 /* Reset the Output N State */
5017 tmpccer &= ~GPT_CCER_CC3NE;
5018
5019 /* Reset the Output Compare and Output Compare N IDLE State */
5020 tmpcr2 &= ~GPT_CR2_OIS3;
5021 tmpcr2 &= ~GPT_CR2_OIS3N;
5022 /* Set the Output Idle state */
5023 tmpcr2 |= (OC_Config->OCIdleState << 4U);
5024 /* Set the Output N Idle state */
5025 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
5026 }
5027 /* Write to TIMx CR2 */
5028 TIMx->CR2 = tmpcr2;
5029
5030 /* Write to TIMx CCMR2 */
5031 TIMx->CCMR2 = tmpccmrx;
5032
5033 /* Set the Capture Compare Register value */
5034 TIMx->CCR3 = OC_Config->Pulse;
5035
5036 /* Write to TIMx CCER */
5037 TIMx->CCER = tmpccer;
5038 }
5039
5040 /**
5041 * @brief Time Output Compare 4 configuration
5042 * @param TIMx to select the TIM peripheral
5043 * @param OC_Config The output configuration structure
5044 * @retval None
5045 */
GPT_OC4_SetConfig(GPT_TypeDef * TIMx,GPT_OC_InitTypeDef * OC_Config)5046 static void GPT_OC4_SetConfig(GPT_TypeDef *TIMx, GPT_OC_InitTypeDef *OC_Config)
5047 {
5048 uint32_t tmpccmrx = 0U;
5049 uint32_t tmpccer = 0U;
5050 uint32_t tmpcr2 = 0U;
5051
5052 /* Disable the Channel 4: Reset the CC4E Bit */
5053 TIMx->CCER &= ~GPT_CCER_CC4E;
5054
5055 /* Get the TIMx CCER register value */
5056 tmpccer = TIMx->CCER;
5057 /* Get the TIMx CR2 register value */
5058 tmpcr2 = TIMx->CR2;
5059
5060 /* Get the TIMx CCMR2 register value */
5061 tmpccmrx = TIMx->CCMR2;
5062
5063 /* Reset the Output Compare mode and Capture/Compare selection Bits */
5064 tmpccmrx &= ~GPT_CCMR2_OC4M;
5065 tmpccmrx &= ~GPT_CCMR2_CC4S;
5066
5067 /* Select the Output Compare Mode */
5068 tmpccmrx |= (OC_Config->OCMode << 8U);
5069
5070 /* Reset the Output Polarity level */
5071 tmpccer &= ~GPT_CCER_CC4P;
5072 /* Set the Output Compare Polarity */
5073 tmpccer |= (OC_Config->OCPolarity << 12U);
5074
5075 /*if((TIMx == TIM1) || (TIMx == TIM8))*/
5076 if (IS_GPT_ADVANCED_INSTANCE(TIMx) != RESET)
5077 {
5078 HAL_ASSERT(IS_GPT_OCIDLE_STATE(OC_Config->OCIdleState));
5079 /* Reset the Output Compare IDLE State */
5080 tmpcr2 &= ~GPT_CR2_OIS4;
5081 /* Set the Output Idle state */
5082 tmpcr2 |= (OC_Config->OCIdleState << 6U);
5083 }
5084 /* Write to TIMx CR2 */
5085 TIMx->CR2 = tmpcr2;
5086
5087 /* Write to TIMx CCMR2 */
5088 TIMx->CCMR2 = tmpccmrx;
5089
5090 /* Set the Capture Compare Register value */
5091 TIMx->CCR4 = OC_Config->Pulse;
5092
5093 /* Write to TIMx CCER */
5094 TIMx->CCER = tmpccer;
5095 }
5096
5097 /**
5098 * @brief Time Output Compare 4 configuration
5099 * @param htim pointer to a GPT_HandleTypeDef structure that contains
5100 * the configuration information for TIM module.
5101 * @param sSlaveConfig The slave configuration structure
5102 * @retval None
5103 */
GPT_SlaveTimer_SetConfig(GPT_HandleTypeDef * htim,GPT_SlaveConfigTypeDef * sSlaveConfig)5104 static void GPT_SlaveTimer_SetConfig(GPT_HandleTypeDef *htim,
5105 GPT_SlaveConfigTypeDef *sSlaveConfig)
5106 {
5107 uint32_t tmpsmcr = 0U;
5108 uint32_t tmpccmr1 = 0U;
5109 uint32_t tmpccer = 0U;
5110
5111 /* Get the TIMx SMCR register value */
5112 tmpsmcr = htim->Instance->SMCR;
5113
5114 /* Reset the Trigger Selection Bits */
5115 tmpsmcr &= ~GPT_SMCR_TS;
5116 /* Set the Input Trigger source */
5117 tmpsmcr |= sSlaveConfig->InputTrigger;
5118
5119 /* Reset the slave mode Bits */
5120 tmpsmcr &= ~GPT_SMCR_SMS;
5121 /* Set the slave mode */
5122 tmpsmcr |= sSlaveConfig->SlaveMode;
5123
5124 /* Write to TIMx SMCR */
5125 htim->Instance->SMCR = tmpsmcr;
5126
5127 /* Configure the trigger prescaler, filter, and polarity */
5128 switch (sSlaveConfig->InputTrigger)
5129 {
5130 case GPT_TS_ETRF:
5131 {
5132 /* Check the parameters */
5133 HAL_ASSERT(IS_GPT_ETR_INSTANCE(htim->Instance));
5134 HAL_ASSERT(IS_GPT_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
5135 HAL_ASSERT(IS_GPT_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
5136 HAL_ASSERT(IS_GPT_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
5137 /* Configure the ETR Trigger source */
5138 GPT_ETR_SetConfig(htim->Instance,
5139 sSlaveConfig->TriggerPrescaler,
5140 sSlaveConfig->TriggerPolarity,
5141 sSlaveConfig->TriggerFilter);
5142 }
5143 break;
5144
5145 case GPT_TS_TI1F_ED:
5146 {
5147 /* Check the parameters */
5148 HAL_ASSERT(IS_GPT_CC1_INSTANCE(htim->Instance));
5149 HAL_ASSERT(IS_GPT_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
5150
5151 /* Disable the Channel 1: Reset the CC1E Bit */
5152 tmpccer = htim->Instance->CCER;
5153 htim->Instance->CCER &= ~GPT_CCER_CC1E;
5154 tmpccmr1 = htim->Instance->CCMR1;
5155
5156 /* Set the filter */
5157 tmpccmr1 &= ~GPT_CCMR1_IC1F;
5158 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
5159
5160 /* Write to TIMx CCMR1 and CCER registers */
5161 htim->Instance->CCMR1 = tmpccmr1;
5162 htim->Instance->CCER = tmpccer;
5163
5164 }
5165 break;
5166
5167 case GPT_TS_TI1FP1:
5168 {
5169 /* Check the parameters */
5170 HAL_ASSERT(IS_GPT_CC1_INSTANCE(htim->Instance));
5171 HAL_ASSERT(IS_GPT_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
5172 HAL_ASSERT(IS_GPT_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
5173
5174 /* Configure TI1 Filter and Polarity */
5175 GPT_TI1_ConfigInputStage(htim->Instance,
5176 sSlaveConfig->TriggerPolarity,
5177 sSlaveConfig->TriggerFilter);
5178 }
5179 break;
5180
5181 case GPT_TS_TI2FP2:
5182 {
5183 /* Check the parameters */
5184 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
5185 HAL_ASSERT(IS_GPT_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
5186 HAL_ASSERT(IS_GPT_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
5187
5188 /* Configure TI2 Filter and Polarity */
5189 GPT_TI2_ConfigInputStage(htim->Instance,
5190 sSlaveConfig->TriggerPolarity,
5191 sSlaveConfig->TriggerFilter);
5192 }
5193 break;
5194
5195 case GPT_TS_ITR0:
5196 {
5197 /* Check the parameter */
5198 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
5199 }
5200 break;
5201
5202 case GPT_TS_ITR1:
5203 {
5204 /* Check the parameter */
5205 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
5206 }
5207 break;
5208
5209 case GPT_TS_ITR2:
5210 {
5211 /* Check the parameter */
5212 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
5213 }
5214 break;
5215
5216 case GPT_TS_ITR3:
5217 {
5218 /* Check the parameter */
5219 HAL_ASSERT(IS_GPT_CC2_INSTANCE(htim->Instance));
5220 }
5221 break;
5222
5223 default:
5224 break;
5225 }
5226 }
5227
5228
5229 /**
5230 * @brief Configure the Polarity and Filter for TI1.
5231 * @param TIMx to select the TIM peripheral.
5232 * @param GPT_ICPolarity The Input Polarity.
5233 * This parameter can be one of the following values:
5234 * @arg GPT_ICPolarity_Rising
5235 * @arg GPT_ICPolarity_Falling
5236 * @arg GPT_ICPolarity_BothEdge
5237 * @param GPT_ICFilter Specifies the Input Capture Filter.
5238 * This parameter must be a value between 0x00 and 0x0F.
5239 * @retval None
5240 */
GPT_TI1_ConfigInputStage(GPT_TypeDef * TIMx,uint32_t GPT_ICPolarity,uint32_t GPT_ICFilter)5241 static void GPT_TI1_ConfigInputStage(GPT_TypeDef *TIMx, uint32_t GPT_ICPolarity, uint32_t GPT_ICFilter)
5242 {
5243 uint32_t tmpccmr1 = 0U;
5244 uint32_t tmpccer = 0U;
5245
5246 /* Disable the Channel 1: Reset the CC1E Bit */
5247 tmpccer = TIMx->CCER;
5248 TIMx->CCER &= ~GPT_CCER_CC1E;
5249 tmpccmr1 = TIMx->CCMR1;
5250
5251 /* Set the filter */
5252 tmpccmr1 &= ~GPT_CCMR1_IC1F;
5253 tmpccmr1 |= (GPT_ICFilter << 4U);
5254
5255 /* Select the Polarity and set the CC1E Bit */
5256 tmpccer &= ~(GPT_CCER_CC1P | GPT_CCER_CC1NP);
5257 tmpccer |= GPT_ICPolarity;
5258
5259 /* Write to TIMx CCMR1 and CCER registers */
5260 TIMx->CCMR1 = tmpccmr1;
5261 TIMx->CCER = tmpccer;
5262 }
5263
5264 /**
5265 * @brief Configure the TI2 as Input.
5266 * @param TIMx to select the TIM peripheral
5267 * @param GPT_ICPolarity The Input Polarity.
5268 * This parameter can be one of the following values:
5269 * @arg GPT_ICPolarity_Rising
5270 * @arg GPT_ICPolarity_Falling
5271 * @arg GPT_ICPolarity_BothEdge
5272 * @param GPT_ICSelection specifies the input to be used.
5273 * This parameter can be one of the following values:
5274 * @arg GPT_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
5275 * @arg GPT_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
5276 * @arg GPT_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
5277 * @param GPT_ICFilter Specifies the Input Capture Filter.
5278 * This parameter must be a value between 0x00 and 0x0F.
5279 * @note GPT_ICFilter and GPT_ICPolarity are not used in INDIRECT mode as TI1FP2
5280 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
5281 * protected against un-initialized filter and polarity values.
5282 * @retval None
5283 */
GPT_TI2_SetConfig(GPT_TypeDef * TIMx,uint32_t GPT_ICPolarity,uint32_t GPT_ICSelection,uint32_t GPT_ICFilter)5284 static void GPT_TI2_SetConfig(GPT_TypeDef *TIMx, uint32_t GPT_ICPolarity, uint32_t GPT_ICSelection,
5285 uint32_t GPT_ICFilter)
5286 {
5287 uint32_t tmpccmr1 = 0U;
5288 uint32_t tmpccer = 0U;
5289
5290 /* Disable the Channel 2: Reset the CC2E Bit */
5291 TIMx->CCER &= ~GPT_CCER_CC2E;
5292 tmpccmr1 = TIMx->CCMR1;
5293 tmpccer = TIMx->CCER;
5294
5295 /* Select the Input */
5296 tmpccmr1 &= ~GPT_CCMR1_CC2S;
5297 tmpccmr1 |= (GPT_ICSelection << 8U);
5298
5299 /* Set the filter */
5300 tmpccmr1 &= ~GPT_CCMR1_IC2F;
5301 tmpccmr1 |= ((GPT_ICFilter << 12U) & GPT_CCMR1_IC2F);
5302
5303 /* Select the Polarity and set the CC2E Bit */
5304 tmpccer &= ~(GPT_CCER_CC2P | GPT_CCER_CC2NP);
5305 tmpccer |= ((GPT_ICPolarity << 4U) & (GPT_CCER_CC2P | GPT_CCER_CC2NP));
5306
5307 /* Write to TIMx CCMR1 and CCER registers */
5308 TIMx->CCMR1 = tmpccmr1 ;
5309 TIMx->CCER = tmpccer;
5310 }
5311
5312 /**
5313 * @brief Configure the Polarity and Filter for TI2.
5314 * @param TIMx to select the TIM peripheral.
5315 * @param GPT_ICPolarity The Input Polarity.
5316 * This parameter can be one of the following values:
5317 * @arg GPT_ICPolarity_Rising
5318 * @arg GPT_ICPolarity_Falling
5319 * @arg GPT_ICPolarity_BothEdge
5320 * @param GPT_ICFilter Specifies the Input Capture Filter.
5321 * This parameter must be a value between 0x00 and 0x0F.
5322 * @retval None
5323 */
GPT_TI2_ConfigInputStage(GPT_TypeDef * TIMx,uint32_t GPT_ICPolarity,uint32_t GPT_ICFilter)5324 static void GPT_TI2_ConfigInputStage(GPT_TypeDef *TIMx, uint32_t GPT_ICPolarity, uint32_t GPT_ICFilter)
5325 {
5326 uint32_t tmpccmr1 = 0U;
5327 uint32_t tmpccer = 0U;
5328
5329 /* Disable the Channel 2: Reset the CC2E Bit */
5330 TIMx->CCER &= ~GPT_CCER_CC2E;
5331 tmpccmr1 = TIMx->CCMR1;
5332 tmpccer = TIMx->CCER;
5333
5334 /* Set the filter */
5335 tmpccmr1 &= ~GPT_CCMR1_IC2F;
5336 tmpccmr1 |= (GPT_ICFilter << 12U);
5337
5338 /* Select the Polarity and set the CC2E Bit */
5339 tmpccer &= ~(GPT_CCER_CC2P | GPT_CCER_CC2NP);
5340 tmpccer |= (GPT_ICPolarity << 4U);
5341
5342 /* Write to TIMx CCMR1 and CCER registers */
5343 TIMx->CCMR1 = tmpccmr1 ;
5344 TIMx->CCER = tmpccer;
5345 }
5346
5347 /**
5348 * @brief Configure the TI3 as Input.
5349 * @param TIMx to select the TIM peripheral
5350 * @param GPT_ICPolarity The Input Polarity.
5351 * This parameter can be one of the following values:
5352 * @arg GPT_ICPolarity_Rising
5353 * @arg GPT_ICPolarity_Falling
5354 * @arg GPT_ICPolarity_BothEdge
5355 * @param GPT_ICSelection specifies the input to be used.
5356 * This parameter can be one of the following values:
5357 * @arg GPT_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
5358 * @arg GPT_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
5359 * @arg GPT_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
5360 * @param GPT_ICFilter Specifies the Input Capture Filter.
5361 * This parameter must be a value between 0x00 and 0x0F.
5362 * @note GPT_ICFilter and GPT_ICPolarity are not used in INDIRECT mode as TI4FP3
5363 * (on channel4 path) is used as the input signal. Therefore CCMR2 must be
5364 * protected against un-initialized filter and polarity values.
5365 * @retval None
5366 */
GPT_TI3_SetConfig(GPT_TypeDef * TIMx,uint32_t GPT_ICPolarity,uint32_t GPT_ICSelection,uint32_t GPT_ICFilter)5367 static void GPT_TI3_SetConfig(GPT_TypeDef *TIMx, uint32_t GPT_ICPolarity, uint32_t GPT_ICSelection,
5368 uint32_t GPT_ICFilter)
5369 {
5370 uint32_t tmpccmr2 = 0U;
5371 uint32_t tmpccer = 0U;
5372
5373 /* Disable the Channel 3: Reset the CC3E Bit */
5374 TIMx->CCER &= ~GPT_CCER_CC3E;
5375 tmpccmr2 = TIMx->CCMR2;
5376 tmpccer = TIMx->CCER;
5377
5378 /* Select the Input */
5379 tmpccmr2 &= ~GPT_CCMR2_CC3S;
5380 tmpccmr2 |= GPT_ICSelection;
5381
5382 /* Set the filter */
5383 tmpccmr2 &= ~GPT_CCMR2_IC3F;
5384 tmpccmr2 |= ((GPT_ICFilter << 4U) & GPT_CCMR2_IC3F);
5385
5386 /* Select the Polarity and set the CC3E Bit */
5387 tmpccer &= ~(GPT_CCER_CC3P | GPT_CCER_CC3NP);
5388 tmpccer |= ((GPT_ICPolarity << 8U) & (GPT_CCER_CC3P | GPT_CCER_CC3NP));
5389
5390 /* Write to TIMx CCMR2 and CCER registers */
5391 TIMx->CCMR2 = tmpccmr2;
5392 TIMx->CCER = tmpccer;
5393 }
5394
5395 /**
5396 * @brief Configure the TI4 as Input.
5397 * @param TIMx to select the TIM peripheral
5398 * @param GPT_ICPolarity The Input Polarity.
5399 * This parameter can be one of the following values:
5400 * @arg GPT_ICPolarity_Rising
5401 * @arg GPT_ICPolarity_Falling
5402 * @arg GPT_ICPolarity_BothEdge
5403 * @param GPT_ICSelection specifies the input to be used.
5404 * This parameter can be one of the following values:
5405 * @arg GPT_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
5406 * @arg GPT_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
5407 * @arg GPT_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
5408 * @param GPT_ICFilter Specifies the Input Capture Filter.
5409 * This parameter must be a value between 0x00 and 0x0F.
5410 * @note GPT_ICFilter and GPT_ICPolarity are not used in INDIRECT mode as TI3FP4
5411 * (on channel3 path) is used as the input signal. Therefore CCMR2 must be
5412 * protected against un-initialized filter and polarity values.
5413 * @retval None
5414 */
GPT_TI4_SetConfig(GPT_TypeDef * TIMx,uint32_t GPT_ICPolarity,uint32_t GPT_ICSelection,uint32_t GPT_ICFilter)5415 static void GPT_TI4_SetConfig(GPT_TypeDef *TIMx, uint32_t GPT_ICPolarity, uint32_t GPT_ICSelection,
5416 uint32_t GPT_ICFilter)
5417 {
5418 uint32_t tmpccmr2 = 0U;
5419 uint32_t tmpccer = 0U;
5420
5421 /* Disable the Channel 4: Reset the CC4E Bit */
5422 TIMx->CCER &= ~GPT_CCER_CC4E;
5423 tmpccmr2 = TIMx->CCMR2;
5424 tmpccer = TIMx->CCER;
5425
5426 /* Select the Input */
5427 tmpccmr2 &= ~GPT_CCMR2_CC4S;
5428 tmpccmr2 |= (GPT_ICSelection << 8U);
5429
5430 /* Set the filter */
5431 tmpccmr2 &= ~GPT_CCMR2_IC4F;
5432 tmpccmr2 |= ((GPT_ICFilter << 12U) & GPT_CCMR2_IC4F);
5433
5434 /* Select the Polarity and set the CC4E Bit */
5435 tmpccer &= ~(GPT_CCER_CC4P | GPT_CCER_CC4NP);
5436 tmpccer |= ((GPT_ICPolarity << 12U) & (GPT_CCER_CC4P | GPT_CCER_CC4NP));
5437
5438 /* Write to TIMx CCMR2 and CCER registers */
5439 TIMx->CCMR2 = tmpccmr2;
5440 TIMx->CCER = tmpccer ;
5441 }
5442
5443 /**
5444 * @brief Selects the Input Trigger source
5445 * @param TIMx to select the TIM peripheral
5446 * @param GPT_ITRx The Input Trigger source.
5447 * This parameter can be one of the following values:
5448 * @arg GPT_TS_ITR0: Internal Trigger 0
5449 * @arg GPT_TS_ITR1: Internal Trigger 1
5450 * @arg GPT_TS_ITR2: Internal Trigger 2
5451 * @arg GPT_TS_ITR3: Internal Trigger 3
5452 * @arg GPT_TS_TI1F_ED: TI1 Edge Detector
5453 * @arg GPT_TS_TI1FP1: Filtered Timer Input 1
5454 * @arg GPT_TS_TI2FP2: Filtered Timer Input 2
5455 * @arg GPT_TS_ETRF: External Trigger input
5456 * @retval None
5457 */
GPT_ITRx_SetConfig(GPT_TypeDef * TIMx,uint16_t GPT_ITRx)5458 static void GPT_ITRx_SetConfig(GPT_TypeDef *TIMx, uint16_t GPT_ITRx)
5459 {
5460 uint32_t tmpsmcr = 0U;
5461
5462 /* Get the TIMx SMCR register value */
5463 tmpsmcr = TIMx->SMCR;
5464 /* Reset the TS Bits */
5465 tmpsmcr &= ~GPT_SMCR_TS;
5466 /* Set the Input Trigger source and the slave mode*/
5467 tmpsmcr |= GPT_ITRx | GPT_SLAVEMODE_EXTERNAL1;
5468 /* Write to TIMx SMCR */
5469 TIMx->SMCR = tmpsmcr;
5470 }
5471
5472 /**
5473 * @brief Configures the TIMx External Trigger (ETR).
5474 * @param TIMx to select the TIM peripheral
5475 * @param GPT_ExtTRGPrescaler The external Trigger Prescaler.
5476 * This parameter can be one of the following values:
5477 * @arg GPT_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
5478 * @arg GPT_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
5479 * @arg GPT_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
5480 * @arg GPT_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
5481 * @param GPT_ExtTRGPolarity The external Trigger Polarity.
5482 * This parameter can be one of the following values:
5483 * @arg GPT_ETRPOLARITY_INVERTED : active low or falling edge active.
5484 * @arg GPT_ETRPOLARITY_NONINVERTED : active high or rising edge active.
5485 * @param ExtTRGFilter External Trigger Filter.
5486 * This parameter must be a value between 0x00 and 0x0F
5487 * @retval None
5488 */
GPT_ETR_SetConfig(GPT_TypeDef * TIMx,uint32_t GPT_ExtTRGPrescaler,uint32_t GPT_ExtTRGPolarity,uint32_t ExtTRGFilter)5489 static void GPT_ETR_SetConfig(GPT_TypeDef *TIMx, uint32_t GPT_ExtTRGPrescaler,
5490 uint32_t GPT_ExtTRGPolarity, uint32_t ExtTRGFilter)
5491 {
5492 uint32_t tmpsmcr = 0U;
5493
5494 tmpsmcr = TIMx->SMCR;
5495
5496 /* Reset the ETR Bits */
5497 tmpsmcr &= ~(GPT_SMCR_ETF | GPT_SMCR_ETPS | GPT_SMCR_ECE | GPT_SMCR_ETP);
5498
5499 /* Set the Prescaler, the Filter value and the Polarity */
5500 tmpsmcr |= (uint32_t)(GPT_ExtTRGPrescaler | (GPT_ExtTRGPolarity | (ExtTRGFilter << 8)));
5501
5502 /* Write to TIMx SMCR */
5503 TIMx->SMCR = tmpsmcr;
5504 }
5505
5506 /**
5507 * @}
5508 */
5509
5510 /**
5511 * @brief Hall commutation changed callback in non blocking mode
5512 * @param htim pointer to a TIM_HandleTypeDef structure that contains
5513 * the configuration information for TIM module.
5514 * @retval None
5515 */
HAL_TIMEx_CommutationCallback(GPT_HandleTypeDef * htim)5516 __weak void HAL_TIMEx_CommutationCallback(GPT_HandleTypeDef *htim)
5517 {
5518 /* Prevent unused argument(s) compilation warning */
5519 UNUSED(htim);
5520 /* NOTE : This function Should not be modified, when the callback is needed,
5521 the HAL_TIMEx_CommutationCallback could be implemented in the user file
5522 */
5523 }
5524
5525 /**
5526 * @brief Hall Break detection callback in non blocking mode
5527 * @param htim pointer to a TIM_HandleTypeDef structure that contains
5528 * the configuration information for TIM module.
5529 * @retval None
5530 */
HAL_TIMEx_BreakCallback(GPT_HandleTypeDef * htim)5531 __weak void HAL_TIMEx_BreakCallback(GPT_HandleTypeDef *htim)
5532 {
5533 /* Prevent unused argument(s) compilation warning */
5534 UNUSED(htim);
5535 /* NOTE : This function Should not be modified, when the callback is needed,
5536 the HAL_TIMEx_BreakCallback could be implemented in the user file
5537 */
5538 }
5539
5540
5541 #endif /* HAL_GPT_MODULE_ENABLED */
5542 /**
5543 * @}
5544 */
5545
5546 /**
5547 * @}
5548 */
