1 /*
2 * SPDX-FileCopyrightText: 2016 STMicroelectronics
3 * SPDX-FileCopyrightText: 2019-2025 SiFli Technologies(Nanjing) Co., Ltd
4 *
5 * SPDX-License-Identifier: BSD-3-Clause AND Apache-2.0
6 */
7
8 #include "bf0_hal.h"
9
10 /** @addtogroup BF0_HAL_Driver
11 * @{
12 */
13
14 /** @addtogroup CORTEX
15 * @{
16 */
17
18 #if defined(HAL_CORTEX_MODULE_ENABLED)||defined(_SIFLI_DOXYGEN_)
19
20 /* Private types -------------------------------------------------------------*/
21 /* Private variables ---------------------------------------------------------*/
22 /* Private constants ---------------------------------------------------------*/
23 /* Private macros ------------------------------------------------------------*/
24 /* Private functions ---------------------------------------------------------*/
25 /* Exported functions --------------------------------------------------------*/
26
27 /** @addtogroup CORTEX_Exported_Functions
28 * @{
29 */
30
31
32 /** @addtogroup CORTEX_Exported_Functions_Group1
33 * @brief Initialization and Configuration functions
34 *
35 @verbatim
36 ==============================================================================
37 ##### Initialization and Configuration functions #####
38 ==============================================================================
39 [..]
40 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
41 SysTick functionalities
42
43 @endverbatim
44 * @{
45 */
46
47
48 /**
49 * @brief Set the priority grouping field (pre-emption priority and subpriority)
50 * using the required unlock sequence.
51 * @param PriorityGroup: The priority grouping bits length.
52 * This parameter can be one of the following values:
53 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
54 * 4 bits for subpriority
55 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
56 * 3 bits for subpriority
57 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
58 * 2 bits for subpriority
59 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
60 * 1 bit for subpriority
61 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
62 * 0 bit for subpriority
63 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
64 * The pending IRQ priority will be managed only by the subpriority.
65 * @retval None
66 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)67 __HAL_ROM_USED void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
68 {
69 /* Check the parameters */
70 HAL_ASSERT(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
71
72 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
73 NVIC_SetPriorityGrouping(PriorityGroup);
74 }
75
76 /**
77 * @brief Set the priority of an interrupt.
78 * @param IRQn: External interrupt number.
79 * This parameter can be an enumerator of IRQn_Type enumeration
80 * @param PreemptPriority: The pre-emption priority for the IRQn channel.
81 * This parameter can be a value between 0 and 15
82 * A lower priority value indicates a higher priority
83 * @param SubPriority: the subpriority level for the IRQ channel.
84 * This parameter can be a value between 0 and 15
85 * A lower priority value indicates a higher priority.
86 * @retval None
87 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)88 __HAL_ROM_USED void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
89 {
90 uint32_t prioritygroup = 0x00;
91
92 /* Check the parameters */
93 HAL_ASSERT(IS_NVIC_SUB_PRIORITY(SubPriority));
94 HAL_ASSERT(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
95
96 prioritygroup = NVIC_GetPriorityGrouping();
97
98 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
99 }
100
101 /**
102 * @brief Enable a device specific interrupt in the NVIC interrupt controller.
103 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
104 * function should be called before.
105 * @param IRQn External interrupt number.
106 * This parameter can be an enumerator of IRQn_Type enumeration
107 * @retval None
108 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)109 __HAL_ROM_USED void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
110 {
111 /* Check the parameters */
112 HAL_ASSERT(IS_NVIC_DEVICE_IRQ(IRQn));
113
114 /* Enable interrupt */
115 NVIC_EnableIRQ(IRQn);
116 }
117
118 /**
119 * @brief Disable a device specific interrupt in the NVIC interrupt controller.
120 * @param IRQn External interrupt number.
121 * This parameter can be an enumerator of IRQn_Type enumeration
122 * @retval None
123 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)124 __HAL_ROM_USED void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
125 {
126 /* Check the parameters */
127 HAL_ASSERT(IS_NVIC_DEVICE_IRQ(IRQn));
128
129 /* Disable interrupt */
130 NVIC_DisableIRQ(IRQn);
131 }
132
133 /**
134 * @brief Initiate a system reset request to reset the MCU.
135 * @retval None
136 */
HAL_NVIC_SystemReset(void)137 __HAL_ROM_USED void HAL_NVIC_SystemReset(void)
138 {
139 /* System Reset */
140 NVIC_SystemReset();
141 }
142
143 /**
144 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
145 * Counter is in free running mode to generate periodic interrupts.
146 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
147 * @retval status: - 0 Function succeeded.
148 * - 1 Function failed.
149 */
HAL_SYSTICK_Config(uint32_t TicksNumb)150 __HAL_ROM_USED uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
151 {
152 return SysTick_Config(TicksNumb);
153 }
154 /**
155 * @}
156 */
157
158 /** @addtogroup CORTEX_Exported_Functions_Group2
159 * @brief Cortex control functions
160 *
161 @verbatim
162 ==============================================================================
163 ##### Peripheral Control functions #####
164 ==============================================================================
165 [..]
166 This subsection provides a set of functions allowing to control the CORTEX
167 (NVIC, SYSTICK, MPU) functionalities.
168
169
170 @endverbatim
171 * @{
172 */
173
174 /**
175 * @brief Get the priority grouping field from the NVIC Interrupt Controller.
176 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
177 */
HAL_NVIC_GetPriorityGrouping(void)178 __HAL_ROM_USED uint32_t HAL_NVIC_GetPriorityGrouping(void)
179 {
180 /* Get the PRIGROUP[10:8] field value */
181 return NVIC_GetPriorityGrouping();
182 }
183
184 /**
185 * @brief Get the priority of an interrupt.
186 * @param IRQn: External interrupt number.
187 * This parameter can be an enumerator of IRQn_Type enumeration
188 * @param PriorityGroup: the priority grouping bits length.
189 * This parameter can be one of the following values:
190 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
191 * 4 bits for subpriority
192 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
193 * 3 bits for subpriority
194 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
195 * 2 bits for subpriority
196 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
197 * 1 bit for subpriority
198 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
199 * 0 bit for subpriority
200 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
201 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
202 * @retval None
203 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)204 __HAL_ROM_USED void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
205 {
206 /* Check the parameters */
207 HAL_ASSERT(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
208 /* Get priority for Cortex-M system or device specific interrupts */
209 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
210 }
211
212 /**
213 * @brief Set Pending bit of an external interrupt.
214 * @param IRQn External interrupt number
215 * This parameter can be an enumerator of IRQn_Type enumeration
216 * @retval None
217 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)218 __HAL_ROM_USED void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
219 {
220 /* Check the parameters */
221 HAL_ASSERT(IS_NVIC_DEVICE_IRQ(IRQn));
222
223 /* Set interrupt pending */
224 NVIC_SetPendingIRQ(IRQn);
225 }
226
227 /**
228 * @brief Get Pending Interrupt (read the pending register in the NVIC
229 * and return the pending bit for the specified interrupt).
230 * @param IRQn External interrupt number.
231 * This parameter can be an enumerator of IRQn_Type enumeration
232 * @retval status: - 0 Interrupt status is not pending.
233 * - 1 Interrupt status is pending.
234 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)235 __HAL_ROM_USED uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
236 {
237 /* Check the parameters */
238 HAL_ASSERT(IS_NVIC_DEVICE_IRQ(IRQn));
239
240 /* Return 1 if pending else 0 */
241 return NVIC_GetPendingIRQ(IRQn);
242 }
243
244 /**
245 * @brief Clear the pending bit of an external interrupt.
246 * @param IRQn External interrupt number.
247 * This parameter can be an enumerator of IRQn_Type enumeration
248 * @retval None
249 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)250 __HAL_ROM_USED void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
251 {
252 /* Check the parameters */
253 HAL_ASSERT(IS_NVIC_DEVICE_IRQ(IRQn));
254
255 /* Clear pending interrupt */
256 NVIC_ClearPendingIRQ(IRQn);
257 }
258
259 /**
260 * @brief Get active interrupt (read the active register in NVIC and return the active bit).
261 * @param IRQn External interrupt number
262 * This parameter can be an enumerator of IRQn_Type enumeration
263 * @retval status: - 0 Interrupt status is not actived.
264 * - 1 Interrupt status is actived.
265 */
HAL_NVIC_GetActive(IRQn_Type IRQn)266 __HAL_ROM_USED uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
267 {
268 /* Check the parameters */
269 HAL_ASSERT(IS_NVIC_DEVICE_IRQ(IRQn));
270
271 /* Return 1 if active else 0 */
272 return NVIC_GetActive(IRQn);
273 }
274
275 /**
276 * @brief Get enable interrupt (read the enable register in NVIC and return the enable bit).
277 * @param IRQn External interrupt number
278 * This parameter can be an enumerator of IRQn_Type enumeration
279 * @retval status: - 0 Interrupt is not enabled.
280 * - 1 Interrupt is enabled.
281 */
HAL_NVIC_GetEnableIRQ(IRQn_Type IRQn)282 __HAL_ROM_USED uint32_t HAL_NVIC_GetEnableIRQ(IRQn_Type IRQn)
283 {
284 /* Check the parameters */
285 HAL_ASSERT(IS_NVIC_DEVICE_IRQ(IRQn));
286
287 /* Return 1 if enable else 0 */
288 return NVIC_GetEnableIRQ(IRQn);
289 }
290
291 /**
292 * @brief Configure the SysTick clock source.
293 * @param CLKSource: specifies the SysTick clock source.
294 * This parameter can be one of the following values:
295 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
296 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
297 * @retval None
298 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)299 __HAL_ROM_USED void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
300 {
301 /* Check the parameters */
302 HAL_ASSERT(IS_SYSTICK_CLK_SOURCE(CLKSource));
303 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
304 {
305 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
306 }
307 else
308 {
309 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
310 }
311 }
312
313 /**
314 * @brief Handle SYSTICK interrupt request.
315 * @retval None
316 */
HAL_SYSTICK_IRQHandler(void)317 __HAL_ROM_USED void HAL_SYSTICK_IRQHandler(void)
318 {
319 HAL_SYSTICK_Callback();
320 }
321
322 /**
323 * @brief SYSTICK callback.
324 * @retval None
325 */
HAL_SYSTICK_Callback(void)326 __weak void HAL_SYSTICK_Callback(void)
327 {
328 /* NOTE : This function should not be modified, when the callback is needed,
329 the HAL_SYSTICK_Callback could be implemented in the user file
330 */
331 }
332
333 #if (__MPU_PRESENT == 1)
334 /**
335 * @brief Disable the MPU.
336 * @retval None
337 */
HAL_MPU_Disable(void)338 __HAL_ROM_USED void HAL_MPU_Disable(void)
339 {
340 /* Make sure outstanding transfers are done */
341 __DMB();
342
343 /* Disable fault exceptions */
344 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
345
346 /* Disable the MPU and clear the control register*/
347 MPU->CTRL = 0U;
348 }
349
350 /**
351 * @brief Enable the MPU.
352 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
353 * NMI, FAULTMASK and privileged accessto the default memory
354 * This parameter can be one of the following values:
355 * @arg MPU_HFNMI_PRIVDEF_NONE
356 * @arg MPU_HARDFAULT_NMI
357 * @arg MPU_PRIVILEGED_DEFAULT
358 * @arg MPU_HFNMI_PRIVDEF
359 * @retval None
360 */
HAL_MPU_Enable(uint32_t MPU_Control)361 __HAL_ROM_USED void HAL_MPU_Enable(uint32_t MPU_Control)
362 {
363 /* Enable the MPU */
364 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
365
366 /* Enable fault exceptions */
367 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
368
369 /* Ensure MPU settings take effects */
370 __DSB();
371 __ISB();
372 }
373
374 /**
375 * @brief Initialize and configure the Region and the memory to be protected.
376 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
377 * the initialization and configuration information.
378 * @retval None
379 */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_Init)380 __HAL_ROM_USED void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
381 {
382 /* Check the parameters */
383 HAL_ASSERT(IS_MPU_REGION_NUMBER(MPU_Init->Number));
384 HAL_ASSERT(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
385
386 /* Set the Region number */
387 MPU->RNR = MPU_Init->Number;
388
389 if ((MPU_Init->Enable) != RESET)
390 {
391 /* Check the parameters */
392 HAL_ASSERT(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
393 HAL_ASSERT(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
394 HAL_ASSERT(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
395 HAL_ASSERT(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
396 HAL_ASSERT(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
397 HAL_ASSERT(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
398 HAL_ASSERT(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
399 HAL_ASSERT(IS_MPU_REGION_SIZE(MPU_Init->Size));
400
401
402 #if 0
403 MPU->RBAR = MPU_Init->BaseAddress;
404 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
405 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
406 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
407 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
408 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
409 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
410 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
411 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
412 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
413 #endif
414 }
415 else
416 {
417 // MPU->RBAR = 0x00;
418 // MPU->RASR = 0x00;
419 }
420 }
421 #endif /* __MPU_PRESENT */
422
423 /**
424 * @}
425 */
426
427 /**
428 * @}
429 */
430
431 #endif /* HAL_CORTEX_MODULE_ENABLED */
432 /**
433 * @}
434 */
435
436 /**
437 * @}
438 */
