1 /*
2 * SPDX-FileCopyrightText: 2019-2025 SiFli Technologies(Nanjing) Co., Ltd
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /* Includes ------------------------------------------------------------------*/
8 #include "bf0_hal.h"
9
10 #if defined(HAL_AUDCODEC_MODULE_ENABLED)||defined(_SIFLI_DOXYGEN_)
11 //#define DBG_LEVEL DBG_LOG
12 //#define LOG_TAG "hal.audcodec"
13 //#include "drv_log.h"
14
15
16 static void HAL_AUDCODEC_DMA_Init(DMA_HandleTypeDef *hdma, uint8_t from_mem);
17
18 static void AUDCODEC_DMATxCplt(DMA_HandleTypeDef *hdma);
19 static void AUDCODEC_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
20 static void AUDCODEC_DMARxCplt(DMA_HandleTypeDef *hdma);
21 static void AUDCODEC_DMAHalfRxCplt(DMA_HandleTypeDef *hdma);
22 static void AUDCODEC_DMAError(DMA_HandleTypeDef *hdma);
23
24 uint8_t g_pll_state = 0;
25 uint8_t g_pll_freq_type = 0;
26 static uint16_t pll_cfg2_reset = 0;
27
set_pll_state(uint8_t state)28 void set_pll_state(uint8_t state)
29 {
30 g_pll_state = state;
31 }
get_pll_state()32 uint8_t get_pll_state()
33 {
34 return g_pll_state;
35 }
set_pll_freq_type(uint8_t type)36 void set_pll_freq_type(uint8_t type)
37 {
38 g_pll_freq_type = type;
39 }
get_pll_freq_type()40 uint8_t get_pll_freq_type()
41 {
42 return g_pll_freq_type;
43 }
44 // need updata drv_audcodec if modify this function
updata_pll_freq(uint8_t type)45 __weak int updata_pll_freq(uint8_t type) //type 0: 16k 1024 series 1:44.1k 1024 series 2:16k 1000 series 3: 44.1k 1000 series
46 {
47 hwp_audcodec->PLL_CFG2 |= AUDCODEC_PLL_CFG2_RSTB;
48 // wait 50us
49 HAL_Delay_us(50);
50 if (0 == type)// set pll to 49.152M [(fcw+3)+sdin/2^20]*6M
51 {
52 hwp_audcodec->PLL_CFG3 = (201327 << AUDCODEC_PLL_CFG3_SDIN_Pos) |
53 (5 << AUDCODEC_PLL_CFG3_FCW_Pos) |
54 (0 << AUDCODEC_PLL_CFG3_SDM_UPDATE_Pos) |
55 (1 << AUDCODEC_PLL_CFG3_SDMIN_BYPASS_Pos) |
56 (0 << AUDCODEC_PLL_CFG3_SDM_MODE_Pos) |
57 (0 << AUDCODEC_PLL_CFG3_EN_SDM_DITHER_Pos) |
58 (0 << AUDCODEC_PLL_CFG3_SDM_DITHER_Pos) |
59 (1 << AUDCODEC_PLL_CFG3_EN_SDM_Pos) |
60 (0 << AUDCODEC_PLL_CFG3_SDMCLK_POL_Pos);
61 }
62 else if (1 == type)// set pll to 45.1584M
63 {
64
65 hwp_audcodec->PLL_CFG3 = (551970 << AUDCODEC_PLL_CFG3_SDIN_Pos) |
66 (4 << AUDCODEC_PLL_CFG3_FCW_Pos) |
67 (0 << AUDCODEC_PLL_CFG3_SDM_UPDATE_Pos) |
68 (1 << AUDCODEC_PLL_CFG3_SDMIN_BYPASS_Pos) |
69 (0 << AUDCODEC_PLL_CFG3_SDM_MODE_Pos) |
70 (0 << AUDCODEC_PLL_CFG3_EN_SDM_DITHER_Pos) |
71 (0 << AUDCODEC_PLL_CFG3_SDM_DITHER_Pos) |
72 (1 << AUDCODEC_PLL_CFG3_EN_SDM_Pos) |
73 (0 << AUDCODEC_PLL_CFG3_SDMCLK_POL_Pos);
74 }
75 else if (3 == type)// set pll to 44.1M
76 {
77
78 hwp_audcodec->PLL_CFG3 = (0x5999A << AUDCODEC_PLL_CFG3_SDIN_Pos) |
79 (4 << AUDCODEC_PLL_CFG3_FCW_Pos) |
80 (0 << AUDCODEC_PLL_CFG3_SDM_UPDATE_Pos) |
81 (1 << AUDCODEC_PLL_CFG3_SDMIN_BYPASS_Pos) |
82 (0 << AUDCODEC_PLL_CFG3_SDM_MODE_Pos) |
83 (0 << AUDCODEC_PLL_CFG3_EN_SDM_DITHER_Pos) |
84 (0 << AUDCODEC_PLL_CFG3_SDM_DITHER_Pos) |
85 (1 << AUDCODEC_PLL_CFG3_EN_SDM_Pos) |
86 (0 << AUDCODEC_PLL_CFG3_SDMCLK_POL_Pos);
87 }
88 else
89 {
90 //RT_ASSERT(0);
91 }
92 hwp_audcodec->PLL_CFG3 |= AUDCODEC_PLL_CFG3_SDM_UPDATE;
93 hwp_audcodec->PLL_CFG3 &= ~AUDCODEC_PLL_CFG3_SDMIN_BYPASS;
94 hwp_audcodec->PLL_CFG2 &= ~AUDCODEC_PLL_CFG2_RSTB;
95 // wait 50us
96 HAL_Delay_us(50);
97 hwp_audcodec->PLL_CFG2 |= AUDCODEC_PLL_CFG2_RSTB;
98 // check pll lock
99 //wait(2500);
100 HAL_Delay_us(50);
101
102 hwp_audcodec->PLL_CFG1 |= AUDCODEC_PLL_CFG1_CSD_EN | AUDCODEC_PLL_CFG1_CSD_RST;
103 HAL_Delay_us(50);
104 hwp_audcodec->PLL_CFG1 &= ~AUDCODEC_PLL_CFG1_CSD_RST;
105 if (hwp_audcodec->PLL_STAT & AUDCODEC_PLL_STAT_UNLOCK_Msk)
106 {
107 //rt_kprintf("pll lock fail! freq_type:%d\n", type);
108 return -1;
109 }
110 else
111 {
112 //rt_kprintf("pll lock! freq_type:%d\n", type);
113 hwp_audcodec->PLL_CFG1 &= ~AUDCODEC_PLL_CFG1_CSD_EN;
114 set_pll_freq_type(type);
115 }
116 return 0;
117 }
118
119 /**
120 * @brief enable PLL function
121 * @param freq - frequency
122 * @param type - 0:1024 series, 1:1000 series
123 * @return
124 */
bf0_enable_pll(uint32_t freq,uint8_t type)125 __weak int bf0_enable_pll(uint32_t freq, uint8_t type)// need updata drv_audcodec if modify this function
126 {
127 uint8_t freq_type;
128 uint8_t test_result = -1;
129 uint32_t pll_cnt;
130 uint32_t xtal_cnt;
131 uint32_t fc_vco;
132 uint32_t fc_vco_min;
133 uint32_t fc_vco_max;
134 uint32_t delta_cnt=0;
135 uint32_t delta_cnt_min=0;
136 uint32_t delta_cnt_max=0;
137 uint32_t delta_fc_vco;
138 uint32_t target_cnt = 1838;
139
140 fc_vco = 16;
141 delta_fc_vco = 8;
142 test_result = 0;
143
144 freq_type = type << 1;
145 if ((freq == 44100) || (freq == 22050) || (freq == 11025))
146 {
147 freq_type += 1;
148 }
149
150 //rt_kprintf("PLL_ENABLE pll_state:%d, freq_type:%d\n", get_pll_state(), freq_type);
151
152 if (0 == get_pll_state())
153 {
154 hwp_pmuc->HXT_CR1 |= PMUC_HXT_CR1_BUF_AUD_EN;
155 hwp_hpsys_rcc->ENR2 |= HPSYS_RCC_ENR2_AUDCODEC;
156 //hwp_lpsys_rcc->ENR1 |= LPSYS_RCC_ENR1_AUDCODEC;
157
158 //-----------------step 2------------------//
159 // turn on bandgap
160 // turn on BG sample clock
161 //hwp_audcodec->BG_CFG1 = 48000;
162 //hwp_audcodec->BG_CFG2 = 48000000;
163 // turn on bandgap
164 hwp_audcodec->BG_CFG0 &= ~AUDCODEC_BG_CFG0_EN_RCFLT;
165 hwp_audcodec->BG_CFG0 |= AUDCODEC_BG_CFG0_EN;
166 HAL_Delay_us(100);
167 #if 1
168 hwp_audcodec->BG_CFG0 &= ~AUDCODEC_BG_CFG0_EN_SMPL; //noise pop
169 #else
170 hwp_audcodec->BG_CFG0 |= AUDCODEC_BG_CFG0_EN_SMPL; //noise pop
171 #endif
172
173 //-----------------step 3------------------//
174 // pll calibration
175 // wait 100us
176 //wait(5000);
177 HAL_Delay_us(100);
178
179 hwp_audcodec->PLL_CFG0 |= AUDCODEC_PLL_CFG0_EN_IARY;
180 hwp_audcodec->PLL_CFG0 |= AUDCODEC_PLL_CFG0_EN_VCO;
181 hwp_audcodec->PLL_CFG0 |= AUDCODEC_PLL_CFG0_EN_ANA;
182 hwp_audcodec->PLL_CFG0 &= ~AUDCODEC_PLL_CFG0_ICP_SEL_Msk;
183 hwp_audcodec->PLL_CFG0 |= (8 << AUDCODEC_PLL_CFG0_ICP_SEL_Pos);
184 hwp_audcodec->PLL_CFG2 |= AUDCODEC_PLL_CFG2_EN_DIG;
185 hwp_audcodec->PLL_CFG3 |= AUDCODEC_PLL_CFG3_EN_SDM;
186 hwp_audcodec->PLL_CFG4 |= AUDCODEC_PLL_CFG4_EN_CLK_DIG;
187 hwp_audcodec->PLL_CFG1 = (3 << AUDCODEC_PLL_CFG1_R3_SEL_Pos) |
188 (1 << AUDCODEC_PLL_CFG1_RZ_SEL_Pos) |
189 (3 << AUDCODEC_PLL_CFG1_C2_SEL_Pos) |
190 (6 << AUDCODEC_PLL_CFG1_CZ_SEL_Pos) |
191 (0 << AUDCODEC_PLL_CFG1_CSD_RST_Pos) |
192 (0 << AUDCODEC_PLL_CFG1_CSD_EN_Pos);
193 // wait 50us
194 //wait(2500);
195 HAL_Delay_us(50);
196 // VCO freq calibration
197 hwp_audcodec->PLL_CFG0 |= AUDCODEC_PLL_CFG0_OPEN;
198 hwp_audcodec->PLL_CFG2 |= AUDCODEC_PLL_CFG2_EN_LF_VCIN;
199 hwp_audcodec->PLL_CAL_CFG = (0 << AUDCODEC_PLL_CAL_CFG_EN_Pos) |
200 (2000 << AUDCODEC_PLL_CAL_CFG_LEN_Pos);
201 // setup calibration and run
202 // target pll_cnt = ceil(46MHz/48MHz*2000)+1 = 1918
203 // target difference between pll_cnt and xtal_cnt should be less than 1
204 while (delta_fc_vco != 0)
205 {
206 hwp_audcodec->PLL_CFG0 &= ~AUDCODEC_PLL_CFG0_FC_VCO;
207 hwp_audcodec->PLL_CFG0 |= (fc_vco << AUDCODEC_PLL_CFG0_FC_VCO_Pos);
208 hwp_audcodec->PLL_CAL_CFG |= AUDCODEC_PLL_CAL_CFG_EN;
209 while (!(hwp_audcodec->PLL_CAL_CFG & AUDCODEC_PLL_CAL_CFG_DONE_Msk));
210 pll_cnt = (hwp_audcodec->PLL_CAL_RESULT >> AUDCODEC_PLL_CAL_RESULT_PLL_CNT_Pos);
211 xtal_cnt = (hwp_audcodec->PLL_CAL_RESULT & AUDCODEC_PLL_CAL_RESULT_XTAL_CNT_Msk);
212 hwp_audcodec->PLL_CAL_CFG &= ~AUDCODEC_PLL_CAL_CFG_EN;
213 if (pll_cnt < target_cnt)
214 {
215 fc_vco = fc_vco + delta_fc_vco;
216 delta_cnt = target_cnt - pll_cnt;
217 }
218 else if (pll_cnt > target_cnt)
219 {
220 fc_vco = fc_vco - delta_fc_vco;
221 delta_cnt = pll_cnt - target_cnt;
222 }
223 delta_fc_vco = delta_fc_vco >> 1;
224 }
225 //rt_kprintf("call par CFG1(%x)\r\n", hwp_audcodec->PLL_CFG1);
226 fc_vco_min = fc_vco - 1;
227 if (fc_vco == 31)
228 {
229 fc_vco_max = fc_vco;
230 }
231 else
232 {
233 fc_vco_max = fc_vco + 1;
234 }
235
236 hwp_audcodec->PLL_CFG0 &= ~AUDCODEC_PLL_CFG0_FC_VCO;
237 hwp_audcodec->PLL_CFG0 |= (fc_vco_min << AUDCODEC_PLL_CFG0_FC_VCO_Pos);
238 hwp_audcodec->PLL_CAL_CFG |= AUDCODEC_PLL_CAL_CFG_EN;
239 //rt_kprintf("fc %d, xtal %d, pll %d\r\n", fc_vco, xtal_cnt, pll_cnt);
240 while (!(hwp_audcodec->PLL_CAL_CFG & AUDCODEC_PLL_CAL_CFG_DONE_Msk));
241 pll_cnt = (hwp_audcodec->PLL_CAL_RESULT >> AUDCODEC_PLL_CAL_RESULT_PLL_CNT_Pos);
242 hwp_audcodec->PLL_CAL_CFG &= ~AUDCODEC_PLL_CAL_CFG_EN;
243 if (pll_cnt < target_cnt)
244 {
245 delta_cnt_min = target_cnt - pll_cnt;
246 }
247 else if (pll_cnt > target_cnt)
248 {
249 delta_cnt_min = pll_cnt - target_cnt;
250 }
251
252 hwp_audcodec->PLL_CFG0 &= ~AUDCODEC_PLL_CFG0_FC_VCO;
253 hwp_audcodec->PLL_CFG0 |= (fc_vco_max << AUDCODEC_PLL_CFG0_FC_VCO_Pos);
254 hwp_audcodec->PLL_CAL_CFG |= AUDCODEC_PLL_CAL_CFG_EN;
255 while (!(hwp_audcodec->PLL_CAL_CFG & AUDCODEC_PLL_CAL_CFG_DONE_Msk));
256 pll_cnt = (hwp_audcodec->PLL_CAL_RESULT >> AUDCODEC_PLL_CAL_RESULT_PLL_CNT_Pos);
257 hwp_audcodec->PLL_CAL_CFG &= ~AUDCODEC_PLL_CAL_CFG_EN;
258 if (pll_cnt < target_cnt)
259 {
260 delta_cnt_max = target_cnt - pll_cnt;
261 }
262 else if (pll_cnt > target_cnt)
263 {
264 delta_cnt_max = pll_cnt - target_cnt;
265 }
266
267 hwp_audcodec->PLL_CFG0 &= ~AUDCODEC_PLL_CFG0_FC_VCO;
268
269 if (delta_cnt_min <= delta_cnt && delta_cnt_min <= delta_cnt_max)
270 {
271 hwp_audcodec->PLL_CFG0 |= (fc_vco_min << AUDCODEC_PLL_CFG0_FC_VCO_Pos);
272 }
273 else if (delta_cnt_max <= delta_cnt && delta_cnt_max <= delta_cnt_min)
274 {
275 hwp_audcodec->PLL_CFG0 |= (fc_vco_max << AUDCODEC_PLL_CFG0_FC_VCO_Pos);
276 }
277 else
278 {
279 hwp_audcodec->PLL_CFG0 |= (fc_vco << AUDCODEC_PLL_CFG0_FC_VCO_Pos);
280 }
281
282 hwp_audcodec->PLL_CFG2 &= ~AUDCODEC_PLL_CFG2_EN_LF_VCIN;
283 hwp_audcodec->PLL_CFG0 &= ~AUDCODEC_PLL_CFG0_OPEN;
284
285 //-----------------step 4------------------//
286 // set pll to 49.152M
287 // wait 50us
288 //wait(2500);
289 HAL_Delay_us(50);
290
291 do
292 {
293 test_result = updata_pll_freq(freq_type);
294 }
295 while (test_result != 0);
296
297 set_pll_state(1);
298 set_pll_freq_type(freq_type);
299 }
300 else if (freq_type != get_pll_freq_type())
301 {
302 do
303 {
304 test_result = updata_pll_freq(freq_type);
305 }
306 while (test_result != 0);
307 set_pll_freq_type(freq_type);
308 }
309
310
311 return test_result;
312 }
bf0_disable_pll()313 __weak void bf0_disable_pll()
314 {
315 HAL_TURN_OFF_PLL();
316 set_pll_state(0);
317 //rt_kprintf("PLL disable\n");
318 }
319
HAL_AUDCODEC_Config_Analog_DACPath(AUDCODE_DAC_CLK_CONFIG_TYPE * cfg)320 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Config_Analog_DACPath(AUDCODE_DAC_CLK_CONFIG_TYPE *cfg)
321 {
322 HAL_DBG_printf("config Aanlog DACPath\n");
323 //-----------------step 5------------------//
324 // turn on refgen
325 // hwp_audcodec->BG_CFG0 &= ~AUDCODEC_BG_CFG0_VREF_SEL;
326 // hwp_audcodec->BG_CFG0 |= (7 << AUDCODEC_BG_CFG0_VREF_SEL_Pos); // AVDD = 3.3V
327 //hwp_audcodec->BG_CFG0 |= (2 << AUDCODEC_BG_CFG0_VREF_SEL_Pos); // AVDD = 1.8V
328 // hwp_audcodec->REFGEN_CFG &= ~AUDCODEC_REFGEN_CFG_EN_CHOP;
329 // hwp_audcodec->REFGEN_CFG |= AUDCODEC_REFGEN_CFG_EN;
330 // hwp_audcodec->PLL_CFG5 = AUDCODEC_PLL_CFG5_EN_CLK_CHOP_BG |
331 // AUDCODEC_PLL_CFG5_EN_CLK_CHOP_REFGEN;
332 // HAL_Delay(2);// wait 2ms
333
334 //-----------------step 6------------------//
335 // turn on hp dac1 and dac2 analog
336 // dac1 and dac2 clock
337 hwp_audcodec->PLL_CFG4 &= ~AUDCODEC_PLL_CFG4_SEL_CLK_DAC;
338 hwp_audcodec->PLL_CFG4 &= ~AUDCODEC_PLL_CFG4_SEL_CLK_DAC_SOURCE;
339 hwp_audcodec->PLL_CFG4 |= (1 << AUDCODEC_PLL_CFG4_EN_CLK_CHOP_DAC_Pos) |
340 (1 << AUDCODEC_PLL_CFG4_EN_CLK_DAC_Pos) |
341 (cfg->sel_clk_dac_source << AUDCODEC_PLL_CFG4_SEL_CLK_DAC_SOURCE_Pos) | // select xtal
342 (cfg->sel_clk_dac << AUDCODEC_PLL_CFG4_SEL_CLK_DAC_Pos) |
343 (1 << AUDCODEC_PLL_CFG4_EN_CLK_DIG_Pos);
344
345 hwp_audcodec->PLL_CFG5 |= (1 << AUDCODEC_PLL_CFG5_EN_CLK_CHOP_BG_Pos) | //
346 (1 << AUDCODEC_PLL_CFG5_EN_CLK_CHOP_REFGEN_Pos); //
347
348 //if (pll_cfg2_reset == 0)
349 {
350 hwp_audcodec->PLL_CFG2 &= ~AUDCODEC_PLL_CFG2_RSTB;
351 HAL_Delay_us(100);
352 hwp_audcodec->PLL_CFG2 |= AUDCODEC_PLL_CFG2_RSTB;
353 }
354
355 // dac1 and dac2 power
356 #ifdef SF32LB58X
357 hwp_audcodec->DAC1_CFG |= AUDCODEC_DAC1_CFG_LP_MODE;
358 hwp_audcodec->DAC2_CFG |= AUDCODEC_DAC2_CFG_LP_MODE;
359 #else
360 #if AVDD_V18_ENABLE
361 hwp_audcodec->DAC1_CFG |= AUDCODEC_DAC1_CFG_LP_MODE; //1.8v
362 #else
363 hwp_audcodec->DAC1_CFG &= ~AUDCODEC_DAC1_CFG_LP_MODE; //3.3v
364 #endif
365 #endif
366 hwp_audcodec->DAC1_CFG &= ~AUDCODEC_DAC1_CFG_EN_OS_DAC;
367 hwp_audcodec->DAC2_CFG &= ~AUDCODEC_DAC2_CFG_EN_OS_DAC;
368 hwp_audcodec->DAC1_CFG |= AUDCODEC_DAC1_CFG_EN_VCM;
369 #ifdef BSP_ENABLE_DAC2
370 hwp_audcodec->DAC2_CFG |= AUDCODEC_DAC2_CFG_EN_VCM;
371 #else
372 hwp_audcodec->DAC2_CFG &= ~AUDCODEC_DAC2_CFG_EN_VCM;
373 #endif
374 // wait 5us
375 //wait(250);
376 HAL_Delay_us(5);
377 hwp_audcodec->DAC1_CFG |= AUDCODEC_DAC1_CFG_EN_AMP;
378 #ifdef BSP_ENABLE_DAC2
379 hwp_audcodec->DAC2_CFG |= AUDCODEC_DAC2_CFG_EN_AMP;
380 #else
381 hwp_audcodec->DAC2_CFG &= ~AUDCODEC_DAC2_CFG_EN_AMP;
382 #endif
383 // wait 1us
384 //wait(50);
385 HAL_Delay_us(1);
386 hwp_audcodec->DAC1_CFG |= AUDCODEC_DAC1_CFG_EN_OS_DAC;
387 hwp_audcodec->DAC2_CFG |= AUDCODEC_DAC2_CFG_EN_OS_DAC;
388 // wait 10us
389 //wait(500);
390 HAL_Delay_us(10);
391 hwp_audcodec->DAC1_CFG |= AUDCODEC_DAC1_CFG_EN_DAC;
392 #ifdef BSP_ENABLE_DAC2
393 hwp_audcodec->DAC2_CFG |= AUDCODEC_DAC2_CFG_EN_DAC;
394 #else
395 hwp_audcodec->DAC2_CFG &= ~AUDCODEC_DAC2_CFG_EN_DAC;
396 #endif
397 // wait 10us
398 //wait(500);
399 HAL_Delay_us(10);
400 hwp_audcodec->DAC1_CFG &= ~AUDCODEC_DAC1_CFG_SR;
401 hwp_audcodec->DAC2_CFG &= ~AUDCODEC_DAC2_CFG_SR;
402 pll_cfg2_reset |= (1 << HAL_AUDCODEC_DAC_CH0);
403 return HAL_OK;
404 }
405
HAL_TURN_OFF_PLL()406 void HAL_TURN_OFF_PLL()
407 {
408 pll_cfg2_reset = 0;
409 // turn off pll
410 hwp_audcodec->PLL_CFG0 &= ~AUDCODEC_PLL_CFG0_EN_IARY;
411 hwp_audcodec->PLL_CFG0 &= ~AUDCODEC_PLL_CFG0_EN_VCO;
412 hwp_audcodec->PLL_CFG0 &= ~AUDCODEC_PLL_CFG0_EN_ANA;
413 hwp_audcodec->PLL_CFG2 &= ~AUDCODEC_PLL_CFG2_EN_DIG;
414 hwp_audcodec->PLL_CFG3 &= ~AUDCODEC_PLL_CFG3_EN_SDM;
415 hwp_audcodec->PLL_CFG4 &= ~AUDCODEC_PLL_CFG4_EN_CLK_DIG;
416
417 // turn off refgen
418 hwp_audcodec->REFGEN_CFG &= ~AUDCODEC_REFGEN_CFG_EN;
419 #if 1
420 // turn off bandgap
421 hwp_audcodec->BG_CFG1 = 0;
422 hwp_audcodec->BG_CFG2 = 0;
423 hwp_audcodec->BG_CFG0 &= ~AUDCODEC_BG_CFG0_EN;
424 hwp_audcodec->BG_CFG0 &= ~AUDCODEC_BG_CFG0_EN_SMPL;
425 #endif
426 HAL_DBG_printf("turn off pll\n");
427
428 }
HAL_TURN_ON_PLL()429 void HAL_TURN_ON_PLL()
430 {
431 HAL_DBG_printf("turn on pll\n");
432 //-----------------step 2------------------//
433 // turn on bandgap
434 hwp_audcodec->BG_CFG0 = (1 << AUDCODEC_BG_CFG0_EN_Pos) |
435 (0 << AUDCODEC_BG_CFG0_LP_MODE_Pos) |
436 #if AVDD_V18_ENABLE
437 (2 << AUDCODEC_BG_CFG0_VREF_SEL_Pos) | // 0xc: 3.3v 2:AVDD = 1.8V
438 #else
439 (0xc << AUDCODEC_BG_CFG0_VREF_SEL_Pos) | // 0xc: 3.3v 2:AVDD = 1.8V
440 #endif
441 // (1 << AUDCODEC_BG_CFG0_EN_CHOP_Pos) |
442 (0 << AUDCODEC_BG_CFG0_EN_SMPL_Pos) |
443 (1 << AUDCODEC_BG_CFG0_EN_RCFLT_Pos) |
444 (4 << AUDCODEC_BG_CFG0_MIC_VREF_SEL_Pos) |
445 (1 << AUDCODEC_BG_CFG0_EN_AMP_Pos) | //----
446 (0 << AUDCODEC_BG_CFG0_SET_VC_Pos);
447 // turn on BG sample clock
448 #if 1 //pop noise
449 hwp_audcodec->BG_CFG1 = 0;
450 hwp_audcodec->BG_CFG2 = 0;
451 #else
452 hwp_audcodec->BG_CFG1 = 48000;
453 hwp_audcodec->BG_CFG2 = 48000000;
454 #endif
455 // turn on bandgap
456 // HAL_Delay_us(100);
457 //hwp_audcodec->BG_CFG0 |= AUDCODEC_BG_CFG0_EN_SMPL;
458
459 //-----------------step 3------------------//
460 // pll calibration
461 // wait 100us
462 //wait(5000);
463 HAL_Delay_us(100);
464
465 hwp_audcodec->PLL_CFG0 |= AUDCODEC_PLL_CFG0_EN_IARY;
466 hwp_audcodec->PLL_CFG0 |= AUDCODEC_PLL_CFG0_EN_VCO;
467 hwp_audcodec->PLL_CFG0 |= AUDCODEC_PLL_CFG0_EN_ANA;
468 hwp_audcodec->PLL_CFG0 &= ~AUDCODEC_PLL_CFG0_ICP_SEL_Msk;
469 hwp_audcodec->PLL_CFG0 |= (8 << AUDCODEC_PLL_CFG0_ICP_SEL_Pos);
470 hwp_audcodec->PLL_CFG2 |= AUDCODEC_PLL_CFG2_EN_DIG;
471 hwp_audcodec->PLL_CFG3 |= AUDCODEC_PLL_CFG3_EN_SDM;
472 hwp_audcodec->PLL_CFG4 |= AUDCODEC_PLL_CFG4_EN_CLK_DIG;
473 hwp_audcodec->PLL_CFG1 = (3 << AUDCODEC_PLL_CFG1_R3_SEL_Pos) |
474 (1 << AUDCODEC_PLL_CFG1_RZ_SEL_Pos) |
475 (3 << AUDCODEC_PLL_CFG1_C2_SEL_Pos) |
476 (6 << AUDCODEC_PLL_CFG1_CZ_SEL_Pos) |
477 (0 << AUDCODEC_PLL_CFG1_CSD_RST_Pos) |
478 (0 << AUDCODEC_PLL_CFG1_CSD_EN_Pos);
479 // wait 50us
480 //wait(2500);
481 HAL_Delay_us(50);
482
483 HAL_AUCODEC_Refgen_Init();
484
485 }
486
HAL_AUDCODEC_Close_Analog_DACPath(void)487 __HAL_ROM_USED void HAL_AUDCODEC_Close_Analog_DACPath(void)
488 {
489 hwp_audcodec->DAC1_CFG |= AUDCODEC_DAC1_CFG_SR;
490 hwp_audcodec->DAC2_CFG |= AUDCODEC_DAC2_CFG_SR;
491 // wait 10us
492 //wait(500);
493 HAL_Delay_us(10);
494 hwp_audcodec->DAC1_CFG &= ~AUDCODEC_DAC1_CFG_EN_DAC;
495 hwp_audcodec->DAC2_CFG &= ~AUDCODEC_DAC2_CFG_EN_DAC;
496 // wait 10us
497 //wait(500);
498 HAL_Delay_us(10);
499 hwp_audcodec->DAC1_CFG &= ~AUDCODEC_DAC1_CFG_EN_VCM;
500 hwp_audcodec->DAC2_CFG &= ~AUDCODEC_DAC2_CFG_EN_VCM;
501 // wait 10us
502 //wait(500);
503 HAL_Delay_us(10);
504 hwp_audcodec->DAC1_CFG &= ~AUDCODEC_DAC1_CFG_EN_AMP;
505 hwp_audcodec->DAC2_CFG &= ~AUDCODEC_DAC2_CFG_EN_AMP;
506 hwp_audcodec->DAC1_CFG &= ~AUDCODEC_DAC1_CFG_EN_OS_DAC;
507 hwp_audcodec->DAC2_CFG &= ~AUDCODEC_DAC2_CFG_EN_OS_DAC;
508 HAL_DBG_printf("close Aanlog DACPath\n");
509
510 }
511
HAL_AUCODEC_Refgen_Init(void)512 __HAL_ROM_USED void HAL_AUCODEC_Refgen_Init(void)
513 {
514 HAL_DBG_printf("turn on refgen\n");
515 // turn on refgen
516 //hwp_audcodec->BG_CFG0 &= ~AUDCODEC_BG_CFG0_EN_SMPL;
517 //hwp_audcodec->BG_CFG0 &= ~AUDCODEC_BG_CFG0_VREF_SEL;
518 //hwp_audcodec->BG_CFG0 |= (7 << AUDCODEC_BG_CFG0_VREF_SEL_Pos); // AVDD = 3.3V
519 //hwp_audcodec->BG_CFG0 |= (2 << AUDCODEC_BG_CFG0_VREF_SEL_Pos); // AVDD = 1.8V
520 hwp_audcodec->BG_CFG0 &= ~AUDCODEC_BG_CFG0_EN_SMPL;
521 hwp_audcodec->REFGEN_CFG &= ~AUDCODEC_REFGEN_CFG_EN_CHOP;
522 hwp_audcodec->REFGEN_CFG |= AUDCODEC_REFGEN_CFG_EN;
523 #if AVDD_V18_ENABLE
524 hwp_audcodec->REFGEN_CFG |= AUDCODEC_REFGEN_CFG_LV_MODE;
525 #else
526 hwp_audcodec->REFGEN_CFG &= ~AUDCODEC_REFGEN_CFG_LV_MODE;
527 #endif
528 //hwp_audcodec->PLL_CFG5 = AUDCODEC_PLL_CFG5_EN_CLK_CHOP_BG |
529 // AUDCODEC_PLL_CFG5_EN_CLK_CHOP_REFGEN;
530 MODIFY_REG(hwp_audcodec->PLL_CFG5, AUDCODEC_PLL_CFG5_EN_CLK_CHOP_BG_Msk, \
531 MAKE_REG_VAL(1, AUDCODEC_PLL_CFG5_EN_CLK_CHOP_BG_Msk, AUDCODEC_PLL_CFG5_EN_CLK_CHOP_BG_Pos));
532 MODIFY_REG(hwp_audcodec->PLL_CFG5, AUDCODEC_PLL_CFG5_EN_CLK_CHOP_REFGEN_Msk, \
533 MAKE_REG_VAL(1, AUDCODEC_PLL_CFG5_EN_CLK_CHOP_REFGEN_Msk, AUDCODEC_PLL_CFG5_EN_CLK_CHOP_REFGEN_Pos));
534 HAL_Delay(2); //2ms
535 #if 1
536 hwp_audcodec->BG_CFG0 &= ~AUDCODEC_BG_CFG0_EN_SMPL; //noise pop
537 #else
538 hwp_audcodec->BG_CFG0 |= AUDCODEC_BG_CFG0_EN_SMPL; //noise pop
539 #endif
540 }
541
HAL_AUDCODEC_Config_Analog_ADCPath(AUDCODE_ADC_CLK_CONFIG_TYPE * cfg)542 __HAL_ROM_USED void HAL_AUDCODEC_Config_Analog_ADCPath(AUDCODE_ADC_CLK_CONFIG_TYPE *cfg)
543 {
544 HAL_DBG_printf("config Aanlog ADCPath\n");
545 // turn on lp adc1 and adc2 analog
546 hwp_audcodec->BG_CFG0 &= ~AUDCODEC_BG_CFG0_EN_SMPL;
547 hwp_audcodec->ADC_ANA_CFG |= AUDCODEC_ADC_ANA_CFG_MICBIAS_EN;
548 hwp_audcodec->ADC_ANA_CFG &= ~AUDCODEC_ADC_ANA_CFG_MICBIAS_CHOP_EN;
549 HAL_Delay(2); //2ms
550 #if 1
551 hwp_audcodec->BG_CFG0 &= ~AUDCODEC_BG_CFG0_EN_SMPL; //noise pop
552 #else
553 hwp_audcodec->BG_CFG0 |= AUDCODEC_BG_CFG0_EN_SMPL; //noise pop
554 #endif
555 // adc1 and adc2 clock
556 hwp_audcodec->PLL_CFG6 = (0 << AUDCODEC_PLL_CFG6_SEL_TST_CLK_Pos) |
557 (0 << AUDCODEC_PLL_CFG6_EN_TST_CLK_Pos) |
558 (0 << AUDCODEC_PLL_CFG6_EN_CLK_RCCAL_Pos) |
559 (3 << AUDCODEC_PLL_CFG6_SEL_CLK_CHOP_MICBIAS_Pos) |
560 (1 << AUDCODEC_PLL_CFG6_EN_CLK_CHOP_MICBIAS_Pos) |
561 (cfg->sel_clk_adc << AUDCODEC_PLL_CFG6_SEL_CLK_ADC2_Pos) |
562 (cfg->diva_clk_adc << AUDCODEC_PLL_CFG6_DIVA_CLK_ADC2_Pos) |
563 (1 << AUDCODEC_PLL_CFG6_EN_CLK_ADC2_Pos) |
564 (cfg->sel_clk_adc << AUDCODEC_PLL_CFG6_SEL_CLK_ADC1_Pos) |
565 (cfg->diva_clk_adc << AUDCODEC_PLL_CFG6_DIVA_CLK_ADC1_Pos) |
566 (1 << AUDCODEC_PLL_CFG6_EN_CLK_ADC1_Pos) |
567 (1 << AUDCODEC_PLL_CFG6_SEL_CLK_ADC0_Pos) |
568 (5 << AUDCODEC_PLL_CFG6_DIVA_CLK_ADC0_Pos) |
569 (1 << AUDCODEC_PLL_CFG6_EN_CLK_ADC0_Pos) |
570 (cfg->sel_clk_adc_source << AUDCODEC_PLL_CFG6_SEL_CLK_ADC_SOURCE_Pos);
571
572 //if (pll_cfg2_reset == 0)
573 {
574 hwp_audcodec->PLL_CFG2 &= ~AUDCODEC_PLL_CFG2_RSTB;
575 HAL_Delay(1);
576 hwp_audcodec->PLL_CFG2 |= AUDCODEC_PLL_CFG2_RSTB;
577 }
578
579 hwp_audcodec->ADC1_CFG1 &= ~AUDCODEC_ADC1_CFG1_DIFF_EN;
580 //hwp_audcodec->ADC1_CFG1 |= AUDCODEC_ADC1_CFG1_DIFF_EN;
581 hwp_audcodec->ADC1_CFG1 &= ~AUDCODEC_ADC1_CFG1_DACN_EN;
582
583 hwp_audcodec->ADC1_CFG1 &= ~AUDCODEC_ADC1_CFG1_FSP;
584 hwp_audcodec->ADC1_CFG1 |= (cfg->fsp << AUDCODEC_ADC1_CFG1_FSP_Pos);
585
586 //this make long mic startup pulse
587 hwp_audcodec->ADC1_CFG1 |= AUDCODEC_ADC1_CFG1_VCMST;
588 hwp_audcodec->ADC1_CFG2 |= AUDCODEC_ADC1_CFG2_CLEAR;
589
590 hwp_audcodec->ADC1_CFG1 &= ~AUDCODEC_ADC1_CFG1_GC_Msk;
591 hwp_audcodec->ADC1_CFG1 |= (0x4 << AUDCODEC_ADC1_CFG1_GC_Pos);
592
593 hwp_audcodec->ADC1_CFG2 |= AUDCODEC_ADC1_CFG2_EN;
594 hwp_audcodec->ADC1_CFG2 &= ~AUDCODEC_ADC1_CFG2_RSTB;
595
596 hwp_audcodec->ADC1_CFG1 &= ~AUDCODEC_ADC1_CFG1_VREF_SEL;
597 hwp_audcodec->ADC1_CFG1 |= (2 << AUDCODEC_ADC1_CFG1_VREF_SEL_Pos) ;
598
599 hwp_audcodec->ADC2_CFG1 &= ~AUDCODEC_ADC2_CFG1_FSP;
600 hwp_audcodec->ADC2_CFG1 |= (cfg->fsp << AUDCODEC_ADC2_CFG1_FSP_Pos);
601
602 hwp_audcodec->ADC2_CFG1 |= AUDCODEC_ADC2_CFG1_VCMST;
603 hwp_audcodec->ADC2_CFG2 |= AUDCODEC_ADC2_CFG2_CLEAR;
604
605 hwp_audcodec->ADC2_CFG1 &= ~AUDCODEC_ADC2_CFG1_GC_Msk;
606 hwp_audcodec->ADC2_CFG1 |= (0x1E << AUDCODEC_ADC2_CFG1_GC_Pos);
607
608 hwp_audcodec->ADC2_CFG2 |= AUDCODEC_ADC2_CFG2_EN;
609 hwp_audcodec->ADC2_CFG2 &= ~AUDCODEC_ADC2_CFG2_RSTB;
610
611 hwp_audcodec->ADC2_CFG2 &= ~AUDCODEC_ADC2_CFG1_VREF_SEL;
612 hwp_audcodec->ADC2_CFG2 |= (2 << AUDCODEC_ADC2_CFG1_VREF_SEL_Pos) ;
613 // wait 20ms
614 HAL_Delay(20);
615 //hwp_audcodec->BG_CFG0 |= AUDCODEC_BG_CFG0_EN_SMPL;
616 hwp_audcodec->ADC1_CFG2 |= AUDCODEC_ADC1_CFG2_RSTB;
617 hwp_audcodec->ADC1_CFG1 &= ~AUDCODEC_ADC1_CFG1_VCMST;
618 hwp_audcodec->ADC1_CFG2 &= ~AUDCODEC_ADC1_CFG2_CLEAR;
619 hwp_audcodec->ADC2_CFG2 |= AUDCODEC_ADC2_CFG2_RSTB;
620 hwp_audcodec->ADC2_CFG1 &= ~AUDCODEC_ADC2_CFG1_VCMST;
621 hwp_audcodec->ADC2_CFG2 &= ~AUDCODEC_ADC2_CFG2_CLEAR;
622 pll_cfg2_reset |= (1 << HAL_AUDCODEC_ADC_CH0);
623
624 }
625
HAL_AUDCODEC_Close_Analog_ADCPath(void)626 __HAL_ROM_USED void HAL_AUDCODEC_Close_Analog_ADCPath(void)
627 {
628 // turn off adc
629 hwp_audcodec->ADC1_CFG2 &= ~AUDCODEC_ADC1_CFG2_EN;
630 hwp_audcodec->ADC2_CFG2 &= ~AUDCODEC_ADC2_CFG2_EN;
631 hwp_audcodec->ADC_ANA_CFG &= ~AUDCODEC_ADC_ANA_CFG_MICBIAS_EN;
632 HAL_DBG_printf("close Aanlog ADCPath\n");
633
634 }
635
636
637 /**
638 * @brief Initializes the AUDCODEC according to the specified parameters
639 * in the AUDCODEC_InitTypeDef and create the associated handle.
640 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
641 * the configuration information for AUDCODEC module
642 * @retval HAL status
643 */
HAL_AUDCODEC_Init(AUDCODEC_HandleTypeDef * hacodec)644 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Init(AUDCODEC_HandleTypeDef *hacodec)
645 {
646 int i = 0;
647 /* Check the AUDCODEC handle allocation */
648 if (hacodec == NULL)
649 {
650 return HAL_ERROR;
651 }
652
653 if (hacodec->State[0] == HAL_AUDCODEC_STATE_RESET)
654 {
655 /* Allocate lock resource and initialize it */
656 hacodec->Lock = HAL_UNLOCKED;
657
658 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
659 HAL_AUDCODEC_MspInit(hacodec);
660 }
661
662 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
663 {
664 hacodec->State[i] = HAL_AUDCODEC_STATE_BUSY;
665 }
666
667 // disable and Set delay count
668 //MODIFY_REG(hacodec->Instance->CFG, AUDCODEC_CFG_EN_DLY_SEL_Msk,
669 // MAKE_REG_VAL(hacodec->Init.en_dly_sel, AUDCODEC_CFG_EN_DLY_SEL_Msk, AUDCODEC_CFG_EN_DLY_SEL_Pos));
670 //hacodec->Instance->CFG = MAKE_REG_VAL(hacodec->Init.en_dly_sel, AUDCODEC_CFG_EN_DLY_SEL_Msk, AUDCODEC_CFG_EN_DLY_SEL_Pos);
671 //hacodec->Instance->CFG = MAKE_REG_VAL(hacodec->Init.en_dly_sel, AUDCODEC_CFG_EN_DLY_SEL_Msk, AUDCODEC_CFG_EN_DLY_SEL_Pos);
672
673
674 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
675 if (hacodec->hdma[i] != NULL)
676 hacodec->hdma[i]->Parent = (void *)hacodec;
677
678 for (i = HAL_AUDCODEC_DAC_CH0; i < HAL_AUDCODEC_ADC_CH0; i++)
679 {
680 if (hacodec->hdma[i] != NULL)
681 HAL_AUDCODEC_DMA_Init(hacodec->hdma[i], 1);
682 }
683 for (i = HAL_AUDCODEC_ADC_CH0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
684 {
685 if (hacodec->hdma[i] != NULL)
686 HAL_AUDCODEC_DMA_Init(hacodec->hdma[i], 0);
687 }
688
689 //HAL_AUDCODEC_Config_DACPath(hacodec, &(hacodec->Init.dac_cfg));
690 //HAL_AUDCODEC_Config_ADCPath(hacodec, &(hacodec->Init.adc_cfg));
691
692 hacodec->ErrorCode = HAL_AUDCODEC_ERROR_NONE;
693 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
694 {
695 hacodec->State[i] = HAL_AUDCODEC_STATE_READY;
696 }
697
698 return HAL_OK;
699 }
700
701 /**
702 * @brief DeInitializes the AUDCODEC peripheral
703 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
704 * the configuration information for AUDCODEC module
705 * @retval HAL status
706 */
HAL_AUDCODEC_DeInit(AUDCODEC_HandleTypeDef * hacodec)707 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_DeInit(AUDCODEC_HandleTypeDef *hacodec)
708 {
709 int i;
710
711 /* Check the AUDCODEC handle allocation */
712 if (hacodec == NULL)
713 {
714 return HAL_ERROR;
715 }
716
717
718 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
719 {
720 hacodec->State[i] |= HAL_AUDCODEC_STATE_BUSY;
721 if (hacodec->hdma[i] != NULL)
722 HAL_DMA_DeInit(hacodec->hdma[i]);
723 }
724
725
726 /* Disable the AUDCODEC Peripheral Clock */
727 __HAL_AUDCODEC_DAC_DISABLE(hacodec);
728 __HAL_AUDCODEC_ADC_DISABLE(hacodec);
729
730 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
731 HAL_AUDCODEC_MspDeInit(hacodec);
732
733 hacodec->ErrorCode = HAL_AUDCODEC_ERROR_NONE;
734 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
735 {
736 hacodec->State[i] |= HAL_AUDCODEC_STATE_RESET;
737 }
738
739 /* Release Lock */
740 __HAL_UNLOCK(hacodec);
741
742 return HAL_OK;
743 }
744
745 /**
746 * @brief Initializes the AUDCODEC pin setting.
747 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
748 * the configuration information for AUDCODEC module
749 * @retval None
750 */
HAL_AUDCODEC_MspInit(AUDCODEC_HandleTypeDef * hacodec)751 __HAL_ROM_USED void HAL_AUDCODEC_MspInit(AUDCODEC_HandleTypeDef *hacodec)
752 {
753 /* Prevent unused argument(s) compilation warning */
754 UNUSED(hacodec);
755 }
756
757 /**
758 * @brief deunitializes the AUDCODEC pin setting.
759 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
760 * the configuration information for AUDCODEC module
761 * @retval None
762 */
HAL_AUDCODEC_MspDeInit(AUDCODEC_HandleTypeDef * hacodec)763 __HAL_ROM_USED void HAL_AUDCODEC_MspDeInit(AUDCODEC_HandleTypeDef *hacodec)
764 {
765 /* Prevent unused argument(s) compilation warning */
766 UNUSED(hacodec);
767 }
768
769 /**
770 * @brief Set AUDCODEC transmit channel configures.
771 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
772 * the configuration information for AUDCODEC module
773 * @param cfg: configure parameters
774 * @retval HAL status
775 */
HAL_AUDCODEC_Config_TChanel(AUDCODEC_HandleTypeDef * hacodec,int channel,AUDCODEC_DACCfgTypeDef * cfg)776 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Config_TChanel(AUDCODEC_HandleTypeDef *hacodec, int channel, AUDCODEC_DACCfgTypeDef *cfg)
777 {
778 AUDCODE_DAC_CLK_CONFIG_TYPE *dac_clk = cfg->dac_clk;
779
780 /* Check the AUDCODEC handle allocation */
781 if (hacodec == NULL)
782 {
783 return HAL_ERROR;
784 }
785
786 hacodec->Instance->CFG |= (3 << AUDCODEC_CFG_ADC_EN_DLY_SEL_Pos);
787 hacodec->Instance->DAC_CFG = (dac_clk->osr_sel << AUDCODEC_DAC_CFG_OSR_SEL_Pos) |
788 (cfg->opmode << AUDCODEC_DAC_CFG_OP_MODE_Pos) |
789 (0 << AUDCODEC_DAC_CFG_PATH_RESET_Pos) |
790 (dac_clk->clk_src_sel << AUDCODEC_DAC_CFG_CLK_SRC_SEL_Pos) |
791 (dac_clk->clk_div << AUDCODEC_DAC_CFG_CLK_DIV_Pos);
792 switch (channel)
793 {
794 case 0:
795 hacodec->Instance->DAC_CH0_CFG = (1 << AUDCODEC_DAC_CH0_CFG_ENABLE_Pos) |
796 (0 << AUDCODEC_DAC_CH0_CFG_DOUT_MUTE_Pos) |
797 (2 << AUDCODEC_DAC_CH0_CFG_DEM_MODE_Pos) |
798 (0 << AUDCODEC_DAC_CH0_CFG_DMA_EN_Pos) |
799 (6 << AUDCODEC_DAC_CH0_CFG_ROUGH_VOL_Pos) |
800 (0 << AUDCODEC_DAC_CH0_CFG_FINE_VOL_Pos) |
801 (1 << AUDCODEC_DAC_CH0_CFG_DATA_FORMAT_Pos) |
802 (dac_clk->sinc_gain << AUDCODEC_DAC_CH0_CFG_SINC_GAIN_Pos) |
803 (0 << AUDCODEC_DAC_CH0_CFG_DITHER_GAIN_Pos) |
804 (0 << AUDCODEC_DAC_CH0_CFG_DITHER_EN_Pos) |
805 (0 << AUDCODEC_DAC_CH0_CFG_CLK_ANA_POL_Pos);
806
807 hacodec->Instance->DAC_CH0_CFG_EXT = (1 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_EN_Pos) |
808 (1 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_MODE_Pos) |
809 (1 << AUDCODEC_DAC_CH0_CFG_EXT_ZERO_ADJUST_EN_Pos) |
810 (2 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_INTERVAL_Pos) |
811 (0 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_STAT_Pos);
812
813 hacodec->Instance->DAC_CH0_DEBUG = (0 << AUDCODEC_DAC_CH0_DEBUG_BYPASS_Pos) |
814 (0xFF << AUDCODEC_DAC_CH0_DEBUG_DATA_OUT_Pos);
815 //hacodec->Instance->DAC_CH0_DC = MAKE_REG_VAL(cfg->dc_offset, AUDCODEC_DAC_CH0_DC_OFFSET_Msk, AUDCODEC_DAC_CH0_DC_OFFSET_Pos);
816 break;
817 case 1:
818 hacodec->Instance->DAC_CH1_CFG = (1 << AUDCODEC_DAC_CH0_CFG_ENABLE_Pos) |
819 (0 << AUDCODEC_DAC_CH0_CFG_DOUT_MUTE_Pos) |
820 (2 << AUDCODEC_DAC_CH0_CFG_DEM_MODE_Pos) |
821 (0 << AUDCODEC_DAC_CH0_CFG_DMA_EN_Pos) |
822 (6 << AUDCODEC_DAC_CH0_CFG_ROUGH_VOL_Pos) |
823 (0 << AUDCODEC_DAC_CH0_CFG_FINE_VOL_Pos) |
824 (1 << AUDCODEC_DAC_CH0_CFG_DATA_FORMAT_Pos) |
825 (dac_clk->sinc_gain << AUDCODEC_DAC_CH0_CFG_SINC_GAIN_Pos) |
826 (0 << AUDCODEC_DAC_CH0_CFG_DITHER_GAIN_Pos) |
827 (0 << AUDCODEC_DAC_CH0_CFG_DITHER_EN_Pos) |
828 (0 << AUDCODEC_DAC_CH0_CFG_CLK_ANA_POL_Pos);
829
830 hacodec->Instance->DAC_CH1_CFG_EXT = (1 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_EN_Pos) |
831 (1 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_MODE_Pos) |
832 (1 << AUDCODEC_DAC_CH0_CFG_EXT_ZERO_ADJUST_EN_Pos) |
833 (2 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_INTERVAL_Pos) |
834 (0 << AUDCODEC_DAC_CH0_CFG_EXT_RAMP_STAT_Pos);
835
836 hacodec->Instance->DAC_CH1_DEBUG = (0 << AUDCODEC_DAC_CH0_DEBUG_BYPASS_Pos) |
837 (0xFF << AUDCODEC_DAC_CH0_DEBUG_DATA_OUT_Pos);
838 //hacodec->Instance->DAC_CH1_DC = MAKE_REG_VAL(cfg->dc_offset, AUDCODEC_DAC_CH1_DC_OFFSET_Msk, AUDCODEC_DAC_CH1_DC_OFFSET_Pos);
839 break;
840 default:
841 return HAL_ERROR;
842 }
843
844 return HAL_OK;
845 }
846
847 /**
848 * @brief Set AUDCODEC Receive configures.
849 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
850 * the configuration information for AUDCODEC module
851 * @param cfg: configure parameters
852 * @retval HAL status
853 */
HAL_AUDCODEC_Config_RChanel(AUDCODEC_HandleTypeDef * hacodec,int channel,AUDCODEC_ADCCfgTypeDef * cfg)854 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Config_RChanel(AUDCODEC_HandleTypeDef *hacodec, int channel, AUDCODEC_ADCCfgTypeDef *cfg)
855 {
856 AUDCODE_ADC_CLK_CONFIG_TYPE *adc_clk = cfg->adc_clk;
857
858 /* Check the AUDCODEC handle allocation */
859 if (hacodec == NULL)
860 {
861 return HAL_ERROR;
862 }
863
864 hacodec->Instance->ADC_CFG = (adc_clk->osr_sel << AUDCODEC_ADC_CFG_OSR_SEL_Pos) |
865 (cfg->opmode << AUDCODEC_ADC_CFG_OP_MODE_Pos) | // 2 for test
866 (0 << AUDCODEC_ADC_CFG_PATH_RESET_Pos) |
867 (adc_clk->clk_src_sel << AUDCODEC_ADC_CFG_CLK_SRC_SEL_Pos) |
868 (adc_clk->clk_div << AUDCODEC_ADC_CFG_CLK_DIV_Pos);
869
870 //hacodec->Instance->ADC_CFG = 0x508;//0x508; 510:raw
871
872 switch (channel)
873 {
874 case 0:
875
876 hacodec->Instance->ADC_CH0_CFG = (1 << AUDCODEC_ADC_CH0_CFG_ENABLE_Pos) |
877 (0 << AUDCODEC_ADC_CH0_CFG_HPF_BYPASS_Pos) |
878 (0x7 << AUDCODEC_ADC_CH0_CFG_HPF_COEF_Pos) |
879 (0 << AUDCODEC_ADC_CH0_CFG_STB_INV_Pos) |
880 (0 << AUDCODEC_ADC_CH0_CFG_DMA_EN_Pos) |
881 (0xc << AUDCODEC_ADC_CH0_CFG_ROUGH_VOL_Pos) |
882 (0 << AUDCODEC_ADC_CH0_CFG_FINE_VOL_Pos) |
883 (1 << AUDCODEC_ADC_CH0_CFG_DATA_FORMAT_Pos); //16bit
884 //hacodec->Instance->ADC_CH0_CFG = 0x10ABD;
885 break;
886 case 1:
887
888 hacodec->Instance->ADC_CH1_CFG = (1 << AUDCODEC_ADC_CH0_CFG_ENABLE_Pos) |
889 (0 << AUDCODEC_ADC_CH0_CFG_HPF_BYPASS_Pos) |
890 (0xf << AUDCODEC_ADC_CH0_CFG_HPF_COEF_Pos) |
891 (0 << AUDCODEC_ADC_CH0_CFG_STB_INV_Pos) |
892 (0 << AUDCODEC_ADC_CH0_CFG_DMA_EN_Pos) |
893 (0xc << AUDCODEC_ADC_CH0_CFG_ROUGH_VOL_Pos) |
894 (0 << AUDCODEC_ADC_CH0_CFG_FINE_VOL_Pos) |
895 (1 << AUDCODEC_ADC_CH0_CFG_DATA_FORMAT_Pos); //16bit
896 break;
897 default:
898 return HAL_ERROR;
899 }
900
901 return HAL_OK;
902 }
903
904
905 /**
906 * @brief all channel disable
907 * @param hacodec -pointer to a AUDCODEC_HandleTypeDef structure that contains
908 * the configuration information for AUDCODEC module
909 * @param ch_type_bit : bit0 is dac, bit1 is adc
910 * @return HAL status
911 */
HAL_AUDCODEC_Clear_All_Channel(AUDCODEC_HandleTypeDef * hacodec,uint8_t ch_type_bit)912 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Clear_All_Channel(AUDCODEC_HandleTypeDef *hacodec, uint8_t ch_type_bit)
913 {
914 if (ch_type_bit & 0x1)
915 {
916 __HAL_AUDCODEC_DAC_CH0_DISABLE(hacodec);
917 __HAL_AUDCODEC_DAC_CH1_DISABLE(hacodec);
918 hacodec->Instance->DAC_CFG |= AUDCODEC_DAC_CFG_PATH_RESET;
919 hacodec->Instance->DAC_CFG &= ~AUDCODEC_DAC_CFG_PATH_RESET;
920 pll_cfg2_reset &= ~(1 << HAL_AUDCODEC_DAC_CH0);
921 }
922
923 if (ch_type_bit & 0x2)
924 {
925 __HAL_AUDCODEC_ADC_CH0_DISABLE(hacodec);
926 __HAL_AUDCODEC_ADC_CH1_DISABLE(hacodec);
927 hacodec->Instance->ADC_CFG |= AUDCODEC_ADC_CFG_PATH_RESET;
928 hacodec->Instance->ADC_CFG &= ~AUDCODEC_ADC_CFG_PATH_RESET;
929 pll_cfg2_reset &= ~(1 << HAL_AUDCODEC_ADC_CH0);
930 }
931
932 return HAL_OK;
933 }
934
935 /**
936 * @brief Configure DAC path volume.
937 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
938 * the configuration information for AUDCODEC module
939 * @param channel: channel 0 or 1
940 * @param volume: configure volume -36dB~54dB, unit is 0.5db, use fix point Q15.1 format
941 * @retval HAL status
942 */
HAL_AUDCODEC_Config_DACPath_Volume(AUDCODEC_HandleTypeDef * hacodec,int channel,int volume)943 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Config_DACPath_Volume(AUDCODEC_HandleTypeDef *hacodec, int channel, int volume)
944 {
945 uint32_t rough_vol, fine_vol;
946 int volume2;
947 /* Check the AUDCODEC handle allocation */
948 if (hacodec == NULL)
949 {
950 return HAL_ERROR;
951 }
952
953 if ((channel < 0) || (channel > 1))
954 {
955 return HAL_ERROR;
956 }
957
958 if (volume >= 0)
959 {
960 volume2 = volume;
961 }
962 else
963 {
964 volume2 = 0 - volume;
965 }
966
967 if (volume2 & 1)
968 {
969 fine_vol = 1;
970 }
971 else
972 {
973 fine_vol = 0;
974 }
975
976 volume2 = (volume2 >> 1);
977
978 if (volume < 0)
979 {
980 volume = 0 - volume2;
981 if (fine_vol)
982 volume--;
983 }
984 else
985 volume = volume2;
986
987 //HAL_DBG_printf("codec vol=%d, 0.5 on/off=%d", volume, fine_vol);
988
989 if ((volume < -36) || (volume > 54) || (volume == 54 && fine_vol))
990 {
991 return HAL_ERROR;
992 }
993
994 rough_vol = (volume + 36) / 6;
995 fine_vol = fine_vol + (((volume + 36) % 6) << 1);
996
997 if (channel == 0)
998 {
999 MODIFY_REG(hacodec->Instance->DAC_CH0_CFG, AUDCODEC_DAC_CH0_CFG_ROUGH_VOL_Msk | AUDCODEC_DAC_CH0_CFG_FINE_VOL_Msk, \
1000 MAKE_REG_VAL(rough_vol, AUDCODEC_DAC_CH0_CFG_ROUGH_VOL_Msk, AUDCODEC_DAC_CH0_CFG_ROUGH_VOL_Pos) |
1001 MAKE_REG_VAL(fine_vol, AUDCODEC_DAC_CH0_CFG_FINE_VOL_Msk, AUDCODEC_DAC_CH0_CFG_FINE_VOL_Pos));
1002 }
1003 else
1004 {
1005 MODIFY_REG(hacodec->Instance->DAC_CH1_CFG, AUDCODEC_DAC_CH0_CFG_ROUGH_VOL_Msk | AUDCODEC_DAC_CH0_CFG_FINE_VOL_Msk, \
1006 MAKE_REG_VAL(rough_vol, AUDCODEC_DAC_CH0_CFG_ROUGH_VOL_Msk, AUDCODEC_DAC_CH0_CFG_ROUGH_VOL_Pos) |
1007 MAKE_REG_VAL(fine_vol, AUDCODEC_DAC_CH0_CFG_FINE_VOL_Msk, AUDCODEC_DAC_CH0_CFG_FINE_VOL_Pos));
1008 }
1009
1010 HAL_DBG_printf("set volume rough:%d, fine:%d, cfg0:0x%x", rough_vol, fine_vol, hacodec->Instance->DAC_CH0_CFG);
1011
1012 return HAL_OK;
1013 }
1014
1015 /**
1016 * @brief Configure ADC path volume.
1017 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
1018 * the configuration information for AUDCODEC module
1019 * @param channel: channel 0 or 1
1020 * @param volume: configure volume -36dB~54dB
1021 * @retval HAL status
1022 */
HAL_AUDCODEC_Config_ADCPath_Volume(AUDCODEC_HandleTypeDef * hacodec,int channel,int volume)1023 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Config_ADCPath_Volume(AUDCODEC_HandleTypeDef *hacodec, int channel, int volume)
1024 {
1025 uint32_t rough_vol, fine_vol;
1026
1027 /* Check the AUDCODEC handle allocation */
1028 if (hacodec == NULL)
1029 {
1030 return HAL_ERROR;
1031 }
1032
1033 if ((channel < 0) || (channel > 1))
1034 {
1035 return HAL_ERROR;
1036 }
1037
1038 if ((volume < -36) || (volume > 54))
1039 {
1040 return HAL_ERROR;
1041 }
1042
1043 rough_vol = (volume + 36) / 6;
1044 fine_vol = ((volume + 36) % 6) << 1;
1045
1046 if (channel == 0)
1047 {
1048 MODIFY_REG(hacodec->Instance->ADC_CH0_CFG, AUDCODEC_ADC_CH0_CFG_ROUGH_VOL_Msk | AUDCODEC_ADC_CH0_CFG_FINE_VOL_Msk, \
1049 MAKE_REG_VAL(rough_vol, AUDCODEC_ADC_CH0_CFG_ROUGH_VOL_Msk, AUDCODEC_ADC_CH0_CFG_ROUGH_VOL_Pos) |
1050 MAKE_REG_VAL(fine_vol, AUDCODEC_ADC_CH0_CFG_FINE_VOL_Msk, AUDCODEC_ADC_CH0_CFG_FINE_VOL_Pos));
1051 }
1052 else
1053 {
1054 MODIFY_REG(hacodec->Instance->ADC_CH1_CFG, AUDCODEC_ADC_CH0_CFG_ROUGH_VOL_Msk | AUDCODEC_ADC_CH0_CFG_FINE_VOL_Msk, \
1055 MAKE_REG_VAL(rough_vol, AUDCODEC_ADC_CH0_CFG_ROUGH_VOL_Msk, AUDCODEC_ADC_CH0_CFG_ROUGH_VOL_Pos) |
1056 MAKE_REG_VAL(fine_vol, AUDCODEC_ADC_CH0_CFG_FINE_VOL_Msk, AUDCODEC_ADC_CH0_CFG_FINE_VOL_Pos));
1057 }
1058
1059 //LOG_E("set ADC volume rough:%d, fine:%d, cfg0:0x%x", rough_vol, fine_vol, hacodec->Instance->DAC_CH0_CFG);
1060
1061 return HAL_OK;
1062 }
1063
1064
1065 /**
1066 * @brief Config DAC path.
1067 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
1068 * the configuration information for AUDCODEC module
1069 * @retval HAL status
1070 */
HAL_AUDCODEC_Config_DACPath(AUDCODEC_HandleTypeDef * hacodec,uint16_t bypass)1071 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Config_DACPath(AUDCODEC_HandleTypeDef *hacodec, uint16_t bypass)
1072 {
1073 /* Check the AUDCODEC handle allocation */
1074 if (hacodec == NULL)
1075 {
1076 return HAL_ERROR;
1077 }
1078
1079 if (bypass)
1080 {
1081 MODIFY_REG(hacodec->Instance->DAC_CH0_CFG, AUDCODEC_DAC_CH0_CFG_DOUT_MUTE_Msk, \
1082 MAKE_REG_VAL(1, AUDCODEC_DAC_CH0_CFG_DOUT_MUTE_Msk, AUDCODEC_DAC_CH0_CFG_DOUT_MUTE_Pos));
1083
1084 hacodec->Instance->DAC_CH0_DEBUG = (1 << AUDCODEC_DAC_CH0_DEBUG_BYPASS_Pos) |
1085 (0xFF << AUDCODEC_DAC_CH0_DEBUG_DATA_OUT_Pos);
1086
1087 MODIFY_REG(hacodec->Instance->DAC_CH1_CFG, AUDCODEC_DAC_CH1_CFG_DOUT_MUTE_Msk, \
1088 MAKE_REG_VAL(1, AUDCODEC_DAC_CH1_CFG_DOUT_MUTE_Msk, AUDCODEC_DAC_CH1_CFG_DOUT_MUTE_Pos));
1089
1090 hacodec->Instance->DAC_CH1_DEBUG = (1 << AUDCODEC_DAC_CH1_DEBUG_BYPASS_Pos) |
1091 (0xFF << AUDCODEC_DAC_CH1_DEBUG_DATA_OUT_Pos);
1092 }
1093 else
1094 {
1095 MODIFY_REG(hacodec->Instance->DAC_CH0_CFG, AUDCODEC_DAC_CH0_CFG_DOUT_MUTE_Msk, \
1096 MAKE_REG_VAL(0, AUDCODEC_DAC_CH0_CFG_DOUT_MUTE_Msk, AUDCODEC_DAC_CH0_CFG_DOUT_MUTE_Pos));
1097 hacodec->Instance->DAC_CH0_DEBUG = (0 << AUDCODEC_DAC_CH0_DEBUG_BYPASS_Pos) |
1098 (0xFF << AUDCODEC_DAC_CH0_DEBUG_DATA_OUT_Pos);
1099 MODIFY_REG(hacodec->Instance->DAC_CH1_CFG, AUDCODEC_DAC_CH1_CFG_DOUT_MUTE_Msk, \
1100 MAKE_REG_VAL(0, AUDCODEC_DAC_CH1_CFG_DOUT_MUTE_Msk, AUDCODEC_DAC_CH1_CFG_DOUT_MUTE_Pos));
1101 hacodec->Instance->DAC_CH1_DEBUG = (0 << AUDCODEC_DAC_CH1_DEBUG_BYPASS_Pos) |
1102 (0xFF << AUDCODEC_DAC_CH1_DEBUG_DATA_OUT_Pos);
1103 }
1104
1105 return HAL_OK;
1106 }
1107
1108 /**
1109 * @brief Configure DAC path mute.
1110 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
1111 * the configuration information for AUDCODEC module
1112 * @param mute: is mute or not
1113 * @retval HAL status
1114 */
HAL_AUDCODEC_Mute_DACPath(AUDCODEC_HandleTypeDef * hacodec,int mute)1115 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Mute_DACPath(AUDCODEC_HandleTypeDef *hacodec, int mute)
1116 {
1117 static int fine_vol_0, fine_vol_1;
1118
1119 /* Check the AUDCODEC handle allocation */
1120 if (hacodec == NULL)
1121 {
1122 return HAL_ERROR;
1123 }
1124
1125 if (mute)
1126 {
1127 fine_vol_0 = GET_REG_VAL(hacodec->Instance->DAC_CH0_CFG, AUDCODEC_DAC_CH0_CFG_FINE_VOL_Msk, AUDCODEC_DAC_CH0_CFG_FINE_VOL_Pos);
1128 fine_vol_1 = GET_REG_VAL(hacodec->Instance->DAC_CH1_CFG, AUDCODEC_DAC_CH1_CFG_FINE_VOL_Msk, AUDCODEC_DAC_CH1_CFG_FINE_VOL_Pos);
1129 MODIFY_REG(hacodec->Instance->DAC_CH0_CFG, AUDCODEC_DAC_CH0_CFG_FINE_VOL_Msk, \
1130 MAKE_REG_VAL(0xF, AUDCODEC_DAC_CH0_CFG_FINE_VOL_Msk, AUDCODEC_DAC_CH0_CFG_FINE_VOL_Pos));
1131 MODIFY_REG(hacodec->Instance->DAC_CH1_CFG, AUDCODEC_DAC_CH1_CFG_FINE_VOL_Msk, \
1132 MAKE_REG_VAL(0xF, AUDCODEC_DAC_CH1_CFG_FINE_VOL_Msk, AUDCODEC_DAC_CH1_CFG_FINE_VOL_Pos));
1133 }
1134 else
1135 {
1136 MODIFY_REG(hacodec->Instance->DAC_CH0_CFG, AUDCODEC_DAC_CH0_CFG_FINE_VOL_Msk, \
1137 MAKE_REG_VAL(fine_vol_0, AUDCODEC_DAC_CH0_CFG_FINE_VOL_Msk, AUDCODEC_DAC_CH0_CFG_FINE_VOL_Pos));
1138 MODIFY_REG(hacodec->Instance->DAC_CH1_CFG, AUDCODEC_DAC_CH1_CFG_FINE_VOL_Msk, \
1139 MAKE_REG_VAL(fine_vol_1, AUDCODEC_DAC_CH1_CFG_FINE_VOL_Msk, AUDCODEC_DAC_CH1_CFG_FINE_VOL_Pos));
1140 }
1141
1142
1143 return HAL_OK;
1144 }
1145
1146 #if 0
1147
1148 /**
1149 * @brief Configure ADC path.
1150 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
1151 * the configuration information for AUDCODEC module
1152 * @param cfg: configure parameters
1153 * @retval HAL status
1154 */
1155 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Config_ADCPath(AUDCODEC_HandleTypeDef *hacodec, AUDCODEC_ADCCfgTypeDef *cfg)
1156 {
1157 uint32_t value;
1158
1159 /* Check the AUDCODEC handle allocation */
1160 if (hacodec == NULL)
1161 {
1162 return HAL_ERROR;
1163 }
1164 value = MAKE_REG_VAL(cfg->clk_div, AUDCODEC_ADC_CFG_CLK_DIV_Msk, AUDCODEC_ADC_CFG_CLK_DIV_Pos)
1165 | MAKE_REG_VAL(cfg->clk_src_sel, AUDCODEC_ADC_CFG_CLK_SRC_SEL_Msk, AUDCODEC_ADC_CFG_CLK_SRC_SEL_Pos)
1166 | MAKE_REG_VAL(cfg->op_mode, AUDCODEC_ADC_CFG_OP_MODE_Msk, AUDCODEC_ADC_CFG_OP_MODE_Pos)
1167 | MAKE_REG_VAL(cfg->osr_sel, AUDCODEC_ADC_CFG_OSR_SEL_Msk, AUDCODEC_ADC_CFG_OSR_SEL_Pos);
1168
1169 hacodec->Instance->CFG = value;
1170
1171 return HAL_OK;
1172 }
1173 #endif
HAL_AUDCODEC_DMA_Init(DMA_HandleTypeDef * hdma,uint8_t from_mem)1174 static void HAL_AUDCODEC_DMA_Init(DMA_HandleTypeDef *hdma, uint8_t from_mem)
1175 {
1176 // configure TX DMA, instance and request should be initialized by caller
1177 if (hdma != NULL)
1178 {
1179 if (from_mem)
1180 hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
1181 else
1182 hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
1183 hdma->Init.PeriphInc = DMA_PINC_DISABLE;
1184 hdma->Init.MemInc = DMA_MINC_ENABLE;
1185 hdma->Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
1186 hdma->Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
1187 /*Mode will be changed, based on destination select*/
1188 hdma->Init.Mode = DMA_CIRCULAR; //DMA_CIRCULAR; //DMA_CIRCULAR; //DMA_NORMAL;
1189 hdma->Init.Priority = DMA_PRIORITY_HIGH;
1190 hdma->Init.BurstSize = 0;
1191 //hdma->Parent = (void *)hacodec;
1192
1193 HAL_DMA_Init(hdma);
1194 }
1195
1196 }
1197
HAL_AUDCODEC_Transmit_DMA(AUDCODEC_HandleTypeDef * hacodec,uint8_t * pData,uint32_t Size,uint32_t did)1198 HAL_StatusTypeDef HAL_AUDCODEC_Transmit_DMA(AUDCODEC_HandleTypeDef *hacodec, uint8_t *pData, uint32_t Size, uint32_t did)
1199 {
1200 uint32_t txentry;
1201 uint32_t *dmamask;
1202
1203 if ((hacodec == NULL) || (hacodec->hdma[did] == NULL) || (pData == NULL) || (Size == 0U) || (did > HAL_AUDCODEC_DAC_CH1))
1204 {
1205 return HAL_ERROR;
1206 }
1207
1208 /* Process Locked */
1209 __HAL_LOCK(hacodec);
1210
1211 if (did == HAL_AUDCODEC_DAC_CH0) // channel 0
1212 {
1213 txentry = (uint32_t)(&hacodec->Instance->DAC_CH0_ENTRY);
1214 dmamask = (uint32_t *)((uint32_t)&hacodec->Instance->DAC_CH0_CFG);
1215 }
1216 else
1217 {
1218 txentry = (uint32_t)(&hacodec->Instance->DAC_CH1_ENTRY);
1219 dmamask = (uint32_t *)((uint32_t)&hacodec->Instance->DAC_CH1_CFG);
1220 }
1221
1222 if (!(hacodec->State[did] & HAL_AUDCODEC_STATE_BUSY_TX))
1223 {
1224 hacodec->buf[did] = pData;
1225 hacodec->State[did] |= HAL_AUDCODEC_STATE_BUSY_TX;
1226 hacodec->ErrorCode = HAL_AUDCODEC_ERROR_NONE;
1227
1228
1229 // DMA transmit as 32 bits
1230 hacodec->dataSize[did] = Size >> 2;
1231
1232 /* Set the AUDCODEC Tx DMA Half transfert complete callback */
1233 hacodec->hdma[did]->XferHalfCpltCallback = AUDCODEC_DMATxHalfCplt;
1234 __HAL_DMA_SET_CIRCLUAR_MODE(hacodec->hdma[did], DMA_CIRCULAR);
1235
1236 /* Set the AUDCODEC Tx DMA transfert complete callback */
1237 hacodec->hdma[did]->XferCpltCallback = AUDCODEC_DMATxCplt;
1238
1239 /* Set the DMA error callback */
1240 hacodec->hdma[did]->XferErrorCallback = AUDCODEC_DMAError;
1241
1242 /* Enable the Tx DMA Channel */
1243 HAL_DMA_Start_IT(hacodec->hdma[did], (uint32_t)hacodec->buf[did], txentry, hacodec->dataSize[did]);
1244
1245 /* Check if the AUDCODEC Tx request is already enabled */
1246 *dmamask &= ~AUDCODEC_DAC_CH0_CFG_DMA_EN_Msk;
1247 *dmamask |= AUDCODEC_DAC_CH0_CFG_DMA_EN;
1248 /* Check if the AUDCODEC is already enabled */
1249 //__HAL_AUDCODEC_ENABLE(hacodec);
1250
1251 /* Process Unlocked */
1252 __HAL_UNLOCK(hacodec);
1253
1254 return HAL_OK;
1255 }
1256 else
1257 {
1258 /* Process Unlocked */
1259 __HAL_UNLOCK(hacodec);
1260 return HAL_BUSY;
1261 }
1262
1263 return HAL_OK;
1264
1265 }
1266
HAL_AUDCODEC_Receive_DMA(AUDCODEC_HandleTypeDef * hacodec,uint8_t * pData,uint32_t Size,uint32_t did)1267 HAL_StatusTypeDef HAL_AUDCODEC_Receive_DMA(AUDCODEC_HandleTypeDef *hacodec, uint8_t *pData, uint32_t Size, uint32_t did)
1268 {
1269 uint32_t rxentry;
1270 uint32_t *dmamask;
1271
1272 /* check dma handle */
1273 if ((hacodec == NULL) || (hacodec->hdma[did] == NULL) || (pData == NULL) || (Size == 0U) || (did > HAL_AUDCODEC_INSTANC_CNT) || (did < HAL_AUDCODEC_ADC_CH0))
1274 {
1275 return HAL_ERROR;
1276 }
1277
1278 if (hacodec->State[did] & HAL_AUDCODEC_STATE_BUSY_RX)
1279 {
1280 return HAL_BUSY;
1281 }
1282
1283 /* Process Locked */
1284 __HAL_LOCK(hacodec);
1285
1286 if (did == HAL_AUDCODEC_ADC_CH0)
1287 {
1288 rxentry = (uint32_t)(&hacodec->Instance->ADC_CH0_ENTRY);
1289 dmamask = (uint32_t *)((uint32_t)&hacodec->Instance->ADC_CH0_CFG);
1290 }
1291 else
1292 {
1293 rxentry = (uint32_t)(&hacodec->Instance->ADC_CH1_ENTRY);
1294 dmamask = (uint32_t *)((uint32_t)&hacodec->Instance->ADC_CH1_CFG);
1295 }
1296
1297 /* Set the transaction information */
1298 hacodec->State[did] = HAL_AUDCODEC_STATE_BUSY_RX;
1299 hacodec->ErrorCode = HAL_AUDCODEC_ERROR_NONE;
1300
1301 hacodec->buf[did] = pData;
1302 hacodec->dataSize[did] = Size >> 2;
1303
1304 /* Set the AUDCODEC RxDMA Half transfer complete callback */
1305 hacodec->hdma[did]->XferHalfCpltCallback = AUDCODEC_DMAHalfRxCplt;
1306 __HAL_DMA_SET_CIRCLUAR_MODE(hacodec->hdma[did], DMA_CIRCULAR);
1307
1308 /* Set the AUDCODEC Rx DMA transfer complete callback */
1309 hacodec->hdma[did]->XferCpltCallback = AUDCODEC_DMARxCplt;
1310
1311 /* Set the AUDCODEC error callback */
1312 hacodec->hdma[did]->XferErrorCallback = AUDCODEC_DMAError;
1313
1314 /* Set the AUDCODEC AbortCpltCallback */
1315 hacodec->hdma[did]->XferAbortCallback = NULL;
1316
1317
1318 /* Enable the Rx DMA Stream/Channel */
1319 HAL_DMA_Start_IT(hacodec->hdma[did], (uint32_t)(rxentry), (uint32_t)hacodec->buf[did], hacodec->dataSize[did]);
1320
1321 /* Check if the AUDCODEC Rx request is already enabled */
1322 *dmamask &= ~AUDCODEC_ADC_CH0_CFG_DMA_EN_Msk;
1323 *dmamask |= AUDCODEC_ADC_CH0_CFG_DMA_EN;
1324 /* Check if the AUDCODEC is already enabled */
1325 //__HAL_AUDCODEC_ENABLE(hacodec);
1326
1327 /* Process Unlocked */
1328 __HAL_UNLOCK(hacodec);
1329
1330 return HAL_OK;
1331 }
1332
1333
HAL_AUDCODEC_DMAStop(AUDCODEC_HandleTypeDef * hacodec,uint32_t did)1334 HAL_StatusTypeDef HAL_AUDCODEC_DMAStop(AUDCODEC_HandleTypeDef *hacodec, uint32_t did)
1335 {
1336 /* Abort the DMA rx/tx Stream/Channel */
1337 if (hacodec->hdma[did] != NULL)
1338 {
1339 //__HAL_DMA_DISABLE(hacodec->hdma[did]);
1340 HAL_DMA_Abort(hacodec->hdma[did]);
1341 }
1342
1343 switch (did)
1344 {
1345 case HAL_AUDCODEC_DAC_CH0:
1346 hacodec->Instance->DAC_CH0_CFG &= (~AUDCODEC_DAC_CH0_CFG_DMA_EN);
1347 break;
1348 case HAL_AUDCODEC_DAC_CH1:
1349 hacodec->Instance->DAC_CH1_CFG &= (~AUDCODEC_DAC_CH1_CFG_DMA_EN);
1350 break;
1351 case HAL_AUDCODEC_ADC_CH0:
1352 hacodec->Instance->ADC_CH0_CFG &= (~AUDCODEC_ADC_CH0_CFG_DMA_EN);
1353 break;
1354 case HAL_AUDCODEC_ADC_CH1:
1355 hacodec->Instance->ADC_CH1_CFG &= (~AUDCODEC_ADC_CH1_CFG_DMA_EN);
1356 break;
1357 }
1358 //__HAL_AUDCODEC_DISABLE(hacodec);
1359
1360 //hacodec->State = HAL_AUDCODEC_STATE_READY;
1361
1362 return HAL_OK;
1363 }
1364
HAL_AUDCODEC_TxCpltCallback(AUDCODEC_HandleTypeDef * hacodec,int cid)1365 __weak void HAL_AUDCODEC_TxCpltCallback(AUDCODEC_HandleTypeDef *hacodec, int cid)
1366 {
1367 /* Prevent unused argument(s) compilation warning */
1368 UNUSED(hacodec);
1369 UNUSED(cid);
1370
1371 /* NOTE : This function should not be modified, when the callback is needed,
1372 the HAL_AUDCODEC_TxHalfCpltCallback should be implemented in the user file
1373 */
1374
1375 }
1376
HAL_AUDCODEC_TxHalfCpltCallback(AUDCODEC_HandleTypeDef * hacodec,int cid)1377 __weak void HAL_AUDCODEC_TxHalfCpltCallback(AUDCODEC_HandleTypeDef *hacodec, int cid)
1378 {
1379 /* Prevent unused argument(s) compilation warning */
1380 UNUSED(hacodec);
1381 UNUSED(cid);
1382
1383 /* NOTE : This function should not be modified, when the callback is needed,
1384 the HAL_AUDCODEC_TxHalfCpltCallback should be implemented in the user file
1385 */
1386
1387 }
1388
HAL_AUDCODEC_RxHalfCpltCallback(AUDCODEC_HandleTypeDef * hacodec,int cid)1389 __weak void HAL_AUDCODEC_RxHalfCpltCallback(AUDCODEC_HandleTypeDef *hacodec, int cid)
1390 {
1391 /* Prevent unused argument(s) compilation warning */
1392 UNUSED(hacodec);
1393 UNUSED(cid);
1394
1395 /* NOTE : This function should not be modified, when the callback is needed,
1396 the HAL_AUDCODEC_RxHalfCpltCallback should be implemented in the user file
1397 */
1398 }
1399
HAL_AUDCODEC_RxCpltCallback(AUDCODEC_HandleTypeDef * hacodec,int cid)1400 __weak void HAL_AUDCODEC_RxCpltCallback(AUDCODEC_HandleTypeDef *hacodec, int cid)
1401 {
1402 /* Prevent unused argument(s) compilation warning */
1403 UNUSED(hacodec);
1404 UNUSED(cid);
1405
1406 /* NOTE : This function should not be modified, when the callback is needed,
1407 the HAL_AUDCODEC_RxCpltCallback should be implemented in the user file
1408 */
1409 }
1410
HAL_AUDCODEC_ErrorCallback(AUDCODEC_HandleTypeDef * hacodec,int cid)1411 __weak void HAL_AUDCODEC_ErrorCallback(AUDCODEC_HandleTypeDef *hacodec, int cid)
1412 {
1413 /* Prevent unused argument(s) compilation warning */
1414 UNUSED(hacodec);
1415 UNUSED(cid);
1416
1417 /* NOTE : This function should not be modified, when the callback is needed,
1418 the HAL_PDM_ErrorCallback should be implemented in the user file
1419 */
1420 }
1421
HAL_AUDCODEC_AbortCpltCallback(AUDCODEC_HandleTypeDef * hacodec,int cid)1422 __weak void HAL_AUDCODEC_AbortCpltCallback(AUDCODEC_HandleTypeDef *hacodec, int cid)
1423 {
1424 /* Prevent unused argument(s) compilation warning */
1425 UNUSED(hacodec);
1426 UNUSED(cid);
1427
1428 /* NOTE : This function should not be modified, when the callback is needed,
1429 the HAL_PDM_AbortCpltCallback should be implemented in the user file
1430 */
1431 }
1432
1433
AUDCODEC_DMATxCplt(DMA_HandleTypeDef * hdma)1434 static void AUDCODEC_DMATxCplt(DMA_HandleTypeDef *hdma)
1435 {
1436 AUDCODEC_HandleTypeDef *aprc = (AUDCODEC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1437
1438 int i;
1439 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
1440 if (aprc->hdma[i] == hdma)
1441 break;
1442 if (i >= HAL_AUDCODEC_INSTANC_CNT) // something wrong
1443 return;
1444
1445 HAL_AUDCODEC_TxCpltCallback(aprc, i);
1446 }
1447
1448 /**
1449 * @brief DMA I2S transmit process half complete callback
1450 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
1451 * the configuration information for the specified DMA module.
1452 * @retval None
1453 */
AUDCODEC_DMATxHalfCplt(DMA_HandleTypeDef * hdma)1454 static void AUDCODEC_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
1455 {
1456 AUDCODEC_HandleTypeDef *aprc = (AUDCODEC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1457 int i;
1458 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
1459 if (aprc->hdma[i] == hdma)
1460 break;
1461 if (i >= HAL_AUDCODEC_INSTANC_CNT) // something wrong
1462 return;
1463
1464 HAL_AUDCODEC_TxHalfCpltCallback(aprc, i);
1465 }
1466
AUDCODEC_DMARxCplt(DMA_HandleTypeDef * hdma)1467 static void AUDCODEC_DMARxCplt(DMA_HandleTypeDef *hdma)
1468 {
1469 AUDCODEC_HandleTypeDef *aprc = (AUDCODEC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1470 int i;
1471
1472 for (i = HAL_AUDCODEC_DAC_CH0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
1473 if (aprc->hdma[i] == hdma)
1474 break;
1475 if (i >= HAL_AUDCODEC_INSTANC_CNT)
1476 return;
1477
1478 HAL_AUDCODEC_RxCpltCallback(aprc, i);
1479
1480 }
1481
1482 /**
1483 * @brief DMA PDM half receive process complete callback
1484 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1485 * the configuration information for the specified DMA module.
1486 * @retval None
1487 */
AUDCODEC_DMAHalfRxCplt(DMA_HandleTypeDef * hdma)1488 static void AUDCODEC_DMAHalfRxCplt(DMA_HandleTypeDef *hdma)
1489 {
1490 AUDCODEC_HandleTypeDef *aprc = (AUDCODEC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1491 int i;
1492 for (i = HAL_AUDCODEC_DAC_CH0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
1493 if (aprc->hdma[i] == hdma)
1494 break;
1495 if (i >= HAL_AUDCODEC_INSTANC_CNT)
1496 return;
1497 HAL_AUDCODEC_RxHalfCpltCallback(aprc, i);
1498 }
1499
1500
1501 /**
1502 * @brief DMA PDM communication error callback.
1503 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1504 * the configuration information for the specified DMA module.
1505 * @retval None
1506 */
AUDCODEC_DMAError(DMA_HandleTypeDef * hdma)1507 static void AUDCODEC_DMAError(DMA_HandleTypeDef *hdma)
1508 {
1509 AUDCODEC_HandleTypeDef *aprc = (AUDCODEC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1510 int i;
1511 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
1512 if (aprc->hdma[i] == hdma)
1513 break;
1514 if (i >= HAL_AUDCODEC_INSTANC_CNT)
1515 return;
1516
1517 aprc->State[i] = HAL_AUDCODEC_STATE_READY;
1518 HAL_AUDCODEC_ErrorCallback(aprc, i);
1519 }
1520
1521 #endif /* HAL_AUDCODEC_MODULE_ENABLED */
