1 /*
2 * SPDX-FileCopyrightText: 2019-2025 SiFli Technologies(Nanjing) Co., Ltd
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /* Includes ------------------------------------------------------------------*/
8 #include "bf0_hal.h"
9
10 #if defined(HAL_AUDCODEC_MODULE_ENABLED)||defined(_SIFLI_DOXYGEN_)
11 //#define DBG_LEVEL DBG_LOG
12 //#define LOG_TAG "hal.audcodec"
13 //#include "drv_log.h"
14
15 #ifdef SF32LB58X
16 #define BSP_ENABLE_DAC2 1
17 #endif
18
19
20 static void HAL_AUDCODEC_DMA_Init(DMA_HandleTypeDef *hdma, uint8_t from_mem);
21
22 static void AUDCODEC_DMATxCplt(DMA_HandleTypeDef *hdma);
23 static void AUDCODEC_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
24 static void AUDCODEC_DMARxCplt(DMA_HandleTypeDef *hdma);
25 static void AUDCODEC_DMAHalfRxCplt(DMA_HandleTypeDef *hdma);
26 static void AUDCODEC_DMAError(DMA_HandleTypeDef *hdma);
27
28 uint8_t g_pll_state = 0;
29 uint8_t g_pll_freq_type = 0;
30 static uint16_t pll_cfg2_reset = 0;
31
set_pll_state(uint8_t state)32 void set_pll_state(uint8_t state)
33 {
34 g_pll_state = state;
35 }
get_pll_state()36 uint8_t get_pll_state()
37 {
38 return g_pll_state;
39 }
set_pll_freq_type(uint8_t type)40 void set_pll_freq_type(uint8_t type)
41 {
42 g_pll_freq_type = type;
43 }
get_pll_freq_type()44 uint8_t get_pll_freq_type()
45 {
46 return g_pll_freq_type;
47 }
48 // need updata drv_audcodec if modify this function
updata_pll_freq(uint8_t type)49 __weak int updata_pll_freq(uint8_t type) //type 0: 16k 1024 series 1:44.1k 1024 series 2:16k 1000 series 3: 44.1k 1000 series
50 {
51 hwp_audcodec_lp->PLL_CFG2 |= AUDCODEC_LP_PLL_CFG2_RSTB;
52 // wait 50us
53 HAL_Delay_us(50);
54 if (0 == type)// set pll to 49.152M [(fcw+3)+sdin/2^20]*6M
55 {
56 hwp_audcodec_lp->PLL_CFG3 = (201327 << AUDCODEC_LP_PLL_CFG3_SDIN_Pos) |
57 (5 << AUDCODEC_LP_PLL_CFG3_FCW_Pos) |
58 (0 << AUDCODEC_LP_PLL_CFG3_SDM_UPDATE_Pos) |
59 (1 << AUDCODEC_LP_PLL_CFG3_SDMIN_BYPASS_Pos) |
60 (0 << AUDCODEC_LP_PLL_CFG3_SDM_MODE_Pos) |
61 (0 << AUDCODEC_LP_PLL_CFG3_EN_SDM_DITHER_Pos) |
62 (0 << AUDCODEC_LP_PLL_CFG3_SDM_DITHER_Pos) |
63 (1 << AUDCODEC_LP_PLL_CFG3_EN_SDM_Pos) |
64 (0 << AUDCODEC_LP_PLL_CFG3_SDMCLK_POL_Pos);
65 }
66 else if (1 == type)// set pll to 45.1584M
67 {
68
69 hwp_audcodec_lp->PLL_CFG3 = (551970 << AUDCODEC_LP_PLL_CFG3_SDIN_Pos) |
70 (4 << AUDCODEC_LP_PLL_CFG3_FCW_Pos) |
71 (0 << AUDCODEC_LP_PLL_CFG3_SDM_UPDATE_Pos) |
72 (1 << AUDCODEC_LP_PLL_CFG3_SDMIN_BYPASS_Pos) |
73 (0 << AUDCODEC_LP_PLL_CFG3_SDM_MODE_Pos) |
74 (0 << AUDCODEC_LP_PLL_CFG3_EN_SDM_DITHER_Pos) |
75 (0 << AUDCODEC_LP_PLL_CFG3_SDM_DITHER_Pos) |
76 (1 << AUDCODEC_LP_PLL_CFG3_EN_SDM_Pos) |
77 (0 << AUDCODEC_LP_PLL_CFG3_SDMCLK_POL_Pos);
78 }
79 else if (3 == type)// set pll to 44.1M
80 {
81
82 hwp_audcodec_lp->PLL_CFG3 = (0x5999A << AUDCODEC_LP_PLL_CFG3_SDIN_Pos) |
83 (4 << AUDCODEC_LP_PLL_CFG3_FCW_Pos) |
84 (0 << AUDCODEC_LP_PLL_CFG3_SDM_UPDATE_Pos) |
85 (1 << AUDCODEC_LP_PLL_CFG3_SDMIN_BYPASS_Pos) |
86 (0 << AUDCODEC_LP_PLL_CFG3_SDM_MODE_Pos) |
87 (0 << AUDCODEC_LP_PLL_CFG3_EN_SDM_DITHER_Pos) |
88 (0 << AUDCODEC_LP_PLL_CFG3_SDM_DITHER_Pos) |
89 (1 << AUDCODEC_LP_PLL_CFG3_EN_SDM_Pos) |
90 (0 << AUDCODEC_LP_PLL_CFG3_SDMCLK_POL_Pos);
91 }
92 else
93 {
94 //RT_ASSERT(0);
95 }
96 hwp_audcodec_lp->PLL_CFG3 |= AUDCODEC_LP_PLL_CFG3_SDM_UPDATE;
97 hwp_audcodec_lp->PLL_CFG3 &= ~AUDCODEC_LP_PLL_CFG3_SDMIN_BYPASS;
98 hwp_audcodec_lp->PLL_CFG2 &= ~AUDCODEC_LP_PLL_CFG2_RSTB;
99 // wait 50us
100 HAL_Delay_us(50);
101 hwp_audcodec_lp->PLL_CFG2 |= AUDCODEC_LP_PLL_CFG2_RSTB;
102 // check pll lock
103 //wait(2500);
104 HAL_Delay_us(50);
105
106 hwp_audcodec_lp->PLL_CFG1 |= AUDCODEC_LP_PLL_CFG1_CSD_EN | AUDCODEC_LP_PLL_CFG1_CSD_RST;
107 HAL_Delay_us(50);
108 hwp_audcodec_lp->PLL_CFG1 &= ~AUDCODEC_LP_PLL_CFG1_CSD_RST;
109 if (hwp_audcodec_lp->PLL_STAT & AUDCODEC_LP_PLL_STAT_UNLOCK_Msk)
110 {
111 HAL_DBG_printf("pll lock fail! freq_type:%d\n", type);
112 return -1;
113 }
114 else
115 {
116 HAL_DBG_printf("pll lock! freq_type:%d\n", type);
117 hwp_audcodec_lp->PLL_CFG1 &= ~AUDCODEC_LP_PLL_CFG1_CSD_EN;
118 set_pll_freq_type(type);
119 }
120 return 0;
121 }
122
123 /**
124 * @brief enable PLL function
125 * @param freq - frequency
126 * @param type - 0:1024 series, 1:1000 series
127 * @return
128 */
bf0_enable_pll(uint32_t freq,uint8_t type)129 __weak int bf0_enable_pll(uint32_t freq, uint8_t type)// need updata drv_audcodec if modify this function
130 {
131 uint8_t freq_type;
132 uint8_t test_result = -1;
133 uint32_t pll_cnt;
134 uint32_t xtal_cnt;
135 uint32_t fc_vco;
136 uint32_t fc_vco_min;
137 uint32_t fc_vco_max;
138 uint32_t delta_cnt;
139 uint32_t delta_cnt_min;
140 uint32_t delta_cnt_max;
141 uint32_t delta_fc_vco;
142 uint32_t target_cnt = 1838;
143
144 fc_vco = 16;
145 delta_fc_vco = 8;
146 test_result = 0;
147
148 freq_type = type << 1;
149 if ((freq == 44100) || (freq == 22050) || (freq == 11025))
150 {
151 freq_type += 1;
152 }
153
154 HAL_DBG_printf("PLL_ENABLE pll_state:%d, freq_type:%d\n", get_pll_state(), freq_type);
155
156 if (0 == get_pll_state())
157 {
158 hwp_pmuc->HXT_CR1 |= PMUC_HXT_CR1_BUF_AUD_EN;
159 hwp_hpsys_rcc->ENR2 |= HPSYS_RCC_ENR2_AUDCODEC;
160 hwp_lpsys_rcc->ENR1 |= LPSYS_RCC_ENR1_AUDCODEC;
161
162 //-----------------step 2------------------//
163 // turn on bandgap
164 // turn on BG sample clock
165 hwp_audcodec_lp->BG_CFG1 = 48000;
166 hwp_audcodec_lp->BG_CFG2 = 48000000;
167 // turn on bandgap
168 hwp_audcodec_lp->BG_CFG0 &= ~AUDCODEC_LP_BG_CFG0_EN_RCFLT;
169 hwp_audcodec_lp->BG_CFG0 |= AUDCODEC_LP_BG_CFG0_EN;
170 HAL_Delay_us(100);
171 //hwp_audcodec_lp->BG_CFG0 |= AUDCODEC_LP_BG_CFG0_EN_SMPL;
172
173 //-----------------step 3------------------//
174 // pll calibration
175 // wait 100us
176 //wait(5000);
177 HAL_Delay_us(100);
178
179 hwp_audcodec_lp->PLL_CFG0 |= AUDCODEC_LP_PLL_CFG0_EN_IARY;
180 hwp_audcodec_lp->PLL_CFG0 |= AUDCODEC_LP_PLL_CFG0_EN_VCO;
181 hwp_audcodec_lp->PLL_CFG0 |= AUDCODEC_LP_PLL_CFG0_EN_ANA;
182 hwp_audcodec_lp->PLL_CFG0 &= ~AUDCODEC_LP_PLL_CFG0_ICP_SEL_Msk;
183 hwp_audcodec_lp->PLL_CFG0 |= (8 << AUDCODEC_LP_PLL_CFG0_ICP_SEL_Pos);
184 hwp_audcodec_lp->PLL_CFG2 |= AUDCODEC_LP_PLL_CFG2_EN_DIG;
185 hwp_audcodec_lp->PLL_CFG3 |= AUDCODEC_LP_PLL_CFG3_EN_SDM;
186 hwp_audcodec_lp->PLL_CFG4 |= AUDCODEC_LP_PLL_CFG4_EN_CLK_DIG;
187 // wait 50us
188 //wait(2500);
189 HAL_Delay_us(50);
190 // VCO freq calibration
191 hwp_audcodec_lp->PLL_CFG0 |= AUDCODEC_LP_PLL_CFG0_OPEN;
192 hwp_audcodec_lp->PLL_CFG2 |= AUDCODEC_LP_PLL_CFG2_EN_LF_VCIN;
193 hwp_audcodec_lp->PLL_CAL_CFG = (0 << AUDCODEC_LP_PLL_CAL_CFG_EN_Pos) |
194 (2000 << AUDCODEC_LP_PLL_CAL_CFG_LEN_Pos);
195 // setup calibration and run
196 // target pll_cnt = ceil(46MHz/48MHz*2000)+1 = 1918
197 // target difference between pll_cnt and xtal_cnt should be less than 1
198 while (delta_fc_vco != 0)
199 {
200 hwp_audcodec_lp->PLL_CFG0 &= ~AUDCODEC_LP_PLL_CFG0_FC_VCO;
201 hwp_audcodec_lp->PLL_CFG0 |= (fc_vco << AUDCODEC_LP_PLL_CFG0_FC_VCO_Pos);
202 hwp_audcodec_lp->PLL_CAL_CFG |= AUDCODEC_LP_PLL_CAL_CFG_EN;
203 while (!(hwp_audcodec_lp->PLL_CAL_CFG & AUDCODEC_LP_PLL_CAL_CFG_DONE_Msk));
204 pll_cnt = (hwp_audcodec_lp->PLL_CAL_RESULT >> AUDCODEC_LP_PLL_CAL_RESULT_PLL_CNT_Pos);
205 xtal_cnt = (hwp_audcodec_lp->PLL_CAL_RESULT & AUDCODEC_LP_PLL_CAL_RESULT_XTAL_CNT_Msk);
206 hwp_audcodec_lp->PLL_CAL_CFG &= ~AUDCODEC_LP_PLL_CAL_CFG_EN;
207 if (pll_cnt < target_cnt)
208 {
209 fc_vco = fc_vco + delta_fc_vco;
210 delta_cnt = target_cnt - pll_cnt;
211 }
212 else if (pll_cnt > target_cnt)
213 {
214 fc_vco = fc_vco - delta_fc_vco;
215 delta_cnt = pll_cnt - target_cnt;
216 }
217 delta_fc_vco = delta_fc_vco >> 1;
218 }
219 HAL_DBG_printf("call par CFG1(%x)\r\n", hwp_audcodec_lp->PLL_CFG1);
220 fc_vco_min = fc_vco - 1;
221 if (fc_vco == 31)
222 {
223 fc_vco_max = fc_vco;
224 }
225 else
226 {
227 fc_vco_max = fc_vco + 1;
228 }
229
230 hwp_audcodec_lp->PLL_CFG0 &= ~AUDCODEC_LP_PLL_CFG0_FC_VCO;
231 hwp_audcodec_lp->PLL_CFG0 |= (fc_vco_min << AUDCODEC_LP_PLL_CFG0_FC_VCO_Pos);
232 hwp_audcodec_lp->PLL_CAL_CFG |= AUDCODEC_LP_PLL_CAL_CFG_EN;
233 HAL_DBG_printf("fc %d, xtal %d, pll %d\r\n", fc_vco, xtal_cnt, pll_cnt);
234 while (!(hwp_audcodec_lp->PLL_CAL_CFG & AUDCODEC_LP_PLL_CAL_CFG_DONE_Msk));
235 pll_cnt = (hwp_audcodec_lp->PLL_CAL_RESULT >> AUDCODEC_LP_PLL_CAL_RESULT_PLL_CNT_Pos);
236 hwp_audcodec_lp->PLL_CAL_CFG &= ~AUDCODEC_LP_PLL_CAL_CFG_EN;
237 if (pll_cnt < target_cnt)
238 {
239 delta_cnt_min = target_cnt - pll_cnt;
240 }
241 else if (pll_cnt > target_cnt)
242 {
243 delta_cnt_min = pll_cnt - target_cnt;
244 }
245
246 hwp_audcodec_lp->PLL_CFG0 &= ~AUDCODEC_LP_PLL_CFG0_FC_VCO;
247 hwp_audcodec_lp->PLL_CFG0 |= (fc_vco_max << AUDCODEC_LP_PLL_CFG0_FC_VCO_Pos);
248 hwp_audcodec_lp->PLL_CAL_CFG |= AUDCODEC_LP_PLL_CAL_CFG_EN;
249 while (!(hwp_audcodec_lp->PLL_CAL_CFG & AUDCODEC_LP_PLL_CAL_CFG_DONE_Msk));
250 pll_cnt = (hwp_audcodec_lp->PLL_CAL_RESULT >> AUDCODEC_LP_PLL_CAL_RESULT_PLL_CNT_Pos);
251 hwp_audcodec_lp->PLL_CAL_CFG &= ~AUDCODEC_LP_PLL_CAL_CFG_EN;
252 if (pll_cnt < target_cnt)
253 {
254 delta_cnt_max = target_cnt - pll_cnt;
255 }
256 else if (pll_cnt > target_cnt)
257 {
258 delta_cnt_max = pll_cnt - target_cnt;
259 }
260
261 hwp_audcodec_lp->PLL_CFG0 &= ~AUDCODEC_LP_PLL_CFG0_FC_VCO;
262 #if 0
263 //only for SF32LB58X a0
264 if (delta_cnt_min <= delta_cnt && delta_cnt_min <= delta_cnt_max)
265 {
266 fc_vco_min = (fc_vco_min < 2) ? 2 : fc_vco_min;
267 hwp_audcodec_lp->PLL_CFG0 |= ((fc_vco_min - 2) << AUDCODEC_LP_PLL_CFG0_FC_VCO_Pos);
268 }
269 else if (delta_cnt_max <= delta_cnt && delta_cnt_max <= delta_cnt_min)
270 {
271 fc_vco_max = (fc_vco_max < 2) ? 2 : fc_vco_max;
272 hwp_audcodec_lp->PLL_CFG0 |= ((fc_vco_max - 2) << AUDCODEC_LP_PLL_CFG0_FC_VCO_Pos);
273 }
274 else
275 {
276 fc_vco = (fc_vco < 2) ? 2 : fc_vco;
277 hwp_audcodec_lp->PLL_CFG0 |= ((fc_vco - 2) << AUDCODEC_LP_PLL_CFG0_FC_VCO_Pos);
278 }
279 #else
280 if (delta_cnt_min <= delta_cnt && delta_cnt_min <= delta_cnt_max)
281 {
282 hwp_audcodec_lp->PLL_CFG0 |= (fc_vco_min << AUDCODEC_LP_PLL_CFG0_FC_VCO_Pos);
283 }
284 else if (delta_cnt_max <= delta_cnt && delta_cnt_max <= delta_cnt_min)
285 {
286 hwp_audcodec_lp->PLL_CFG0 |= (fc_vco_max << AUDCODEC_LP_PLL_CFG0_FC_VCO_Pos);
287 }
288 else
289 {
290 hwp_audcodec_lp->PLL_CFG0 |= (fc_vco << AUDCODEC_LP_PLL_CFG0_FC_VCO_Pos);
291 }
292 #endif
293 hwp_audcodec_lp->PLL_CFG2 &= ~AUDCODEC_LP_PLL_CFG2_EN_LF_VCIN;
294 hwp_audcodec_lp->PLL_CFG0 &= ~AUDCODEC_LP_PLL_CFG0_OPEN;
295
296 //-----------------step 4------------------//
297 // set pll to 49.152M
298 // wait 50us
299 //wait(2500);
300 HAL_Delay_us(50);
301
302 do
303 {
304 test_result = updata_pll_freq(freq_type);
305 }
306 while (test_result != 0);
307
308 set_pll_state(1);
309 set_pll_freq_type(freq_type);
310 }
311 else if (freq_type != get_pll_freq_type())
312 {
313 do
314 {
315 test_result = updata_pll_freq(freq_type);
316 }
317 while (test_result != 0);
318 set_pll_freq_type(freq_type);
319 }
320
321
322 return test_result;
323 }
bf0_disable_pll()324 __weak void bf0_disable_pll()
325 {
326 HAL_TURN_OFF_PLL();
327 set_pll_state(0);
328 HAL_DBG_printf("PLL disable\n");
329 }
330
HAL_AUDCODEC_Config_Analog_DACPath(AUDCODE_DAC_CLK_CONFIG_TYPE * cfg)331 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Config_Analog_DACPath(AUDCODE_DAC_CLK_CONFIG_TYPE *cfg)
332 {
333 HAL_DBG_printf("config Aanlog DACPath\n");
334 //-----------------step 5------------------//
335 // turn on refgen
336 // hwp_audcodec_lp->BG_CFG0 &= ~AUDCODEC_LP_BG_CFG0_VREF_SEL;
337 // hwp_audcodec_lp->BG_CFG0 |= (7 << AUDCODEC_LP_BG_CFG0_VREF_SEL_Pos); // AVDD = 3.3V
338 //hwp_audcodec_lp->BG_CFG0 |= (2 << AUDCODEC_LP_BG_CFG0_VREF_SEL_Pos); // AVDD = 1.8V
339 // hwp_audcodec_lp->REFGEN_CFG &= ~AUDCODEC_LP_REFGEN_CFG_EN_CHOP;
340 // hwp_audcodec_lp->REFGEN_CFG |= AUDCODEC_LP_REFGEN_CFG_EN;
341 // hwp_audcodec_lp->PLL_CFG5 = AUDCODEC_LP_PLL_CFG5_EN_CLK_CHOP_BG |
342 // AUDCODEC_LP_PLL_CFG5_EN_CLK_CHOP_REFGEN;
343 // HAL_Delay(2);// wait 2ms
344
345 //-----------------step 6------------------//
346 // turn on hp dac1 and dac2 analog
347 // dac1 and dac2 clock
348 hwp_audcodec_lp->PLL_CFG4 = (cfg->divb_clk_chop_dac << AUDCODEC_LP_PLL_CFG4_DIVB_CLK_CHOP_DAC_Pos) |
349 (cfg->diva_clk_chop_dac << AUDCODEC_LP_PLL_CFG4_DIVA_CLK_CHOP_DAC_Pos) |
350 (1 << AUDCODEC_LP_PLL_CFG4_EN_CLK_CHOP_DAC_Pos) |
351 (cfg->diva_clk_dac << AUDCODEC_LP_PLL_CFG4_DIVA_CLK_DAC_Pos) |
352 (1 << AUDCODEC_LP_PLL_CFG4_EN_CLK_DAC_Pos) |
353 (cfg->sel_clk_dac_source << AUDCODEC_LP_PLL_CFG4_SEL_CLK_DAC_SOURCE_Pos) | // select xtal
354 (0 << AUDCODEC_LP_PLL_CFG4_SEL_CLK_DIG_Pos) |
355 (1 << AUDCODEC_LP_PLL_CFG4_CLK_DIG_STR_Pos) |
356 (2 << AUDCODEC_LP_PLL_CFG4_DIVA_CLK_DIG_Pos) |
357 (1 << AUDCODEC_LP_PLL_CFG4_EN_CLK_DIG_Pos);
358
359 hwp_audcodec_lp->PLL_CFG5 = (2 << AUDCODEC_LP_PLL_CFG5_DIVB_CLK_CHOP_BG_Pos) |
360 (cfg->diva_clk_chop_bg << AUDCODEC_LP_PLL_CFG5_DIVA_CLK_CHOP_BG_Pos) |
361 (1 << AUDCODEC_LP_PLL_CFG5_EN_CLK_CHOP_BG_Pos) |
362 (2 << AUDCODEC_LP_PLL_CFG5_DIVB_CLK_CHOP_REFGEN_Pos) |
363 (cfg->diva_clk_chop_refgen << AUDCODEC_LP_PLL_CFG5_DIVA_CLK_CHOP_REFGEN_Pos) |
364 (1 << AUDCODEC_LP_PLL_CFG5_EN_CLK_CHOP_REFGEN_Pos) |
365 (cfg->divb_clk_chop_dac << AUDCODEC_LP_PLL_CFG5_DIVB_CLK_CHOP_DAC2_Pos) |
366 (cfg->diva_clk_chop_dac << AUDCODEC_LP_PLL_CFG5_DIVA_CLK_CHOP_DAC2_Pos) |
367 (1 << AUDCODEC_LP_PLL_CFG5_EN_CLK_CHOP_DAC2_Pos) |
368 (cfg->diva_clk_dac << AUDCODEC_LP_PLL_CFG5_DIVA_CLK_DAC2_Pos) |
369 (1 << AUDCODEC_LP_PLL_CFG5_EN_CLK_DAC2_Pos);
370
371 //if (pll_cfg2_reset == 0)
372 {
373 hwp_audcodec_lp->PLL_CFG2 &= ~AUDCODEC_LP_PLL_CFG2_RSTB;
374 HAL_Delay_us(100);
375 hwp_audcodec_lp->PLL_CFG2 |= AUDCODEC_LP_PLL_CFG2_RSTB;
376 }
377
378 // dac1 and dac2 power
379 #ifdef SF32LB58X
380 hwp_audcodec_lp->DAC1_CFG |= AUDCODEC_LP_DAC1_CFG_LP_MODE;
381 hwp_audcodec_lp->DAC2_CFG |= AUDCODEC_LP_DAC2_CFG_LP_MODE;
382 #endif
383 hwp_audcodec_lp->DAC1_CFG &= ~AUDCODEC_LP_DAC1_CFG_EN_OS_DAC;
384 hwp_audcodec_lp->DAC2_CFG &= ~AUDCODEC_LP_DAC2_CFG_EN_OS_DAC;
385 hwp_audcodec_lp->DAC1_CFG |= AUDCODEC_LP_DAC1_CFG_EN_VCM;
386 #ifdef BSP_ENABLE_DAC2
387 hwp_audcodec_lp->DAC2_CFG |= AUDCODEC_LP_DAC2_CFG_EN_VCM;
388 #else
389 hwp_audcodec_lp->DAC2_CFG &= ~AUDCODEC_LP_DAC2_CFG_EN_VCM;
390 #endif
391 // wait 5us
392 //wait(250);
393 HAL_Delay_us(5);
394 hwp_audcodec_lp->DAC1_CFG |= AUDCODEC_LP_DAC1_CFG_EN_AMP;
395 #ifdef BSP_ENABLE_DAC2
396 hwp_audcodec_lp->DAC2_CFG |= AUDCODEC_LP_DAC2_CFG_EN_AMP;
397 #else
398 hwp_audcodec_lp->DAC2_CFG &= ~AUDCODEC_LP_DAC2_CFG_EN_AMP;
399 #endif
400 // wait 1us
401 //wait(50);
402 HAL_Delay_us(1);
403 hwp_audcodec_lp->DAC1_CFG |= AUDCODEC_LP_DAC1_CFG_EN_OS_DAC;
404 hwp_audcodec_lp->DAC2_CFG |= AUDCODEC_LP_DAC2_CFG_EN_OS_DAC;
405 // wait 10us
406 //wait(500);
407 HAL_Delay_us(10);
408 hwp_audcodec_lp->DAC1_CFG |= AUDCODEC_LP_DAC1_CFG_EN_DAC;
409 #ifdef BSP_ENABLE_DAC2
410 hwp_audcodec_lp->DAC2_CFG |= AUDCODEC_LP_DAC2_CFG_EN_DAC;
411 #else
412 hwp_audcodec_lp->DAC2_CFG &= ~AUDCODEC_LP_DAC2_CFG_EN_DAC;
413 #endif
414 // wait 10us
415 //wait(500);
416 HAL_Delay_us(10);
417 hwp_audcodec_lp->DAC1_CFG &= ~AUDCODEC_LP_DAC1_CFG_SR;
418 hwp_audcodec_lp->DAC2_CFG &= ~AUDCODEC_LP_DAC2_CFG_SR;
419 pll_cfg2_reset |= (1 << HAL_AUDCODEC_DAC_CH0);
420 return HAL_OK;
421 }
422
HAL_TURN_OFF_PLL()423 void HAL_TURN_OFF_PLL()
424 {
425 pll_cfg2_reset = 0;
426 // turn off pll
427 hwp_audcodec_lp->PLL_CFG0 &= ~AUDCODEC_LP_PLL_CFG0_EN_IARY;
428 hwp_audcodec_lp->PLL_CFG0 &= ~AUDCODEC_LP_PLL_CFG0_EN_VCO;
429 hwp_audcodec_lp->PLL_CFG0 &= ~AUDCODEC_LP_PLL_CFG0_EN_ANA;
430 hwp_audcodec_lp->PLL_CFG2 &= ~AUDCODEC_LP_PLL_CFG2_EN_DIG;
431 hwp_audcodec_lp->PLL_CFG3 &= ~AUDCODEC_LP_PLL_CFG3_EN_SDM;
432 hwp_audcodec_lp->PLL_CFG4 &= ~AUDCODEC_LP_PLL_CFG4_EN_CLK_DIG;
433
434 // turn off refgen
435 hwp_audcodec_lp->REFGEN_CFG &= ~AUDCODEC_LP_REFGEN_CFG_EN;
436 #if 1
437 // turn off bandgap
438 hwp_audcodec_lp->BG_CFG1 = 0;
439 hwp_audcodec_lp->BG_CFG2 = 0;
440 hwp_audcodec_lp->BG_CFG0 &= ~AUDCODEC_LP_BG_CFG0_EN;
441 hwp_audcodec_lp->BG_CFG0 &= ~AUDCODEC_LP_BG_CFG0_EN_SMPL;
442 #endif
443 HAL_DBG_printf("turn off pll\n");
444
445 }
HAL_TURN_ON_PLL()446 void HAL_TURN_ON_PLL()
447 {
448 HAL_DBG_printf("turn on pll\n");
449 //-----------------step 2------------------//
450 // turn on bandgap
451 hwp_audcodec_lp->BG_CFG0 = (1 << AUDCODEC_LP_BG_CFG0_EN_Pos) |
452 (0 << AUDCODEC_LP_BG_CFG0_LP_MODE_Pos) |
453 (4 << AUDCODEC_LP_BG_CFG0_VREF_SEL_Pos) | // 4: 3.3v 2:AVDD = 1.8V
454 // (1 << AUDCODEC_LP_BG_CFG0_EN_CHOP_Pos) |
455 (0 << AUDCODEC_LP_BG_CFG0_EN_SMPL_Pos) |
456 (1 << AUDCODEC_LP_BG_CFG0_EN_RCFLT_Pos) |
457 (4 << AUDCODEC_LP_BG_CFG0_MIC_VREF_SEL_Pos);
458 // turn on BG sample clock
459 hwp_audcodec_lp->BG_CFG1 = 48000;
460 hwp_audcodec_lp->BG_CFG2 = 48000000;
461 // turn on bandgap
462 HAL_Delay_us(100);
463 //hwp_audcodec_lp->BG_CFG0 |= AUDCODEC_LP_BG_CFG0_EN_SMPL;
464
465 //-----------------step 3------------------//
466 // pll calibration
467 // wait 100us
468 //wait(5000);
469 HAL_Delay_us(100);
470
471 hwp_audcodec_lp->PLL_CFG0 |= AUDCODEC_LP_PLL_CFG0_EN_IARY;
472 hwp_audcodec_lp->PLL_CFG0 |= AUDCODEC_LP_PLL_CFG0_EN_VCO;
473 hwp_audcodec_lp->PLL_CFG0 |= AUDCODEC_LP_PLL_CFG0_EN_ANA;
474 hwp_audcodec_lp->PLL_CFG0 &= ~AUDCODEC_LP_PLL_CFG0_ICP_SEL_Msk;
475 hwp_audcodec_lp->PLL_CFG0 |= (8 << AUDCODEC_LP_PLL_CFG0_ICP_SEL_Pos);
476 hwp_audcodec_lp->PLL_CFG2 |= AUDCODEC_LP_PLL_CFG2_EN_DIG;
477 hwp_audcodec_lp->PLL_CFG3 |= AUDCODEC_LP_PLL_CFG3_EN_SDM;
478 hwp_audcodec_lp->PLL_CFG4 |= AUDCODEC_LP_PLL_CFG4_EN_CLK_DIG;
479 // wait 50us
480 //wait(2500);
481 HAL_Delay_us(50);
482
483 HAL_AUCODEC_Refgen_Init();
484
485 }
486
HAL_AUDCODEC_Close_Analog_DACPath(void)487 __HAL_ROM_USED void HAL_AUDCODEC_Close_Analog_DACPath(void)
488 {
489 hwp_audcodec_lp->DAC1_CFG |= AUDCODEC_LP_DAC1_CFG_SR;
490 hwp_audcodec_lp->DAC2_CFG |= AUDCODEC_LP_DAC2_CFG_SR;
491 // wait 10us
492 //wait(500);
493 HAL_Delay_us(10);
494 hwp_audcodec_lp->DAC1_CFG &= ~AUDCODEC_LP_DAC1_CFG_EN_DAC;
495 hwp_audcodec_lp->DAC2_CFG &= ~AUDCODEC_LP_DAC2_CFG_EN_DAC;
496 // wait 10us
497 //wait(500);
498 HAL_Delay_us(10);
499 hwp_audcodec_lp->DAC1_CFG &= ~AUDCODEC_LP_DAC1_CFG_EN_VCM;
500 hwp_audcodec_lp->DAC2_CFG &= ~AUDCODEC_LP_DAC2_CFG_EN_VCM;
501 // wait 10us
502 //wait(500);
503 HAL_Delay_us(10);
504 hwp_audcodec_lp->DAC1_CFG &= ~AUDCODEC_LP_DAC1_CFG_EN_AMP;
505 hwp_audcodec_lp->DAC2_CFG &= ~AUDCODEC_LP_DAC2_CFG_EN_AMP;
506 hwp_audcodec_lp->DAC1_CFG &= ~AUDCODEC_LP_DAC1_CFG_EN_OS_DAC;
507 hwp_audcodec_lp->DAC2_CFG &= ~AUDCODEC_LP_DAC2_CFG_EN_OS_DAC;
508 HAL_DBG_printf("close Aanlog DACPath\n");
509
510 }
511
HAL_AUCODEC_Refgen_Init(void)512 __HAL_ROM_USED void HAL_AUCODEC_Refgen_Init(void)
513 {
514 HAL_DBG_printf("turn on refgen\n");
515 // turn on refgen
516 //hwp_audcodec_lp->BG_CFG0 &= ~AUDCODEC_LP_BG_CFG0_EN_SMPL;
517 //hwp_audcodec_lp->BG_CFG0 &= ~AUDCODEC_LP_BG_CFG0_VREF_SEL;
518 //hwp_audcodec_lp->BG_CFG0 |= (7 << AUDCODEC_LP_BG_CFG0_VREF_SEL_Pos); // AVDD = 3.3V
519 //hwp_audcodec_lp->BG_CFG0 |= (2 << AUDCODEC_LP_BG_CFG0_VREF_SEL_Pos); // AVDD = 1.8V
520 hwp_audcodec_lp->BG_CFG0 &= ~AUDCODEC_LP_BG_CFG0_EN_SMPL;
521 hwp_audcodec_lp->REFGEN_CFG &= ~AUDCODEC_LP_REFGEN_CFG_EN_CHOP;
522 hwp_audcodec_lp->REFGEN_CFG |= AUDCODEC_LP_REFGEN_CFG_EN;
523 //hwp_audcodec_lp->PLL_CFG5 = AUDCODEC_LP_PLL_CFG5_EN_CLK_CHOP_BG |
524 // AUDCODEC_LP_PLL_CFG5_EN_CLK_CHOP_REFGEN;
525 MODIFY_REG(hwp_audcodec_lp->PLL_CFG5, AUDCODEC_LP_PLL_CFG5_EN_CLK_CHOP_BG_Msk, \
526 MAKE_REG_VAL(1, AUDCODEC_LP_PLL_CFG5_EN_CLK_CHOP_BG_Msk, AUDCODEC_LP_PLL_CFG5_EN_CLK_CHOP_BG_Pos));
527 MODIFY_REG(hwp_audcodec_lp->PLL_CFG5, AUDCODEC_LP_PLL_CFG5_EN_CLK_CHOP_REFGEN_Msk, \
528 MAKE_REG_VAL(1, AUDCODEC_LP_PLL_CFG5_EN_CLK_CHOP_REFGEN_Msk, AUDCODEC_LP_PLL_CFG5_EN_CLK_CHOP_REFGEN_Pos));
529 HAL_Delay(2); //2ms
530 hwp_audcodec_lp->BG_CFG0 |= AUDCODEC_LP_BG_CFG0_EN_SMPL;
531 }
532
HAL_AUDCODEC_Config_Analog_ADCPath(AUDCODE_ADC_CLK_CONFIG_TYPE * cfg)533 __HAL_ROM_USED void HAL_AUDCODEC_Config_Analog_ADCPath(AUDCODE_ADC_CLK_CONFIG_TYPE *cfg)
534 {
535 HAL_DBG_printf("config Aanlog ADCPath\n");
536 // turn on lp adc1 and adc2 analog
537 hwp_audcodec_lp->BG_CFG0 &= ~AUDCODEC_LP_BG_CFG0_EN_SMPL;
538 hwp_audcodec_lp->ADC_ANA_CFG |= AUDCODEC_LP_ADC_ANA_CFG_MICBIAS_EN;
539 hwp_audcodec_lp->ADC_ANA_CFG &= ~AUDCODEC_LP_ADC_ANA_CFG_MICBIAS_CHOP_EN;
540 HAL_Delay(2); //2ms
541 hwp_audcodec_lp->BG_CFG0 |= AUDCODEC_LP_BG_CFG0_EN_SMPL;
542
543 // adc1 and adc2 clock
544 hwp_audcodec_lp->PLL_CFG6 = (0 << AUDCODEC_LP_PLL_CFG6_SEL_TST_CLK_Pos) |
545 (0 << AUDCODEC_LP_PLL_CFG6_EN_TST_CLK_Pos) |
546 (0 << AUDCODEC_LP_PLL_CFG6_EN_CLK_RCCAL_Pos) |
547 (3 << AUDCODEC_LP_PLL_CFG6_SEL_CLK_CHOP_MICBIAS_Pos) |
548 (1 << AUDCODEC_LP_PLL_CFG6_EN_CLK_CHOP_MICBIAS_Pos) |
549 (cfg->sel_clk_adc << AUDCODEC_LP_PLL_CFG6_SEL_CLK_ADC2_Pos) |
550 (cfg->diva_clk_adc << AUDCODEC_LP_PLL_CFG6_DIVA_CLK_ADC2_Pos) |
551 (1 << AUDCODEC_LP_PLL_CFG6_EN_CLK_ADC2_Pos) |
552 (cfg->sel_clk_adc << AUDCODEC_LP_PLL_CFG6_SEL_CLK_ADC1_Pos) |
553 (cfg->diva_clk_adc << AUDCODEC_LP_PLL_CFG6_DIVA_CLK_ADC1_Pos) |
554 (1 << AUDCODEC_LP_PLL_CFG6_EN_CLK_ADC1_Pos) |
555 (1 << AUDCODEC_LP_PLL_CFG6_SEL_CLK_ADC0_Pos) |
556 (5 << AUDCODEC_LP_PLL_CFG6_DIVA_CLK_ADC0_Pos) |
557 (1 << AUDCODEC_LP_PLL_CFG6_EN_CLK_ADC0_Pos) |
558 (cfg->sel_clk_adc_source << AUDCODEC_LP_PLL_CFG6_SEL_CLK_ADC_SOURCE_Pos);
559 //if (pll_cfg2_reset == 0)
560 {
561 hwp_audcodec_lp->PLL_CFG2 &= ~AUDCODEC_LP_PLL_CFG2_RSTB;
562 HAL_Delay(1);
563 hwp_audcodec_lp->PLL_CFG2 |= AUDCODEC_LP_PLL_CFG2_RSTB;
564 }
565
566 hwp_audcodec_lp->ADC1_CFG1 &= ~AUDCODEC_LP_ADC1_CFG1_FSP;
567 hwp_audcodec_lp->ADC1_CFG1 |= (cfg->fsp << AUDCODEC_LP_ADC1_CFG1_FSP_Pos);
568
569 //this make long mic startup pulse
570 hwp_audcodec_lp->ADC1_CFG1 |= AUDCODEC_LP_ADC1_CFG1_VCMST;
571 hwp_audcodec_lp->ADC1_CFG2 |= AUDCODEC_LP_ADC1_CFG2_CLEAR;
572
573 hwp_audcodec_lp->ADC1_CFG1 &= ~AUDCODEC_LP_ADC1_CFG1_GC_Msk;
574 hwp_audcodec_lp->ADC1_CFG1 |= (0x1E << AUDCODEC_LP_ADC1_CFG1_GC_Pos);
575
576 hwp_audcodec_lp->ADC1_CFG2 |= AUDCODEC_LP_ADC1_CFG2_EN;
577 hwp_audcodec_lp->ADC1_CFG2 &= ~AUDCODEC_LP_ADC1_CFG2_RSTB;
578
579 hwp_audcodec_lp->ADC1_CFG1 &= ~AUDCODEC_LP_ADC1_CFG1_VREF_SEL;
580 hwp_audcodec_lp->ADC1_CFG1 |= (2 << AUDCODEC_LP_ADC1_CFG1_VREF_SEL_Pos) ;
581
582 hwp_audcodec_lp->ADC2_CFG1 &= ~AUDCODEC_LP_ADC2_CFG1_FSP;
583 hwp_audcodec_lp->ADC2_CFG1 |= (cfg->fsp << AUDCODEC_LP_ADC2_CFG1_FSP_Pos);
584
585 hwp_audcodec_lp->ADC2_CFG1 |= AUDCODEC_LP_ADC2_CFG1_VCMST;
586 hwp_audcodec_lp->ADC2_CFG2 |= AUDCODEC_LP_ADC2_CFG2_CLEAR;
587
588 hwp_audcodec_lp->ADC2_CFG1 &= ~AUDCODEC_LP_ADC2_CFG1_GC_Msk;
589 hwp_audcodec_lp->ADC2_CFG1 |= (0x1E << AUDCODEC_LP_ADC2_CFG1_GC_Pos);
590
591 hwp_audcodec_lp->ADC2_CFG2 |= AUDCODEC_LP_ADC2_CFG2_EN;
592 hwp_audcodec_lp->ADC2_CFG2 &= ~AUDCODEC_LP_ADC2_CFG2_RSTB;
593
594 hwp_audcodec_lp->ADC2_CFG2 &= ~AUDCODEC_LP_ADC2_CFG1_VREF_SEL;
595 hwp_audcodec_lp->ADC2_CFG2 |= (2 << AUDCODEC_LP_ADC2_CFG1_VREF_SEL_Pos) ;
596 // wait 20ms
597 HAL_Delay(20);
598 //hwp_audcodec_lp->BG_CFG0 |= AUDCODEC_LP_BG_CFG0_EN_SMPL;
599 hwp_audcodec_lp->ADC1_CFG2 |= AUDCODEC_LP_ADC1_CFG2_RSTB;
600 hwp_audcodec_lp->ADC1_CFG1 &= ~AUDCODEC_LP_ADC1_CFG1_VCMST;
601 hwp_audcodec_lp->ADC1_CFG2 &= ~AUDCODEC_LP_ADC1_CFG2_CLEAR;
602 hwp_audcodec_lp->ADC2_CFG2 |= AUDCODEC_LP_ADC2_CFG2_RSTB;
603 hwp_audcodec_lp->ADC2_CFG1 &= ~AUDCODEC_LP_ADC2_CFG1_VCMST;
604 hwp_audcodec_lp->ADC2_CFG2 &= ~AUDCODEC_LP_ADC2_CFG2_CLEAR;
605 pll_cfg2_reset |= (1 << HAL_AUDCODEC_ADC_CH0);
606 }
607
HAL_AUDCODEC_Close_Analog_ADCPath(void)608 __HAL_ROM_USED void HAL_AUDCODEC_Close_Analog_ADCPath(void)
609 {
610 // turn off adc
611 hwp_audcodec_lp->ADC1_CFG2 &= ~AUDCODEC_LP_ADC1_CFG2_EN;
612 hwp_audcodec_lp->ADC2_CFG2 &= ~AUDCODEC_LP_ADC2_CFG2_EN;
613 hwp_audcodec_lp->ADC_ANA_CFG &= ~AUDCODEC_LP_ADC_ANA_CFG_MICBIAS_EN;
614 HAL_DBG_printf("close Aanlog ADCPath\n");
615
616 }
617
618
619 /**
620 * @brief Initializes the AUDCODEC according to the specified parameters
621 * in the AUDCODEC_InitTypeDef and create the associated handle.
622 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
623 * the configuration information for AUDCODEC module
624 * @retval HAL status
625 */
HAL_AUDCODEC_Init(AUDCODEC_HandleTypeDef * hacodec)626 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Init(AUDCODEC_HandleTypeDef *hacodec)
627 {
628 int i = 0;
629 /* Check the AUDCODEC handle allocation */
630 if (hacodec == NULL)
631 {
632 return HAL_ERROR;
633 }
634
635 if (hacodec->State[0] == HAL_AUDCODEC_STATE_RESET)
636 {
637 /* Allocate lock resource and initialize it */
638 hacodec->Lock = HAL_UNLOCKED;
639
640 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
641 HAL_AUDCODEC_MspInit(hacodec);
642 }
643
644 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
645 {
646 hacodec->State[i] = HAL_AUDCODEC_STATE_BUSY;
647 }
648
649 // disable and Set delay count
650 //MODIFY_REG(hacodec->Instance_hp->CFG, AUDCODEC_HP_CFG_EN_DLY_SEL_Msk,
651 // MAKE_REG_VAL(hacodec->Init.en_dly_sel, AUDCODEC_HP_CFG_EN_DLY_SEL_Msk, AUDCODEC_HP_CFG_EN_DLY_SEL_Pos));
652 //hacodec->Instance_hp->CFG = MAKE_REG_VAL(hacodec->Init.en_dly_sel, AUDCODEC_HP_CFG_EN_DLY_SEL_Msk, AUDCODEC_HP_CFG_EN_DLY_SEL_Pos);
653 //hacodec->Instance_lp->CFG = MAKE_REG_VAL(hacodec->Init.en_dly_sel, AUDCODEC_LP_CFG_EN_DLY_SEL_Msk, AUDCODEC_LP_CFG_EN_DLY_SEL_Pos);
654
655
656 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
657 if (hacodec->hdma[i] != NULL)
658 hacodec->hdma[i]->Parent = (void *)hacodec;
659
660 for (i = HAL_AUDCODEC_DAC_CH0; i < HAL_AUDCODEC_ADC_CH0; i++)
661 {
662 if (hacodec->hdma[i] != NULL)
663 HAL_AUDCODEC_DMA_Init(hacodec->hdma[i], 1);
664 }
665 for (i = HAL_AUDCODEC_ADC_CH0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
666 {
667 if (hacodec->hdma[i] != NULL)
668 HAL_AUDCODEC_DMA_Init(hacodec->hdma[i], 0);
669 }
670
671 //HAL_AUDCODEC_Config_DACPath(hacodec, &(hacodec->Init.dac_cfg));
672 //HAL_AUDCODEC_Config_ADCPath(hacodec, &(hacodec->Init.adc_cfg));
673
674 hacodec->ErrorCode = HAL_AUDCODEC_ERROR_NONE;
675 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
676 {
677 hacodec->State[i] = HAL_AUDCODEC_STATE_READY;
678 }
679
680 return HAL_OK;
681 }
682
683 /**
684 * @brief DeInitializes the AUDCODEC peripheral
685 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
686 * the configuration information for AUDCODEC module
687 * @retval HAL status
688 */
HAL_AUDCODEC_DeInit(AUDCODEC_HandleTypeDef * hacodec)689 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_DeInit(AUDCODEC_HandleTypeDef *hacodec)
690 {
691 int i;
692
693 /* Check the AUDCODEC handle allocation */
694 if (hacodec == NULL)
695 {
696 return HAL_ERROR;
697 }
698
699
700 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
701 {
702 hacodec->State[i] |= HAL_AUDCODEC_STATE_BUSY;
703 if (hacodec->hdma[i] != NULL)
704 HAL_DMA_DeInit(hacodec->hdma[i]);
705 }
706
707
708 /* Disable the AUDCODEC Peripheral Clock */
709 __HAL_AUDCODEC_HP_DISABLE(hacodec);
710 __HAL_AUDCODEC_LP_DISABLE(hacodec);
711
712 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
713 HAL_AUDCODEC_MspDeInit(hacodec);
714
715 hacodec->ErrorCode = HAL_AUDCODEC_ERROR_NONE;
716 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
717 {
718 hacodec->State[i] |= HAL_AUDCODEC_STATE_RESET;
719 }
720
721 /* Release Lock */
722 __HAL_UNLOCK(hacodec);
723
724 return HAL_OK;
725 }
726
727 /**
728 * @brief Initializes the AUDCODEC pin setting.
729 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
730 * the configuration information for AUDCODEC module
731 * @retval None
732 */
HAL_AUDCODEC_MspInit(AUDCODEC_HandleTypeDef * hacodec)733 __HAL_ROM_USED void HAL_AUDCODEC_MspInit(AUDCODEC_HandleTypeDef *hacodec)
734 {
735 /* Prevent unused argument(s) compilation warning */
736 UNUSED(hacodec);
737 }
738
739 /**
740 * @brief deunitializes the AUDCODEC pin setting.
741 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
742 * the configuration information for AUDCODEC module
743 * @retval None
744 */
HAL_AUDCODEC_MspDeInit(AUDCODEC_HandleTypeDef * hacodec)745 __HAL_ROM_USED void HAL_AUDCODEC_MspDeInit(AUDCODEC_HandleTypeDef *hacodec)
746 {
747 /* Prevent unused argument(s) compilation warning */
748 UNUSED(hacodec);
749 }
750
751 /**
752 * @brief Set AUDCODEC transmit channel configures.
753 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
754 * the configuration information for AUDCODEC module
755 * @param cfg: configure parameters
756 * @retval HAL status
757 */
HAL_AUDCODEC_Config_TChanel(AUDCODEC_HandleTypeDef * hacodec,int channel,AUDCODEC_DACCfgTypeDef * cfg)758 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Config_TChanel(AUDCODEC_HandleTypeDef *hacodec, int channel, AUDCODEC_DACCfgTypeDef *cfg)
759 {
760 AUDCODE_DAC_CLK_CONFIG_TYPE *dac_clk = cfg->dac_clk;
761
762 /* Check the AUDCODEC handle allocation */
763 if (hacodec == NULL)
764 {
765 return HAL_ERROR;
766 }
767
768 hacodec->Instance_hp->CFG |= (3 << AUDCODEC_HP_CFG_EN_DLY_SEL_Pos);
769 hacodec->Instance_hp->DAC_CFG = (dac_clk->osr_sel << AUDCODEC_HP_DAC_CFG_OSR_SEL_Pos) |
770 (cfg->opmode << AUDCODEC_HP_DAC_CFG_OP_MODE_Pos) |
771 (0 << AUDCODEC_HP_DAC_CFG_PATH_RESET_Pos) |
772 (dac_clk->clk_src_sel << AUDCODEC_HP_DAC_CFG_CLK_SRC_SEL_Pos) |
773 (dac_clk->clk_div << AUDCODEC_HP_DAC_CFG_CLK_DIV_Pos);
774 switch (channel)
775 {
776 case 0:
777 hacodec->Instance_hp->DAC_CH0_CFG = (1 << AUDCODEC_HP_DAC_CH0_CFG_ENABLE_Pos) |
778 (0 << AUDCODEC_HP_DAC_CH0_CFG_DOUT_MUTE_Pos) |
779 (2 << AUDCODEC_HP_DAC_CH0_CFG_DEM_MODE_Pos) |
780 (0 << AUDCODEC_HP_DAC_CH0_CFG_DMA_EN_Pos) |
781 (6 << AUDCODEC_HP_DAC_CH0_CFG_ROUGH_VOL_Pos) |
782 (0 << AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Pos) |
783 (1 << AUDCODEC_HP_DAC_CH0_CFG_DATA_FORMAT_Pos) |
784 (dac_clk->sinc_gain << AUDCODEC_HP_DAC_CH0_CFG_SINC_GAIN_Pos) |
785 (0 << AUDCODEC_HP_DAC_CH0_CFG_DITHER_GAIN_Pos) |
786 (0 << AUDCODEC_HP_DAC_CH0_CFG_DITHER_EN_Pos) |
787 (0 << AUDCODEC_HP_DAC_CH0_CFG_CLK_ANA_POL_Pos);
788
789 hacodec->Instance_hp->DAC_CH0_CFG_EXT = (1 << AUDCODEC_HP_DAC_CH0_CFG_EXT_RAMP_EN_Pos) |
790 (1 << AUDCODEC_HP_DAC_CH0_CFG_EXT_RAMP_MODE_Pos) |
791 (1 << AUDCODEC_HP_DAC_CH0_CFG_EXT_ZERO_ADJUST_EN_Pos) |
792 (6 << AUDCODEC_HP_DAC_CH0_CFG_EXT_RAMP_INTERVAL_Pos) |
793 (0 << AUDCODEC_HP_DAC_CH0_CFG_EXT_RAMP_STAT_Pos);
794
795 hacodec->Instance_hp->DAC_CH0_DEBUG = (0 << AUDCODEC_HP_DAC_CH0_DEBUG_BYPASS_Pos) |
796 (0xFF << AUDCODEC_HP_DAC_CH0_DEBUG_DATA_OUT_Pos);
797 //hacodec->Instance_hp->DAC_CH0_DC = MAKE_REG_VAL(cfg->dc_offset, AUDCODEC_HP_DAC_CH0_DC_OFFSET_Msk, AUDCODEC_HP_DAC_CH0_DC_OFFSET_Pos);
798 break;
799 case 1:
800 hacodec->Instance_hp->DAC_CH1_CFG = (1 << AUDCODEC_HP_DAC_CH0_CFG_ENABLE_Pos) |
801 (0 << AUDCODEC_HP_DAC_CH0_CFG_DOUT_MUTE_Pos) |
802 (2 << AUDCODEC_HP_DAC_CH0_CFG_DEM_MODE_Pos) |
803 (0 << AUDCODEC_HP_DAC_CH0_CFG_DMA_EN_Pos) |
804 (6 << AUDCODEC_HP_DAC_CH0_CFG_ROUGH_VOL_Pos) |
805 (0 << AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Pos) |
806 (1 << AUDCODEC_HP_DAC_CH0_CFG_DATA_FORMAT_Pos) |
807 (dac_clk->sinc_gain << AUDCODEC_HP_DAC_CH0_CFG_SINC_GAIN_Pos) |
808 (0 << AUDCODEC_HP_DAC_CH0_CFG_DITHER_GAIN_Pos) |
809 (0 << AUDCODEC_HP_DAC_CH0_CFG_DITHER_EN_Pos) |
810 (0 << AUDCODEC_HP_DAC_CH0_CFG_CLK_ANA_POL_Pos);
811
812 hacodec->Instance_hp->DAC_CH1_CFG_EXT = (1 << AUDCODEC_HP_DAC_CH0_CFG_EXT_RAMP_EN_Pos) |
813 (1 << AUDCODEC_HP_DAC_CH0_CFG_EXT_RAMP_MODE_Pos) |
814 (1 << AUDCODEC_HP_DAC_CH0_CFG_EXT_ZERO_ADJUST_EN_Pos) |
815 (6 << AUDCODEC_HP_DAC_CH0_CFG_EXT_RAMP_INTERVAL_Pos) |
816 (0 << AUDCODEC_HP_DAC_CH0_CFG_EXT_RAMP_STAT_Pos);
817
818 hacodec->Instance_hp->DAC_CH1_DEBUG = (0 << AUDCODEC_HP_DAC_CH0_DEBUG_BYPASS_Pos) |
819 (0xFF << AUDCODEC_HP_DAC_CH0_DEBUG_DATA_OUT_Pos);
820 //hacodec->Instance_hp->DAC_CH1_DC = MAKE_REG_VAL(cfg->dc_offset, AUDCODEC_HP_DAC_CH1_DC_OFFSET_Msk, AUDCODEC_HP_DAC_CH1_DC_OFFSET_Pos);
821 break;
822 default:
823 return HAL_ERROR;
824 }
825
826 return HAL_OK;
827 }
828
829 /**
830 * @brief Set AUDCODEC Receive configures.
831 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
832 * the configuration information for AUDCODEC module
833 * @param cfg: configure parameters
834 * @retval HAL status
835 */
HAL_AUDCODEC_Config_RChanel(AUDCODEC_HandleTypeDef * hacodec,int channel,AUDCODEC_ADCCfgTypeDef * cfg)836 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Config_RChanel(AUDCODEC_HandleTypeDef *hacodec, int channel, AUDCODEC_ADCCfgTypeDef *cfg)
837 {
838 AUDCODE_ADC_CLK_CONFIG_TYPE *adc_clk = cfg->adc_clk;
839
840 /* Check the AUDCODEC handle allocation */
841 if (hacodec == NULL)
842 {
843 return HAL_ERROR;
844 }
845
846 hacodec->Instance_lp->ADC_CFG = (adc_clk->osr_sel << AUDCODEC_LP_ADC_CFG_OSR_SEL_Pos) |
847 (cfg->opmode << AUDCODEC_LP_ADC_CFG_OP_MODE_Pos) | // 2 for test
848 (0 << AUDCODEC_LP_ADC_CFG_PATH_RESET_Pos) |
849 (adc_clk->clk_src_sel << AUDCODEC_LP_ADC_CFG_CLK_SRC_SEL_Pos) |
850 (adc_clk->clk_div << AUDCODEC_LP_ADC_CFG_CLK_DIV_Pos);
851
852 //hacodec->Instance_lp->ADC_CFG = 0x508;//0x508; 510:raw
853
854 switch (channel)
855 {
856 case 0:
857
858 hacodec->Instance_lp->ADC_CH0_CFG = (1 << AUDCODEC_LP_ADC_CH0_CFG_ENABLE_Pos) |
859 (0 << AUDCODEC_LP_ADC_CH0_CFG_HPF_BYPASS_Pos) |
860 (0x7 << AUDCODEC_LP_ADC_CH0_CFG_HPF_COEF_Pos) |
861 (0 << AUDCODEC_LP_ADC_CH0_CFG_STB_INV_Pos) |
862 (0 << AUDCODEC_LP_ADC_CH0_CFG_DMA_EN_Pos) |
863 (0xc << AUDCODEC_LP_ADC_CH0_CFG_ROUGH_VOL_Pos) |
864 (0 << AUDCODEC_LP_ADC_CH0_CFG_FINE_VOL_Pos) |
865 (1 << AUDCODEC_LP_ADC_CH0_CFG_DATA_FORMAT_Pos); //16bit
866 //hacodec->Instance_lp->ADC_CH0_CFG = 0x10ABD;
867 break;
868 case 1:
869
870 hacodec->Instance_lp->ADC_CH1_CFG = (1 << AUDCODEC_LP_ADC_CH0_CFG_ENABLE_Pos) |
871 (0 << AUDCODEC_LP_ADC_CH0_CFG_HPF_BYPASS_Pos) |
872 (0xf << AUDCODEC_LP_ADC_CH0_CFG_HPF_COEF_Pos) |
873 (0 << AUDCODEC_LP_ADC_CH0_CFG_STB_INV_Pos) |
874 (0 << AUDCODEC_LP_ADC_CH0_CFG_DMA_EN_Pos) |
875 (0xc << AUDCODEC_LP_ADC_CH0_CFG_ROUGH_VOL_Pos) |
876 (0 << AUDCODEC_LP_ADC_CH0_CFG_FINE_VOL_Pos) |
877 (1 << AUDCODEC_LP_ADC_CH0_CFG_DATA_FORMAT_Pos); //16bit
878 break;
879 default:
880 return HAL_ERROR;
881 }
882
883 return HAL_OK;
884 }
885
886
887 /**
888 * @brief all channel disable
889 * @param hacodec -pointer to a AUDCODEC_HandleTypeDef structure that contains
890 * the configuration information for AUDCODEC module
891 * @param ch_type_bit : bit0 is dac, bit1 is adc
892 * @return HAL status
893 */
HAL_AUDCODEC_Clear_All_Channel(AUDCODEC_HandleTypeDef * hacodec,uint8_t ch_type_bit)894 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Clear_All_Channel(AUDCODEC_HandleTypeDef *hacodec, uint8_t ch_type_bit)
895 {
896 if (ch_type_bit & 0x1)
897 {
898 __HAL_AUDCODEC_HP_DAC_CH0_DISABLE(hacodec);
899 __HAL_AUDCODEC_HP_DAC_CH1_DISABLE(hacodec);
900 hacodec->Instance_hp->DAC_CFG |= AUDCODEC_HP_DAC_CFG_PATH_RESET;
901 hacodec->Instance_hp->DAC_CFG &= ~AUDCODEC_HP_DAC_CFG_PATH_RESET;
902 pll_cfg2_reset &= ~(1 << HAL_AUDCODEC_DAC_CH0);
903 }
904
905 if (ch_type_bit & 0x2)
906 {
907 __HAL_AUDCODEC_HP_ADC_CH0_DISABLE(hacodec);
908 __HAL_AUDCODEC_HP_ADC_CH1_DISABLE(hacodec);
909 hacodec->Instance_lp->ADC_CFG |= AUDCODEC_LP_ADC_CFG_PATH_RESET;
910 hacodec->Instance_lp->ADC_CFG &= ~AUDCODEC_LP_ADC_CFG_PATH_RESET;
911 pll_cfg2_reset &= ~(1 << HAL_AUDCODEC_ADC_CH0);
912 }
913
914 return HAL_OK;
915 }
916
917 /**
918 * @brief Configure DAC path volume.
919 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
920 * the configuration information for AUDCODEC module
921 * @param channel: channel 0 or 1
922 * @param volume: configure volume -36dB~54dB, unit is 0.5db, use fix point Q15.1 format
923 * @retval HAL status
924 */
HAL_AUDCODEC_Config_DACPath_Volume(AUDCODEC_HandleTypeDef * hacodec,int channel,int volume)925 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Config_DACPath_Volume(AUDCODEC_HandleTypeDef *hacodec, int channel, int volume)
926 {
927 uint32_t rough_vol, fine_vol;
928 int volume2;
929
930 /* Check the AUDCODEC handle allocation */
931 if (hacodec == NULL)
932 {
933 return HAL_ERROR;
934 }
935
936 if ((channel < 0) || (channel > 1))
937 {
938 return HAL_ERROR;
939 }
940
941 if (volume >= 0)
942 {
943 volume2 = volume;
944 }
945 else
946 {
947 volume2 = 0 - volume;
948 }
949
950 if (volume2 & 1)
951 {
952 fine_vol = 1;
953 }
954 else
955 {
956 fine_vol = 0;
957 }
958
959 volume2 = (volume2 >> 1);
960
961 if (volume < 0)
962 {
963 volume = 0 - volume2;
964 if (fine_vol)
965 volume--;
966 }
967 else
968 volume = volume2;
969
970 //HAL_DBG_printf("codec vol=%d, 0.5 on/off=%d", volume, fine_vol);
971
972 if ((volume < -36) || (volume > 54) || (volume == 54 && fine_vol))
973 {
974 return HAL_ERROR;
975 }
976
977 rough_vol = (volume + 36) / 6;
978 fine_vol = fine_vol + (((volume + 36) % 6) << 1);
979
980 if (channel == 0)
981 {
982 MODIFY_REG(hacodec->Instance_hp->DAC_CH0_CFG, AUDCODEC_HP_DAC_CH0_CFG_ROUGH_VOL_Msk | AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Msk, \
983 MAKE_REG_VAL(rough_vol, AUDCODEC_HP_DAC_CH0_CFG_ROUGH_VOL_Msk, AUDCODEC_HP_DAC_CH0_CFG_ROUGH_VOL_Pos) |
984 MAKE_REG_VAL(fine_vol, AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Msk, AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Pos));
985 }
986 else
987 {
988 MODIFY_REG(hacodec->Instance_hp->DAC_CH1_CFG, AUDCODEC_HP_DAC_CH0_CFG_ROUGH_VOL_Msk | AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Msk, \
989 MAKE_REG_VAL(rough_vol, AUDCODEC_HP_DAC_CH0_CFG_ROUGH_VOL_Msk, AUDCODEC_HP_DAC_CH0_CFG_ROUGH_VOL_Pos) |
990 MAKE_REG_VAL(fine_vol, AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Msk, AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Pos));
991 }
992
993 HAL_DBG_printf("set volume rough:%d, fine:%d, cfg0:0x%x", rough_vol, fine_vol, hacodec->Instance_hp->DAC_CH0_CFG);
994
995 return HAL_OK;
996 }
997
998 /**
999 * @brief Configure ADC path volume.
1000 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
1001 * the configuration information for AUDCODEC module
1002 * @param channel: channel 0 or 1
1003 * @param volume: configure volume -36dB~54dB
1004 * @retval HAL status
1005 */
HAL_AUDCODEC_Config_ADCPath_Volume(AUDCODEC_HandleTypeDef * hacodec,int channel,int volume)1006 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Config_ADCPath_Volume(AUDCODEC_HandleTypeDef *hacodec, int channel, int volume)
1007 {
1008 uint32_t rough_vol, fine_vol;
1009
1010 /* Check the AUDCODEC handle allocation */
1011 if (hacodec == NULL)
1012 {
1013 return HAL_ERROR;
1014 }
1015
1016 if ((channel < 0) || (channel > 1))
1017 {
1018 return HAL_ERROR;
1019 }
1020
1021 if ((volume < -36) || (volume > 54))
1022 {
1023 return HAL_ERROR;
1024 }
1025
1026 rough_vol = (volume + 36) / 6;
1027 fine_vol = ((volume + 36) % 6) << 1;
1028
1029 if (channel == 0)
1030 {
1031 MODIFY_REG(hacodec->Instance_lp->ADC_CH0_CFG, AUDCODEC_LP_ADC_CH0_CFG_ROUGH_VOL_Msk | AUDCODEC_LP_ADC_CH0_CFG_FINE_VOL_Msk, \
1032 MAKE_REG_VAL(rough_vol, AUDCODEC_LP_ADC_CH0_CFG_ROUGH_VOL_Msk, AUDCODEC_LP_ADC_CH0_CFG_ROUGH_VOL_Pos) |
1033 MAKE_REG_VAL(fine_vol, AUDCODEC_LP_ADC_CH0_CFG_FINE_VOL_Msk, AUDCODEC_LP_ADC_CH0_CFG_FINE_VOL_Pos));
1034 }
1035 else
1036 {
1037 MODIFY_REG(hacodec->Instance_lp->ADC_CH1_CFG, AUDCODEC_LP_ADC_CH0_CFG_ROUGH_VOL_Msk | AUDCODEC_LP_ADC_CH0_CFG_FINE_VOL_Msk, \
1038 MAKE_REG_VAL(rough_vol, AUDCODEC_LP_ADC_CH0_CFG_ROUGH_VOL_Msk, AUDCODEC_LP_ADC_CH0_CFG_ROUGH_VOL_Pos) |
1039 MAKE_REG_VAL(fine_vol, AUDCODEC_LP_ADC_CH0_CFG_FINE_VOL_Msk, AUDCODEC_LP_ADC_CH0_CFG_FINE_VOL_Pos));
1040 }
1041
1042 //LOG_E("set ADC volume rough:%d, fine:%d, cfg0:0x%x", rough_vol, fine_vol, hacodec->Instance_hp->DAC_CH0_CFG);
1043
1044 return HAL_OK;
1045 }
1046
1047
1048 /**
1049 * @brief Config DAC path.
1050 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
1051 * the configuration information for AUDCODEC module
1052 * @retval HAL status
1053 */
HAL_AUDCODEC_Config_DACPath(AUDCODEC_HandleTypeDef * hacodec,uint16_t bypass)1054 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Config_DACPath(AUDCODEC_HandleTypeDef *hacodec, uint16_t bypass)
1055 {
1056
1057 /* Check the AUDCODEC handle allocation */
1058 if (hacodec == NULL)
1059 {
1060 return HAL_ERROR;
1061 }
1062
1063 if (bypass)
1064 {
1065 MODIFY_REG(hacodec->Instance_hp->DAC_CH0_CFG, AUDCODEC_HP_DAC_CH0_CFG_DOUT_MUTE_Msk, \
1066 MAKE_REG_VAL(1, AUDCODEC_HP_DAC_CH0_CFG_DOUT_MUTE_Msk, AUDCODEC_HP_DAC_CH0_CFG_DOUT_MUTE_Pos));
1067
1068 hacodec->Instance_hp->DAC_CH0_DEBUG = (1 << AUDCODEC_HP_DAC_CH0_DEBUG_BYPASS_Pos) |
1069 (0xFF << AUDCODEC_HP_DAC_CH0_DEBUG_DATA_OUT_Pos);
1070
1071 MODIFY_REG(hacodec->Instance_hp->DAC_CH1_CFG, AUDCODEC_HP_DAC_CH1_CFG_DOUT_MUTE_Msk, \
1072 MAKE_REG_VAL(1, AUDCODEC_HP_DAC_CH1_CFG_DOUT_MUTE_Msk, AUDCODEC_HP_DAC_CH1_CFG_DOUT_MUTE_Pos));
1073
1074 hacodec->Instance_hp->DAC_CH1_DEBUG = (1 << AUDCODEC_HP_DAC_CH1_DEBUG_BYPASS_Pos) |
1075 (0xFF << AUDCODEC_HP_DAC_CH1_DEBUG_DATA_OUT_Pos);
1076 }
1077 else
1078 {
1079 MODIFY_REG(hacodec->Instance_hp->DAC_CH0_CFG, AUDCODEC_HP_DAC_CH0_CFG_DOUT_MUTE_Msk, \
1080 MAKE_REG_VAL(0, AUDCODEC_HP_DAC_CH0_CFG_DOUT_MUTE_Msk, AUDCODEC_HP_DAC_CH0_CFG_DOUT_MUTE_Pos));
1081 hacodec->Instance_hp->DAC_CH0_DEBUG = (0 << AUDCODEC_HP_DAC_CH0_DEBUG_BYPASS_Pos) |
1082 (0xFF << AUDCODEC_HP_DAC_CH0_DEBUG_DATA_OUT_Pos);
1083 MODIFY_REG(hacodec->Instance_hp->DAC_CH1_CFG, AUDCODEC_HP_DAC_CH1_CFG_DOUT_MUTE_Msk, \
1084 MAKE_REG_VAL(0, AUDCODEC_HP_DAC_CH1_CFG_DOUT_MUTE_Msk, AUDCODEC_HP_DAC_CH1_CFG_DOUT_MUTE_Pos));
1085 hacodec->Instance_hp->DAC_CH1_DEBUG = (0 << AUDCODEC_HP_DAC_CH1_DEBUG_BYPASS_Pos) |
1086 (0xFF << AUDCODEC_HP_DAC_CH1_DEBUG_DATA_OUT_Pos);
1087 }
1088
1089 return HAL_OK;
1090 }
1091
1092 /**
1093 * @brief Configure DAC path mute.
1094 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
1095 * the configuration information for AUDCODEC module
1096 * @param mute: is mute or not
1097 * @retval HAL status
1098 */
HAL_AUDCODEC_Mute_DACPath(AUDCODEC_HandleTypeDef * hacodec,int mute)1099 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Mute_DACPath(AUDCODEC_HandleTypeDef *hacodec, int mute)
1100 {
1101 static int fine_vol_0, fine_vol_1;
1102
1103 /* Check the AUDCODEC handle allocation */
1104 if (hacodec == NULL)
1105 {
1106 return HAL_ERROR;
1107 }
1108
1109 if (mute)
1110 {
1111 fine_vol_0 = GET_REG_VAL(hacodec->Instance_hp->DAC_CH0_CFG, AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Msk, AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Pos);
1112 fine_vol_1 = GET_REG_VAL(hacodec->Instance_hp->DAC_CH1_CFG, AUDCODEC_HP_DAC_CH1_CFG_FINE_VOL_Msk, AUDCODEC_HP_DAC_CH1_CFG_FINE_VOL_Pos);
1113 MODIFY_REG(hacodec->Instance_hp->DAC_CH0_CFG, AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Msk, \
1114 MAKE_REG_VAL(0xF, AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Msk, AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Pos));
1115 MODIFY_REG(hacodec->Instance_hp->DAC_CH1_CFG, AUDCODEC_HP_DAC_CH1_CFG_FINE_VOL_Msk, \
1116 MAKE_REG_VAL(0xF, AUDCODEC_HP_DAC_CH1_CFG_FINE_VOL_Msk, AUDCODEC_HP_DAC_CH1_CFG_FINE_VOL_Pos));
1117 }
1118 else
1119 {
1120 MODIFY_REG(hacodec->Instance_hp->DAC_CH0_CFG, AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Msk, \
1121 MAKE_REG_VAL(fine_vol_0, AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Msk, AUDCODEC_HP_DAC_CH0_CFG_FINE_VOL_Pos));
1122 MODIFY_REG(hacodec->Instance_hp->DAC_CH1_CFG, AUDCODEC_HP_DAC_CH1_CFG_FINE_VOL_Msk, \
1123 MAKE_REG_VAL(fine_vol_1, AUDCODEC_HP_DAC_CH1_CFG_FINE_VOL_Msk, AUDCODEC_HP_DAC_CH1_CFG_FINE_VOL_Pos));
1124 }
1125
1126
1127 return HAL_OK;
1128 }
1129
1130 #if 0
1131
1132 /**
1133 * @brief Configure ADC path.
1134 * @param hacodec: pointer to a AUDCODEC_HandleTypeDef structure that contains
1135 * the configuration information for AUDCODEC module
1136 * @param cfg: configure parameters
1137 * @retval HAL status
1138 */
1139 __HAL_ROM_USED HAL_StatusTypeDef HAL_AUDCODEC_Config_ADCPath(AUDCODEC_HandleTypeDef *hacodec, AUDCODEC_ADCCfgTypeDef *cfg)
1140 {
1141 uint32_t value;
1142
1143 /* Check the AUDCODEC handle allocation */
1144 if (hacodec == NULL)
1145 {
1146 return HAL_ERROR;
1147 }
1148 value = MAKE_REG_VAL(cfg->clk_div, AUDCODEC_LP_ADC_CFG_CLK_DIV_Msk, AUDCODEC_LP_ADC_CFG_CLK_DIV_Pos)
1149 | MAKE_REG_VAL(cfg->clk_src_sel, AUDCODEC_LP_ADC_CFG_CLK_SRC_SEL_Msk, AUDCODEC_LP_ADC_CFG_CLK_SRC_SEL_Pos)
1150 | MAKE_REG_VAL(cfg->op_mode, AUDCODEC_LP_ADC_CFG_OP_MODE_Msk, AUDCODEC_LP_ADC_CFG_OP_MODE_Pos)
1151 | MAKE_REG_VAL(cfg->osr_sel, AUDCODEC_LP_ADC_CFG_OSR_SEL_Msk, AUDCODEC_LP_ADC_CFG_OSR_SEL_Pos);
1152
1153 hacodec->Instance_hp->CFG = value;
1154
1155 return HAL_OK;
1156 }
1157 #endif
HAL_AUDCODEC_DMA_Init(DMA_HandleTypeDef * hdma,uint8_t from_mem)1158 static void HAL_AUDCODEC_DMA_Init(DMA_HandleTypeDef *hdma, uint8_t from_mem)
1159 {
1160 // configure TX DMA, instance and request should be initialized by caller
1161 if (hdma != NULL)
1162 {
1163 if (from_mem)
1164 hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
1165 else
1166 hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
1167 hdma->Init.PeriphInc = DMA_PINC_DISABLE;
1168 hdma->Init.MemInc = DMA_MINC_ENABLE;
1169 hdma->Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
1170 hdma->Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
1171 /*Mode will be changed, based on destination select*/
1172 hdma->Init.Mode = DMA_CIRCULAR; //DMA_CIRCULAR; //DMA_CIRCULAR; //DMA_NORMAL;
1173 hdma->Init.Priority = DMA_PRIORITY_HIGH;
1174 hdma->Init.BurstSize = 0;
1175 //hdma->Parent = (void *)hacodec;
1176
1177 HAL_DMA_Init(hdma);
1178 }
1179
1180 }
1181
HAL_AUDCODEC_Transmit_DMA(AUDCODEC_HandleTypeDef * hacodec,uint8_t * pData,uint32_t Size,uint32_t did)1182 HAL_StatusTypeDef HAL_AUDCODEC_Transmit_DMA(AUDCODEC_HandleTypeDef *hacodec, uint8_t *pData, uint32_t Size, uint32_t did)
1183 {
1184 uint32_t txentry;
1185 uint32_t *dmamask;
1186
1187 if ((hacodec == NULL) || (hacodec->hdma[did] == NULL) || (pData == NULL) || (Size == 0U) || (did > HAL_AUDCODEC_DAC_CH1))
1188 {
1189 return HAL_ERROR;
1190 }
1191
1192 /* Process Locked */
1193 __HAL_LOCK(hacodec);
1194
1195 if (did == HAL_AUDCODEC_DAC_CH0) // channel 0
1196 {
1197 txentry = (uint32_t)(&hacodec->Instance_hp->DAC_CH0_ENTRY);
1198 dmamask = (uint32_t *)((uint32_t)&hacodec->Instance_hp->DAC_CH0_CFG);
1199 }
1200 else
1201 {
1202 txentry = (uint32_t)(&hacodec->Instance_hp->DAC_CH1_ENTRY);
1203 dmamask = (uint32_t *)((uint32_t)&hacodec->Instance_hp->DAC_CH1_CFG);
1204 }
1205
1206 if (!(hacodec->State[did] & HAL_AUDCODEC_STATE_BUSY_TX))
1207 {
1208 hacodec->buf[did] = pData;
1209 hacodec->State[did] |= HAL_AUDCODEC_STATE_BUSY_TX;
1210 hacodec->ErrorCode = HAL_AUDCODEC_ERROR_NONE;
1211
1212
1213 // DMA transmit as 32 bits
1214 hacodec->dataSize[did] = Size >> 2;
1215
1216 /* Set the AUDCODEC Tx DMA Half transfert complete callback */
1217 hacodec->hdma[did]->XferHalfCpltCallback = AUDCODEC_DMATxHalfCplt;
1218 __HAL_DMA_SET_CIRCLUAR_MODE(hacodec->hdma[did], DMA_CIRCULAR);
1219
1220 /* Set the AUDCODEC Tx DMA transfert complete callback */
1221 hacodec->hdma[did]->XferCpltCallback = AUDCODEC_DMATxCplt;
1222
1223 /* Set the DMA error callback */
1224 hacodec->hdma[did]->XferErrorCallback = AUDCODEC_DMAError;
1225
1226 /* Enable the Tx DMA Channel */
1227 HAL_DMA_Start_IT(hacodec->hdma[did], (uint32_t)hacodec->buf[did], txentry, hacodec->dataSize[did]);
1228
1229 /* Check if the AUDCODEC Tx request is already enabled */
1230 *dmamask &= ~AUDCODEC_HP_DAC_CH0_CFG_DMA_EN_Msk;
1231 *dmamask |= AUDCODEC_HP_DAC_CH0_CFG_DMA_EN;
1232 /* Check if the AUDCODEC is already enabled */
1233 //__HAL_AUDCODEC_ENABLE(hacodec);
1234
1235 /* Process Unlocked */
1236 __HAL_UNLOCK(hacodec);
1237
1238 return HAL_OK;
1239 }
1240 else
1241 {
1242 /* Process Unlocked */
1243 __HAL_UNLOCK(hacodec);
1244 return HAL_BUSY;
1245 }
1246
1247 return HAL_OK;
1248
1249 }
1250
HAL_AUDCODEC_Receive_DMA(AUDCODEC_HandleTypeDef * hacodec,uint8_t * pData,uint32_t Size,uint32_t did)1251 HAL_StatusTypeDef HAL_AUDCODEC_Receive_DMA(AUDCODEC_HandleTypeDef *hacodec, uint8_t *pData, uint32_t Size, uint32_t did)
1252 {
1253 uint32_t rxentry;
1254 uint32_t *dmamask;
1255
1256 /* check dma handle */
1257 if ((hacodec == NULL) || (hacodec->hdma[did] == NULL) || (pData == NULL) || (Size == 0U) || (did > HAL_AUDCODEC_INSTANC_CNT) || (did < HAL_AUDCODEC_ADC_CH0))
1258 {
1259 return HAL_ERROR;
1260 }
1261
1262 if (hacodec->State[did] & HAL_AUDCODEC_STATE_BUSY_RX)
1263 {
1264 return HAL_BUSY;
1265 }
1266
1267 /* Process Locked */
1268 __HAL_LOCK(hacodec);
1269
1270 if (did == HAL_AUDCODEC_ADC_CH0)
1271 {
1272 rxentry = (uint32_t)(&hacodec->Instance_lp->ADC_CH0_ENTRY);
1273 dmamask = (uint32_t *)((uint32_t)&hacodec->Instance_lp->ADC_CH0_CFG);
1274 }
1275 else
1276 {
1277 rxentry = (uint32_t)(&hacodec->Instance_lp->ADC_CH1_ENTRY);
1278 dmamask = (uint32_t *)((uint32_t)&hacodec->Instance_lp->ADC_CH1_CFG);
1279 }
1280
1281 /* Set the transaction information */
1282 hacodec->State[did] = HAL_AUDCODEC_STATE_BUSY_RX;
1283 hacodec->ErrorCode = HAL_AUDCODEC_ERROR_NONE;
1284
1285 hacodec->buf[did] = pData;
1286 hacodec->dataSize[did] = Size >> 2;
1287
1288 /* Set the AUDCODEC RxDMA Half transfer complete callback */
1289 hacodec->hdma[did]->XferHalfCpltCallback = AUDCODEC_DMAHalfRxCplt;
1290 __HAL_DMA_SET_CIRCLUAR_MODE(hacodec->hdma[did], DMA_CIRCULAR);
1291
1292 /* Set the AUDCODEC Rx DMA transfer complete callback */
1293 hacodec->hdma[did]->XferCpltCallback = AUDCODEC_DMARxCplt;
1294
1295 /* Set the AUDCODEC error callback */
1296 hacodec->hdma[did]->XferErrorCallback = AUDCODEC_DMAError;
1297
1298 /* Set the AUDCODEC AbortCpltCallback */
1299 hacodec->hdma[did]->XferAbortCallback = NULL;
1300
1301
1302 /* Enable the Rx DMA Stream/Channel */
1303 HAL_DMA_Start_IT(hacodec->hdma[did], (uint32_t)(rxentry), (uint32_t)hacodec->buf[did], hacodec->dataSize[did]);
1304
1305 /* Check if the AUDCODEC Rx request is already enabled */
1306 *dmamask &= ~AUDCODEC_LP_ADC_CH0_CFG_DMA_EN_Msk;
1307 *dmamask |= AUDCODEC_LP_ADC_CH0_CFG_DMA_EN;
1308 /* Check if the AUDCODEC is already enabled */
1309 //__HAL_AUDCODEC_ENABLE(hacodec);
1310
1311 /* Process Unlocked */
1312 __HAL_UNLOCK(hacodec);
1313
1314 return HAL_OK;
1315 }
1316
1317
HAL_AUDCODEC_DMAStop(AUDCODEC_HandleTypeDef * hacodec,uint32_t did)1318 HAL_StatusTypeDef HAL_AUDCODEC_DMAStop(AUDCODEC_HandleTypeDef *hacodec, uint32_t did)
1319 {
1320 /* Abort the DMA rx/tx Stream/Channel */
1321 if (hacodec->hdma[did] != NULL)
1322 {
1323 //__HAL_DMA_DISABLE(hacodec->hdma[did]);
1324 HAL_DMA_Abort(hacodec->hdma[did]);
1325 }
1326
1327 switch (did)
1328 {
1329 case HAL_AUDCODEC_DAC_CH0:
1330 hacodec->Instance_hp->DAC_CH0_CFG &= (~AUDCODEC_HP_DAC_CH0_CFG_DMA_EN);
1331 break;
1332 case HAL_AUDCODEC_DAC_CH1:
1333 hacodec->Instance_hp->DAC_CH1_CFG &= (~AUDCODEC_HP_DAC_CH1_CFG_DMA_EN);
1334 break;
1335 case HAL_AUDCODEC_ADC_CH0:
1336 hacodec->Instance_lp->ADC_CH0_CFG &= (~AUDCODEC_LP_ADC_CH0_CFG_DMA_EN);
1337 break;
1338 case HAL_AUDCODEC_ADC_CH1:
1339 hacodec->Instance_lp->ADC_CH1_CFG &= (~AUDCODEC_LP_ADC_CH1_CFG_DMA_EN);
1340 break;
1341 }
1342 //__HAL_AUDCODEC_DISABLE(hacodec);
1343
1344 //hacodec->State = HAL_AUDCODEC_STATE_READY;
1345
1346 return HAL_OK;
1347 }
1348
HAL_AUDCODEC_TxCpltCallback(AUDCODEC_HandleTypeDef * hacodec,int cid)1349 __weak void HAL_AUDCODEC_TxCpltCallback(AUDCODEC_HandleTypeDef *hacodec, int cid)
1350 {
1351 /* Prevent unused argument(s) compilation warning */
1352 UNUSED(hacodec);
1353 UNUSED(cid);
1354
1355 /* NOTE : This function should not be modified, when the callback is needed,
1356 the HAL_AUDCODEC_TxHalfCpltCallback should be implemented in the user file
1357 */
1358
1359 }
1360
HAL_AUDCODEC_TxHalfCpltCallback(AUDCODEC_HandleTypeDef * hacodec,int cid)1361 __weak void HAL_AUDCODEC_TxHalfCpltCallback(AUDCODEC_HandleTypeDef *hacodec, int cid)
1362 {
1363 /* Prevent unused argument(s) compilation warning */
1364 UNUSED(hacodec);
1365 UNUSED(cid);
1366
1367 /* NOTE : This function should not be modified, when the callback is needed,
1368 the HAL_AUDCODEC_TxHalfCpltCallback should be implemented in the user file
1369 */
1370
1371 }
1372
HAL_AUDCODEC_RxHalfCpltCallback(AUDCODEC_HandleTypeDef * hacodec,int cid)1373 __weak void HAL_AUDCODEC_RxHalfCpltCallback(AUDCODEC_HandleTypeDef *hacodec, int cid)
1374 {
1375 /* Prevent unused argument(s) compilation warning */
1376 UNUSED(hacodec);
1377 UNUSED(cid);
1378
1379 /* NOTE : This function should not be modified, when the callback is needed,
1380 the HAL_AUDCODEC_RxHalfCpltCallback should be implemented in the user file
1381 */
1382 }
1383
HAL_AUDCODEC_RxCpltCallback(AUDCODEC_HandleTypeDef * hacodec,int cid)1384 __weak void HAL_AUDCODEC_RxCpltCallback(AUDCODEC_HandleTypeDef *hacodec, int cid)
1385 {
1386 /* Prevent unused argument(s) compilation warning */
1387 UNUSED(hacodec);
1388 UNUSED(cid);
1389
1390 /* NOTE : This function should not be modified, when the callback is needed,
1391 the HAL_AUDCODEC_RxCpltCallback should be implemented in the user file
1392 */
1393 }
1394
HAL_AUDCODEC_ErrorCallback(AUDCODEC_HandleTypeDef * hacodec,int cid)1395 __weak void HAL_AUDCODEC_ErrorCallback(AUDCODEC_HandleTypeDef *hacodec, int cid)
1396 {
1397 /* Prevent unused argument(s) compilation warning */
1398 UNUSED(hacodec);
1399 UNUSED(cid);
1400
1401 /* NOTE : This function should not be modified, when the callback is needed,
1402 the HAL_PDM_ErrorCallback should be implemented in the user file
1403 */
1404 }
1405
HAL_AUDCODEC_AbortCpltCallback(AUDCODEC_HandleTypeDef * hacodec,int cid)1406 __weak void HAL_AUDCODEC_AbortCpltCallback(AUDCODEC_HandleTypeDef *hacodec, int cid)
1407 {
1408 /* Prevent unused argument(s) compilation warning */
1409 UNUSED(hacodec);
1410 UNUSED(cid);
1411
1412 /* NOTE : This function should not be modified, when the callback is needed,
1413 the HAL_PDM_AbortCpltCallback should be implemented in the user file
1414 */
1415 }
1416
1417
AUDCODEC_DMATxCplt(DMA_HandleTypeDef * hdma)1418 static void AUDCODEC_DMATxCplt(DMA_HandleTypeDef *hdma)
1419 {
1420 AUDCODEC_HandleTypeDef *aprc = (AUDCODEC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1421
1422 int i;
1423 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
1424 if (aprc->hdma[i] == hdma)
1425 break;
1426 if (i >= HAL_AUDCODEC_INSTANC_CNT) // something wrong
1427 return;
1428
1429 HAL_AUDCODEC_TxCpltCallback(aprc, i);
1430 }
1431
1432 /**
1433 * @brief DMA I2S transmit process half complete callback
1434 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
1435 * the configuration information for the specified DMA module.
1436 * @retval None
1437 */
AUDCODEC_DMATxHalfCplt(DMA_HandleTypeDef * hdma)1438 static void AUDCODEC_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
1439 {
1440 AUDCODEC_HandleTypeDef *aprc = (AUDCODEC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1441 int i;
1442 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
1443 if (aprc->hdma[i] == hdma)
1444 break;
1445 if (i >= HAL_AUDCODEC_INSTANC_CNT) // something wrong
1446 return;
1447
1448 HAL_AUDCODEC_TxHalfCpltCallback(aprc, i);
1449 }
1450
AUDCODEC_DMARxCplt(DMA_HandleTypeDef * hdma)1451 static void AUDCODEC_DMARxCplt(DMA_HandleTypeDef *hdma)
1452 {
1453 AUDCODEC_HandleTypeDef *aprc = (AUDCODEC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1454 int i;
1455 for (i = HAL_AUDCODEC_DAC_CH0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
1456 if (aprc->hdma[i] == hdma)
1457 break;
1458 if (i >= HAL_AUDCODEC_INSTANC_CNT)
1459 return;
1460
1461 HAL_AUDCODEC_RxCpltCallback(aprc, i);
1462
1463 }
1464
1465 /**
1466 * @brief DMA PDM half receive process complete callback
1467 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1468 * the configuration information for the specified DMA module.
1469 * @retval None
1470 */
AUDCODEC_DMAHalfRxCplt(DMA_HandleTypeDef * hdma)1471 static void AUDCODEC_DMAHalfRxCplt(DMA_HandleTypeDef *hdma)
1472 {
1473 AUDCODEC_HandleTypeDef *aprc = (AUDCODEC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1474 int i;
1475 for (i = HAL_AUDCODEC_DAC_CH0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
1476 if (aprc->hdma[i] == hdma)
1477 break;
1478 if (i >= HAL_AUDCODEC_INSTANC_CNT)
1479 return;
1480 HAL_AUDCODEC_RxHalfCpltCallback(aprc, i);
1481 }
1482
1483
1484 /**
1485 * @brief DMA PDM communication error callback.
1486 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1487 * the configuration information for the specified DMA module.
1488 * @retval None
1489 */
AUDCODEC_DMAError(DMA_HandleTypeDef * hdma)1490 static void AUDCODEC_DMAError(DMA_HandleTypeDef *hdma)
1491 {
1492 AUDCODEC_HandleTypeDef *aprc = (AUDCODEC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1493 int i;
1494 for (i = 0; i < HAL_AUDCODEC_INSTANC_CNT; i++)
1495 if (aprc->hdma[i] == hdma)
1496 break;
1497 if (i >= HAL_AUDCODEC_INSTANC_CNT)
1498 return;
1499
1500 aprc->State[i] = HAL_AUDCODEC_STATE_READY;
1501 HAL_AUDCODEC_ErrorCallback(aprc, i);
1502 }
1503
1504 #endif /* HAL_AUDCODEC_MODULE_ENABLED */
